[deliverable/linux.git] / drivers / spi / spi-orion.c

/*
 * Marvell Orion SPI controller driver
 *
 * Author: Shadi Ammouri <shadi@marvell.com>
 * Copyright (C) 2007-2008 Marvell Ltd.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */

#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/delay.h>
#include <linux/platform_device.h>
#include <linux/err.h>
#include <linux/io.h>
#include <linux/spi/spi.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/clk.h>
#include <linux/sizes.h>
#include <asm/unaligned.h>

#define DRIVER_NAME			"orion_spi"

#define ORION_NUM_CHIPSELECTS		1 /* only one slave is supported*/
#define ORION_SPI_WAIT_RDY_MAX_LOOP	2000 /* in usec */

#define ORION_SPI_IF_CTRL_REG		0x00
#define ORION_SPI_IF_CONFIG_REG		0x04
#define ORION_SPI_DATA_OUT_REG		0x08
#define ORION_SPI_DATA_IN_REG		0x0c
#define ORION_SPI_INT_CAUSE_REG		0x10

#define ORION_SPI_MODE_CPOL		(1 << 11)
#define ORION_SPI_MODE_CPHA		(1 << 12)
#define ORION_SPI_IF_8_16_BIT_MODE	(1 << 5)
#define ORION_SPI_CLK_PRESCALE_MASK	0x1F
#define ORION_SPI_MODE_MASK		(ORION_SPI_MODE_CPOL | \
					 ORION_SPI_MODE_CPHA)

struct orion_spi {
	struct spi_master	*master;
	void __iomem		*base;
	struct clk              *clk;
};

static inline void __iomem *spi_reg(struct orion_spi *orion_spi, u32 reg)
{
	return orion_spi->base + reg;
}

static inline void
orion_spi_setbits(struct orion_spi *orion_spi, u32 reg, u32 mask)
{
	void __iomem *reg_addr = spi_reg(orion_spi, reg);
	u32 val;

	val = readl(reg_addr);
	val |= mask;
	writel(val, reg_addr);
}

static inline void
orion_spi_clrbits(struct orion_spi *orion_spi, u32 reg, u32 mask)
{
	void __iomem *reg_addr = spi_reg(orion_spi, reg);
	u32 val;

	val = readl(reg_addr);
	val &= ~mask;
	writel(val, reg_addr);
}

static int orion_spi_set_transfer_size(struct orion_spi *orion_spi, int size)
{
	if (size == 16) {
		orion_spi_setbits(orion_spi, ORION_SPI_IF_CONFIG_REG,
				  ORION_SPI_IF_8_16_BIT_MODE);
	} else if (size == 8) {
		orion_spi_clrbits(orion_spi, ORION_SPI_IF_CONFIG_REG,
				  ORION_SPI_IF_8_16_BIT_MODE);
	} else {
		pr_debug("Bad bits per word value %d (only 8 or 16 are allowed).\n",
			size);
		return -EINVAL;
	}

	return 0;
}

static int orion_spi_baudrate_set(struct spi_device *spi, unsigned int speed)
{
	u32 tclk_hz;
	u32 rate;
	u32 prescale;
	u32 reg;
	struct orion_spi *orion_spi;

	orion_spi = spi_master_get_devdata(spi->master);

	tclk_hz = clk_get_rate(orion_spi->clk);

	/*
	 * the supported rates are: 4,6,8...30
	 * round up as we look for equal or less speed
	 */
	rate = DIV_ROUND_UP(tclk_hz, speed);
	rate = roundup(rate, 2);

	/* check if requested speed is too small */
	if (rate > 30)
		return -EINVAL;

	if (rate < 4)
		rate = 4;

	/* Convert the rate to SPI clock divisor value.	*/
	prescale = 0x10 + rate/2;

	reg = readl(spi_reg(orion_spi, ORION_SPI_IF_CONFIG_REG));
	reg = ((reg & ~ORION_SPI_CLK_PRESCALE_MASK) | prescale);
	writel(reg, spi_reg(orion_spi, ORION_SPI_IF_CONFIG_REG));

	return 0;
}

static void
orion_spi_mode_set(struct spi_device *spi)
{
	u32 reg;
	struct orion_spi *orion_spi;

	orion_spi = spi_master_get_devdata(spi->master);

	reg = readl(spi_reg(orion_spi, ORION_SPI_IF_CONFIG_REG));
	reg &= ~ORION_SPI_MODE_MASK;
	if (spi->mode & SPI_CPOL)
		reg |= ORION_SPI_MODE_CPOL;
	if (spi->mode & SPI_CPHA)
		reg |= ORION_SPI_MODE_CPHA;
	writel(reg, spi_reg(orion_spi, ORION_SPI_IF_CONFIG_REG));
}

/*
 * called only when no transfer is active on the bus
 */
static int
orion_spi_setup_transfer(struct spi_device *spi, struct spi_transfer *t)
{
	struct orion_spi *orion_spi;
	unsigned int speed = spi->max_speed_hz;
	unsigned int bits_per_word = spi->bits_per_word;
	int	rc;

	orion_spi = spi_master_get_devdata(spi->master);

	if ((t != NULL) && t->speed_hz)
		speed = t->speed_hz;

	if ((t != NULL) && t->bits_per_word)
		bits_per_word = t->bits_per_word;

	orion_spi_mode_set(spi);

	rc = orion_spi_baudrate_set(spi, speed);
	if (rc)
		return rc;

	return orion_spi_set_transfer_size(orion_spi, bits_per_word);
}

static void orion_spi_set_cs(struct orion_spi *orion_spi, int enable)
{
	if (enable)
		orion_spi_setbits(orion_spi, ORION_SPI_IF_CTRL_REG, 0x1);
	else
		orion_spi_clrbits(orion_spi, ORION_SPI_IF_CTRL_REG, 0x1);
}

static inline int orion_spi_wait_till_ready(struct orion_spi *orion_spi)
{
	int i;

	for (i = 0; i < ORION_SPI_WAIT_RDY_MAX_LOOP; i++) {
		if (readl(spi_reg(orion_spi, ORION_SPI_INT_CAUSE_REG)))
			return 1;
		else
			udelay(1);
	}

	return -1;
}

static inline int
orion_spi_write_read_8bit(struct spi_device *spi,
			  const u8 **tx_buf, u8 **rx_buf)
{
	void __iomem *tx_reg, *rx_reg, *int_reg;
	struct orion_spi *orion_spi;

	orion_spi = spi_master_get_devdata(spi->master);
	tx_reg = spi_reg(orion_spi, ORION_SPI_DATA_OUT_REG);
	rx_reg = spi_reg(orion_spi, ORION_SPI_DATA_IN_REG);
	int_reg = spi_reg(orion_spi, ORION_SPI_INT_CAUSE_REG);

	/* clear the interrupt cause register */
	writel(0x0, int_reg);

	if (tx_buf && *tx_buf)
		writel(*(*tx_buf)++, tx_reg);
	else
		writel(0, tx_reg);

	if (orion_spi_wait_till_ready(orion_spi) < 0) {
		dev_err(&spi->dev, "TXS timed out\n");
		return -1;
	}

	if (rx_buf && *rx_buf)
		*(*rx_buf)++ = readl(rx_reg);

	return 1;
}

static inline int
orion_spi_write_read_16bit(struct spi_device *spi,
			   const u16 **tx_buf, u16 **rx_buf)
{
	void __iomem *tx_reg, *rx_reg, *int_reg;
	struct orion_spi *orion_spi;

	orion_spi = spi_master_get_devdata(spi->master);
	tx_reg = spi_reg(orion_spi, ORION_SPI_DATA_OUT_REG);
	rx_reg = spi_reg(orion_spi, ORION_SPI_DATA_IN_REG);
	int_reg = spi_reg(orion_spi, ORION_SPI_INT_CAUSE_REG);

	/* clear the interrupt cause register */
	writel(0x0, int_reg);

	if (tx_buf && *tx_buf)
		writel(__cpu_to_le16(get_unaligned((*tx_buf)++)), tx_reg);
	else
		writel(0, tx_reg);

	if (orion_spi_wait_till_ready(orion_spi) < 0) {
		dev_err(&spi->dev, "TXS timed out\n");
		return -1;
	}

	if (rx_buf && *rx_buf)
		put_unaligned(__le16_to_cpu(readl(rx_reg)), (*rx_buf)++);

	return 1;
}

static unsigned int
orion_spi_write_read(struct spi_device *spi, struct spi_transfer *xfer)
{
	unsigned int count;
	int word_len;

	word_len = spi->bits_per_word;
	count = xfer->len;

	if (word_len == 8) {
		const u8 *tx = xfer->tx_buf;
		u8 *rx = xfer->rx_buf;

		do {
			if (orion_spi_write_read_8bit(spi, &tx, &rx) < 0)
				goto out;
			count--;
		} while (count);
	} else if (word_len == 16) {
		const u16 *tx = xfer->tx_buf;
		u16 *rx = xfer->rx_buf;

		do {
			if (orion_spi_write_read_16bit(spi, &tx, &rx) < 0)
				goto out;
			count -= 2;
		} while (count);
	}

out:
	return xfer->len - count;
}


static int orion_spi_transfer_one_message(struct spi_master *master,
					   struct spi_message *m)
{
	struct orion_spi *orion_spi = spi_master_get_devdata(master);
	struct spi_device *spi = m->spi;
	struct spi_transfer *t = NULL;
	int par_override = 0;
	int status = 0;
	int cs_active = 0;

	/* Load defaults */
	status = orion_spi_setup_transfer(spi, NULL);

	if (status < 0)
		goto msg_done;

	list_for_each_entry(t, &m->transfers, transfer_list) {
		/* make sure buffer length is even when working in 16
		 * bit mode*/
		if ((t->bits_per_word == 16) && (t->len & 1)) {
			dev_err(&spi->dev,
				"message rejected : "
				"odd data length %d while in 16 bit mode\n",
				t->len);
			status = -EIO;
			goto msg_done;
		}

		if (par_override || t->speed_hz || t->bits_per_word) {
			par_override = 1;
			status = orion_spi_setup_transfer(spi, t);
			if (status < 0)
				break;
			if (!t->speed_hz && !t->bits_per_word)
				par_override = 0;
		}

		if (!cs_active) {
			orion_spi_set_cs(orion_spi, 1);
			cs_active = 1;
		}

		if (t->len)
			m->actual_length += orion_spi_write_read(spi, t);

		if (t->delay_usecs)
			udelay(t->delay_usecs);

		if (t->cs_change) {
			orion_spi_set_cs(orion_spi, 0);
			cs_active = 0;
		}
	}

msg_done:
	if (cs_active)
		orion_spi_set_cs(orion_spi, 0);

	m->status = status;
	spi_finalize_current_message(master);

	return 0;
}

static int orion_spi_reset(struct orion_spi *orion_spi)
{
	/* Verify that the CS is deasserted */
	orion_spi_set_cs(orion_spi, 0);

	return 0;
}

static int orion_spi_probe(struct platform_device *pdev)
{
	struct spi_master *master;
	struct orion_spi *spi;
	struct resource *r;
	unsigned long tclk_hz;
	int status = 0;
	const u32 *iprop;
	int size;

	master = spi_alloc_master(&pdev->dev, sizeof(*spi));
	if (master == NULL) {
		dev_dbg(&pdev->dev, "master allocation failed\n");
		return -ENOMEM;
	}

	if (pdev->id != -1)
		master->bus_num = pdev->id;
	if (pdev->dev.of_node) {
		iprop = of_get_property(pdev->dev.of_node, "cell-index",
					&size);
		if (iprop && size == sizeof(*iprop))
			master->bus_num = *iprop;
	}

	/* we support only mode 0, and no options */
	master->mode_bits = SPI_CPHA | SPI_CPOL;

	master->transfer_one_message = orion_spi_transfer_one_message;
	master->num_chipselect = ORION_NUM_CHIPSELECTS;

	platform_set_drvdata(pdev, master);

	spi = spi_master_get_devdata(master);
	spi->master = master;

	spi->clk = devm_clk_get(&pdev->dev, NULL);
	if (IS_ERR(spi->clk)) {
		status = PTR_ERR(spi->clk);
		goto out;
	}

	clk_prepare(spi->clk);
	clk_enable(spi->clk);
	tclk_hz = clk_get_rate(spi->clk);
	master->max_speed_hz = DIV_ROUND_UP(tclk_hz, 4);
	master->min_speed_hz = DIV_ROUND_UP(tclk_hz, 30);

	r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	spi->base = devm_ioremap_resource(&pdev->dev, r);
	if (IS_ERR(spi->base)) {
		status = PTR_ERR(spi->base);
		goto out_rel_clk;
	}

	if (orion_spi_reset(spi) < 0)
		goto out_rel_clk;

	master->dev.of_node = pdev->dev.of_node;
	status = devm_spi_register_master(&pdev->dev, master);
	if (status < 0)
		goto out_rel_clk;

	return status;

out_rel_clk:
	clk_disable_unprepare(spi->clk);
out:
	spi_master_put(master);
	return status;
}


static int orion_spi_remove(struct platform_device *pdev)
{
	struct spi_master *master;
	struct orion_spi *spi;

	master = platform_get_drvdata(pdev);
	spi = spi_master_get_devdata(master);

	clk_disable_unprepare(spi->clk);

	return 0;
}

MODULE_ALIAS("platform:" DRIVER_NAME);

static const struct of_device_id orion_spi_of_match_table[] = {
	{ .compatible = "marvell,orion-spi", },
	{}
};
MODULE_DEVICE_TABLE(of, orion_spi_of_match_table);

static struct platform_driver orion_spi_driver = {
	.driver = {
		.name	= DRIVER_NAME,
		.owner	= THIS_MODULE,
		.of_match_table = of_match_ptr(orion_spi_of_match_table),
	},
	.probe		= orion_spi_probe,
	.remove		= orion_spi_remove,
};

module_platform_driver(orion_spi_driver);

MODULE_DESCRIPTION("Orion SPI driver");
MODULE_AUTHOR("Shadi Ammouri <shadi@marvell.com>");
MODULE_LICENSE("GPL");
Commit	Line	Data
60cadec9	1	/*
ca632f55	2	* Marvell Orion SPI controller driver
60cadec9 SA	3	*
	4	* Author: Shadi Ammouri <shadi@marvell.com>
	5	* Copyright (C) 2007-2008 Marvell Ltd.
	6	*
	7	* This program is free software; you can redistribute it and/or modify
	8	* it under the terms of the GNU General Public License version 2 as
	9	* published by the Free Software Foundation.
	10	*/
	11
	12	#include <linux/init.h>
	13	#include <linux/interrupt.h>
	14	#include <linux/delay.h>
	15	#include <linux/platform_device.h>
	16	#include <linux/err.h>
	17	#include <linux/io.h>
	18	#include <linux/spi/spi.h>
d7614de4	19	#include <linux/module.h>
f814f9ac	20	#include <linux/of.h>
4574b886	21	#include <linux/clk.h>
895248f8	22	#include <linux/sizes.h>
60cadec9 SA	23	#include <asm/unaligned.h>
	24
	25	#define DRIVER_NAME "orion_spi"
	26
	27	#define ORION_NUM_CHIPSELECTS 1 /* only one slave is supported*/
	28	#define ORION_SPI_WAIT_RDY_MAX_LOOP 2000 /* in usec */
	29
	30	#define ORION_SPI_IF_CTRL_REG 0x00
	31	#define ORION_SPI_IF_CONFIG_REG 0x04
	32	#define ORION_SPI_DATA_OUT_REG 0x08
	33	#define ORION_SPI_DATA_IN_REG 0x0c
	34	#define ORION_SPI_INT_CAUSE_REG 0x10
	35
b15d5d70 JG	36	#define ORION_SPI_MODE_CPOL (1 << 11)
b15d5d70 JG	37	#define ORION_SPI_MODE_CPHA (1 << 12)
60cadec9 SA	38	#define ORION_SPI_IF_8_16_BIT_MODE (1 << 5)
60cadec9 SA	39	#define ORION_SPI_CLK_PRESCALE_MASK 0x1F
b15d5d70 JG	40	#define ORION_SPI_MODE_MASK (ORION_SPI_MODE_CPOL \| \
b15d5d70 JG	41	ORION_SPI_MODE_CPHA)
60cadec9 SA	42
60cadec9 SA	43	struct orion_spi {
60cadec9 SA	44	struct spi_master *master;
60cadec9 SA	45	void __iomem *base;
4574b886	46	struct clk *clk;
60cadec9 SA	47	};
60cadec9 SA	48
60cadec9 SA	49	static inline void __iomem spi_reg(struct orion_spi orion_spi, u32 reg)
	50	{
	51	return orion_spi->base + reg;
	52	}
	53
	54	static inline void
	55	orion_spi_setbits(struct orion_spi *orion_spi, u32 reg, u32 mask)
	56	{
	57	void __iomem *reg_addr = spi_reg(orion_spi, reg);
	58	u32 val;
	59
	60	val = readl(reg_addr);
	61	val \|= mask;
	62	writel(val, reg_addr);
	63	}
	64
	65	static inline void
	66	orion_spi_clrbits(struct orion_spi *orion_spi, u32 reg, u32 mask)
	67	{
	68	void __iomem *reg_addr = spi_reg(orion_spi, reg);
	69	u32 val;
	70
	71	val = readl(reg_addr);
	72	val &= ~mask;
	73	writel(val, reg_addr);
	74	}
	75
	76	static int orion_spi_set_transfer_size(struct orion_spi *orion_spi, int size)
	77	{
	78	if (size == 16) {
	79	orion_spi_setbits(orion_spi, ORION_SPI_IF_CONFIG_REG,
	80	ORION_SPI_IF_8_16_BIT_MODE);
	81	} else if (size == 8) {
	82	orion_spi_clrbits(orion_spi, ORION_SPI_IF_CONFIG_REG,
	83	ORION_SPI_IF_8_16_BIT_MODE);
	84	} else {
3fed8068 JH	85	pr_debug("Bad bits per word value %d (only 8 or 16 are allowed).\n",
3fed8068 JH	86	size);
60cadec9 SA	87	return -EINVAL;
	88	}
	89
	90	return 0;
	91	}
	92
	93	static int orion_spi_baudrate_set(struct spi_device *spi, unsigned int speed)
	94	{
	95	u32 tclk_hz;
	96	u32 rate;
	97	u32 prescale;
	98	u32 reg;
	99	struct orion_spi *orion_spi;
	100
	101	orion_spi = spi_master_get_devdata(spi->master);
	102
4574b886	103	tclk_hz = clk_get_rate(orion_spi->clk);
60cadec9 SA	104
	105	/*
	106	* the supported rates are: 4,6,8...30
	107	* round up as we look for equal or less speed
	108	*/
	109	rate = DIV_ROUND_UP(tclk_hz, speed);
	110	rate = roundup(rate, 2);
	111
	112	/* check if requested speed is too small */
	113	if (rate > 30)
	114	return -EINVAL;
	115
	116	if (rate < 4)
	117	rate = 4;
	118
	119	/* Convert the rate to SPI clock divisor value. */
	120	prescale = 0x10 + rate/2;
	121
	122	reg = readl(spi_reg(orion_spi, ORION_SPI_IF_CONFIG_REG));
	123	reg = ((reg & ~ORION_SPI_CLK_PRESCALE_MASK) \| prescale);
	124	writel(reg, spi_reg(orion_spi, ORION_SPI_IF_CONFIG_REG));
	125
	126	return 0;
	127	}
	128
b15d5d70 JG	129	static void
	130	orion_spi_mode_set(struct spi_device *spi)
	131	{
	132	u32 reg;
	133	struct orion_spi *orion_spi;
	134
	135	orion_spi = spi_master_get_devdata(spi->master);
	136
	137	reg = readl(spi_reg(orion_spi, ORION_SPI_IF_CONFIG_REG));
	138	reg &= ~ORION_SPI_MODE_MASK;
	139	if (spi->mode & SPI_CPOL)
	140	reg \|= ORION_SPI_MODE_CPOL;
	141	if (spi->mode & SPI_CPHA)
	142	reg \|= ORION_SPI_MODE_CPHA;
	143	writel(reg, spi_reg(orion_spi, ORION_SPI_IF_CONFIG_REG));
	144	}
	145
60cadec9 SA	146	/*
	147	* called only when no transfer is active on the bus
	148	*/
	149	static int
	150	orion_spi_setup_transfer(struct spi_device spi, struct spi_transfer t)
	151	{
	152	struct orion_spi *orion_spi;
	153	unsigned int speed = spi->max_speed_hz;
	154	unsigned int bits_per_word = spi->bits_per_word;
	155	int rc;
	156
	157	orion_spi = spi_master_get_devdata(spi->master);
	158
	159	if ((t != NULL) && t->speed_hz)
	160	speed = t->speed_hz;
	161
	162	if ((t != NULL) && t->bits_per_word)
	163	bits_per_word = t->bits_per_word;
	164
b15d5d70 JG	165	orion_spi_mode_set(spi);
b15d5d70 JG	166
60cadec9 SA	167	rc = orion_spi_baudrate_set(spi, speed);
	168	if (rc)
	169	return rc;
	170
	171	return orion_spi_set_transfer_size(orion_spi, bits_per_word);
	172	}
	173
	174	static void orion_spi_set_cs(struct orion_spi *orion_spi, int enable)
	175	{
	176	if (enable)
	177	orion_spi_setbits(orion_spi, ORION_SPI_IF_CTRL_REG, 0x1);
	178	else
	179	orion_spi_clrbits(orion_spi, ORION_SPI_IF_CTRL_REG, 0x1);
	180	}
	181
	182	static inline int orion_spi_wait_till_ready(struct orion_spi *orion_spi)
	183	{
	184	int i;
	185
	186	for (i = 0; i < ORION_SPI_WAIT_RDY_MAX_LOOP; i++) {
	187	if (readl(spi_reg(orion_spi, ORION_SPI_INT_CAUSE_REG)))
	188	return 1;
	189	else
	190	udelay(1);
	191	}
	192
	193	return -1;
	194	}
	195
	196	static inline int
	197	orion_spi_write_read_8bit(struct spi_device *spi,
	198	const u8 tx_buf, u8 rx_buf)
	199	{
	200	void __iomem tx_reg, rx_reg, *int_reg;
	201	struct orion_spi *orion_spi;
	202
	203	orion_spi = spi_master_get_devdata(spi->master);
	204	tx_reg = spi_reg(orion_spi, ORION_SPI_DATA_OUT_REG);
	205	rx_reg = spi_reg(orion_spi, ORION_SPI_DATA_IN_REG);
	206	int_reg = spi_reg(orion_spi, ORION_SPI_INT_CAUSE_REG);
	207
	208	/* clear the interrupt cause register */
	209	writel(0x0, int_reg);
	210
	211	if (tx_buf && *tx_buf)
	212	writel((tx_buf)++, tx_reg);
	213	else
	214	writel(0, tx_reg);
	215
	216	if (orion_spi_wait_till_ready(orion_spi) < 0) {
	217	dev_err(&spi->dev, "TXS timed out\n");
	218	return -1;
	219	}
	220
	221	if (rx_buf && *rx_buf)
	222	(rx_buf)++ = readl(rx_reg);
	223
	224	return 1;
	225	}
	226
	227	static inline int
	228	orion_spi_write_read_16bit(struct spi_device *spi,
	229	const u16 tx_buf, u16 rx_buf)
	230	{
231	void __iomem tx_reg, rx_reg, *int_reg;
232	struct orion_spi *orion_spi;
233
234	orion_spi = spi_master_get_devdata(spi->master);
235	tx_reg = spi_reg(orion_spi, ORION_SPI_DATA_OUT_REG);
236	rx_reg = spi_reg(orion_spi, ORION_SPI_DATA_IN_REG);
237	int_reg = spi_reg(orion_spi, ORION_SPI_INT_CAUSE_REG);
238
239	/* clear the interrupt cause register */
240	writel(0x0, int_reg);
241
242	if (tx_buf && *tx_buf)
243	writel(__cpu_to_le16(get_unaligned((*tx_buf)++)), tx_reg);
244	else
245	writel(0, tx_reg);
246
247	if (orion_spi_wait_till_ready(orion_spi) < 0) {
248	dev_err(&spi->dev, "TXS timed out\n");
249	return -1;
250	}
251
252	if (rx_buf && *rx_buf)
253	put_unaligned(__le16_to_cpu(readl(rx_reg)), (*rx_buf)++);
254
255	return 1;
256	}
257
258	static unsigned int
259	orion_spi_write_read(struct spi_device spi, struct spi_transfer xfer)
260	{
60cadec9 SA	261	unsigned int count;
	262	int word_len;
	263
60cadec9 SA	264	word_len = spi->bits_per_word;
	265	count = xfer->len;
	266
	267	if (word_len == 8) {
	268	const u8 *tx = xfer->tx_buf;
	269	u8 *rx = xfer->rx_buf;
	270
	271	do {
	272	if (orion_spi_write_read_8bit(spi, &tx, &rx) < 0)
	273	goto out;
	274	count--;
	275	} while (count);
	276	} else if (word_len == 16) {
	277	const u16 *tx = xfer->tx_buf;
	278	u16 *rx = xfer->rx_buf;
	279
	280	do {
	281	if (orion_spi_write_read_16bit(spi, &tx, &rx) < 0)
	282	goto out;
	283	count -= 2;
	284	} while (count);
	285	}
	286
	287	out:
	288	return xfer->len - count;
	289	}
	290
	291
ba59a807 AL	292	static int orion_spi_transfer_one_message(struct spi_master *master,
ba59a807 AL	293	struct spi_message *m)
60cadec9	294	{
ba59a807 AL	295	struct orion_spi *orion_spi = spi_master_get_devdata(master);
	296	struct spi_device *spi = m->spi;
	297	struct spi_transfer *t = NULL;
	298	int par_override = 0;
	299	int status = 0;
	300	int cs_active = 0;
60cadec9	301
ba59a807 AL	302	/* Load defaults */
ba59a807 AL	303	status = orion_spi_setup_transfer(spi, NULL);
60cadec9	304
ba59a807 AL	305	if (status < 0)
ba59a807 AL	306	goto msg_done;
60cadec9	307
ba59a807 AL	308	list_for_each_entry(t, &m->transfers, transfer_list) {
	309	/* make sure buffer length is even when working in 16
	310	* bit mode*/
	311	if ((t->bits_per_word == 16) && (t->len & 1)) {
	312	dev_err(&spi->dev,
	313	"message rejected : "
	314	"odd data length %d while in 16 bit mode\n",
	315	t->len);
	316	status = -EIO;
	317	goto msg_done;
	318	}
60cadec9	319
ba59a807 AL	320	if (par_override \|\| t->speed_hz \|\| t->bits_per_word) {
	321	par_override = 1;
	322	status = orion_spi_setup_transfer(spi, t);
	323	if (status < 0)
	324	break;
	325	if (!t->speed_hz && !t->bits_per_word)
	326	par_override = 0;
60cadec9 SA	327	}
60cadec9 SA	328
ba59a807 AL	329	if (!cs_active) {
	330	orion_spi_set_cs(orion_spi, 1);
	331	cs_active = 1;
	332	}
60cadec9	333
ba59a807 AL	334	if (t->len)
ba59a807 AL	335	m->actual_length += orion_spi_write_read(spi, t);
60cadec9	336
ba59a807 AL	337	if (t->delay_usecs)
	338	udelay(t->delay_usecs);
	339
	340	if (t->cs_change) {
	341	orion_spi_set_cs(orion_spi, 0);
	342	cs_active = 0;
	343	}
60cadec9 SA	344	}
60cadec9 SA	345
ba59a807 AL	346	msg_done:
	347	if (cs_active)
	348	orion_spi_set_cs(orion_spi, 0);
	349
	350	m->status = status;
	351	spi_finalize_current_message(master);
	352
	353	return 0;
60cadec9 SA	354	}
60cadec9 SA	355
2deff8d6	356	static int orion_spi_reset(struct orion_spi *orion_spi)
60cadec9 SA	357	{
	358	/* Verify that the CS is deasserted */
	359	orion_spi_set_cs(orion_spi, 0);
	360
	361	return 0;
	362	}
	363
2deff8d6	364	static int orion_spi_probe(struct platform_device *pdev)
60cadec9 SA	365	{
	366	struct spi_master *master;
	367	struct orion_spi *spi;
	368	struct resource *r;
4574b886	369	unsigned long tclk_hz;
60cadec9	370	int status = 0;
f814f9ac AL	371	const u32 *iprop;
f814f9ac AL	372	int size;
60cadec9	373
3fed8068	374	master = spi_alloc_master(&pdev->dev, sizeof(*spi));
60cadec9 SA	375	if (master == NULL) {
	376	dev_dbg(&pdev->dev, "master allocation failed\n");
	377	return -ENOMEM;
	378	}
	379
	380	if (pdev->id != -1)
	381	master->bus_num = pdev->id;
f814f9ac AL	382	if (pdev->dev.of_node) {
	383	iprop = of_get_property(pdev->dev.of_node, "cell-index",
	384	&size);
	385	if (iprop && size == sizeof(*iprop))
	386	master->bus_num = *iprop;
	387	}
60cadec9	388
e7db06b5	389	/* we support only mode 0, and no options */
b15d5d70	390	master->mode_bits = SPI_CPHA \| SPI_CPOL;
e7db06b5	391
ba59a807	392	master->transfer_one_message = orion_spi_transfer_one_message;
60cadec9 SA	393	master->num_chipselect = ORION_NUM_CHIPSELECTS;
60cadec9 SA	394
24b5a82c	395	platform_set_drvdata(pdev, master);
60cadec9 SA	396
	397	spi = spi_master_get_devdata(master);
	398	spi->master = master;
60cadec9	399
bb489841	400	spi->clk = devm_clk_get(&pdev->dev, NULL);
4574b886 AL	401	if (IS_ERR(spi->clk)) {
	402	status = PTR_ERR(spi->clk);
	403	goto out;
	404	}
	405
	406	clk_prepare(spi->clk);
	407	clk_enable(spi->clk);
	408	tclk_hz = clk_get_rate(spi->clk);
b52a37f5 AL	409	master->max_speed_hz = DIV_ROUND_UP(tclk_hz, 4);
b52a37f5 AL	410	master->min_speed_hz = DIV_ROUND_UP(tclk_hz, 30);
60cadec9 SA	411
60cadec9 SA	412	r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1729ce34 MB	413	spi->base = devm_ioremap_resource(&pdev->dev, r);
	414	if (IS_ERR(spi->base)) {
	415	status = PTR_ERR(spi->base);
4574b886	416	goto out_rel_clk;
60cadec9 SA	417	}
60cadec9 SA	418
60cadec9	419	if (orion_spi_reset(spi) < 0)
1729ce34	420	goto out_rel_clk;
60cadec9	421
f814f9ac	422	master->dev.of_node = pdev->dev.of_node;
4bd3d8e3	423	status = devm_spi_register_master(&pdev->dev, master);
60cadec9	424	if (status < 0)
1729ce34	425	goto out_rel_clk;
60cadec9 SA	426
	427	return status;
	428
4574b886 AL	429	out_rel_clk:
4574b886 AL	430	clk_disable_unprepare(spi->clk);
60cadec9 SA	431	out:
	432	spi_master_put(master);
	433	return status;
	434	}
	435
	436
2deff8d6	437	static int orion_spi_remove(struct platform_device *pdev)
60cadec9 SA	438	{
60cadec9 SA	439	struct spi_master *master;
ba59a807	440	struct orion_spi *spi;
60cadec9	441
24b5a82c	442	master = platform_get_drvdata(pdev);
60cadec9 SA	443	spi = spi_master_get_devdata(master);
60cadec9 SA	444
4574b886	445	clk_disable_unprepare(spi->clk);
4574b886	446
60cadec9 SA	447	return 0;
	448	}
	449
	450	MODULE_ALIAS("platform:" DRIVER_NAME);
	451
fd4a319b	452	static const struct of_device_id orion_spi_of_match_table[] = {
f814f9ac AL	453	{ .compatible = "marvell,orion-spi", },
	454	{}
	455	};
	456	MODULE_DEVICE_TABLE(of, orion_spi_of_match_table);
	457
60cadec9 SA	458	static struct platform_driver orion_spi_driver = {
	459	.driver = {
	460	.name = DRIVER_NAME,
	461	.owner = THIS_MODULE,
f814f9ac	462	.of_match_table = of_match_ptr(orion_spi_of_match_table),
60cadec9	463	},
41ab724a	464	.probe = orion_spi_probe,
2deff8d6	465	.remove = orion_spi_remove,
60cadec9 SA	466	};
60cadec9 SA	467
41ab724a	468	module_platform_driver(orion_spi_driver);
60cadec9 SA	469
	470	MODULE_DESCRIPTION("Orion SPI driver");
	471	MODULE_AUTHOR("Shadi Ammouri <shadi@marvell.com>");
	472	MODULE_LICENSE("GPL");