Commit | Line | Data |
---|---|---|
b43d65f7 | 1 | /* |
b43d65f7 LW |
2 | * A driver for the ARM PL022 PrimeCell SSP/SPI bus master. |
3 | * | |
4 | * Copyright (C) 2008-2009 ST-Ericsson AB | |
5 | * Copyright (C) 2006 STMicroelectronics Pvt. Ltd. | |
6 | * | |
7 | * Author: Linus Walleij <linus.walleij@stericsson.com> | |
8 | * | |
9 | * Initial version inspired by: | |
10 | * linux-2.6.17-rc3-mm1/drivers/spi/pxa2xx_spi.c | |
11 | * Initial adoption to PL022 by: | |
12 | * Sachin Verma <sachin.verma@st.com> | |
13 | * | |
14 | * This program is free software; you can redistribute it and/or modify | |
15 | * it under the terms of the GNU General Public License as published by | |
16 | * the Free Software Foundation; either version 2 of the License, or | |
17 | * (at your option) any later version. | |
18 | * | |
19 | * This program is distributed in the hope that it will be useful, | |
20 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
21 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
22 | * GNU General Public License for more details. | |
23 | */ | |
24 | ||
b43d65f7 LW |
25 | #include <linux/init.h> |
26 | #include <linux/module.h> | |
27 | #include <linux/device.h> | |
28 | #include <linux/ioport.h> | |
29 | #include <linux/errno.h> | |
30 | #include <linux/interrupt.h> | |
31 | #include <linux/spi/spi.h> | |
32 | #include <linux/workqueue.h> | |
b43d65f7 LW |
33 | #include <linux/delay.h> |
34 | #include <linux/clk.h> | |
35 | #include <linux/err.h> | |
36 | #include <linux/amba/bus.h> | |
37 | #include <linux/amba/pl022.h> | |
38 | #include <linux/io.h> | |
5a0e3ad6 | 39 | #include <linux/slab.h> |
b1b6b9aa LW |
40 | #include <linux/dmaengine.h> |
41 | #include <linux/dma-mapping.h> | |
42 | #include <linux/scatterlist.h> | |
bcda6ff8 | 43 | #include <linux/pm_runtime.h> |
b43d65f7 LW |
44 | |
45 | /* | |
46 | * This macro is used to define some register default values. | |
47 | * reg is masked with mask, the OR:ed with an (again masked) | |
48 | * val shifted sb steps to the left. | |
49 | */ | |
50 | #define SSP_WRITE_BITS(reg, val, mask, sb) \ | |
51 | ((reg) = (((reg) & ~(mask)) | (((val)<<(sb)) & (mask)))) | |
52 | ||
53 | /* | |
54 | * This macro is also used to define some default values. | |
55 | * It will just shift val by sb steps to the left and mask | |
56 | * the result with mask. | |
57 | */ | |
58 | #define GEN_MASK_BITS(val, mask, sb) \ | |
59 | (((val)<<(sb)) & (mask)) | |
60 | ||
61 | #define DRIVE_TX 0 | |
62 | #define DO_NOT_DRIVE_TX 1 | |
63 | ||
64 | #define DO_NOT_QUEUE_DMA 0 | |
65 | #define QUEUE_DMA 1 | |
66 | ||
67 | #define RX_TRANSFER 1 | |
68 | #define TX_TRANSFER 2 | |
69 | ||
70 | /* | |
71 | * Macros to access SSP Registers with their offsets | |
72 | */ | |
73 | #define SSP_CR0(r) (r + 0x000) | |
74 | #define SSP_CR1(r) (r + 0x004) | |
75 | #define SSP_DR(r) (r + 0x008) | |
76 | #define SSP_SR(r) (r + 0x00C) | |
77 | #define SSP_CPSR(r) (r + 0x010) | |
78 | #define SSP_IMSC(r) (r + 0x014) | |
79 | #define SSP_RIS(r) (r + 0x018) | |
80 | #define SSP_MIS(r) (r + 0x01C) | |
81 | #define SSP_ICR(r) (r + 0x020) | |
82 | #define SSP_DMACR(r) (r + 0x024) | |
83 | #define SSP_ITCR(r) (r + 0x080) | |
84 | #define SSP_ITIP(r) (r + 0x084) | |
85 | #define SSP_ITOP(r) (r + 0x088) | |
86 | #define SSP_TDR(r) (r + 0x08C) | |
87 | ||
88 | #define SSP_PID0(r) (r + 0xFE0) | |
89 | #define SSP_PID1(r) (r + 0xFE4) | |
90 | #define SSP_PID2(r) (r + 0xFE8) | |
91 | #define SSP_PID3(r) (r + 0xFEC) | |
92 | ||
93 | #define SSP_CID0(r) (r + 0xFF0) | |
94 | #define SSP_CID1(r) (r + 0xFF4) | |
95 | #define SSP_CID2(r) (r + 0xFF8) | |
96 | #define SSP_CID3(r) (r + 0xFFC) | |
97 | ||
98 | /* | |
99 | * SSP Control Register 0 - SSP_CR0 | |
100 | */ | |
556f4aeb LW |
101 | #define SSP_CR0_MASK_DSS (0x0FUL << 0) |
102 | #define SSP_CR0_MASK_FRF (0x3UL << 4) | |
b43d65f7 LW |
103 | #define SSP_CR0_MASK_SPO (0x1UL << 6) |
104 | #define SSP_CR0_MASK_SPH (0x1UL << 7) | |
105 | #define SSP_CR0_MASK_SCR (0xFFUL << 8) | |
556f4aeb LW |
106 | |
107 | /* | |
108 | * The ST version of this block moves som bits | |
109 | * in SSP_CR0 and extends it to 32 bits | |
110 | */ | |
111 | #define SSP_CR0_MASK_DSS_ST (0x1FUL << 0) | |
112 | #define SSP_CR0_MASK_HALFDUP_ST (0x1UL << 5) | |
113 | #define SSP_CR0_MASK_CSS_ST (0x1FUL << 16) | |
114 | #define SSP_CR0_MASK_FRF_ST (0x3UL << 21) | |
115 | ||
b43d65f7 LW |
116 | /* |
117 | * SSP Control Register 0 - SSP_CR1 | |
118 | */ | |
119 | #define SSP_CR1_MASK_LBM (0x1UL << 0) | |
120 | #define SSP_CR1_MASK_SSE (0x1UL << 1) | |
121 | #define SSP_CR1_MASK_MS (0x1UL << 2) | |
122 | #define SSP_CR1_MASK_SOD (0x1UL << 3) | |
b43d65f7 LW |
123 | |
124 | /* | |
556f4aeb LW |
125 | * The ST version of this block adds some bits |
126 | * in SSP_CR1 | |
b43d65f7 | 127 | */ |
556f4aeb LW |
128 | #define SSP_CR1_MASK_RENDN_ST (0x1UL << 4) |
129 | #define SSP_CR1_MASK_TENDN_ST (0x1UL << 5) | |
130 | #define SSP_CR1_MASK_MWAIT_ST (0x1UL << 6) | |
131 | #define SSP_CR1_MASK_RXIFLSEL_ST (0x7UL << 7) | |
132 | #define SSP_CR1_MASK_TXIFLSEL_ST (0x7UL << 10) | |
781c7b12 LW |
133 | /* This one is only in the PL023 variant */ |
134 | #define SSP_CR1_MASK_FBCLKDEL_ST (0x7UL << 13) | |
b43d65f7 LW |
135 | |
136 | /* | |
137 | * SSP Status Register - SSP_SR | |
138 | */ | |
139 | #define SSP_SR_MASK_TFE (0x1UL << 0) /* Transmit FIFO empty */ | |
140 | #define SSP_SR_MASK_TNF (0x1UL << 1) /* Transmit FIFO not full */ | |
141 | #define SSP_SR_MASK_RNE (0x1UL << 2) /* Receive FIFO not empty */ | |
556f4aeb | 142 | #define SSP_SR_MASK_RFF (0x1UL << 3) /* Receive FIFO full */ |
b43d65f7 LW |
143 | #define SSP_SR_MASK_BSY (0x1UL << 4) /* Busy Flag */ |
144 | ||
145 | /* | |
146 | * SSP Clock Prescale Register - SSP_CPSR | |
147 | */ | |
148 | #define SSP_CPSR_MASK_CPSDVSR (0xFFUL << 0) | |
149 | ||
150 | /* | |
151 | * SSP Interrupt Mask Set/Clear Register - SSP_IMSC | |
152 | */ | |
153 | #define SSP_IMSC_MASK_RORIM (0x1UL << 0) /* Receive Overrun Interrupt mask */ | |
154 | #define SSP_IMSC_MASK_RTIM (0x1UL << 1) /* Receive timeout Interrupt mask */ | |
155 | #define SSP_IMSC_MASK_RXIM (0x1UL << 2) /* Receive FIFO Interrupt mask */ | |
156 | #define SSP_IMSC_MASK_TXIM (0x1UL << 3) /* Transmit FIFO Interrupt mask */ | |
157 | ||
158 | /* | |
159 | * SSP Raw Interrupt Status Register - SSP_RIS | |
160 | */ | |
161 | /* Receive Overrun Raw Interrupt status */ | |
162 | #define SSP_RIS_MASK_RORRIS (0x1UL << 0) | |
163 | /* Receive Timeout Raw Interrupt status */ | |
164 | #define SSP_RIS_MASK_RTRIS (0x1UL << 1) | |
165 | /* Receive FIFO Raw Interrupt status */ | |
166 | #define SSP_RIS_MASK_RXRIS (0x1UL << 2) | |
167 | /* Transmit FIFO Raw Interrupt status */ | |
168 | #define SSP_RIS_MASK_TXRIS (0x1UL << 3) | |
169 | ||
170 | /* | |
171 | * SSP Masked Interrupt Status Register - SSP_MIS | |
172 | */ | |
173 | /* Receive Overrun Masked Interrupt status */ | |
174 | #define SSP_MIS_MASK_RORMIS (0x1UL << 0) | |
175 | /* Receive Timeout Masked Interrupt status */ | |
176 | #define SSP_MIS_MASK_RTMIS (0x1UL << 1) | |
177 | /* Receive FIFO Masked Interrupt status */ | |
178 | #define SSP_MIS_MASK_RXMIS (0x1UL << 2) | |
179 | /* Transmit FIFO Masked Interrupt status */ | |
180 | #define SSP_MIS_MASK_TXMIS (0x1UL << 3) | |
181 | ||
182 | /* | |
183 | * SSP Interrupt Clear Register - SSP_ICR | |
184 | */ | |
185 | /* Receive Overrun Raw Clear Interrupt bit */ | |
186 | #define SSP_ICR_MASK_RORIC (0x1UL << 0) | |
187 | /* Receive Timeout Clear Interrupt bit */ | |
188 | #define SSP_ICR_MASK_RTIC (0x1UL << 1) | |
189 | ||
190 | /* | |
191 | * SSP DMA Control Register - SSP_DMACR | |
192 | */ | |
193 | /* Receive DMA Enable bit */ | |
194 | #define SSP_DMACR_MASK_RXDMAE (0x1UL << 0) | |
195 | /* Transmit DMA Enable bit */ | |
196 | #define SSP_DMACR_MASK_TXDMAE (0x1UL << 1) | |
197 | ||
198 | /* | |
199 | * SSP Integration Test control Register - SSP_ITCR | |
200 | */ | |
201 | #define SSP_ITCR_MASK_ITEN (0x1UL << 0) | |
202 | #define SSP_ITCR_MASK_TESTFIFO (0x1UL << 1) | |
203 | ||
204 | /* | |
205 | * SSP Integration Test Input Register - SSP_ITIP | |
206 | */ | |
207 | #define ITIP_MASK_SSPRXD (0x1UL << 0) | |
208 | #define ITIP_MASK_SSPFSSIN (0x1UL << 1) | |
209 | #define ITIP_MASK_SSPCLKIN (0x1UL << 2) | |
210 | #define ITIP_MASK_RXDMAC (0x1UL << 3) | |
211 | #define ITIP_MASK_TXDMAC (0x1UL << 4) | |
212 | #define ITIP_MASK_SSPTXDIN (0x1UL << 5) | |
213 | ||
214 | /* | |
215 | * SSP Integration Test output Register - SSP_ITOP | |
216 | */ | |
217 | #define ITOP_MASK_SSPTXD (0x1UL << 0) | |
218 | #define ITOP_MASK_SSPFSSOUT (0x1UL << 1) | |
219 | #define ITOP_MASK_SSPCLKOUT (0x1UL << 2) | |
220 | #define ITOP_MASK_SSPOEn (0x1UL << 3) | |
221 | #define ITOP_MASK_SSPCTLOEn (0x1UL << 4) | |
222 | #define ITOP_MASK_RORINTR (0x1UL << 5) | |
223 | #define ITOP_MASK_RTINTR (0x1UL << 6) | |
224 | #define ITOP_MASK_RXINTR (0x1UL << 7) | |
225 | #define ITOP_MASK_TXINTR (0x1UL << 8) | |
226 | #define ITOP_MASK_INTR (0x1UL << 9) | |
227 | #define ITOP_MASK_RXDMABREQ (0x1UL << 10) | |
228 | #define ITOP_MASK_RXDMASREQ (0x1UL << 11) | |
229 | #define ITOP_MASK_TXDMABREQ (0x1UL << 12) | |
230 | #define ITOP_MASK_TXDMASREQ (0x1UL << 13) | |
231 | ||
232 | /* | |
233 | * SSP Test Data Register - SSP_TDR | |
234 | */ | |
556f4aeb | 235 | #define TDR_MASK_TESTDATA (0xFFFFFFFF) |
b43d65f7 LW |
236 | |
237 | /* | |
238 | * Message State | |
239 | * we use the spi_message.state (void *) pointer to | |
240 | * hold a single state value, that's why all this | |
241 | * (void *) casting is done here. | |
242 | */ | |
556f4aeb LW |
243 | #define STATE_START ((void *) 0) |
244 | #define STATE_RUNNING ((void *) 1) | |
245 | #define STATE_DONE ((void *) 2) | |
246 | #define STATE_ERROR ((void *) -1) | |
b43d65f7 | 247 | |
b43d65f7 LW |
248 | /* |
249 | * SSP State - Whether Enabled or Disabled | |
250 | */ | |
556f4aeb LW |
251 | #define SSP_DISABLED (0) |
252 | #define SSP_ENABLED (1) | |
b43d65f7 LW |
253 | |
254 | /* | |
255 | * SSP DMA State - Whether DMA Enabled or Disabled | |
256 | */ | |
556f4aeb LW |
257 | #define SSP_DMA_DISABLED (0) |
258 | #define SSP_DMA_ENABLED (1) | |
b43d65f7 LW |
259 | |
260 | /* | |
261 | * SSP Clock Defaults | |
262 | */ | |
556f4aeb LW |
263 | #define SSP_DEFAULT_CLKRATE 0x2 |
264 | #define SSP_DEFAULT_PRESCALE 0x40 | |
b43d65f7 LW |
265 | |
266 | /* | |
267 | * SSP Clock Parameter ranges | |
268 | */ | |
269 | #define CPSDVR_MIN 0x02 | |
270 | #define CPSDVR_MAX 0xFE | |
271 | #define SCR_MIN 0x00 | |
272 | #define SCR_MAX 0xFF | |
273 | ||
274 | /* | |
275 | * SSP Interrupt related Macros | |
276 | */ | |
277 | #define DEFAULT_SSP_REG_IMSC 0x0UL | |
278 | #define DISABLE_ALL_INTERRUPTS DEFAULT_SSP_REG_IMSC | |
279 | #define ENABLE_ALL_INTERRUPTS (~DEFAULT_SSP_REG_IMSC) | |
280 | ||
281 | #define CLEAR_ALL_INTERRUPTS 0x3 | |
282 | ||
a18c266f MT |
283 | #define SPI_POLLING_TIMEOUT 1000 |
284 | ||
b43d65f7 LW |
285 | /* |
286 | * The type of reading going on on this chip | |
287 | */ | |
288 | enum ssp_reading { | |
289 | READING_NULL, | |
290 | READING_U8, | |
291 | READING_U16, | |
292 | READING_U32 | |
293 | }; | |
294 | ||
295 | /** | |
296 | * The type of writing going on on this chip | |
297 | */ | |
298 | enum ssp_writing { | |
299 | WRITING_NULL, | |
300 | WRITING_U8, | |
301 | WRITING_U16, | |
302 | WRITING_U32 | |
303 | }; | |
304 | ||
305 | /** | |
306 | * struct vendor_data - vendor-specific config parameters | |
307 | * for PL022 derivates | |
308 | * @fifodepth: depth of FIFOs (both) | |
309 | * @max_bpw: maximum number of bits per word | |
310 | * @unidir: supports unidirection transfers | |
556f4aeb LW |
311 | * @extended_cr: 32 bit wide control register 0 with extra |
312 | * features and extra features in CR1 as found in the ST variants | |
781c7b12 | 313 | * @pl023: supports a subset of the ST extensions called "PL023" |
b43d65f7 LW |
314 | */ |
315 | struct vendor_data { | |
316 | int fifodepth; | |
317 | int max_bpw; | |
318 | bool unidir; | |
556f4aeb | 319 | bool extended_cr; |
781c7b12 | 320 | bool pl023; |
06fb01fd | 321 | bool loopback; |
b43d65f7 LW |
322 | }; |
323 | ||
324 | /** | |
325 | * struct pl022 - This is the private SSP driver data structure | |
326 | * @adev: AMBA device model hookup | |
12e8b325 LW |
327 | * @vendor: vendor data for the IP block |
328 | * @phybase: the physical memory where the SSP device resides | |
329 | * @virtbase: the virtual memory where the SSP is mapped | |
330 | * @clk: outgoing clock "SPICLK" for the SPI bus | |
b43d65f7 LW |
331 | * @master: SPI framework hookup |
332 | * @master_info: controller-specific data from machine setup | |
b43d65f7 | 333 | * @workqueue: a workqueue on which any spi_message request is queued |
12e8b325 LW |
334 | * @pump_messages: work struct for scheduling work to the workqueue |
335 | * @queue_lock: spinlock to syncronise access to message queue | |
336 | * @queue: message queue | |
b43d65f7 | 337 | * @busy: workqueue is busy |
5e8b821d | 338 | * @running: workqueue is running |
b43d65f7 LW |
339 | * @pump_transfers: Tasklet used in Interrupt Transfer mode |
340 | * @cur_msg: Pointer to current spi_message being processed | |
341 | * @cur_transfer: Pointer to current spi_transfer | |
342 | * @cur_chip: pointer to current clients chip(assigned from controller_state) | |
8b8d7191 VS |
343 | * @next_msg_cs_active: the next message in the queue has been examined |
344 | * and it was found that it uses the same chip select as the previous | |
345 | * message, so we left it active after the previous transfer, and it's | |
346 | * active already. | |
b43d65f7 LW |
347 | * @tx: current position in TX buffer to be read |
348 | * @tx_end: end position in TX buffer to be read | |
349 | * @rx: current position in RX buffer to be written | |
350 | * @rx_end: end position in RX buffer to be written | |
12e8b325 LW |
351 | * @read: the type of read currently going on |
352 | * @write: the type of write currently going on | |
353 | * @exp_fifo_level: expected FIFO level | |
354 | * @dma_rx_channel: optional channel for RX DMA | |
355 | * @dma_tx_channel: optional channel for TX DMA | |
356 | * @sgt_rx: scattertable for the RX transfer | |
357 | * @sgt_tx: scattertable for the TX transfer | |
358 | * @dummypage: a dummy page used for driving data on the bus with DMA | |
b43d65f7 LW |
359 | */ |
360 | struct pl022 { | |
361 | struct amba_device *adev; | |
362 | struct vendor_data *vendor; | |
363 | resource_size_t phybase; | |
364 | void __iomem *virtbase; | |
365 | struct clk *clk; | |
366 | struct spi_master *master; | |
367 | struct pl022_ssp_controller *master_info; | |
368 | /* Driver message queue */ | |
369 | struct workqueue_struct *workqueue; | |
370 | struct work_struct pump_messages; | |
371 | spinlock_t queue_lock; | |
372 | struct list_head queue; | |
dec5a581 | 373 | bool busy; |
5e8b821d | 374 | bool running; |
b43d65f7 LW |
375 | /* Message transfer pump */ |
376 | struct tasklet_struct pump_transfers; | |
377 | struct spi_message *cur_msg; | |
378 | struct spi_transfer *cur_transfer; | |
379 | struct chip_data *cur_chip; | |
8b8d7191 | 380 | bool next_msg_cs_active; |
b43d65f7 LW |
381 | void *tx; |
382 | void *tx_end; | |
383 | void *rx; | |
384 | void *rx_end; | |
385 | enum ssp_reading read; | |
386 | enum ssp_writing write; | |
fc05475f | 387 | u32 exp_fifo_level; |
083be3f0 LW |
388 | enum ssp_rx_level_trig rx_lev_trig; |
389 | enum ssp_tx_level_trig tx_lev_trig; | |
b1b6b9aa LW |
390 | /* DMA settings */ |
391 | #ifdef CONFIG_DMA_ENGINE | |
392 | struct dma_chan *dma_rx_channel; | |
393 | struct dma_chan *dma_tx_channel; | |
394 | struct sg_table sgt_rx; | |
395 | struct sg_table sgt_tx; | |
396 | char *dummypage; | |
397 | #endif | |
b43d65f7 LW |
398 | }; |
399 | ||
400 | /** | |
401 | * struct chip_data - To maintain runtime state of SSP for each client chip | |
556f4aeb LW |
402 | * @cr0: Value of control register CR0 of SSP - on later ST variants this |
403 | * register is 32 bits wide rather than just 16 | |
b43d65f7 LW |
404 | * @cr1: Value of control register CR1 of SSP |
405 | * @dmacr: Value of DMA control Register of SSP | |
406 | * @cpsr: Value of Clock prescale register | |
407 | * @n_bytes: how many bytes(power of 2) reqd for a given data width of client | |
408 | * @enable_dma: Whether to enable DMA or not | |
b43d65f7 | 409 | * @read: function ptr to be used to read when doing xfer for this chip |
12e8b325 | 410 | * @write: function ptr to be used to write when doing xfer for this chip |
b43d65f7 LW |
411 | * @cs_control: chip select callback provided by chip |
412 | * @xfer_type: polling/interrupt/DMA | |
413 | * | |
414 | * Runtime state of the SSP controller, maintained per chip, | |
415 | * This would be set according to the current message that would be served | |
416 | */ | |
417 | struct chip_data { | |
556f4aeb | 418 | u32 cr0; |
b43d65f7 LW |
419 | u16 cr1; |
420 | u16 dmacr; | |
421 | u16 cpsr; | |
422 | u8 n_bytes; | |
b1b6b9aa | 423 | bool enable_dma; |
b43d65f7 LW |
424 | enum ssp_reading read; |
425 | enum ssp_writing write; | |
426 | void (*cs_control) (u32 command); | |
427 | int xfer_type; | |
428 | }; | |
429 | ||
430 | /** | |
431 | * null_cs_control - Dummy chip select function | |
432 | * @command: select/delect the chip | |
433 | * | |
434 | * If no chip select function is provided by client this is used as dummy | |
435 | * chip select | |
436 | */ | |
437 | static void null_cs_control(u32 command) | |
438 | { | |
439 | pr_debug("pl022: dummy chip select control, CS=0x%x\n", command); | |
440 | } | |
441 | ||
442 | /** | |
443 | * giveback - current spi_message is over, schedule next message and call | |
444 | * callback of this message. Assumes that caller already | |
445 | * set message->status; dma and pio irqs are blocked | |
446 | * @pl022: SSP driver private data structure | |
447 | */ | |
448 | static void giveback(struct pl022 *pl022) | |
449 | { | |
450 | struct spi_transfer *last_transfer; | |
451 | unsigned long flags; | |
452 | struct spi_message *msg; | |
8b8d7191 | 453 | pl022->next_msg_cs_active = false; |
b43d65f7 | 454 | |
8b8d7191 | 455 | last_transfer = list_entry(pl022->cur_msg->transfers.prev, |
b43d65f7 LW |
456 | struct spi_transfer, |
457 | transfer_list); | |
458 | ||
459 | /* Delay if requested before any change in chip select */ | |
460 | if (last_transfer->delay_usecs) | |
461 | /* | |
462 | * FIXME: This runs in interrupt context. | |
463 | * Is this really smart? | |
464 | */ | |
465 | udelay(last_transfer->delay_usecs); | |
466 | ||
8b8d7191 | 467 | if (!last_transfer->cs_change) { |
b43d65f7 LW |
468 | struct spi_message *next_msg; |
469 | ||
8b8d7191 VS |
470 | /* |
471 | * cs_change was not set. We can keep the chip select | |
472 | * enabled if there is message in the queue and it is | |
473 | * for the same spi device. | |
b43d65f7 LW |
474 | * |
475 | * We cannot postpone this until pump_messages, because | |
476 | * after calling msg->complete (below) the driver that | |
477 | * sent the current message could be unloaded, which | |
478 | * could invalidate the cs_control() callback... | |
479 | */ | |
480 | ||
481 | /* get a pointer to the next message, if any */ | |
482 | spin_lock_irqsave(&pl022->queue_lock, flags); | |
483 | if (list_empty(&pl022->queue)) | |
484 | next_msg = NULL; | |
485 | else | |
486 | next_msg = list_entry(pl022->queue.next, | |
487 | struct spi_message, queue); | |
488 | spin_unlock_irqrestore(&pl022->queue_lock, flags); | |
489 | ||
8b8d7191 VS |
490 | /* |
491 | * see if the next and current messages point | |
492 | * to the same spi device. | |
b43d65f7 | 493 | */ |
8b8d7191 | 494 | if (next_msg && next_msg->spi != pl022->cur_msg->spi) |
b43d65f7 | 495 | next_msg = NULL; |
8b8d7191 VS |
496 | if (!next_msg || pl022->cur_msg->state == STATE_ERROR) |
497 | pl022->cur_chip->cs_control(SSP_CHIP_DESELECT); | |
498 | else | |
499 | pl022->next_msg_cs_active = true; | |
b43d65f7 | 500 | } |
8b8d7191 VS |
501 | |
502 | spin_lock_irqsave(&pl022->queue_lock, flags); | |
503 | msg = pl022->cur_msg; | |
504 | pl022->cur_msg = NULL; | |
505 | pl022->cur_transfer = NULL; | |
506 | pl022->cur_chip = NULL; | |
507 | queue_work(pl022->workqueue, &pl022->pump_messages); | |
508 | spin_unlock_irqrestore(&pl022->queue_lock, flags); | |
509 | ||
b43d65f7 LW |
510 | msg->state = NULL; |
511 | if (msg->complete) | |
512 | msg->complete(msg->context); | |
b43d65f7 LW |
513 | } |
514 | ||
515 | /** | |
516 | * flush - flush the FIFO to reach a clean state | |
517 | * @pl022: SSP driver private data structure | |
518 | */ | |
519 | static int flush(struct pl022 *pl022) | |
520 | { | |
521 | unsigned long limit = loops_per_jiffy << 1; | |
522 | ||
523 | dev_dbg(&pl022->adev->dev, "flush\n"); | |
524 | do { | |
525 | while (readw(SSP_SR(pl022->virtbase)) & SSP_SR_MASK_RNE) | |
526 | readw(SSP_DR(pl022->virtbase)); | |
527 | } while ((readw(SSP_SR(pl022->virtbase)) & SSP_SR_MASK_BSY) && limit--); | |
fc05475f LW |
528 | |
529 | pl022->exp_fifo_level = 0; | |
530 | ||
b43d65f7 LW |
531 | return limit; |
532 | } | |
533 | ||
534 | /** | |
535 | * restore_state - Load configuration of current chip | |
536 | * @pl022: SSP driver private data structure | |
537 | */ | |
538 | static void restore_state(struct pl022 *pl022) | |
539 | { | |
540 | struct chip_data *chip = pl022->cur_chip; | |
541 | ||
556f4aeb LW |
542 | if (pl022->vendor->extended_cr) |
543 | writel(chip->cr0, SSP_CR0(pl022->virtbase)); | |
544 | else | |
545 | writew(chip->cr0, SSP_CR0(pl022->virtbase)); | |
b43d65f7 LW |
546 | writew(chip->cr1, SSP_CR1(pl022->virtbase)); |
547 | writew(chip->dmacr, SSP_DMACR(pl022->virtbase)); | |
548 | writew(chip->cpsr, SSP_CPSR(pl022->virtbase)); | |
549 | writew(DISABLE_ALL_INTERRUPTS, SSP_IMSC(pl022->virtbase)); | |
550 | writew(CLEAR_ALL_INTERRUPTS, SSP_ICR(pl022->virtbase)); | |
551 | } | |
552 | ||
b43d65f7 LW |
553 | /* |
554 | * Default SSP Register Values | |
555 | */ | |
556 | #define DEFAULT_SSP_REG_CR0 ( \ | |
557 | GEN_MASK_BITS(SSP_DATA_BITS_12, SSP_CR0_MASK_DSS, 0) | \ | |
556f4aeb LW |
558 | GEN_MASK_BITS(SSP_INTERFACE_MOTOROLA_SPI, SSP_CR0_MASK_FRF, 4) | \ |
559 | GEN_MASK_BITS(SSP_CLK_POL_IDLE_LOW, SSP_CR0_MASK_SPO, 6) | \ | |
560 | GEN_MASK_BITS(SSP_CLK_SECOND_EDGE, SSP_CR0_MASK_SPH, 7) | \ | |
561 | GEN_MASK_BITS(SSP_DEFAULT_CLKRATE, SSP_CR0_MASK_SCR, 8) \ | |
562 | ) | |
563 | ||
564 | /* ST versions have slightly different bit layout */ | |
565 | #define DEFAULT_SSP_REG_CR0_ST ( \ | |
566 | GEN_MASK_BITS(SSP_DATA_BITS_12, SSP_CR0_MASK_DSS_ST, 0) | \ | |
567 | GEN_MASK_BITS(SSP_MICROWIRE_CHANNEL_FULL_DUPLEX, SSP_CR0_MASK_HALFDUP_ST, 5) | \ | |
b43d65f7 | 568 | GEN_MASK_BITS(SSP_CLK_POL_IDLE_LOW, SSP_CR0_MASK_SPO, 6) | \ |
ee2b805c | 569 | GEN_MASK_BITS(SSP_CLK_SECOND_EDGE, SSP_CR0_MASK_SPH, 7) | \ |
556f4aeb LW |
570 | GEN_MASK_BITS(SSP_DEFAULT_CLKRATE, SSP_CR0_MASK_SCR, 8) | \ |
571 | GEN_MASK_BITS(SSP_BITS_8, SSP_CR0_MASK_CSS_ST, 16) | \ | |
572 | GEN_MASK_BITS(SSP_INTERFACE_MOTOROLA_SPI, SSP_CR0_MASK_FRF_ST, 21) \ | |
b43d65f7 LW |
573 | ) |
574 | ||
781c7b12 LW |
575 | /* The PL023 version is slightly different again */ |
576 | #define DEFAULT_SSP_REG_CR0_ST_PL023 ( \ | |
577 | GEN_MASK_BITS(SSP_DATA_BITS_12, SSP_CR0_MASK_DSS_ST, 0) | \ | |
578 | GEN_MASK_BITS(SSP_CLK_POL_IDLE_LOW, SSP_CR0_MASK_SPO, 6) | \ | |
579 | GEN_MASK_BITS(SSP_CLK_SECOND_EDGE, SSP_CR0_MASK_SPH, 7) | \ | |
580 | GEN_MASK_BITS(SSP_DEFAULT_CLKRATE, SSP_CR0_MASK_SCR, 8) \ | |
581 | ) | |
582 | ||
b43d65f7 LW |
583 | #define DEFAULT_SSP_REG_CR1 ( \ |
584 | GEN_MASK_BITS(LOOPBACK_DISABLED, SSP_CR1_MASK_LBM, 0) | \ | |
585 | GEN_MASK_BITS(SSP_DISABLED, SSP_CR1_MASK_SSE, 1) | \ | |
586 | GEN_MASK_BITS(SSP_MASTER, SSP_CR1_MASK_MS, 2) | \ | |
556f4aeb | 587 | GEN_MASK_BITS(DO_NOT_DRIVE_TX, SSP_CR1_MASK_SOD, 3) \ |
b43d65f7 LW |
588 | ) |
589 | ||
556f4aeb LW |
590 | /* ST versions extend this register to use all 16 bits */ |
591 | #define DEFAULT_SSP_REG_CR1_ST ( \ | |
592 | DEFAULT_SSP_REG_CR1 | \ | |
593 | GEN_MASK_BITS(SSP_RX_MSB, SSP_CR1_MASK_RENDN_ST, 4) | \ | |
594 | GEN_MASK_BITS(SSP_TX_MSB, SSP_CR1_MASK_TENDN_ST, 5) | \ | |
595 | GEN_MASK_BITS(SSP_MWIRE_WAIT_ZERO, SSP_CR1_MASK_MWAIT_ST, 6) |\ | |
596 | GEN_MASK_BITS(SSP_RX_1_OR_MORE_ELEM, SSP_CR1_MASK_RXIFLSEL_ST, 7) | \ | |
597 | GEN_MASK_BITS(SSP_TX_1_OR_MORE_EMPTY_LOC, SSP_CR1_MASK_TXIFLSEL_ST, 10) \ | |
598 | ) | |
599 | ||
781c7b12 LW |
600 | /* |
601 | * The PL023 variant has further differences: no loopback mode, no microwire | |
602 | * support, and a new clock feedback delay setting. | |
603 | */ | |
604 | #define DEFAULT_SSP_REG_CR1_ST_PL023 ( \ | |
605 | GEN_MASK_BITS(SSP_DISABLED, SSP_CR1_MASK_SSE, 1) | \ | |
606 | GEN_MASK_BITS(SSP_MASTER, SSP_CR1_MASK_MS, 2) | \ | |
607 | GEN_MASK_BITS(DO_NOT_DRIVE_TX, SSP_CR1_MASK_SOD, 3) | \ | |
608 | GEN_MASK_BITS(SSP_RX_MSB, SSP_CR1_MASK_RENDN_ST, 4) | \ | |
609 | GEN_MASK_BITS(SSP_TX_MSB, SSP_CR1_MASK_TENDN_ST, 5) | \ | |
610 | GEN_MASK_BITS(SSP_RX_1_OR_MORE_ELEM, SSP_CR1_MASK_RXIFLSEL_ST, 7) | \ | |
611 | GEN_MASK_BITS(SSP_TX_1_OR_MORE_EMPTY_LOC, SSP_CR1_MASK_TXIFLSEL_ST, 10) | \ | |
612 | GEN_MASK_BITS(SSP_FEEDBACK_CLK_DELAY_NONE, SSP_CR1_MASK_FBCLKDEL_ST, 13) \ | |
613 | ) | |
556f4aeb | 614 | |
b43d65f7 | 615 | #define DEFAULT_SSP_REG_CPSR ( \ |
556f4aeb | 616 | GEN_MASK_BITS(SSP_DEFAULT_PRESCALE, SSP_CPSR_MASK_CPSDVSR, 0) \ |
b43d65f7 LW |
617 | ) |
618 | ||
619 | #define DEFAULT_SSP_REG_DMACR (\ | |
620 | GEN_MASK_BITS(SSP_DMA_DISABLED, SSP_DMACR_MASK_RXDMAE, 0) | \ | |
621 | GEN_MASK_BITS(SSP_DMA_DISABLED, SSP_DMACR_MASK_TXDMAE, 1) \ | |
622 | ) | |
623 | ||
781c7b12 LW |
624 | /** |
625 | * load_ssp_default_config - Load default configuration for SSP | |
626 | * @pl022: SSP driver private data structure | |
627 | */ | |
b43d65f7 LW |
628 | static void load_ssp_default_config(struct pl022 *pl022) |
629 | { | |
781c7b12 LW |
630 | if (pl022->vendor->pl023) { |
631 | writel(DEFAULT_SSP_REG_CR0_ST_PL023, SSP_CR0(pl022->virtbase)); | |
632 | writew(DEFAULT_SSP_REG_CR1_ST_PL023, SSP_CR1(pl022->virtbase)); | |
633 | } else if (pl022->vendor->extended_cr) { | |
556f4aeb LW |
634 | writel(DEFAULT_SSP_REG_CR0_ST, SSP_CR0(pl022->virtbase)); |
635 | writew(DEFAULT_SSP_REG_CR1_ST, SSP_CR1(pl022->virtbase)); | |
636 | } else { | |
637 | writew(DEFAULT_SSP_REG_CR0, SSP_CR0(pl022->virtbase)); | |
638 | writew(DEFAULT_SSP_REG_CR1, SSP_CR1(pl022->virtbase)); | |
639 | } | |
b43d65f7 LW |
640 | writew(DEFAULT_SSP_REG_DMACR, SSP_DMACR(pl022->virtbase)); |
641 | writew(DEFAULT_SSP_REG_CPSR, SSP_CPSR(pl022->virtbase)); | |
642 | writew(DISABLE_ALL_INTERRUPTS, SSP_IMSC(pl022->virtbase)); | |
643 | writew(CLEAR_ALL_INTERRUPTS, SSP_ICR(pl022->virtbase)); | |
644 | } | |
645 | ||
646 | /** | |
647 | * This will write to TX and read from RX according to the parameters | |
648 | * set in pl022. | |
649 | */ | |
650 | static void readwriter(struct pl022 *pl022) | |
651 | { | |
652 | ||
653 | /* | |
25985edc | 654 | * The FIFO depth is different between primecell variants. |
b43d65f7 LW |
655 | * I believe filling in too much in the FIFO might cause |
656 | * errons in 8bit wide transfers on ARM variants (just 8 words | |
657 | * FIFO, means only 8x8 = 64 bits in FIFO) at least. | |
658 | * | |
fc05475f LW |
659 | * To prevent this issue, the TX FIFO is only filled to the |
660 | * unused RX FIFO fill length, regardless of what the TX | |
661 | * FIFO status flag indicates. | |
b43d65f7 LW |
662 | */ |
663 | dev_dbg(&pl022->adev->dev, | |
664 | "%s, rx: %p, rxend: %p, tx: %p, txend: %p\n", | |
665 | __func__, pl022->rx, pl022->rx_end, pl022->tx, pl022->tx_end); | |
666 | ||
667 | /* Read as much as you can */ | |
668 | while ((readw(SSP_SR(pl022->virtbase)) & SSP_SR_MASK_RNE) | |
669 | && (pl022->rx < pl022->rx_end)) { | |
670 | switch (pl022->read) { | |
671 | case READING_NULL: | |
672 | readw(SSP_DR(pl022->virtbase)); | |
673 | break; | |
674 | case READING_U8: | |
675 | *(u8 *) (pl022->rx) = | |
676 | readw(SSP_DR(pl022->virtbase)) & 0xFFU; | |
677 | break; | |
678 | case READING_U16: | |
679 | *(u16 *) (pl022->rx) = | |
680 | (u16) readw(SSP_DR(pl022->virtbase)); | |
681 | break; | |
682 | case READING_U32: | |
683 | *(u32 *) (pl022->rx) = | |
684 | readl(SSP_DR(pl022->virtbase)); | |
685 | break; | |
686 | } | |
687 | pl022->rx += (pl022->cur_chip->n_bytes); | |
fc05475f | 688 | pl022->exp_fifo_level--; |
b43d65f7 LW |
689 | } |
690 | /* | |
fc05475f | 691 | * Write as much as possible up to the RX FIFO size |
b43d65f7 | 692 | */ |
fc05475f | 693 | while ((pl022->exp_fifo_level < pl022->vendor->fifodepth) |
b43d65f7 LW |
694 | && (pl022->tx < pl022->tx_end)) { |
695 | switch (pl022->write) { | |
696 | case WRITING_NULL: | |
697 | writew(0x0, SSP_DR(pl022->virtbase)); | |
698 | break; | |
699 | case WRITING_U8: | |
700 | writew(*(u8 *) (pl022->tx), SSP_DR(pl022->virtbase)); | |
701 | break; | |
702 | case WRITING_U16: | |
703 | writew((*(u16 *) (pl022->tx)), SSP_DR(pl022->virtbase)); | |
704 | break; | |
705 | case WRITING_U32: | |
706 | writel(*(u32 *) (pl022->tx), SSP_DR(pl022->virtbase)); | |
707 | break; | |
708 | } | |
709 | pl022->tx += (pl022->cur_chip->n_bytes); | |
fc05475f | 710 | pl022->exp_fifo_level++; |
b43d65f7 LW |
711 | /* |
712 | * This inner reader takes care of things appearing in the RX | |
713 | * FIFO as we're transmitting. This will happen a lot since the | |
714 | * clock starts running when you put things into the TX FIFO, | |
25985edc | 715 | * and then things are continuously clocked into the RX FIFO. |
b43d65f7 LW |
716 | */ |
717 | while ((readw(SSP_SR(pl022->virtbase)) & SSP_SR_MASK_RNE) | |
718 | && (pl022->rx < pl022->rx_end)) { | |
719 | switch (pl022->read) { | |
720 | case READING_NULL: | |
721 | readw(SSP_DR(pl022->virtbase)); | |
722 | break; | |
723 | case READING_U8: | |
724 | *(u8 *) (pl022->rx) = | |
725 | readw(SSP_DR(pl022->virtbase)) & 0xFFU; | |
726 | break; | |
727 | case READING_U16: | |
728 | *(u16 *) (pl022->rx) = | |
729 | (u16) readw(SSP_DR(pl022->virtbase)); | |
730 | break; | |
731 | case READING_U32: | |
732 | *(u32 *) (pl022->rx) = | |
733 | readl(SSP_DR(pl022->virtbase)); | |
734 | break; | |
735 | } | |
736 | pl022->rx += (pl022->cur_chip->n_bytes); | |
fc05475f | 737 | pl022->exp_fifo_level--; |
b43d65f7 LW |
738 | } |
739 | } | |
740 | /* | |
741 | * When we exit here the TX FIFO should be full and the RX FIFO | |
742 | * should be empty | |
743 | */ | |
744 | } | |
745 | ||
b43d65f7 LW |
746 | /** |
747 | * next_transfer - Move to the Next transfer in the current spi message | |
748 | * @pl022: SSP driver private data structure | |
749 | * | |
750 | * This function moves though the linked list of spi transfers in the | |
751 | * current spi message and returns with the state of current spi | |
752 | * message i.e whether its last transfer is done(STATE_DONE) or | |
753 | * Next transfer is ready(STATE_RUNNING) | |
754 | */ | |
755 | static void *next_transfer(struct pl022 *pl022) | |
756 | { | |
757 | struct spi_message *msg = pl022->cur_msg; | |
758 | struct spi_transfer *trans = pl022->cur_transfer; | |
759 | ||
760 | /* Move to next transfer */ | |
761 | if (trans->transfer_list.next != &msg->transfers) { | |
762 | pl022->cur_transfer = | |
763 | list_entry(trans->transfer_list.next, | |
764 | struct spi_transfer, transfer_list); | |
765 | return STATE_RUNNING; | |
766 | } | |
767 | return STATE_DONE; | |
768 | } | |
b1b6b9aa LW |
769 | |
770 | /* | |
771 | * This DMA functionality is only compiled in if we have | |
772 | * access to the generic DMA devices/DMA engine. | |
773 | */ | |
774 | #ifdef CONFIG_DMA_ENGINE | |
775 | static void unmap_free_dma_scatter(struct pl022 *pl022) | |
776 | { | |
777 | /* Unmap and free the SG tables */ | |
b7298896 | 778 | dma_unmap_sg(pl022->dma_tx_channel->device->dev, pl022->sgt_tx.sgl, |
b1b6b9aa | 779 | pl022->sgt_tx.nents, DMA_TO_DEVICE); |
b7298896 | 780 | dma_unmap_sg(pl022->dma_rx_channel->device->dev, pl022->sgt_rx.sgl, |
b1b6b9aa LW |
781 | pl022->sgt_rx.nents, DMA_FROM_DEVICE); |
782 | sg_free_table(&pl022->sgt_rx); | |
783 | sg_free_table(&pl022->sgt_tx); | |
784 | } | |
785 | ||
786 | static void dma_callback(void *data) | |
787 | { | |
788 | struct pl022 *pl022 = data; | |
789 | struct spi_message *msg = pl022->cur_msg; | |
790 | ||
791 | BUG_ON(!pl022->sgt_rx.sgl); | |
792 | ||
793 | #ifdef VERBOSE_DEBUG | |
794 | /* | |
795 | * Optionally dump out buffers to inspect contents, this is | |
796 | * good if you want to convince yourself that the loopback | |
797 | * read/write contents are the same, when adopting to a new | |
798 | * DMA engine. | |
799 | */ | |
800 | { | |
801 | struct scatterlist *sg; | |
802 | unsigned int i; | |
803 | ||
804 | dma_sync_sg_for_cpu(&pl022->adev->dev, | |
805 | pl022->sgt_rx.sgl, | |
806 | pl022->sgt_rx.nents, | |
807 | DMA_FROM_DEVICE); | |
808 | ||
809 | for_each_sg(pl022->sgt_rx.sgl, sg, pl022->sgt_rx.nents, i) { | |
810 | dev_dbg(&pl022->adev->dev, "SPI RX SG ENTRY: %d", i); | |
811 | print_hex_dump(KERN_ERR, "SPI RX: ", | |
812 | DUMP_PREFIX_OFFSET, | |
813 | 16, | |
814 | 1, | |
815 | sg_virt(sg), | |
816 | sg_dma_len(sg), | |
817 | 1); | |
818 | } | |
819 | for_each_sg(pl022->sgt_tx.sgl, sg, pl022->sgt_tx.nents, i) { | |
820 | dev_dbg(&pl022->adev->dev, "SPI TX SG ENTRY: %d", i); | |
821 | print_hex_dump(KERN_ERR, "SPI TX: ", | |
822 | DUMP_PREFIX_OFFSET, | |
823 | 16, | |
824 | 1, | |
825 | sg_virt(sg), | |
826 | sg_dma_len(sg), | |
827 | 1); | |
828 | } | |
829 | } | |
830 | #endif | |
831 | ||
832 | unmap_free_dma_scatter(pl022); | |
833 | ||
25985edc | 834 | /* Update total bytes transferred */ |
b1b6b9aa LW |
835 | msg->actual_length += pl022->cur_transfer->len; |
836 | if (pl022->cur_transfer->cs_change) | |
837 | pl022->cur_chip-> | |
838 | cs_control(SSP_CHIP_DESELECT); | |
839 | ||
840 | /* Move to next transfer */ | |
841 | msg->state = next_transfer(pl022); | |
842 | tasklet_schedule(&pl022->pump_transfers); | |
843 | } | |
844 | ||
845 | static void setup_dma_scatter(struct pl022 *pl022, | |
846 | void *buffer, | |
847 | unsigned int length, | |
848 | struct sg_table *sgtab) | |
849 | { | |
850 | struct scatterlist *sg; | |
851 | int bytesleft = length; | |
852 | void *bufp = buffer; | |
853 | int mapbytes; | |
854 | int i; | |
855 | ||
856 | if (buffer) { | |
857 | for_each_sg(sgtab->sgl, sg, sgtab->nents, i) { | |
858 | /* | |
859 | * If there are less bytes left than what fits | |
860 | * in the current page (plus page alignment offset) | |
861 | * we just feed in this, else we stuff in as much | |
862 | * as we can. | |
863 | */ | |
864 | if (bytesleft < (PAGE_SIZE - offset_in_page(bufp))) | |
865 | mapbytes = bytesleft; | |
866 | else | |
867 | mapbytes = PAGE_SIZE - offset_in_page(bufp); | |
868 | sg_set_page(sg, virt_to_page(bufp), | |
869 | mapbytes, offset_in_page(bufp)); | |
870 | bufp += mapbytes; | |
871 | bytesleft -= mapbytes; | |
872 | dev_dbg(&pl022->adev->dev, | |
873 | "set RX/TX target page @ %p, %d bytes, %d left\n", | |
874 | bufp, mapbytes, bytesleft); | |
875 | } | |
876 | } else { | |
877 | /* Map the dummy buffer on every page */ | |
878 | for_each_sg(sgtab->sgl, sg, sgtab->nents, i) { | |
879 | if (bytesleft < PAGE_SIZE) | |
880 | mapbytes = bytesleft; | |
881 | else | |
882 | mapbytes = PAGE_SIZE; | |
883 | sg_set_page(sg, virt_to_page(pl022->dummypage), | |
884 | mapbytes, 0); | |
885 | bytesleft -= mapbytes; | |
886 | dev_dbg(&pl022->adev->dev, | |
887 | "set RX/TX to dummy page %d bytes, %d left\n", | |
888 | mapbytes, bytesleft); | |
889 | ||
890 | } | |
891 | } | |
892 | BUG_ON(bytesleft); | |
893 | } | |
894 | ||
895 | /** | |
896 | * configure_dma - configures the channels for the next transfer | |
897 | * @pl022: SSP driver's private data structure | |
898 | */ | |
899 | static int configure_dma(struct pl022 *pl022) | |
900 | { | |
901 | struct dma_slave_config rx_conf = { | |
902 | .src_addr = SSP_DR(pl022->phybase), | |
a485df4b | 903 | .direction = DMA_DEV_TO_MEM, |
258aea76 | 904 | .device_fc = false, |
b1b6b9aa LW |
905 | }; |
906 | struct dma_slave_config tx_conf = { | |
907 | .dst_addr = SSP_DR(pl022->phybase), | |
a485df4b | 908 | .direction = DMA_MEM_TO_DEV, |
258aea76 | 909 | .device_fc = false, |
b1b6b9aa LW |
910 | }; |
911 | unsigned int pages; | |
912 | int ret; | |
082086f2 | 913 | int rx_sglen, tx_sglen; |
b1b6b9aa LW |
914 | struct dma_chan *rxchan = pl022->dma_rx_channel; |
915 | struct dma_chan *txchan = pl022->dma_tx_channel; | |
916 | struct dma_async_tx_descriptor *rxdesc; | |
917 | struct dma_async_tx_descriptor *txdesc; | |
b1b6b9aa LW |
918 | |
919 | /* Check that the channels are available */ | |
920 | if (!rxchan || !txchan) | |
921 | return -ENODEV; | |
922 | ||
083be3f0 LW |
923 | /* |
924 | * If supplied, the DMA burstsize should equal the FIFO trigger level. | |
925 | * Notice that the DMA engine uses one-to-one mapping. Since we can | |
926 | * not trigger on 2 elements this needs explicit mapping rather than | |
927 | * calculation. | |
928 | */ | |
929 | switch (pl022->rx_lev_trig) { | |
930 | case SSP_RX_1_OR_MORE_ELEM: | |
931 | rx_conf.src_maxburst = 1; | |
932 | break; | |
933 | case SSP_RX_4_OR_MORE_ELEM: | |
934 | rx_conf.src_maxburst = 4; | |
935 | break; | |
936 | case SSP_RX_8_OR_MORE_ELEM: | |
937 | rx_conf.src_maxburst = 8; | |
938 | break; | |
939 | case SSP_RX_16_OR_MORE_ELEM: | |
940 | rx_conf.src_maxburst = 16; | |
941 | break; | |
942 | case SSP_RX_32_OR_MORE_ELEM: | |
943 | rx_conf.src_maxburst = 32; | |
944 | break; | |
945 | default: | |
946 | rx_conf.src_maxburst = pl022->vendor->fifodepth >> 1; | |
947 | break; | |
948 | } | |
949 | ||
950 | switch (pl022->tx_lev_trig) { | |
951 | case SSP_TX_1_OR_MORE_EMPTY_LOC: | |
952 | tx_conf.dst_maxburst = 1; | |
953 | break; | |
954 | case SSP_TX_4_OR_MORE_EMPTY_LOC: | |
955 | tx_conf.dst_maxburst = 4; | |
956 | break; | |
957 | case SSP_TX_8_OR_MORE_EMPTY_LOC: | |
958 | tx_conf.dst_maxburst = 8; | |
959 | break; | |
960 | case SSP_TX_16_OR_MORE_EMPTY_LOC: | |
961 | tx_conf.dst_maxburst = 16; | |
962 | break; | |
963 | case SSP_TX_32_OR_MORE_EMPTY_LOC: | |
964 | tx_conf.dst_maxburst = 32; | |
965 | break; | |
966 | default: | |
967 | tx_conf.dst_maxburst = pl022->vendor->fifodepth >> 1; | |
968 | break; | |
969 | } | |
970 | ||
b1b6b9aa LW |
971 | switch (pl022->read) { |
972 | case READING_NULL: | |
973 | /* Use the same as for writing */ | |
974 | rx_conf.src_addr_width = DMA_SLAVE_BUSWIDTH_UNDEFINED; | |
975 | break; | |
976 | case READING_U8: | |
977 | rx_conf.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; | |
978 | break; | |
979 | case READING_U16: | |
980 | rx_conf.src_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES; | |
981 | break; | |
982 | case READING_U32: | |
983 | rx_conf.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; | |
984 | break; | |
985 | } | |
986 | ||
987 | switch (pl022->write) { | |
988 | case WRITING_NULL: | |
989 | /* Use the same as for reading */ | |
990 | tx_conf.dst_addr_width = DMA_SLAVE_BUSWIDTH_UNDEFINED; | |
991 | break; | |
992 | case WRITING_U8: | |
993 | tx_conf.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; | |
994 | break; | |
995 | case WRITING_U16: | |
996 | tx_conf.dst_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES; | |
997 | break; | |
998 | case WRITING_U32: | |
bc3f67a3 | 999 | tx_conf.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; |
b1b6b9aa LW |
1000 | break; |
1001 | } | |
1002 | ||
1003 | /* SPI pecularity: we need to read and write the same width */ | |
1004 | if (rx_conf.src_addr_width == DMA_SLAVE_BUSWIDTH_UNDEFINED) | |
1005 | rx_conf.src_addr_width = tx_conf.dst_addr_width; | |
1006 | if (tx_conf.dst_addr_width == DMA_SLAVE_BUSWIDTH_UNDEFINED) | |
1007 | tx_conf.dst_addr_width = rx_conf.src_addr_width; | |
1008 | BUG_ON(rx_conf.src_addr_width != tx_conf.dst_addr_width); | |
1009 | ||
ecd442fd LW |
1010 | dmaengine_slave_config(rxchan, &rx_conf); |
1011 | dmaengine_slave_config(txchan, &tx_conf); | |
b1b6b9aa LW |
1012 | |
1013 | /* Create sglists for the transfers */ | |
b181565e | 1014 | pages = DIV_ROUND_UP(pl022->cur_transfer->len, PAGE_SIZE); |
b1b6b9aa LW |
1015 | dev_dbg(&pl022->adev->dev, "using %d pages for transfer\n", pages); |
1016 | ||
538a18dc | 1017 | ret = sg_alloc_table(&pl022->sgt_rx, pages, GFP_ATOMIC); |
b1b6b9aa LW |
1018 | if (ret) |
1019 | goto err_alloc_rx_sg; | |
1020 | ||
538a18dc | 1021 | ret = sg_alloc_table(&pl022->sgt_tx, pages, GFP_ATOMIC); |
b1b6b9aa LW |
1022 | if (ret) |
1023 | goto err_alloc_tx_sg; | |
1024 | ||
1025 | /* Fill in the scatterlists for the RX+TX buffers */ | |
1026 | setup_dma_scatter(pl022, pl022->rx, | |
1027 | pl022->cur_transfer->len, &pl022->sgt_rx); | |
1028 | setup_dma_scatter(pl022, pl022->tx, | |
1029 | pl022->cur_transfer->len, &pl022->sgt_tx); | |
1030 | ||
1031 | /* Map DMA buffers */ | |
082086f2 | 1032 | rx_sglen = dma_map_sg(rxchan->device->dev, pl022->sgt_rx.sgl, |
b1b6b9aa | 1033 | pl022->sgt_rx.nents, DMA_FROM_DEVICE); |
082086f2 | 1034 | if (!rx_sglen) |
b1b6b9aa LW |
1035 | goto err_rx_sgmap; |
1036 | ||
082086f2 | 1037 | tx_sglen = dma_map_sg(txchan->device->dev, pl022->sgt_tx.sgl, |
b1b6b9aa | 1038 | pl022->sgt_tx.nents, DMA_TO_DEVICE); |
082086f2 | 1039 | if (!tx_sglen) |
b1b6b9aa LW |
1040 | goto err_tx_sgmap; |
1041 | ||
1042 | /* Send both scatterlists */ | |
1043 | rxdesc = rxchan->device->device_prep_slave_sg(rxchan, | |
1044 | pl022->sgt_rx.sgl, | |
082086f2 | 1045 | rx_sglen, |
a485df4b | 1046 | DMA_DEV_TO_MEM, |
b1b6b9aa LW |
1047 | DMA_PREP_INTERRUPT | DMA_CTRL_ACK); |
1048 | if (!rxdesc) | |
1049 | goto err_rxdesc; | |
1050 | ||
1051 | txdesc = txchan->device->device_prep_slave_sg(txchan, | |
1052 | pl022->sgt_tx.sgl, | |
082086f2 | 1053 | tx_sglen, |
a485df4b | 1054 | DMA_MEM_TO_DEV, |
b1b6b9aa LW |
1055 | DMA_PREP_INTERRUPT | DMA_CTRL_ACK); |
1056 | if (!txdesc) | |
1057 | goto err_txdesc; | |
1058 | ||
1059 | /* Put the callback on the RX transfer only, that should finish last */ | |
1060 | rxdesc->callback = dma_callback; | |
1061 | rxdesc->callback_param = pl022; | |
1062 | ||
1063 | /* Submit and fire RX and TX with TX last so we're ready to read! */ | |
ecd442fd LW |
1064 | dmaengine_submit(rxdesc); |
1065 | dmaengine_submit(txdesc); | |
1066 | dma_async_issue_pending(rxchan); | |
1067 | dma_async_issue_pending(txchan); | |
b1b6b9aa LW |
1068 | |
1069 | return 0; | |
1070 | ||
b1b6b9aa | 1071 | err_txdesc: |
ecd442fd | 1072 | dmaengine_terminate_all(txchan); |
b1b6b9aa | 1073 | err_rxdesc: |
ecd442fd | 1074 | dmaengine_terminate_all(rxchan); |
b7298896 | 1075 | dma_unmap_sg(txchan->device->dev, pl022->sgt_tx.sgl, |
b1b6b9aa LW |
1076 | pl022->sgt_tx.nents, DMA_TO_DEVICE); |
1077 | err_tx_sgmap: | |
b7298896 | 1078 | dma_unmap_sg(rxchan->device->dev, pl022->sgt_rx.sgl, |
b1b6b9aa LW |
1079 | pl022->sgt_tx.nents, DMA_FROM_DEVICE); |
1080 | err_rx_sgmap: | |
1081 | sg_free_table(&pl022->sgt_tx); | |
1082 | err_alloc_tx_sg: | |
1083 | sg_free_table(&pl022->sgt_rx); | |
1084 | err_alloc_rx_sg: | |
1085 | return -ENOMEM; | |
1086 | } | |
1087 | ||
1088 | static int __init pl022_dma_probe(struct pl022 *pl022) | |
1089 | { | |
1090 | dma_cap_mask_t mask; | |
1091 | ||
1092 | /* Try to acquire a generic DMA engine slave channel */ | |
1093 | dma_cap_zero(mask); | |
1094 | dma_cap_set(DMA_SLAVE, mask); | |
1095 | /* | |
1096 | * We need both RX and TX channels to do DMA, else do none | |
1097 | * of them. | |
1098 | */ | |
1099 | pl022->dma_rx_channel = dma_request_channel(mask, | |
1100 | pl022->master_info->dma_filter, | |
1101 | pl022->master_info->dma_rx_param); | |
1102 | if (!pl022->dma_rx_channel) { | |
43c64015 | 1103 | dev_dbg(&pl022->adev->dev, "no RX DMA channel!\n"); |
b1b6b9aa LW |
1104 | goto err_no_rxchan; |
1105 | } | |
1106 | ||
1107 | pl022->dma_tx_channel = dma_request_channel(mask, | |
1108 | pl022->master_info->dma_filter, | |
1109 | pl022->master_info->dma_tx_param); | |
1110 | if (!pl022->dma_tx_channel) { | |
43c64015 | 1111 | dev_dbg(&pl022->adev->dev, "no TX DMA channel!\n"); |
b1b6b9aa LW |
1112 | goto err_no_txchan; |
1113 | } | |
1114 | ||
1115 | pl022->dummypage = kmalloc(PAGE_SIZE, GFP_KERNEL); | |
1116 | if (!pl022->dummypage) { | |
43c64015 | 1117 | dev_dbg(&pl022->adev->dev, "no DMA dummypage!\n"); |
b1b6b9aa LW |
1118 | goto err_no_dummypage; |
1119 | } | |
1120 | ||
1121 | dev_info(&pl022->adev->dev, "setup for DMA on RX %s, TX %s\n", | |
1122 | dma_chan_name(pl022->dma_rx_channel), | |
1123 | dma_chan_name(pl022->dma_tx_channel)); | |
1124 | ||
1125 | return 0; | |
1126 | ||
1127 | err_no_dummypage: | |
1128 | dma_release_channel(pl022->dma_tx_channel); | |
1129 | err_no_txchan: | |
1130 | dma_release_channel(pl022->dma_rx_channel); | |
1131 | pl022->dma_rx_channel = NULL; | |
1132 | err_no_rxchan: | |
43c64015 VK |
1133 | dev_err(&pl022->adev->dev, |
1134 | "Failed to work in dma mode, work without dma!\n"); | |
b1b6b9aa LW |
1135 | return -ENODEV; |
1136 | } | |
1137 | ||
1138 | static void terminate_dma(struct pl022 *pl022) | |
1139 | { | |
1140 | struct dma_chan *rxchan = pl022->dma_rx_channel; | |
1141 | struct dma_chan *txchan = pl022->dma_tx_channel; | |
1142 | ||
ecd442fd LW |
1143 | dmaengine_terminate_all(rxchan); |
1144 | dmaengine_terminate_all(txchan); | |
b1b6b9aa LW |
1145 | unmap_free_dma_scatter(pl022); |
1146 | } | |
1147 | ||
1148 | static void pl022_dma_remove(struct pl022 *pl022) | |
1149 | { | |
1150 | if (pl022->busy) | |
1151 | terminate_dma(pl022); | |
1152 | if (pl022->dma_tx_channel) | |
1153 | dma_release_channel(pl022->dma_tx_channel); | |
1154 | if (pl022->dma_rx_channel) | |
1155 | dma_release_channel(pl022->dma_rx_channel); | |
1156 | kfree(pl022->dummypage); | |
1157 | } | |
1158 | ||
1159 | #else | |
1160 | static inline int configure_dma(struct pl022 *pl022) | |
1161 | { | |
1162 | return -ENODEV; | |
1163 | } | |
1164 | ||
1165 | static inline int pl022_dma_probe(struct pl022 *pl022) | |
1166 | { | |
1167 | return 0; | |
1168 | } | |
1169 | ||
1170 | static inline void pl022_dma_remove(struct pl022 *pl022) | |
1171 | { | |
1172 | } | |
1173 | #endif | |
1174 | ||
b43d65f7 LW |
1175 | /** |
1176 | * pl022_interrupt_handler - Interrupt handler for SSP controller | |
1177 | * | |
1178 | * This function handles interrupts generated for an interrupt based transfer. | |
1179 | * If a receive overrun (ROR) interrupt is there then we disable SSP, flag the | |
1180 | * current message's state as STATE_ERROR and schedule the tasklet | |
1181 | * pump_transfers which will do the postprocessing of the current message by | |
1182 | * calling giveback(). Otherwise it reads data from RX FIFO till there is no | |
1183 | * more data, and writes data in TX FIFO till it is not full. If we complete | |
1184 | * the transfer we move to the next transfer and schedule the tasklet. | |
1185 | */ | |
1186 | static irqreturn_t pl022_interrupt_handler(int irq, void *dev_id) | |
1187 | { | |
1188 | struct pl022 *pl022 = dev_id; | |
1189 | struct spi_message *msg = pl022->cur_msg; | |
1190 | u16 irq_status = 0; | |
1191 | u16 flag = 0; | |
1192 | ||
1193 | if (unlikely(!msg)) { | |
1194 | dev_err(&pl022->adev->dev, | |
1195 | "bad message state in interrupt handler"); | |
1196 | /* Never fail */ | |
1197 | return IRQ_HANDLED; | |
1198 | } | |
1199 | ||
1200 | /* Read the Interrupt Status Register */ | |
1201 | irq_status = readw(SSP_MIS(pl022->virtbase)); | |
1202 | ||
1203 | if (unlikely(!irq_status)) | |
1204 | return IRQ_NONE; | |
1205 | ||
b1b6b9aa LW |
1206 | /* |
1207 | * This handles the FIFO interrupts, the timeout | |
1208 | * interrupts are flatly ignored, they cannot be | |
1209 | * trusted. | |
1210 | */ | |
b43d65f7 LW |
1211 | if (unlikely(irq_status & SSP_MIS_MASK_RORMIS)) { |
1212 | /* | |
1213 | * Overrun interrupt - bail out since our Data has been | |
1214 | * corrupted | |
1215 | */ | |
b1b6b9aa | 1216 | dev_err(&pl022->adev->dev, "FIFO overrun\n"); |
b43d65f7 LW |
1217 | if (readw(SSP_SR(pl022->virtbase)) & SSP_SR_MASK_RFF) |
1218 | dev_err(&pl022->adev->dev, | |
1219 | "RXFIFO is full\n"); | |
1220 | if (readw(SSP_SR(pl022->virtbase)) & SSP_SR_MASK_TNF) | |
1221 | dev_err(&pl022->adev->dev, | |
1222 | "TXFIFO is full\n"); | |
1223 | ||
1224 | /* | |
1225 | * Disable and clear interrupts, disable SSP, | |
1226 | * mark message with bad status so it can be | |
1227 | * retried. | |
1228 | */ | |
1229 | writew(DISABLE_ALL_INTERRUPTS, | |
1230 | SSP_IMSC(pl022->virtbase)); | |
1231 | writew(CLEAR_ALL_INTERRUPTS, SSP_ICR(pl022->virtbase)); | |
1232 | writew((readw(SSP_CR1(pl022->virtbase)) & | |
1233 | (~SSP_CR1_MASK_SSE)), SSP_CR1(pl022->virtbase)); | |
1234 | msg->state = STATE_ERROR; | |
1235 | ||
1236 | /* Schedule message queue handler */ | |
1237 | tasklet_schedule(&pl022->pump_transfers); | |
1238 | return IRQ_HANDLED; | |
1239 | } | |
1240 | ||
1241 | readwriter(pl022); | |
1242 | ||
1243 | if ((pl022->tx == pl022->tx_end) && (flag == 0)) { | |
1244 | flag = 1; | |
172289df CB |
1245 | /* Disable Transmit interrupt, enable receive interrupt */ |
1246 | writew((readw(SSP_IMSC(pl022->virtbase)) & | |
1247 | ~SSP_IMSC_MASK_TXIM) | SSP_IMSC_MASK_RXIM, | |
b43d65f7 LW |
1248 | SSP_IMSC(pl022->virtbase)); |
1249 | } | |
1250 | ||
1251 | /* | |
1252 | * Since all transactions must write as much as shall be read, | |
1253 | * we can conclude the entire transaction once RX is complete. | |
1254 | * At this point, all TX will always be finished. | |
1255 | */ | |
1256 | if (pl022->rx >= pl022->rx_end) { | |
1257 | writew(DISABLE_ALL_INTERRUPTS, | |
1258 | SSP_IMSC(pl022->virtbase)); | |
1259 | writew(CLEAR_ALL_INTERRUPTS, SSP_ICR(pl022->virtbase)); | |
1260 | if (unlikely(pl022->rx > pl022->rx_end)) { | |
1261 | dev_warn(&pl022->adev->dev, "read %u surplus " | |
1262 | "bytes (did you request an odd " | |
1263 | "number of bytes on a 16bit bus?)\n", | |
1264 | (u32) (pl022->rx - pl022->rx_end)); | |
1265 | } | |
25985edc | 1266 | /* Update total bytes transferred */ |
b43d65f7 LW |
1267 | msg->actual_length += pl022->cur_transfer->len; |
1268 | if (pl022->cur_transfer->cs_change) | |
1269 | pl022->cur_chip-> | |
1270 | cs_control(SSP_CHIP_DESELECT); | |
1271 | /* Move to next transfer */ | |
1272 | msg->state = next_transfer(pl022); | |
1273 | tasklet_schedule(&pl022->pump_transfers); | |
1274 | return IRQ_HANDLED; | |
1275 | } | |
1276 | ||
1277 | return IRQ_HANDLED; | |
1278 | } | |
1279 | ||
1280 | /** | |
1281 | * This sets up the pointers to memory for the next message to | |
1282 | * send out on the SPI bus. | |
1283 | */ | |
1284 | static int set_up_next_transfer(struct pl022 *pl022, | |
1285 | struct spi_transfer *transfer) | |
1286 | { | |
1287 | int residue; | |
1288 | ||
1289 | /* Sanity check the message for this bus width */ | |
1290 | residue = pl022->cur_transfer->len % pl022->cur_chip->n_bytes; | |
1291 | if (unlikely(residue != 0)) { | |
1292 | dev_err(&pl022->adev->dev, | |
1293 | "message of %u bytes to transmit but the current " | |
1294 | "chip bus has a data width of %u bytes!\n", | |
1295 | pl022->cur_transfer->len, | |
1296 | pl022->cur_chip->n_bytes); | |
1297 | dev_err(&pl022->adev->dev, "skipping this message\n"); | |
1298 | return -EIO; | |
1299 | } | |
1300 | pl022->tx = (void *)transfer->tx_buf; | |
1301 | pl022->tx_end = pl022->tx + pl022->cur_transfer->len; | |
1302 | pl022->rx = (void *)transfer->rx_buf; | |
1303 | pl022->rx_end = pl022->rx + pl022->cur_transfer->len; | |
1304 | pl022->write = | |
1305 | pl022->tx ? pl022->cur_chip->write : WRITING_NULL; | |
1306 | pl022->read = pl022->rx ? pl022->cur_chip->read : READING_NULL; | |
1307 | return 0; | |
1308 | } | |
1309 | ||
1310 | /** | |
b1b6b9aa LW |
1311 | * pump_transfers - Tasklet function which schedules next transfer |
1312 | * when running in interrupt or DMA transfer mode. | |
b43d65f7 LW |
1313 | * @data: SSP driver private data structure |
1314 | * | |
1315 | */ | |
1316 | static void pump_transfers(unsigned long data) | |
1317 | { | |
1318 | struct pl022 *pl022 = (struct pl022 *) data; | |
1319 | struct spi_message *message = NULL; | |
1320 | struct spi_transfer *transfer = NULL; | |
1321 | struct spi_transfer *previous = NULL; | |
1322 | ||
1323 | /* Get current state information */ | |
1324 | message = pl022->cur_msg; | |
1325 | transfer = pl022->cur_transfer; | |
1326 | ||
1327 | /* Handle for abort */ | |
1328 | if (message->state == STATE_ERROR) { | |
1329 | message->status = -EIO; | |
1330 | giveback(pl022); | |
1331 | return; | |
1332 | } | |
1333 | ||
1334 | /* Handle end of message */ | |
1335 | if (message->state == STATE_DONE) { | |
1336 | message->status = 0; | |
1337 | giveback(pl022); | |
1338 | return; | |
1339 | } | |
1340 | ||
1341 | /* Delay if requested at end of transfer before CS change */ | |
1342 | if (message->state == STATE_RUNNING) { | |
1343 | previous = list_entry(transfer->transfer_list.prev, | |
1344 | struct spi_transfer, | |
1345 | transfer_list); | |
1346 | if (previous->delay_usecs) | |
1347 | /* | |
1348 | * FIXME: This runs in interrupt context. | |
1349 | * Is this really smart? | |
1350 | */ | |
1351 | udelay(previous->delay_usecs); | |
1352 | ||
8b8d7191 | 1353 | /* Reselect chip select only if cs_change was requested */ |
b43d65f7 LW |
1354 | if (previous->cs_change) |
1355 | pl022->cur_chip->cs_control(SSP_CHIP_SELECT); | |
1356 | } else { | |
1357 | /* STATE_START */ | |
1358 | message->state = STATE_RUNNING; | |
1359 | } | |
1360 | ||
1361 | if (set_up_next_transfer(pl022, transfer)) { | |
1362 | message->state = STATE_ERROR; | |
1363 | message->status = -EIO; | |
1364 | giveback(pl022); | |
1365 | return; | |
1366 | } | |
1367 | /* Flush the FIFOs and let's go! */ | |
1368 | flush(pl022); | |
b43d65f7 | 1369 | |
b1b6b9aa LW |
1370 | if (pl022->cur_chip->enable_dma) { |
1371 | if (configure_dma(pl022)) { | |
1372 | dev_dbg(&pl022->adev->dev, | |
1373 | "configuration of DMA failed, fall back to interrupt mode\n"); | |
1374 | goto err_config_dma; | |
1375 | } | |
b43d65f7 LW |
1376 | return; |
1377 | } | |
b43d65f7 | 1378 | |
b1b6b9aa | 1379 | err_config_dma: |
172289df CB |
1380 | /* enable all interrupts except RX */ |
1381 | writew(ENABLE_ALL_INTERRUPTS & ~SSP_IMSC_MASK_RXIM, SSP_IMSC(pl022->virtbase)); | |
b43d65f7 LW |
1382 | } |
1383 | ||
b1b6b9aa | 1384 | static void do_interrupt_dma_transfer(struct pl022 *pl022) |
b43d65f7 | 1385 | { |
172289df CB |
1386 | /* |
1387 | * Default is to enable all interrupts except RX - | |
1388 | * this will be enabled once TX is complete | |
1389 | */ | |
1390 | u32 irqflags = ENABLE_ALL_INTERRUPTS & ~SSP_IMSC_MASK_RXIM; | |
b43d65f7 | 1391 | |
8b8d7191 VS |
1392 | /* Enable target chip, if not already active */ |
1393 | if (!pl022->next_msg_cs_active) | |
1394 | pl022->cur_chip->cs_control(SSP_CHIP_SELECT); | |
b43d65f7 | 1395 | |
b43d65f7 LW |
1396 | if (set_up_next_transfer(pl022, pl022->cur_transfer)) { |
1397 | /* Error path */ | |
1398 | pl022->cur_msg->state = STATE_ERROR; | |
1399 | pl022->cur_msg->status = -EIO; | |
1400 | giveback(pl022); | |
1401 | return; | |
1402 | } | |
b1b6b9aa LW |
1403 | /* If we're using DMA, set up DMA here */ |
1404 | if (pl022->cur_chip->enable_dma) { | |
1405 | /* Configure DMA transfer */ | |
1406 | if (configure_dma(pl022)) { | |
1407 | dev_dbg(&pl022->adev->dev, | |
1408 | "configuration of DMA failed, fall back to interrupt mode\n"); | |
1409 | goto err_config_dma; | |
1410 | } | |
1411 | /* Disable interrupts in DMA mode, IRQ from DMA controller */ | |
1412 | irqflags = DISABLE_ALL_INTERRUPTS; | |
1413 | } | |
1414 | err_config_dma: | |
b43d65f7 LW |
1415 | /* Enable SSP, turn on interrupts */ |
1416 | writew((readw(SSP_CR1(pl022->virtbase)) | SSP_CR1_MASK_SSE), | |
1417 | SSP_CR1(pl022->virtbase)); | |
b1b6b9aa | 1418 | writew(irqflags, SSP_IMSC(pl022->virtbase)); |
b43d65f7 LW |
1419 | } |
1420 | ||
b1b6b9aa | 1421 | static void do_polling_transfer(struct pl022 *pl022) |
b43d65f7 | 1422 | { |
b43d65f7 LW |
1423 | struct spi_message *message = NULL; |
1424 | struct spi_transfer *transfer = NULL; | |
1425 | struct spi_transfer *previous = NULL; | |
1426 | struct chip_data *chip; | |
a18c266f | 1427 | unsigned long time, timeout; |
b43d65f7 LW |
1428 | |
1429 | chip = pl022->cur_chip; | |
1430 | message = pl022->cur_msg; | |
1431 | ||
1432 | while (message->state != STATE_DONE) { | |
1433 | /* Handle for abort */ | |
1434 | if (message->state == STATE_ERROR) | |
1435 | break; | |
1436 | transfer = pl022->cur_transfer; | |
1437 | ||
1438 | /* Delay if requested at end of transfer */ | |
1439 | if (message->state == STATE_RUNNING) { | |
1440 | previous = | |
1441 | list_entry(transfer->transfer_list.prev, | |
1442 | struct spi_transfer, transfer_list); | |
1443 | if (previous->delay_usecs) | |
1444 | udelay(previous->delay_usecs); | |
1445 | if (previous->cs_change) | |
1446 | pl022->cur_chip->cs_control(SSP_CHIP_SELECT); | |
1447 | } else { | |
1448 | /* STATE_START */ | |
1449 | message->state = STATE_RUNNING; | |
8b8d7191 VS |
1450 | if (!pl022->next_msg_cs_active) |
1451 | pl022->cur_chip->cs_control(SSP_CHIP_SELECT); | |
b43d65f7 LW |
1452 | } |
1453 | ||
1454 | /* Configuration Changing Per Transfer */ | |
1455 | if (set_up_next_transfer(pl022, transfer)) { | |
1456 | /* Error path */ | |
1457 | message->state = STATE_ERROR; | |
1458 | break; | |
1459 | } | |
1460 | /* Flush FIFOs and enable SSP */ | |
1461 | flush(pl022); | |
1462 | writew((readw(SSP_CR1(pl022->virtbase)) | SSP_CR1_MASK_SSE), | |
1463 | SSP_CR1(pl022->virtbase)); | |
1464 | ||
556f4aeb | 1465 | dev_dbg(&pl022->adev->dev, "polling transfer ongoing ...\n"); |
a18c266f MT |
1466 | |
1467 | timeout = jiffies + msecs_to_jiffies(SPI_POLLING_TIMEOUT); | |
1468 | while (pl022->tx < pl022->tx_end || pl022->rx < pl022->rx_end) { | |
1469 | time = jiffies; | |
b43d65f7 | 1470 | readwriter(pl022); |
a18c266f MT |
1471 | if (time_after(time, timeout)) { |
1472 | dev_warn(&pl022->adev->dev, | |
1473 | "%s: timeout!\n", __func__); | |
1474 | message->state = STATE_ERROR; | |
1475 | goto out; | |
1476 | } | |
521999bd | 1477 | cpu_relax(); |
a18c266f | 1478 | } |
b43d65f7 | 1479 | |
25985edc | 1480 | /* Update total byte transferred */ |
b43d65f7 LW |
1481 | message->actual_length += pl022->cur_transfer->len; |
1482 | if (pl022->cur_transfer->cs_change) | |
1483 | pl022->cur_chip->cs_control(SSP_CHIP_DESELECT); | |
1484 | /* Move to next transfer */ | |
1485 | message->state = next_transfer(pl022); | |
1486 | } | |
a18c266f | 1487 | out: |
b43d65f7 LW |
1488 | /* Handle end of message */ |
1489 | if (message->state == STATE_DONE) | |
1490 | message->status = 0; | |
1491 | else | |
1492 | message->status = -EIO; | |
1493 | ||
1494 | giveback(pl022); | |
1495 | return; | |
1496 | } | |
1497 | ||
1498 | /** | |
1499 | * pump_messages - Workqueue function which processes spi message queue | |
1500 | * @data: pointer to private data of SSP driver | |
1501 | * | |
1502 | * This function checks if there is any spi message in the queue that | |
1503 | * needs processing and delegate control to appropriate function | |
b1b6b9aa | 1504 | * do_polling_transfer()/do_interrupt_dma_transfer() |
b43d65f7 LW |
1505 | * based on the kind of the transfer |
1506 | * | |
1507 | */ | |
1508 | static void pump_messages(struct work_struct *work) | |
1509 | { | |
1510 | struct pl022 *pl022 = | |
1511 | container_of(work, struct pl022, pump_messages); | |
1512 | unsigned long flags; | |
d4b6af2e | 1513 | bool was_busy = false; |
b43d65f7 LW |
1514 | |
1515 | /* Lock queue and check for queue work */ | |
1516 | spin_lock_irqsave(&pl022->queue_lock, flags); | |
5e8b821d | 1517 | if (list_empty(&pl022->queue) || !pl022->running) { |
0ad2deea VS |
1518 | if (pl022->busy) { |
1519 | /* nothing more to do - disable spi/ssp and power off */ | |
1520 | writew((readw(SSP_CR1(pl022->virtbase)) & | |
1521 | (~SSP_CR1_MASK_SSE)), SSP_CR1(pl022->virtbase)); | |
53e4acea CB |
1522 | |
1523 | if (pl022->master_info->autosuspend_delay > 0) { | |
1524 | pm_runtime_mark_last_busy(&pl022->adev->dev); | |
1525 | pm_runtime_put_autosuspend(&pl022->adev->dev); | |
1526 | } else { | |
1527 | pm_runtime_put(&pl022->adev->dev); | |
1528 | } | |
0ad2deea | 1529 | } |
dec5a581 | 1530 | pl022->busy = false; |
b43d65f7 LW |
1531 | spin_unlock_irqrestore(&pl022->queue_lock, flags); |
1532 | return; | |
1533 | } | |
d4b6af2e | 1534 | |
b43d65f7 LW |
1535 | /* Make sure we are not already running a message */ |
1536 | if (pl022->cur_msg) { | |
1537 | spin_unlock_irqrestore(&pl022->queue_lock, flags); | |
1538 | return; | |
1539 | } | |
1540 | /* Extract head of queue */ | |
1541 | pl022->cur_msg = | |
1542 | list_entry(pl022->queue.next, struct spi_message, queue); | |
1543 | ||
1544 | list_del_init(&pl022->cur_msg->queue); | |
d4b6af2e CB |
1545 | if (pl022->busy) |
1546 | was_busy = true; | |
1547 | else | |
1548 | pl022->busy = true; | |
b43d65f7 LW |
1549 | spin_unlock_irqrestore(&pl022->queue_lock, flags); |
1550 | ||
1551 | /* Initial message state */ | |
1552 | pl022->cur_msg->state = STATE_START; | |
1553 | pl022->cur_transfer = list_entry(pl022->cur_msg->transfers.next, | |
f1e45f86 | 1554 | struct spi_transfer, transfer_list); |
b43d65f7 LW |
1555 | |
1556 | /* Setup the SPI using the per chip configuration */ | |
1557 | pl022->cur_chip = spi_get_ctldata(pl022->cur_msg->spi); | |
d4b6af2e CB |
1558 | if (!was_busy) |
1559 | /* | |
1560 | * We enable the core voltage and clocks here, then the clocks | |
1561 | * and core will be disabled when this workqueue is run again | |
1562 | * and there is no more work to be done. | |
1563 | */ | |
1564 | pm_runtime_get_sync(&pl022->adev->dev); | |
1565 | ||
b43d65f7 LW |
1566 | restore_state(pl022); |
1567 | flush(pl022); | |
1568 | ||
1569 | if (pl022->cur_chip->xfer_type == POLLING_TRANSFER) | |
1570 | do_polling_transfer(pl022); | |
b43d65f7 | 1571 | else |
b1b6b9aa | 1572 | do_interrupt_dma_transfer(pl022); |
b43d65f7 LW |
1573 | } |
1574 | ||
b43d65f7 LW |
1575 | static int __init init_queue(struct pl022 *pl022) |
1576 | { | |
1577 | INIT_LIST_HEAD(&pl022->queue); | |
1578 | spin_lock_init(&pl022->queue_lock); | |
1579 | ||
5e8b821d | 1580 | pl022->running = false; |
dec5a581 | 1581 | pl022->busy = false; |
b43d65f7 | 1582 | |
f1e45f86 VK |
1583 | tasklet_init(&pl022->pump_transfers, pump_transfers, |
1584 | (unsigned long)pl022); | |
b43d65f7 LW |
1585 | |
1586 | INIT_WORK(&pl022->pump_messages, pump_messages); | |
1587 | pl022->workqueue = create_singlethread_workqueue( | |
1588 | dev_name(pl022->master->dev.parent)); | |
1589 | if (pl022->workqueue == NULL) | |
1590 | return -EBUSY; | |
1591 | ||
1592 | return 0; | |
1593 | } | |
1594 | ||
b43d65f7 LW |
1595 | static int start_queue(struct pl022 *pl022) |
1596 | { | |
1597 | unsigned long flags; | |
1598 | ||
1599 | spin_lock_irqsave(&pl022->queue_lock, flags); | |
1600 | ||
5e8b821d | 1601 | if (pl022->running || pl022->busy) { |
b43d65f7 LW |
1602 | spin_unlock_irqrestore(&pl022->queue_lock, flags); |
1603 | return -EBUSY; | |
1604 | } | |
1605 | ||
5e8b821d | 1606 | pl022->running = true; |
b43d65f7 LW |
1607 | pl022->cur_msg = NULL; |
1608 | pl022->cur_transfer = NULL; | |
1609 | pl022->cur_chip = NULL; | |
8b8d7191 | 1610 | pl022->next_msg_cs_active = false; |
b43d65f7 LW |
1611 | spin_unlock_irqrestore(&pl022->queue_lock, flags); |
1612 | ||
1613 | queue_work(pl022->workqueue, &pl022->pump_messages); | |
1614 | ||
1615 | return 0; | |
1616 | } | |
1617 | ||
b43d65f7 LW |
1618 | static int stop_queue(struct pl022 *pl022) |
1619 | { | |
1620 | unsigned long flags; | |
1621 | unsigned limit = 500; | |
1622 | int status = 0; | |
1623 | ||
1624 | spin_lock_irqsave(&pl022->queue_lock, flags); | |
1625 | ||
1626 | /* This is a bit lame, but is optimized for the common execution path. | |
1627 | * A wait_queue on the pl022->busy could be used, but then the common | |
1628 | * execution path (pump_messages) would be required to call wake_up or | |
1629 | * friends on every SPI message. Do this instead */ | |
850a28ec | 1630 | while ((!list_empty(&pl022->queue) || pl022->busy) && limit--) { |
b43d65f7 LW |
1631 | spin_unlock_irqrestore(&pl022->queue_lock, flags); |
1632 | msleep(10); | |
1633 | spin_lock_irqsave(&pl022->queue_lock, flags); | |
1634 | } | |
1635 | ||
1636 | if (!list_empty(&pl022->queue) || pl022->busy) | |
1637 | status = -EBUSY; | |
5e8b821d LW |
1638 | else |
1639 | pl022->running = false; | |
b43d65f7 LW |
1640 | |
1641 | spin_unlock_irqrestore(&pl022->queue_lock, flags); | |
1642 | ||
1643 | return status; | |
1644 | } | |
1645 | ||
1646 | static int destroy_queue(struct pl022 *pl022) | |
1647 | { | |
1648 | int status; | |
1649 | ||
1650 | status = stop_queue(pl022); | |
1651 | /* we are unloading the module or failing to load (only two calls | |
1652 | * to this routine), and neither call can handle a return value. | |
1653 | * However, destroy_workqueue calls flush_workqueue, and that will | |
1654 | * block until all work is done. If the reason that stop_queue | |
1655 | * timed out is that the work will never finish, then it does no | |
1656 | * good to call destroy_workqueue, so return anyway. */ | |
1657 | if (status != 0) | |
1658 | return status; | |
1659 | ||
1660 | destroy_workqueue(pl022->workqueue); | |
1661 | ||
1662 | return 0; | |
1663 | } | |
1664 | ||
1665 | static int verify_controller_parameters(struct pl022 *pl022, | |
f9d629c7 | 1666 | struct pl022_config_chip const *chip_info) |
b43d65f7 | 1667 | { |
b43d65f7 LW |
1668 | if ((chip_info->iface < SSP_INTERFACE_MOTOROLA_SPI) |
1669 | || (chip_info->iface > SSP_INTERFACE_UNIDIRECTIONAL)) { | |
5a1c98be | 1670 | dev_err(&pl022->adev->dev, |
b43d65f7 LW |
1671 | "interface is configured incorrectly\n"); |
1672 | return -EINVAL; | |
1673 | } | |
1674 | if ((chip_info->iface == SSP_INTERFACE_UNIDIRECTIONAL) && | |
1675 | (!pl022->vendor->unidir)) { | |
5a1c98be | 1676 | dev_err(&pl022->adev->dev, |
b43d65f7 LW |
1677 | "unidirectional mode not supported in this " |
1678 | "hardware version\n"); | |
1679 | return -EINVAL; | |
1680 | } | |
1681 | if ((chip_info->hierarchy != SSP_MASTER) | |
1682 | && (chip_info->hierarchy != SSP_SLAVE)) { | |
5a1c98be | 1683 | dev_err(&pl022->adev->dev, |
b43d65f7 LW |
1684 | "hierarchy is configured incorrectly\n"); |
1685 | return -EINVAL; | |
1686 | } | |
b43d65f7 LW |
1687 | if ((chip_info->com_mode != INTERRUPT_TRANSFER) |
1688 | && (chip_info->com_mode != DMA_TRANSFER) | |
1689 | && (chip_info->com_mode != POLLING_TRANSFER)) { | |
5a1c98be | 1690 | dev_err(&pl022->adev->dev, |
b43d65f7 LW |
1691 | "Communication mode is configured incorrectly\n"); |
1692 | return -EINVAL; | |
1693 | } | |
78b2b911 LW |
1694 | switch (chip_info->rx_lev_trig) { |
1695 | case SSP_RX_1_OR_MORE_ELEM: | |
1696 | case SSP_RX_4_OR_MORE_ELEM: | |
1697 | case SSP_RX_8_OR_MORE_ELEM: | |
1698 | /* These are always OK, all variants can handle this */ | |
1699 | break; | |
1700 | case SSP_RX_16_OR_MORE_ELEM: | |
1701 | if (pl022->vendor->fifodepth < 16) { | |
1702 | dev_err(&pl022->adev->dev, | |
1703 | "RX FIFO Trigger Level is configured incorrectly\n"); | |
1704 | return -EINVAL; | |
1705 | } | |
1706 | break; | |
1707 | case SSP_RX_32_OR_MORE_ELEM: | |
1708 | if (pl022->vendor->fifodepth < 32) { | |
1709 | dev_err(&pl022->adev->dev, | |
1710 | "RX FIFO Trigger Level is configured incorrectly\n"); | |
1711 | return -EINVAL; | |
1712 | } | |
1713 | break; | |
1714 | default: | |
5a1c98be | 1715 | dev_err(&pl022->adev->dev, |
b43d65f7 LW |
1716 | "RX FIFO Trigger Level is configured incorrectly\n"); |
1717 | return -EINVAL; | |
78b2b911 | 1718 | break; |
b43d65f7 | 1719 | } |
78b2b911 LW |
1720 | switch (chip_info->tx_lev_trig) { |
1721 | case SSP_TX_1_OR_MORE_EMPTY_LOC: | |
1722 | case SSP_TX_4_OR_MORE_EMPTY_LOC: | |
1723 | case SSP_TX_8_OR_MORE_EMPTY_LOC: | |
1724 | /* These are always OK, all variants can handle this */ | |
1725 | break; | |
1726 | case SSP_TX_16_OR_MORE_EMPTY_LOC: | |
1727 | if (pl022->vendor->fifodepth < 16) { | |
1728 | dev_err(&pl022->adev->dev, | |
1729 | "TX FIFO Trigger Level is configured incorrectly\n"); | |
1730 | return -EINVAL; | |
1731 | } | |
1732 | break; | |
1733 | case SSP_TX_32_OR_MORE_EMPTY_LOC: | |
1734 | if (pl022->vendor->fifodepth < 32) { | |
1735 | dev_err(&pl022->adev->dev, | |
1736 | "TX FIFO Trigger Level is configured incorrectly\n"); | |
1737 | return -EINVAL; | |
1738 | } | |
1739 | break; | |
1740 | default: | |
5a1c98be | 1741 | dev_err(&pl022->adev->dev, |
b43d65f7 LW |
1742 | "TX FIFO Trigger Level is configured incorrectly\n"); |
1743 | return -EINVAL; | |
78b2b911 | 1744 | break; |
b43d65f7 | 1745 | } |
b43d65f7 LW |
1746 | if (chip_info->iface == SSP_INTERFACE_NATIONAL_MICROWIRE) { |
1747 | if ((chip_info->ctrl_len < SSP_BITS_4) | |
1748 | || (chip_info->ctrl_len > SSP_BITS_32)) { | |
5a1c98be | 1749 | dev_err(&pl022->adev->dev, |
b43d65f7 LW |
1750 | "CTRL LEN is configured incorrectly\n"); |
1751 | return -EINVAL; | |
1752 | } | |
1753 | if ((chip_info->wait_state != SSP_MWIRE_WAIT_ZERO) | |
1754 | && (chip_info->wait_state != SSP_MWIRE_WAIT_ONE)) { | |
5a1c98be | 1755 | dev_err(&pl022->adev->dev, |
b43d65f7 LW |
1756 | "Wait State is configured incorrectly\n"); |
1757 | return -EINVAL; | |
1758 | } | |
556f4aeb LW |
1759 | /* Half duplex is only available in the ST Micro version */ |
1760 | if (pl022->vendor->extended_cr) { | |
1761 | if ((chip_info->duplex != | |
1762 | SSP_MICROWIRE_CHANNEL_FULL_DUPLEX) | |
1763 | && (chip_info->duplex != | |
4a4fd471 | 1764 | SSP_MICROWIRE_CHANNEL_HALF_DUPLEX)) { |
5a1c98be | 1765 | dev_err(&pl022->adev->dev, |
556f4aeb LW |
1766 | "Microwire duplex mode is configured incorrectly\n"); |
1767 | return -EINVAL; | |
4a4fd471 | 1768 | } |
556f4aeb LW |
1769 | } else { |
1770 | if (chip_info->duplex != SSP_MICROWIRE_CHANNEL_FULL_DUPLEX) | |
5a1c98be | 1771 | dev_err(&pl022->adev->dev, |
556f4aeb LW |
1772 | "Microwire half duplex mode requested," |
1773 | " but this is only available in the" | |
1774 | " ST version of PL022\n"); | |
b43d65f7 LW |
1775 | return -EINVAL; |
1776 | } | |
1777 | } | |
b43d65f7 LW |
1778 | return 0; |
1779 | } | |
1780 | ||
1781 | /** | |
1782 | * pl022_transfer - transfer function registered to SPI master framework | |
1783 | * @spi: spi device which is requesting transfer | |
1784 | * @msg: spi message which is to handled is queued to driver queue | |
1785 | * | |
1786 | * This function is registered to the SPI framework for this SPI master | |
1787 | * controller. It will queue the spi_message in the queue of driver if | |
1788 | * the queue is not stopped and return. | |
1789 | */ | |
1790 | static int pl022_transfer(struct spi_device *spi, struct spi_message *msg) | |
1791 | { | |
1792 | struct pl022 *pl022 = spi_master_get_devdata(spi->master); | |
1793 | unsigned long flags; | |
1794 | ||
1795 | spin_lock_irqsave(&pl022->queue_lock, flags); | |
1796 | ||
5e8b821d | 1797 | if (!pl022->running) { |
b43d65f7 LW |
1798 | spin_unlock_irqrestore(&pl022->queue_lock, flags); |
1799 | return -ESHUTDOWN; | |
1800 | } | |
1801 | msg->actual_length = 0; | |
1802 | msg->status = -EINPROGRESS; | |
1803 | msg->state = STATE_START; | |
1804 | ||
1805 | list_add_tail(&msg->queue, &pl022->queue); | |
5e8b821d | 1806 | if (pl022->running && !pl022->busy) |
b43d65f7 LW |
1807 | queue_work(pl022->workqueue, &pl022->pump_messages); |
1808 | ||
1809 | spin_unlock_irqrestore(&pl022->queue_lock, flags); | |
1810 | return 0; | |
1811 | } | |
1812 | ||
0379b2a3 VK |
1813 | static inline u32 spi_rate(u32 rate, u16 cpsdvsr, u16 scr) |
1814 | { | |
1815 | return rate / (cpsdvsr * (1 + scr)); | |
1816 | } | |
1817 | ||
1818 | static int calculate_effective_freq(struct pl022 *pl022, int freq, struct | |
1819 | ssp_clock_params * clk_freq) | |
b43d65f7 LW |
1820 | { |
1821 | /* Lets calculate the frequency parameters */ | |
0379b2a3 VK |
1822 | u16 cpsdvsr = CPSDVR_MIN, scr = SCR_MIN; |
1823 | u32 rate, max_tclk, min_tclk, best_freq = 0, best_cpsdvsr = 0, | |
1824 | best_scr = 0, tmp, found = 0; | |
b43d65f7 LW |
1825 | |
1826 | rate = clk_get_rate(pl022->clk); | |
1827 | /* cpsdvscr = 2 & scr 0 */ | |
0379b2a3 | 1828 | max_tclk = spi_rate(rate, CPSDVR_MIN, SCR_MIN); |
b43d65f7 | 1829 | /* cpsdvsr = 254 & scr = 255 */ |
0379b2a3 VK |
1830 | min_tclk = spi_rate(rate, CPSDVR_MAX, SCR_MAX); |
1831 | ||
1832 | if (!((freq <= max_tclk) && (freq >= min_tclk))) { | |
b43d65f7 LW |
1833 | dev_err(&pl022->adev->dev, |
1834 | "controller data is incorrect: out of range frequency"); | |
1835 | return -EINVAL; | |
1836 | } | |
0379b2a3 VK |
1837 | |
1838 | /* | |
1839 | * best_freq will give closest possible available rate (<= requested | |
1840 | * freq) for all values of scr & cpsdvsr. | |
1841 | */ | |
1842 | while ((cpsdvsr <= CPSDVR_MAX) && !found) { | |
1843 | while (scr <= SCR_MAX) { | |
1844 | tmp = spi_rate(rate, cpsdvsr, scr); | |
1845 | ||
1846 | if (tmp > freq) | |
1847 | scr++; | |
1848 | /* | |
1849 | * If found exact value, update and break. | |
1850 | * If found more closer value, update and continue. | |
1851 | */ | |
1852 | else if ((tmp == freq) || (tmp > best_freq)) { | |
1853 | best_freq = tmp; | |
1854 | best_cpsdvsr = cpsdvsr; | |
1855 | best_scr = scr; | |
1856 | ||
1857 | if (tmp == freq) | |
1858 | break; | |
1859 | } | |
1860 | scr++; | |
1861 | } | |
1862 | cpsdvsr += 2; | |
1863 | scr = SCR_MIN; | |
1864 | } | |
1865 | ||
1866 | clk_freq->cpsdvsr = (u8) (best_cpsdvsr & 0xFF); | |
1867 | clk_freq->scr = (u8) (best_scr & 0xFF); | |
1868 | dev_dbg(&pl022->adev->dev, | |
1869 | "SSP Target Frequency is: %u, Effective Frequency is %u\n", | |
1870 | freq, best_freq); | |
1871 | dev_dbg(&pl022->adev->dev, "SSP cpsdvsr = %d, scr = %d\n", | |
1872 | clk_freq->cpsdvsr, clk_freq->scr); | |
1873 | ||
b43d65f7 LW |
1874 | return 0; |
1875 | } | |
1876 | ||
f9d629c7 LW |
1877 | /* |
1878 | * A piece of default chip info unless the platform | |
1879 | * supplies it. | |
1880 | */ | |
1881 | static const struct pl022_config_chip pl022_default_chip_info = { | |
1882 | .com_mode = POLLING_TRANSFER, | |
1883 | .iface = SSP_INTERFACE_MOTOROLA_SPI, | |
1884 | .hierarchy = SSP_SLAVE, | |
1885 | .slave_tx_disable = DO_NOT_DRIVE_TX, | |
1886 | .rx_lev_trig = SSP_RX_1_OR_MORE_ELEM, | |
1887 | .tx_lev_trig = SSP_TX_1_OR_MORE_EMPTY_LOC, | |
1888 | .ctrl_len = SSP_BITS_8, | |
1889 | .wait_state = SSP_MWIRE_WAIT_ZERO, | |
1890 | .duplex = SSP_MICROWIRE_CHANNEL_FULL_DUPLEX, | |
1891 | .cs_control = null_cs_control, | |
1892 | }; | |
1893 | ||
b43d65f7 LW |
1894 | /** |
1895 | * pl022_setup - setup function registered to SPI master framework | |
1896 | * @spi: spi device which is requesting setup | |
1897 | * | |
1898 | * This function is registered to the SPI framework for this SPI master | |
1899 | * controller. If it is the first time when setup is called by this device, | |
1900 | * this function will initialize the runtime state for this chip and save | |
1901 | * the same in the device structure. Else it will update the runtime info | |
1902 | * with the updated chip info. Nothing is really being written to the | |
1903 | * controller hardware here, that is not done until the actual transfer | |
1904 | * commence. | |
1905 | */ | |
b43d65f7 LW |
1906 | static int pl022_setup(struct spi_device *spi) |
1907 | { | |
f9d629c7 | 1908 | struct pl022_config_chip const *chip_info; |
b43d65f7 | 1909 | struct chip_data *chip; |
c4a47843 | 1910 | struct ssp_clock_params clk_freq = { .cpsdvsr = 0, .scr = 0}; |
b43d65f7 LW |
1911 | int status = 0; |
1912 | struct pl022 *pl022 = spi_master_get_devdata(spi->master); | |
bde435a9 KW |
1913 | unsigned int bits = spi->bits_per_word; |
1914 | u32 tmp; | |
b43d65f7 LW |
1915 | |
1916 | if (!spi->max_speed_hz) | |
1917 | return -EINVAL; | |
1918 | ||
1919 | /* Get controller_state if one is supplied */ | |
1920 | chip = spi_get_ctldata(spi); | |
1921 | ||
1922 | if (chip == NULL) { | |
1923 | chip = kzalloc(sizeof(struct chip_data), GFP_KERNEL); | |
1924 | if (!chip) { | |
1925 | dev_err(&spi->dev, | |
1926 | "cannot allocate controller state\n"); | |
1927 | return -ENOMEM; | |
1928 | } | |
1929 | dev_dbg(&spi->dev, | |
1930 | "allocated memory for controller's runtime state\n"); | |
1931 | } | |
1932 | ||
1933 | /* Get controller data if one is supplied */ | |
1934 | chip_info = spi->controller_data; | |
1935 | ||
1936 | if (chip_info == NULL) { | |
f9d629c7 | 1937 | chip_info = &pl022_default_chip_info; |
b43d65f7 LW |
1938 | /* spi_board_info.controller_data not is supplied */ |
1939 | dev_dbg(&spi->dev, | |
1940 | "using default controller_data settings\n"); | |
f9d629c7 | 1941 | } else |
b43d65f7 LW |
1942 | dev_dbg(&spi->dev, |
1943 | "using user supplied controller_data settings\n"); | |
b43d65f7 LW |
1944 | |
1945 | /* | |
1946 | * We can override with custom divisors, else we use the board | |
1947 | * frequency setting | |
1948 | */ | |
1949 | if ((0 == chip_info->clk_freq.cpsdvsr) | |
1950 | && (0 == chip_info->clk_freq.scr)) { | |
1951 | status = calculate_effective_freq(pl022, | |
1952 | spi->max_speed_hz, | |
f9d629c7 | 1953 | &clk_freq); |
b43d65f7 LW |
1954 | if (status < 0) |
1955 | goto err_config_params; | |
1956 | } else { | |
f9d629c7 LW |
1957 | memcpy(&clk_freq, &chip_info->clk_freq, sizeof(clk_freq)); |
1958 | if ((clk_freq.cpsdvsr % 2) != 0) | |
1959 | clk_freq.cpsdvsr = | |
1960 | clk_freq.cpsdvsr - 1; | |
b43d65f7 | 1961 | } |
f9d629c7 LW |
1962 | if ((clk_freq.cpsdvsr < CPSDVR_MIN) |
1963 | || (clk_freq.cpsdvsr > CPSDVR_MAX)) { | |
e3f88ae9 | 1964 | status = -EINVAL; |
f9d629c7 LW |
1965 | dev_err(&spi->dev, |
1966 | "cpsdvsr is configured incorrectly\n"); | |
1967 | goto err_config_params; | |
1968 | } | |
1969 | ||
b43d65f7 LW |
1970 | status = verify_controller_parameters(pl022, chip_info); |
1971 | if (status) { | |
1972 | dev_err(&spi->dev, "controller data is incorrect"); | |
1973 | goto err_config_params; | |
1974 | } | |
f9d629c7 | 1975 | |
083be3f0 LW |
1976 | pl022->rx_lev_trig = chip_info->rx_lev_trig; |
1977 | pl022->tx_lev_trig = chip_info->tx_lev_trig; | |
1978 | ||
b43d65f7 LW |
1979 | /* Now set controller state based on controller data */ |
1980 | chip->xfer_type = chip_info->com_mode; | |
f9d629c7 LW |
1981 | if (!chip_info->cs_control) { |
1982 | chip->cs_control = null_cs_control; | |
1983 | dev_warn(&spi->dev, | |
1984 | "chip select function is NULL for this chip\n"); | |
1985 | } else | |
1986 | chip->cs_control = chip_info->cs_control; | |
b43d65f7 | 1987 | |
bde435a9 KW |
1988 | if (bits <= 3) { |
1989 | /* PL022 doesn't support less than 4-bits */ | |
1990 | status = -ENOTSUPP; | |
1991 | goto err_config_params; | |
1992 | } else if (bits <= 8) { | |
1993 | dev_dbg(&spi->dev, "4 <= n <=8 bits per word\n"); | |
b43d65f7 LW |
1994 | chip->n_bytes = 1; |
1995 | chip->read = READING_U8; | |
1996 | chip->write = WRITING_U8; | |
bde435a9 | 1997 | } else if (bits <= 16) { |
b43d65f7 LW |
1998 | dev_dbg(&spi->dev, "9 <= n <= 16 bits per word\n"); |
1999 | chip->n_bytes = 2; | |
2000 | chip->read = READING_U16; | |
2001 | chip->write = WRITING_U16; | |
2002 | } else { | |
2003 | if (pl022->vendor->max_bpw >= 32) { | |
2004 | dev_dbg(&spi->dev, "17 <= n <= 32 bits per word\n"); | |
2005 | chip->n_bytes = 4; | |
2006 | chip->read = READING_U32; | |
2007 | chip->write = WRITING_U32; | |
2008 | } else { | |
2009 | dev_err(&spi->dev, | |
2010 | "illegal data size for this controller!\n"); | |
2011 | dev_err(&spi->dev, | |
2012 | "a standard pl022 can only handle " | |
2013 | "1 <= n <= 16 bit words\n"); | |
bde435a9 | 2014 | status = -ENOTSUPP; |
b43d65f7 LW |
2015 | goto err_config_params; |
2016 | } | |
2017 | } | |
2018 | ||
2019 | /* Now Initialize all register settings required for this chip */ | |
2020 | chip->cr0 = 0; | |
2021 | chip->cr1 = 0; | |
2022 | chip->dmacr = 0; | |
2023 | chip->cpsr = 0; | |
2024 | if ((chip_info->com_mode == DMA_TRANSFER) | |
2025 | && ((pl022->master_info)->enable_dma)) { | |
b1b6b9aa | 2026 | chip->enable_dma = true; |
b43d65f7 | 2027 | dev_dbg(&spi->dev, "DMA mode set in controller state\n"); |
b43d65f7 LW |
2028 | SSP_WRITE_BITS(chip->dmacr, SSP_DMA_ENABLED, |
2029 | SSP_DMACR_MASK_RXDMAE, 0); | |
2030 | SSP_WRITE_BITS(chip->dmacr, SSP_DMA_ENABLED, | |
2031 | SSP_DMACR_MASK_TXDMAE, 1); | |
2032 | } else { | |
b1b6b9aa | 2033 | chip->enable_dma = false; |
b43d65f7 LW |
2034 | dev_dbg(&spi->dev, "DMA mode NOT set in controller state\n"); |
2035 | SSP_WRITE_BITS(chip->dmacr, SSP_DMA_DISABLED, | |
2036 | SSP_DMACR_MASK_RXDMAE, 0); | |
2037 | SSP_WRITE_BITS(chip->dmacr, SSP_DMA_DISABLED, | |
2038 | SSP_DMACR_MASK_TXDMAE, 1); | |
2039 | } | |
2040 | ||
f9d629c7 | 2041 | chip->cpsr = clk_freq.cpsdvsr; |
b43d65f7 | 2042 | |
556f4aeb LW |
2043 | /* Special setup for the ST micro extended control registers */ |
2044 | if (pl022->vendor->extended_cr) { | |
bde435a9 KW |
2045 | u32 etx; |
2046 | ||
781c7b12 LW |
2047 | if (pl022->vendor->pl023) { |
2048 | /* These bits are only in the PL023 */ | |
2049 | SSP_WRITE_BITS(chip->cr1, chip_info->clkdelay, | |
2050 | SSP_CR1_MASK_FBCLKDEL_ST, 13); | |
2051 | } else { | |
2052 | /* These bits are in the PL022 but not PL023 */ | |
2053 | SSP_WRITE_BITS(chip->cr0, chip_info->duplex, | |
2054 | SSP_CR0_MASK_HALFDUP_ST, 5); | |
2055 | SSP_WRITE_BITS(chip->cr0, chip_info->ctrl_len, | |
2056 | SSP_CR0_MASK_CSS_ST, 16); | |
2057 | SSP_WRITE_BITS(chip->cr0, chip_info->iface, | |
2058 | SSP_CR0_MASK_FRF_ST, 21); | |
2059 | SSP_WRITE_BITS(chip->cr1, chip_info->wait_state, | |
2060 | SSP_CR1_MASK_MWAIT_ST, 6); | |
2061 | } | |
bde435a9 | 2062 | SSP_WRITE_BITS(chip->cr0, bits - 1, |
556f4aeb | 2063 | SSP_CR0_MASK_DSS_ST, 0); |
bde435a9 KW |
2064 | |
2065 | if (spi->mode & SPI_LSB_FIRST) { | |
2066 | tmp = SSP_RX_LSB; | |
2067 | etx = SSP_TX_LSB; | |
2068 | } else { | |
2069 | tmp = SSP_RX_MSB; | |
2070 | etx = SSP_TX_MSB; | |
2071 | } | |
2072 | SSP_WRITE_BITS(chip->cr1, tmp, SSP_CR1_MASK_RENDN_ST, 4); | |
2073 | SSP_WRITE_BITS(chip->cr1, etx, SSP_CR1_MASK_TENDN_ST, 5); | |
556f4aeb LW |
2074 | SSP_WRITE_BITS(chip->cr1, chip_info->rx_lev_trig, |
2075 | SSP_CR1_MASK_RXIFLSEL_ST, 7); | |
2076 | SSP_WRITE_BITS(chip->cr1, chip_info->tx_lev_trig, | |
2077 | SSP_CR1_MASK_TXIFLSEL_ST, 10); | |
2078 | } else { | |
bde435a9 | 2079 | SSP_WRITE_BITS(chip->cr0, bits - 1, |
556f4aeb LW |
2080 | SSP_CR0_MASK_DSS, 0); |
2081 | SSP_WRITE_BITS(chip->cr0, chip_info->iface, | |
2082 | SSP_CR0_MASK_FRF, 4); | |
2083 | } | |
bde435a9 | 2084 | |
556f4aeb | 2085 | /* Stuff that is common for all versions */ |
bde435a9 KW |
2086 | if (spi->mode & SPI_CPOL) |
2087 | tmp = SSP_CLK_POL_IDLE_HIGH; | |
2088 | else | |
2089 | tmp = SSP_CLK_POL_IDLE_LOW; | |
2090 | SSP_WRITE_BITS(chip->cr0, tmp, SSP_CR0_MASK_SPO, 6); | |
2091 | ||
2092 | if (spi->mode & SPI_CPHA) | |
2093 | tmp = SSP_CLK_SECOND_EDGE; | |
2094 | else | |
2095 | tmp = SSP_CLK_FIRST_EDGE; | |
2096 | SSP_WRITE_BITS(chip->cr0, tmp, SSP_CR0_MASK_SPH, 7); | |
2097 | ||
f9d629c7 | 2098 | SSP_WRITE_BITS(chip->cr0, clk_freq.scr, SSP_CR0_MASK_SCR, 8); |
781c7b12 | 2099 | /* Loopback is available on all versions except PL023 */ |
06fb01fd | 2100 | if (pl022->vendor->loopback) { |
bde435a9 KW |
2101 | if (spi->mode & SPI_LOOP) |
2102 | tmp = LOOPBACK_ENABLED; | |
2103 | else | |
2104 | tmp = LOOPBACK_DISABLED; | |
2105 | SSP_WRITE_BITS(chip->cr1, tmp, SSP_CR1_MASK_LBM, 0); | |
2106 | } | |
b43d65f7 LW |
2107 | SSP_WRITE_BITS(chip->cr1, SSP_DISABLED, SSP_CR1_MASK_SSE, 1); |
2108 | SSP_WRITE_BITS(chip->cr1, chip_info->hierarchy, SSP_CR1_MASK_MS, 2); | |
f1e45f86 VK |
2109 | SSP_WRITE_BITS(chip->cr1, chip_info->slave_tx_disable, SSP_CR1_MASK_SOD, |
2110 | 3); | |
b43d65f7 LW |
2111 | |
2112 | /* Save controller_state */ | |
2113 | spi_set_ctldata(spi, chip); | |
2114 | return status; | |
2115 | err_config_params: | |
bde435a9 | 2116 | spi_set_ctldata(spi, NULL); |
b43d65f7 LW |
2117 | kfree(chip); |
2118 | return status; | |
2119 | } | |
2120 | ||
2121 | /** | |
2122 | * pl022_cleanup - cleanup function registered to SPI master framework | |
2123 | * @spi: spi device which is requesting cleanup | |
2124 | * | |
2125 | * This function is registered to the SPI framework for this SPI master | |
2126 | * controller. It will free the runtime state of chip. | |
2127 | */ | |
2128 | static void pl022_cleanup(struct spi_device *spi) | |
2129 | { | |
2130 | struct chip_data *chip = spi_get_ctldata(spi); | |
2131 | ||
2132 | spi_set_ctldata(spi, NULL); | |
2133 | kfree(chip); | |
2134 | } | |
2135 | ||
b4225885 | 2136 | static int __devinit |
aa25afad | 2137 | pl022_probe(struct amba_device *adev, const struct amba_id *id) |
b43d65f7 LW |
2138 | { |
2139 | struct device *dev = &adev->dev; | |
2140 | struct pl022_ssp_controller *platform_info = adev->dev.platform_data; | |
2141 | struct spi_master *master; | |
2142 | struct pl022 *pl022 = NULL; /*Data for this driver */ | |
2143 | int status = 0; | |
2144 | ||
2145 | dev_info(&adev->dev, | |
2146 | "ARM PL022 driver, device ID: 0x%08x\n", adev->periphid); | |
2147 | if (platform_info == NULL) { | |
2148 | dev_err(&adev->dev, "probe - no platform data supplied\n"); | |
2149 | status = -ENODEV; | |
2150 | goto err_no_pdata; | |
2151 | } | |
2152 | ||
2153 | /* Allocate master with space for data */ | |
2154 | master = spi_alloc_master(dev, sizeof(struct pl022)); | |
2155 | if (master == NULL) { | |
2156 | dev_err(&adev->dev, "probe - cannot alloc SPI master\n"); | |
2157 | status = -ENOMEM; | |
2158 | goto err_no_master; | |
2159 | } | |
2160 | ||
2161 | pl022 = spi_master_get_devdata(master); | |
2162 | pl022->master = master; | |
2163 | pl022->master_info = platform_info; | |
2164 | pl022->adev = adev; | |
2165 | pl022->vendor = id->data; | |
2166 | ||
2167 | /* | |
2168 | * Bus Number Which has been Assigned to this SSP controller | |
2169 | * on this board | |
2170 | */ | |
2171 | master->bus_num = platform_info->bus_id; | |
2172 | master->num_chipselect = platform_info->num_chipselect; | |
2173 | master->cleanup = pl022_cleanup; | |
2174 | master->setup = pl022_setup; | |
2175 | master->transfer = pl022_transfer; | |
2176 | ||
bde435a9 KW |
2177 | /* |
2178 | * Supports mode 0-3, loopback, and active low CS. Transfers are | |
2179 | * always MS bit first on the original pl022. | |
2180 | */ | |
2181 | master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH | SPI_LOOP; | |
2182 | if (pl022->vendor->extended_cr) | |
2183 | master->mode_bits |= SPI_LSB_FIRST; | |
2184 | ||
b43d65f7 LW |
2185 | dev_dbg(&adev->dev, "BUSNO: %d\n", master->bus_num); |
2186 | ||
2187 | status = amba_request_regions(adev, NULL); | |
2188 | if (status) | |
2189 | goto err_no_ioregion; | |
2190 | ||
b1b6b9aa | 2191 | pl022->phybase = adev->res.start; |
b43d65f7 LW |
2192 | pl022->virtbase = ioremap(adev->res.start, resource_size(&adev->res)); |
2193 | if (pl022->virtbase == NULL) { | |
2194 | status = -ENOMEM; | |
2195 | goto err_no_ioremap; | |
2196 | } | |
2197 | printk(KERN_INFO "pl022: mapped registers from 0x%08x to %p\n", | |
2198 | adev->res.start, pl022->virtbase); | |
2199 | ||
2200 | pl022->clk = clk_get(&adev->dev, NULL); | |
2201 | if (IS_ERR(pl022->clk)) { | |
2202 | status = PTR_ERR(pl022->clk); | |
2203 | dev_err(&adev->dev, "could not retrieve SSP/SPI bus clock\n"); | |
2204 | goto err_no_clk; | |
2205 | } | |
7ff6bcf0 RK |
2206 | |
2207 | status = clk_prepare(pl022->clk); | |
2208 | if (status) { | |
2209 | dev_err(&adev->dev, "could not prepare SSP/SPI bus clock\n"); | |
2210 | goto err_clk_prep; | |
2211 | } | |
2212 | ||
71e63e74 UH |
2213 | status = clk_enable(pl022->clk); |
2214 | if (status) { | |
2215 | dev_err(&adev->dev, "could not enable SSP/SPI bus clock\n"); | |
2216 | goto err_no_clk_en; | |
2217 | } | |
2218 | ||
b43d65f7 | 2219 | /* Disable SSP */ |
b43d65f7 LW |
2220 | writew((readw(SSP_CR1(pl022->virtbase)) & (~SSP_CR1_MASK_SSE)), |
2221 | SSP_CR1(pl022->virtbase)); | |
2222 | load_ssp_default_config(pl022); | |
b43d65f7 LW |
2223 | |
2224 | status = request_irq(adev->irq[0], pl022_interrupt_handler, 0, "pl022", | |
2225 | pl022); | |
2226 | if (status < 0) { | |
2227 | dev_err(&adev->dev, "probe - cannot get IRQ (%d)\n", status); | |
2228 | goto err_no_irq; | |
2229 | } | |
b1b6b9aa LW |
2230 | |
2231 | /* Get DMA channels */ | |
2232 | if (platform_info->enable_dma) { | |
2233 | status = pl022_dma_probe(pl022); | |
2234 | if (status != 0) | |
43c64015 | 2235 | platform_info->enable_dma = 0; |
b1b6b9aa LW |
2236 | } |
2237 | ||
b43d65f7 LW |
2238 | /* Initialize and start queue */ |
2239 | status = init_queue(pl022); | |
2240 | if (status != 0) { | |
2241 | dev_err(&adev->dev, "probe - problem initializing queue\n"); | |
2242 | goto err_init_queue; | |
2243 | } | |
2244 | status = start_queue(pl022); | |
2245 | if (status != 0) { | |
2246 | dev_err(&adev->dev, "probe - problem starting queue\n"); | |
2247 | goto err_start_queue; | |
2248 | } | |
2249 | /* Register with the SPI framework */ | |
2250 | amba_set_drvdata(adev, pl022); | |
2251 | status = spi_register_master(master); | |
2252 | if (status != 0) { | |
2253 | dev_err(&adev->dev, | |
2254 | "probe - problem registering spi master\n"); | |
2255 | goto err_spi_register; | |
2256 | } | |
25985edc | 2257 | dev_dbg(dev, "probe succeeded\n"); |
92b97f0a RK |
2258 | |
2259 | /* let runtime pm put suspend */ | |
53e4acea CB |
2260 | if (platform_info->autosuspend_delay > 0) { |
2261 | dev_info(&adev->dev, | |
2262 | "will use autosuspend for runtime pm, delay %dms\n", | |
2263 | platform_info->autosuspend_delay); | |
2264 | pm_runtime_set_autosuspend_delay(dev, | |
2265 | platform_info->autosuspend_delay); | |
2266 | pm_runtime_use_autosuspend(dev); | |
2267 | pm_runtime_put_autosuspend(dev); | |
2268 | } else { | |
2269 | pm_runtime_put(dev); | |
2270 | } | |
b43d65f7 LW |
2271 | return 0; |
2272 | ||
2273 | err_spi_register: | |
2274 | err_start_queue: | |
2275 | err_init_queue: | |
2276 | destroy_queue(pl022); | |
3e3ea716 VK |
2277 | if (platform_info->enable_dma) |
2278 | pl022_dma_remove(pl022); | |
2279 | ||
b43d65f7 LW |
2280 | free_irq(adev->irq[0], pl022); |
2281 | err_no_irq: | |
71e63e74 UH |
2282 | clk_disable(pl022->clk); |
2283 | err_no_clk_en: | |
7ff6bcf0 RK |
2284 | clk_unprepare(pl022->clk); |
2285 | err_clk_prep: | |
b43d65f7 LW |
2286 | clk_put(pl022->clk); |
2287 | err_no_clk: | |
2288 | iounmap(pl022->virtbase); | |
2289 | err_no_ioremap: | |
2290 | amba_release_regions(adev); | |
2291 | err_no_ioregion: | |
2292 | spi_master_put(master); | |
2293 | err_no_master: | |
2294 | err_no_pdata: | |
2295 | return status; | |
2296 | } | |
2297 | ||
b4225885 | 2298 | static int __devexit |
b43d65f7 LW |
2299 | pl022_remove(struct amba_device *adev) |
2300 | { | |
2301 | struct pl022 *pl022 = amba_get_drvdata(adev); | |
50658b66 | 2302 | |
b43d65f7 LW |
2303 | if (!pl022) |
2304 | return 0; | |
2305 | ||
92b97f0a RK |
2306 | /* |
2307 | * undo pm_runtime_put() in probe. I assume that we're not | |
2308 | * accessing the primecell here. | |
2309 | */ | |
2310 | pm_runtime_get_noresume(&adev->dev); | |
2311 | ||
b43d65f7 | 2312 | /* Remove the queue */ |
50658b66 LW |
2313 | if (destroy_queue(pl022) != 0) |
2314 | dev_err(&adev->dev, "queue remove failed\n"); | |
b43d65f7 | 2315 | load_ssp_default_config(pl022); |
3e3ea716 VK |
2316 | if (pl022->master_info->enable_dma) |
2317 | pl022_dma_remove(pl022); | |
2318 | ||
b43d65f7 LW |
2319 | free_irq(adev->irq[0], pl022); |
2320 | clk_disable(pl022->clk); | |
7ff6bcf0 | 2321 | clk_unprepare(pl022->clk); |
b43d65f7 LW |
2322 | clk_put(pl022->clk); |
2323 | iounmap(pl022->virtbase); | |
2324 | amba_release_regions(adev); | |
2325 | tasklet_disable(&pl022->pump_transfers); | |
2326 | spi_unregister_master(pl022->master); | |
2327 | spi_master_put(pl022->master); | |
2328 | amba_set_drvdata(adev, NULL); | |
b43d65f7 LW |
2329 | return 0; |
2330 | } | |
2331 | ||
92b97f0a | 2332 | #ifdef CONFIG_SUSPEND |
6cfa6279 | 2333 | static int pl022_suspend(struct device *dev) |
b43d65f7 | 2334 | { |
92b97f0a | 2335 | struct pl022 *pl022 = dev_get_drvdata(dev); |
b43d65f7 LW |
2336 | int status = 0; |
2337 | ||
2338 | status = stop_queue(pl022); | |
2339 | if (status) { | |
6cfa6279 | 2340 | dev_warn(dev, "suspend cannot stop queue\n"); |
b43d65f7 LW |
2341 | return status; |
2342 | } | |
2343 | ||
6cfa6279 | 2344 | dev_dbg(dev, "suspended\n"); |
b43d65f7 LW |
2345 | return 0; |
2346 | } | |
2347 | ||
92b97f0a | 2348 | static int pl022_resume(struct device *dev) |
b43d65f7 | 2349 | { |
92b97f0a | 2350 | struct pl022 *pl022 = dev_get_drvdata(dev); |
b43d65f7 LW |
2351 | int status = 0; |
2352 | ||
2353 | /* Start the queue running */ | |
2354 | status = start_queue(pl022); | |
2355 | if (status) | |
92b97f0a | 2356 | dev_err(dev, "problem starting queue (%d)\n", status); |
b43d65f7 | 2357 | else |
92b97f0a | 2358 | dev_dbg(dev, "resumed\n"); |
b43d65f7 LW |
2359 | |
2360 | return status; | |
2361 | } | |
b43d65f7 LW |
2362 | #endif /* CONFIG_PM */ |
2363 | ||
92b97f0a RK |
2364 | #ifdef CONFIG_PM_RUNTIME |
2365 | static int pl022_runtime_suspend(struct device *dev) | |
2366 | { | |
2367 | struct pl022 *pl022 = dev_get_drvdata(dev); | |
2368 | ||
2369 | clk_disable(pl022->clk); | |
2370 | amba_vcore_disable(pl022->adev); | |
2371 | ||
2372 | return 0; | |
2373 | } | |
2374 | ||
2375 | static int pl022_runtime_resume(struct device *dev) | |
2376 | { | |
2377 | struct pl022 *pl022 = dev_get_drvdata(dev); | |
2378 | ||
2379 | amba_vcore_enable(pl022->adev); | |
2380 | clk_enable(pl022->clk); | |
2381 | ||
2382 | return 0; | |
2383 | } | |
2384 | #endif | |
2385 | ||
2386 | static const struct dev_pm_ops pl022_dev_pm_ops = { | |
2387 | SET_SYSTEM_SLEEP_PM_OPS(pl022_suspend, pl022_resume) | |
2388 | SET_RUNTIME_PM_OPS(pl022_runtime_suspend, pl022_runtime_resume, NULL) | |
2389 | }; | |
2390 | ||
b43d65f7 LW |
2391 | static struct vendor_data vendor_arm = { |
2392 | .fifodepth = 8, | |
2393 | .max_bpw = 16, | |
2394 | .unidir = false, | |
556f4aeb | 2395 | .extended_cr = false, |
781c7b12 | 2396 | .pl023 = false, |
06fb01fd | 2397 | .loopback = true, |
b43d65f7 LW |
2398 | }; |
2399 | ||
b43d65f7 LW |
2400 | static struct vendor_data vendor_st = { |
2401 | .fifodepth = 32, | |
2402 | .max_bpw = 32, | |
2403 | .unidir = false, | |
556f4aeb | 2404 | .extended_cr = true, |
781c7b12 | 2405 | .pl023 = false, |
06fb01fd | 2406 | .loopback = true, |
781c7b12 LW |
2407 | }; |
2408 | ||
2409 | static struct vendor_data vendor_st_pl023 = { | |
2410 | .fifodepth = 32, | |
2411 | .max_bpw = 32, | |
2412 | .unidir = false, | |
2413 | .extended_cr = true, | |
2414 | .pl023 = true, | |
06fb01fd PL |
2415 | .loopback = false, |
2416 | }; | |
2417 | ||
2418 | static struct vendor_data vendor_db5500_pl023 = { | |
2419 | .fifodepth = 32, | |
2420 | .max_bpw = 32, | |
2421 | .unidir = false, | |
2422 | .extended_cr = true, | |
2423 | .pl023 = true, | |
2424 | .loopback = true, | |
b43d65f7 LW |
2425 | }; |
2426 | ||
2427 | static struct amba_id pl022_ids[] = { | |
2428 | { | |
2429 | /* | |
2430 | * ARM PL022 variant, this has a 16bit wide | |
2431 | * and 8 locations deep TX/RX FIFO | |
2432 | */ | |
2433 | .id = 0x00041022, | |
2434 | .mask = 0x000fffff, | |
2435 | .data = &vendor_arm, | |
2436 | }, | |
2437 | { | |
2438 | /* | |
2439 | * ST Micro derivative, this has 32bit wide | |
2440 | * and 32 locations deep TX/RX FIFO | |
2441 | */ | |
e89e04fc | 2442 | .id = 0x01080022, |
b43d65f7 LW |
2443 | .mask = 0xffffffff, |
2444 | .data = &vendor_st, | |
2445 | }, | |
781c7b12 LW |
2446 | { |
2447 | /* | |
2448 | * ST-Ericsson derivative "PL023" (this is not | |
2449 | * an official ARM number), this is a PL022 SSP block | |
2450 | * stripped to SPI mode only, it has 32bit wide | |
2451 | * and 32 locations deep TX/RX FIFO but no extended | |
2452 | * CR0/CR1 register | |
2453 | */ | |
f1e45f86 VK |
2454 | .id = 0x00080023, |
2455 | .mask = 0xffffffff, | |
2456 | .data = &vendor_st_pl023, | |
781c7b12 | 2457 | }, |
06fb01fd PL |
2458 | { |
2459 | .id = 0x10080023, | |
2460 | .mask = 0xffffffff, | |
2461 | .data = &vendor_db5500_pl023, | |
2462 | }, | |
b43d65f7 LW |
2463 | { 0, 0 }, |
2464 | }; | |
2465 | ||
7eeac71b DM |
2466 | MODULE_DEVICE_TABLE(amba, pl022_ids); |
2467 | ||
b43d65f7 LW |
2468 | static struct amba_driver pl022_driver = { |
2469 | .drv = { | |
2470 | .name = "ssp-pl022", | |
92b97f0a | 2471 | .pm = &pl022_dev_pm_ops, |
b43d65f7 LW |
2472 | }, |
2473 | .id_table = pl022_ids, | |
2474 | .probe = pl022_probe, | |
b4225885 | 2475 | .remove = __devexit_p(pl022_remove), |
b43d65f7 LW |
2476 | }; |
2477 | ||
b43d65f7 LW |
2478 | static int __init pl022_init(void) |
2479 | { | |
2480 | return amba_driver_register(&pl022_driver); | |
2481 | } | |
25c8e03b | 2482 | subsys_initcall(pl022_init); |
b43d65f7 LW |
2483 | |
2484 | static void __exit pl022_exit(void) | |
2485 | { | |
2486 | amba_driver_unregister(&pl022_driver); | |
2487 | } | |
b43d65f7 LW |
2488 | module_exit(pl022_exit); |
2489 | ||
2490 | MODULE_AUTHOR("Linus Walleij <linus.walleij@stericsson.com>"); | |
2491 | MODULE_DESCRIPTION("PL022 SSP Controller Driver"); | |
2492 | MODULE_LICENSE("GPL"); |