[deliverable/linux.git] / drivers / spi / spi-pxa2xx-dma.c

/*
 * PXA2xx SPI DMA engine support.
 *
 * Copyright (C) 2013, Intel Corporation
 * Author: Mika Westerberg <mika.westerberg@linux.intel.com>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */

#include <linux/device.h>
#include <linux/dma-mapping.h>
#include <linux/dmaengine.h>
#include <linux/pxa2xx_ssp.h>
#include <linux/scatterlist.h>
#include <linux/sizes.h>
#include <linux/spi/spi.h>
#include <linux/spi/pxa2xx_spi.h>

#include "spi-pxa2xx.h"

static int pxa2xx_spi_map_dma_buffer(struct driver_data *drv_data,
				     enum dma_data_direction dir)
{
	int i, nents, len = drv_data->len;
	struct scatterlist *sg;
	struct device *dmadev;
	struct sg_table *sgt;
	void *buf, *pbuf;

	if (dir == DMA_TO_DEVICE) {
		dmadev = drv_data->tx_chan->device->dev;
		sgt = &drv_data->tx_sgt;
		buf = drv_data->tx;
	} else {
		dmadev = drv_data->rx_chan->device->dev;
		sgt = &drv_data->rx_sgt;
		buf = drv_data->rx;
	}

	nents = DIV_ROUND_UP(len, SZ_2K);
	if (nents != sgt->nents) {
		int ret;

		sg_free_table(sgt);
		ret = sg_alloc_table(sgt, nents, GFP_ATOMIC);
		if (ret)
			return ret;
	}

	pbuf = buf;
	for_each_sg(sgt->sgl, sg, sgt->nents, i) {
		size_t bytes = min_t(size_t, len, SZ_2K);

		sg_set_buf(sg, pbuf, bytes);
		pbuf += bytes;
		len -= bytes;
	}

	nents = dma_map_sg(dmadev, sgt->sgl, sgt->nents, dir);
	if (!nents)
		return -ENOMEM;

	return nents;
}

static void pxa2xx_spi_unmap_dma_buffer(struct driver_data *drv_data,
					enum dma_data_direction dir)
{
	struct device *dmadev;
	struct sg_table *sgt;

	if (dir == DMA_TO_DEVICE) {
		dmadev = drv_data->tx_chan->device->dev;
		sgt = &drv_data->tx_sgt;
	} else {
		dmadev = drv_data->rx_chan->device->dev;
		sgt = &drv_data->rx_sgt;
	}

	dma_unmap_sg(dmadev, sgt->sgl, sgt->nents, dir);
}

static void pxa2xx_spi_unmap_dma_buffers(struct driver_data *drv_data)
{
	if (!drv_data->dma_mapped)
		return;

	pxa2xx_spi_unmap_dma_buffer(drv_data, DMA_FROM_DEVICE);
	pxa2xx_spi_unmap_dma_buffer(drv_data, DMA_TO_DEVICE);

	drv_data->dma_mapped = 0;
}

static void pxa2xx_spi_dma_transfer_complete(struct driver_data *drv_data,
					     bool error)
{
	struct spi_message *msg = drv_data->cur_msg;

	/*
	 * It is possible that one CPU is handling ROR interrupt and other
	 * just gets DMA completion. Calling pump_transfers() twice for the
	 * same transfer leads to problems thus we prevent concurrent calls
	 * by using ->dma_running.
	 */
	if (atomic_dec_and_test(&drv_data->dma_running)) {
		/*
		 * If the other CPU is still handling the ROR interrupt we
		 * might not know about the error yet. So we re-check the
		 * ROR bit here before we clear the status register.
		 */
		if (!error) {
			u32 status = pxa2xx_spi_read(drv_data, SSSR)
				     & drv_data->mask_sr;
			error = status & SSSR_ROR;
		}

		/* Clear status & disable interrupts */
		pxa2xx_spi_write(drv_data, SSCR1,
				 pxa2xx_spi_read(drv_data, SSCR1)
				 & ~drv_data->dma_cr1);
		write_SSSR_CS(drv_data, drv_data->clear_sr);
		if (!pxa25x_ssp_comp(drv_data))
			pxa2xx_spi_write(drv_data, SSTO, 0);

		if (!error) {
			pxa2xx_spi_unmap_dma_buffers(drv_data);

			msg->actual_length += drv_data->len;
			msg->state = pxa2xx_spi_next_transfer(drv_data);
		} else {
			/* In case we got an error we disable the SSP now */
			pxa2xx_spi_write(drv_data, SSCR0,
					 pxa2xx_spi_read(drv_data, SSCR0)
					 & ~SSCR0_SSE);

			msg->state = ERROR_STATE;
		}

		tasklet_schedule(&drv_data->pump_transfers);
	}
}

static void pxa2xx_spi_dma_callback(void *data)
{
	pxa2xx_spi_dma_transfer_complete(data, false);
}

static struct dma_async_tx_descriptor *
pxa2xx_spi_dma_prepare_one(struct driver_data *drv_data,
			   enum dma_transfer_direction dir)
{
	struct chip_data *chip = drv_data->cur_chip;
	enum dma_slave_buswidth width;
	struct dma_slave_config cfg;
	struct dma_chan *chan;
	struct sg_table *sgt;
	int nents, ret;

	switch (drv_data->n_bytes) {
	case 1:
		width = DMA_SLAVE_BUSWIDTH_1_BYTE;
		break;
	case 2:
		width = DMA_SLAVE_BUSWIDTH_2_BYTES;
		break;
	default:
		width = DMA_SLAVE_BUSWIDTH_4_BYTES;
		break;
	}

	memset(&cfg, 0, sizeof(cfg));
	cfg.direction = dir;

	if (dir == DMA_MEM_TO_DEV) {
		cfg.dst_addr = drv_data->ssdr_physical;
		cfg.dst_addr_width = width;
		cfg.dst_maxburst = chip->dma_burst_size;

		sgt = &drv_data->tx_sgt;
		nents = drv_data->tx_nents;
		chan = drv_data->tx_chan;
	} else {
		cfg.src_addr = drv_data->ssdr_physical;
		cfg.src_addr_width = width;
		cfg.src_maxburst = chip->dma_burst_size;

		sgt = &drv_data->rx_sgt;
		nents = drv_data->rx_nents;
		chan = drv_data->rx_chan;
	}

	ret = dmaengine_slave_config(chan, &cfg);
	if (ret) {
		dev_warn(&drv_data->pdev->dev, "DMA slave config failed\n");
		return NULL;
	}

	return dmaengine_prep_slave_sg(chan, sgt->sgl, nents, dir,
				       DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
}

bool pxa2xx_spi_dma_is_possible(size_t len)
{
	return len <= MAX_DMA_LEN;
}

int pxa2xx_spi_map_dma_buffers(struct driver_data *drv_data)
{
	const struct chip_data *chip = drv_data->cur_chip;
	int ret;

	if (!chip->enable_dma)
		return 0;

	/* Don't bother with DMA if we can't do even a single burst */
	if (drv_data->len < chip->dma_burst_size)
		return 0;

	ret = pxa2xx_spi_map_dma_buffer(drv_data, DMA_TO_DEVICE);
	if (ret <= 0) {
		dev_warn(&drv_data->pdev->dev, "failed to DMA map TX\n");
		return 0;
	}

	drv_data->tx_nents = ret;

	ret = pxa2xx_spi_map_dma_buffer(drv_data, DMA_FROM_DEVICE);
	if (ret <= 0) {
		pxa2xx_spi_unmap_dma_buffer(drv_data, DMA_TO_DEVICE);
		dev_warn(&drv_data->pdev->dev, "failed to DMA map RX\n");
		return 0;
	}

	drv_data->rx_nents = ret;
	return 1;
}

irqreturn_t pxa2xx_spi_dma_transfer(struct driver_data *drv_data)
{
	u32 status;

	status = pxa2xx_spi_read(drv_data, SSSR) & drv_data->mask_sr;
	if (status & SSSR_ROR) {
		dev_err(&drv_data->pdev->dev, "FIFO overrun\n");

		dmaengine_terminate_async(drv_data->rx_chan);
		dmaengine_terminate_async(drv_data->tx_chan);

		pxa2xx_spi_dma_transfer_complete(drv_data, true);
		return IRQ_HANDLED;
	}

	return IRQ_NONE;
}

int pxa2xx_spi_dma_prepare(struct driver_data *drv_data, u32 dma_burst)
{
	struct dma_async_tx_descriptor *tx_desc, *rx_desc;
	int err = 0;

	tx_desc = pxa2xx_spi_dma_prepare_one(drv_data, DMA_MEM_TO_DEV);
	if (!tx_desc) {
		dev_err(&drv_data->pdev->dev,
			"failed to get DMA TX descriptor\n");
		err = -EBUSY;
		goto err_tx;
	}

	rx_desc = pxa2xx_spi_dma_prepare_one(drv_data, DMA_DEV_TO_MEM);
	if (!rx_desc) {
		dev_err(&drv_data->pdev->dev,
			"failed to get DMA RX descriptor\n");
		err = -EBUSY;
		goto err_rx;
	}

	/* We are ready when RX completes */
	rx_desc->callback = pxa2xx_spi_dma_callback;
	rx_desc->callback_param = drv_data;

	dmaengine_submit(rx_desc);
	dmaengine_submit(tx_desc);
	return 0;

err_rx:
	dmaengine_terminate_async(drv_data->tx_chan);
err_tx:
	pxa2xx_spi_unmap_dma_buffers(drv_data);
	return err;
}

void pxa2xx_spi_dma_start(struct driver_data *drv_data)
{
	dma_async_issue_pending(drv_data->rx_chan);
	dma_async_issue_pending(drv_data->tx_chan);

	atomic_set(&drv_data->dma_running, 1);
}

int pxa2xx_spi_dma_setup(struct driver_data *drv_data)
{
	struct pxa2xx_spi_master *pdata = drv_data->master_info;
	struct device *dev = &drv_data->pdev->dev;
	dma_cap_mask_t mask;

	dma_cap_zero(mask);
	dma_cap_set(DMA_SLAVE, mask);

	drv_data->tx_chan = dma_request_slave_channel_compat(mask,
				pdata->dma_filter, pdata->tx_param, dev, "tx");
	if (!drv_data->tx_chan)
		return -ENODEV;

	drv_data->rx_chan = dma_request_slave_channel_compat(mask,
				pdata->dma_filter, pdata->rx_param, dev, "rx");
	if (!drv_data->rx_chan) {
		dma_release_channel(drv_data->tx_chan);
		drv_data->tx_chan = NULL;
		return -ENODEV;
	}

	return 0;
}

void pxa2xx_spi_dma_release(struct driver_data *drv_data)
{
	if (drv_data->rx_chan) {
		dmaengine_terminate_sync(drv_data->rx_chan);
		dma_release_channel(drv_data->rx_chan);
		sg_free_table(&drv_data->rx_sgt);
		drv_data->rx_chan = NULL;
	}
	if (drv_data->tx_chan) {
		dmaengine_terminate_sync(drv_data->tx_chan);
		dma_release_channel(drv_data->tx_chan);
		sg_free_table(&drv_data->tx_sgt);
		drv_data->tx_chan = NULL;
	}
}

int pxa2xx_spi_set_dma_burst_and_threshold(struct chip_data *chip,
					   struct spi_device *spi,
					   u8 bits_per_word, u32 *burst_code,
					   u32 *threshold)
{
	struct pxa2xx_spi_chip *chip_info = spi->controller_data;

	/*
	 * If the DMA burst size is given in chip_info we use that,
	 * otherwise we use the default. Also we use the default FIFO
	 * thresholds for now.
	 */
	*burst_code = chip_info ? chip_info->dma_burst_size : 1;
	*threshold = SSCR1_RxTresh(RX_THRESH_DFLT)
		   | SSCR1_TxTresh(TX_THRESH_DFLT);

	return 0;
}
Commit	Line	Data
5928808e MW	1	/*
	2	* PXA2xx SPI DMA engine support.
	3	*
	4	* Copyright (C) 2013, Intel Corporation
	5	* Author: Mika Westerberg <mika.westerberg@linux.intel.com>
	6	*
	7	* This program is free software; you can redistribute it and/or modify
	8	* it under the terms of the GNU General Public License version 2 as
	9	* published by the Free Software Foundation.
	10	*/
	11
5928808e MW	12	#include <linux/device.h>
	13	#include <linux/dma-mapping.h>
	14	#include <linux/dmaengine.h>
	15	#include <linux/pxa2xx_ssp.h>
	16	#include <linux/scatterlist.h>
	17	#include <linux/sizes.h>
	18	#include <linux/spi/spi.h>
	19	#include <linux/spi/pxa2xx_spi.h>
	20
	21	#include "spi-pxa2xx.h"
	22
	23	static int pxa2xx_spi_map_dma_buffer(struct driver_data *drv_data,
	24	enum dma_data_direction dir)
	25	{
	26	int i, nents, len = drv_data->len;
	27	struct scatterlist *sg;
	28	struct device *dmadev;
	29	struct sg_table *sgt;
	30	void buf, pbuf;
	31
5928808e MW	32	if (dir == DMA_TO_DEVICE) {
	33	dmadev = drv_data->tx_chan->device->dev;
	34	sgt = &drv_data->tx_sgt;
	35	buf = drv_data->tx;
5928808e MW	36	} else {
	37	dmadev = drv_data->rx_chan->device->dev;
	38	sgt = &drv_data->rx_sgt;
	39	buf = drv_data->rx;
5928808e MW	40	}
	41
	42	nents = DIV_ROUND_UP(len, SZ_2K);
	43	if (nents != sgt->nents) {
	44	int ret;
	45
	46	sg_free_table(sgt);
5548f98c	47	ret = sg_alloc_table(sgt, nents, GFP_ATOMIC);
5928808e MW	48	if (ret)
	49	return ret;
	50	}
	51
	52	pbuf = buf;
	53	for_each_sg(sgt->sgl, sg, sgt->nents, i) {
	54	size_t bytes = min_t(size_t, len, SZ_2K);
	55
8c3ad488	56	sg_set_buf(sg, pbuf, bytes);
5928808e MW	57	pbuf += bytes;
	58	len -= bytes;
	59	}
	60
	61	nents = dma_map_sg(dmadev, sgt->sgl, sgt->nents, dir);
	62	if (!nents)
	63	return -ENOMEM;
	64
	65	return nents;
	66	}
	67
	68	static void pxa2xx_spi_unmap_dma_buffer(struct driver_data *drv_data,
	69	enum dma_data_direction dir)
	70	{
	71	struct device *dmadev;
	72	struct sg_table *sgt;
	73
	74	if (dir == DMA_TO_DEVICE) {
	75	dmadev = drv_data->tx_chan->device->dev;
	76	sgt = &drv_data->tx_sgt;
	77	} else {
	78	dmadev = drv_data->rx_chan->device->dev;
	79	sgt = &drv_data->rx_sgt;
	80	}
	81
	82	dma_unmap_sg(dmadev, sgt->sgl, sgt->nents, dir);
	83	}
	84
	85	static void pxa2xx_spi_unmap_dma_buffers(struct driver_data *drv_data)
	86	{
	87	if (!drv_data->dma_mapped)
	88	return;
	89
	90	pxa2xx_spi_unmap_dma_buffer(drv_data, DMA_FROM_DEVICE);
	91	pxa2xx_spi_unmap_dma_buffer(drv_data, DMA_TO_DEVICE);
	92
	93	drv_data->dma_mapped = 0;
	94	}
	95
	96	static void pxa2xx_spi_dma_transfer_complete(struct driver_data *drv_data,
	97	bool error)
	98	{
	99	struct spi_message *msg = drv_data->cur_msg;
	100
	101	/*
	102	* It is possible that one CPU is handling ROR interrupt and other
	103	* just gets DMA completion. Calling pump_transfers() twice for the
	104	* same transfer leads to problems thus we prevent concurrent calls
	105	* by using ->dma_running.
	106	*/
	107	if (atomic_dec_and_test(&drv_data->dma_running)) {
5928808e MW	108	/*
	109	* If the other CPU is still handling the ROR interrupt we
	110	* might not know about the error yet. So we re-check the
	111	* ROR bit here before we clear the status register.
	112	*/
	113	if (!error) {
c039dd27 JN	114	u32 status = pxa2xx_spi_read(drv_data, SSSR)
c039dd27 JN	115	& drv_data->mask_sr;
5928808e MW	116	error = status & SSSR_ROR;
	117	}
	118
	119	/* Clear status & disable interrupts */
c039dd27 JN	120	pxa2xx_spi_write(drv_data, SSCR1,
	121	pxa2xx_spi_read(drv_data, SSCR1)
	122	& ~drv_data->dma_cr1);
5928808e MW	123	write_SSSR_CS(drv_data, drv_data->clear_sr);
5928808e MW	124	if (!pxa25x_ssp_comp(drv_data))
c039dd27	125	pxa2xx_spi_write(drv_data, SSTO, 0);
5928808e MW	126
	127	if (!error) {
	128	pxa2xx_spi_unmap_dma_buffers(drv_data);
	129
5928808e MW	130	msg->actual_length += drv_data->len;
	131	msg->state = pxa2xx_spi_next_transfer(drv_data);
	132	} else {
	133	/* In case we got an error we disable the SSP now */
c039dd27 JN	134	pxa2xx_spi_write(drv_data, SSCR0,
	135	pxa2xx_spi_read(drv_data, SSCR0)
	136	& ~SSCR0_SSE);
5928808e MW	137
	138	msg->state = ERROR_STATE;
	139	}
	140
	141	tasklet_schedule(&drv_data->pump_transfers);
	142	}
	143	}
	144
	145	static void pxa2xx_spi_dma_callback(void *data)
	146	{
	147	pxa2xx_spi_dma_transfer_complete(data, false);
	148	}
	149
	150	static struct dma_async_tx_descriptor *
	151	pxa2xx_spi_dma_prepare_one(struct driver_data *drv_data,
	152	enum dma_transfer_direction dir)
	153	{
5928808e MW	154	struct chip_data *chip = drv_data->cur_chip;
	155	enum dma_slave_buswidth width;
	156	struct dma_slave_config cfg;
	157	struct dma_chan *chan;
	158	struct sg_table *sgt;
	159	int nents, ret;
	160
	161	switch (drv_data->n_bytes) {
	162	case 1:
	163	width = DMA_SLAVE_BUSWIDTH_1_BYTE;
	164	break;
	165	case 2:
	166	width = DMA_SLAVE_BUSWIDTH_2_BYTES;
	167	break;
	168	default:
	169	width = DMA_SLAVE_BUSWIDTH_4_BYTES;
	170	break;
	171	}
	172
	173	memset(&cfg, 0, sizeof(cfg));
	174	cfg.direction = dir;
	175
	176	if (dir == DMA_MEM_TO_DEV) {
	177	cfg.dst_addr = drv_data->ssdr_physical;
	178	cfg.dst_addr_width = width;
	179	cfg.dst_maxburst = chip->dma_burst_size;
5928808e MW	180
	181	sgt = &drv_data->tx_sgt;
	182	nents = drv_data->tx_nents;
	183	chan = drv_data->tx_chan;
	184	} else {
	185	cfg.src_addr = drv_data->ssdr_physical;
	186	cfg.src_addr_width = width;
	187	cfg.src_maxburst = chip->dma_burst_size;
5928808e MW	188
	189	sgt = &drv_data->rx_sgt;
	190	nents = drv_data->rx_nents;
	191	chan = drv_data->rx_chan;
	192	}
	193
	194	ret = dmaengine_slave_config(chan, &cfg);
	195	if (ret) {
	196	dev_warn(&drv_data->pdev->dev, "DMA slave config failed\n");
	197	return NULL;
	198	}
	199
	200	return dmaengine_prep_slave_sg(chan, sgt->sgl, nents, dir,
	201	DMA_PREP_INTERRUPT \| DMA_CTRL_ACK);
	202	}
	203
5928808e MW	204	bool pxa2xx_spi_dma_is_possible(size_t len)
	205	{
	206	return len <= MAX_DMA_LEN;
	207	}
	208
	209	int pxa2xx_spi_map_dma_buffers(struct driver_data *drv_data)
	210	{
	211	const struct chip_data *chip = drv_data->cur_chip;
	212	int ret;
	213
	214	if (!chip->enable_dma)
	215	return 0;
	216
	217	/* Don't bother with DMA if we can't do even a single burst */
	218	if (drv_data->len < chip->dma_burst_size)
	219	return 0;
	220
	221	ret = pxa2xx_spi_map_dma_buffer(drv_data, DMA_TO_DEVICE);
	222	if (ret <= 0) {
	223	dev_warn(&drv_data->pdev->dev, "failed to DMA map TX\n");
	224	return 0;
	225	}
	226
	227	drv_data->tx_nents = ret;
	228
	229	ret = pxa2xx_spi_map_dma_buffer(drv_data, DMA_FROM_DEVICE);
	230	if (ret <= 0) {
	231	pxa2xx_spi_unmap_dma_buffer(drv_data, DMA_TO_DEVICE);
	232	dev_warn(&drv_data->pdev->dev, "failed to DMA map RX\n");
	233	return 0;
	234	}
	235
	236	drv_data->rx_nents = ret;
	237	return 1;
	238	}
	239
	240	irqreturn_t pxa2xx_spi_dma_transfer(struct driver_data *drv_data)
	241	{
	242	u32 status;
	243
c039dd27	244	status = pxa2xx_spi_read(drv_data, SSSR) & drv_data->mask_sr;
5928808e MW	245	if (status & SSSR_ROR) {
	246	dev_err(&drv_data->pdev->dev, "FIFO overrun\n");
	247
59074501 JN	248	dmaengine_terminate_async(drv_data->rx_chan);
59074501 JN	249	dmaengine_terminate_async(drv_data->tx_chan);
5928808e MW	250
	251	pxa2xx_spi_dma_transfer_complete(drv_data, true);
	252	return IRQ_HANDLED;
	253	}
	254
	255	return IRQ_NONE;
	256	}
	257
	258	int pxa2xx_spi_dma_prepare(struct driver_data *drv_data, u32 dma_burst)
	259	{
	260	struct dma_async_tx_descriptor tx_desc, rx_desc;
7d1f1bf6	261	int err = 0;
5928808e MW	262
	263	tx_desc = pxa2xx_spi_dma_prepare_one(drv_data, DMA_MEM_TO_DEV);
	264	if (!tx_desc) {
	265	dev_err(&drv_data->pdev->dev,
	266	"failed to get DMA TX descriptor\n");
7d1f1bf6 AS	267	err = -EBUSY;
7d1f1bf6 AS	268	goto err_tx;
5928808e MW	269	}
	270
	271	rx_desc = pxa2xx_spi_dma_prepare_one(drv_data, DMA_DEV_TO_MEM);
	272	if (!rx_desc) {
	273	dev_err(&drv_data->pdev->dev,
	274	"failed to get DMA RX descriptor\n");
7d1f1bf6 AS	275	err = -EBUSY;
7d1f1bf6 AS	276	goto err_rx;
5928808e MW	277	}
	278
	279	/* We are ready when RX completes */
	280	rx_desc->callback = pxa2xx_spi_dma_callback;
	281	rx_desc->callback_param = drv_data;
	282
	283	dmaengine_submit(rx_desc);
	284	dmaengine_submit(tx_desc);
	285	return 0;
7d1f1bf6 AS	286
	287	err_rx:
	288	dmaengine_terminate_async(drv_data->tx_chan);
	289	err_tx:
	290	pxa2xx_spi_unmap_dma_buffers(drv_data);
	291	return err;
5928808e MW	292	}
	293
	294	void pxa2xx_spi_dma_start(struct driver_data *drv_data)
	295	{
	296	dma_async_issue_pending(drv_data->rx_chan);
	297	dma_async_issue_pending(drv_data->tx_chan);
	298
	299	atomic_set(&drv_data->dma_running, 1);
	300	}
	301
	302	int pxa2xx_spi_dma_setup(struct driver_data *drv_data)
	303	{
	304	struct pxa2xx_spi_master *pdata = drv_data->master_info;
cddb339b	305	struct device *dev = &drv_data->pdev->dev;
5928808e MW	306	dma_cap_mask_t mask;
	307
	308	dma_cap_zero(mask);
	309	dma_cap_set(DMA_SLAVE, mask);
	310
cddb339b	311	drv_data->tx_chan = dma_request_slave_channel_compat(mask,
b729bf34	312	pdata->dma_filter, pdata->tx_param, dev, "tx");
5928808e MW	313	if (!drv_data->tx_chan)
	314	return -ENODEV;
	315
cddb339b	316	drv_data->rx_chan = dma_request_slave_channel_compat(mask,
b729bf34	317	pdata->dma_filter, pdata->rx_param, dev, "rx");
5928808e MW	318	if (!drv_data->rx_chan) {
	319	dma_release_channel(drv_data->tx_chan);
	320	drv_data->tx_chan = NULL;
	321	return -ENODEV;
	322	}
	323
	324	return 0;
	325	}
	326
	327	void pxa2xx_spi_dma_release(struct driver_data *drv_data)
	328	{
	329	if (drv_data->rx_chan) {
59074501	330	dmaengine_terminate_sync(drv_data->rx_chan);
5928808e MW	331	dma_release_channel(drv_data->rx_chan);
	332	sg_free_table(&drv_data->rx_sgt);
	333	drv_data->rx_chan = NULL;
	334	}
	335	if (drv_data->tx_chan) {
59074501	336	dmaengine_terminate_sync(drv_data->tx_chan);
5928808e MW	337	dma_release_channel(drv_data->tx_chan);
	338	sg_free_table(&drv_data->tx_sgt);
	339	drv_data->tx_chan = NULL;
	340	}
	341	}
	342
5928808e MW	343	int pxa2xx_spi_set_dma_burst_and_threshold(struct chip_data *chip,
	344	struct spi_device *spi,
	345	u8 bits_per_word, u32 *burst_code,
	346	u32 *threshold)
	347	{
	348	struct pxa2xx_spi_chip *chip_info = spi->controller_data;
	349
	350	/*
	351	* If the DMA burst size is given in chip_info we use that,
	352	* otherwise we use the default. Also we use the default FIFO
	353	* thresholds for now.
	354	*/
01d7aafb	355	*burst_code = chip_info ? chip_info->dma_burst_size : 1;
5928808e MW	356	*threshold = SSCR1_RxTresh(RX_THRESH_DFLT)
	357	\| SSCR1_TxTresh(TX_THRESH_DFLT);
	358
	359	return 0;
	360	}