Commit | Line | Data |
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d6ea3df0 SAS |
1 | /* |
2 | * CE4100's SPI device is more or less the same one as found on PXA | |
3 | * | |
4 | */ | |
5 | #include <linux/pci.h> | |
6 | #include <linux/platform_device.h> | |
7 | #include <linux/of_device.h> | |
d7614de4 | 8 | #include <linux/module.h> |
d6ea3df0 | 9 | #include <linux/spi/pxa2xx_spi.h> |
afa93c90 CCE |
10 | #include <linux/clk.h> |
11 | #include <linux/clk-provider.h> | |
d6ea3df0 | 12 | |
b729bf34 MW |
13 | #include <linux/dmaengine.h> |
14 | #include <linux/platform_data/dma-dw.h> | |
15 | ||
d6ba32d5 CCE |
16 | enum { |
17 | PORT_CE4100, | |
18 | PORT_BYT, | |
39d36536 MW |
19 | PORT_BSW0, |
20 | PORT_BSW1, | |
21 | PORT_BSW2, | |
e5262d05 | 22 | PORT_QUARK_X1000, |
d6ba32d5 CCE |
23 | }; |
24 | ||
25 | struct pxa_spi_info { | |
26 | enum pxa_ssp_type type; | |
27 | int port_id; | |
28 | int num_chipselect; | |
afa93c90 | 29 | unsigned long max_clk_rate; |
b729bf34 MW |
30 | |
31 | /* DMA channel request parameters */ | |
32 | void *tx_param; | |
33 | void *rx_param; | |
d6ba32d5 CCE |
34 | }; |
35 | ||
b729bf34 MW |
36 | static struct dw_dma_slave byt_tx_param = { .dst_id = 0 }; |
37 | static struct dw_dma_slave byt_rx_param = { .src_id = 1 }; | |
38 | ||
39d36536 MW |
39 | static struct dw_dma_slave bsw0_tx_param = { .dst_id = 0 }; |
40 | static struct dw_dma_slave bsw0_rx_param = { .src_id = 1 }; | |
41 | static struct dw_dma_slave bsw1_tx_param = { .dst_id = 6 }; | |
42 | static struct dw_dma_slave bsw1_rx_param = { .src_id = 7 }; | |
43 | static struct dw_dma_slave bsw2_tx_param = { .dst_id = 8 }; | |
44 | static struct dw_dma_slave bsw2_rx_param = { .src_id = 9 }; | |
45 | ||
b729bf34 MW |
46 | static bool lpss_dma_filter(struct dma_chan *chan, void *param) |
47 | { | |
48 | struct dw_dma_slave *dws = param; | |
49 | ||
50 | if (dws->dma_dev != chan->device->dev) | |
51 | return false; | |
52 | ||
53 | chan->private = dws; | |
54 | return true; | |
55 | } | |
56 | ||
d6ba32d5 CCE |
57 | static struct pxa_spi_info spi_info_configs[] = { |
58 | [PORT_CE4100] = { | |
59 | .type = PXA25x_SSP, | |
60 | .port_id = -1, | |
61 | .num_chipselect = -1, | |
afa93c90 | 62 | .max_clk_rate = 3686400, |
d6ba32d5 CCE |
63 | }, |
64 | [PORT_BYT] = { | |
65 | .type = LPSS_SSP, | |
66 | .port_id = 0, | |
67 | .num_chipselect = 1, | |
afa93c90 | 68 | .max_clk_rate = 50000000, |
b729bf34 MW |
69 | .tx_param = &byt_tx_param, |
70 | .rx_param = &byt_rx_param, | |
d6ba32d5 | 71 | }, |
39d36536 MW |
72 | [PORT_BSW0] = { |
73 | .type = LPSS_SSP, | |
74 | .port_id = 0, | |
75 | .num_chipselect = 1, | |
76 | .max_clk_rate = 50000000, | |
77 | .tx_param = &bsw0_tx_param, | |
78 | .rx_param = &bsw0_rx_param, | |
79 | }, | |
80 | [PORT_BSW1] = { | |
81 | .type = LPSS_SSP, | |
82 | .port_id = 1, | |
83 | .num_chipselect = 1, | |
84 | .max_clk_rate = 50000000, | |
85 | .tx_param = &bsw1_tx_param, | |
86 | .rx_param = &bsw1_rx_param, | |
87 | }, | |
88 | [PORT_BSW2] = { | |
89 | .type = LPSS_SSP, | |
90 | .port_id = 2, | |
91 | .num_chipselect = 1, | |
92 | .max_clk_rate = 50000000, | |
93 | .tx_param = &bsw2_tx_param, | |
94 | .rx_param = &bsw2_rx_param, | |
d6ba32d5 | 95 | }, |
e5262d05 WC |
96 | [PORT_QUARK_X1000] = { |
97 | .type = QUARK_X1000_SSP, | |
98 | .port_id = -1, | |
99 | .num_chipselect = 1, | |
100 | .max_clk_rate = 50000000, | |
101 | }, | |
d6ba32d5 CCE |
102 | }; |
103 | ||
104 | static int pxa2xx_spi_pci_probe(struct pci_dev *dev, | |
d6ea3df0 SAS |
105 | const struct pci_device_id *ent) |
106 | { | |
0202775b | 107 | struct platform_device_info pi; |
d6ea3df0 | 108 | int ret; |
d6ea3df0 | 109 | struct platform_device *pdev; |
0f3e1d27 | 110 | struct pxa2xx_spi_master spi_pdata; |
d6ea3df0 | 111 | struct ssp_device *ssp; |
d6ba32d5 | 112 | struct pxa_spi_info *c; |
afa93c90 | 113 | char buf[40]; |
b729bf34 | 114 | struct pci_dev *dma_dev; |
d6ea3df0 | 115 | |
0202775b | 116 | ret = pcim_enable_device(dev); |
d6ea3df0 SAS |
117 | if (ret) |
118 | return ret; | |
119 | ||
0202775b | 120 | ret = pcim_iomap_regions(dev, 1 << 0, "PXA2xx SPI"); |
c1346340 | 121 | if (ret) |
d6ea3df0 | 122 | return ret; |
d6ea3df0 | 123 | |
d6ba32d5 CCE |
124 | c = &spi_info_configs[ent->driver_data]; |
125 | ||
0f3e1d27 | 126 | memset(&spi_pdata, 0, sizeof(spi_pdata)); |
d6ba32d5 CCE |
127 | spi_pdata.num_chipselect = (c->num_chipselect > 0) ? |
128 | c->num_chipselect : dev->devfn; | |
b729bf34 MW |
129 | |
130 | dma_dev = pci_get_slot(dev->bus, PCI_DEVFN(PCI_SLOT(dev->devfn), 0)); | |
131 | ||
132 | if (c->tx_param) { | |
133 | struct dw_dma_slave *slave = c->tx_param; | |
134 | ||
135 | slave->dma_dev = &dma_dev->dev; | |
136 | slave->src_master = 1; | |
137 | slave->dst_master = 0; | |
138 | } | |
139 | ||
140 | if (c->rx_param) { | |
141 | struct dw_dma_slave *slave = c->rx_param; | |
142 | ||
143 | slave->dma_dev = &dma_dev->dev; | |
144 | slave->src_master = 1; | |
145 | slave->dst_master = 0; | |
146 | } | |
147 | ||
148 | spi_pdata.dma_filter = lpss_dma_filter; | |
149 | spi_pdata.tx_param = c->tx_param; | |
150 | spi_pdata.rx_param = c->rx_param; | |
151 | spi_pdata.enable_dma = c->rx_param && c->tx_param; | |
d6ea3df0 | 152 | |
851bacf5 | 153 | ssp = &spi_pdata.ssp; |
d6ea3df0 | 154 | ssp->phys_base = pci_resource_start(dev, 0); |
0202775b | 155 | ssp->mmio_base = pcim_iomap_table(dev)[0]; |
d6ea3df0 | 156 | if (!ssp->mmio_base) { |
0202775b MW |
157 | dev_err(&dev->dev, "failed to ioremap() registers\n"); |
158 | return -EIO; | |
d6ea3df0 SAS |
159 | } |
160 | ssp->irq = dev->irq; | |
d6ba32d5 CCE |
161 | ssp->port_id = (c->port_id >= 0) ? c->port_id : dev->devfn; |
162 | ssp->type = c->type; | |
d6ea3df0 | 163 | |
afa93c90 CCE |
164 | snprintf(buf, sizeof(buf), "pxa2xx-spi.%d", ssp->port_id); |
165 | ssp->clk = clk_register_fixed_rate(&dev->dev, buf , NULL, | |
166 | CLK_IS_ROOT, c->max_clk_rate); | |
167 | if (IS_ERR(ssp->clk)) | |
168 | return PTR_ERR(ssp->clk); | |
169 | ||
0202775b MW |
170 | memset(&pi, 0, sizeof(pi)); |
171 | pi.parent = &dev->dev; | |
172 | pi.name = "pxa2xx-spi"; | |
173 | pi.id = ssp->port_id; | |
174 | pi.data = &spi_pdata; | |
175 | pi.size_data = sizeof(spi_pdata); | |
d6ea3df0 | 176 | |
0202775b | 177 | pdev = platform_device_register_full(&pi); |
afa93c90 CCE |
178 | if (IS_ERR(pdev)) { |
179 | clk_unregister(ssp->clk); | |
d77b5382 | 180 | return PTR_ERR(pdev); |
afa93c90 | 181 | } |
d6ea3df0 | 182 | |
851bacf5 | 183 | pci_set_drvdata(dev, pdev); |
d6ea3df0 | 184 | |
0202775b | 185 | return 0; |
d6ea3df0 SAS |
186 | } |
187 | ||
d6ba32d5 | 188 | static void pxa2xx_spi_pci_remove(struct pci_dev *dev) |
d6ea3df0 | 189 | { |
851bacf5 | 190 | struct platform_device *pdev = pci_get_drvdata(dev); |
afa93c90 CCE |
191 | struct pxa2xx_spi_master *spi_pdata; |
192 | ||
193 | spi_pdata = dev_get_platdata(&pdev->dev); | |
d6ea3df0 | 194 | |
851bacf5 | 195 | platform_device_unregister(pdev); |
afa93c90 | 196 | clk_unregister(spi_pdata->ssp.clk); |
d6ea3df0 SAS |
197 | } |
198 | ||
d6ba32d5 CCE |
199 | static const struct pci_device_id pxa2xx_spi_pci_devices[] = { |
200 | { PCI_VDEVICE(INTEL, 0x2e6a), PORT_CE4100 }, | |
e5262d05 | 201 | { PCI_VDEVICE(INTEL, 0x0935), PORT_QUARK_X1000 }, |
d6ba32d5 | 202 | { PCI_VDEVICE(INTEL, 0x0f0e), PORT_BYT }, |
39d36536 MW |
203 | { PCI_VDEVICE(INTEL, 0x228e), PORT_BSW0 }, |
204 | { PCI_VDEVICE(INTEL, 0x2290), PORT_BSW1 }, | |
205 | { PCI_VDEVICE(INTEL, 0x22ac), PORT_BSW2 }, | |
d6ea3df0 SAS |
206 | { }, |
207 | }; | |
d6ba32d5 | 208 | MODULE_DEVICE_TABLE(pci, pxa2xx_spi_pci_devices); |
d6ea3df0 | 209 | |
d6ba32d5 CCE |
210 | static struct pci_driver pxa2xx_spi_pci_driver = { |
211 | .name = "pxa2xx_spi_pci", | |
212 | .id_table = pxa2xx_spi_pci_devices, | |
213 | .probe = pxa2xx_spi_pci_probe, | |
214 | .remove = pxa2xx_spi_pci_remove, | |
d6ea3df0 SAS |
215 | }; |
216 | ||
d6ba32d5 | 217 | module_pci_driver(pxa2xx_spi_pci_driver); |
d6ea3df0 | 218 | |
d6ba32d5 | 219 | MODULE_DESCRIPTION("CE4100/LPSS PCI-SPI glue code for PXA's driver"); |
d6ea3df0 SAS |
220 | MODULE_LICENSE("GPL v2"); |
221 | MODULE_AUTHOR("Sebastian Andrzej Siewior <bigeasy@linutronix.de>"); |