Commit | Line | Data |
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d6ea3df0 SAS |
1 | /* |
2 | * CE4100's SPI device is more or less the same one as found on PXA | |
3 | * | |
4 | */ | |
5 | #include <linux/pci.h> | |
6 | #include <linux/platform_device.h> | |
7 | #include <linux/of_device.h> | |
d7614de4 | 8 | #include <linux/module.h> |
d6ea3df0 | 9 | #include <linux/spi/pxa2xx_spi.h> |
afa93c90 | 10 | #include <linux/clk-provider.h> |
d6ea3df0 | 11 | |
b729bf34 MW |
12 | #include <linux/dmaengine.h> |
13 | #include <linux/platform_data/dma-dw.h> | |
14 | ||
d6ba32d5 CCE |
15 | enum { |
16 | PORT_CE4100, | |
17 | PORT_BYT, | |
39d36536 MW |
18 | PORT_BSW0, |
19 | PORT_BSW1, | |
20 | PORT_BSW2, | |
e5262d05 | 21 | PORT_QUARK_X1000, |
d6ba32d5 CCE |
22 | }; |
23 | ||
24 | struct pxa_spi_info { | |
25 | enum pxa_ssp_type type; | |
26 | int port_id; | |
27 | int num_chipselect; | |
afa93c90 | 28 | unsigned long max_clk_rate; |
b729bf34 MW |
29 | |
30 | /* DMA channel request parameters */ | |
31 | void *tx_param; | |
32 | void *rx_param; | |
d6ba32d5 CCE |
33 | }; |
34 | ||
b729bf34 MW |
35 | static struct dw_dma_slave byt_tx_param = { .dst_id = 0 }; |
36 | static struct dw_dma_slave byt_rx_param = { .src_id = 1 }; | |
37 | ||
39d36536 MW |
38 | static struct dw_dma_slave bsw0_tx_param = { .dst_id = 0 }; |
39 | static struct dw_dma_slave bsw0_rx_param = { .src_id = 1 }; | |
40 | static struct dw_dma_slave bsw1_tx_param = { .dst_id = 6 }; | |
41 | static struct dw_dma_slave bsw1_rx_param = { .src_id = 7 }; | |
42 | static struct dw_dma_slave bsw2_tx_param = { .dst_id = 8 }; | |
43 | static struct dw_dma_slave bsw2_rx_param = { .src_id = 9 }; | |
44 | ||
b729bf34 MW |
45 | static bool lpss_dma_filter(struct dma_chan *chan, void *param) |
46 | { | |
47 | struct dw_dma_slave *dws = param; | |
48 | ||
49 | if (dws->dma_dev != chan->device->dev) | |
50 | return false; | |
51 | ||
52 | chan->private = dws; | |
53 | return true; | |
54 | } | |
55 | ||
d6ba32d5 CCE |
56 | static struct pxa_spi_info spi_info_configs[] = { |
57 | [PORT_CE4100] = { | |
58 | .type = PXA25x_SSP, | |
59 | .port_id = -1, | |
60 | .num_chipselect = -1, | |
afa93c90 | 61 | .max_clk_rate = 3686400, |
d6ba32d5 CCE |
62 | }, |
63 | [PORT_BYT] = { | |
03fbf488 | 64 | .type = LPSS_BYT_SSP, |
d6ba32d5 CCE |
65 | .port_id = 0, |
66 | .num_chipselect = 1, | |
afa93c90 | 67 | .max_clk_rate = 50000000, |
b729bf34 MW |
68 | .tx_param = &byt_tx_param, |
69 | .rx_param = &byt_rx_param, | |
d6ba32d5 | 70 | }, |
39d36536 | 71 | [PORT_BSW0] = { |
03fbf488 | 72 | .type = LPSS_BYT_SSP, |
39d36536 MW |
73 | .port_id = 0, |
74 | .num_chipselect = 1, | |
75 | .max_clk_rate = 50000000, | |
76 | .tx_param = &bsw0_tx_param, | |
77 | .rx_param = &bsw0_rx_param, | |
78 | }, | |
79 | [PORT_BSW1] = { | |
03fbf488 | 80 | .type = LPSS_BYT_SSP, |
39d36536 MW |
81 | .port_id = 1, |
82 | .num_chipselect = 1, | |
83 | .max_clk_rate = 50000000, | |
84 | .tx_param = &bsw1_tx_param, | |
85 | .rx_param = &bsw1_rx_param, | |
86 | }, | |
87 | [PORT_BSW2] = { | |
03fbf488 | 88 | .type = LPSS_BYT_SSP, |
39d36536 MW |
89 | .port_id = 2, |
90 | .num_chipselect = 1, | |
91 | .max_clk_rate = 50000000, | |
92 | .tx_param = &bsw2_tx_param, | |
93 | .rx_param = &bsw2_rx_param, | |
d6ba32d5 | 94 | }, |
e5262d05 WC |
95 | [PORT_QUARK_X1000] = { |
96 | .type = QUARK_X1000_SSP, | |
97 | .port_id = -1, | |
98 | .num_chipselect = 1, | |
99 | .max_clk_rate = 50000000, | |
100 | }, | |
d6ba32d5 CCE |
101 | }; |
102 | ||
103 | static int pxa2xx_spi_pci_probe(struct pci_dev *dev, | |
d6ea3df0 SAS |
104 | const struct pci_device_id *ent) |
105 | { | |
0202775b | 106 | struct platform_device_info pi; |
d6ea3df0 | 107 | int ret; |
d6ea3df0 | 108 | struct platform_device *pdev; |
0f3e1d27 | 109 | struct pxa2xx_spi_master spi_pdata; |
d6ea3df0 | 110 | struct ssp_device *ssp; |
d6ba32d5 | 111 | struct pxa_spi_info *c; |
afa93c90 | 112 | char buf[40]; |
b729bf34 | 113 | struct pci_dev *dma_dev; |
d6ea3df0 | 114 | |
0202775b | 115 | ret = pcim_enable_device(dev); |
d6ea3df0 SAS |
116 | if (ret) |
117 | return ret; | |
118 | ||
0202775b | 119 | ret = pcim_iomap_regions(dev, 1 << 0, "PXA2xx SPI"); |
c1346340 | 120 | if (ret) |
d6ea3df0 | 121 | return ret; |
d6ea3df0 | 122 | |
d6ba32d5 CCE |
123 | c = &spi_info_configs[ent->driver_data]; |
124 | ||
0f3e1d27 | 125 | memset(&spi_pdata, 0, sizeof(spi_pdata)); |
d6ba32d5 CCE |
126 | spi_pdata.num_chipselect = (c->num_chipselect > 0) ? |
127 | c->num_chipselect : dev->devfn; | |
b729bf34 MW |
128 | |
129 | dma_dev = pci_get_slot(dev->bus, PCI_DEVFN(PCI_SLOT(dev->devfn), 0)); | |
130 | ||
131 | if (c->tx_param) { | |
132 | struct dw_dma_slave *slave = c->tx_param; | |
133 | ||
134 | slave->dma_dev = &dma_dev->dev; | |
135 | slave->src_master = 1; | |
136 | slave->dst_master = 0; | |
137 | } | |
138 | ||
139 | if (c->rx_param) { | |
140 | struct dw_dma_slave *slave = c->rx_param; | |
141 | ||
142 | slave->dma_dev = &dma_dev->dev; | |
143 | slave->src_master = 1; | |
144 | slave->dst_master = 0; | |
145 | } | |
146 | ||
147 | spi_pdata.dma_filter = lpss_dma_filter; | |
148 | spi_pdata.tx_param = c->tx_param; | |
149 | spi_pdata.rx_param = c->rx_param; | |
150 | spi_pdata.enable_dma = c->rx_param && c->tx_param; | |
d6ea3df0 | 151 | |
851bacf5 | 152 | ssp = &spi_pdata.ssp; |
d6ea3df0 | 153 | ssp->phys_base = pci_resource_start(dev, 0); |
0202775b | 154 | ssp->mmio_base = pcim_iomap_table(dev)[0]; |
d6ea3df0 | 155 | if (!ssp->mmio_base) { |
0202775b MW |
156 | dev_err(&dev->dev, "failed to ioremap() registers\n"); |
157 | return -EIO; | |
d6ea3df0 SAS |
158 | } |
159 | ssp->irq = dev->irq; | |
d6ba32d5 CCE |
160 | ssp->port_id = (c->port_id >= 0) ? c->port_id : dev->devfn; |
161 | ssp->type = c->type; | |
d6ea3df0 | 162 | |
afa93c90 CCE |
163 | snprintf(buf, sizeof(buf), "pxa2xx-spi.%d", ssp->port_id); |
164 | ssp->clk = clk_register_fixed_rate(&dev->dev, buf , NULL, | |
165 | CLK_IS_ROOT, c->max_clk_rate); | |
166 | if (IS_ERR(ssp->clk)) | |
167 | return PTR_ERR(ssp->clk); | |
168 | ||
0202775b MW |
169 | memset(&pi, 0, sizeof(pi)); |
170 | pi.parent = &dev->dev; | |
171 | pi.name = "pxa2xx-spi"; | |
172 | pi.id = ssp->port_id; | |
173 | pi.data = &spi_pdata; | |
174 | pi.size_data = sizeof(spi_pdata); | |
d6ea3df0 | 175 | |
0202775b | 176 | pdev = platform_device_register_full(&pi); |
afa93c90 CCE |
177 | if (IS_ERR(pdev)) { |
178 | clk_unregister(ssp->clk); | |
d77b5382 | 179 | return PTR_ERR(pdev); |
afa93c90 | 180 | } |
d6ea3df0 | 181 | |
851bacf5 | 182 | pci_set_drvdata(dev, pdev); |
d6ea3df0 | 183 | |
0202775b | 184 | return 0; |
d6ea3df0 SAS |
185 | } |
186 | ||
d6ba32d5 | 187 | static void pxa2xx_spi_pci_remove(struct pci_dev *dev) |
d6ea3df0 | 188 | { |
851bacf5 | 189 | struct platform_device *pdev = pci_get_drvdata(dev); |
afa93c90 CCE |
190 | struct pxa2xx_spi_master *spi_pdata; |
191 | ||
192 | spi_pdata = dev_get_platdata(&pdev->dev); | |
d6ea3df0 | 193 | |
851bacf5 | 194 | platform_device_unregister(pdev); |
afa93c90 | 195 | clk_unregister(spi_pdata->ssp.clk); |
d6ea3df0 SAS |
196 | } |
197 | ||
d6ba32d5 CCE |
198 | static const struct pci_device_id pxa2xx_spi_pci_devices[] = { |
199 | { PCI_VDEVICE(INTEL, 0x2e6a), PORT_CE4100 }, | |
e5262d05 | 200 | { PCI_VDEVICE(INTEL, 0x0935), PORT_QUARK_X1000 }, |
d6ba32d5 | 201 | { PCI_VDEVICE(INTEL, 0x0f0e), PORT_BYT }, |
39d36536 MW |
202 | { PCI_VDEVICE(INTEL, 0x228e), PORT_BSW0 }, |
203 | { PCI_VDEVICE(INTEL, 0x2290), PORT_BSW1 }, | |
204 | { PCI_VDEVICE(INTEL, 0x22ac), PORT_BSW2 }, | |
d6ea3df0 SAS |
205 | { }, |
206 | }; | |
d6ba32d5 | 207 | MODULE_DEVICE_TABLE(pci, pxa2xx_spi_pci_devices); |
d6ea3df0 | 208 | |
d6ba32d5 CCE |
209 | static struct pci_driver pxa2xx_spi_pci_driver = { |
210 | .name = "pxa2xx_spi_pci", | |
211 | .id_table = pxa2xx_spi_pci_devices, | |
212 | .probe = pxa2xx_spi_pci_probe, | |
213 | .remove = pxa2xx_spi_pci_remove, | |
d6ea3df0 SAS |
214 | }; |
215 | ||
d6ba32d5 | 216 | module_pci_driver(pxa2xx_spi_pci_driver); |
d6ea3df0 | 217 | |
d6ba32d5 | 218 | MODULE_DESCRIPTION("CE4100/LPSS PCI-SPI glue code for PXA's driver"); |
d6ea3df0 SAS |
219 | MODULE_LICENSE("GPL v2"); |
220 | MODULE_AUTHOR("Sebastian Andrzej Siewior <bigeasy@linutronix.de>"); |