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e0c9905e SS |
1 | /* |
2 | * Copyright (C) 2005 Stephen Street / StreetFire Sound Labs | |
a0d2642e | 3 | * Copyright (C) 2013, Intel Corporation |
e0c9905e SS |
4 | * |
5 | * This program is free software; you can redistribute it and/or modify | |
6 | * it under the terms of the GNU General Public License as published by | |
7 | * the Free Software Foundation; either version 2 of the License, or | |
8 | * (at your option) any later version. | |
9 | * | |
10 | * This program is distributed in the hope that it will be useful, | |
11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | * GNU General Public License for more details. | |
14 | * | |
15 | * You should have received a copy of the GNU General Public License | |
16 | * along with this program; if not, write to the Free Software | |
17 | * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. | |
18 | */ | |
19 | ||
20 | #include <linux/init.h> | |
21 | #include <linux/module.h> | |
22 | #include <linux/device.h> | |
23 | #include <linux/ioport.h> | |
24 | #include <linux/errno.h> | |
25 | #include <linux/interrupt.h> | |
26 | #include <linux/platform_device.h> | |
8348c259 | 27 | #include <linux/spi/pxa2xx_spi.h> |
e0c9905e SS |
28 | #include <linux/spi/spi.h> |
29 | #include <linux/workqueue.h> | |
e0c9905e | 30 | #include <linux/delay.h> |
a7bb3909 | 31 | #include <linux/gpio.h> |
5a0e3ad6 | 32 | #include <linux/slab.h> |
3343b7a6 | 33 | #include <linux/clk.h> |
7d94a505 | 34 | #include <linux/pm_runtime.h> |
a3496855 | 35 | #include <linux/acpi.h> |
e0c9905e SS |
36 | |
37 | #include <asm/io.h> | |
38 | #include <asm/irq.h> | |
e0c9905e | 39 | #include <asm/delay.h> |
e0c9905e | 40 | |
cd7bed00 | 41 | #include "spi-pxa2xx.h" |
e0c9905e SS |
42 | |
43 | MODULE_AUTHOR("Stephen Street"); | |
037cdafe | 44 | MODULE_DESCRIPTION("PXA2xx SSP SPI Controller"); |
e0c9905e | 45 | MODULE_LICENSE("GPL"); |
7e38c3c4 | 46 | MODULE_ALIAS("platform:pxa2xx-spi"); |
e0c9905e SS |
47 | |
48 | #define MAX_BUSES 3 | |
49 | ||
f1f640a9 VS |
50 | #define TIMOUT_DFLT 1000 |
51 | ||
b97c74bd NF |
52 | /* |
53 | * for testing SSCR1 changes that require SSP restart, basically | |
54 | * everything except the service and interrupt enables, the pxa270 developer | |
55 | * manual says only SSCR1_SCFR, SSCR1_SPH, SSCR1_SPO need to be in this | |
56 | * list, but the PXA255 dev man says all bits without really meaning the | |
57 | * service and interrupt enables | |
58 | */ | |
59 | #define SSCR1_CHANGE_MASK (SSCR1_TTELP | SSCR1_TTE | SSCR1_SCFR \ | |
8d94cc50 | 60 | | SSCR1_ECRA | SSCR1_ECRB | SSCR1_SCLKDIR \ |
b97c74bd NF |
61 | | SSCR1_SFRMDIR | SSCR1_RWOT | SSCR1_TRAIL \ |
62 | | SSCR1_IFS | SSCR1_STRF | SSCR1_EFWR \ | |
63 | | SSCR1_RFT | SSCR1_TFT | SSCR1_MWDS \ | |
64 | | SSCR1_SPH | SSCR1_SPO | SSCR1_LBM) | |
8d94cc50 | 65 | |
a0d2642e MW |
66 | #define LPSS_RX_THRESH_DFLT 64 |
67 | #define LPSS_TX_LOTHRESH_DFLT 160 | |
68 | #define LPSS_TX_HITHRESH_DFLT 224 | |
69 | ||
70 | /* Offset from drv_data->lpss_base */ | |
71 | #define SPI_CS_CONTROL 0x18 | |
72 | #define SPI_CS_CONTROL_SW_MODE BIT(0) | |
73 | #define SPI_CS_CONTROL_CS_HIGH BIT(1) | |
74 | ||
75 | static bool is_lpss_ssp(const struct driver_data *drv_data) | |
76 | { | |
77 | return drv_data->ssp_type == LPSS_SSP; | |
78 | } | |
79 | ||
80 | /* | |
81 | * Read and write LPSS SSP private registers. Caller must first check that | |
82 | * is_lpss_ssp() returns true before these can be called. | |
83 | */ | |
84 | static u32 __lpss_ssp_read_priv(struct driver_data *drv_data, unsigned offset) | |
85 | { | |
86 | WARN_ON(!drv_data->lpss_base); | |
87 | return readl(drv_data->lpss_base + offset); | |
88 | } | |
89 | ||
90 | static void __lpss_ssp_write_priv(struct driver_data *drv_data, | |
91 | unsigned offset, u32 value) | |
92 | { | |
93 | WARN_ON(!drv_data->lpss_base); | |
94 | writel(value, drv_data->lpss_base + offset); | |
95 | } | |
96 | ||
97 | /* | |
98 | * lpss_ssp_setup - perform LPSS SSP specific setup | |
99 | * @drv_data: pointer to the driver private data | |
100 | * | |
101 | * Perform LPSS SSP specific setup. This function must be called first if | |
102 | * one is going to use LPSS SSP private registers. | |
103 | */ | |
104 | static void lpss_ssp_setup(struct driver_data *drv_data) | |
105 | { | |
106 | unsigned offset = 0x400; | |
107 | u32 value, orig; | |
108 | ||
109 | if (!is_lpss_ssp(drv_data)) | |
110 | return; | |
111 | ||
112 | /* | |
113 | * Perform auto-detection of the LPSS SSP private registers. They | |
114 | * can be either at 1k or 2k offset from the base address. | |
115 | */ | |
116 | orig = readl(drv_data->ioaddr + offset + SPI_CS_CONTROL); | |
117 | ||
118 | value = orig | SPI_CS_CONTROL_SW_MODE; | |
119 | writel(value, drv_data->ioaddr + offset + SPI_CS_CONTROL); | |
120 | value = readl(drv_data->ioaddr + offset + SPI_CS_CONTROL); | |
121 | if (value != (orig | SPI_CS_CONTROL_SW_MODE)) { | |
122 | offset = 0x800; | |
123 | goto detection_done; | |
124 | } | |
125 | ||
126 | value &= ~SPI_CS_CONTROL_SW_MODE; | |
127 | writel(value, drv_data->ioaddr + offset + SPI_CS_CONTROL); | |
128 | value = readl(drv_data->ioaddr + offset + SPI_CS_CONTROL); | |
129 | if (value != orig) { | |
130 | offset = 0x800; | |
131 | goto detection_done; | |
132 | } | |
133 | ||
134 | detection_done: | |
135 | /* Now set the LPSS base */ | |
136 | drv_data->lpss_base = drv_data->ioaddr + offset; | |
137 | ||
138 | /* Enable software chip select control */ | |
139 | value = SPI_CS_CONTROL_SW_MODE | SPI_CS_CONTROL_CS_HIGH; | |
140 | __lpss_ssp_write_priv(drv_data, SPI_CS_CONTROL, value); | |
141 | } | |
142 | ||
143 | static void lpss_ssp_cs_control(struct driver_data *drv_data, bool enable) | |
144 | { | |
145 | u32 value; | |
146 | ||
147 | if (!is_lpss_ssp(drv_data)) | |
148 | return; | |
149 | ||
150 | value = __lpss_ssp_read_priv(drv_data, SPI_CS_CONTROL); | |
151 | if (enable) | |
152 | value &= ~SPI_CS_CONTROL_CS_HIGH; | |
153 | else | |
154 | value |= SPI_CS_CONTROL_CS_HIGH; | |
155 | __lpss_ssp_write_priv(drv_data, SPI_CS_CONTROL, value); | |
156 | } | |
157 | ||
a7bb3909 EM |
158 | static void cs_assert(struct driver_data *drv_data) |
159 | { | |
160 | struct chip_data *chip = drv_data->cur_chip; | |
161 | ||
2a8626a9 SAS |
162 | if (drv_data->ssp_type == CE4100_SSP) { |
163 | write_SSSR(drv_data->cur_chip->frm, drv_data->ioaddr); | |
164 | return; | |
165 | } | |
166 | ||
a7bb3909 EM |
167 | if (chip->cs_control) { |
168 | chip->cs_control(PXA2XX_CS_ASSERT); | |
169 | return; | |
170 | } | |
171 | ||
a0d2642e | 172 | if (gpio_is_valid(chip->gpio_cs)) { |
a7bb3909 | 173 | gpio_set_value(chip->gpio_cs, chip->gpio_cs_inverted); |
a0d2642e MW |
174 | return; |
175 | } | |
176 | ||
177 | lpss_ssp_cs_control(drv_data, true); | |
a7bb3909 EM |
178 | } |
179 | ||
180 | static void cs_deassert(struct driver_data *drv_data) | |
181 | { | |
182 | struct chip_data *chip = drv_data->cur_chip; | |
183 | ||
2a8626a9 SAS |
184 | if (drv_data->ssp_type == CE4100_SSP) |
185 | return; | |
186 | ||
a7bb3909 | 187 | if (chip->cs_control) { |
2b2562d3 | 188 | chip->cs_control(PXA2XX_CS_DEASSERT); |
a7bb3909 EM |
189 | return; |
190 | } | |
191 | ||
a0d2642e | 192 | if (gpio_is_valid(chip->gpio_cs)) { |
a7bb3909 | 193 | gpio_set_value(chip->gpio_cs, !chip->gpio_cs_inverted); |
a0d2642e MW |
194 | return; |
195 | } | |
196 | ||
197 | lpss_ssp_cs_control(drv_data, false); | |
a7bb3909 EM |
198 | } |
199 | ||
cd7bed00 | 200 | int pxa2xx_spi_flush(struct driver_data *drv_data) |
e0c9905e SS |
201 | { |
202 | unsigned long limit = loops_per_jiffy << 1; | |
203 | ||
cf43369d | 204 | void __iomem *reg = drv_data->ioaddr; |
e0c9905e SS |
205 | |
206 | do { | |
207 | while (read_SSSR(reg) & SSSR_RNE) { | |
208 | read_SSDR(reg); | |
209 | } | |
306c68aa | 210 | } while ((read_SSSR(reg) & SSSR_BSY) && --limit); |
2a8626a9 | 211 | write_SSSR_CS(drv_data, SSSR_ROR); |
e0c9905e SS |
212 | |
213 | return limit; | |
214 | } | |
215 | ||
8d94cc50 | 216 | static int null_writer(struct driver_data *drv_data) |
e0c9905e | 217 | { |
cf43369d | 218 | void __iomem *reg = drv_data->ioaddr; |
9708c121 | 219 | u8 n_bytes = drv_data->n_bytes; |
e0c9905e | 220 | |
4a25605f | 221 | if (((read_SSSR(reg) & SSSR_TFL_MASK) == SSSR_TFL_MASK) |
8d94cc50 SS |
222 | || (drv_data->tx == drv_data->tx_end)) |
223 | return 0; | |
224 | ||
225 | write_SSDR(0, reg); | |
226 | drv_data->tx += n_bytes; | |
227 | ||
228 | return 1; | |
e0c9905e SS |
229 | } |
230 | ||
8d94cc50 | 231 | static int null_reader(struct driver_data *drv_data) |
e0c9905e | 232 | { |
cf43369d | 233 | void __iomem *reg = drv_data->ioaddr; |
9708c121 | 234 | u8 n_bytes = drv_data->n_bytes; |
e0c9905e SS |
235 | |
236 | while ((read_SSSR(reg) & SSSR_RNE) | |
8d94cc50 | 237 | && (drv_data->rx < drv_data->rx_end)) { |
e0c9905e SS |
238 | read_SSDR(reg); |
239 | drv_data->rx += n_bytes; | |
240 | } | |
8d94cc50 SS |
241 | |
242 | return drv_data->rx == drv_data->rx_end; | |
e0c9905e SS |
243 | } |
244 | ||
8d94cc50 | 245 | static int u8_writer(struct driver_data *drv_data) |
e0c9905e | 246 | { |
cf43369d | 247 | void __iomem *reg = drv_data->ioaddr; |
e0c9905e | 248 | |
4a25605f | 249 | if (((read_SSSR(reg) & SSSR_TFL_MASK) == SSSR_TFL_MASK) |
8d94cc50 SS |
250 | || (drv_data->tx == drv_data->tx_end)) |
251 | return 0; | |
252 | ||
253 | write_SSDR(*(u8 *)(drv_data->tx), reg); | |
254 | ++drv_data->tx; | |
255 | ||
256 | return 1; | |
e0c9905e SS |
257 | } |
258 | ||
8d94cc50 | 259 | static int u8_reader(struct driver_data *drv_data) |
e0c9905e | 260 | { |
cf43369d | 261 | void __iomem *reg = drv_data->ioaddr; |
e0c9905e SS |
262 | |
263 | while ((read_SSSR(reg) & SSSR_RNE) | |
8d94cc50 | 264 | && (drv_data->rx < drv_data->rx_end)) { |
e0c9905e SS |
265 | *(u8 *)(drv_data->rx) = read_SSDR(reg); |
266 | ++drv_data->rx; | |
267 | } | |
8d94cc50 SS |
268 | |
269 | return drv_data->rx == drv_data->rx_end; | |
e0c9905e SS |
270 | } |
271 | ||
8d94cc50 | 272 | static int u16_writer(struct driver_data *drv_data) |
e0c9905e | 273 | { |
cf43369d | 274 | void __iomem *reg = drv_data->ioaddr; |
e0c9905e | 275 | |
4a25605f | 276 | if (((read_SSSR(reg) & SSSR_TFL_MASK) == SSSR_TFL_MASK) |
8d94cc50 SS |
277 | || (drv_data->tx == drv_data->tx_end)) |
278 | return 0; | |
279 | ||
280 | write_SSDR(*(u16 *)(drv_data->tx), reg); | |
281 | drv_data->tx += 2; | |
282 | ||
283 | return 1; | |
e0c9905e SS |
284 | } |
285 | ||
8d94cc50 | 286 | static int u16_reader(struct driver_data *drv_data) |
e0c9905e | 287 | { |
cf43369d | 288 | void __iomem *reg = drv_data->ioaddr; |
e0c9905e SS |
289 | |
290 | while ((read_SSSR(reg) & SSSR_RNE) | |
8d94cc50 | 291 | && (drv_data->rx < drv_data->rx_end)) { |
e0c9905e SS |
292 | *(u16 *)(drv_data->rx) = read_SSDR(reg); |
293 | drv_data->rx += 2; | |
294 | } | |
8d94cc50 SS |
295 | |
296 | return drv_data->rx == drv_data->rx_end; | |
e0c9905e | 297 | } |
8d94cc50 SS |
298 | |
299 | static int u32_writer(struct driver_data *drv_data) | |
e0c9905e | 300 | { |
cf43369d | 301 | void __iomem *reg = drv_data->ioaddr; |
e0c9905e | 302 | |
4a25605f | 303 | if (((read_SSSR(reg) & SSSR_TFL_MASK) == SSSR_TFL_MASK) |
8d94cc50 SS |
304 | || (drv_data->tx == drv_data->tx_end)) |
305 | return 0; | |
306 | ||
307 | write_SSDR(*(u32 *)(drv_data->tx), reg); | |
308 | drv_data->tx += 4; | |
309 | ||
310 | return 1; | |
e0c9905e SS |
311 | } |
312 | ||
8d94cc50 | 313 | static int u32_reader(struct driver_data *drv_data) |
e0c9905e | 314 | { |
cf43369d | 315 | void __iomem *reg = drv_data->ioaddr; |
e0c9905e SS |
316 | |
317 | while ((read_SSSR(reg) & SSSR_RNE) | |
8d94cc50 | 318 | && (drv_data->rx < drv_data->rx_end)) { |
e0c9905e SS |
319 | *(u32 *)(drv_data->rx) = read_SSDR(reg); |
320 | drv_data->rx += 4; | |
321 | } | |
8d94cc50 SS |
322 | |
323 | return drv_data->rx == drv_data->rx_end; | |
e0c9905e SS |
324 | } |
325 | ||
cd7bed00 | 326 | void *pxa2xx_spi_next_transfer(struct driver_data *drv_data) |
e0c9905e SS |
327 | { |
328 | struct spi_message *msg = drv_data->cur_msg; | |
329 | struct spi_transfer *trans = drv_data->cur_transfer; | |
330 | ||
331 | /* Move to next transfer */ | |
332 | if (trans->transfer_list.next != &msg->transfers) { | |
333 | drv_data->cur_transfer = | |
334 | list_entry(trans->transfer_list.next, | |
335 | struct spi_transfer, | |
336 | transfer_list); | |
337 | return RUNNING_STATE; | |
338 | } else | |
339 | return DONE_STATE; | |
340 | } | |
341 | ||
e0c9905e | 342 | /* caller already set message->status; dma and pio irqs are blocked */ |
5daa3ba0 | 343 | static void giveback(struct driver_data *drv_data) |
e0c9905e SS |
344 | { |
345 | struct spi_transfer* last_transfer; | |
5daa3ba0 | 346 | struct spi_message *msg; |
e0c9905e | 347 | |
5daa3ba0 SS |
348 | msg = drv_data->cur_msg; |
349 | drv_data->cur_msg = NULL; | |
350 | drv_data->cur_transfer = NULL; | |
5daa3ba0 SS |
351 | |
352 | last_transfer = list_entry(msg->transfers.prev, | |
e0c9905e SS |
353 | struct spi_transfer, |
354 | transfer_list); | |
355 | ||
8423597d NF |
356 | /* Delay if requested before any change in chip select */ |
357 | if (last_transfer->delay_usecs) | |
358 | udelay(last_transfer->delay_usecs); | |
359 | ||
360 | /* Drop chip select UNLESS cs_change is true or we are returning | |
361 | * a message with an error, or next message is for another chip | |
362 | */ | |
e0c9905e | 363 | if (!last_transfer->cs_change) |
a7bb3909 | 364 | cs_deassert(drv_data); |
8423597d NF |
365 | else { |
366 | struct spi_message *next_msg; | |
367 | ||
368 | /* Holding of cs was hinted, but we need to make sure | |
369 | * the next message is for the same chip. Don't waste | |
370 | * time with the following tests unless this was hinted. | |
371 | * | |
372 | * We cannot postpone this until pump_messages, because | |
373 | * after calling msg->complete (below) the driver that | |
374 | * sent the current message could be unloaded, which | |
375 | * could invalidate the cs_control() callback... | |
376 | */ | |
377 | ||
378 | /* get a pointer to the next message, if any */ | |
7f86bde9 | 379 | next_msg = spi_get_next_queued_message(drv_data->master); |
8423597d NF |
380 | |
381 | /* see if the next and current messages point | |
382 | * to the same chip | |
383 | */ | |
384 | if (next_msg && next_msg->spi != msg->spi) | |
385 | next_msg = NULL; | |
386 | if (!next_msg || msg->state == ERROR_STATE) | |
a7bb3909 | 387 | cs_deassert(drv_data); |
8423597d | 388 | } |
e0c9905e | 389 | |
7f86bde9 | 390 | spi_finalize_current_message(drv_data->master); |
a7bb3909 | 391 | drv_data->cur_chip = NULL; |
e0c9905e SS |
392 | } |
393 | ||
579d3bb2 SAS |
394 | static void reset_sccr1(struct driver_data *drv_data) |
395 | { | |
396 | void __iomem *reg = drv_data->ioaddr; | |
397 | struct chip_data *chip = drv_data->cur_chip; | |
398 | u32 sccr1_reg; | |
399 | ||
400 | sccr1_reg = read_SSCR1(reg) & ~drv_data->int_cr1; | |
401 | sccr1_reg &= ~SSCR1_RFT; | |
402 | sccr1_reg |= chip->threshold; | |
403 | write_SSCR1(sccr1_reg, reg); | |
404 | } | |
405 | ||
8d94cc50 | 406 | static void int_error_stop(struct driver_data *drv_data, const char* msg) |
e0c9905e | 407 | { |
cf43369d | 408 | void __iomem *reg = drv_data->ioaddr; |
e0c9905e | 409 | |
8d94cc50 | 410 | /* Stop and reset SSP */ |
2a8626a9 | 411 | write_SSSR_CS(drv_data, drv_data->clear_sr); |
579d3bb2 | 412 | reset_sccr1(drv_data); |
2a8626a9 | 413 | if (!pxa25x_ssp_comp(drv_data)) |
8d94cc50 | 414 | write_SSTO(0, reg); |
cd7bed00 | 415 | pxa2xx_spi_flush(drv_data); |
8d94cc50 | 416 | write_SSCR0(read_SSCR0(reg) & ~SSCR0_SSE, reg); |
e0c9905e | 417 | |
8d94cc50 | 418 | dev_err(&drv_data->pdev->dev, "%s\n", msg); |
e0c9905e | 419 | |
8d94cc50 SS |
420 | drv_data->cur_msg->state = ERROR_STATE; |
421 | tasklet_schedule(&drv_data->pump_transfers); | |
422 | } | |
5daa3ba0 | 423 | |
8d94cc50 SS |
424 | static void int_transfer_complete(struct driver_data *drv_data) |
425 | { | |
cf43369d | 426 | void __iomem *reg = drv_data->ioaddr; |
e0c9905e | 427 | |
8d94cc50 | 428 | /* Stop SSP */ |
2a8626a9 | 429 | write_SSSR_CS(drv_data, drv_data->clear_sr); |
579d3bb2 | 430 | reset_sccr1(drv_data); |
2a8626a9 | 431 | if (!pxa25x_ssp_comp(drv_data)) |
8d94cc50 | 432 | write_SSTO(0, reg); |
e0c9905e | 433 | |
25985edc | 434 | /* Update total byte transferred return count actual bytes read */ |
8d94cc50 SS |
435 | drv_data->cur_msg->actual_length += drv_data->len - |
436 | (drv_data->rx_end - drv_data->rx); | |
e0c9905e | 437 | |
8423597d NF |
438 | /* Transfer delays and chip select release are |
439 | * handled in pump_transfers or giveback | |
440 | */ | |
e0c9905e | 441 | |
8d94cc50 | 442 | /* Move to next transfer */ |
cd7bed00 | 443 | drv_data->cur_msg->state = pxa2xx_spi_next_transfer(drv_data); |
e0c9905e | 444 | |
8d94cc50 SS |
445 | /* Schedule transfer tasklet */ |
446 | tasklet_schedule(&drv_data->pump_transfers); | |
447 | } | |
e0c9905e | 448 | |
8d94cc50 SS |
449 | static irqreturn_t interrupt_transfer(struct driver_data *drv_data) |
450 | { | |
cf43369d | 451 | void __iomem *reg = drv_data->ioaddr; |
e0c9905e | 452 | |
8d94cc50 SS |
453 | u32 irq_mask = (read_SSCR1(reg) & SSCR1_TIE) ? |
454 | drv_data->mask_sr : drv_data->mask_sr & ~SSSR_TFS; | |
e0c9905e | 455 | |
8d94cc50 | 456 | u32 irq_status = read_SSSR(reg) & irq_mask; |
e0c9905e | 457 | |
8d94cc50 SS |
458 | if (irq_status & SSSR_ROR) { |
459 | int_error_stop(drv_data, "interrupt_transfer: fifo overrun"); | |
460 | return IRQ_HANDLED; | |
461 | } | |
e0c9905e | 462 | |
8d94cc50 SS |
463 | if (irq_status & SSSR_TINT) { |
464 | write_SSSR(SSSR_TINT, reg); | |
465 | if (drv_data->read(drv_data)) { | |
466 | int_transfer_complete(drv_data); | |
467 | return IRQ_HANDLED; | |
468 | } | |
469 | } | |
e0c9905e | 470 | |
8d94cc50 SS |
471 | /* Drain rx fifo, Fill tx fifo and prevent overruns */ |
472 | do { | |
473 | if (drv_data->read(drv_data)) { | |
474 | int_transfer_complete(drv_data); | |
475 | return IRQ_HANDLED; | |
476 | } | |
477 | } while (drv_data->write(drv_data)); | |
e0c9905e | 478 | |
8d94cc50 SS |
479 | if (drv_data->read(drv_data)) { |
480 | int_transfer_complete(drv_data); | |
481 | return IRQ_HANDLED; | |
482 | } | |
e0c9905e | 483 | |
8d94cc50 | 484 | if (drv_data->tx == drv_data->tx_end) { |
579d3bb2 SAS |
485 | u32 bytes_left; |
486 | u32 sccr1_reg; | |
487 | ||
488 | sccr1_reg = read_SSCR1(reg); | |
489 | sccr1_reg &= ~SSCR1_TIE; | |
490 | ||
491 | /* | |
492 | * PXA25x_SSP has no timeout, set up rx threshould for the | |
25985edc | 493 | * remaining RX bytes. |
579d3bb2 | 494 | */ |
2a8626a9 | 495 | if (pxa25x_ssp_comp(drv_data)) { |
579d3bb2 SAS |
496 | |
497 | sccr1_reg &= ~SSCR1_RFT; | |
498 | ||
499 | bytes_left = drv_data->rx_end - drv_data->rx; | |
500 | switch (drv_data->n_bytes) { | |
501 | case 4: | |
502 | bytes_left >>= 1; | |
503 | case 2: | |
504 | bytes_left >>= 1; | |
8d94cc50 | 505 | } |
579d3bb2 SAS |
506 | |
507 | if (bytes_left > RX_THRESH_DFLT) | |
508 | bytes_left = RX_THRESH_DFLT; | |
509 | ||
510 | sccr1_reg |= SSCR1_RxTresh(bytes_left); | |
e0c9905e | 511 | } |
579d3bb2 | 512 | write_SSCR1(sccr1_reg, reg); |
e0c9905e SS |
513 | } |
514 | ||
5daa3ba0 SS |
515 | /* We did something */ |
516 | return IRQ_HANDLED; | |
e0c9905e SS |
517 | } |
518 | ||
7d12e780 | 519 | static irqreturn_t ssp_int(int irq, void *dev_id) |
e0c9905e | 520 | { |
c7bec5ab | 521 | struct driver_data *drv_data = dev_id; |
cf43369d | 522 | void __iomem *reg = drv_data->ioaddr; |
7d94a505 | 523 | u32 sccr1_reg; |
49cbb1e0 SAS |
524 | u32 mask = drv_data->mask_sr; |
525 | u32 status; | |
526 | ||
7d94a505 MW |
527 | /* |
528 | * The IRQ might be shared with other peripherals so we must first | |
529 | * check that are we RPM suspended or not. If we are we assume that | |
530 | * the IRQ was not for us (we shouldn't be RPM suspended when the | |
531 | * interrupt is enabled). | |
532 | */ | |
533 | if (pm_runtime_suspended(&drv_data->pdev->dev)) | |
534 | return IRQ_NONE; | |
535 | ||
536 | sccr1_reg = read_SSCR1(reg); | |
49cbb1e0 SAS |
537 | status = read_SSSR(reg); |
538 | ||
539 | /* Ignore possible writes if we don't need to write */ | |
540 | if (!(sccr1_reg & SSCR1_TIE)) | |
541 | mask &= ~SSSR_TFS; | |
542 | ||
543 | if (!(status & mask)) | |
544 | return IRQ_NONE; | |
e0c9905e SS |
545 | |
546 | if (!drv_data->cur_msg) { | |
5daa3ba0 SS |
547 | |
548 | write_SSCR0(read_SSCR0(reg) & ~SSCR0_SSE, reg); | |
549 | write_SSCR1(read_SSCR1(reg) & ~drv_data->int_cr1, reg); | |
2a8626a9 | 550 | if (!pxa25x_ssp_comp(drv_data)) |
5daa3ba0 | 551 | write_SSTO(0, reg); |
2a8626a9 | 552 | write_SSSR_CS(drv_data, drv_data->clear_sr); |
5daa3ba0 | 553 | |
e0c9905e | 554 | dev_err(&drv_data->pdev->dev, "bad message state " |
8d94cc50 | 555 | "in interrupt handler\n"); |
5daa3ba0 | 556 | |
e0c9905e SS |
557 | /* Never fail */ |
558 | return IRQ_HANDLED; | |
559 | } | |
560 | ||
561 | return drv_data->transfer_handler(drv_data); | |
562 | } | |
563 | ||
3343b7a6 | 564 | static unsigned int ssp_get_clk_div(struct driver_data *drv_data, int rate) |
2f1a74e5 | 565 | { |
3343b7a6 MW |
566 | unsigned long ssp_clk = drv_data->max_clk_rate; |
567 | const struct ssp_device *ssp = drv_data->ssp; | |
568 | ||
569 | rate = min_t(int, ssp_clk, rate); | |
2f1a74e5 | 570 | |
2a8626a9 | 571 | if (ssp->type == PXA25x_SSP || ssp->type == CE4100_SSP) |
2f1a74e5 | 572 | return ((ssp_clk / (2 * rate) - 1) & 0xff) << 8; |
573 | else | |
574 | return ((ssp_clk / rate - 1) & 0xfff) << 8; | |
575 | } | |
576 | ||
e0c9905e SS |
577 | static void pump_transfers(unsigned long data) |
578 | { | |
579 | struct driver_data *drv_data = (struct driver_data *)data; | |
580 | struct spi_message *message = NULL; | |
581 | struct spi_transfer *transfer = NULL; | |
582 | struct spi_transfer *previous = NULL; | |
583 | struct chip_data *chip = NULL; | |
cf43369d | 584 | void __iomem *reg = drv_data->ioaddr; |
9708c121 SS |
585 | u32 clk_div = 0; |
586 | u8 bits = 0; | |
587 | u32 speed = 0; | |
588 | u32 cr0; | |
8d94cc50 SS |
589 | u32 cr1; |
590 | u32 dma_thresh = drv_data->cur_chip->dma_threshold; | |
591 | u32 dma_burst = drv_data->cur_chip->dma_burst_size; | |
e0c9905e SS |
592 | |
593 | /* Get current state information */ | |
594 | message = drv_data->cur_msg; | |
595 | transfer = drv_data->cur_transfer; | |
596 | chip = drv_data->cur_chip; | |
597 | ||
598 | /* Handle for abort */ | |
599 | if (message->state == ERROR_STATE) { | |
600 | message->status = -EIO; | |
5daa3ba0 | 601 | giveback(drv_data); |
e0c9905e SS |
602 | return; |
603 | } | |
604 | ||
605 | /* Handle end of message */ | |
606 | if (message->state == DONE_STATE) { | |
607 | message->status = 0; | |
5daa3ba0 | 608 | giveback(drv_data); |
e0c9905e SS |
609 | return; |
610 | } | |
611 | ||
8423597d | 612 | /* Delay if requested at end of transfer before CS change */ |
e0c9905e SS |
613 | if (message->state == RUNNING_STATE) { |
614 | previous = list_entry(transfer->transfer_list.prev, | |
615 | struct spi_transfer, | |
616 | transfer_list); | |
617 | if (previous->delay_usecs) | |
618 | udelay(previous->delay_usecs); | |
8423597d NF |
619 | |
620 | /* Drop chip select only if cs_change is requested */ | |
621 | if (previous->cs_change) | |
a7bb3909 | 622 | cs_deassert(drv_data); |
e0c9905e SS |
623 | } |
624 | ||
cd7bed00 MW |
625 | /* Check if we can DMA this transfer */ |
626 | if (!pxa2xx_spi_dma_is_possible(transfer->len) && chip->enable_dma) { | |
7e964455 NF |
627 | |
628 | /* reject already-mapped transfers; PIO won't always work */ | |
629 | if (message->is_dma_mapped | |
630 | || transfer->rx_dma || transfer->tx_dma) { | |
631 | dev_err(&drv_data->pdev->dev, | |
632 | "pump_transfers: mapped transfer length " | |
20b918dc | 633 | "of %u is greater than %d\n", |
7e964455 NF |
634 | transfer->len, MAX_DMA_LEN); |
635 | message->status = -EINVAL; | |
636 | giveback(drv_data); | |
637 | return; | |
638 | } | |
639 | ||
640 | /* warn ... we force this to PIO mode */ | |
641 | if (printk_ratelimit()) | |
642 | dev_warn(&message->spi->dev, "pump_transfers: " | |
643 | "DMA disabled for transfer length %ld " | |
644 | "greater than %d\n", | |
645 | (long)drv_data->len, MAX_DMA_LEN); | |
8d94cc50 SS |
646 | } |
647 | ||
e0c9905e | 648 | /* Setup the transfer state based on the type of transfer */ |
cd7bed00 | 649 | if (pxa2xx_spi_flush(drv_data) == 0) { |
e0c9905e SS |
650 | dev_err(&drv_data->pdev->dev, "pump_transfers: flush failed\n"); |
651 | message->status = -EIO; | |
5daa3ba0 | 652 | giveback(drv_data); |
e0c9905e SS |
653 | return; |
654 | } | |
9708c121 | 655 | drv_data->n_bytes = chip->n_bytes; |
e0c9905e SS |
656 | drv_data->tx = (void *)transfer->tx_buf; |
657 | drv_data->tx_end = drv_data->tx + transfer->len; | |
658 | drv_data->rx = transfer->rx_buf; | |
659 | drv_data->rx_end = drv_data->rx + transfer->len; | |
660 | drv_data->rx_dma = transfer->rx_dma; | |
661 | drv_data->tx_dma = transfer->tx_dma; | |
cd7bed00 | 662 | drv_data->len = transfer->len; |
e0c9905e SS |
663 | drv_data->write = drv_data->tx ? chip->write : null_writer; |
664 | drv_data->read = drv_data->rx ? chip->read : null_reader; | |
9708c121 SS |
665 | |
666 | /* Change speed and bit per word on a per transfer */ | |
8d94cc50 | 667 | cr0 = chip->cr0; |
9708c121 SS |
668 | if (transfer->speed_hz || transfer->bits_per_word) { |
669 | ||
9708c121 SS |
670 | bits = chip->bits_per_word; |
671 | speed = chip->speed_hz; | |
672 | ||
673 | if (transfer->speed_hz) | |
674 | speed = transfer->speed_hz; | |
675 | ||
676 | if (transfer->bits_per_word) | |
677 | bits = transfer->bits_per_word; | |
678 | ||
3343b7a6 | 679 | clk_div = ssp_get_clk_div(drv_data, speed); |
9708c121 SS |
680 | |
681 | if (bits <= 8) { | |
682 | drv_data->n_bytes = 1; | |
9708c121 SS |
683 | drv_data->read = drv_data->read != null_reader ? |
684 | u8_reader : null_reader; | |
685 | drv_data->write = drv_data->write != null_writer ? | |
686 | u8_writer : null_writer; | |
687 | } else if (bits <= 16) { | |
688 | drv_data->n_bytes = 2; | |
9708c121 SS |
689 | drv_data->read = drv_data->read != null_reader ? |
690 | u16_reader : null_reader; | |
691 | drv_data->write = drv_data->write != null_writer ? | |
692 | u16_writer : null_writer; | |
693 | } else if (bits <= 32) { | |
694 | drv_data->n_bytes = 4; | |
9708c121 SS |
695 | drv_data->read = drv_data->read != null_reader ? |
696 | u32_reader : null_reader; | |
697 | drv_data->write = drv_data->write != null_writer ? | |
698 | u32_writer : null_writer; | |
699 | } | |
8d94cc50 SS |
700 | /* if bits/word is changed in dma mode, then must check the |
701 | * thresholds and burst also */ | |
702 | if (chip->enable_dma) { | |
cd7bed00 MW |
703 | if (pxa2xx_spi_set_dma_burst_and_threshold(chip, |
704 | message->spi, | |
8d94cc50 SS |
705 | bits, &dma_burst, |
706 | &dma_thresh)) | |
707 | if (printk_ratelimit()) | |
708 | dev_warn(&message->spi->dev, | |
7e964455 | 709 | "pump_transfers: " |
8d94cc50 SS |
710 | "DMA burst size reduced to " |
711 | "match bits_per_word\n"); | |
712 | } | |
9708c121 SS |
713 | |
714 | cr0 = clk_div | |
715 | | SSCR0_Motorola | |
5daa3ba0 | 716 | | SSCR0_DataSize(bits > 16 ? bits - 16 : bits) |
9708c121 SS |
717 | | SSCR0_SSE |
718 | | (bits > 16 ? SSCR0_EDSS : 0); | |
9708c121 SS |
719 | } |
720 | ||
e0c9905e SS |
721 | message->state = RUNNING_STATE; |
722 | ||
7e964455 | 723 | drv_data->dma_mapped = 0; |
cd7bed00 MW |
724 | if (pxa2xx_spi_dma_is_possible(drv_data->len)) |
725 | drv_data->dma_mapped = pxa2xx_spi_map_dma_buffers(drv_data); | |
7e964455 | 726 | if (drv_data->dma_mapped) { |
e0c9905e SS |
727 | |
728 | /* Ensure we have the correct interrupt handler */ | |
cd7bed00 MW |
729 | drv_data->transfer_handler = pxa2xx_spi_dma_transfer; |
730 | ||
731 | pxa2xx_spi_dma_prepare(drv_data, dma_burst); | |
e0c9905e | 732 | |
8d94cc50 SS |
733 | /* Clear status and start DMA engine */ |
734 | cr1 = chip->cr1 | dma_thresh | drv_data->dma_cr1; | |
e0c9905e | 735 | write_SSSR(drv_data->clear_sr, reg); |
cd7bed00 MW |
736 | |
737 | pxa2xx_spi_dma_start(drv_data); | |
e0c9905e SS |
738 | } else { |
739 | /* Ensure we have the correct interrupt handler */ | |
740 | drv_data->transfer_handler = interrupt_transfer; | |
741 | ||
8d94cc50 SS |
742 | /* Clear status */ |
743 | cr1 = chip->cr1 | chip->threshold | drv_data->int_cr1; | |
2a8626a9 | 744 | write_SSSR_CS(drv_data, drv_data->clear_sr); |
8d94cc50 SS |
745 | } |
746 | ||
a0d2642e MW |
747 | if (is_lpss_ssp(drv_data)) { |
748 | if ((read_SSIRF(reg) & 0xff) != chip->lpss_rx_threshold) | |
749 | write_SSIRF(chip->lpss_rx_threshold, reg); | |
750 | if ((read_SSITF(reg) & 0xffff) != chip->lpss_tx_threshold) | |
751 | write_SSITF(chip->lpss_tx_threshold, reg); | |
752 | } | |
753 | ||
8d94cc50 SS |
754 | /* see if we need to reload the config registers */ |
755 | if ((read_SSCR0(reg) != cr0) | |
756 | || (read_SSCR1(reg) & SSCR1_CHANGE_MASK) != | |
757 | (cr1 & SSCR1_CHANGE_MASK)) { | |
758 | ||
b97c74bd | 759 | /* stop the SSP, and update the other bits */ |
8d94cc50 | 760 | write_SSCR0(cr0 & ~SSCR0_SSE, reg); |
2a8626a9 | 761 | if (!pxa25x_ssp_comp(drv_data)) |
e0c9905e | 762 | write_SSTO(chip->timeout, reg); |
b97c74bd NF |
763 | /* first set CR1 without interrupt and service enables */ |
764 | write_SSCR1(cr1 & SSCR1_CHANGE_MASK, reg); | |
765 | /* restart the SSP */ | |
8d94cc50 | 766 | write_SSCR0(cr0, reg); |
b97c74bd | 767 | |
8d94cc50 | 768 | } else { |
2a8626a9 | 769 | if (!pxa25x_ssp_comp(drv_data)) |
8d94cc50 | 770 | write_SSTO(chip->timeout, reg); |
e0c9905e | 771 | } |
b97c74bd | 772 | |
a7bb3909 | 773 | cs_assert(drv_data); |
b97c74bd NF |
774 | |
775 | /* after chip select, release the data by enabling service | |
776 | * requests and interrupts, without changing any mode bits */ | |
777 | write_SSCR1(cr1, reg); | |
e0c9905e SS |
778 | } |
779 | ||
7f86bde9 MW |
780 | static int pxa2xx_spi_transfer_one_message(struct spi_master *master, |
781 | struct spi_message *msg) | |
e0c9905e | 782 | { |
7f86bde9 | 783 | struct driver_data *drv_data = spi_master_get_devdata(master); |
e0c9905e | 784 | |
7f86bde9 | 785 | drv_data->cur_msg = msg; |
e0c9905e SS |
786 | /* Initial message state*/ |
787 | drv_data->cur_msg->state = START_STATE; | |
788 | drv_data->cur_transfer = list_entry(drv_data->cur_msg->transfers.next, | |
789 | struct spi_transfer, | |
790 | transfer_list); | |
791 | ||
8d94cc50 SS |
792 | /* prepare to setup the SSP, in pump_transfers, using the per |
793 | * chip configuration */ | |
e0c9905e | 794 | drv_data->cur_chip = spi_get_ctldata(drv_data->cur_msg->spi); |
e0c9905e SS |
795 | |
796 | /* Mark as busy and launch transfers */ | |
797 | tasklet_schedule(&drv_data->pump_transfers); | |
e0c9905e SS |
798 | return 0; |
799 | } | |
800 | ||
7d94a505 MW |
801 | static int pxa2xx_spi_prepare_transfer(struct spi_master *master) |
802 | { | |
803 | struct driver_data *drv_data = spi_master_get_devdata(master); | |
804 | ||
805 | pm_runtime_get_sync(&drv_data->pdev->dev); | |
806 | return 0; | |
807 | } | |
808 | ||
809 | static int pxa2xx_spi_unprepare_transfer(struct spi_master *master) | |
810 | { | |
811 | struct driver_data *drv_data = spi_master_get_devdata(master); | |
812 | ||
813 | /* Disable the SSP now */ | |
814 | write_SSCR0(read_SSCR0(drv_data->ioaddr) & ~SSCR0_SSE, | |
815 | drv_data->ioaddr); | |
816 | ||
817 | pm_runtime_mark_last_busy(&drv_data->pdev->dev); | |
818 | pm_runtime_put_autosuspend(&drv_data->pdev->dev); | |
819 | return 0; | |
820 | } | |
821 | ||
a7bb3909 EM |
822 | static int setup_cs(struct spi_device *spi, struct chip_data *chip, |
823 | struct pxa2xx_spi_chip *chip_info) | |
824 | { | |
825 | int err = 0; | |
826 | ||
827 | if (chip == NULL || chip_info == NULL) | |
828 | return 0; | |
829 | ||
830 | /* NOTE: setup() can be called multiple times, possibly with | |
831 | * different chip_info, release previously requested GPIO | |
832 | */ | |
833 | if (gpio_is_valid(chip->gpio_cs)) | |
834 | gpio_free(chip->gpio_cs); | |
835 | ||
836 | /* If (*cs_control) is provided, ignore GPIO chip select */ | |
837 | if (chip_info->cs_control) { | |
838 | chip->cs_control = chip_info->cs_control; | |
839 | return 0; | |
840 | } | |
841 | ||
842 | if (gpio_is_valid(chip_info->gpio_cs)) { | |
843 | err = gpio_request(chip_info->gpio_cs, "SPI_CS"); | |
844 | if (err) { | |
845 | dev_err(&spi->dev, "failed to request chip select " | |
846 | "GPIO%d\n", chip_info->gpio_cs); | |
847 | return err; | |
848 | } | |
849 | ||
850 | chip->gpio_cs = chip_info->gpio_cs; | |
851 | chip->gpio_cs_inverted = spi->mode & SPI_CS_HIGH; | |
852 | ||
853 | err = gpio_direction_output(chip->gpio_cs, | |
854 | !chip->gpio_cs_inverted); | |
855 | } | |
856 | ||
857 | return err; | |
858 | } | |
859 | ||
e0c9905e SS |
860 | static int setup(struct spi_device *spi) |
861 | { | |
862 | struct pxa2xx_spi_chip *chip_info = NULL; | |
863 | struct chip_data *chip; | |
864 | struct driver_data *drv_data = spi_master_get_devdata(spi->master); | |
865 | unsigned int clk_div; | |
a0d2642e MW |
866 | uint tx_thres, tx_hi_thres, rx_thres; |
867 | ||
868 | if (is_lpss_ssp(drv_data)) { | |
869 | tx_thres = LPSS_TX_LOTHRESH_DFLT; | |
870 | tx_hi_thres = LPSS_TX_HITHRESH_DFLT; | |
871 | rx_thres = LPSS_RX_THRESH_DFLT; | |
872 | } else { | |
873 | tx_thres = TX_THRESH_DFLT; | |
874 | tx_hi_thres = 0; | |
875 | rx_thres = RX_THRESH_DFLT; | |
876 | } | |
e0c9905e | 877 | |
2a8626a9 | 878 | if (!pxa25x_ssp_comp(drv_data) |
8d94cc50 SS |
879 | && (spi->bits_per_word < 4 || spi->bits_per_word > 32)) { |
880 | dev_err(&spi->dev, "failed setup: ssp_type=%d, bits/wrd=%d " | |
881 | "b/w not 4-32 for type non-PXA25x_SSP\n", | |
882 | drv_data->ssp_type, spi->bits_per_word); | |
e0c9905e | 883 | return -EINVAL; |
2a8626a9 | 884 | } else if (pxa25x_ssp_comp(drv_data) |
8d94cc50 SS |
885 | && (spi->bits_per_word < 4 |
886 | || spi->bits_per_word > 16)) { | |
887 | dev_err(&spi->dev, "failed setup: ssp_type=%d, bits/wrd=%d " | |
888 | "b/w not 4-16 for type PXA25x_SSP\n", | |
889 | drv_data->ssp_type, spi->bits_per_word); | |
e0c9905e | 890 | return -EINVAL; |
8d94cc50 | 891 | } |
e0c9905e | 892 | |
8d94cc50 | 893 | /* Only alloc on first setup */ |
e0c9905e | 894 | chip = spi_get_ctldata(spi); |
8d94cc50 | 895 | if (!chip) { |
e0c9905e | 896 | chip = kzalloc(sizeof(struct chip_data), GFP_KERNEL); |
8d94cc50 SS |
897 | if (!chip) { |
898 | dev_err(&spi->dev, | |
899 | "failed setup: can't allocate chip data\n"); | |
e0c9905e | 900 | return -ENOMEM; |
8d94cc50 | 901 | } |
e0c9905e | 902 | |
2a8626a9 SAS |
903 | if (drv_data->ssp_type == CE4100_SSP) { |
904 | if (spi->chip_select > 4) { | |
905 | dev_err(&spi->dev, "failed setup: " | |
906 | "cs number must not be > 4.\n"); | |
907 | kfree(chip); | |
908 | return -EINVAL; | |
909 | } | |
910 | ||
911 | chip->frm = spi->chip_select; | |
912 | } else | |
913 | chip->gpio_cs = -1; | |
e0c9905e | 914 | chip->enable_dma = 0; |
f1f640a9 | 915 | chip->timeout = TIMOUT_DFLT; |
e0c9905e SS |
916 | } |
917 | ||
8d94cc50 SS |
918 | /* protocol drivers may change the chip settings, so... |
919 | * if chip_info exists, use it */ | |
920 | chip_info = spi->controller_data; | |
921 | ||
e0c9905e | 922 | /* chip_info isn't always needed */ |
8d94cc50 | 923 | chip->cr1 = 0; |
e0c9905e | 924 | if (chip_info) { |
f1f640a9 VS |
925 | if (chip_info->timeout) |
926 | chip->timeout = chip_info->timeout; | |
927 | if (chip_info->tx_threshold) | |
928 | tx_thres = chip_info->tx_threshold; | |
a0d2642e MW |
929 | if (chip_info->tx_hi_threshold) |
930 | tx_hi_thres = chip_info->tx_hi_threshold; | |
f1f640a9 VS |
931 | if (chip_info->rx_threshold) |
932 | rx_thres = chip_info->rx_threshold; | |
933 | chip->enable_dma = drv_data->master_info->enable_dma; | |
e0c9905e | 934 | chip->dma_threshold = 0; |
e0c9905e SS |
935 | if (chip_info->enable_loopback) |
936 | chip->cr1 = SSCR1_LBM; | |
a3496855 MW |
937 | } else if (ACPI_HANDLE(&spi->dev)) { |
938 | /* | |
939 | * Slave devices enumerated from ACPI namespace don't | |
940 | * usually have chip_info but we still might want to use | |
941 | * DMA with them. | |
942 | */ | |
943 | chip->enable_dma = drv_data->master_info->enable_dma; | |
e0c9905e SS |
944 | } |
945 | ||
f1f640a9 VS |
946 | chip->threshold = (SSCR1_RxTresh(rx_thres) & SSCR1_RFT) | |
947 | (SSCR1_TxTresh(tx_thres) & SSCR1_TFT); | |
948 | ||
a0d2642e MW |
949 | chip->lpss_rx_threshold = SSIRF_RxThresh(rx_thres); |
950 | chip->lpss_tx_threshold = SSITF_TxLoThresh(tx_thres) | |
951 | | SSITF_TxHiThresh(tx_hi_thres); | |
952 | ||
8d94cc50 SS |
953 | /* set dma burst and threshold outside of chip_info path so that if |
954 | * chip_info goes away after setting chip->enable_dma, the | |
955 | * burst and threshold can still respond to changes in bits_per_word */ | |
956 | if (chip->enable_dma) { | |
957 | /* set up legal burst and threshold for dma */ | |
cd7bed00 MW |
958 | if (pxa2xx_spi_set_dma_burst_and_threshold(chip, spi, |
959 | spi->bits_per_word, | |
8d94cc50 SS |
960 | &chip->dma_burst_size, |
961 | &chip->dma_threshold)) { | |
962 | dev_warn(&spi->dev, "in setup: DMA burst size reduced " | |
963 | "to match bits_per_word\n"); | |
964 | } | |
965 | } | |
966 | ||
3343b7a6 | 967 | clk_div = ssp_get_clk_div(drv_data, spi->max_speed_hz); |
9708c121 | 968 | chip->speed_hz = spi->max_speed_hz; |
e0c9905e SS |
969 | |
970 | chip->cr0 = clk_div | |
971 | | SSCR0_Motorola | |
5daa3ba0 SS |
972 | | SSCR0_DataSize(spi->bits_per_word > 16 ? |
973 | spi->bits_per_word - 16 : spi->bits_per_word) | |
e0c9905e SS |
974 | | SSCR0_SSE |
975 | | (spi->bits_per_word > 16 ? SSCR0_EDSS : 0); | |
7f6ee1ad JC |
976 | chip->cr1 &= ~(SSCR1_SPO | SSCR1_SPH); |
977 | chip->cr1 |= (((spi->mode & SPI_CPHA) != 0) ? SSCR1_SPH : 0) | |
978 | | (((spi->mode & SPI_CPOL) != 0) ? SSCR1_SPO : 0); | |
e0c9905e | 979 | |
b833172f MW |
980 | if (spi->mode & SPI_LOOP) |
981 | chip->cr1 |= SSCR1_LBM; | |
982 | ||
e0c9905e | 983 | /* NOTE: PXA25x_SSP _could_ use external clocking ... */ |
2a8626a9 | 984 | if (!pxa25x_ssp_comp(drv_data)) |
7d077197 | 985 | dev_dbg(&spi->dev, "%ld Hz actual, %s\n", |
3343b7a6 | 986 | drv_data->max_clk_rate |
c9840daa EM |
987 | / (1 + ((chip->cr0 & SSCR0_SCR(0xfff)) >> 8)), |
988 | chip->enable_dma ? "DMA" : "PIO"); | |
e0c9905e | 989 | else |
7d077197 | 990 | dev_dbg(&spi->dev, "%ld Hz actual, %s\n", |
3343b7a6 | 991 | drv_data->max_clk_rate / 2 |
c9840daa EM |
992 | / (1 + ((chip->cr0 & SSCR0_SCR(0x0ff)) >> 8)), |
993 | chip->enable_dma ? "DMA" : "PIO"); | |
e0c9905e SS |
994 | |
995 | if (spi->bits_per_word <= 8) { | |
996 | chip->n_bytes = 1; | |
e0c9905e SS |
997 | chip->read = u8_reader; |
998 | chip->write = u8_writer; | |
999 | } else if (spi->bits_per_word <= 16) { | |
1000 | chip->n_bytes = 2; | |
e0c9905e SS |
1001 | chip->read = u16_reader; |
1002 | chip->write = u16_writer; | |
1003 | } else if (spi->bits_per_word <= 32) { | |
1004 | chip->cr0 |= SSCR0_EDSS; | |
1005 | chip->n_bytes = 4; | |
e0c9905e SS |
1006 | chip->read = u32_reader; |
1007 | chip->write = u32_writer; | |
1008 | } else { | |
1009 | dev_err(&spi->dev, "invalid wordsize\n"); | |
e0c9905e SS |
1010 | return -ENODEV; |
1011 | } | |
9708c121 | 1012 | chip->bits_per_word = spi->bits_per_word; |
e0c9905e SS |
1013 | |
1014 | spi_set_ctldata(spi, chip); | |
1015 | ||
2a8626a9 SAS |
1016 | if (drv_data->ssp_type == CE4100_SSP) |
1017 | return 0; | |
1018 | ||
a7bb3909 | 1019 | return setup_cs(spi, chip, chip_info); |
e0c9905e SS |
1020 | } |
1021 | ||
0ffa0285 | 1022 | static void cleanup(struct spi_device *spi) |
e0c9905e | 1023 | { |
0ffa0285 | 1024 | struct chip_data *chip = spi_get_ctldata(spi); |
2a8626a9 | 1025 | struct driver_data *drv_data = spi_master_get_devdata(spi->master); |
e0c9905e | 1026 | |
7348d82a DR |
1027 | if (!chip) |
1028 | return; | |
1029 | ||
2a8626a9 | 1030 | if (drv_data->ssp_type != CE4100_SSP && gpio_is_valid(chip->gpio_cs)) |
a7bb3909 EM |
1031 | gpio_free(chip->gpio_cs); |
1032 | ||
e0c9905e SS |
1033 | kfree(chip); |
1034 | } | |
1035 | ||
a3496855 MW |
1036 | #ifdef CONFIG_ACPI |
1037 | static int pxa2xx_spi_acpi_add_dma(struct acpi_resource *res, void *data) | |
1038 | { | |
1039 | struct pxa2xx_spi_master *pdata = data; | |
1040 | ||
1041 | if (res->type == ACPI_RESOURCE_TYPE_FIXED_DMA) { | |
1042 | const struct acpi_resource_fixed_dma *dma; | |
1043 | ||
1044 | dma = &res->data.fixed_dma; | |
1045 | if (pdata->tx_slave_id < 0) { | |
1046 | pdata->tx_slave_id = dma->request_lines; | |
1047 | pdata->tx_chan_id = dma->channels; | |
1048 | } else if (pdata->rx_slave_id < 0) { | |
1049 | pdata->rx_slave_id = dma->request_lines; | |
1050 | pdata->rx_chan_id = dma->channels; | |
1051 | } | |
1052 | } | |
1053 | ||
1054 | /* Tell the ACPI core to skip this resource */ | |
1055 | return 1; | |
1056 | } | |
1057 | ||
1058 | static struct pxa2xx_spi_master * | |
1059 | pxa2xx_spi_acpi_get_pdata(struct platform_device *pdev) | |
1060 | { | |
1061 | struct pxa2xx_spi_master *pdata; | |
1062 | struct list_head resource_list; | |
1063 | struct acpi_device *adev; | |
1064 | struct ssp_device *ssp; | |
1065 | struct resource *res; | |
1066 | int devid; | |
1067 | ||
1068 | if (!ACPI_HANDLE(&pdev->dev) || | |
1069 | acpi_bus_get_device(ACPI_HANDLE(&pdev->dev), &adev)) | |
1070 | return NULL; | |
1071 | ||
1072 | pdata = devm_kzalloc(&pdev->dev, sizeof(*ssp), GFP_KERNEL); | |
1073 | if (!pdata) { | |
1074 | dev_err(&pdev->dev, | |
1075 | "failed to allocate memory for platform data\n"); | |
1076 | return NULL; | |
1077 | } | |
1078 | ||
1079 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
1080 | if (!res) | |
1081 | return NULL; | |
1082 | ||
1083 | ssp = &pdata->ssp; | |
1084 | ||
1085 | ssp->phys_base = res->start; | |
1086 | ssp->mmio_base = devm_request_and_ioremap(&pdev->dev, res); | |
1087 | if (!ssp->mmio_base) { | |
1088 | dev_err(&pdev->dev, "failed to ioremap mmio_base\n"); | |
1089 | return NULL; | |
1090 | } | |
1091 | ||
1092 | ssp->clk = devm_clk_get(&pdev->dev, NULL); | |
1093 | ssp->irq = platform_get_irq(pdev, 0); | |
1094 | ssp->type = LPSS_SSP; | |
1095 | ssp->pdev = pdev; | |
1096 | ||
1097 | ssp->port_id = -1; | |
1098 | if (adev->pnp.unique_id && !kstrtoint(adev->pnp.unique_id, 0, &devid)) | |
1099 | ssp->port_id = devid; | |
1100 | ||
1101 | pdata->num_chipselect = 1; | |
1102 | pdata->rx_slave_id = -1; | |
1103 | pdata->tx_slave_id = -1; | |
1104 | ||
1105 | INIT_LIST_HEAD(&resource_list); | |
1106 | acpi_dev_get_resources(adev, &resource_list, pxa2xx_spi_acpi_add_dma, | |
1107 | pdata); | |
1108 | acpi_dev_free_resource_list(&resource_list); | |
1109 | ||
1110 | pdata->enable_dma = pdata->rx_slave_id >= 0 && pdata->tx_slave_id >= 0; | |
1111 | ||
1112 | return pdata; | |
1113 | } | |
1114 | ||
1115 | static struct acpi_device_id pxa2xx_spi_acpi_match[] = { | |
1116 | { "INT33C0", 0 }, | |
1117 | { "INT33C1", 0 }, | |
1118 | { }, | |
1119 | }; | |
1120 | MODULE_DEVICE_TABLE(acpi, pxa2xx_spi_acpi_match); | |
1121 | #else | |
1122 | static inline struct pxa2xx_spi_master * | |
1123 | pxa2xx_spi_acpi_get_pdata(struct platform_device *pdev) | |
1124 | { | |
1125 | return NULL; | |
1126 | } | |
1127 | #endif | |
1128 | ||
fd4a319b | 1129 | static int pxa2xx_spi_probe(struct platform_device *pdev) |
e0c9905e SS |
1130 | { |
1131 | struct device *dev = &pdev->dev; | |
1132 | struct pxa2xx_spi_master *platform_info; | |
1133 | struct spi_master *master; | |
65a00a20 | 1134 | struct driver_data *drv_data; |
2f1a74e5 | 1135 | struct ssp_device *ssp; |
65a00a20 | 1136 | int status; |
e0c9905e | 1137 | |
851bacf5 MW |
1138 | platform_info = dev_get_platdata(dev); |
1139 | if (!platform_info) { | |
a3496855 MW |
1140 | platform_info = pxa2xx_spi_acpi_get_pdata(pdev); |
1141 | if (!platform_info) { | |
1142 | dev_err(&pdev->dev, "missing platform data\n"); | |
1143 | return -ENODEV; | |
1144 | } | |
851bacf5 | 1145 | } |
e0c9905e | 1146 | |
baffe169 | 1147 | ssp = pxa_ssp_request(pdev->id, pdev->name); |
851bacf5 MW |
1148 | if (!ssp) |
1149 | ssp = &platform_info->ssp; | |
1150 | ||
1151 | if (!ssp->mmio_base) { | |
1152 | dev_err(&pdev->dev, "failed to get ssp\n"); | |
e0c9905e SS |
1153 | return -ENODEV; |
1154 | } | |
1155 | ||
1156 | /* Allocate master with space for drv_data and null dma buffer */ | |
1157 | master = spi_alloc_master(dev, sizeof(struct driver_data) + 16); | |
1158 | if (!master) { | |
65a00a20 | 1159 | dev_err(&pdev->dev, "cannot alloc spi_master\n"); |
baffe169 | 1160 | pxa_ssp_free(ssp); |
e0c9905e SS |
1161 | return -ENOMEM; |
1162 | } | |
1163 | drv_data = spi_master_get_devdata(master); | |
1164 | drv_data->master = master; | |
1165 | drv_data->master_info = platform_info; | |
1166 | drv_data->pdev = pdev; | |
2f1a74e5 | 1167 | drv_data->ssp = ssp; |
e0c9905e | 1168 | |
21486af0 | 1169 | master->dev.parent = &pdev->dev; |
21486af0 | 1170 | master->dev.of_node = pdev->dev.of_node; |
a3496855 | 1171 | ACPI_HANDLE_SET(&master->dev, ACPI_HANDLE(&pdev->dev)); |
e7db06b5 | 1172 | /* the spi->mode bits understood by this driver: */ |
b833172f | 1173 | master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH | SPI_LOOP; |
e7db06b5 | 1174 | |
851bacf5 | 1175 | master->bus_num = ssp->port_id; |
e0c9905e | 1176 | master->num_chipselect = platform_info->num_chipselect; |
7ad0ba91 | 1177 | master->dma_alignment = DMA_ALIGNMENT; |
e0c9905e SS |
1178 | master->cleanup = cleanup; |
1179 | master->setup = setup; | |
7f86bde9 | 1180 | master->transfer_one_message = pxa2xx_spi_transfer_one_message; |
7d94a505 MW |
1181 | master->prepare_transfer_hardware = pxa2xx_spi_prepare_transfer; |
1182 | master->unprepare_transfer_hardware = pxa2xx_spi_unprepare_transfer; | |
e0c9905e | 1183 | |
2f1a74e5 | 1184 | drv_data->ssp_type = ssp->type; |
2b9b84f4 | 1185 | drv_data->null_dma_buf = (u32 *)PTR_ALIGN(&drv_data[1], DMA_ALIGNMENT); |
e0c9905e | 1186 | |
2f1a74e5 | 1187 | drv_data->ioaddr = ssp->mmio_base; |
1188 | drv_data->ssdr_physical = ssp->phys_base + SSDR; | |
2a8626a9 | 1189 | if (pxa25x_ssp_comp(drv_data)) { |
e0c9905e SS |
1190 | drv_data->int_cr1 = SSCR1_TIE | SSCR1_RIE; |
1191 | drv_data->dma_cr1 = 0; | |
1192 | drv_data->clear_sr = SSSR_ROR; | |
1193 | drv_data->mask_sr = SSSR_RFS | SSSR_TFS | SSSR_ROR; | |
1194 | } else { | |
1195 | drv_data->int_cr1 = SSCR1_TIE | SSCR1_RIE | SSCR1_TINTE; | |
5928808e | 1196 | drv_data->dma_cr1 = DEFAULT_DMA_CR1; |
e0c9905e SS |
1197 | drv_data->clear_sr = SSSR_ROR | SSSR_TINT; |
1198 | drv_data->mask_sr = SSSR_TINT | SSSR_RFS | SSSR_TFS | SSSR_ROR; | |
1199 | } | |
1200 | ||
49cbb1e0 SAS |
1201 | status = request_irq(ssp->irq, ssp_int, IRQF_SHARED, dev_name(dev), |
1202 | drv_data); | |
e0c9905e | 1203 | if (status < 0) { |
65a00a20 | 1204 | dev_err(&pdev->dev, "cannot get IRQ %d\n", ssp->irq); |
e0c9905e SS |
1205 | goto out_error_master_alloc; |
1206 | } | |
1207 | ||
1208 | /* Setup DMA if requested */ | |
1209 | drv_data->tx_channel = -1; | |
1210 | drv_data->rx_channel = -1; | |
1211 | if (platform_info->enable_dma) { | |
cd7bed00 MW |
1212 | status = pxa2xx_spi_dma_setup(drv_data); |
1213 | if (status) { | |
1214 | dev_warn(dev, "failed to setup DMA, using PIO\n"); | |
1215 | platform_info->enable_dma = false; | |
e0c9905e | 1216 | } |
e0c9905e SS |
1217 | } |
1218 | ||
1219 | /* Enable SOC clock */ | |
3343b7a6 MW |
1220 | clk_prepare_enable(ssp->clk); |
1221 | ||
1222 | drv_data->max_clk_rate = clk_get_rate(ssp->clk); | |
e0c9905e SS |
1223 | |
1224 | /* Load default SSP configuration */ | |
1225 | write_SSCR0(0, drv_data->ioaddr); | |
f1f640a9 VS |
1226 | write_SSCR1(SSCR1_RxTresh(RX_THRESH_DFLT) | |
1227 | SSCR1_TxTresh(TX_THRESH_DFLT), | |
1228 | drv_data->ioaddr); | |
c9840daa | 1229 | write_SSCR0(SSCR0_SCR(2) |
e0c9905e SS |
1230 | | SSCR0_Motorola |
1231 | | SSCR0_DataSize(8), | |
1232 | drv_data->ioaddr); | |
2a8626a9 | 1233 | if (!pxa25x_ssp_comp(drv_data)) |
e0c9905e SS |
1234 | write_SSTO(0, drv_data->ioaddr); |
1235 | write_SSPSP(0, drv_data->ioaddr); | |
1236 | ||
a0d2642e MW |
1237 | lpss_ssp_setup(drv_data); |
1238 | ||
7f86bde9 MW |
1239 | tasklet_init(&drv_data->pump_transfers, pump_transfers, |
1240 | (unsigned long)drv_data); | |
e0c9905e SS |
1241 | |
1242 | /* Register with the SPI framework */ | |
1243 | platform_set_drvdata(pdev, drv_data); | |
1244 | status = spi_register_master(master); | |
1245 | if (status != 0) { | |
1246 | dev_err(&pdev->dev, "problem registering spi master\n"); | |
7f86bde9 | 1247 | goto out_error_clock_enabled; |
e0c9905e SS |
1248 | } |
1249 | ||
7d94a505 MW |
1250 | pm_runtime_set_autosuspend_delay(&pdev->dev, 50); |
1251 | pm_runtime_use_autosuspend(&pdev->dev); | |
1252 | pm_runtime_set_active(&pdev->dev); | |
1253 | pm_runtime_enable(&pdev->dev); | |
1254 | ||
e0c9905e SS |
1255 | return status; |
1256 | ||
e0c9905e | 1257 | out_error_clock_enabled: |
3343b7a6 | 1258 | clk_disable_unprepare(ssp->clk); |
cd7bed00 | 1259 | pxa2xx_spi_dma_release(drv_data); |
2f1a74e5 | 1260 | free_irq(ssp->irq, drv_data); |
e0c9905e SS |
1261 | |
1262 | out_error_master_alloc: | |
1263 | spi_master_put(master); | |
baffe169 | 1264 | pxa_ssp_free(ssp); |
e0c9905e SS |
1265 | return status; |
1266 | } | |
1267 | ||
1268 | static int pxa2xx_spi_remove(struct platform_device *pdev) | |
1269 | { | |
1270 | struct driver_data *drv_data = platform_get_drvdata(pdev); | |
51e911e2 | 1271 | struct ssp_device *ssp; |
e0c9905e SS |
1272 | |
1273 | if (!drv_data) | |
1274 | return 0; | |
51e911e2 | 1275 | ssp = drv_data->ssp; |
e0c9905e | 1276 | |
7d94a505 MW |
1277 | pm_runtime_get_sync(&pdev->dev); |
1278 | ||
e0c9905e SS |
1279 | /* Disable the SSP at the peripheral and SOC level */ |
1280 | write_SSCR0(0, drv_data->ioaddr); | |
3343b7a6 | 1281 | clk_disable_unprepare(ssp->clk); |
e0c9905e SS |
1282 | |
1283 | /* Release DMA */ | |
cd7bed00 MW |
1284 | if (drv_data->master_info->enable_dma) |
1285 | pxa2xx_spi_dma_release(drv_data); | |
e0c9905e | 1286 | |
7d94a505 MW |
1287 | pm_runtime_put_noidle(&pdev->dev); |
1288 | pm_runtime_disable(&pdev->dev); | |
1289 | ||
e0c9905e | 1290 | /* Release IRQ */ |
2f1a74e5 | 1291 | free_irq(ssp->irq, drv_data); |
1292 | ||
1293 | /* Release SSP */ | |
baffe169 | 1294 | pxa_ssp_free(ssp); |
e0c9905e SS |
1295 | |
1296 | /* Disconnect from the SPI framework */ | |
1297 | spi_unregister_master(drv_data->master); | |
1298 | ||
1299 | /* Prevent double remove */ | |
1300 | platform_set_drvdata(pdev, NULL); | |
1301 | ||
1302 | return 0; | |
1303 | } | |
1304 | ||
1305 | static void pxa2xx_spi_shutdown(struct platform_device *pdev) | |
1306 | { | |
1307 | int status = 0; | |
1308 | ||
1309 | if ((status = pxa2xx_spi_remove(pdev)) != 0) | |
1310 | dev_err(&pdev->dev, "shutdown failed with %d\n", status); | |
1311 | } | |
1312 | ||
1313 | #ifdef CONFIG_PM | |
86d2593a | 1314 | static int pxa2xx_spi_suspend(struct device *dev) |
e0c9905e | 1315 | { |
86d2593a | 1316 | struct driver_data *drv_data = dev_get_drvdata(dev); |
2f1a74e5 | 1317 | struct ssp_device *ssp = drv_data->ssp; |
e0c9905e SS |
1318 | int status = 0; |
1319 | ||
7f86bde9 | 1320 | status = spi_master_suspend(drv_data->master); |
e0c9905e SS |
1321 | if (status != 0) |
1322 | return status; | |
1323 | write_SSCR0(0, drv_data->ioaddr); | |
3343b7a6 | 1324 | clk_disable_unprepare(ssp->clk); |
e0c9905e SS |
1325 | |
1326 | return 0; | |
1327 | } | |
1328 | ||
86d2593a | 1329 | static int pxa2xx_spi_resume(struct device *dev) |
e0c9905e | 1330 | { |
86d2593a | 1331 | struct driver_data *drv_data = dev_get_drvdata(dev); |
2f1a74e5 | 1332 | struct ssp_device *ssp = drv_data->ssp; |
e0c9905e SS |
1333 | int status = 0; |
1334 | ||
cd7bed00 | 1335 | pxa2xx_spi_dma_resume(drv_data); |
148da331 | 1336 | |
e0c9905e | 1337 | /* Enable the SSP clock */ |
3343b7a6 | 1338 | clk_prepare_enable(ssp->clk); |
e0c9905e SS |
1339 | |
1340 | /* Start the queue running */ | |
7f86bde9 | 1341 | status = spi_master_resume(drv_data->master); |
e0c9905e | 1342 | if (status != 0) { |
86d2593a | 1343 | dev_err(dev, "problem starting queue (%d)\n", status); |
e0c9905e SS |
1344 | return status; |
1345 | } | |
1346 | ||
1347 | return 0; | |
1348 | } | |
7d94a505 MW |
1349 | #endif |
1350 | ||
1351 | #ifdef CONFIG_PM_RUNTIME | |
1352 | static int pxa2xx_spi_runtime_suspend(struct device *dev) | |
1353 | { | |
1354 | struct driver_data *drv_data = dev_get_drvdata(dev); | |
1355 | ||
1356 | clk_disable_unprepare(drv_data->ssp->clk); | |
1357 | return 0; | |
1358 | } | |
1359 | ||
1360 | static int pxa2xx_spi_runtime_resume(struct device *dev) | |
1361 | { | |
1362 | struct driver_data *drv_data = dev_get_drvdata(dev); | |
1363 | ||
1364 | clk_prepare_enable(drv_data->ssp->clk); | |
1365 | return 0; | |
1366 | } | |
1367 | #endif | |
86d2593a | 1368 | |
47145210 | 1369 | static const struct dev_pm_ops pxa2xx_spi_pm_ops = { |
7d94a505 MW |
1370 | SET_SYSTEM_SLEEP_PM_OPS(pxa2xx_spi_suspend, pxa2xx_spi_resume) |
1371 | SET_RUNTIME_PM_OPS(pxa2xx_spi_runtime_suspend, | |
1372 | pxa2xx_spi_runtime_resume, NULL) | |
86d2593a | 1373 | }; |
e0c9905e SS |
1374 | |
1375 | static struct platform_driver driver = { | |
1376 | .driver = { | |
86d2593a MR |
1377 | .name = "pxa2xx-spi", |
1378 | .owner = THIS_MODULE, | |
86d2593a | 1379 | .pm = &pxa2xx_spi_pm_ops, |
a3496855 | 1380 | .acpi_match_table = ACPI_PTR(pxa2xx_spi_acpi_match), |
e0c9905e | 1381 | }, |
fbd29a14 | 1382 | .probe = pxa2xx_spi_probe, |
d1e44d9c | 1383 | .remove = pxa2xx_spi_remove, |
e0c9905e | 1384 | .shutdown = pxa2xx_spi_shutdown, |
e0c9905e SS |
1385 | }; |
1386 | ||
1387 | static int __init pxa2xx_spi_init(void) | |
1388 | { | |
fbd29a14 | 1389 | return platform_driver_register(&driver); |
e0c9905e | 1390 | } |
5b61a749 | 1391 | subsys_initcall(pxa2xx_spi_init); |
e0c9905e SS |
1392 | |
1393 | static void __exit pxa2xx_spi_exit(void) | |
1394 | { | |
1395 | platform_driver_unregister(&driver); | |
1396 | } | |
1397 | module_exit(pxa2xx_spi_exit); |