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e0c9905e SS |
1 | /* |
2 | * Copyright (C) 2005 Stephen Street / StreetFire Sound Labs | |
a0d2642e | 3 | * Copyright (C) 2013, Intel Corporation |
e0c9905e SS |
4 | * |
5 | * This program is free software; you can redistribute it and/or modify | |
6 | * it under the terms of the GNU General Public License as published by | |
7 | * the Free Software Foundation; either version 2 of the License, or | |
8 | * (at your option) any later version. | |
9 | * | |
10 | * This program is distributed in the hope that it will be useful, | |
11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | * GNU General Public License for more details. | |
14 | * | |
15 | * You should have received a copy of the GNU General Public License | |
16 | * along with this program; if not, write to the Free Software | |
17 | * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. | |
18 | */ | |
19 | ||
20 | #include <linux/init.h> | |
21 | #include <linux/module.h> | |
22 | #include <linux/device.h> | |
23 | #include <linux/ioport.h> | |
24 | #include <linux/errno.h> | |
25 | #include <linux/interrupt.h> | |
26 | #include <linux/platform_device.h> | |
8348c259 | 27 | #include <linux/spi/pxa2xx_spi.h> |
e0c9905e SS |
28 | #include <linux/spi/spi.h> |
29 | #include <linux/workqueue.h> | |
e0c9905e | 30 | #include <linux/delay.h> |
a7bb3909 | 31 | #include <linux/gpio.h> |
5a0e3ad6 | 32 | #include <linux/slab.h> |
3343b7a6 | 33 | #include <linux/clk.h> |
7d94a505 | 34 | #include <linux/pm_runtime.h> |
a3496855 | 35 | #include <linux/acpi.h> |
e0c9905e SS |
36 | |
37 | #include <asm/io.h> | |
38 | #include <asm/irq.h> | |
e0c9905e | 39 | #include <asm/delay.h> |
e0c9905e | 40 | |
cd7bed00 | 41 | #include "spi-pxa2xx.h" |
e0c9905e SS |
42 | |
43 | MODULE_AUTHOR("Stephen Street"); | |
037cdafe | 44 | MODULE_DESCRIPTION("PXA2xx SSP SPI Controller"); |
e0c9905e | 45 | MODULE_LICENSE("GPL"); |
7e38c3c4 | 46 | MODULE_ALIAS("platform:pxa2xx-spi"); |
e0c9905e SS |
47 | |
48 | #define MAX_BUSES 3 | |
49 | ||
f1f640a9 VS |
50 | #define TIMOUT_DFLT 1000 |
51 | ||
b97c74bd NF |
52 | /* |
53 | * for testing SSCR1 changes that require SSP restart, basically | |
54 | * everything except the service and interrupt enables, the pxa270 developer | |
55 | * manual says only SSCR1_SCFR, SSCR1_SPH, SSCR1_SPO need to be in this | |
56 | * list, but the PXA255 dev man says all bits without really meaning the | |
57 | * service and interrupt enables | |
58 | */ | |
59 | #define SSCR1_CHANGE_MASK (SSCR1_TTELP | SSCR1_TTE | SSCR1_SCFR \ | |
8d94cc50 | 60 | | SSCR1_ECRA | SSCR1_ECRB | SSCR1_SCLKDIR \ |
b97c74bd NF |
61 | | SSCR1_SFRMDIR | SSCR1_RWOT | SSCR1_TRAIL \ |
62 | | SSCR1_IFS | SSCR1_STRF | SSCR1_EFWR \ | |
63 | | SSCR1_RFT | SSCR1_TFT | SSCR1_MWDS \ | |
64 | | SSCR1_SPH | SSCR1_SPO | SSCR1_LBM) | |
8d94cc50 | 65 | |
a0d2642e MW |
66 | #define LPSS_RX_THRESH_DFLT 64 |
67 | #define LPSS_TX_LOTHRESH_DFLT 160 | |
68 | #define LPSS_TX_HITHRESH_DFLT 224 | |
69 | ||
70 | /* Offset from drv_data->lpss_base */ | |
0054e28d | 71 | #define SSP_REG 0x0c |
a0d2642e MW |
72 | #define SPI_CS_CONTROL 0x18 |
73 | #define SPI_CS_CONTROL_SW_MODE BIT(0) | |
74 | #define SPI_CS_CONTROL_CS_HIGH BIT(1) | |
75 | ||
76 | static bool is_lpss_ssp(const struct driver_data *drv_data) | |
77 | { | |
78 | return drv_data->ssp_type == LPSS_SSP; | |
79 | } | |
80 | ||
81 | /* | |
82 | * Read and write LPSS SSP private registers. Caller must first check that | |
83 | * is_lpss_ssp() returns true before these can be called. | |
84 | */ | |
85 | static u32 __lpss_ssp_read_priv(struct driver_data *drv_data, unsigned offset) | |
86 | { | |
87 | WARN_ON(!drv_data->lpss_base); | |
88 | return readl(drv_data->lpss_base + offset); | |
89 | } | |
90 | ||
91 | static void __lpss_ssp_write_priv(struct driver_data *drv_data, | |
92 | unsigned offset, u32 value) | |
93 | { | |
94 | WARN_ON(!drv_data->lpss_base); | |
95 | writel(value, drv_data->lpss_base + offset); | |
96 | } | |
97 | ||
98 | /* | |
99 | * lpss_ssp_setup - perform LPSS SSP specific setup | |
100 | * @drv_data: pointer to the driver private data | |
101 | * | |
102 | * Perform LPSS SSP specific setup. This function must be called first if | |
103 | * one is going to use LPSS SSP private registers. | |
104 | */ | |
105 | static void lpss_ssp_setup(struct driver_data *drv_data) | |
106 | { | |
107 | unsigned offset = 0x400; | |
108 | u32 value, orig; | |
109 | ||
110 | if (!is_lpss_ssp(drv_data)) | |
111 | return; | |
112 | ||
113 | /* | |
114 | * Perform auto-detection of the LPSS SSP private registers. They | |
115 | * can be either at 1k or 2k offset from the base address. | |
116 | */ | |
117 | orig = readl(drv_data->ioaddr + offset + SPI_CS_CONTROL); | |
118 | ||
119 | value = orig | SPI_CS_CONTROL_SW_MODE; | |
120 | writel(value, drv_data->ioaddr + offset + SPI_CS_CONTROL); | |
121 | value = readl(drv_data->ioaddr + offset + SPI_CS_CONTROL); | |
122 | if (value != (orig | SPI_CS_CONTROL_SW_MODE)) { | |
123 | offset = 0x800; | |
124 | goto detection_done; | |
125 | } | |
126 | ||
127 | value &= ~SPI_CS_CONTROL_SW_MODE; | |
128 | writel(value, drv_data->ioaddr + offset + SPI_CS_CONTROL); | |
129 | value = readl(drv_data->ioaddr + offset + SPI_CS_CONTROL); | |
130 | if (value != orig) { | |
131 | offset = 0x800; | |
132 | goto detection_done; | |
133 | } | |
134 | ||
135 | detection_done: | |
136 | /* Now set the LPSS base */ | |
137 | drv_data->lpss_base = drv_data->ioaddr + offset; | |
138 | ||
139 | /* Enable software chip select control */ | |
140 | value = SPI_CS_CONTROL_SW_MODE | SPI_CS_CONTROL_CS_HIGH; | |
141 | __lpss_ssp_write_priv(drv_data, SPI_CS_CONTROL, value); | |
0054e28d MW |
142 | |
143 | /* Enable multiblock DMA transfers */ | |
144 | if (drv_data->master_info->enable_dma) | |
145 | __lpss_ssp_write_priv(drv_data, SSP_REG, 1); | |
a0d2642e MW |
146 | } |
147 | ||
148 | static void lpss_ssp_cs_control(struct driver_data *drv_data, bool enable) | |
149 | { | |
150 | u32 value; | |
151 | ||
152 | if (!is_lpss_ssp(drv_data)) | |
153 | return; | |
154 | ||
155 | value = __lpss_ssp_read_priv(drv_data, SPI_CS_CONTROL); | |
156 | if (enable) | |
157 | value &= ~SPI_CS_CONTROL_CS_HIGH; | |
158 | else | |
159 | value |= SPI_CS_CONTROL_CS_HIGH; | |
160 | __lpss_ssp_write_priv(drv_data, SPI_CS_CONTROL, value); | |
161 | } | |
162 | ||
a7bb3909 EM |
163 | static void cs_assert(struct driver_data *drv_data) |
164 | { | |
165 | struct chip_data *chip = drv_data->cur_chip; | |
166 | ||
2a8626a9 SAS |
167 | if (drv_data->ssp_type == CE4100_SSP) { |
168 | write_SSSR(drv_data->cur_chip->frm, drv_data->ioaddr); | |
169 | return; | |
170 | } | |
171 | ||
a7bb3909 EM |
172 | if (chip->cs_control) { |
173 | chip->cs_control(PXA2XX_CS_ASSERT); | |
174 | return; | |
175 | } | |
176 | ||
a0d2642e | 177 | if (gpio_is_valid(chip->gpio_cs)) { |
a7bb3909 | 178 | gpio_set_value(chip->gpio_cs, chip->gpio_cs_inverted); |
a0d2642e MW |
179 | return; |
180 | } | |
181 | ||
182 | lpss_ssp_cs_control(drv_data, true); | |
a7bb3909 EM |
183 | } |
184 | ||
185 | static void cs_deassert(struct driver_data *drv_data) | |
186 | { | |
187 | struct chip_data *chip = drv_data->cur_chip; | |
188 | ||
2a8626a9 SAS |
189 | if (drv_data->ssp_type == CE4100_SSP) |
190 | return; | |
191 | ||
a7bb3909 | 192 | if (chip->cs_control) { |
2b2562d3 | 193 | chip->cs_control(PXA2XX_CS_DEASSERT); |
a7bb3909 EM |
194 | return; |
195 | } | |
196 | ||
a0d2642e | 197 | if (gpio_is_valid(chip->gpio_cs)) { |
a7bb3909 | 198 | gpio_set_value(chip->gpio_cs, !chip->gpio_cs_inverted); |
a0d2642e MW |
199 | return; |
200 | } | |
201 | ||
202 | lpss_ssp_cs_control(drv_data, false); | |
a7bb3909 EM |
203 | } |
204 | ||
cd7bed00 | 205 | int pxa2xx_spi_flush(struct driver_data *drv_data) |
e0c9905e SS |
206 | { |
207 | unsigned long limit = loops_per_jiffy << 1; | |
208 | ||
cf43369d | 209 | void __iomem *reg = drv_data->ioaddr; |
e0c9905e SS |
210 | |
211 | do { | |
212 | while (read_SSSR(reg) & SSSR_RNE) { | |
213 | read_SSDR(reg); | |
214 | } | |
306c68aa | 215 | } while ((read_SSSR(reg) & SSSR_BSY) && --limit); |
2a8626a9 | 216 | write_SSSR_CS(drv_data, SSSR_ROR); |
e0c9905e SS |
217 | |
218 | return limit; | |
219 | } | |
220 | ||
8d94cc50 | 221 | static int null_writer(struct driver_data *drv_data) |
e0c9905e | 222 | { |
cf43369d | 223 | void __iomem *reg = drv_data->ioaddr; |
9708c121 | 224 | u8 n_bytes = drv_data->n_bytes; |
e0c9905e | 225 | |
4a25605f | 226 | if (((read_SSSR(reg) & SSSR_TFL_MASK) == SSSR_TFL_MASK) |
8d94cc50 SS |
227 | || (drv_data->tx == drv_data->tx_end)) |
228 | return 0; | |
229 | ||
230 | write_SSDR(0, reg); | |
231 | drv_data->tx += n_bytes; | |
232 | ||
233 | return 1; | |
e0c9905e SS |
234 | } |
235 | ||
8d94cc50 | 236 | static int null_reader(struct driver_data *drv_data) |
e0c9905e | 237 | { |
cf43369d | 238 | void __iomem *reg = drv_data->ioaddr; |
9708c121 | 239 | u8 n_bytes = drv_data->n_bytes; |
e0c9905e SS |
240 | |
241 | while ((read_SSSR(reg) & SSSR_RNE) | |
8d94cc50 | 242 | && (drv_data->rx < drv_data->rx_end)) { |
e0c9905e SS |
243 | read_SSDR(reg); |
244 | drv_data->rx += n_bytes; | |
245 | } | |
8d94cc50 SS |
246 | |
247 | return drv_data->rx == drv_data->rx_end; | |
e0c9905e SS |
248 | } |
249 | ||
8d94cc50 | 250 | static int u8_writer(struct driver_data *drv_data) |
e0c9905e | 251 | { |
cf43369d | 252 | void __iomem *reg = drv_data->ioaddr; |
e0c9905e | 253 | |
4a25605f | 254 | if (((read_SSSR(reg) & SSSR_TFL_MASK) == SSSR_TFL_MASK) |
8d94cc50 SS |
255 | || (drv_data->tx == drv_data->tx_end)) |
256 | return 0; | |
257 | ||
258 | write_SSDR(*(u8 *)(drv_data->tx), reg); | |
259 | ++drv_data->tx; | |
260 | ||
261 | return 1; | |
e0c9905e SS |
262 | } |
263 | ||
8d94cc50 | 264 | static int u8_reader(struct driver_data *drv_data) |
e0c9905e | 265 | { |
cf43369d | 266 | void __iomem *reg = drv_data->ioaddr; |
e0c9905e SS |
267 | |
268 | while ((read_SSSR(reg) & SSSR_RNE) | |
8d94cc50 | 269 | && (drv_data->rx < drv_data->rx_end)) { |
e0c9905e SS |
270 | *(u8 *)(drv_data->rx) = read_SSDR(reg); |
271 | ++drv_data->rx; | |
272 | } | |
8d94cc50 SS |
273 | |
274 | return drv_data->rx == drv_data->rx_end; | |
e0c9905e SS |
275 | } |
276 | ||
8d94cc50 | 277 | static int u16_writer(struct driver_data *drv_data) |
e0c9905e | 278 | { |
cf43369d | 279 | void __iomem *reg = drv_data->ioaddr; |
e0c9905e | 280 | |
4a25605f | 281 | if (((read_SSSR(reg) & SSSR_TFL_MASK) == SSSR_TFL_MASK) |
8d94cc50 SS |
282 | || (drv_data->tx == drv_data->tx_end)) |
283 | return 0; | |
284 | ||
285 | write_SSDR(*(u16 *)(drv_data->tx), reg); | |
286 | drv_data->tx += 2; | |
287 | ||
288 | return 1; | |
e0c9905e SS |
289 | } |
290 | ||
8d94cc50 | 291 | static int u16_reader(struct driver_data *drv_data) |
e0c9905e | 292 | { |
cf43369d | 293 | void __iomem *reg = drv_data->ioaddr; |
e0c9905e SS |
294 | |
295 | while ((read_SSSR(reg) & SSSR_RNE) | |
8d94cc50 | 296 | && (drv_data->rx < drv_data->rx_end)) { |
e0c9905e SS |
297 | *(u16 *)(drv_data->rx) = read_SSDR(reg); |
298 | drv_data->rx += 2; | |
299 | } | |
8d94cc50 SS |
300 | |
301 | return drv_data->rx == drv_data->rx_end; | |
e0c9905e | 302 | } |
8d94cc50 SS |
303 | |
304 | static int u32_writer(struct driver_data *drv_data) | |
e0c9905e | 305 | { |
cf43369d | 306 | void __iomem *reg = drv_data->ioaddr; |
e0c9905e | 307 | |
4a25605f | 308 | if (((read_SSSR(reg) & SSSR_TFL_MASK) == SSSR_TFL_MASK) |
8d94cc50 SS |
309 | || (drv_data->tx == drv_data->tx_end)) |
310 | return 0; | |
311 | ||
312 | write_SSDR(*(u32 *)(drv_data->tx), reg); | |
313 | drv_data->tx += 4; | |
314 | ||
315 | return 1; | |
e0c9905e SS |
316 | } |
317 | ||
8d94cc50 | 318 | static int u32_reader(struct driver_data *drv_data) |
e0c9905e | 319 | { |
cf43369d | 320 | void __iomem *reg = drv_data->ioaddr; |
e0c9905e SS |
321 | |
322 | while ((read_SSSR(reg) & SSSR_RNE) | |
8d94cc50 | 323 | && (drv_data->rx < drv_data->rx_end)) { |
e0c9905e SS |
324 | *(u32 *)(drv_data->rx) = read_SSDR(reg); |
325 | drv_data->rx += 4; | |
326 | } | |
8d94cc50 SS |
327 | |
328 | return drv_data->rx == drv_data->rx_end; | |
e0c9905e SS |
329 | } |
330 | ||
cd7bed00 | 331 | void *pxa2xx_spi_next_transfer(struct driver_data *drv_data) |
e0c9905e SS |
332 | { |
333 | struct spi_message *msg = drv_data->cur_msg; | |
334 | struct spi_transfer *trans = drv_data->cur_transfer; | |
335 | ||
336 | /* Move to next transfer */ | |
337 | if (trans->transfer_list.next != &msg->transfers) { | |
338 | drv_data->cur_transfer = | |
339 | list_entry(trans->transfer_list.next, | |
340 | struct spi_transfer, | |
341 | transfer_list); | |
342 | return RUNNING_STATE; | |
343 | } else | |
344 | return DONE_STATE; | |
345 | } | |
346 | ||
e0c9905e | 347 | /* caller already set message->status; dma and pio irqs are blocked */ |
5daa3ba0 | 348 | static void giveback(struct driver_data *drv_data) |
e0c9905e SS |
349 | { |
350 | struct spi_transfer* last_transfer; | |
5daa3ba0 | 351 | struct spi_message *msg; |
e0c9905e | 352 | |
5daa3ba0 SS |
353 | msg = drv_data->cur_msg; |
354 | drv_data->cur_msg = NULL; | |
355 | drv_data->cur_transfer = NULL; | |
5daa3ba0 SS |
356 | |
357 | last_transfer = list_entry(msg->transfers.prev, | |
e0c9905e SS |
358 | struct spi_transfer, |
359 | transfer_list); | |
360 | ||
8423597d NF |
361 | /* Delay if requested before any change in chip select */ |
362 | if (last_transfer->delay_usecs) | |
363 | udelay(last_transfer->delay_usecs); | |
364 | ||
365 | /* Drop chip select UNLESS cs_change is true or we are returning | |
366 | * a message with an error, or next message is for another chip | |
367 | */ | |
e0c9905e | 368 | if (!last_transfer->cs_change) |
a7bb3909 | 369 | cs_deassert(drv_data); |
8423597d NF |
370 | else { |
371 | struct spi_message *next_msg; | |
372 | ||
373 | /* Holding of cs was hinted, but we need to make sure | |
374 | * the next message is for the same chip. Don't waste | |
375 | * time with the following tests unless this was hinted. | |
376 | * | |
377 | * We cannot postpone this until pump_messages, because | |
378 | * after calling msg->complete (below) the driver that | |
379 | * sent the current message could be unloaded, which | |
380 | * could invalidate the cs_control() callback... | |
381 | */ | |
382 | ||
383 | /* get a pointer to the next message, if any */ | |
7f86bde9 | 384 | next_msg = spi_get_next_queued_message(drv_data->master); |
8423597d NF |
385 | |
386 | /* see if the next and current messages point | |
387 | * to the same chip | |
388 | */ | |
389 | if (next_msg && next_msg->spi != msg->spi) | |
390 | next_msg = NULL; | |
391 | if (!next_msg || msg->state == ERROR_STATE) | |
a7bb3909 | 392 | cs_deassert(drv_data); |
8423597d | 393 | } |
e0c9905e | 394 | |
7f86bde9 | 395 | spi_finalize_current_message(drv_data->master); |
a7bb3909 | 396 | drv_data->cur_chip = NULL; |
e0c9905e SS |
397 | } |
398 | ||
579d3bb2 SAS |
399 | static void reset_sccr1(struct driver_data *drv_data) |
400 | { | |
401 | void __iomem *reg = drv_data->ioaddr; | |
402 | struct chip_data *chip = drv_data->cur_chip; | |
403 | u32 sccr1_reg; | |
404 | ||
405 | sccr1_reg = read_SSCR1(reg) & ~drv_data->int_cr1; | |
406 | sccr1_reg &= ~SSCR1_RFT; | |
407 | sccr1_reg |= chip->threshold; | |
408 | write_SSCR1(sccr1_reg, reg); | |
409 | } | |
410 | ||
8d94cc50 | 411 | static void int_error_stop(struct driver_data *drv_data, const char* msg) |
e0c9905e | 412 | { |
cf43369d | 413 | void __iomem *reg = drv_data->ioaddr; |
e0c9905e | 414 | |
8d94cc50 | 415 | /* Stop and reset SSP */ |
2a8626a9 | 416 | write_SSSR_CS(drv_data, drv_data->clear_sr); |
579d3bb2 | 417 | reset_sccr1(drv_data); |
2a8626a9 | 418 | if (!pxa25x_ssp_comp(drv_data)) |
8d94cc50 | 419 | write_SSTO(0, reg); |
cd7bed00 | 420 | pxa2xx_spi_flush(drv_data); |
8d94cc50 | 421 | write_SSCR0(read_SSCR0(reg) & ~SSCR0_SSE, reg); |
e0c9905e | 422 | |
8d94cc50 | 423 | dev_err(&drv_data->pdev->dev, "%s\n", msg); |
e0c9905e | 424 | |
8d94cc50 SS |
425 | drv_data->cur_msg->state = ERROR_STATE; |
426 | tasklet_schedule(&drv_data->pump_transfers); | |
427 | } | |
5daa3ba0 | 428 | |
8d94cc50 SS |
429 | static void int_transfer_complete(struct driver_data *drv_data) |
430 | { | |
cf43369d | 431 | void __iomem *reg = drv_data->ioaddr; |
e0c9905e | 432 | |
8d94cc50 | 433 | /* Stop SSP */ |
2a8626a9 | 434 | write_SSSR_CS(drv_data, drv_data->clear_sr); |
579d3bb2 | 435 | reset_sccr1(drv_data); |
2a8626a9 | 436 | if (!pxa25x_ssp_comp(drv_data)) |
8d94cc50 | 437 | write_SSTO(0, reg); |
e0c9905e | 438 | |
25985edc | 439 | /* Update total byte transferred return count actual bytes read */ |
8d94cc50 SS |
440 | drv_data->cur_msg->actual_length += drv_data->len - |
441 | (drv_data->rx_end - drv_data->rx); | |
e0c9905e | 442 | |
8423597d NF |
443 | /* Transfer delays and chip select release are |
444 | * handled in pump_transfers or giveback | |
445 | */ | |
e0c9905e | 446 | |
8d94cc50 | 447 | /* Move to next transfer */ |
cd7bed00 | 448 | drv_data->cur_msg->state = pxa2xx_spi_next_transfer(drv_data); |
e0c9905e | 449 | |
8d94cc50 SS |
450 | /* Schedule transfer tasklet */ |
451 | tasklet_schedule(&drv_data->pump_transfers); | |
452 | } | |
e0c9905e | 453 | |
8d94cc50 SS |
454 | static irqreturn_t interrupt_transfer(struct driver_data *drv_data) |
455 | { | |
cf43369d | 456 | void __iomem *reg = drv_data->ioaddr; |
e0c9905e | 457 | |
8d94cc50 SS |
458 | u32 irq_mask = (read_SSCR1(reg) & SSCR1_TIE) ? |
459 | drv_data->mask_sr : drv_data->mask_sr & ~SSSR_TFS; | |
e0c9905e | 460 | |
8d94cc50 | 461 | u32 irq_status = read_SSSR(reg) & irq_mask; |
e0c9905e | 462 | |
8d94cc50 SS |
463 | if (irq_status & SSSR_ROR) { |
464 | int_error_stop(drv_data, "interrupt_transfer: fifo overrun"); | |
465 | return IRQ_HANDLED; | |
466 | } | |
e0c9905e | 467 | |
8d94cc50 SS |
468 | if (irq_status & SSSR_TINT) { |
469 | write_SSSR(SSSR_TINT, reg); | |
470 | if (drv_data->read(drv_data)) { | |
471 | int_transfer_complete(drv_data); | |
472 | return IRQ_HANDLED; | |
473 | } | |
474 | } | |
e0c9905e | 475 | |
8d94cc50 SS |
476 | /* Drain rx fifo, Fill tx fifo and prevent overruns */ |
477 | do { | |
478 | if (drv_data->read(drv_data)) { | |
479 | int_transfer_complete(drv_data); | |
480 | return IRQ_HANDLED; | |
481 | } | |
482 | } while (drv_data->write(drv_data)); | |
e0c9905e | 483 | |
8d94cc50 SS |
484 | if (drv_data->read(drv_data)) { |
485 | int_transfer_complete(drv_data); | |
486 | return IRQ_HANDLED; | |
487 | } | |
e0c9905e | 488 | |
8d94cc50 | 489 | if (drv_data->tx == drv_data->tx_end) { |
579d3bb2 SAS |
490 | u32 bytes_left; |
491 | u32 sccr1_reg; | |
492 | ||
493 | sccr1_reg = read_SSCR1(reg); | |
494 | sccr1_reg &= ~SSCR1_TIE; | |
495 | ||
496 | /* | |
497 | * PXA25x_SSP has no timeout, set up rx threshould for the | |
25985edc | 498 | * remaining RX bytes. |
579d3bb2 | 499 | */ |
2a8626a9 | 500 | if (pxa25x_ssp_comp(drv_data)) { |
579d3bb2 SAS |
501 | |
502 | sccr1_reg &= ~SSCR1_RFT; | |
503 | ||
504 | bytes_left = drv_data->rx_end - drv_data->rx; | |
505 | switch (drv_data->n_bytes) { | |
506 | case 4: | |
507 | bytes_left >>= 1; | |
508 | case 2: | |
509 | bytes_left >>= 1; | |
8d94cc50 | 510 | } |
579d3bb2 SAS |
511 | |
512 | if (bytes_left > RX_THRESH_DFLT) | |
513 | bytes_left = RX_THRESH_DFLT; | |
514 | ||
515 | sccr1_reg |= SSCR1_RxTresh(bytes_left); | |
e0c9905e | 516 | } |
579d3bb2 | 517 | write_SSCR1(sccr1_reg, reg); |
e0c9905e SS |
518 | } |
519 | ||
5daa3ba0 SS |
520 | /* We did something */ |
521 | return IRQ_HANDLED; | |
e0c9905e SS |
522 | } |
523 | ||
7d12e780 | 524 | static irqreturn_t ssp_int(int irq, void *dev_id) |
e0c9905e | 525 | { |
c7bec5ab | 526 | struct driver_data *drv_data = dev_id; |
cf43369d | 527 | void __iomem *reg = drv_data->ioaddr; |
7d94a505 | 528 | u32 sccr1_reg; |
49cbb1e0 SAS |
529 | u32 mask = drv_data->mask_sr; |
530 | u32 status; | |
531 | ||
7d94a505 MW |
532 | /* |
533 | * The IRQ might be shared with other peripherals so we must first | |
534 | * check that are we RPM suspended or not. If we are we assume that | |
535 | * the IRQ was not for us (we shouldn't be RPM suspended when the | |
536 | * interrupt is enabled). | |
537 | */ | |
538 | if (pm_runtime_suspended(&drv_data->pdev->dev)) | |
539 | return IRQ_NONE; | |
540 | ||
541 | sccr1_reg = read_SSCR1(reg); | |
49cbb1e0 SAS |
542 | status = read_SSSR(reg); |
543 | ||
544 | /* Ignore possible writes if we don't need to write */ | |
545 | if (!(sccr1_reg & SSCR1_TIE)) | |
546 | mask &= ~SSSR_TFS; | |
547 | ||
548 | if (!(status & mask)) | |
549 | return IRQ_NONE; | |
e0c9905e SS |
550 | |
551 | if (!drv_data->cur_msg) { | |
5daa3ba0 SS |
552 | |
553 | write_SSCR0(read_SSCR0(reg) & ~SSCR0_SSE, reg); | |
554 | write_SSCR1(read_SSCR1(reg) & ~drv_data->int_cr1, reg); | |
2a8626a9 | 555 | if (!pxa25x_ssp_comp(drv_data)) |
5daa3ba0 | 556 | write_SSTO(0, reg); |
2a8626a9 | 557 | write_SSSR_CS(drv_data, drv_data->clear_sr); |
5daa3ba0 | 558 | |
e0c9905e | 559 | dev_err(&drv_data->pdev->dev, "bad message state " |
8d94cc50 | 560 | "in interrupt handler\n"); |
5daa3ba0 | 561 | |
e0c9905e SS |
562 | /* Never fail */ |
563 | return IRQ_HANDLED; | |
564 | } | |
565 | ||
566 | return drv_data->transfer_handler(drv_data); | |
567 | } | |
568 | ||
3343b7a6 | 569 | static unsigned int ssp_get_clk_div(struct driver_data *drv_data, int rate) |
2f1a74e5 | 570 | { |
3343b7a6 MW |
571 | unsigned long ssp_clk = drv_data->max_clk_rate; |
572 | const struct ssp_device *ssp = drv_data->ssp; | |
573 | ||
574 | rate = min_t(int, ssp_clk, rate); | |
2f1a74e5 | 575 | |
2a8626a9 | 576 | if (ssp->type == PXA25x_SSP || ssp->type == CE4100_SSP) |
2f1a74e5 | 577 | return ((ssp_clk / (2 * rate) - 1) & 0xff) << 8; |
578 | else | |
579 | return ((ssp_clk / rate - 1) & 0xfff) << 8; | |
580 | } | |
581 | ||
e0c9905e SS |
582 | static void pump_transfers(unsigned long data) |
583 | { | |
584 | struct driver_data *drv_data = (struct driver_data *)data; | |
585 | struct spi_message *message = NULL; | |
586 | struct spi_transfer *transfer = NULL; | |
587 | struct spi_transfer *previous = NULL; | |
588 | struct chip_data *chip = NULL; | |
cf43369d | 589 | void __iomem *reg = drv_data->ioaddr; |
9708c121 SS |
590 | u32 clk_div = 0; |
591 | u8 bits = 0; | |
592 | u32 speed = 0; | |
593 | u32 cr0; | |
8d94cc50 SS |
594 | u32 cr1; |
595 | u32 dma_thresh = drv_data->cur_chip->dma_threshold; | |
596 | u32 dma_burst = drv_data->cur_chip->dma_burst_size; | |
e0c9905e SS |
597 | |
598 | /* Get current state information */ | |
599 | message = drv_data->cur_msg; | |
600 | transfer = drv_data->cur_transfer; | |
601 | chip = drv_data->cur_chip; | |
602 | ||
603 | /* Handle for abort */ | |
604 | if (message->state == ERROR_STATE) { | |
605 | message->status = -EIO; | |
5daa3ba0 | 606 | giveback(drv_data); |
e0c9905e SS |
607 | return; |
608 | } | |
609 | ||
610 | /* Handle end of message */ | |
611 | if (message->state == DONE_STATE) { | |
612 | message->status = 0; | |
5daa3ba0 | 613 | giveback(drv_data); |
e0c9905e SS |
614 | return; |
615 | } | |
616 | ||
8423597d | 617 | /* Delay if requested at end of transfer before CS change */ |
e0c9905e SS |
618 | if (message->state == RUNNING_STATE) { |
619 | previous = list_entry(transfer->transfer_list.prev, | |
620 | struct spi_transfer, | |
621 | transfer_list); | |
622 | if (previous->delay_usecs) | |
623 | udelay(previous->delay_usecs); | |
8423597d NF |
624 | |
625 | /* Drop chip select only if cs_change is requested */ | |
626 | if (previous->cs_change) | |
a7bb3909 | 627 | cs_deassert(drv_data); |
e0c9905e SS |
628 | } |
629 | ||
cd7bed00 MW |
630 | /* Check if we can DMA this transfer */ |
631 | if (!pxa2xx_spi_dma_is_possible(transfer->len) && chip->enable_dma) { | |
7e964455 NF |
632 | |
633 | /* reject already-mapped transfers; PIO won't always work */ | |
634 | if (message->is_dma_mapped | |
635 | || transfer->rx_dma || transfer->tx_dma) { | |
636 | dev_err(&drv_data->pdev->dev, | |
637 | "pump_transfers: mapped transfer length " | |
20b918dc | 638 | "of %u is greater than %d\n", |
7e964455 NF |
639 | transfer->len, MAX_DMA_LEN); |
640 | message->status = -EINVAL; | |
641 | giveback(drv_data); | |
642 | return; | |
643 | } | |
644 | ||
645 | /* warn ... we force this to PIO mode */ | |
646 | if (printk_ratelimit()) | |
647 | dev_warn(&message->spi->dev, "pump_transfers: " | |
648 | "DMA disabled for transfer length %ld " | |
649 | "greater than %d\n", | |
650 | (long)drv_data->len, MAX_DMA_LEN); | |
8d94cc50 SS |
651 | } |
652 | ||
e0c9905e | 653 | /* Setup the transfer state based on the type of transfer */ |
cd7bed00 | 654 | if (pxa2xx_spi_flush(drv_data) == 0) { |
e0c9905e SS |
655 | dev_err(&drv_data->pdev->dev, "pump_transfers: flush failed\n"); |
656 | message->status = -EIO; | |
5daa3ba0 | 657 | giveback(drv_data); |
e0c9905e SS |
658 | return; |
659 | } | |
9708c121 | 660 | drv_data->n_bytes = chip->n_bytes; |
e0c9905e SS |
661 | drv_data->tx = (void *)transfer->tx_buf; |
662 | drv_data->tx_end = drv_data->tx + transfer->len; | |
663 | drv_data->rx = transfer->rx_buf; | |
664 | drv_data->rx_end = drv_data->rx + transfer->len; | |
665 | drv_data->rx_dma = transfer->rx_dma; | |
666 | drv_data->tx_dma = transfer->tx_dma; | |
cd7bed00 | 667 | drv_data->len = transfer->len; |
e0c9905e SS |
668 | drv_data->write = drv_data->tx ? chip->write : null_writer; |
669 | drv_data->read = drv_data->rx ? chip->read : null_reader; | |
9708c121 SS |
670 | |
671 | /* Change speed and bit per word on a per transfer */ | |
8d94cc50 | 672 | cr0 = chip->cr0; |
9708c121 SS |
673 | if (transfer->speed_hz || transfer->bits_per_word) { |
674 | ||
9708c121 SS |
675 | bits = chip->bits_per_word; |
676 | speed = chip->speed_hz; | |
677 | ||
678 | if (transfer->speed_hz) | |
679 | speed = transfer->speed_hz; | |
680 | ||
681 | if (transfer->bits_per_word) | |
682 | bits = transfer->bits_per_word; | |
683 | ||
3343b7a6 | 684 | clk_div = ssp_get_clk_div(drv_data, speed); |
9708c121 SS |
685 | |
686 | if (bits <= 8) { | |
687 | drv_data->n_bytes = 1; | |
9708c121 SS |
688 | drv_data->read = drv_data->read != null_reader ? |
689 | u8_reader : null_reader; | |
690 | drv_data->write = drv_data->write != null_writer ? | |
691 | u8_writer : null_writer; | |
692 | } else if (bits <= 16) { | |
693 | drv_data->n_bytes = 2; | |
9708c121 SS |
694 | drv_data->read = drv_data->read != null_reader ? |
695 | u16_reader : null_reader; | |
696 | drv_data->write = drv_data->write != null_writer ? | |
697 | u16_writer : null_writer; | |
698 | } else if (bits <= 32) { | |
699 | drv_data->n_bytes = 4; | |
9708c121 SS |
700 | drv_data->read = drv_data->read != null_reader ? |
701 | u32_reader : null_reader; | |
702 | drv_data->write = drv_data->write != null_writer ? | |
703 | u32_writer : null_writer; | |
704 | } | |
8d94cc50 SS |
705 | /* if bits/word is changed in dma mode, then must check the |
706 | * thresholds and burst also */ | |
707 | if (chip->enable_dma) { | |
cd7bed00 MW |
708 | if (pxa2xx_spi_set_dma_burst_and_threshold(chip, |
709 | message->spi, | |
8d94cc50 SS |
710 | bits, &dma_burst, |
711 | &dma_thresh)) | |
712 | if (printk_ratelimit()) | |
713 | dev_warn(&message->spi->dev, | |
7e964455 | 714 | "pump_transfers: " |
8d94cc50 SS |
715 | "DMA burst size reduced to " |
716 | "match bits_per_word\n"); | |
717 | } | |
9708c121 SS |
718 | |
719 | cr0 = clk_div | |
720 | | SSCR0_Motorola | |
5daa3ba0 | 721 | | SSCR0_DataSize(bits > 16 ? bits - 16 : bits) |
9708c121 SS |
722 | | SSCR0_SSE |
723 | | (bits > 16 ? SSCR0_EDSS : 0); | |
9708c121 SS |
724 | } |
725 | ||
e0c9905e SS |
726 | message->state = RUNNING_STATE; |
727 | ||
7e964455 | 728 | drv_data->dma_mapped = 0; |
cd7bed00 MW |
729 | if (pxa2xx_spi_dma_is_possible(drv_data->len)) |
730 | drv_data->dma_mapped = pxa2xx_spi_map_dma_buffers(drv_data); | |
7e964455 | 731 | if (drv_data->dma_mapped) { |
e0c9905e SS |
732 | |
733 | /* Ensure we have the correct interrupt handler */ | |
cd7bed00 MW |
734 | drv_data->transfer_handler = pxa2xx_spi_dma_transfer; |
735 | ||
736 | pxa2xx_spi_dma_prepare(drv_data, dma_burst); | |
e0c9905e | 737 | |
8d94cc50 SS |
738 | /* Clear status and start DMA engine */ |
739 | cr1 = chip->cr1 | dma_thresh | drv_data->dma_cr1; | |
e0c9905e | 740 | write_SSSR(drv_data->clear_sr, reg); |
cd7bed00 MW |
741 | |
742 | pxa2xx_spi_dma_start(drv_data); | |
e0c9905e SS |
743 | } else { |
744 | /* Ensure we have the correct interrupt handler */ | |
745 | drv_data->transfer_handler = interrupt_transfer; | |
746 | ||
8d94cc50 SS |
747 | /* Clear status */ |
748 | cr1 = chip->cr1 | chip->threshold | drv_data->int_cr1; | |
2a8626a9 | 749 | write_SSSR_CS(drv_data, drv_data->clear_sr); |
8d94cc50 SS |
750 | } |
751 | ||
a0d2642e MW |
752 | if (is_lpss_ssp(drv_data)) { |
753 | if ((read_SSIRF(reg) & 0xff) != chip->lpss_rx_threshold) | |
754 | write_SSIRF(chip->lpss_rx_threshold, reg); | |
755 | if ((read_SSITF(reg) & 0xffff) != chip->lpss_tx_threshold) | |
756 | write_SSITF(chip->lpss_tx_threshold, reg); | |
757 | } | |
758 | ||
8d94cc50 SS |
759 | /* see if we need to reload the config registers */ |
760 | if ((read_SSCR0(reg) != cr0) | |
761 | || (read_SSCR1(reg) & SSCR1_CHANGE_MASK) != | |
762 | (cr1 & SSCR1_CHANGE_MASK)) { | |
763 | ||
b97c74bd | 764 | /* stop the SSP, and update the other bits */ |
8d94cc50 | 765 | write_SSCR0(cr0 & ~SSCR0_SSE, reg); |
2a8626a9 | 766 | if (!pxa25x_ssp_comp(drv_data)) |
e0c9905e | 767 | write_SSTO(chip->timeout, reg); |
b97c74bd NF |
768 | /* first set CR1 without interrupt and service enables */ |
769 | write_SSCR1(cr1 & SSCR1_CHANGE_MASK, reg); | |
770 | /* restart the SSP */ | |
8d94cc50 | 771 | write_SSCR0(cr0, reg); |
b97c74bd | 772 | |
8d94cc50 | 773 | } else { |
2a8626a9 | 774 | if (!pxa25x_ssp_comp(drv_data)) |
8d94cc50 | 775 | write_SSTO(chip->timeout, reg); |
e0c9905e | 776 | } |
b97c74bd | 777 | |
a7bb3909 | 778 | cs_assert(drv_data); |
b97c74bd NF |
779 | |
780 | /* after chip select, release the data by enabling service | |
781 | * requests and interrupts, without changing any mode bits */ | |
782 | write_SSCR1(cr1, reg); | |
e0c9905e SS |
783 | } |
784 | ||
7f86bde9 MW |
785 | static int pxa2xx_spi_transfer_one_message(struct spi_master *master, |
786 | struct spi_message *msg) | |
e0c9905e | 787 | { |
7f86bde9 | 788 | struct driver_data *drv_data = spi_master_get_devdata(master); |
e0c9905e | 789 | |
7f86bde9 | 790 | drv_data->cur_msg = msg; |
e0c9905e SS |
791 | /* Initial message state*/ |
792 | drv_data->cur_msg->state = START_STATE; | |
793 | drv_data->cur_transfer = list_entry(drv_data->cur_msg->transfers.next, | |
794 | struct spi_transfer, | |
795 | transfer_list); | |
796 | ||
8d94cc50 SS |
797 | /* prepare to setup the SSP, in pump_transfers, using the per |
798 | * chip configuration */ | |
e0c9905e | 799 | drv_data->cur_chip = spi_get_ctldata(drv_data->cur_msg->spi); |
e0c9905e SS |
800 | |
801 | /* Mark as busy and launch transfers */ | |
802 | tasklet_schedule(&drv_data->pump_transfers); | |
e0c9905e SS |
803 | return 0; |
804 | } | |
805 | ||
7d94a505 MW |
806 | static int pxa2xx_spi_prepare_transfer(struct spi_master *master) |
807 | { | |
808 | struct driver_data *drv_data = spi_master_get_devdata(master); | |
809 | ||
810 | pm_runtime_get_sync(&drv_data->pdev->dev); | |
811 | return 0; | |
812 | } | |
813 | ||
814 | static int pxa2xx_spi_unprepare_transfer(struct spi_master *master) | |
815 | { | |
816 | struct driver_data *drv_data = spi_master_get_devdata(master); | |
817 | ||
818 | /* Disable the SSP now */ | |
819 | write_SSCR0(read_SSCR0(drv_data->ioaddr) & ~SSCR0_SSE, | |
820 | drv_data->ioaddr); | |
821 | ||
822 | pm_runtime_mark_last_busy(&drv_data->pdev->dev); | |
823 | pm_runtime_put_autosuspend(&drv_data->pdev->dev); | |
824 | return 0; | |
825 | } | |
826 | ||
a7bb3909 EM |
827 | static int setup_cs(struct spi_device *spi, struct chip_data *chip, |
828 | struct pxa2xx_spi_chip *chip_info) | |
829 | { | |
830 | int err = 0; | |
831 | ||
832 | if (chip == NULL || chip_info == NULL) | |
833 | return 0; | |
834 | ||
835 | /* NOTE: setup() can be called multiple times, possibly with | |
836 | * different chip_info, release previously requested GPIO | |
837 | */ | |
838 | if (gpio_is_valid(chip->gpio_cs)) | |
839 | gpio_free(chip->gpio_cs); | |
840 | ||
841 | /* If (*cs_control) is provided, ignore GPIO chip select */ | |
842 | if (chip_info->cs_control) { | |
843 | chip->cs_control = chip_info->cs_control; | |
844 | return 0; | |
845 | } | |
846 | ||
847 | if (gpio_is_valid(chip_info->gpio_cs)) { | |
848 | err = gpio_request(chip_info->gpio_cs, "SPI_CS"); | |
849 | if (err) { | |
850 | dev_err(&spi->dev, "failed to request chip select " | |
851 | "GPIO%d\n", chip_info->gpio_cs); | |
852 | return err; | |
853 | } | |
854 | ||
855 | chip->gpio_cs = chip_info->gpio_cs; | |
856 | chip->gpio_cs_inverted = spi->mode & SPI_CS_HIGH; | |
857 | ||
858 | err = gpio_direction_output(chip->gpio_cs, | |
859 | !chip->gpio_cs_inverted); | |
860 | } | |
861 | ||
862 | return err; | |
863 | } | |
864 | ||
e0c9905e SS |
865 | static int setup(struct spi_device *spi) |
866 | { | |
867 | struct pxa2xx_spi_chip *chip_info = NULL; | |
868 | struct chip_data *chip; | |
869 | struct driver_data *drv_data = spi_master_get_devdata(spi->master); | |
870 | unsigned int clk_div; | |
a0d2642e MW |
871 | uint tx_thres, tx_hi_thres, rx_thres; |
872 | ||
873 | if (is_lpss_ssp(drv_data)) { | |
874 | tx_thres = LPSS_TX_LOTHRESH_DFLT; | |
875 | tx_hi_thres = LPSS_TX_HITHRESH_DFLT; | |
876 | rx_thres = LPSS_RX_THRESH_DFLT; | |
877 | } else { | |
878 | tx_thres = TX_THRESH_DFLT; | |
879 | tx_hi_thres = 0; | |
880 | rx_thres = RX_THRESH_DFLT; | |
881 | } | |
e0c9905e | 882 | |
2a8626a9 | 883 | if (!pxa25x_ssp_comp(drv_data) |
8d94cc50 SS |
884 | && (spi->bits_per_word < 4 || spi->bits_per_word > 32)) { |
885 | dev_err(&spi->dev, "failed setup: ssp_type=%d, bits/wrd=%d " | |
886 | "b/w not 4-32 for type non-PXA25x_SSP\n", | |
887 | drv_data->ssp_type, spi->bits_per_word); | |
e0c9905e | 888 | return -EINVAL; |
2a8626a9 | 889 | } else if (pxa25x_ssp_comp(drv_data) |
8d94cc50 SS |
890 | && (spi->bits_per_word < 4 |
891 | || spi->bits_per_word > 16)) { | |
892 | dev_err(&spi->dev, "failed setup: ssp_type=%d, bits/wrd=%d " | |
893 | "b/w not 4-16 for type PXA25x_SSP\n", | |
894 | drv_data->ssp_type, spi->bits_per_word); | |
e0c9905e | 895 | return -EINVAL; |
8d94cc50 | 896 | } |
e0c9905e | 897 | |
8d94cc50 | 898 | /* Only alloc on first setup */ |
e0c9905e | 899 | chip = spi_get_ctldata(spi); |
8d94cc50 | 900 | if (!chip) { |
e0c9905e | 901 | chip = kzalloc(sizeof(struct chip_data), GFP_KERNEL); |
8d94cc50 SS |
902 | if (!chip) { |
903 | dev_err(&spi->dev, | |
904 | "failed setup: can't allocate chip data\n"); | |
e0c9905e | 905 | return -ENOMEM; |
8d94cc50 | 906 | } |
e0c9905e | 907 | |
2a8626a9 SAS |
908 | if (drv_data->ssp_type == CE4100_SSP) { |
909 | if (spi->chip_select > 4) { | |
910 | dev_err(&spi->dev, "failed setup: " | |
911 | "cs number must not be > 4.\n"); | |
912 | kfree(chip); | |
913 | return -EINVAL; | |
914 | } | |
915 | ||
916 | chip->frm = spi->chip_select; | |
917 | } else | |
918 | chip->gpio_cs = -1; | |
e0c9905e | 919 | chip->enable_dma = 0; |
f1f640a9 | 920 | chip->timeout = TIMOUT_DFLT; |
e0c9905e SS |
921 | } |
922 | ||
8d94cc50 SS |
923 | /* protocol drivers may change the chip settings, so... |
924 | * if chip_info exists, use it */ | |
925 | chip_info = spi->controller_data; | |
926 | ||
e0c9905e | 927 | /* chip_info isn't always needed */ |
8d94cc50 | 928 | chip->cr1 = 0; |
e0c9905e | 929 | if (chip_info) { |
f1f640a9 VS |
930 | if (chip_info->timeout) |
931 | chip->timeout = chip_info->timeout; | |
932 | if (chip_info->tx_threshold) | |
933 | tx_thres = chip_info->tx_threshold; | |
a0d2642e MW |
934 | if (chip_info->tx_hi_threshold) |
935 | tx_hi_thres = chip_info->tx_hi_threshold; | |
f1f640a9 VS |
936 | if (chip_info->rx_threshold) |
937 | rx_thres = chip_info->rx_threshold; | |
938 | chip->enable_dma = drv_data->master_info->enable_dma; | |
e0c9905e | 939 | chip->dma_threshold = 0; |
e0c9905e SS |
940 | if (chip_info->enable_loopback) |
941 | chip->cr1 = SSCR1_LBM; | |
a3496855 MW |
942 | } else if (ACPI_HANDLE(&spi->dev)) { |
943 | /* | |
944 | * Slave devices enumerated from ACPI namespace don't | |
945 | * usually have chip_info but we still might want to use | |
946 | * DMA with them. | |
947 | */ | |
948 | chip->enable_dma = drv_data->master_info->enable_dma; | |
e0c9905e SS |
949 | } |
950 | ||
f1f640a9 VS |
951 | chip->threshold = (SSCR1_RxTresh(rx_thres) & SSCR1_RFT) | |
952 | (SSCR1_TxTresh(tx_thres) & SSCR1_TFT); | |
953 | ||
a0d2642e MW |
954 | chip->lpss_rx_threshold = SSIRF_RxThresh(rx_thres); |
955 | chip->lpss_tx_threshold = SSITF_TxLoThresh(tx_thres) | |
956 | | SSITF_TxHiThresh(tx_hi_thres); | |
957 | ||
8d94cc50 SS |
958 | /* set dma burst and threshold outside of chip_info path so that if |
959 | * chip_info goes away after setting chip->enable_dma, the | |
960 | * burst and threshold can still respond to changes in bits_per_word */ | |
961 | if (chip->enable_dma) { | |
962 | /* set up legal burst and threshold for dma */ | |
cd7bed00 MW |
963 | if (pxa2xx_spi_set_dma_burst_and_threshold(chip, spi, |
964 | spi->bits_per_word, | |
8d94cc50 SS |
965 | &chip->dma_burst_size, |
966 | &chip->dma_threshold)) { | |
967 | dev_warn(&spi->dev, "in setup: DMA burst size reduced " | |
968 | "to match bits_per_word\n"); | |
969 | } | |
970 | } | |
971 | ||
3343b7a6 | 972 | clk_div = ssp_get_clk_div(drv_data, spi->max_speed_hz); |
9708c121 | 973 | chip->speed_hz = spi->max_speed_hz; |
e0c9905e SS |
974 | |
975 | chip->cr0 = clk_div | |
976 | | SSCR0_Motorola | |
5daa3ba0 SS |
977 | | SSCR0_DataSize(spi->bits_per_word > 16 ? |
978 | spi->bits_per_word - 16 : spi->bits_per_word) | |
e0c9905e SS |
979 | | SSCR0_SSE |
980 | | (spi->bits_per_word > 16 ? SSCR0_EDSS : 0); | |
7f6ee1ad JC |
981 | chip->cr1 &= ~(SSCR1_SPO | SSCR1_SPH); |
982 | chip->cr1 |= (((spi->mode & SPI_CPHA) != 0) ? SSCR1_SPH : 0) | |
983 | | (((spi->mode & SPI_CPOL) != 0) ? SSCR1_SPO : 0); | |
e0c9905e | 984 | |
b833172f MW |
985 | if (spi->mode & SPI_LOOP) |
986 | chip->cr1 |= SSCR1_LBM; | |
987 | ||
e0c9905e | 988 | /* NOTE: PXA25x_SSP _could_ use external clocking ... */ |
2a8626a9 | 989 | if (!pxa25x_ssp_comp(drv_data)) |
7d077197 | 990 | dev_dbg(&spi->dev, "%ld Hz actual, %s\n", |
3343b7a6 | 991 | drv_data->max_clk_rate |
c9840daa EM |
992 | / (1 + ((chip->cr0 & SSCR0_SCR(0xfff)) >> 8)), |
993 | chip->enable_dma ? "DMA" : "PIO"); | |
e0c9905e | 994 | else |
7d077197 | 995 | dev_dbg(&spi->dev, "%ld Hz actual, %s\n", |
3343b7a6 | 996 | drv_data->max_clk_rate / 2 |
c9840daa EM |
997 | / (1 + ((chip->cr0 & SSCR0_SCR(0x0ff)) >> 8)), |
998 | chip->enable_dma ? "DMA" : "PIO"); | |
e0c9905e SS |
999 | |
1000 | if (spi->bits_per_word <= 8) { | |
1001 | chip->n_bytes = 1; | |
e0c9905e SS |
1002 | chip->read = u8_reader; |
1003 | chip->write = u8_writer; | |
1004 | } else if (spi->bits_per_word <= 16) { | |
1005 | chip->n_bytes = 2; | |
e0c9905e SS |
1006 | chip->read = u16_reader; |
1007 | chip->write = u16_writer; | |
1008 | } else if (spi->bits_per_word <= 32) { | |
1009 | chip->cr0 |= SSCR0_EDSS; | |
1010 | chip->n_bytes = 4; | |
e0c9905e SS |
1011 | chip->read = u32_reader; |
1012 | chip->write = u32_writer; | |
1013 | } else { | |
1014 | dev_err(&spi->dev, "invalid wordsize\n"); | |
e0c9905e SS |
1015 | return -ENODEV; |
1016 | } | |
9708c121 | 1017 | chip->bits_per_word = spi->bits_per_word; |
e0c9905e SS |
1018 | |
1019 | spi_set_ctldata(spi, chip); | |
1020 | ||
2a8626a9 SAS |
1021 | if (drv_data->ssp_type == CE4100_SSP) |
1022 | return 0; | |
1023 | ||
a7bb3909 | 1024 | return setup_cs(spi, chip, chip_info); |
e0c9905e SS |
1025 | } |
1026 | ||
0ffa0285 | 1027 | static void cleanup(struct spi_device *spi) |
e0c9905e | 1028 | { |
0ffa0285 | 1029 | struct chip_data *chip = spi_get_ctldata(spi); |
2a8626a9 | 1030 | struct driver_data *drv_data = spi_master_get_devdata(spi->master); |
e0c9905e | 1031 | |
7348d82a DR |
1032 | if (!chip) |
1033 | return; | |
1034 | ||
2a8626a9 | 1035 | if (drv_data->ssp_type != CE4100_SSP && gpio_is_valid(chip->gpio_cs)) |
a7bb3909 EM |
1036 | gpio_free(chip->gpio_cs); |
1037 | ||
e0c9905e SS |
1038 | kfree(chip); |
1039 | } | |
1040 | ||
a3496855 MW |
1041 | #ifdef CONFIG_ACPI |
1042 | static int pxa2xx_spi_acpi_add_dma(struct acpi_resource *res, void *data) | |
1043 | { | |
1044 | struct pxa2xx_spi_master *pdata = data; | |
1045 | ||
1046 | if (res->type == ACPI_RESOURCE_TYPE_FIXED_DMA) { | |
1047 | const struct acpi_resource_fixed_dma *dma; | |
1048 | ||
1049 | dma = &res->data.fixed_dma; | |
1050 | if (pdata->tx_slave_id < 0) { | |
1051 | pdata->tx_slave_id = dma->request_lines; | |
1052 | pdata->tx_chan_id = dma->channels; | |
1053 | } else if (pdata->rx_slave_id < 0) { | |
1054 | pdata->rx_slave_id = dma->request_lines; | |
1055 | pdata->rx_chan_id = dma->channels; | |
1056 | } | |
1057 | } | |
1058 | ||
1059 | /* Tell the ACPI core to skip this resource */ | |
1060 | return 1; | |
1061 | } | |
1062 | ||
1063 | static struct pxa2xx_spi_master * | |
1064 | pxa2xx_spi_acpi_get_pdata(struct platform_device *pdev) | |
1065 | { | |
1066 | struct pxa2xx_spi_master *pdata; | |
1067 | struct list_head resource_list; | |
1068 | struct acpi_device *adev; | |
1069 | struct ssp_device *ssp; | |
1070 | struct resource *res; | |
1071 | int devid; | |
1072 | ||
1073 | if (!ACPI_HANDLE(&pdev->dev) || | |
1074 | acpi_bus_get_device(ACPI_HANDLE(&pdev->dev), &adev)) | |
1075 | return NULL; | |
1076 | ||
1077 | pdata = devm_kzalloc(&pdev->dev, sizeof(*ssp), GFP_KERNEL); | |
1078 | if (!pdata) { | |
1079 | dev_err(&pdev->dev, | |
1080 | "failed to allocate memory for platform data\n"); | |
1081 | return NULL; | |
1082 | } | |
1083 | ||
1084 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
1085 | if (!res) | |
1086 | return NULL; | |
1087 | ||
1088 | ssp = &pdata->ssp; | |
1089 | ||
1090 | ssp->phys_base = res->start; | |
1091 | ssp->mmio_base = devm_request_and_ioremap(&pdev->dev, res); | |
1092 | if (!ssp->mmio_base) { | |
1093 | dev_err(&pdev->dev, "failed to ioremap mmio_base\n"); | |
1094 | return NULL; | |
1095 | } | |
1096 | ||
1097 | ssp->clk = devm_clk_get(&pdev->dev, NULL); | |
1098 | ssp->irq = platform_get_irq(pdev, 0); | |
1099 | ssp->type = LPSS_SSP; | |
1100 | ssp->pdev = pdev; | |
1101 | ||
1102 | ssp->port_id = -1; | |
1103 | if (adev->pnp.unique_id && !kstrtoint(adev->pnp.unique_id, 0, &devid)) | |
1104 | ssp->port_id = devid; | |
1105 | ||
1106 | pdata->num_chipselect = 1; | |
1107 | pdata->rx_slave_id = -1; | |
1108 | pdata->tx_slave_id = -1; | |
1109 | ||
1110 | INIT_LIST_HEAD(&resource_list); | |
1111 | acpi_dev_get_resources(adev, &resource_list, pxa2xx_spi_acpi_add_dma, | |
1112 | pdata); | |
1113 | acpi_dev_free_resource_list(&resource_list); | |
1114 | ||
1115 | pdata->enable_dma = pdata->rx_slave_id >= 0 && pdata->tx_slave_id >= 0; | |
1116 | ||
1117 | return pdata; | |
1118 | } | |
1119 | ||
1120 | static struct acpi_device_id pxa2xx_spi_acpi_match[] = { | |
1121 | { "INT33C0", 0 }, | |
1122 | { "INT33C1", 0 }, | |
1123 | { }, | |
1124 | }; | |
1125 | MODULE_DEVICE_TABLE(acpi, pxa2xx_spi_acpi_match); | |
1126 | #else | |
1127 | static inline struct pxa2xx_spi_master * | |
1128 | pxa2xx_spi_acpi_get_pdata(struct platform_device *pdev) | |
1129 | { | |
1130 | return NULL; | |
1131 | } | |
1132 | #endif | |
1133 | ||
fd4a319b | 1134 | static int pxa2xx_spi_probe(struct platform_device *pdev) |
e0c9905e SS |
1135 | { |
1136 | struct device *dev = &pdev->dev; | |
1137 | struct pxa2xx_spi_master *platform_info; | |
1138 | struct spi_master *master; | |
65a00a20 | 1139 | struct driver_data *drv_data; |
2f1a74e5 | 1140 | struct ssp_device *ssp; |
65a00a20 | 1141 | int status; |
e0c9905e | 1142 | |
851bacf5 MW |
1143 | platform_info = dev_get_platdata(dev); |
1144 | if (!platform_info) { | |
a3496855 MW |
1145 | platform_info = pxa2xx_spi_acpi_get_pdata(pdev); |
1146 | if (!platform_info) { | |
1147 | dev_err(&pdev->dev, "missing platform data\n"); | |
1148 | return -ENODEV; | |
1149 | } | |
851bacf5 | 1150 | } |
e0c9905e | 1151 | |
baffe169 | 1152 | ssp = pxa_ssp_request(pdev->id, pdev->name); |
851bacf5 MW |
1153 | if (!ssp) |
1154 | ssp = &platform_info->ssp; | |
1155 | ||
1156 | if (!ssp->mmio_base) { | |
1157 | dev_err(&pdev->dev, "failed to get ssp\n"); | |
e0c9905e SS |
1158 | return -ENODEV; |
1159 | } | |
1160 | ||
1161 | /* Allocate master with space for drv_data and null dma buffer */ | |
1162 | master = spi_alloc_master(dev, sizeof(struct driver_data) + 16); | |
1163 | if (!master) { | |
65a00a20 | 1164 | dev_err(&pdev->dev, "cannot alloc spi_master\n"); |
baffe169 | 1165 | pxa_ssp_free(ssp); |
e0c9905e SS |
1166 | return -ENOMEM; |
1167 | } | |
1168 | drv_data = spi_master_get_devdata(master); | |
1169 | drv_data->master = master; | |
1170 | drv_data->master_info = platform_info; | |
1171 | drv_data->pdev = pdev; | |
2f1a74e5 | 1172 | drv_data->ssp = ssp; |
e0c9905e | 1173 | |
21486af0 | 1174 | master->dev.parent = &pdev->dev; |
21486af0 | 1175 | master->dev.of_node = pdev->dev.of_node; |
a3496855 | 1176 | ACPI_HANDLE_SET(&master->dev, ACPI_HANDLE(&pdev->dev)); |
e7db06b5 | 1177 | /* the spi->mode bits understood by this driver: */ |
b833172f | 1178 | master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH | SPI_LOOP; |
e7db06b5 | 1179 | |
851bacf5 | 1180 | master->bus_num = ssp->port_id; |
e0c9905e | 1181 | master->num_chipselect = platform_info->num_chipselect; |
7ad0ba91 | 1182 | master->dma_alignment = DMA_ALIGNMENT; |
e0c9905e SS |
1183 | master->cleanup = cleanup; |
1184 | master->setup = setup; | |
7f86bde9 | 1185 | master->transfer_one_message = pxa2xx_spi_transfer_one_message; |
7d94a505 MW |
1186 | master->prepare_transfer_hardware = pxa2xx_spi_prepare_transfer; |
1187 | master->unprepare_transfer_hardware = pxa2xx_spi_unprepare_transfer; | |
e0c9905e | 1188 | |
2f1a74e5 | 1189 | drv_data->ssp_type = ssp->type; |
2b9b84f4 | 1190 | drv_data->null_dma_buf = (u32 *)PTR_ALIGN(&drv_data[1], DMA_ALIGNMENT); |
e0c9905e | 1191 | |
2f1a74e5 | 1192 | drv_data->ioaddr = ssp->mmio_base; |
1193 | drv_data->ssdr_physical = ssp->phys_base + SSDR; | |
2a8626a9 | 1194 | if (pxa25x_ssp_comp(drv_data)) { |
e0c9905e SS |
1195 | drv_data->int_cr1 = SSCR1_TIE | SSCR1_RIE; |
1196 | drv_data->dma_cr1 = 0; | |
1197 | drv_data->clear_sr = SSSR_ROR; | |
1198 | drv_data->mask_sr = SSSR_RFS | SSSR_TFS | SSSR_ROR; | |
1199 | } else { | |
1200 | drv_data->int_cr1 = SSCR1_TIE | SSCR1_RIE | SSCR1_TINTE; | |
5928808e | 1201 | drv_data->dma_cr1 = DEFAULT_DMA_CR1; |
e0c9905e SS |
1202 | drv_data->clear_sr = SSSR_ROR | SSSR_TINT; |
1203 | drv_data->mask_sr = SSSR_TINT | SSSR_RFS | SSSR_TFS | SSSR_ROR; | |
1204 | } | |
1205 | ||
49cbb1e0 SAS |
1206 | status = request_irq(ssp->irq, ssp_int, IRQF_SHARED, dev_name(dev), |
1207 | drv_data); | |
e0c9905e | 1208 | if (status < 0) { |
65a00a20 | 1209 | dev_err(&pdev->dev, "cannot get IRQ %d\n", ssp->irq); |
e0c9905e SS |
1210 | goto out_error_master_alloc; |
1211 | } | |
1212 | ||
1213 | /* Setup DMA if requested */ | |
1214 | drv_data->tx_channel = -1; | |
1215 | drv_data->rx_channel = -1; | |
1216 | if (platform_info->enable_dma) { | |
cd7bed00 MW |
1217 | status = pxa2xx_spi_dma_setup(drv_data); |
1218 | if (status) { | |
1219 | dev_warn(dev, "failed to setup DMA, using PIO\n"); | |
1220 | platform_info->enable_dma = false; | |
e0c9905e | 1221 | } |
e0c9905e SS |
1222 | } |
1223 | ||
1224 | /* Enable SOC clock */ | |
3343b7a6 MW |
1225 | clk_prepare_enable(ssp->clk); |
1226 | ||
1227 | drv_data->max_clk_rate = clk_get_rate(ssp->clk); | |
e0c9905e SS |
1228 | |
1229 | /* Load default SSP configuration */ | |
1230 | write_SSCR0(0, drv_data->ioaddr); | |
f1f640a9 VS |
1231 | write_SSCR1(SSCR1_RxTresh(RX_THRESH_DFLT) | |
1232 | SSCR1_TxTresh(TX_THRESH_DFLT), | |
1233 | drv_data->ioaddr); | |
c9840daa | 1234 | write_SSCR0(SSCR0_SCR(2) |
e0c9905e SS |
1235 | | SSCR0_Motorola |
1236 | | SSCR0_DataSize(8), | |
1237 | drv_data->ioaddr); | |
2a8626a9 | 1238 | if (!pxa25x_ssp_comp(drv_data)) |
e0c9905e SS |
1239 | write_SSTO(0, drv_data->ioaddr); |
1240 | write_SSPSP(0, drv_data->ioaddr); | |
1241 | ||
a0d2642e MW |
1242 | lpss_ssp_setup(drv_data); |
1243 | ||
7f86bde9 MW |
1244 | tasklet_init(&drv_data->pump_transfers, pump_transfers, |
1245 | (unsigned long)drv_data); | |
e0c9905e SS |
1246 | |
1247 | /* Register with the SPI framework */ | |
1248 | platform_set_drvdata(pdev, drv_data); | |
1249 | status = spi_register_master(master); | |
1250 | if (status != 0) { | |
1251 | dev_err(&pdev->dev, "problem registering spi master\n"); | |
7f86bde9 | 1252 | goto out_error_clock_enabled; |
e0c9905e SS |
1253 | } |
1254 | ||
7d94a505 MW |
1255 | pm_runtime_set_autosuspend_delay(&pdev->dev, 50); |
1256 | pm_runtime_use_autosuspend(&pdev->dev); | |
1257 | pm_runtime_set_active(&pdev->dev); | |
1258 | pm_runtime_enable(&pdev->dev); | |
1259 | ||
e0c9905e SS |
1260 | return status; |
1261 | ||
e0c9905e | 1262 | out_error_clock_enabled: |
3343b7a6 | 1263 | clk_disable_unprepare(ssp->clk); |
cd7bed00 | 1264 | pxa2xx_spi_dma_release(drv_data); |
2f1a74e5 | 1265 | free_irq(ssp->irq, drv_data); |
e0c9905e SS |
1266 | |
1267 | out_error_master_alloc: | |
1268 | spi_master_put(master); | |
baffe169 | 1269 | pxa_ssp_free(ssp); |
e0c9905e SS |
1270 | return status; |
1271 | } | |
1272 | ||
1273 | static int pxa2xx_spi_remove(struct platform_device *pdev) | |
1274 | { | |
1275 | struct driver_data *drv_data = platform_get_drvdata(pdev); | |
51e911e2 | 1276 | struct ssp_device *ssp; |
e0c9905e SS |
1277 | |
1278 | if (!drv_data) | |
1279 | return 0; | |
51e911e2 | 1280 | ssp = drv_data->ssp; |
e0c9905e | 1281 | |
7d94a505 MW |
1282 | pm_runtime_get_sync(&pdev->dev); |
1283 | ||
e0c9905e SS |
1284 | /* Disable the SSP at the peripheral and SOC level */ |
1285 | write_SSCR0(0, drv_data->ioaddr); | |
3343b7a6 | 1286 | clk_disable_unprepare(ssp->clk); |
e0c9905e SS |
1287 | |
1288 | /* Release DMA */ | |
cd7bed00 MW |
1289 | if (drv_data->master_info->enable_dma) |
1290 | pxa2xx_spi_dma_release(drv_data); | |
e0c9905e | 1291 | |
7d94a505 MW |
1292 | pm_runtime_put_noidle(&pdev->dev); |
1293 | pm_runtime_disable(&pdev->dev); | |
1294 | ||
e0c9905e | 1295 | /* Release IRQ */ |
2f1a74e5 | 1296 | free_irq(ssp->irq, drv_data); |
1297 | ||
1298 | /* Release SSP */ | |
baffe169 | 1299 | pxa_ssp_free(ssp); |
e0c9905e SS |
1300 | |
1301 | /* Disconnect from the SPI framework */ | |
1302 | spi_unregister_master(drv_data->master); | |
1303 | ||
1304 | /* Prevent double remove */ | |
1305 | platform_set_drvdata(pdev, NULL); | |
1306 | ||
1307 | return 0; | |
1308 | } | |
1309 | ||
1310 | static void pxa2xx_spi_shutdown(struct platform_device *pdev) | |
1311 | { | |
1312 | int status = 0; | |
1313 | ||
1314 | if ((status = pxa2xx_spi_remove(pdev)) != 0) | |
1315 | dev_err(&pdev->dev, "shutdown failed with %d\n", status); | |
1316 | } | |
1317 | ||
1318 | #ifdef CONFIG_PM | |
86d2593a | 1319 | static int pxa2xx_spi_suspend(struct device *dev) |
e0c9905e | 1320 | { |
86d2593a | 1321 | struct driver_data *drv_data = dev_get_drvdata(dev); |
2f1a74e5 | 1322 | struct ssp_device *ssp = drv_data->ssp; |
e0c9905e SS |
1323 | int status = 0; |
1324 | ||
7f86bde9 | 1325 | status = spi_master_suspend(drv_data->master); |
e0c9905e SS |
1326 | if (status != 0) |
1327 | return status; | |
1328 | write_SSCR0(0, drv_data->ioaddr); | |
3343b7a6 | 1329 | clk_disable_unprepare(ssp->clk); |
e0c9905e SS |
1330 | |
1331 | return 0; | |
1332 | } | |
1333 | ||
86d2593a | 1334 | static int pxa2xx_spi_resume(struct device *dev) |
e0c9905e | 1335 | { |
86d2593a | 1336 | struct driver_data *drv_data = dev_get_drvdata(dev); |
2f1a74e5 | 1337 | struct ssp_device *ssp = drv_data->ssp; |
e0c9905e SS |
1338 | int status = 0; |
1339 | ||
cd7bed00 | 1340 | pxa2xx_spi_dma_resume(drv_data); |
148da331 | 1341 | |
e0c9905e | 1342 | /* Enable the SSP clock */ |
3343b7a6 | 1343 | clk_prepare_enable(ssp->clk); |
e0c9905e SS |
1344 | |
1345 | /* Start the queue running */ | |
7f86bde9 | 1346 | status = spi_master_resume(drv_data->master); |
e0c9905e | 1347 | if (status != 0) { |
86d2593a | 1348 | dev_err(dev, "problem starting queue (%d)\n", status); |
e0c9905e SS |
1349 | return status; |
1350 | } | |
1351 | ||
1352 | return 0; | |
1353 | } | |
7d94a505 MW |
1354 | #endif |
1355 | ||
1356 | #ifdef CONFIG_PM_RUNTIME | |
1357 | static int pxa2xx_spi_runtime_suspend(struct device *dev) | |
1358 | { | |
1359 | struct driver_data *drv_data = dev_get_drvdata(dev); | |
1360 | ||
1361 | clk_disable_unprepare(drv_data->ssp->clk); | |
1362 | return 0; | |
1363 | } | |
1364 | ||
1365 | static int pxa2xx_spi_runtime_resume(struct device *dev) | |
1366 | { | |
1367 | struct driver_data *drv_data = dev_get_drvdata(dev); | |
1368 | ||
1369 | clk_prepare_enable(drv_data->ssp->clk); | |
1370 | return 0; | |
1371 | } | |
1372 | #endif | |
86d2593a | 1373 | |
47145210 | 1374 | static const struct dev_pm_ops pxa2xx_spi_pm_ops = { |
7d94a505 MW |
1375 | SET_SYSTEM_SLEEP_PM_OPS(pxa2xx_spi_suspend, pxa2xx_spi_resume) |
1376 | SET_RUNTIME_PM_OPS(pxa2xx_spi_runtime_suspend, | |
1377 | pxa2xx_spi_runtime_resume, NULL) | |
86d2593a | 1378 | }; |
e0c9905e SS |
1379 | |
1380 | static struct platform_driver driver = { | |
1381 | .driver = { | |
86d2593a MR |
1382 | .name = "pxa2xx-spi", |
1383 | .owner = THIS_MODULE, | |
86d2593a | 1384 | .pm = &pxa2xx_spi_pm_ops, |
a3496855 | 1385 | .acpi_match_table = ACPI_PTR(pxa2xx_spi_acpi_match), |
e0c9905e | 1386 | }, |
fbd29a14 | 1387 | .probe = pxa2xx_spi_probe, |
d1e44d9c | 1388 | .remove = pxa2xx_spi_remove, |
e0c9905e | 1389 | .shutdown = pxa2xx_spi_shutdown, |
e0c9905e SS |
1390 | }; |
1391 | ||
1392 | static int __init pxa2xx_spi_init(void) | |
1393 | { | |
fbd29a14 | 1394 | return platform_driver_register(&driver); |
e0c9905e | 1395 | } |
5b61a749 | 1396 | subsys_initcall(pxa2xx_spi_init); |
e0c9905e SS |
1397 | |
1398 | static void __exit pxa2xx_spi_exit(void) | |
1399 | { | |
1400 | platform_driver_unregister(&driver); | |
1401 | } | |
1402 | module_exit(pxa2xx_spi_exit); |