[deliverable/linux.git] / drivers / spi / spi-sh-hspi.c

/*
 * SuperH HSPI bus driver
 *
 * Copyright (C) 2011  Kuninori Morimoto
 *
 * Based on spi-sh.c:
 * Based on pxa2xx_spi.c:
 * Copyright (C) 2011 Renesas Solutions Corp.
 * Copyright (C) 2005 Stephen Street / StreetFire Sound Labs
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; version 2 of the License.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
 *
 */
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/timer.h>
#include <linux/delay.h>
#include <linux/list.h>
#include <linux/interrupt.h>
#include <linux/platform_device.h>
#include <linux/pm_runtime.h>
#include <linux/io.h>
#include <linux/spi/spi.h>
#include <linux/spi/sh_hspi.h>

#define SPCR	0x00
#define SPSR	0x04
#define SPSCR	0x08
#define SPTBR	0x0C
#define SPRBR	0x10
#define SPCR2	0x14

/* SPSR */
#define RXFL	(1 << 2)

#define hspi2info(h)	(h->dev->platform_data)

struct hspi_priv {
	void __iomem *addr;
	struct spi_master *master;
	struct device *dev;
};

/*
 *		basic function
 */
static void hspi_write(struct hspi_priv *hspi, int reg, u32 val)
{
	iowrite32(val, hspi->addr + reg);
}

static u32 hspi_read(struct hspi_priv *hspi, int reg)
{
	return ioread32(hspi->addr + reg);
}

/*
 *		transfer function
 */
static int hspi_status_check_timeout(struct hspi_priv *hspi, u32 mask, u32 val)
{
	int t = 256;

	while (t--) {
		if ((mask & hspi_read(hspi, SPSR)) == val)
			return 0;

		msleep(20);
	}

	dev_err(hspi->dev, "timeout\n");
	return -ETIMEDOUT;
}

static int hspi_push(struct hspi_priv *hspi, struct spi_message *msg,
		     struct spi_transfer *t)
{
	int i, ret;
	u8 *data = (u8 *)t->tx_buf;

	/*
	 * FIXME
	 * very simple, but polling transfer
	 */
	for (i = 0; i < t->len; i++) {
		/* wait remains */
		ret = hspi_status_check_timeout(hspi, 0x1, 0x0);
		if (ret < 0)
			return ret;

		hspi_write(hspi, SPTBR, (u32)data[i]);

		/* wait recive */
		ret = hspi_status_check_timeout(hspi, 0x4, 0x4);
		if (ret < 0)
			return ret;

		/* dummy read */
		hspi_read(hspi, SPRBR);
	}

	return 0;
}

static int hspi_pop(struct hspi_priv *hspi, struct spi_message *msg,
		    struct spi_transfer *t)
{
	int i, ret;
	u8 *data = (u8 *)t->rx_buf;

	/*
	 * FIXME
	 * very simple, but polling receive
	 */
	for (i = 0; i < t->len; i++) {
		/* wait remains */
		ret = hspi_status_check_timeout(hspi, 0x1, 0);
		if (ret < 0)
			return ret;

		/* dummy write */
		hspi_write(hspi, SPTBR, 0x0);

		/* wait recive */
		ret = hspi_status_check_timeout(hspi, 0x4, 0x4);
		if (ret < 0)
			return ret;

		data[i] = (u8)hspi_read(hspi, SPRBR);
	}

	return 0;
}

/*
 *		spi master function
 */
static int hspi_prepare_transfer(struct spi_master *master)
{
	struct hspi_priv *hspi = spi_master_get_devdata(master);

	pm_runtime_get_sync(hspi->dev);
	return 0;
}

static int hspi_unprepare_transfer(struct spi_master *master)
{
	struct hspi_priv *hspi = spi_master_get_devdata(master);

	pm_runtime_put_sync(hspi->dev);
	return 0;
}

static int hspi_transfer_one_message(struct spi_master *master,
				     struct spi_message *msg)
{
	struct hspi_priv *hspi = spi_master_get_devdata(master);
	struct spi_transfer *t;
	int ret;

	dev_dbg(hspi->dev, "%s\n", __func__);

	ret = 0;
	list_for_each_entry(t, &msg->transfers, transfer_list) {
		if (t->tx_buf) {
			ret = hspi_push(hspi, msg, t);
			if (ret < 0)
				goto error;
		}
		if (t->rx_buf) {
			ret = hspi_pop(hspi, msg, t);
			if (ret < 0)
				goto error;
		}
		msg->actual_length += t->len;
	}
error:

	msg->status = ret;
	spi_finalize_current_message(master);

	return ret;
}

static int hspi_setup(struct spi_device *spi)
{
	struct hspi_priv *hspi = spi_master_get_devdata(spi->master);
	struct device *dev = hspi->dev;
	struct sh_hspi_info *info = hspi2info(hspi);
	u32 data;

	if (8 != spi->bits_per_word) {
		dev_err(dev, "bits_per_word should be 8\n");
		return -EIO;
	}

	/* setup first of all in under pm_runtime */
	data = SH_HSPI_CLK_DIVC(info->flags);

	if (info->flags & SH_HSPI_FBS)
		data |= 1 << 7;
	if (info->flags & SH_HSPI_CLKP_HIGH)
		data |= 1 << 6;
	if (info->flags & SH_HSPI_IDIV_DIV128)
		data |= 1 << 5;

	hspi_write(hspi, SPCR, data);
	hspi_write(hspi, SPSR, 0x0);
	hspi_write(hspi, SPSCR, 0x1);	/* master mode */

	dev_dbg(dev, "%s setup\n", spi->modalias);

	return 0;
}

static void hspi_cleanup(struct spi_device *spi)
{
	struct hspi_priv *hspi = spi_master_get_devdata(spi->master);
	struct device *dev = hspi->dev;

	dev_dbg(dev, "%s cleanup\n", spi->modalias);
}

static int __devinit hspi_probe(struct platform_device *pdev)
{
	struct resource *res;
	struct spi_master *master;
	struct hspi_priv *hspi;
	int ret;

	/* get base addr */
	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	if (!res) {
		dev_err(&pdev->dev, "invalid resource\n");
		return -EINVAL;
	}

	master = spi_alloc_master(&pdev->dev, sizeof(*hspi));
	if (!master) {
		dev_err(&pdev->dev, "spi_alloc_master error.\n");
		return -ENOMEM;
	}

	hspi = spi_master_get_devdata(master);
	dev_set_drvdata(&pdev->dev, hspi);

	/* init hspi */
	hspi->master	= master;
	hspi->dev	= &pdev->dev;
	hspi->addr	= devm_ioremap(hspi->dev,
				       res->start, resource_size(res));
	if (!hspi->addr) {
		dev_err(&pdev->dev, "ioremap error.\n");
		ret = -ENOMEM;
		goto error1;
	}

	master->num_chipselect	= 1;
	master->bus_num		= pdev->id;
	master->setup		= hspi_setup;
	master->cleanup		= hspi_cleanup;
	master->mode_bits	= SPI_CPOL | SPI_CPHA;
	master->prepare_transfer_hardware	= hspi_prepare_transfer;
	master->transfer_one_message		= hspi_transfer_one_message;
	master->unprepare_transfer_hardware	= hspi_unprepare_transfer;
	ret = spi_register_master(master);
	if (ret < 0) {
		dev_err(&pdev->dev, "spi_register_master error.\n");
		goto error2;
	}

	pm_runtime_enable(&pdev->dev);

	dev_info(&pdev->dev, "probed\n");

	return 0;

 error2:
	devm_iounmap(hspi->dev, hspi->addr);
 error1:
	spi_master_put(master);

	return ret;
}

static int __devexit hspi_remove(struct platform_device *pdev)
{
	struct hspi_priv *hspi = dev_get_drvdata(&pdev->dev);

	pm_runtime_disable(&pdev->dev);

	spi_unregister_master(hspi->master);
	devm_iounmap(hspi->dev, hspi->addr);

	return 0;
}

static struct platform_driver hspi_driver = {
	.probe = hspi_probe,
	.remove = __devexit_p(hspi_remove),
	.driver = {
		.name = "sh-hspi",
		.owner = THIS_MODULE,
	},
};
module_platform_driver(hspi_driver);

MODULE_DESCRIPTION("SuperH HSPI bus driver");
MODULE_LICENSE("GPL");
MODULE_AUTHOR("Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>");
MODULE_ALIAS("platform:sh_spi");
Commit	Line	Data
d1c8bbd7 KM	1	/*
	2	* SuperH HSPI bus driver
	3	*
	4	* Copyright (C) 2011 Kuninori Morimoto
	5	*
	6	* Based on spi-sh.c:
	7	* Based on pxa2xx_spi.c:
	8	* Copyright (C) 2011 Renesas Solutions Corp.
	9	* Copyright (C) 2005 Stephen Street / StreetFire Sound Labs
	10	*
	11	* This program is free software; you can redistribute it and/or modify
	12	* it under the terms of the GNU General Public License as published by
	13	* the Free Software Foundation; version 2 of the License.
	14	*
	15	* This program is distributed in the hope that it will be useful,
	16	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	17	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	18	* GNU General Public License for more details.
	19	*
	20	* You should have received a copy of the GNU General Public License
	21	* along with this program; if not, write to the Free Software
	22	* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
	23	*
	24	*/
	25	#include <linux/module.h>
	26	#include <linux/kernel.h>
	27	#include <linux/timer.h>
	28	#include <linux/delay.h>
	29	#include <linux/list.h>
d1c8bbd7 KM	30	#include <linux/interrupt.h>
	31	#include <linux/platform_device.h>
	32	#include <linux/pm_runtime.h>
	33	#include <linux/io.h>
	34	#include <linux/spi/spi.h>
	35	#include <linux/spi/sh_hspi.h>
	36
	37	#define SPCR 0x00
	38	#define SPSR 0x04
	39	#define SPSCR 0x08
	40	#define SPTBR 0x0C
	41	#define SPRBR 0x10
	42	#define SPCR2 0x14
	43
	44	/* SPSR */
	45	#define RXFL (1 << 2)
	46
	47	#define hspi2info(h) (h->dev->platform_data)
	48
	49	struct hspi_priv {
	50	void __iomem *addr;
	51	struct spi_master *master;
d1c8bbd7	52	struct device *dev;
d1c8bbd7 KM	53	};
	54
	55	/*
	56	* basic function
	57	*/
	58	static void hspi_write(struct hspi_priv *hspi, int reg, u32 val)
	59	{
	60	iowrite32(val, hspi->addr + reg);
	61	}
	62
	63	static u32 hspi_read(struct hspi_priv *hspi, int reg)
	64	{
	65	return ioread32(hspi->addr + reg);
	66	}
	67
	68	/*
	69	* transfer function
	70	*/
	71	static int hspi_status_check_timeout(struct hspi_priv *hspi, u32 mask, u32 val)
	72	{
	73	int t = 256;
	74
	75	while (t--) {
	76	if ((mask & hspi_read(hspi, SPSR)) == val)
	77	return 0;
	78
	79	msleep(20);
	80	}
	81
	82	dev_err(hspi->dev, "timeout\n");
	83	return -ETIMEDOUT;
	84	}
	85
	86	static int hspi_push(struct hspi_priv hspi, struct spi_message msg,
	87	struct spi_transfer *t)
	88	{
	89	int i, ret;
	90	u8 data = (u8 )t->tx_buf;
	91
	92	/*
	93	* FIXME
	94	* very simple, but polling transfer
	95	*/
	96	for (i = 0; i < t->len; i++) {
	97	/* wait remains */
	98	ret = hspi_status_check_timeout(hspi, 0x1, 0x0);
	99	if (ret < 0)
	100	return ret;
	101
	102	hspi_write(hspi, SPTBR, (u32)data[i]);
	103
	104	/* wait recive */
	105	ret = hspi_status_check_timeout(hspi, 0x4, 0x4);
	106	if (ret < 0)
	107	return ret;
	108
	109	/* dummy read */
	110	hspi_read(hspi, SPRBR);
	111	}
	112
	113	return 0;
	114	}
	115
	116	static int hspi_pop(struct hspi_priv hspi, struct spi_message msg,
117	struct spi_transfer *t)
118	{
119	int i, ret;
120	u8 data = (u8 )t->rx_buf;
121
122	/*
123	* FIXME
124	* very simple, but polling receive
125	*/
126	for (i = 0; i < t->len; i++) {
127	/* wait remains */
128	ret = hspi_status_check_timeout(hspi, 0x1, 0);
129	if (ret < 0)
130	return ret;
131
132	/* dummy write */
133	hspi_write(hspi, SPTBR, 0x0);
134
135	/* wait recive */
136	ret = hspi_status_check_timeout(hspi, 0x4, 0x4);
137	if (ret < 0)
138	return ret;
139
140	data[i] = (u8)hspi_read(hspi, SPRBR);
141	}
142
143	return 0;
144	}
145
ec139b67 KM	146	/*
	147	* spi master function
	148	*/
	149	static int hspi_prepare_transfer(struct spi_master *master)
d1c8bbd7	150	{
ec139b67	151	struct hspi_priv *hspi = spi_master_get_devdata(master);
d1c8bbd7	152
d1c8bbd7	153	pm_runtime_get_sync(hspi->dev);
ec139b67 KM	154	return 0;
ec139b67 KM	155	}
d1c8bbd7	156
ec139b67 KM	157	static int hspi_unprepare_transfer(struct spi_master *master)
	158	{
	159	struct hspi_priv *hspi = spi_master_get_devdata(master);
d1c8bbd7	160
ec139b67 KM	161	pm_runtime_put_sync(hspi->dev);
	162	return 0;
	163	}
d1c8bbd7	164
ec139b67 KM	165	static int hspi_transfer_one_message(struct spi_master *master,
	166	struct spi_message *msg)
	167	{
	168	struct hspi_priv *hspi = spi_master_get_devdata(master);
	169	struct spi_transfer *t;
	170	int ret;
d1c8bbd7	171
ec139b67	172	dev_dbg(hspi->dev, "%s\n", __func__);
d1c8bbd7	173
ec139b67 KM	174	ret = 0;
	175	list_for_each_entry(t, &msg->transfers, transfer_list) {
	176	if (t->tx_buf) {
	177	ret = hspi_push(hspi, msg, t);
	178	if (ret < 0)
	179	goto error;
d1c8bbd7	180	}
ec139b67 KM	181	if (t->rx_buf) {
	182	ret = hspi_pop(hspi, msg, t);
	183	if (ret < 0)
	184	goto error;
d1c8bbd7	185	}
ec139b67	186	msg->actual_length += t->len;
d1c8bbd7	187	}
ec139b67	188	error:
d1c8bbd7	189
ec139b67 KM	190	msg->status = ret;
ec139b67 KM	191	spi_finalize_current_message(master);
d1c8bbd7	192
ec139b67	193	return ret;
d1c8bbd7 KM	194	}
d1c8bbd7 KM	195
d1c8bbd7 KM	196	static int hspi_setup(struct spi_device *spi)
	197	{
	198	struct hspi_priv *hspi = spi_master_get_devdata(spi->master);
	199	struct device *dev = hspi->dev;
ec139b67 KM	200	struct sh_hspi_info *info = hspi2info(hspi);
ec139b67 KM	201	u32 data;
d1c8bbd7 KM	202
	203	if (8 != spi->bits_per_word) {
	204	dev_err(dev, "bits_per_word should be 8\n");
	205	return -EIO;
	206	}
	207
ec139b67 KM	208	/* setup first of all in under pm_runtime */
	209	data = SH_HSPI_CLK_DIVC(info->flags);
	210
	211	if (info->flags & SH_HSPI_FBS)
	212	data \|= 1 << 7;
	213	if (info->flags & SH_HSPI_CLKP_HIGH)
	214	data \|= 1 << 6;
	215	if (info->flags & SH_HSPI_IDIV_DIV128)
	216	data \|= 1 << 5;
	217
	218	hspi_write(hspi, SPCR, data);
	219	hspi_write(hspi, SPSR, 0x0);
	220	hspi_write(hspi, SPSCR, 0x1); /* master mode */
	221
d1c8bbd7 KM	222	dev_dbg(dev, "%s setup\n", spi->modalias);
	223
	224	return 0;
	225	}
	226
	227	static void hspi_cleanup(struct spi_device *spi)
	228	{
	229	struct hspi_priv *hspi = spi_master_get_devdata(spi->master);
	230	struct device *dev = hspi->dev;
	231
	232	dev_dbg(dev, "%s cleanup\n", spi->modalias);
	233	}
	234
d1c8bbd7 KM	235	static int __devinit hspi_probe(struct platform_device *pdev)
	236	{
	237	struct resource *res;
	238	struct spi_master *master;
	239	struct hspi_priv *hspi;
	240	int ret;
	241
	242	/* get base addr */
	243	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	244	if (!res) {
	245	dev_err(&pdev->dev, "invalid resource\n");
	246	return -EINVAL;
	247	}
	248
	249	master = spi_alloc_master(&pdev->dev, sizeof(*hspi));
	250	if (!master) {
	251	dev_err(&pdev->dev, "spi_alloc_master error.\n");
	252	return -ENOMEM;
	253	}
	254
	255	hspi = spi_master_get_devdata(master);
	256	dev_set_drvdata(&pdev->dev, hspi);
	257
	258	/* init hspi */
	259	hspi->master = master;
	260	hspi->dev = &pdev->dev;
	261	hspi->addr = devm_ioremap(hspi->dev,
	262	res->start, resource_size(res));
	263	if (!hspi->addr) {
	264	dev_err(&pdev->dev, "ioremap error.\n");
	265	ret = -ENOMEM;
	266	goto error1;
	267	}
d1c8bbd7 KM	268
	269	master->num_chipselect = 1;
	270	master->bus_num = pdev->id;
	271	master->setup = hspi_setup;
d1c8bbd7 KM	272	master->cleanup = hspi_cleanup;
d1c8bbd7 KM	273	master->mode_bits = SPI_CPOL \| SPI_CPHA;
ec139b67 KM	274	master->prepare_transfer_hardware = hspi_prepare_transfer;
	275	master->transfer_one_message = hspi_transfer_one_message;
	276	master->unprepare_transfer_hardware = hspi_unprepare_transfer;
d1c8bbd7 KM	277	ret = spi_register_master(master);
	278	if (ret < 0) {
	279	dev_err(&pdev->dev, "spi_register_master error.\n");
ec139b67	280	goto error2;
d1c8bbd7 KM	281	}
	282
	283	pm_runtime_enable(&pdev->dev);
	284
	285	dev_info(&pdev->dev, "probed\n");
	286
	287	return 0;
	288
d1c8bbd7 KM	289	error2:
	290	devm_iounmap(hspi->dev, hspi->addr);
	291	error1:
	292	spi_master_put(master);
	293
	294	return ret;
	295	}
	296
	297	static int __devexit hspi_remove(struct platform_device *pdev)
	298	{
	299	struct hspi_priv *hspi = dev_get_drvdata(&pdev->dev);
	300
	301	pm_runtime_disable(&pdev->dev);
	302
	303	spi_unregister_master(hspi->master);
d1c8bbd7 KM	304	devm_iounmap(hspi->dev, hspi->addr);
	305
	306	return 0;
	307	}
	308
	309	static struct platform_driver hspi_driver = {
	310	.probe = hspi_probe,
	311	.remove = __devexit_p(hspi_remove),
	312	.driver = {
	313	.name = "sh-hspi",
	314	.owner = THIS_MODULE,
	315	},
	316	};
	317	module_platform_driver(hspi_driver);
	318
	319	MODULE_DESCRIPTION("SuperH HSPI bus driver");
	320	MODULE_LICENSE("GPL");
	321	MODULE_AUTHOR("Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>");
	322	MODULE_ALIAS("platform:sh_spi");