Commit | Line | Data |
---|---|---|
8051effc MD |
1 | /* |
2 | * SuperH MSIOF SPI Master Interface | |
3 | * | |
4 | * Copyright (c) 2009 Magnus Damm | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License version 2 as | |
8 | * published by the Free Software Foundation. | |
9 | * | |
10 | */ | |
11 | ||
e2dbf5eb GL |
12 | #include <linux/bitmap.h> |
13 | #include <linux/clk.h> | |
14 | #include <linux/completion.h> | |
8051effc | 15 | #include <linux/delay.h> |
e2dbf5eb GL |
16 | #include <linux/err.h> |
17 | #include <linux/gpio.h> | |
18 | #include <linux/init.h> | |
8051effc | 19 | #include <linux/interrupt.h> |
e2dbf5eb GL |
20 | #include <linux/io.h> |
21 | #include <linux/kernel.h> | |
d7614de4 | 22 | #include <linux/module.h> |
8051effc | 23 | #include <linux/platform_device.h> |
8051effc | 24 | #include <linux/pm_runtime.h> |
8051effc | 25 | |
e2dbf5eb | 26 | #include <linux/spi/sh_msiof.h> |
8051effc MD |
27 | #include <linux/spi/spi.h> |
28 | #include <linux/spi/spi_bitbang.h> | |
8051effc | 29 | |
8051effc MD |
30 | #include <asm/unaligned.h> |
31 | ||
32 | struct sh_msiof_spi_priv { | |
33 | struct spi_bitbang bitbang; /* must be first for spi_bitbang.c */ | |
34 | void __iomem *mapbase; | |
35 | struct clk *clk; | |
36 | struct platform_device *pdev; | |
37 | struct sh_msiof_spi_info *info; | |
38 | struct completion done; | |
39 | unsigned long flags; | |
40 | int tx_fifo_size; | |
41 | int rx_fifo_size; | |
42 | }; | |
43 | ||
44 | #define TMDR1 0x00 | |
45 | #define TMDR2 0x04 | |
46 | #define TMDR3 0x08 | |
47 | #define RMDR1 0x10 | |
48 | #define RMDR2 0x14 | |
49 | #define RMDR3 0x18 | |
50 | #define TSCR 0x20 | |
51 | #define RSCR 0x22 | |
52 | #define CTR 0x28 | |
53 | #define FCTR 0x30 | |
54 | #define STR 0x40 | |
55 | #define IER 0x44 | |
56 | #define TDR1 0x48 | |
57 | #define TDR2 0x4c | |
58 | #define TFDR 0x50 | |
59 | #define RDR1 0x58 | |
60 | #define RDR2 0x5c | |
61 | #define RFDR 0x60 | |
62 | ||
63 | #define CTR_TSCKE (1 << 15) | |
64 | #define CTR_TFSE (1 << 14) | |
65 | #define CTR_TXE (1 << 9) | |
66 | #define CTR_RXE (1 << 8) | |
67 | ||
68 | #define STR_TEOF (1 << 23) | |
69 | #define STR_REOF (1 << 7) | |
70 | ||
e2dbf5eb | 71 | static u32 sh_msiof_read(struct sh_msiof_spi_priv *p, int reg_offs) |
8051effc MD |
72 | { |
73 | switch (reg_offs) { | |
74 | case TSCR: | |
75 | case RSCR: | |
76 | return ioread16(p->mapbase + reg_offs); | |
77 | default: | |
78 | return ioread32(p->mapbase + reg_offs); | |
79 | } | |
80 | } | |
81 | ||
82 | static void sh_msiof_write(struct sh_msiof_spi_priv *p, int reg_offs, | |
e2dbf5eb | 83 | u32 value) |
8051effc MD |
84 | { |
85 | switch (reg_offs) { | |
86 | case TSCR: | |
87 | case RSCR: | |
88 | iowrite16(value, p->mapbase + reg_offs); | |
89 | break; | |
90 | default: | |
91 | iowrite32(value, p->mapbase + reg_offs); | |
92 | break; | |
93 | } | |
94 | } | |
95 | ||
96 | static int sh_msiof_modify_ctr_wait(struct sh_msiof_spi_priv *p, | |
e2dbf5eb | 97 | u32 clr, u32 set) |
8051effc | 98 | { |
e2dbf5eb GL |
99 | u32 mask = clr | set; |
100 | u32 data; | |
8051effc MD |
101 | int k; |
102 | ||
103 | data = sh_msiof_read(p, CTR); | |
104 | data &= ~clr; | |
105 | data |= set; | |
106 | sh_msiof_write(p, CTR, data); | |
107 | ||
108 | for (k = 100; k > 0; k--) { | |
109 | if ((sh_msiof_read(p, CTR) & mask) == set) | |
110 | break; | |
111 | ||
112 | udelay(10); | |
113 | } | |
114 | ||
115 | return k > 0 ? 0 : -ETIMEDOUT; | |
116 | } | |
117 | ||
118 | static irqreturn_t sh_msiof_spi_irq(int irq, void *data) | |
119 | { | |
120 | struct sh_msiof_spi_priv *p = data; | |
121 | ||
122 | /* just disable the interrupt and wake up */ | |
123 | sh_msiof_write(p, IER, 0); | |
124 | complete(&p->done); | |
125 | ||
126 | return IRQ_HANDLED; | |
127 | } | |
128 | ||
129 | static struct { | |
130 | unsigned short div; | |
131 | unsigned short scr; | |
132 | } const sh_msiof_spi_clk_table[] = { | |
133 | { 1, 0x0007 }, | |
134 | { 2, 0x0000 }, | |
135 | { 4, 0x0001 }, | |
136 | { 8, 0x0002 }, | |
137 | { 16, 0x0003 }, | |
138 | { 32, 0x0004 }, | |
139 | { 64, 0x1f00 }, | |
140 | { 128, 0x1f01 }, | |
141 | { 256, 0x1f02 }, | |
142 | { 512, 0x1f03 }, | |
143 | { 1024, 0x1f04 }, | |
144 | }; | |
145 | ||
146 | static void sh_msiof_spi_set_clk_regs(struct sh_msiof_spi_priv *p, | |
147 | unsigned long parent_rate, | |
148 | unsigned long spi_hz) | |
149 | { | |
150 | unsigned long div = 1024; | |
151 | size_t k; | |
152 | ||
153 | if (!WARN_ON(!spi_hz || !parent_rate)) | |
154 | div = parent_rate / spi_hz; | |
155 | ||
156 | /* TODO: make more fine grained */ | |
157 | ||
158 | for (k = 0; k < ARRAY_SIZE(sh_msiof_spi_clk_table); k++) { | |
159 | if (sh_msiof_spi_clk_table[k].div >= div) | |
160 | break; | |
161 | } | |
162 | ||
163 | k = min_t(int, k, ARRAY_SIZE(sh_msiof_spi_clk_table) - 1); | |
164 | ||
165 | sh_msiof_write(p, TSCR, sh_msiof_spi_clk_table[k].scr); | |
166 | sh_msiof_write(p, RSCR, sh_msiof_spi_clk_table[k].scr); | |
167 | } | |
168 | ||
169 | static void sh_msiof_spi_set_pin_regs(struct sh_msiof_spi_priv *p, | |
e2dbf5eb GL |
170 | u32 cpol, u32 cpha, |
171 | u32 tx_hi_z, u32 lsb_first) | |
8051effc | 172 | { |
e2dbf5eb | 173 | u32 tmp; |
8051effc MD |
174 | int edge; |
175 | ||
176 | /* | |
e8708ef7 MP |
177 | * CPOL CPHA TSCKIZ RSCKIZ TEDG REDG |
178 | * 0 0 10 10 1 1 | |
179 | * 0 1 10 10 0 0 | |
180 | * 1 0 11 11 0 0 | |
181 | * 1 1 11 11 1 1 | |
8051effc | 182 | */ |
8051effc MD |
183 | sh_msiof_write(p, FCTR, 0); |
184 | sh_msiof_write(p, TMDR1, 0xe2000005 | (lsb_first << 24)); | |
185 | sh_msiof_write(p, RMDR1, 0x22000005 | (lsb_first << 24)); | |
186 | ||
187 | tmp = 0xa0000000; | |
188 | tmp |= cpol << 30; /* TSCKIZ */ | |
189 | tmp |= cpol << 28; /* RSCKIZ */ | |
190 | ||
e2dbf5eb | 191 | edge = cpol ^ !cpha; |
8051effc MD |
192 | |
193 | tmp |= edge << 27; /* TEDG */ | |
e8708ef7 | 194 | tmp |= edge << 26; /* REDG */ |
8051effc MD |
195 | tmp |= (tx_hi_z ? 2 : 0) << 22; /* TXDIZ */ |
196 | sh_msiof_write(p, CTR, tmp); | |
197 | } | |
198 | ||
199 | static void sh_msiof_spi_set_mode_regs(struct sh_msiof_spi_priv *p, | |
200 | const void *tx_buf, void *rx_buf, | |
e2dbf5eb | 201 | u32 bits, u32 words) |
8051effc | 202 | { |
e2dbf5eb | 203 | u32 dr2 = ((bits - 1) << 24) | ((words - 1) << 16); |
8051effc MD |
204 | |
205 | if (tx_buf) | |
206 | sh_msiof_write(p, TMDR2, dr2); | |
207 | else | |
208 | sh_msiof_write(p, TMDR2, dr2 | 1); | |
209 | ||
210 | if (rx_buf) | |
211 | sh_msiof_write(p, RMDR2, dr2); | |
212 | ||
213 | sh_msiof_write(p, IER, STR_TEOF | STR_REOF); | |
214 | } | |
215 | ||
216 | static void sh_msiof_reset_str(struct sh_msiof_spi_priv *p) | |
217 | { | |
218 | sh_msiof_write(p, STR, sh_msiof_read(p, STR)); | |
219 | } | |
220 | ||
221 | static void sh_msiof_spi_write_fifo_8(struct sh_msiof_spi_priv *p, | |
222 | const void *tx_buf, int words, int fs) | |
223 | { | |
e2dbf5eb | 224 | const u8 *buf_8 = tx_buf; |
8051effc MD |
225 | int k; |
226 | ||
227 | for (k = 0; k < words; k++) | |
228 | sh_msiof_write(p, TFDR, buf_8[k] << fs); | |
229 | } | |
230 | ||
231 | static void sh_msiof_spi_write_fifo_16(struct sh_msiof_spi_priv *p, | |
232 | const void *tx_buf, int words, int fs) | |
233 | { | |
e2dbf5eb | 234 | const u16 *buf_16 = tx_buf; |
8051effc MD |
235 | int k; |
236 | ||
237 | for (k = 0; k < words; k++) | |
238 | sh_msiof_write(p, TFDR, buf_16[k] << fs); | |
239 | } | |
240 | ||
241 | static void sh_msiof_spi_write_fifo_16u(struct sh_msiof_spi_priv *p, | |
242 | const void *tx_buf, int words, int fs) | |
243 | { | |
e2dbf5eb | 244 | const u16 *buf_16 = tx_buf; |
8051effc MD |
245 | int k; |
246 | ||
247 | for (k = 0; k < words; k++) | |
248 | sh_msiof_write(p, TFDR, get_unaligned(&buf_16[k]) << fs); | |
249 | } | |
250 | ||
251 | static void sh_msiof_spi_write_fifo_32(struct sh_msiof_spi_priv *p, | |
252 | const void *tx_buf, int words, int fs) | |
253 | { | |
e2dbf5eb | 254 | const u32 *buf_32 = tx_buf; |
8051effc MD |
255 | int k; |
256 | ||
257 | for (k = 0; k < words; k++) | |
258 | sh_msiof_write(p, TFDR, buf_32[k] << fs); | |
259 | } | |
260 | ||
261 | static void sh_msiof_spi_write_fifo_32u(struct sh_msiof_spi_priv *p, | |
262 | const void *tx_buf, int words, int fs) | |
263 | { | |
e2dbf5eb | 264 | const u32 *buf_32 = tx_buf; |
8051effc MD |
265 | int k; |
266 | ||
267 | for (k = 0; k < words; k++) | |
268 | sh_msiof_write(p, TFDR, get_unaligned(&buf_32[k]) << fs); | |
269 | } | |
270 | ||
9dabb3f3 GL |
271 | static void sh_msiof_spi_write_fifo_s32(struct sh_msiof_spi_priv *p, |
272 | const void *tx_buf, int words, int fs) | |
273 | { | |
274 | const u32 *buf_32 = tx_buf; | |
275 | int k; | |
276 | ||
277 | for (k = 0; k < words; k++) | |
278 | sh_msiof_write(p, TFDR, swab32(buf_32[k] << fs)); | |
279 | } | |
280 | ||
281 | static void sh_msiof_spi_write_fifo_s32u(struct sh_msiof_spi_priv *p, | |
282 | const void *tx_buf, int words, int fs) | |
283 | { | |
284 | const u32 *buf_32 = tx_buf; | |
285 | int k; | |
286 | ||
287 | for (k = 0; k < words; k++) | |
288 | sh_msiof_write(p, TFDR, swab32(get_unaligned(&buf_32[k]) << fs)); | |
289 | } | |
290 | ||
8051effc MD |
291 | static void sh_msiof_spi_read_fifo_8(struct sh_msiof_spi_priv *p, |
292 | void *rx_buf, int words, int fs) | |
293 | { | |
e2dbf5eb | 294 | u8 *buf_8 = rx_buf; |
8051effc MD |
295 | int k; |
296 | ||
297 | for (k = 0; k < words; k++) | |
298 | buf_8[k] = sh_msiof_read(p, RFDR) >> fs; | |
299 | } | |
300 | ||
301 | static void sh_msiof_spi_read_fifo_16(struct sh_msiof_spi_priv *p, | |
302 | void *rx_buf, int words, int fs) | |
303 | { | |
e2dbf5eb | 304 | u16 *buf_16 = rx_buf; |
8051effc MD |
305 | int k; |
306 | ||
307 | for (k = 0; k < words; k++) | |
308 | buf_16[k] = sh_msiof_read(p, RFDR) >> fs; | |
309 | } | |
310 | ||
311 | static void sh_msiof_spi_read_fifo_16u(struct sh_msiof_spi_priv *p, | |
312 | void *rx_buf, int words, int fs) | |
313 | { | |
e2dbf5eb | 314 | u16 *buf_16 = rx_buf; |
8051effc MD |
315 | int k; |
316 | ||
317 | for (k = 0; k < words; k++) | |
318 | put_unaligned(sh_msiof_read(p, RFDR) >> fs, &buf_16[k]); | |
319 | } | |
320 | ||
321 | static void sh_msiof_spi_read_fifo_32(struct sh_msiof_spi_priv *p, | |
322 | void *rx_buf, int words, int fs) | |
323 | { | |
e2dbf5eb | 324 | u32 *buf_32 = rx_buf; |
8051effc MD |
325 | int k; |
326 | ||
327 | for (k = 0; k < words; k++) | |
328 | buf_32[k] = sh_msiof_read(p, RFDR) >> fs; | |
329 | } | |
330 | ||
331 | static void sh_msiof_spi_read_fifo_32u(struct sh_msiof_spi_priv *p, | |
332 | void *rx_buf, int words, int fs) | |
333 | { | |
e2dbf5eb | 334 | u32 *buf_32 = rx_buf; |
8051effc MD |
335 | int k; |
336 | ||
337 | for (k = 0; k < words; k++) | |
338 | put_unaligned(sh_msiof_read(p, RFDR) >> fs, &buf_32[k]); | |
339 | } | |
340 | ||
9dabb3f3 GL |
341 | static void sh_msiof_spi_read_fifo_s32(struct sh_msiof_spi_priv *p, |
342 | void *rx_buf, int words, int fs) | |
343 | { | |
344 | u32 *buf_32 = rx_buf; | |
345 | int k; | |
346 | ||
347 | for (k = 0; k < words; k++) | |
348 | buf_32[k] = swab32(sh_msiof_read(p, RFDR) >> fs); | |
349 | } | |
350 | ||
351 | static void sh_msiof_spi_read_fifo_s32u(struct sh_msiof_spi_priv *p, | |
352 | void *rx_buf, int words, int fs) | |
353 | { | |
354 | u32 *buf_32 = rx_buf; | |
355 | int k; | |
356 | ||
357 | for (k = 0; k < words; k++) | |
358 | put_unaligned(swab32(sh_msiof_read(p, RFDR) >> fs), &buf_32[k]); | |
359 | } | |
360 | ||
8051effc MD |
361 | static int sh_msiof_spi_bits(struct spi_device *spi, struct spi_transfer *t) |
362 | { | |
363 | int bits; | |
364 | ||
365 | bits = t ? t->bits_per_word : 0; | |
e2dbf5eb GL |
366 | if (!bits) |
367 | bits = spi->bits_per_word; | |
8051effc MD |
368 | return bits; |
369 | } | |
370 | ||
371 | static unsigned long sh_msiof_spi_hz(struct spi_device *spi, | |
372 | struct spi_transfer *t) | |
373 | { | |
374 | unsigned long hz; | |
375 | ||
376 | hz = t ? t->speed_hz : 0; | |
e2dbf5eb GL |
377 | if (!hz) |
378 | hz = spi->max_speed_hz; | |
8051effc MD |
379 | return hz; |
380 | } | |
381 | ||
382 | static int sh_msiof_spi_setup_transfer(struct spi_device *spi, | |
383 | struct spi_transfer *t) | |
384 | { | |
385 | int bits; | |
386 | ||
387 | /* noting to check hz values against since parent clock is disabled */ | |
388 | ||
389 | bits = sh_msiof_spi_bits(spi, t); | |
390 | if (bits < 8) | |
391 | return -EINVAL; | |
392 | if (bits > 32) | |
393 | return -EINVAL; | |
394 | ||
395 | return spi_bitbang_setup_transfer(spi, t); | |
396 | } | |
397 | ||
398 | static void sh_msiof_spi_chipselect(struct spi_device *spi, int is_on) | |
399 | { | |
400 | struct sh_msiof_spi_priv *p = spi_master_get_devdata(spi->master); | |
401 | int value; | |
402 | ||
403 | /* chip select is active low unless SPI_CS_HIGH is set */ | |
404 | if (spi->mode & SPI_CS_HIGH) | |
405 | value = (is_on == BITBANG_CS_ACTIVE) ? 1 : 0; | |
406 | else | |
407 | value = (is_on == BITBANG_CS_ACTIVE) ? 0 : 1; | |
408 | ||
409 | if (is_on == BITBANG_CS_ACTIVE) { | |
410 | if (!test_and_set_bit(0, &p->flags)) { | |
411 | pm_runtime_get_sync(&p->pdev->dev); | |
412 | clk_enable(p->clk); | |
413 | } | |
414 | ||
415 | /* Configure pins before asserting CS */ | |
416 | sh_msiof_spi_set_pin_regs(p, !!(spi->mode & SPI_CPOL), | |
417 | !!(spi->mode & SPI_CPHA), | |
418 | !!(spi->mode & SPI_3WIRE), | |
419 | !!(spi->mode & SPI_LSB_FIRST)); | |
420 | } | |
421 | ||
422 | /* use spi->controller data for CS (same strategy as spi_gpio) */ | |
423 | gpio_set_value((unsigned)spi->controller_data, value); | |
424 | ||
425 | if (is_on == BITBANG_CS_INACTIVE) { | |
426 | if (test_and_clear_bit(0, &p->flags)) { | |
427 | clk_disable(p->clk); | |
428 | pm_runtime_put(&p->pdev->dev); | |
429 | } | |
430 | } | |
431 | } | |
432 | ||
433 | static int sh_msiof_spi_txrx_once(struct sh_msiof_spi_priv *p, | |
434 | void (*tx_fifo)(struct sh_msiof_spi_priv *, | |
435 | const void *, int, int), | |
436 | void (*rx_fifo)(struct sh_msiof_spi_priv *, | |
437 | void *, int, int), | |
438 | const void *tx_buf, void *rx_buf, | |
439 | int words, int bits) | |
440 | { | |
441 | int fifo_shift; | |
442 | int ret; | |
443 | ||
444 | /* limit maximum word transfer to rx/tx fifo size */ | |
445 | if (tx_buf) | |
446 | words = min_t(int, words, p->tx_fifo_size); | |
447 | if (rx_buf) | |
448 | words = min_t(int, words, p->rx_fifo_size); | |
449 | ||
450 | /* the fifo contents need shifting */ | |
451 | fifo_shift = 32 - bits; | |
452 | ||
453 | /* setup msiof transfer mode registers */ | |
454 | sh_msiof_spi_set_mode_regs(p, tx_buf, rx_buf, bits, words); | |
455 | ||
456 | /* write tx fifo */ | |
457 | if (tx_buf) | |
458 | tx_fifo(p, tx_buf, words, fifo_shift); | |
459 | ||
460 | /* setup clock and rx/tx signals */ | |
461 | ret = sh_msiof_modify_ctr_wait(p, 0, CTR_TSCKE); | |
462 | if (rx_buf) | |
463 | ret = ret ? ret : sh_msiof_modify_ctr_wait(p, 0, CTR_RXE); | |
464 | ret = ret ? ret : sh_msiof_modify_ctr_wait(p, 0, CTR_TXE); | |
465 | ||
466 | /* start by setting frame bit */ | |
467 | INIT_COMPLETION(p->done); | |
468 | ret = ret ? ret : sh_msiof_modify_ctr_wait(p, 0, CTR_TFSE); | |
469 | if (ret) { | |
470 | dev_err(&p->pdev->dev, "failed to start hardware\n"); | |
471 | goto err; | |
472 | } | |
473 | ||
474 | /* wait for tx fifo to be emptied / rx fifo to be filled */ | |
475 | wait_for_completion(&p->done); | |
476 | ||
477 | /* read rx fifo */ | |
478 | if (rx_buf) | |
479 | rx_fifo(p, rx_buf, words, fifo_shift); | |
480 | ||
481 | /* clear status bits */ | |
482 | sh_msiof_reset_str(p); | |
483 | ||
484 | /* shut down frame, tx/tx and clock signals */ | |
485 | ret = sh_msiof_modify_ctr_wait(p, CTR_TFSE, 0); | |
486 | ret = ret ? ret : sh_msiof_modify_ctr_wait(p, CTR_TXE, 0); | |
487 | if (rx_buf) | |
488 | ret = ret ? ret : sh_msiof_modify_ctr_wait(p, CTR_RXE, 0); | |
489 | ret = ret ? ret : sh_msiof_modify_ctr_wait(p, CTR_TSCKE, 0); | |
490 | if (ret) { | |
491 | dev_err(&p->pdev->dev, "failed to shut down hardware\n"); | |
492 | goto err; | |
493 | } | |
494 | ||
495 | return words; | |
496 | ||
497 | err: | |
498 | sh_msiof_write(p, IER, 0); | |
499 | return ret; | |
500 | } | |
501 | ||
502 | static int sh_msiof_spi_txrx(struct spi_device *spi, struct spi_transfer *t) | |
503 | { | |
504 | struct sh_msiof_spi_priv *p = spi_master_get_devdata(spi->master); | |
505 | void (*tx_fifo)(struct sh_msiof_spi_priv *, const void *, int, int); | |
506 | void (*rx_fifo)(struct sh_msiof_spi_priv *, void *, int, int); | |
507 | int bits; | |
508 | int bytes_per_word; | |
509 | int bytes_done; | |
510 | int words; | |
511 | int n; | |
9dabb3f3 | 512 | bool swab; |
8051effc MD |
513 | |
514 | bits = sh_msiof_spi_bits(spi, t); | |
515 | ||
9dabb3f3 GL |
516 | if (bits <= 8 && t->len > 15 && !(t->len & 3)) { |
517 | bits = 32; | |
518 | swab = true; | |
519 | } else { | |
520 | swab = false; | |
521 | } | |
522 | ||
8051effc MD |
523 | /* setup bytes per word and fifo read/write functions */ |
524 | if (bits <= 8) { | |
525 | bytes_per_word = 1; | |
526 | tx_fifo = sh_msiof_spi_write_fifo_8; | |
527 | rx_fifo = sh_msiof_spi_read_fifo_8; | |
528 | } else if (bits <= 16) { | |
529 | bytes_per_word = 2; | |
530 | if ((unsigned long)t->tx_buf & 0x01) | |
531 | tx_fifo = sh_msiof_spi_write_fifo_16u; | |
532 | else | |
533 | tx_fifo = sh_msiof_spi_write_fifo_16; | |
534 | ||
535 | if ((unsigned long)t->rx_buf & 0x01) | |
536 | rx_fifo = sh_msiof_spi_read_fifo_16u; | |
537 | else | |
538 | rx_fifo = sh_msiof_spi_read_fifo_16; | |
9dabb3f3 GL |
539 | } else if (swab) { |
540 | bytes_per_word = 4; | |
541 | if ((unsigned long)t->tx_buf & 0x03) | |
542 | tx_fifo = sh_msiof_spi_write_fifo_s32u; | |
543 | else | |
544 | tx_fifo = sh_msiof_spi_write_fifo_s32; | |
545 | ||
546 | if ((unsigned long)t->rx_buf & 0x03) | |
547 | rx_fifo = sh_msiof_spi_read_fifo_s32u; | |
548 | else | |
549 | rx_fifo = sh_msiof_spi_read_fifo_s32; | |
8051effc MD |
550 | } else { |
551 | bytes_per_word = 4; | |
552 | if ((unsigned long)t->tx_buf & 0x03) | |
553 | tx_fifo = sh_msiof_spi_write_fifo_32u; | |
554 | else | |
555 | tx_fifo = sh_msiof_spi_write_fifo_32; | |
556 | ||
557 | if ((unsigned long)t->rx_buf & 0x03) | |
558 | rx_fifo = sh_msiof_spi_read_fifo_32u; | |
559 | else | |
560 | rx_fifo = sh_msiof_spi_read_fifo_32; | |
561 | } | |
562 | ||
563 | /* setup clocks (clock already enabled in chipselect()) */ | |
564 | sh_msiof_spi_set_clk_regs(p, clk_get_rate(p->clk), | |
565 | sh_msiof_spi_hz(spi, t)); | |
566 | ||
567 | /* transfer in fifo sized chunks */ | |
568 | words = t->len / bytes_per_word; | |
569 | bytes_done = 0; | |
570 | ||
571 | while (bytes_done < t->len) { | |
8a6afb9a GL |
572 | void *rx_buf = t->rx_buf ? t->rx_buf + bytes_done : NULL; |
573 | const void *tx_buf = t->tx_buf ? t->tx_buf + bytes_done : NULL; | |
8051effc | 574 | n = sh_msiof_spi_txrx_once(p, tx_fifo, rx_fifo, |
8a6afb9a GL |
575 | tx_buf, |
576 | rx_buf, | |
8051effc MD |
577 | words, bits); |
578 | if (n < 0) | |
579 | break; | |
580 | ||
581 | bytes_done += n * bytes_per_word; | |
582 | words -= n; | |
583 | } | |
584 | ||
585 | return bytes_done; | |
586 | } | |
587 | ||
588 | static u32 sh_msiof_spi_txrx_word(struct spi_device *spi, unsigned nsecs, | |
589 | u32 word, u8 bits) | |
590 | { | |
591 | BUG(); /* unused but needed by bitbang code */ | |
592 | return 0; | |
593 | } | |
594 | ||
595 | static int sh_msiof_spi_probe(struct platform_device *pdev) | |
596 | { | |
597 | struct resource *r; | |
598 | struct spi_master *master; | |
599 | struct sh_msiof_spi_priv *p; | |
600 | char clk_name[16]; | |
601 | int i; | |
602 | int ret; | |
603 | ||
604 | master = spi_alloc_master(&pdev->dev, sizeof(struct sh_msiof_spi_priv)); | |
605 | if (master == NULL) { | |
606 | dev_err(&pdev->dev, "failed to allocate spi master\n"); | |
607 | ret = -ENOMEM; | |
608 | goto err0; | |
609 | } | |
610 | ||
611 | p = spi_master_get_devdata(master); | |
612 | ||
613 | platform_set_drvdata(pdev, p); | |
614 | p->info = pdev->dev.platform_data; | |
615 | init_completion(&p->done); | |
616 | ||
617 | snprintf(clk_name, sizeof(clk_name), "msiof%d", pdev->id); | |
618 | p->clk = clk_get(&pdev->dev, clk_name); | |
619 | if (IS_ERR(p->clk)) { | |
620 | dev_err(&pdev->dev, "cannot get clock \"%s\"\n", clk_name); | |
621 | ret = PTR_ERR(p->clk); | |
622 | goto err1; | |
623 | } | |
624 | ||
625 | r = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
626 | i = platform_get_irq(pdev, 0); | |
627 | if (!r || i < 0) { | |
628 | dev_err(&pdev->dev, "cannot get platform resources\n"); | |
629 | ret = -ENOENT; | |
630 | goto err2; | |
631 | } | |
632 | p->mapbase = ioremap_nocache(r->start, resource_size(r)); | |
633 | if (!p->mapbase) { | |
634 | dev_err(&pdev->dev, "unable to ioremap\n"); | |
635 | ret = -ENXIO; | |
636 | goto err2; | |
637 | } | |
638 | ||
38ada214 | 639 | ret = request_irq(i, sh_msiof_spi_irq, 0, |
8051effc MD |
640 | dev_name(&pdev->dev), p); |
641 | if (ret) { | |
642 | dev_err(&pdev->dev, "unable to request irq\n"); | |
643 | goto err3; | |
644 | } | |
645 | ||
646 | p->pdev = pdev; | |
647 | pm_runtime_enable(&pdev->dev); | |
648 | ||
649 | /* The standard version of MSIOF use 64 word FIFOs */ | |
650 | p->tx_fifo_size = 64; | |
651 | p->rx_fifo_size = 64; | |
652 | ||
653 | /* Platform data may override FIFO sizes */ | |
654 | if (p->info->tx_fifo_override) | |
655 | p->tx_fifo_size = p->info->tx_fifo_override; | |
656 | if (p->info->rx_fifo_override) | |
657 | p->rx_fifo_size = p->info->rx_fifo_override; | |
658 | ||
659 | /* init master and bitbang code */ | |
660 | master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH; | |
661 | master->mode_bits |= SPI_LSB_FIRST | SPI_3WIRE; | |
662 | master->flags = 0; | |
663 | master->bus_num = pdev->id; | |
664 | master->num_chipselect = p->info->num_chipselect; | |
665 | master->setup = spi_bitbang_setup; | |
666 | master->cleanup = spi_bitbang_cleanup; | |
667 | ||
668 | p->bitbang.master = master; | |
669 | p->bitbang.chipselect = sh_msiof_spi_chipselect; | |
670 | p->bitbang.setup_transfer = sh_msiof_spi_setup_transfer; | |
671 | p->bitbang.txrx_bufs = sh_msiof_spi_txrx; | |
672 | p->bitbang.txrx_word[SPI_MODE_0] = sh_msiof_spi_txrx_word; | |
673 | p->bitbang.txrx_word[SPI_MODE_1] = sh_msiof_spi_txrx_word; | |
674 | p->bitbang.txrx_word[SPI_MODE_2] = sh_msiof_spi_txrx_word; | |
675 | p->bitbang.txrx_word[SPI_MODE_3] = sh_msiof_spi_txrx_word; | |
676 | ||
677 | ret = spi_bitbang_start(&p->bitbang); | |
678 | if (ret == 0) | |
679 | return 0; | |
680 | ||
681 | pm_runtime_disable(&pdev->dev); | |
682 | err3: | |
683 | iounmap(p->mapbase); | |
684 | err2: | |
685 | clk_put(p->clk); | |
686 | err1: | |
687 | spi_master_put(master); | |
688 | err0: | |
689 | return ret; | |
690 | } | |
691 | ||
692 | static int sh_msiof_spi_remove(struct platform_device *pdev) | |
693 | { | |
694 | struct sh_msiof_spi_priv *p = platform_get_drvdata(pdev); | |
695 | int ret; | |
696 | ||
697 | ret = spi_bitbang_stop(&p->bitbang); | |
698 | if (!ret) { | |
699 | pm_runtime_disable(&pdev->dev); | |
d95defac | 700 | free_irq(platform_get_irq(pdev, 0), p); |
8051effc MD |
701 | iounmap(p->mapbase); |
702 | clk_put(p->clk); | |
703 | spi_master_put(p->bitbang.master); | |
704 | } | |
705 | return ret; | |
706 | } | |
707 | ||
708 | static int sh_msiof_spi_runtime_nop(struct device *dev) | |
709 | { | |
710 | /* Runtime PM callback shared between ->runtime_suspend() | |
711 | * and ->runtime_resume(). Simply returns success. | |
712 | * | |
713 | * This driver re-initializes all registers after | |
714 | * pm_runtime_get_sync() anyway so there is no need | |
715 | * to save and restore registers here. | |
716 | */ | |
717 | return 0; | |
718 | } | |
719 | ||
720 | static struct dev_pm_ops sh_msiof_spi_dev_pm_ops = { | |
721 | .runtime_suspend = sh_msiof_spi_runtime_nop, | |
722 | .runtime_resume = sh_msiof_spi_runtime_nop, | |
723 | }; | |
724 | ||
725 | static struct platform_driver sh_msiof_spi_drv = { | |
726 | .probe = sh_msiof_spi_probe, | |
727 | .remove = sh_msiof_spi_remove, | |
728 | .driver = { | |
729 | .name = "spi_sh_msiof", | |
730 | .owner = THIS_MODULE, | |
731 | .pm = &sh_msiof_spi_dev_pm_ops, | |
732 | }, | |
733 | }; | |
940ab889 | 734 | module_platform_driver(sh_msiof_spi_drv); |
8051effc MD |
735 | |
736 | MODULE_DESCRIPTION("SuperH MSIOF SPI Master Interface Driver"); | |
737 | MODULE_AUTHOR("Magnus Damm"); | |
738 | MODULE_LICENSE("GPL v2"); | |
739 | MODULE_ALIAS("platform:spi_sh_msiof"); |