Commit | Line | Data |
---|---|---|
8051effc MD |
1 | /* |
2 | * SuperH MSIOF SPI Master Interface | |
3 | * | |
4 | * Copyright (c) 2009 Magnus Damm | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License version 2 as | |
8 | * published by the Free Software Foundation. | |
9 | * | |
10 | */ | |
11 | ||
e2dbf5eb GL |
12 | #include <linux/bitmap.h> |
13 | #include <linux/clk.h> | |
14 | #include <linux/completion.h> | |
8051effc | 15 | #include <linux/delay.h> |
e2dbf5eb GL |
16 | #include <linux/err.h> |
17 | #include <linux/gpio.h> | |
18 | #include <linux/init.h> | |
8051effc | 19 | #include <linux/interrupt.h> |
e2dbf5eb GL |
20 | #include <linux/io.h> |
21 | #include <linux/kernel.h> | |
d7614de4 | 22 | #include <linux/module.h> |
cf9c86ef | 23 | #include <linux/of.h> |
8051effc | 24 | #include <linux/platform_device.h> |
8051effc | 25 | #include <linux/pm_runtime.h> |
8051effc | 26 | |
e2dbf5eb | 27 | #include <linux/spi/sh_msiof.h> |
8051effc MD |
28 | #include <linux/spi/spi.h> |
29 | #include <linux/spi/spi_bitbang.h> | |
8051effc | 30 | |
8051effc MD |
31 | #include <asm/unaligned.h> |
32 | ||
33 | struct sh_msiof_spi_priv { | |
34 | struct spi_bitbang bitbang; /* must be first for spi_bitbang.c */ | |
35 | void __iomem *mapbase; | |
36 | struct clk *clk; | |
37 | struct platform_device *pdev; | |
38 | struct sh_msiof_spi_info *info; | |
39 | struct completion done; | |
40 | unsigned long flags; | |
41 | int tx_fifo_size; | |
42 | int rx_fifo_size; | |
43 | }; | |
44 | ||
45 | #define TMDR1 0x00 | |
46 | #define TMDR2 0x04 | |
47 | #define TMDR3 0x08 | |
48 | #define RMDR1 0x10 | |
49 | #define RMDR2 0x14 | |
50 | #define RMDR3 0x18 | |
51 | #define TSCR 0x20 | |
52 | #define RSCR 0x22 | |
53 | #define CTR 0x28 | |
54 | #define FCTR 0x30 | |
55 | #define STR 0x40 | |
56 | #define IER 0x44 | |
57 | #define TDR1 0x48 | |
58 | #define TDR2 0x4c | |
59 | #define TFDR 0x50 | |
60 | #define RDR1 0x58 | |
61 | #define RDR2 0x5c | |
62 | #define RFDR 0x60 | |
63 | ||
64 | #define CTR_TSCKE (1 << 15) | |
65 | #define CTR_TFSE (1 << 14) | |
66 | #define CTR_TXE (1 << 9) | |
67 | #define CTR_RXE (1 << 8) | |
68 | ||
69 | #define STR_TEOF (1 << 23) | |
70 | #define STR_REOF (1 << 7) | |
71 | ||
e2dbf5eb | 72 | static u32 sh_msiof_read(struct sh_msiof_spi_priv *p, int reg_offs) |
8051effc MD |
73 | { |
74 | switch (reg_offs) { | |
75 | case TSCR: | |
76 | case RSCR: | |
77 | return ioread16(p->mapbase + reg_offs); | |
78 | default: | |
79 | return ioread32(p->mapbase + reg_offs); | |
80 | } | |
81 | } | |
82 | ||
83 | static void sh_msiof_write(struct sh_msiof_spi_priv *p, int reg_offs, | |
e2dbf5eb | 84 | u32 value) |
8051effc MD |
85 | { |
86 | switch (reg_offs) { | |
87 | case TSCR: | |
88 | case RSCR: | |
89 | iowrite16(value, p->mapbase + reg_offs); | |
90 | break; | |
91 | default: | |
92 | iowrite32(value, p->mapbase + reg_offs); | |
93 | break; | |
94 | } | |
95 | } | |
96 | ||
97 | static int sh_msiof_modify_ctr_wait(struct sh_msiof_spi_priv *p, | |
e2dbf5eb | 98 | u32 clr, u32 set) |
8051effc | 99 | { |
e2dbf5eb GL |
100 | u32 mask = clr | set; |
101 | u32 data; | |
8051effc MD |
102 | int k; |
103 | ||
104 | data = sh_msiof_read(p, CTR); | |
105 | data &= ~clr; | |
106 | data |= set; | |
107 | sh_msiof_write(p, CTR, data); | |
108 | ||
109 | for (k = 100; k > 0; k--) { | |
110 | if ((sh_msiof_read(p, CTR) & mask) == set) | |
111 | break; | |
112 | ||
113 | udelay(10); | |
114 | } | |
115 | ||
116 | return k > 0 ? 0 : -ETIMEDOUT; | |
117 | } | |
118 | ||
119 | static irqreturn_t sh_msiof_spi_irq(int irq, void *data) | |
120 | { | |
121 | struct sh_msiof_spi_priv *p = data; | |
122 | ||
123 | /* just disable the interrupt and wake up */ | |
124 | sh_msiof_write(p, IER, 0); | |
125 | complete(&p->done); | |
126 | ||
127 | return IRQ_HANDLED; | |
128 | } | |
129 | ||
130 | static struct { | |
131 | unsigned short div; | |
132 | unsigned short scr; | |
133 | } const sh_msiof_spi_clk_table[] = { | |
134 | { 1, 0x0007 }, | |
135 | { 2, 0x0000 }, | |
136 | { 4, 0x0001 }, | |
137 | { 8, 0x0002 }, | |
138 | { 16, 0x0003 }, | |
139 | { 32, 0x0004 }, | |
140 | { 64, 0x1f00 }, | |
141 | { 128, 0x1f01 }, | |
142 | { 256, 0x1f02 }, | |
143 | { 512, 0x1f03 }, | |
144 | { 1024, 0x1f04 }, | |
145 | }; | |
146 | ||
147 | static void sh_msiof_spi_set_clk_regs(struct sh_msiof_spi_priv *p, | |
148 | unsigned long parent_rate, | |
149 | unsigned long spi_hz) | |
150 | { | |
151 | unsigned long div = 1024; | |
152 | size_t k; | |
153 | ||
154 | if (!WARN_ON(!spi_hz || !parent_rate)) | |
155 | div = parent_rate / spi_hz; | |
156 | ||
157 | /* TODO: make more fine grained */ | |
158 | ||
159 | for (k = 0; k < ARRAY_SIZE(sh_msiof_spi_clk_table); k++) { | |
160 | if (sh_msiof_spi_clk_table[k].div >= div) | |
161 | break; | |
162 | } | |
163 | ||
164 | k = min_t(int, k, ARRAY_SIZE(sh_msiof_spi_clk_table) - 1); | |
165 | ||
166 | sh_msiof_write(p, TSCR, sh_msiof_spi_clk_table[k].scr); | |
167 | sh_msiof_write(p, RSCR, sh_msiof_spi_clk_table[k].scr); | |
168 | } | |
169 | ||
170 | static void sh_msiof_spi_set_pin_regs(struct sh_msiof_spi_priv *p, | |
e2dbf5eb GL |
171 | u32 cpol, u32 cpha, |
172 | u32 tx_hi_z, u32 lsb_first) | |
8051effc | 173 | { |
e2dbf5eb | 174 | u32 tmp; |
8051effc MD |
175 | int edge; |
176 | ||
177 | /* | |
e8708ef7 MP |
178 | * CPOL CPHA TSCKIZ RSCKIZ TEDG REDG |
179 | * 0 0 10 10 1 1 | |
180 | * 0 1 10 10 0 0 | |
181 | * 1 0 11 11 0 0 | |
182 | * 1 1 11 11 1 1 | |
8051effc | 183 | */ |
8051effc MD |
184 | sh_msiof_write(p, FCTR, 0); |
185 | sh_msiof_write(p, TMDR1, 0xe2000005 | (lsb_first << 24)); | |
186 | sh_msiof_write(p, RMDR1, 0x22000005 | (lsb_first << 24)); | |
187 | ||
188 | tmp = 0xa0000000; | |
189 | tmp |= cpol << 30; /* TSCKIZ */ | |
190 | tmp |= cpol << 28; /* RSCKIZ */ | |
191 | ||
e2dbf5eb | 192 | edge = cpol ^ !cpha; |
8051effc MD |
193 | |
194 | tmp |= edge << 27; /* TEDG */ | |
e8708ef7 | 195 | tmp |= edge << 26; /* REDG */ |
8051effc MD |
196 | tmp |= (tx_hi_z ? 2 : 0) << 22; /* TXDIZ */ |
197 | sh_msiof_write(p, CTR, tmp); | |
198 | } | |
199 | ||
200 | static void sh_msiof_spi_set_mode_regs(struct sh_msiof_spi_priv *p, | |
201 | const void *tx_buf, void *rx_buf, | |
e2dbf5eb | 202 | u32 bits, u32 words) |
8051effc | 203 | { |
e2dbf5eb | 204 | u32 dr2 = ((bits - 1) << 24) | ((words - 1) << 16); |
8051effc MD |
205 | |
206 | if (tx_buf) | |
207 | sh_msiof_write(p, TMDR2, dr2); | |
208 | else | |
209 | sh_msiof_write(p, TMDR2, dr2 | 1); | |
210 | ||
211 | if (rx_buf) | |
212 | sh_msiof_write(p, RMDR2, dr2); | |
213 | ||
214 | sh_msiof_write(p, IER, STR_TEOF | STR_REOF); | |
215 | } | |
216 | ||
217 | static void sh_msiof_reset_str(struct sh_msiof_spi_priv *p) | |
218 | { | |
219 | sh_msiof_write(p, STR, sh_msiof_read(p, STR)); | |
220 | } | |
221 | ||
222 | static void sh_msiof_spi_write_fifo_8(struct sh_msiof_spi_priv *p, | |
223 | const void *tx_buf, int words, int fs) | |
224 | { | |
e2dbf5eb | 225 | const u8 *buf_8 = tx_buf; |
8051effc MD |
226 | int k; |
227 | ||
228 | for (k = 0; k < words; k++) | |
229 | sh_msiof_write(p, TFDR, buf_8[k] << fs); | |
230 | } | |
231 | ||
232 | static void sh_msiof_spi_write_fifo_16(struct sh_msiof_spi_priv *p, | |
233 | const void *tx_buf, int words, int fs) | |
234 | { | |
e2dbf5eb | 235 | const u16 *buf_16 = tx_buf; |
8051effc MD |
236 | int k; |
237 | ||
238 | for (k = 0; k < words; k++) | |
239 | sh_msiof_write(p, TFDR, buf_16[k] << fs); | |
240 | } | |
241 | ||
242 | static void sh_msiof_spi_write_fifo_16u(struct sh_msiof_spi_priv *p, | |
243 | const void *tx_buf, int words, int fs) | |
244 | { | |
e2dbf5eb | 245 | const u16 *buf_16 = tx_buf; |
8051effc MD |
246 | int k; |
247 | ||
248 | for (k = 0; k < words; k++) | |
249 | sh_msiof_write(p, TFDR, get_unaligned(&buf_16[k]) << fs); | |
250 | } | |
251 | ||
252 | static void sh_msiof_spi_write_fifo_32(struct sh_msiof_spi_priv *p, | |
253 | const void *tx_buf, int words, int fs) | |
254 | { | |
e2dbf5eb | 255 | const u32 *buf_32 = tx_buf; |
8051effc MD |
256 | int k; |
257 | ||
258 | for (k = 0; k < words; k++) | |
259 | sh_msiof_write(p, TFDR, buf_32[k] << fs); | |
260 | } | |
261 | ||
262 | static void sh_msiof_spi_write_fifo_32u(struct sh_msiof_spi_priv *p, | |
263 | const void *tx_buf, int words, int fs) | |
264 | { | |
e2dbf5eb | 265 | const u32 *buf_32 = tx_buf; |
8051effc MD |
266 | int k; |
267 | ||
268 | for (k = 0; k < words; k++) | |
269 | sh_msiof_write(p, TFDR, get_unaligned(&buf_32[k]) << fs); | |
270 | } | |
271 | ||
9dabb3f3 GL |
272 | static void sh_msiof_spi_write_fifo_s32(struct sh_msiof_spi_priv *p, |
273 | const void *tx_buf, int words, int fs) | |
274 | { | |
275 | const u32 *buf_32 = tx_buf; | |
276 | int k; | |
277 | ||
278 | for (k = 0; k < words; k++) | |
279 | sh_msiof_write(p, TFDR, swab32(buf_32[k] << fs)); | |
280 | } | |
281 | ||
282 | static void sh_msiof_spi_write_fifo_s32u(struct sh_msiof_spi_priv *p, | |
283 | const void *tx_buf, int words, int fs) | |
284 | { | |
285 | const u32 *buf_32 = tx_buf; | |
286 | int k; | |
287 | ||
288 | for (k = 0; k < words; k++) | |
289 | sh_msiof_write(p, TFDR, swab32(get_unaligned(&buf_32[k]) << fs)); | |
290 | } | |
291 | ||
8051effc MD |
292 | static void sh_msiof_spi_read_fifo_8(struct sh_msiof_spi_priv *p, |
293 | void *rx_buf, int words, int fs) | |
294 | { | |
e2dbf5eb | 295 | u8 *buf_8 = rx_buf; |
8051effc MD |
296 | int k; |
297 | ||
298 | for (k = 0; k < words; k++) | |
299 | buf_8[k] = sh_msiof_read(p, RFDR) >> fs; | |
300 | } | |
301 | ||
302 | static void sh_msiof_spi_read_fifo_16(struct sh_msiof_spi_priv *p, | |
303 | void *rx_buf, int words, int fs) | |
304 | { | |
e2dbf5eb | 305 | u16 *buf_16 = rx_buf; |
8051effc MD |
306 | int k; |
307 | ||
308 | for (k = 0; k < words; k++) | |
309 | buf_16[k] = sh_msiof_read(p, RFDR) >> fs; | |
310 | } | |
311 | ||
312 | static void sh_msiof_spi_read_fifo_16u(struct sh_msiof_spi_priv *p, | |
313 | void *rx_buf, int words, int fs) | |
314 | { | |
e2dbf5eb | 315 | u16 *buf_16 = rx_buf; |
8051effc MD |
316 | int k; |
317 | ||
318 | for (k = 0; k < words; k++) | |
319 | put_unaligned(sh_msiof_read(p, RFDR) >> fs, &buf_16[k]); | |
320 | } | |
321 | ||
322 | static void sh_msiof_spi_read_fifo_32(struct sh_msiof_spi_priv *p, | |
323 | void *rx_buf, int words, int fs) | |
324 | { | |
e2dbf5eb | 325 | u32 *buf_32 = rx_buf; |
8051effc MD |
326 | int k; |
327 | ||
328 | for (k = 0; k < words; k++) | |
329 | buf_32[k] = sh_msiof_read(p, RFDR) >> fs; | |
330 | } | |
331 | ||
332 | static void sh_msiof_spi_read_fifo_32u(struct sh_msiof_spi_priv *p, | |
333 | void *rx_buf, int words, int fs) | |
334 | { | |
e2dbf5eb | 335 | u32 *buf_32 = rx_buf; |
8051effc MD |
336 | int k; |
337 | ||
338 | for (k = 0; k < words; k++) | |
339 | put_unaligned(sh_msiof_read(p, RFDR) >> fs, &buf_32[k]); | |
340 | } | |
341 | ||
9dabb3f3 GL |
342 | static void sh_msiof_spi_read_fifo_s32(struct sh_msiof_spi_priv *p, |
343 | void *rx_buf, int words, int fs) | |
344 | { | |
345 | u32 *buf_32 = rx_buf; | |
346 | int k; | |
347 | ||
348 | for (k = 0; k < words; k++) | |
349 | buf_32[k] = swab32(sh_msiof_read(p, RFDR) >> fs); | |
350 | } | |
351 | ||
352 | static void sh_msiof_spi_read_fifo_s32u(struct sh_msiof_spi_priv *p, | |
353 | void *rx_buf, int words, int fs) | |
354 | { | |
355 | u32 *buf_32 = rx_buf; | |
356 | int k; | |
357 | ||
358 | for (k = 0; k < words; k++) | |
359 | put_unaligned(swab32(sh_msiof_read(p, RFDR) >> fs), &buf_32[k]); | |
360 | } | |
361 | ||
8051effc MD |
362 | static int sh_msiof_spi_bits(struct spi_device *spi, struct spi_transfer *t) |
363 | { | |
364 | int bits; | |
365 | ||
366 | bits = t ? t->bits_per_word : 0; | |
e2dbf5eb GL |
367 | if (!bits) |
368 | bits = spi->bits_per_word; | |
8051effc MD |
369 | return bits; |
370 | } | |
371 | ||
372 | static unsigned long sh_msiof_spi_hz(struct spi_device *spi, | |
373 | struct spi_transfer *t) | |
374 | { | |
375 | unsigned long hz; | |
376 | ||
377 | hz = t ? t->speed_hz : 0; | |
e2dbf5eb GL |
378 | if (!hz) |
379 | hz = spi->max_speed_hz; | |
8051effc MD |
380 | return hz; |
381 | } | |
382 | ||
383 | static int sh_msiof_spi_setup_transfer(struct spi_device *spi, | |
384 | struct spi_transfer *t) | |
385 | { | |
386 | int bits; | |
387 | ||
388 | /* noting to check hz values against since parent clock is disabled */ | |
389 | ||
390 | bits = sh_msiof_spi_bits(spi, t); | |
391 | if (bits < 8) | |
392 | return -EINVAL; | |
393 | if (bits > 32) | |
394 | return -EINVAL; | |
395 | ||
396 | return spi_bitbang_setup_transfer(spi, t); | |
397 | } | |
398 | ||
399 | static void sh_msiof_spi_chipselect(struct spi_device *spi, int is_on) | |
400 | { | |
401 | struct sh_msiof_spi_priv *p = spi_master_get_devdata(spi->master); | |
402 | int value; | |
403 | ||
404 | /* chip select is active low unless SPI_CS_HIGH is set */ | |
405 | if (spi->mode & SPI_CS_HIGH) | |
406 | value = (is_on == BITBANG_CS_ACTIVE) ? 1 : 0; | |
407 | else | |
408 | value = (is_on == BITBANG_CS_ACTIVE) ? 0 : 1; | |
409 | ||
410 | if (is_on == BITBANG_CS_ACTIVE) { | |
411 | if (!test_and_set_bit(0, &p->flags)) { | |
412 | pm_runtime_get_sync(&p->pdev->dev); | |
413 | clk_enable(p->clk); | |
414 | } | |
415 | ||
416 | /* Configure pins before asserting CS */ | |
417 | sh_msiof_spi_set_pin_regs(p, !!(spi->mode & SPI_CPOL), | |
418 | !!(spi->mode & SPI_CPHA), | |
419 | !!(spi->mode & SPI_3WIRE), | |
420 | !!(spi->mode & SPI_LSB_FIRST)); | |
421 | } | |
422 | ||
423 | /* use spi->controller data for CS (same strategy as spi_gpio) */ | |
424 | gpio_set_value((unsigned)spi->controller_data, value); | |
425 | ||
426 | if (is_on == BITBANG_CS_INACTIVE) { | |
427 | if (test_and_clear_bit(0, &p->flags)) { | |
428 | clk_disable(p->clk); | |
429 | pm_runtime_put(&p->pdev->dev); | |
430 | } | |
431 | } | |
432 | } | |
433 | ||
434 | static int sh_msiof_spi_txrx_once(struct sh_msiof_spi_priv *p, | |
435 | void (*tx_fifo)(struct sh_msiof_spi_priv *, | |
436 | const void *, int, int), | |
437 | void (*rx_fifo)(struct sh_msiof_spi_priv *, | |
438 | void *, int, int), | |
439 | const void *tx_buf, void *rx_buf, | |
440 | int words, int bits) | |
441 | { | |
442 | int fifo_shift; | |
443 | int ret; | |
444 | ||
445 | /* limit maximum word transfer to rx/tx fifo size */ | |
446 | if (tx_buf) | |
447 | words = min_t(int, words, p->tx_fifo_size); | |
448 | if (rx_buf) | |
449 | words = min_t(int, words, p->rx_fifo_size); | |
450 | ||
451 | /* the fifo contents need shifting */ | |
452 | fifo_shift = 32 - bits; | |
453 | ||
454 | /* setup msiof transfer mode registers */ | |
455 | sh_msiof_spi_set_mode_regs(p, tx_buf, rx_buf, bits, words); | |
456 | ||
457 | /* write tx fifo */ | |
458 | if (tx_buf) | |
459 | tx_fifo(p, tx_buf, words, fifo_shift); | |
460 | ||
461 | /* setup clock and rx/tx signals */ | |
462 | ret = sh_msiof_modify_ctr_wait(p, 0, CTR_TSCKE); | |
463 | if (rx_buf) | |
464 | ret = ret ? ret : sh_msiof_modify_ctr_wait(p, 0, CTR_RXE); | |
465 | ret = ret ? ret : sh_msiof_modify_ctr_wait(p, 0, CTR_TXE); | |
466 | ||
467 | /* start by setting frame bit */ | |
468 | INIT_COMPLETION(p->done); | |
469 | ret = ret ? ret : sh_msiof_modify_ctr_wait(p, 0, CTR_TFSE); | |
470 | if (ret) { | |
471 | dev_err(&p->pdev->dev, "failed to start hardware\n"); | |
472 | goto err; | |
473 | } | |
474 | ||
475 | /* wait for tx fifo to be emptied / rx fifo to be filled */ | |
476 | wait_for_completion(&p->done); | |
477 | ||
478 | /* read rx fifo */ | |
479 | if (rx_buf) | |
480 | rx_fifo(p, rx_buf, words, fifo_shift); | |
481 | ||
482 | /* clear status bits */ | |
483 | sh_msiof_reset_str(p); | |
484 | ||
485 | /* shut down frame, tx/tx and clock signals */ | |
486 | ret = sh_msiof_modify_ctr_wait(p, CTR_TFSE, 0); | |
487 | ret = ret ? ret : sh_msiof_modify_ctr_wait(p, CTR_TXE, 0); | |
488 | if (rx_buf) | |
489 | ret = ret ? ret : sh_msiof_modify_ctr_wait(p, CTR_RXE, 0); | |
490 | ret = ret ? ret : sh_msiof_modify_ctr_wait(p, CTR_TSCKE, 0); | |
491 | if (ret) { | |
492 | dev_err(&p->pdev->dev, "failed to shut down hardware\n"); | |
493 | goto err; | |
494 | } | |
495 | ||
496 | return words; | |
497 | ||
498 | err: | |
499 | sh_msiof_write(p, IER, 0); | |
500 | return ret; | |
501 | } | |
502 | ||
503 | static int sh_msiof_spi_txrx(struct spi_device *spi, struct spi_transfer *t) | |
504 | { | |
505 | struct sh_msiof_spi_priv *p = spi_master_get_devdata(spi->master); | |
506 | void (*tx_fifo)(struct sh_msiof_spi_priv *, const void *, int, int); | |
507 | void (*rx_fifo)(struct sh_msiof_spi_priv *, void *, int, int); | |
508 | int bits; | |
509 | int bytes_per_word; | |
510 | int bytes_done; | |
511 | int words; | |
512 | int n; | |
9dabb3f3 | 513 | bool swab; |
8051effc MD |
514 | |
515 | bits = sh_msiof_spi_bits(spi, t); | |
516 | ||
9dabb3f3 GL |
517 | if (bits <= 8 && t->len > 15 && !(t->len & 3)) { |
518 | bits = 32; | |
519 | swab = true; | |
520 | } else { | |
521 | swab = false; | |
522 | } | |
523 | ||
8051effc MD |
524 | /* setup bytes per word and fifo read/write functions */ |
525 | if (bits <= 8) { | |
526 | bytes_per_word = 1; | |
527 | tx_fifo = sh_msiof_spi_write_fifo_8; | |
528 | rx_fifo = sh_msiof_spi_read_fifo_8; | |
529 | } else if (bits <= 16) { | |
530 | bytes_per_word = 2; | |
531 | if ((unsigned long)t->tx_buf & 0x01) | |
532 | tx_fifo = sh_msiof_spi_write_fifo_16u; | |
533 | else | |
534 | tx_fifo = sh_msiof_spi_write_fifo_16; | |
535 | ||
536 | if ((unsigned long)t->rx_buf & 0x01) | |
537 | rx_fifo = sh_msiof_spi_read_fifo_16u; | |
538 | else | |
539 | rx_fifo = sh_msiof_spi_read_fifo_16; | |
9dabb3f3 GL |
540 | } else if (swab) { |
541 | bytes_per_word = 4; | |
542 | if ((unsigned long)t->tx_buf & 0x03) | |
543 | tx_fifo = sh_msiof_spi_write_fifo_s32u; | |
544 | else | |
545 | tx_fifo = sh_msiof_spi_write_fifo_s32; | |
546 | ||
547 | if ((unsigned long)t->rx_buf & 0x03) | |
548 | rx_fifo = sh_msiof_spi_read_fifo_s32u; | |
549 | else | |
550 | rx_fifo = sh_msiof_spi_read_fifo_s32; | |
8051effc MD |
551 | } else { |
552 | bytes_per_word = 4; | |
553 | if ((unsigned long)t->tx_buf & 0x03) | |
554 | tx_fifo = sh_msiof_spi_write_fifo_32u; | |
555 | else | |
556 | tx_fifo = sh_msiof_spi_write_fifo_32; | |
557 | ||
558 | if ((unsigned long)t->rx_buf & 0x03) | |
559 | rx_fifo = sh_msiof_spi_read_fifo_32u; | |
560 | else | |
561 | rx_fifo = sh_msiof_spi_read_fifo_32; | |
562 | } | |
563 | ||
564 | /* setup clocks (clock already enabled in chipselect()) */ | |
565 | sh_msiof_spi_set_clk_regs(p, clk_get_rate(p->clk), | |
566 | sh_msiof_spi_hz(spi, t)); | |
567 | ||
568 | /* transfer in fifo sized chunks */ | |
569 | words = t->len / bytes_per_word; | |
570 | bytes_done = 0; | |
571 | ||
572 | while (bytes_done < t->len) { | |
8a6afb9a GL |
573 | void *rx_buf = t->rx_buf ? t->rx_buf + bytes_done : NULL; |
574 | const void *tx_buf = t->tx_buf ? t->tx_buf + bytes_done : NULL; | |
8051effc | 575 | n = sh_msiof_spi_txrx_once(p, tx_fifo, rx_fifo, |
8a6afb9a GL |
576 | tx_buf, |
577 | rx_buf, | |
8051effc MD |
578 | words, bits); |
579 | if (n < 0) | |
580 | break; | |
581 | ||
582 | bytes_done += n * bytes_per_word; | |
583 | words -= n; | |
584 | } | |
585 | ||
586 | return bytes_done; | |
587 | } | |
588 | ||
589 | static u32 sh_msiof_spi_txrx_word(struct spi_device *spi, unsigned nsecs, | |
590 | u32 word, u8 bits) | |
591 | { | |
592 | BUG(); /* unused but needed by bitbang code */ | |
593 | return 0; | |
594 | } | |
595 | ||
cf9c86ef BH |
596 | #ifdef CONFIG_OF |
597 | static struct sh_msiof_spi_info *sh_msiof_spi_parse_dt(struct device *dev) | |
598 | { | |
599 | struct sh_msiof_spi_info *info; | |
600 | struct device_node *np = dev->of_node; | |
601 | u32 num_cs = 0; | |
602 | ||
603 | info = devm_kzalloc(dev, sizeof(struct sh_msiof_spi_info), GFP_KERNEL); | |
604 | if (!info) { | |
605 | dev_err(dev, "failed to allocate setup data\n"); | |
606 | return NULL; | |
607 | } | |
608 | ||
609 | /* Parse the MSIOF properties */ | |
610 | of_property_read_u32(np, "num-cs", &num_cs); | |
611 | of_property_read_u32(np, "renesas,tx-fifo-size", | |
612 | &info->tx_fifo_override); | |
613 | of_property_read_u32(np, "renesas,rx-fifo-size", | |
614 | &info->rx_fifo_override); | |
615 | ||
616 | info->num_chipselect = num_cs; | |
617 | ||
618 | return info; | |
619 | } | |
620 | #else | |
621 | static struct sh_msiof_spi_info *sh_msiof_spi_parse_dt(struct device *dev) | |
622 | { | |
623 | return NULL; | |
624 | } | |
625 | #endif | |
626 | ||
8051effc MD |
627 | static int sh_msiof_spi_probe(struct platform_device *pdev) |
628 | { | |
629 | struct resource *r; | |
630 | struct spi_master *master; | |
631 | struct sh_msiof_spi_priv *p; | |
8051effc MD |
632 | int i; |
633 | int ret; | |
634 | ||
635 | master = spi_alloc_master(&pdev->dev, sizeof(struct sh_msiof_spi_priv)); | |
636 | if (master == NULL) { | |
637 | dev_err(&pdev->dev, "failed to allocate spi master\n"); | |
638 | ret = -ENOMEM; | |
639 | goto err0; | |
640 | } | |
641 | ||
642 | p = spi_master_get_devdata(master); | |
643 | ||
644 | platform_set_drvdata(pdev, p); | |
cf9c86ef BH |
645 | if (pdev->dev.of_node) |
646 | p->info = sh_msiof_spi_parse_dt(&pdev->dev); | |
647 | else | |
648 | p->info = pdev->dev.platform_data; | |
649 | ||
650 | if (!p->info) { | |
651 | dev_err(&pdev->dev, "failed to obtain device info\n"); | |
652 | ret = -ENXIO; | |
653 | goto err1; | |
654 | } | |
655 | ||
8051effc MD |
656 | init_completion(&p->done); |
657 | ||
078b6ead | 658 | p->clk = clk_get(&pdev->dev, NULL); |
8051effc | 659 | if (IS_ERR(p->clk)) { |
078b6ead | 660 | dev_err(&pdev->dev, "cannot get clock\n"); |
8051effc MD |
661 | ret = PTR_ERR(p->clk); |
662 | goto err1; | |
663 | } | |
664 | ||
665 | r = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
666 | i = platform_get_irq(pdev, 0); | |
667 | if (!r || i < 0) { | |
668 | dev_err(&pdev->dev, "cannot get platform resources\n"); | |
669 | ret = -ENOENT; | |
670 | goto err2; | |
671 | } | |
672 | p->mapbase = ioremap_nocache(r->start, resource_size(r)); | |
673 | if (!p->mapbase) { | |
674 | dev_err(&pdev->dev, "unable to ioremap\n"); | |
675 | ret = -ENXIO; | |
676 | goto err2; | |
677 | } | |
678 | ||
38ada214 | 679 | ret = request_irq(i, sh_msiof_spi_irq, 0, |
8051effc MD |
680 | dev_name(&pdev->dev), p); |
681 | if (ret) { | |
682 | dev_err(&pdev->dev, "unable to request irq\n"); | |
683 | goto err3; | |
684 | } | |
685 | ||
686 | p->pdev = pdev; | |
687 | pm_runtime_enable(&pdev->dev); | |
688 | ||
689 | /* The standard version of MSIOF use 64 word FIFOs */ | |
690 | p->tx_fifo_size = 64; | |
691 | p->rx_fifo_size = 64; | |
692 | ||
693 | /* Platform data may override FIFO sizes */ | |
694 | if (p->info->tx_fifo_override) | |
695 | p->tx_fifo_size = p->info->tx_fifo_override; | |
696 | if (p->info->rx_fifo_override) | |
697 | p->rx_fifo_size = p->info->rx_fifo_override; | |
698 | ||
699 | /* init master and bitbang code */ | |
700 | master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH; | |
701 | master->mode_bits |= SPI_LSB_FIRST | SPI_3WIRE; | |
702 | master->flags = 0; | |
703 | master->bus_num = pdev->id; | |
704 | master->num_chipselect = p->info->num_chipselect; | |
705 | master->setup = spi_bitbang_setup; | |
706 | master->cleanup = spi_bitbang_cleanup; | |
707 | ||
708 | p->bitbang.master = master; | |
709 | p->bitbang.chipselect = sh_msiof_spi_chipselect; | |
710 | p->bitbang.setup_transfer = sh_msiof_spi_setup_transfer; | |
711 | p->bitbang.txrx_bufs = sh_msiof_spi_txrx; | |
712 | p->bitbang.txrx_word[SPI_MODE_0] = sh_msiof_spi_txrx_word; | |
713 | p->bitbang.txrx_word[SPI_MODE_1] = sh_msiof_spi_txrx_word; | |
714 | p->bitbang.txrx_word[SPI_MODE_2] = sh_msiof_spi_txrx_word; | |
715 | p->bitbang.txrx_word[SPI_MODE_3] = sh_msiof_spi_txrx_word; | |
716 | ||
717 | ret = spi_bitbang_start(&p->bitbang); | |
718 | if (ret == 0) | |
719 | return 0; | |
720 | ||
721 | pm_runtime_disable(&pdev->dev); | |
722 | err3: | |
723 | iounmap(p->mapbase); | |
724 | err2: | |
725 | clk_put(p->clk); | |
726 | err1: | |
727 | spi_master_put(master); | |
728 | err0: | |
729 | return ret; | |
730 | } | |
731 | ||
732 | static int sh_msiof_spi_remove(struct platform_device *pdev) | |
733 | { | |
734 | struct sh_msiof_spi_priv *p = platform_get_drvdata(pdev); | |
735 | int ret; | |
736 | ||
737 | ret = spi_bitbang_stop(&p->bitbang); | |
738 | if (!ret) { | |
739 | pm_runtime_disable(&pdev->dev); | |
d95defac | 740 | free_irq(platform_get_irq(pdev, 0), p); |
8051effc MD |
741 | iounmap(p->mapbase); |
742 | clk_put(p->clk); | |
743 | spi_master_put(p->bitbang.master); | |
744 | } | |
745 | return ret; | |
746 | } | |
747 | ||
748 | static int sh_msiof_spi_runtime_nop(struct device *dev) | |
749 | { | |
750 | /* Runtime PM callback shared between ->runtime_suspend() | |
751 | * and ->runtime_resume(). Simply returns success. | |
752 | * | |
753 | * This driver re-initializes all registers after | |
754 | * pm_runtime_get_sync() anyway so there is no need | |
755 | * to save and restore registers here. | |
756 | */ | |
757 | return 0; | |
758 | } | |
759 | ||
cf9c86ef BH |
760 | #ifdef CONFIG_OF |
761 | static const struct of_device_id sh_msiof_match[] = { | |
762 | { .compatible = "renesas,sh-msiof", }, | |
763 | { .compatible = "renesas,sh-mobile-msiof", }, | |
764 | {}, | |
765 | }; | |
766 | MODULE_DEVICE_TABLE(of, sh_msiof_match); | |
767 | #else | |
768 | #define sh_msiof_match NULL | |
769 | #endif | |
770 | ||
8051effc MD |
771 | static struct dev_pm_ops sh_msiof_spi_dev_pm_ops = { |
772 | .runtime_suspend = sh_msiof_spi_runtime_nop, | |
773 | .runtime_resume = sh_msiof_spi_runtime_nop, | |
774 | }; | |
775 | ||
776 | static struct platform_driver sh_msiof_spi_drv = { | |
777 | .probe = sh_msiof_spi_probe, | |
778 | .remove = sh_msiof_spi_remove, | |
779 | .driver = { | |
780 | .name = "spi_sh_msiof", | |
781 | .owner = THIS_MODULE, | |
782 | .pm = &sh_msiof_spi_dev_pm_ops, | |
cf9c86ef | 783 | .of_match_table = sh_msiof_match, |
8051effc MD |
784 | }, |
785 | }; | |
940ab889 | 786 | module_platform_driver(sh_msiof_spi_drv); |
8051effc MD |
787 | |
788 | MODULE_DESCRIPTION("SuperH MSIOF SPI Master Interface Driver"); | |
789 | MODULE_AUTHOR("Magnus Damm"); | |
790 | MODULE_LICENSE("GPL v2"); | |
791 | MODULE_ALIAS("platform:spi_sh_msiof"); |