Commit | Line | Data |
---|---|---|
8051effc MD |
1 | /* |
2 | * SuperH MSIOF SPI Master Interface | |
3 | * | |
4 | * Copyright (c) 2009 Magnus Damm | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License version 2 as | |
8 | * published by the Free Software Foundation. | |
9 | * | |
10 | */ | |
11 | ||
e2dbf5eb GL |
12 | #include <linux/bitmap.h> |
13 | #include <linux/clk.h> | |
14 | #include <linux/completion.h> | |
8051effc | 15 | #include <linux/delay.h> |
e2dbf5eb GL |
16 | #include <linux/err.h> |
17 | #include <linux/gpio.h> | |
18 | #include <linux/init.h> | |
8051effc | 19 | #include <linux/interrupt.h> |
e2dbf5eb GL |
20 | #include <linux/io.h> |
21 | #include <linux/kernel.h> | |
d7614de4 | 22 | #include <linux/module.h> |
cf9c86ef | 23 | #include <linux/of.h> |
8051effc | 24 | #include <linux/platform_device.h> |
8051effc | 25 | #include <linux/pm_runtime.h> |
8051effc | 26 | |
e2dbf5eb | 27 | #include <linux/spi/sh_msiof.h> |
8051effc MD |
28 | #include <linux/spi/spi.h> |
29 | #include <linux/spi/spi_bitbang.h> | |
8051effc | 30 | |
8051effc MD |
31 | #include <asm/unaligned.h> |
32 | ||
33 | struct sh_msiof_spi_priv { | |
34 | struct spi_bitbang bitbang; /* must be first for spi_bitbang.c */ | |
35 | void __iomem *mapbase; | |
36 | struct clk *clk; | |
37 | struct platform_device *pdev; | |
38 | struct sh_msiof_spi_info *info; | |
39 | struct completion done; | |
40 | unsigned long flags; | |
41 | int tx_fifo_size; | |
42 | int rx_fifo_size; | |
43 | }; | |
44 | ||
45 | #define TMDR1 0x00 | |
46 | #define TMDR2 0x04 | |
47 | #define TMDR3 0x08 | |
48 | #define RMDR1 0x10 | |
49 | #define RMDR2 0x14 | |
50 | #define RMDR3 0x18 | |
51 | #define TSCR 0x20 | |
52 | #define RSCR 0x22 | |
53 | #define CTR 0x28 | |
54 | #define FCTR 0x30 | |
55 | #define STR 0x40 | |
56 | #define IER 0x44 | |
57 | #define TDR1 0x48 | |
58 | #define TDR2 0x4c | |
59 | #define TFDR 0x50 | |
60 | #define RDR1 0x58 | |
61 | #define RDR2 0x5c | |
62 | #define RFDR 0x60 | |
63 | ||
64 | #define CTR_TSCKE (1 << 15) | |
65 | #define CTR_TFSE (1 << 14) | |
66 | #define CTR_TXE (1 << 9) | |
67 | #define CTR_RXE (1 << 8) | |
68 | ||
69 | #define STR_TEOF (1 << 23) | |
70 | #define STR_REOF (1 << 7) | |
71 | ||
e2dbf5eb | 72 | static u32 sh_msiof_read(struct sh_msiof_spi_priv *p, int reg_offs) |
8051effc MD |
73 | { |
74 | switch (reg_offs) { | |
75 | case TSCR: | |
76 | case RSCR: | |
77 | return ioread16(p->mapbase + reg_offs); | |
78 | default: | |
79 | return ioread32(p->mapbase + reg_offs); | |
80 | } | |
81 | } | |
82 | ||
83 | static void sh_msiof_write(struct sh_msiof_spi_priv *p, int reg_offs, | |
e2dbf5eb | 84 | u32 value) |
8051effc MD |
85 | { |
86 | switch (reg_offs) { | |
87 | case TSCR: | |
88 | case RSCR: | |
89 | iowrite16(value, p->mapbase + reg_offs); | |
90 | break; | |
91 | default: | |
92 | iowrite32(value, p->mapbase + reg_offs); | |
93 | break; | |
94 | } | |
95 | } | |
96 | ||
97 | static int sh_msiof_modify_ctr_wait(struct sh_msiof_spi_priv *p, | |
e2dbf5eb | 98 | u32 clr, u32 set) |
8051effc | 99 | { |
e2dbf5eb GL |
100 | u32 mask = clr | set; |
101 | u32 data; | |
8051effc MD |
102 | int k; |
103 | ||
104 | data = sh_msiof_read(p, CTR); | |
105 | data &= ~clr; | |
106 | data |= set; | |
107 | sh_msiof_write(p, CTR, data); | |
108 | ||
109 | for (k = 100; k > 0; k--) { | |
110 | if ((sh_msiof_read(p, CTR) & mask) == set) | |
111 | break; | |
112 | ||
113 | udelay(10); | |
114 | } | |
115 | ||
116 | return k > 0 ? 0 : -ETIMEDOUT; | |
117 | } | |
118 | ||
119 | static irqreturn_t sh_msiof_spi_irq(int irq, void *data) | |
120 | { | |
121 | struct sh_msiof_spi_priv *p = data; | |
122 | ||
123 | /* just disable the interrupt and wake up */ | |
124 | sh_msiof_write(p, IER, 0); | |
125 | complete(&p->done); | |
126 | ||
127 | return IRQ_HANDLED; | |
128 | } | |
129 | ||
130 | static struct { | |
131 | unsigned short div; | |
132 | unsigned short scr; | |
133 | } const sh_msiof_spi_clk_table[] = { | |
134 | { 1, 0x0007 }, | |
135 | { 2, 0x0000 }, | |
136 | { 4, 0x0001 }, | |
137 | { 8, 0x0002 }, | |
138 | { 16, 0x0003 }, | |
139 | { 32, 0x0004 }, | |
140 | { 64, 0x1f00 }, | |
141 | { 128, 0x1f01 }, | |
142 | { 256, 0x1f02 }, | |
143 | { 512, 0x1f03 }, | |
144 | { 1024, 0x1f04 }, | |
145 | }; | |
146 | ||
147 | static void sh_msiof_spi_set_clk_regs(struct sh_msiof_spi_priv *p, | |
148 | unsigned long parent_rate, | |
149 | unsigned long spi_hz) | |
150 | { | |
151 | unsigned long div = 1024; | |
152 | size_t k; | |
153 | ||
154 | if (!WARN_ON(!spi_hz || !parent_rate)) | |
e4d313ff | 155 | div = DIV_ROUND_UP(parent_rate, spi_hz); |
8051effc MD |
156 | |
157 | /* TODO: make more fine grained */ | |
158 | ||
159 | for (k = 0; k < ARRAY_SIZE(sh_msiof_spi_clk_table); k++) { | |
160 | if (sh_msiof_spi_clk_table[k].div >= div) | |
161 | break; | |
162 | } | |
163 | ||
164 | k = min_t(int, k, ARRAY_SIZE(sh_msiof_spi_clk_table) - 1); | |
165 | ||
166 | sh_msiof_write(p, TSCR, sh_msiof_spi_clk_table[k].scr); | |
167 | sh_msiof_write(p, RSCR, sh_msiof_spi_clk_table[k].scr); | |
168 | } | |
169 | ||
170 | static void sh_msiof_spi_set_pin_regs(struct sh_msiof_spi_priv *p, | |
e2dbf5eb | 171 | u32 cpol, u32 cpha, |
50a77998 | 172 | u32 tx_hi_z, u32 lsb_first, u32 cs_high) |
8051effc | 173 | { |
e2dbf5eb | 174 | u32 tmp; |
8051effc MD |
175 | int edge; |
176 | ||
177 | /* | |
e8708ef7 MP |
178 | * CPOL CPHA TSCKIZ RSCKIZ TEDG REDG |
179 | * 0 0 10 10 1 1 | |
180 | * 0 1 10 10 0 0 | |
181 | * 1 0 11 11 0 0 | |
182 | * 1 1 11 11 1 1 | |
8051effc | 183 | */ |
8051effc | 184 | sh_msiof_write(p, FCTR, 0); |
50a77998 TY |
185 | |
186 | tmp = 0; | |
187 | tmp |= !cs_high << 25; | |
188 | tmp |= lsb_first << 24; | |
189 | sh_msiof_write(p, TMDR1, 0xe0000005 | tmp); | |
190 | sh_msiof_write(p, RMDR1, 0x20000005 | tmp); | |
8051effc MD |
191 | |
192 | tmp = 0xa0000000; | |
193 | tmp |= cpol << 30; /* TSCKIZ */ | |
194 | tmp |= cpol << 28; /* RSCKIZ */ | |
195 | ||
e2dbf5eb | 196 | edge = cpol ^ !cpha; |
8051effc MD |
197 | |
198 | tmp |= edge << 27; /* TEDG */ | |
e8708ef7 | 199 | tmp |= edge << 26; /* REDG */ |
8051effc MD |
200 | tmp |= (tx_hi_z ? 2 : 0) << 22; /* TXDIZ */ |
201 | sh_msiof_write(p, CTR, tmp); | |
202 | } | |
203 | ||
204 | static void sh_msiof_spi_set_mode_regs(struct sh_msiof_spi_priv *p, | |
205 | const void *tx_buf, void *rx_buf, | |
e2dbf5eb | 206 | u32 bits, u32 words) |
8051effc | 207 | { |
e2dbf5eb | 208 | u32 dr2 = ((bits - 1) << 24) | ((words - 1) << 16); |
8051effc MD |
209 | |
210 | if (tx_buf) | |
211 | sh_msiof_write(p, TMDR2, dr2); | |
212 | else | |
213 | sh_msiof_write(p, TMDR2, dr2 | 1); | |
214 | ||
215 | if (rx_buf) | |
216 | sh_msiof_write(p, RMDR2, dr2); | |
217 | ||
218 | sh_msiof_write(p, IER, STR_TEOF | STR_REOF); | |
219 | } | |
220 | ||
221 | static void sh_msiof_reset_str(struct sh_msiof_spi_priv *p) | |
222 | { | |
223 | sh_msiof_write(p, STR, sh_msiof_read(p, STR)); | |
224 | } | |
225 | ||
226 | static void sh_msiof_spi_write_fifo_8(struct sh_msiof_spi_priv *p, | |
227 | const void *tx_buf, int words, int fs) | |
228 | { | |
e2dbf5eb | 229 | const u8 *buf_8 = tx_buf; |
8051effc MD |
230 | int k; |
231 | ||
232 | for (k = 0; k < words; k++) | |
233 | sh_msiof_write(p, TFDR, buf_8[k] << fs); | |
234 | } | |
235 | ||
236 | static void sh_msiof_spi_write_fifo_16(struct sh_msiof_spi_priv *p, | |
237 | const void *tx_buf, int words, int fs) | |
238 | { | |
e2dbf5eb | 239 | const u16 *buf_16 = tx_buf; |
8051effc MD |
240 | int k; |
241 | ||
242 | for (k = 0; k < words; k++) | |
243 | sh_msiof_write(p, TFDR, buf_16[k] << fs); | |
244 | } | |
245 | ||
246 | static void sh_msiof_spi_write_fifo_16u(struct sh_msiof_spi_priv *p, | |
247 | const void *tx_buf, int words, int fs) | |
248 | { | |
e2dbf5eb | 249 | const u16 *buf_16 = tx_buf; |
8051effc MD |
250 | int k; |
251 | ||
252 | for (k = 0; k < words; k++) | |
253 | sh_msiof_write(p, TFDR, get_unaligned(&buf_16[k]) << fs); | |
254 | } | |
255 | ||
256 | static void sh_msiof_spi_write_fifo_32(struct sh_msiof_spi_priv *p, | |
257 | const void *tx_buf, int words, int fs) | |
258 | { | |
e2dbf5eb | 259 | const u32 *buf_32 = tx_buf; |
8051effc MD |
260 | int k; |
261 | ||
262 | for (k = 0; k < words; k++) | |
263 | sh_msiof_write(p, TFDR, buf_32[k] << fs); | |
264 | } | |
265 | ||
266 | static void sh_msiof_spi_write_fifo_32u(struct sh_msiof_spi_priv *p, | |
267 | const void *tx_buf, int words, int fs) | |
268 | { | |
e2dbf5eb | 269 | const u32 *buf_32 = tx_buf; |
8051effc MD |
270 | int k; |
271 | ||
272 | for (k = 0; k < words; k++) | |
273 | sh_msiof_write(p, TFDR, get_unaligned(&buf_32[k]) << fs); | |
274 | } | |
275 | ||
9dabb3f3 GL |
276 | static void sh_msiof_spi_write_fifo_s32(struct sh_msiof_spi_priv *p, |
277 | const void *tx_buf, int words, int fs) | |
278 | { | |
279 | const u32 *buf_32 = tx_buf; | |
280 | int k; | |
281 | ||
282 | for (k = 0; k < words; k++) | |
283 | sh_msiof_write(p, TFDR, swab32(buf_32[k] << fs)); | |
284 | } | |
285 | ||
286 | static void sh_msiof_spi_write_fifo_s32u(struct sh_msiof_spi_priv *p, | |
287 | const void *tx_buf, int words, int fs) | |
288 | { | |
289 | const u32 *buf_32 = tx_buf; | |
290 | int k; | |
291 | ||
292 | for (k = 0; k < words; k++) | |
293 | sh_msiof_write(p, TFDR, swab32(get_unaligned(&buf_32[k]) << fs)); | |
294 | } | |
295 | ||
8051effc MD |
296 | static void sh_msiof_spi_read_fifo_8(struct sh_msiof_spi_priv *p, |
297 | void *rx_buf, int words, int fs) | |
298 | { | |
e2dbf5eb | 299 | u8 *buf_8 = rx_buf; |
8051effc MD |
300 | int k; |
301 | ||
302 | for (k = 0; k < words; k++) | |
303 | buf_8[k] = sh_msiof_read(p, RFDR) >> fs; | |
304 | } | |
305 | ||
306 | static void sh_msiof_spi_read_fifo_16(struct sh_msiof_spi_priv *p, | |
307 | void *rx_buf, int words, int fs) | |
308 | { | |
e2dbf5eb | 309 | u16 *buf_16 = rx_buf; |
8051effc MD |
310 | int k; |
311 | ||
312 | for (k = 0; k < words; k++) | |
313 | buf_16[k] = sh_msiof_read(p, RFDR) >> fs; | |
314 | } | |
315 | ||
316 | static void sh_msiof_spi_read_fifo_16u(struct sh_msiof_spi_priv *p, | |
317 | void *rx_buf, int words, int fs) | |
318 | { | |
e2dbf5eb | 319 | u16 *buf_16 = rx_buf; |
8051effc MD |
320 | int k; |
321 | ||
322 | for (k = 0; k < words; k++) | |
323 | put_unaligned(sh_msiof_read(p, RFDR) >> fs, &buf_16[k]); | |
324 | } | |
325 | ||
326 | static void sh_msiof_spi_read_fifo_32(struct sh_msiof_spi_priv *p, | |
327 | void *rx_buf, int words, int fs) | |
328 | { | |
e2dbf5eb | 329 | u32 *buf_32 = rx_buf; |
8051effc MD |
330 | int k; |
331 | ||
332 | for (k = 0; k < words; k++) | |
333 | buf_32[k] = sh_msiof_read(p, RFDR) >> fs; | |
334 | } | |
335 | ||
336 | static void sh_msiof_spi_read_fifo_32u(struct sh_msiof_spi_priv *p, | |
337 | void *rx_buf, int words, int fs) | |
338 | { | |
e2dbf5eb | 339 | u32 *buf_32 = rx_buf; |
8051effc MD |
340 | int k; |
341 | ||
342 | for (k = 0; k < words; k++) | |
343 | put_unaligned(sh_msiof_read(p, RFDR) >> fs, &buf_32[k]); | |
344 | } | |
345 | ||
9dabb3f3 GL |
346 | static void sh_msiof_spi_read_fifo_s32(struct sh_msiof_spi_priv *p, |
347 | void *rx_buf, int words, int fs) | |
348 | { | |
349 | u32 *buf_32 = rx_buf; | |
350 | int k; | |
351 | ||
352 | for (k = 0; k < words; k++) | |
353 | buf_32[k] = swab32(sh_msiof_read(p, RFDR) >> fs); | |
354 | } | |
355 | ||
356 | static void sh_msiof_spi_read_fifo_s32u(struct sh_msiof_spi_priv *p, | |
357 | void *rx_buf, int words, int fs) | |
358 | { | |
359 | u32 *buf_32 = rx_buf; | |
360 | int k; | |
361 | ||
362 | for (k = 0; k < words; k++) | |
363 | put_unaligned(swab32(sh_msiof_read(p, RFDR) >> fs), &buf_32[k]); | |
364 | } | |
365 | ||
8051effc MD |
366 | static int sh_msiof_spi_bits(struct spi_device *spi, struct spi_transfer *t) |
367 | { | |
368 | int bits; | |
369 | ||
370 | bits = t ? t->bits_per_word : 0; | |
e2dbf5eb GL |
371 | if (!bits) |
372 | bits = spi->bits_per_word; | |
8051effc MD |
373 | return bits; |
374 | } | |
375 | ||
376 | static unsigned long sh_msiof_spi_hz(struct spi_device *spi, | |
377 | struct spi_transfer *t) | |
378 | { | |
379 | unsigned long hz; | |
380 | ||
381 | hz = t ? t->speed_hz : 0; | |
e2dbf5eb GL |
382 | if (!hz) |
383 | hz = spi->max_speed_hz; | |
8051effc MD |
384 | return hz; |
385 | } | |
386 | ||
387 | static int sh_msiof_spi_setup_transfer(struct spi_device *spi, | |
388 | struct spi_transfer *t) | |
389 | { | |
390 | int bits; | |
391 | ||
392 | /* noting to check hz values against since parent clock is disabled */ | |
393 | ||
394 | bits = sh_msiof_spi_bits(spi, t); | |
395 | if (bits < 8) | |
396 | return -EINVAL; | |
397 | if (bits > 32) | |
398 | return -EINVAL; | |
399 | ||
400 | return spi_bitbang_setup_transfer(spi, t); | |
401 | } | |
402 | ||
403 | static void sh_msiof_spi_chipselect(struct spi_device *spi, int is_on) | |
404 | { | |
405 | struct sh_msiof_spi_priv *p = spi_master_get_devdata(spi->master); | |
406 | int value; | |
407 | ||
408 | /* chip select is active low unless SPI_CS_HIGH is set */ | |
409 | if (spi->mode & SPI_CS_HIGH) | |
410 | value = (is_on == BITBANG_CS_ACTIVE) ? 1 : 0; | |
411 | else | |
412 | value = (is_on == BITBANG_CS_ACTIVE) ? 0 : 1; | |
413 | ||
414 | if (is_on == BITBANG_CS_ACTIVE) { | |
415 | if (!test_and_set_bit(0, &p->flags)) { | |
416 | pm_runtime_get_sync(&p->pdev->dev); | |
417 | clk_enable(p->clk); | |
418 | } | |
419 | ||
420 | /* Configure pins before asserting CS */ | |
421 | sh_msiof_spi_set_pin_regs(p, !!(spi->mode & SPI_CPOL), | |
422 | !!(spi->mode & SPI_CPHA), | |
423 | !!(spi->mode & SPI_3WIRE), | |
50a77998 TY |
424 | !!(spi->mode & SPI_LSB_FIRST), |
425 | !!(spi->mode & SPI_CS_HIGH)); | |
8051effc MD |
426 | } |
427 | ||
428 | /* use spi->controller data for CS (same strategy as spi_gpio) */ | |
3e6006e4 | 429 | gpio_set_value((uintptr_t)spi->controller_data, value); |
8051effc MD |
430 | |
431 | if (is_on == BITBANG_CS_INACTIVE) { | |
432 | if (test_and_clear_bit(0, &p->flags)) { | |
433 | clk_disable(p->clk); | |
434 | pm_runtime_put(&p->pdev->dev); | |
435 | } | |
436 | } | |
437 | } | |
438 | ||
439 | static int sh_msiof_spi_txrx_once(struct sh_msiof_spi_priv *p, | |
440 | void (*tx_fifo)(struct sh_msiof_spi_priv *, | |
441 | const void *, int, int), | |
442 | void (*rx_fifo)(struct sh_msiof_spi_priv *, | |
443 | void *, int, int), | |
444 | const void *tx_buf, void *rx_buf, | |
445 | int words, int bits) | |
446 | { | |
447 | int fifo_shift; | |
448 | int ret; | |
449 | ||
450 | /* limit maximum word transfer to rx/tx fifo size */ | |
451 | if (tx_buf) | |
452 | words = min_t(int, words, p->tx_fifo_size); | |
453 | if (rx_buf) | |
454 | words = min_t(int, words, p->rx_fifo_size); | |
455 | ||
456 | /* the fifo contents need shifting */ | |
457 | fifo_shift = 32 - bits; | |
458 | ||
459 | /* setup msiof transfer mode registers */ | |
460 | sh_msiof_spi_set_mode_regs(p, tx_buf, rx_buf, bits, words); | |
461 | ||
462 | /* write tx fifo */ | |
463 | if (tx_buf) | |
464 | tx_fifo(p, tx_buf, words, fifo_shift); | |
465 | ||
466 | /* setup clock and rx/tx signals */ | |
467 | ret = sh_msiof_modify_ctr_wait(p, 0, CTR_TSCKE); | |
468 | if (rx_buf) | |
469 | ret = ret ? ret : sh_msiof_modify_ctr_wait(p, 0, CTR_RXE); | |
470 | ret = ret ? ret : sh_msiof_modify_ctr_wait(p, 0, CTR_TXE); | |
471 | ||
472 | /* start by setting frame bit */ | |
16735d02 | 473 | reinit_completion(&p->done); |
8051effc MD |
474 | ret = ret ? ret : sh_msiof_modify_ctr_wait(p, 0, CTR_TFSE); |
475 | if (ret) { | |
476 | dev_err(&p->pdev->dev, "failed to start hardware\n"); | |
477 | goto err; | |
478 | } | |
479 | ||
480 | /* wait for tx fifo to be emptied / rx fifo to be filled */ | |
481 | wait_for_completion(&p->done); | |
482 | ||
483 | /* read rx fifo */ | |
484 | if (rx_buf) | |
485 | rx_fifo(p, rx_buf, words, fifo_shift); | |
486 | ||
487 | /* clear status bits */ | |
488 | sh_msiof_reset_str(p); | |
489 | ||
a669c11a | 490 | /* shut down frame, rx/tx and clock signals */ |
8051effc MD |
491 | ret = sh_msiof_modify_ctr_wait(p, CTR_TFSE, 0); |
492 | ret = ret ? ret : sh_msiof_modify_ctr_wait(p, CTR_TXE, 0); | |
493 | if (rx_buf) | |
494 | ret = ret ? ret : sh_msiof_modify_ctr_wait(p, CTR_RXE, 0); | |
495 | ret = ret ? ret : sh_msiof_modify_ctr_wait(p, CTR_TSCKE, 0); | |
496 | if (ret) { | |
497 | dev_err(&p->pdev->dev, "failed to shut down hardware\n"); | |
498 | goto err; | |
499 | } | |
500 | ||
501 | return words; | |
502 | ||
503 | err: | |
504 | sh_msiof_write(p, IER, 0); | |
505 | return ret; | |
506 | } | |
507 | ||
508 | static int sh_msiof_spi_txrx(struct spi_device *spi, struct spi_transfer *t) | |
509 | { | |
510 | struct sh_msiof_spi_priv *p = spi_master_get_devdata(spi->master); | |
511 | void (*tx_fifo)(struct sh_msiof_spi_priv *, const void *, int, int); | |
512 | void (*rx_fifo)(struct sh_msiof_spi_priv *, void *, int, int); | |
513 | int bits; | |
514 | int bytes_per_word; | |
515 | int bytes_done; | |
516 | int words; | |
517 | int n; | |
9dabb3f3 | 518 | bool swab; |
8051effc MD |
519 | |
520 | bits = sh_msiof_spi_bits(spi, t); | |
521 | ||
9dabb3f3 GL |
522 | if (bits <= 8 && t->len > 15 && !(t->len & 3)) { |
523 | bits = 32; | |
524 | swab = true; | |
525 | } else { | |
526 | swab = false; | |
527 | } | |
528 | ||
8051effc MD |
529 | /* setup bytes per word and fifo read/write functions */ |
530 | if (bits <= 8) { | |
531 | bytes_per_word = 1; | |
532 | tx_fifo = sh_msiof_spi_write_fifo_8; | |
533 | rx_fifo = sh_msiof_spi_read_fifo_8; | |
534 | } else if (bits <= 16) { | |
535 | bytes_per_word = 2; | |
536 | if ((unsigned long)t->tx_buf & 0x01) | |
537 | tx_fifo = sh_msiof_spi_write_fifo_16u; | |
538 | else | |
539 | tx_fifo = sh_msiof_spi_write_fifo_16; | |
540 | ||
541 | if ((unsigned long)t->rx_buf & 0x01) | |
542 | rx_fifo = sh_msiof_spi_read_fifo_16u; | |
543 | else | |
544 | rx_fifo = sh_msiof_spi_read_fifo_16; | |
9dabb3f3 GL |
545 | } else if (swab) { |
546 | bytes_per_word = 4; | |
547 | if ((unsigned long)t->tx_buf & 0x03) | |
548 | tx_fifo = sh_msiof_spi_write_fifo_s32u; | |
549 | else | |
550 | tx_fifo = sh_msiof_spi_write_fifo_s32; | |
551 | ||
552 | if ((unsigned long)t->rx_buf & 0x03) | |
553 | rx_fifo = sh_msiof_spi_read_fifo_s32u; | |
554 | else | |
555 | rx_fifo = sh_msiof_spi_read_fifo_s32; | |
8051effc MD |
556 | } else { |
557 | bytes_per_word = 4; | |
558 | if ((unsigned long)t->tx_buf & 0x03) | |
559 | tx_fifo = sh_msiof_spi_write_fifo_32u; | |
560 | else | |
561 | tx_fifo = sh_msiof_spi_write_fifo_32; | |
562 | ||
563 | if ((unsigned long)t->rx_buf & 0x03) | |
564 | rx_fifo = sh_msiof_spi_read_fifo_32u; | |
565 | else | |
566 | rx_fifo = sh_msiof_spi_read_fifo_32; | |
567 | } | |
568 | ||
569 | /* setup clocks (clock already enabled in chipselect()) */ | |
570 | sh_msiof_spi_set_clk_regs(p, clk_get_rate(p->clk), | |
571 | sh_msiof_spi_hz(spi, t)); | |
572 | ||
573 | /* transfer in fifo sized chunks */ | |
574 | words = t->len / bytes_per_word; | |
575 | bytes_done = 0; | |
576 | ||
577 | while (bytes_done < t->len) { | |
8a6afb9a GL |
578 | void *rx_buf = t->rx_buf ? t->rx_buf + bytes_done : NULL; |
579 | const void *tx_buf = t->tx_buf ? t->tx_buf + bytes_done : NULL; | |
8051effc | 580 | n = sh_msiof_spi_txrx_once(p, tx_fifo, rx_fifo, |
8a6afb9a GL |
581 | tx_buf, |
582 | rx_buf, | |
8051effc MD |
583 | words, bits); |
584 | if (n < 0) | |
585 | break; | |
586 | ||
587 | bytes_done += n * bytes_per_word; | |
588 | words -= n; | |
589 | } | |
590 | ||
591 | return bytes_done; | |
592 | } | |
593 | ||
594 | static u32 sh_msiof_spi_txrx_word(struct spi_device *spi, unsigned nsecs, | |
595 | u32 word, u8 bits) | |
596 | { | |
597 | BUG(); /* unused but needed by bitbang code */ | |
598 | return 0; | |
599 | } | |
600 | ||
cf9c86ef BH |
601 | #ifdef CONFIG_OF |
602 | static struct sh_msiof_spi_info *sh_msiof_spi_parse_dt(struct device *dev) | |
603 | { | |
604 | struct sh_msiof_spi_info *info; | |
605 | struct device_node *np = dev->of_node; | |
606 | u32 num_cs = 0; | |
607 | ||
608 | info = devm_kzalloc(dev, sizeof(struct sh_msiof_spi_info), GFP_KERNEL); | |
609 | if (!info) { | |
610 | dev_err(dev, "failed to allocate setup data\n"); | |
611 | return NULL; | |
612 | } | |
613 | ||
614 | /* Parse the MSIOF properties */ | |
615 | of_property_read_u32(np, "num-cs", &num_cs); | |
616 | of_property_read_u32(np, "renesas,tx-fifo-size", | |
617 | &info->tx_fifo_override); | |
618 | of_property_read_u32(np, "renesas,rx-fifo-size", | |
619 | &info->rx_fifo_override); | |
620 | ||
621 | info->num_chipselect = num_cs; | |
622 | ||
623 | return info; | |
624 | } | |
625 | #else | |
626 | static struct sh_msiof_spi_info *sh_msiof_spi_parse_dt(struct device *dev) | |
627 | { | |
628 | return NULL; | |
629 | } | |
630 | #endif | |
631 | ||
8051effc MD |
632 | static int sh_msiof_spi_probe(struct platform_device *pdev) |
633 | { | |
634 | struct resource *r; | |
635 | struct spi_master *master; | |
636 | struct sh_msiof_spi_priv *p; | |
8051effc MD |
637 | int i; |
638 | int ret; | |
639 | ||
640 | master = spi_alloc_master(&pdev->dev, sizeof(struct sh_msiof_spi_priv)); | |
641 | if (master == NULL) { | |
642 | dev_err(&pdev->dev, "failed to allocate spi master\n"); | |
b4dd05de | 643 | return -ENOMEM; |
8051effc MD |
644 | } |
645 | ||
646 | p = spi_master_get_devdata(master); | |
647 | ||
648 | platform_set_drvdata(pdev, p); | |
cf9c86ef BH |
649 | if (pdev->dev.of_node) |
650 | p->info = sh_msiof_spi_parse_dt(&pdev->dev); | |
651 | else | |
8074cf06 | 652 | p->info = dev_get_platdata(&pdev->dev); |
cf9c86ef BH |
653 | |
654 | if (!p->info) { | |
655 | dev_err(&pdev->dev, "failed to obtain device info\n"); | |
656 | ret = -ENXIO; | |
657 | goto err1; | |
658 | } | |
659 | ||
8051effc MD |
660 | init_completion(&p->done); |
661 | ||
b4dd05de | 662 | p->clk = devm_clk_get(&pdev->dev, NULL); |
8051effc | 663 | if (IS_ERR(p->clk)) { |
078b6ead | 664 | dev_err(&pdev->dev, "cannot get clock\n"); |
8051effc MD |
665 | ret = PTR_ERR(p->clk); |
666 | goto err1; | |
667 | } | |
668 | ||
8051effc | 669 | i = platform_get_irq(pdev, 0); |
b4dd05de LP |
670 | if (i < 0) { |
671 | dev_err(&pdev->dev, "cannot get platform IRQ\n"); | |
8051effc | 672 | ret = -ENOENT; |
b4dd05de | 673 | goto err1; |
8051effc | 674 | } |
b4dd05de LP |
675 | |
676 | r = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
677 | p->mapbase = devm_ioremap_resource(&pdev->dev, r); | |
678 | if (IS_ERR(p->mapbase)) { | |
679 | ret = PTR_ERR(p->mapbase); | |
680 | goto err1; | |
8051effc MD |
681 | } |
682 | ||
b4dd05de LP |
683 | ret = devm_request_irq(&pdev->dev, i, sh_msiof_spi_irq, 0, |
684 | dev_name(&pdev->dev), p); | |
8051effc MD |
685 | if (ret) { |
686 | dev_err(&pdev->dev, "unable to request irq\n"); | |
b4dd05de | 687 | goto err1; |
8051effc MD |
688 | } |
689 | ||
5c32d29f LP |
690 | ret = clk_prepare(p->clk); |
691 | if (ret < 0) { | |
692 | dev_err(&pdev->dev, "unable to prepare clock\n"); | |
693 | goto err1; | |
8051effc MD |
694 | } |
695 | ||
696 | p->pdev = pdev; | |
697 | pm_runtime_enable(&pdev->dev); | |
698 | ||
699 | /* The standard version of MSIOF use 64 word FIFOs */ | |
700 | p->tx_fifo_size = 64; | |
701 | p->rx_fifo_size = 64; | |
702 | ||
703 | /* Platform data may override FIFO sizes */ | |
704 | if (p->info->tx_fifo_override) | |
705 | p->tx_fifo_size = p->info->tx_fifo_override; | |
706 | if (p->info->rx_fifo_override) | |
707 | p->rx_fifo_size = p->info->rx_fifo_override; | |
708 | ||
709 | /* init master and bitbang code */ | |
710 | master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH; | |
711 | master->mode_bits |= SPI_LSB_FIRST | SPI_3WIRE; | |
712 | master->flags = 0; | |
713 | master->bus_num = pdev->id; | |
f7c05e83 | 714 | master->dev.of_node = pdev->dev.of_node; |
8051effc MD |
715 | master->num_chipselect = p->info->num_chipselect; |
716 | master->setup = spi_bitbang_setup; | |
717 | master->cleanup = spi_bitbang_cleanup; | |
718 | ||
719 | p->bitbang.master = master; | |
720 | p->bitbang.chipselect = sh_msiof_spi_chipselect; | |
721 | p->bitbang.setup_transfer = sh_msiof_spi_setup_transfer; | |
722 | p->bitbang.txrx_bufs = sh_msiof_spi_txrx; | |
723 | p->bitbang.txrx_word[SPI_MODE_0] = sh_msiof_spi_txrx_word; | |
724 | p->bitbang.txrx_word[SPI_MODE_1] = sh_msiof_spi_txrx_word; | |
725 | p->bitbang.txrx_word[SPI_MODE_2] = sh_msiof_spi_txrx_word; | |
726 | p->bitbang.txrx_word[SPI_MODE_3] = sh_msiof_spi_txrx_word; | |
727 | ||
728 | ret = spi_bitbang_start(&p->bitbang); | |
729 | if (ret == 0) | |
730 | return 0; | |
731 | ||
732 | pm_runtime_disable(&pdev->dev); | |
5c32d29f | 733 | clk_unprepare(p->clk); |
8051effc MD |
734 | err1: |
735 | spi_master_put(master); | |
8051effc MD |
736 | return ret; |
737 | } | |
738 | ||
739 | static int sh_msiof_spi_remove(struct platform_device *pdev) | |
740 | { | |
741 | struct sh_msiof_spi_priv *p = platform_get_drvdata(pdev); | |
742 | int ret; | |
743 | ||
744 | ret = spi_bitbang_stop(&p->bitbang); | |
745 | if (!ret) { | |
746 | pm_runtime_disable(&pdev->dev); | |
5c32d29f | 747 | clk_unprepare(p->clk); |
8051effc MD |
748 | spi_master_put(p->bitbang.master); |
749 | } | |
750 | return ret; | |
751 | } | |
752 | ||
cf9c86ef BH |
753 | #ifdef CONFIG_OF |
754 | static const struct of_device_id sh_msiof_match[] = { | |
755 | { .compatible = "renesas,sh-msiof", }, | |
756 | { .compatible = "renesas,sh-mobile-msiof", }, | |
757 | {}, | |
758 | }; | |
759 | MODULE_DEVICE_TABLE(of, sh_msiof_match); | |
cf9c86ef BH |
760 | #endif |
761 | ||
8051effc MD |
762 | static struct platform_driver sh_msiof_spi_drv = { |
763 | .probe = sh_msiof_spi_probe, | |
764 | .remove = sh_msiof_spi_remove, | |
765 | .driver = { | |
766 | .name = "spi_sh_msiof", | |
767 | .owner = THIS_MODULE, | |
691ee4ed | 768 | .of_match_table = of_match_ptr(sh_msiof_match), |
8051effc MD |
769 | }, |
770 | }; | |
940ab889 | 771 | module_platform_driver(sh_msiof_spi_drv); |
8051effc MD |
772 | |
773 | MODULE_DESCRIPTION("SuperH MSIOF SPI Master Interface Driver"); | |
774 | MODULE_AUTHOR("Magnus Damm"); | |
775 | MODULE_LICENSE("GPL v2"); | |
776 | MODULE_ALIAS("platform:spi_sh_msiof"); |