Commit | Line | Data |
---|---|---|
dc4dc360 LD |
1 | /* |
2 | * SPI driver for Nvidia's Tegra20/Tegra30 SLINK Controller. | |
3 | * | |
4 | * Copyright (c) 2012, NVIDIA CORPORATION. All rights reserved. | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify it | |
7 | * under the terms and conditions of the GNU General Public License, | |
8 | * version 2, as published by the Free Software Foundation. | |
9 | * | |
10 | * This program is distributed in the hope it will be useful, but WITHOUT | |
11 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
12 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
13 | * more details. | |
14 | * | |
15 | * You should have received a copy of the GNU General Public License | |
16 | * along with this program. If not, see <http://www.gnu.org/licenses/>. | |
17 | */ | |
18 | ||
19 | #include <linux/clk.h> | |
20 | #include <linux/completion.h> | |
21 | #include <linux/delay.h> | |
22 | #include <linux/dmaengine.h> | |
23 | #include <linux/dma-mapping.h> | |
24 | #include <linux/dmapool.h> | |
25 | #include <linux/err.h> | |
26 | #include <linux/init.h> | |
27 | #include <linux/interrupt.h> | |
28 | #include <linux/io.h> | |
29 | #include <linux/kernel.h> | |
30 | #include <linux/kthread.h> | |
31 | #include <linux/module.h> | |
32 | #include <linux/platform_device.h> | |
33 | #include <linux/pm_runtime.h> | |
34 | #include <linux/of.h> | |
35 | #include <linux/of_device.h> | |
ff2251e3 | 36 | #include <linux/reset.h> |
dc4dc360 | 37 | #include <linux/spi/spi.h> |
dc4dc360 LD |
38 | |
39 | #define SLINK_COMMAND 0x000 | |
40 | #define SLINK_BIT_LENGTH(x) (((x) & 0x1f) << 0) | |
41 | #define SLINK_WORD_SIZE(x) (((x) & 0x1f) << 5) | |
42 | #define SLINK_BOTH_EN (1 << 10) | |
43 | #define SLINK_CS_SW (1 << 11) | |
44 | #define SLINK_CS_VALUE (1 << 12) | |
45 | #define SLINK_CS_POLARITY (1 << 13) | |
46 | #define SLINK_IDLE_SDA_DRIVE_LOW (0 << 16) | |
47 | #define SLINK_IDLE_SDA_DRIVE_HIGH (1 << 16) | |
48 | #define SLINK_IDLE_SDA_PULL_LOW (2 << 16) | |
49 | #define SLINK_IDLE_SDA_PULL_HIGH (3 << 16) | |
50 | #define SLINK_IDLE_SDA_MASK (3 << 16) | |
51 | #define SLINK_CS_POLARITY1 (1 << 20) | |
52 | #define SLINK_CK_SDA (1 << 21) | |
53 | #define SLINK_CS_POLARITY2 (1 << 22) | |
54 | #define SLINK_CS_POLARITY3 (1 << 23) | |
55 | #define SLINK_IDLE_SCLK_DRIVE_LOW (0 << 24) | |
56 | #define SLINK_IDLE_SCLK_DRIVE_HIGH (1 << 24) | |
57 | #define SLINK_IDLE_SCLK_PULL_LOW (2 << 24) | |
58 | #define SLINK_IDLE_SCLK_PULL_HIGH (3 << 24) | |
59 | #define SLINK_IDLE_SCLK_MASK (3 << 24) | |
60 | #define SLINK_M_S (1 << 28) | |
61 | #define SLINK_WAIT (1 << 29) | |
62 | #define SLINK_GO (1 << 30) | |
63 | #define SLINK_ENB (1 << 31) | |
64 | ||
65 | #define SLINK_MODES (SLINK_IDLE_SCLK_MASK | SLINK_CK_SDA) | |
66 | ||
67 | #define SLINK_COMMAND2 0x004 | |
68 | #define SLINK_LSBFE (1 << 0) | |
69 | #define SLINK_SSOE (1 << 1) | |
70 | #define SLINK_SPIE (1 << 4) | |
71 | #define SLINK_BIDIROE (1 << 6) | |
72 | #define SLINK_MODFEN (1 << 7) | |
73 | #define SLINK_INT_SIZE(x) (((x) & 0x1f) << 8) | |
74 | #define SLINK_CS_ACTIVE_BETWEEN (1 << 17) | |
75 | #define SLINK_SS_EN_CS(x) (((x) & 0x3) << 18) | |
76 | #define SLINK_SS_SETUP(x) (((x) & 0x3) << 20) | |
77 | #define SLINK_FIFO_REFILLS_0 (0 << 22) | |
78 | #define SLINK_FIFO_REFILLS_1 (1 << 22) | |
79 | #define SLINK_FIFO_REFILLS_2 (2 << 22) | |
80 | #define SLINK_FIFO_REFILLS_3 (3 << 22) | |
81 | #define SLINK_FIFO_REFILLS_MASK (3 << 22) | |
82 | #define SLINK_WAIT_PACK_INT(x) (((x) & 0x7) << 26) | |
83 | #define SLINK_SPC0 (1 << 29) | |
84 | #define SLINK_TXEN (1 << 30) | |
85 | #define SLINK_RXEN (1 << 31) | |
86 | ||
87 | #define SLINK_STATUS 0x008 | |
88 | #define SLINK_COUNT(val) (((val) >> 0) & 0x1f) | |
89 | #define SLINK_WORD(val) (((val) >> 5) & 0x1f) | |
90 | #define SLINK_BLK_CNT(val) (((val) >> 0) & 0xffff) | |
91 | #define SLINK_MODF (1 << 16) | |
92 | #define SLINK_RX_UNF (1 << 18) | |
93 | #define SLINK_TX_OVF (1 << 19) | |
94 | #define SLINK_TX_FULL (1 << 20) | |
95 | #define SLINK_TX_EMPTY (1 << 21) | |
96 | #define SLINK_RX_FULL (1 << 22) | |
97 | #define SLINK_RX_EMPTY (1 << 23) | |
98 | #define SLINK_TX_UNF (1 << 24) | |
99 | #define SLINK_RX_OVF (1 << 25) | |
100 | #define SLINK_TX_FLUSH (1 << 26) | |
101 | #define SLINK_RX_FLUSH (1 << 27) | |
102 | #define SLINK_SCLK (1 << 28) | |
103 | #define SLINK_ERR (1 << 29) | |
104 | #define SLINK_RDY (1 << 30) | |
105 | #define SLINK_BSY (1 << 31) | |
106 | #define SLINK_FIFO_ERROR (SLINK_TX_OVF | SLINK_RX_UNF | \ | |
107 | SLINK_TX_UNF | SLINK_RX_OVF) | |
108 | ||
109 | #define SLINK_FIFO_EMPTY (SLINK_TX_EMPTY | SLINK_RX_EMPTY) | |
110 | ||
111 | #define SLINK_MAS_DATA 0x010 | |
112 | #define SLINK_SLAVE_DATA 0x014 | |
113 | ||
114 | #define SLINK_DMA_CTL 0x018 | |
115 | #define SLINK_DMA_BLOCK_SIZE(x) (((x) & 0xffff) << 0) | |
116 | #define SLINK_TX_TRIG_1 (0 << 16) | |
117 | #define SLINK_TX_TRIG_4 (1 << 16) | |
118 | #define SLINK_TX_TRIG_8 (2 << 16) | |
119 | #define SLINK_TX_TRIG_16 (3 << 16) | |
120 | #define SLINK_TX_TRIG_MASK (3 << 16) | |
121 | #define SLINK_RX_TRIG_1 (0 << 18) | |
122 | #define SLINK_RX_TRIG_4 (1 << 18) | |
123 | #define SLINK_RX_TRIG_8 (2 << 18) | |
124 | #define SLINK_RX_TRIG_16 (3 << 18) | |
125 | #define SLINK_RX_TRIG_MASK (3 << 18) | |
126 | #define SLINK_PACKED (1 << 20) | |
127 | #define SLINK_PACK_SIZE_4 (0 << 21) | |
128 | #define SLINK_PACK_SIZE_8 (1 << 21) | |
129 | #define SLINK_PACK_SIZE_16 (2 << 21) | |
130 | #define SLINK_PACK_SIZE_32 (3 << 21) | |
131 | #define SLINK_PACK_SIZE_MASK (3 << 21) | |
132 | #define SLINK_IE_TXC (1 << 26) | |
133 | #define SLINK_IE_RXC (1 << 27) | |
134 | #define SLINK_DMA_EN (1 << 31) | |
135 | ||
136 | #define SLINK_STATUS2 0x01c | |
137 | #define SLINK_TX_FIFO_EMPTY_COUNT(val) (((val) & 0x3f) >> 0) | |
138 | #define SLINK_RX_FIFO_FULL_COUNT(val) (((val) & 0x3f0000) >> 16) | |
139 | #define SLINK_SS_HOLD_TIME(val) (((val) & 0xF) << 6) | |
140 | ||
141 | #define SLINK_TX_FIFO 0x100 | |
142 | #define SLINK_RX_FIFO 0x180 | |
143 | ||
144 | #define DATA_DIR_TX (1 << 0) | |
145 | #define DATA_DIR_RX (1 << 1) | |
146 | ||
147 | #define SLINK_DMA_TIMEOUT (msecs_to_jiffies(1000)) | |
148 | ||
149 | #define DEFAULT_SPI_DMA_BUF_LEN (16*1024) | |
150 | #define TX_FIFO_EMPTY_COUNT_MAX SLINK_TX_FIFO_EMPTY_COUNT(0x20) | |
151 | #define RX_FIFO_FULL_COUNT_ZERO SLINK_RX_FIFO_FULL_COUNT(0) | |
152 | ||
153 | #define SLINK_STATUS2_RESET \ | |
154 | (TX_FIFO_EMPTY_COUNT_MAX | RX_FIFO_FULL_COUNT_ZERO << 16) | |
155 | ||
156 | #define MAX_CHIP_SELECT 4 | |
157 | #define SLINK_FIFO_DEPTH 32 | |
158 | ||
159 | struct tegra_slink_chip_data { | |
160 | bool cs_hold_time; | |
161 | }; | |
162 | ||
163 | struct tegra_slink_data { | |
164 | struct device *dev; | |
165 | struct spi_master *master; | |
166 | const struct tegra_slink_chip_data *chip_data; | |
167 | spinlock_t lock; | |
168 | ||
169 | struct clk *clk; | |
ff2251e3 | 170 | struct reset_control *rst; |
dc4dc360 LD |
171 | void __iomem *base; |
172 | phys_addr_t phys; | |
173 | unsigned irq; | |
dc4dc360 LD |
174 | u32 spi_max_frequency; |
175 | u32 cur_speed; | |
176 | ||
177 | struct spi_device *cur_spi; | |
178 | unsigned cur_pos; | |
179 | unsigned cur_len; | |
180 | unsigned words_per_32bit; | |
181 | unsigned bytes_per_word; | |
182 | unsigned curr_dma_words; | |
183 | unsigned cur_direction; | |
184 | ||
185 | unsigned cur_rx_pos; | |
186 | unsigned cur_tx_pos; | |
187 | ||
188 | unsigned dma_buf_size; | |
189 | unsigned max_buf_size; | |
190 | bool is_curr_dma_xfer; | |
dc4dc360 LD |
191 | |
192 | struct completion rx_dma_complete; | |
193 | struct completion tx_dma_complete; | |
194 | ||
195 | u32 tx_status; | |
196 | u32 rx_status; | |
197 | u32 status_reg; | |
198 | bool is_packed; | |
5fd38677 | 199 | u32 packed_size; |
dc4dc360 LD |
200 | |
201 | u32 command_reg; | |
202 | u32 command2_reg; | |
203 | u32 dma_control_reg; | |
204 | u32 def_command_reg; | |
205 | u32 def_command2_reg; | |
206 | ||
207 | struct completion xfer_completion; | |
208 | struct spi_transfer *curr_xfer; | |
209 | struct dma_chan *rx_dma_chan; | |
210 | u32 *rx_dma_buf; | |
211 | dma_addr_t rx_dma_phys; | |
212 | struct dma_async_tx_descriptor *rx_dma_desc; | |
213 | ||
214 | struct dma_chan *tx_dma_chan; | |
215 | u32 *tx_dma_buf; | |
216 | dma_addr_t tx_dma_phys; | |
217 | struct dma_async_tx_descriptor *tx_dma_desc; | |
218 | }; | |
219 | ||
220 | static int tegra_slink_runtime_suspend(struct device *dev); | |
221 | static int tegra_slink_runtime_resume(struct device *dev); | |
222 | ||
5fd38677 | 223 | static inline u32 tegra_slink_readl(struct tegra_slink_data *tspi, |
dc4dc360 LD |
224 | unsigned long reg) |
225 | { | |
226 | return readl(tspi->base + reg); | |
227 | } | |
228 | ||
229 | static inline void tegra_slink_writel(struct tegra_slink_data *tspi, | |
5fd38677 | 230 | u32 val, unsigned long reg) |
dc4dc360 LD |
231 | { |
232 | writel(val, tspi->base + reg); | |
233 | ||
234 | /* Read back register to make sure that register writes completed */ | |
235 | if (reg != SLINK_TX_FIFO) | |
236 | readl(tspi->base + SLINK_MAS_DATA); | |
237 | } | |
238 | ||
239 | static void tegra_slink_clear_status(struct tegra_slink_data *tspi) | |
240 | { | |
5fd38677 | 241 | u32 val_write; |
dc4dc360 | 242 | |
5fd38677 | 243 | tegra_slink_readl(tspi, SLINK_STATUS); |
dc4dc360 LD |
244 | |
245 | /* Write 1 to clear status register */ | |
246 | val_write = SLINK_RDY | SLINK_FIFO_ERROR; | |
247 | tegra_slink_writel(tspi, val_write, SLINK_STATUS); | |
248 | } | |
249 | ||
5fd38677 | 250 | static u32 tegra_slink_get_packed_size(struct tegra_slink_data *tspi, |
dc4dc360 LD |
251 | struct spi_transfer *t) |
252 | { | |
dc4dc360 LD |
253 | switch (tspi->bytes_per_word) { |
254 | case 0: | |
5fd38677 | 255 | return SLINK_PACK_SIZE_4; |
dc4dc360 | 256 | case 1: |
5fd38677 | 257 | return SLINK_PACK_SIZE_8; |
dc4dc360 | 258 | case 2: |
5fd38677 | 259 | return SLINK_PACK_SIZE_16; |
dc4dc360 | 260 | case 4: |
5fd38677 | 261 | return SLINK_PACK_SIZE_32; |
dc4dc360 | 262 | default: |
5fd38677 | 263 | return 0; |
dc4dc360 | 264 | } |
dc4dc360 LD |
265 | } |
266 | ||
267 | static unsigned tegra_slink_calculate_curr_xfer_param( | |
268 | struct spi_device *spi, struct tegra_slink_data *tspi, | |
269 | struct spi_transfer *t) | |
270 | { | |
271 | unsigned remain_len = t->len - tspi->cur_pos; | |
272 | unsigned max_word; | |
3cb7b407 | 273 | unsigned bits_per_word; |
dc4dc360 LD |
274 | unsigned max_len; |
275 | unsigned total_fifo_words; | |
276 | ||
766ed704 | 277 | bits_per_word = t->bits_per_word; |
e91d2352 | 278 | tspi->bytes_per_word = DIV_ROUND_UP(bits_per_word, 8); |
dc4dc360 LD |
279 | |
280 | if (bits_per_word == 8 || bits_per_word == 16) { | |
281 | tspi->is_packed = 1; | |
282 | tspi->words_per_32bit = 32/bits_per_word; | |
283 | } else { | |
284 | tspi->is_packed = 0; | |
285 | tspi->words_per_32bit = 1; | |
286 | } | |
287 | tspi->packed_size = tegra_slink_get_packed_size(tspi, t); | |
288 | ||
289 | if (tspi->is_packed) { | |
290 | max_len = min(remain_len, tspi->max_buf_size); | |
291 | tspi->curr_dma_words = max_len/tspi->bytes_per_word; | |
292 | total_fifo_words = max_len/4; | |
293 | } else { | |
294 | max_word = (remain_len - 1) / tspi->bytes_per_word + 1; | |
295 | max_word = min(max_word, tspi->max_buf_size/4); | |
296 | tspi->curr_dma_words = max_word; | |
297 | total_fifo_words = max_word; | |
298 | } | |
299 | return total_fifo_words; | |
300 | } | |
301 | ||
302 | static unsigned tegra_slink_fill_tx_fifo_from_client_txbuf( | |
303 | struct tegra_slink_data *tspi, struct spi_transfer *t) | |
304 | { | |
305 | unsigned nbytes; | |
306 | unsigned tx_empty_count; | |
5fd38677 | 307 | u32 fifo_status; |
dc4dc360 LD |
308 | unsigned max_n_32bit; |
309 | unsigned i, count; | |
dc4dc360 LD |
310 | unsigned int written_words; |
311 | unsigned fifo_words_left; | |
312 | u8 *tx_buf = (u8 *)t->tx_buf + tspi->cur_tx_pos; | |
313 | ||
314 | fifo_status = tegra_slink_readl(tspi, SLINK_STATUS2); | |
315 | tx_empty_count = SLINK_TX_FIFO_EMPTY_COUNT(fifo_status); | |
316 | ||
317 | if (tspi->is_packed) { | |
318 | fifo_words_left = tx_empty_count * tspi->words_per_32bit; | |
319 | written_words = min(fifo_words_left, tspi->curr_dma_words); | |
320 | nbytes = written_words * tspi->bytes_per_word; | |
321 | max_n_32bit = DIV_ROUND_UP(nbytes, 4); | |
322 | for (count = 0; count < max_n_32bit; count++) { | |
5fd38677 | 323 | u32 x = 0; |
dc4dc360 | 324 | for (i = 0; (i < 4) && nbytes; i++, nbytes--) |
5fd38677 | 325 | x |= (u32)(*tx_buf++) << (i * 8); |
dc4dc360 LD |
326 | tegra_slink_writel(tspi, x, SLINK_TX_FIFO); |
327 | } | |
328 | } else { | |
329 | max_n_32bit = min(tspi->curr_dma_words, tx_empty_count); | |
330 | written_words = max_n_32bit; | |
331 | nbytes = written_words * tspi->bytes_per_word; | |
332 | for (count = 0; count < max_n_32bit; count++) { | |
5fd38677 | 333 | u32 x = 0; |
dc4dc360 LD |
334 | for (i = 0; nbytes && (i < tspi->bytes_per_word); |
335 | i++, nbytes--) | |
5fd38677 | 336 | x |= (u32)(*tx_buf++) << (i * 8); |
dc4dc360 LD |
337 | tegra_slink_writel(tspi, x, SLINK_TX_FIFO); |
338 | } | |
339 | } | |
340 | tspi->cur_tx_pos += written_words * tspi->bytes_per_word; | |
341 | return written_words; | |
342 | } | |
343 | ||
344 | static unsigned int tegra_slink_read_rx_fifo_to_client_rxbuf( | |
345 | struct tegra_slink_data *tspi, struct spi_transfer *t) | |
346 | { | |
347 | unsigned rx_full_count; | |
5fd38677 | 348 | u32 fifo_status; |
dc4dc360 | 349 | unsigned i, count; |
dc4dc360 LD |
350 | unsigned int read_words = 0; |
351 | unsigned len; | |
352 | u8 *rx_buf = (u8 *)t->rx_buf + tspi->cur_rx_pos; | |
353 | ||
354 | fifo_status = tegra_slink_readl(tspi, SLINK_STATUS2); | |
355 | rx_full_count = SLINK_RX_FIFO_FULL_COUNT(fifo_status); | |
356 | if (tspi->is_packed) { | |
357 | len = tspi->curr_dma_words * tspi->bytes_per_word; | |
358 | for (count = 0; count < rx_full_count; count++) { | |
5fd38677 | 359 | u32 x = tegra_slink_readl(tspi, SLINK_RX_FIFO); |
dc4dc360 LD |
360 | for (i = 0; len && (i < 4); i++, len--) |
361 | *rx_buf++ = (x >> i*8) & 0xFF; | |
362 | } | |
363 | tspi->cur_rx_pos += tspi->curr_dma_words * tspi->bytes_per_word; | |
364 | read_words += tspi->curr_dma_words; | |
365 | } else { | |
dc4dc360 | 366 | for (count = 0; count < rx_full_count; count++) { |
5fd38677 | 367 | u32 x = tegra_slink_readl(tspi, SLINK_RX_FIFO); |
dc4dc360 LD |
368 | for (i = 0; (i < tspi->bytes_per_word); i++) |
369 | *rx_buf++ = (x >> (i*8)) & 0xFF; | |
370 | } | |
371 | tspi->cur_rx_pos += rx_full_count * tspi->bytes_per_word; | |
372 | read_words += rx_full_count; | |
373 | } | |
374 | return read_words; | |
375 | } | |
376 | ||
377 | static void tegra_slink_copy_client_txbuf_to_spi_txbuf( | |
378 | struct tegra_slink_data *tspi, struct spi_transfer *t) | |
379 | { | |
dc4dc360 LD |
380 | /* Make the dma buffer to read by cpu */ |
381 | dma_sync_single_for_cpu(tspi->dev, tspi->tx_dma_phys, | |
382 | tspi->dma_buf_size, DMA_TO_DEVICE); | |
383 | ||
384 | if (tspi->is_packed) { | |
5fd38677 | 385 | unsigned len = tspi->curr_dma_words * tspi->bytes_per_word; |
dc4dc360 LD |
386 | memcpy(tspi->tx_dma_buf, t->tx_buf + tspi->cur_pos, len); |
387 | } else { | |
388 | unsigned int i; | |
389 | unsigned int count; | |
390 | u8 *tx_buf = (u8 *)t->tx_buf + tspi->cur_tx_pos; | |
391 | unsigned consume = tspi->curr_dma_words * tspi->bytes_per_word; | |
dc4dc360 LD |
392 | |
393 | for (count = 0; count < tspi->curr_dma_words; count++) { | |
5fd38677 | 394 | u32 x = 0; |
dc4dc360 LD |
395 | for (i = 0; consume && (i < tspi->bytes_per_word); |
396 | i++, consume--) | |
5fd38677 | 397 | x |= (u32)(*tx_buf++) << (i * 8); |
dc4dc360 LD |
398 | tspi->tx_dma_buf[count] = x; |
399 | } | |
400 | } | |
401 | tspi->cur_tx_pos += tspi->curr_dma_words * tspi->bytes_per_word; | |
402 | ||
403 | /* Make the dma buffer to read by dma */ | |
404 | dma_sync_single_for_device(tspi->dev, tspi->tx_dma_phys, | |
405 | tspi->dma_buf_size, DMA_TO_DEVICE); | |
406 | } | |
407 | ||
408 | static void tegra_slink_copy_spi_rxbuf_to_client_rxbuf( | |
409 | struct tegra_slink_data *tspi, struct spi_transfer *t) | |
410 | { | |
411 | unsigned len; | |
412 | ||
413 | /* Make the dma buffer to read by cpu */ | |
414 | dma_sync_single_for_cpu(tspi->dev, tspi->rx_dma_phys, | |
415 | tspi->dma_buf_size, DMA_FROM_DEVICE); | |
416 | ||
417 | if (tspi->is_packed) { | |
418 | len = tspi->curr_dma_words * tspi->bytes_per_word; | |
419 | memcpy(t->rx_buf + tspi->cur_rx_pos, tspi->rx_dma_buf, len); | |
420 | } else { | |
421 | unsigned int i; | |
422 | unsigned int count; | |
423 | unsigned char *rx_buf = t->rx_buf + tspi->cur_rx_pos; | |
5fd38677 | 424 | u32 rx_mask = ((u32)1 << t->bits_per_word) - 1; |
dc4dc360 | 425 | |
dc4dc360 | 426 | for (count = 0; count < tspi->curr_dma_words; count++) { |
5fd38677 | 427 | u32 x = tspi->rx_dma_buf[count] & rx_mask; |
dc4dc360 LD |
428 | for (i = 0; (i < tspi->bytes_per_word); i++) |
429 | *rx_buf++ = (x >> (i*8)) & 0xFF; | |
430 | } | |
431 | } | |
432 | tspi->cur_rx_pos += tspi->curr_dma_words * tspi->bytes_per_word; | |
433 | ||
434 | /* Make the dma buffer to read by dma */ | |
435 | dma_sync_single_for_device(tspi->dev, tspi->rx_dma_phys, | |
436 | tspi->dma_buf_size, DMA_FROM_DEVICE); | |
437 | } | |
438 | ||
439 | static void tegra_slink_dma_complete(void *args) | |
440 | { | |
441 | struct completion *dma_complete = args; | |
442 | ||
443 | complete(dma_complete); | |
444 | } | |
445 | ||
446 | static int tegra_slink_start_tx_dma(struct tegra_slink_data *tspi, int len) | |
447 | { | |
16735d02 | 448 | reinit_completion(&tspi->tx_dma_complete); |
dc4dc360 LD |
449 | tspi->tx_dma_desc = dmaengine_prep_slave_single(tspi->tx_dma_chan, |
450 | tspi->tx_dma_phys, len, DMA_MEM_TO_DEV, | |
72919f34 | 451 | DMA_PREP_INTERRUPT | DMA_CTRL_ACK); |
dc4dc360 LD |
452 | if (!tspi->tx_dma_desc) { |
453 | dev_err(tspi->dev, "Not able to get desc for Tx\n"); | |
454 | return -EIO; | |
455 | } | |
456 | ||
457 | tspi->tx_dma_desc->callback = tegra_slink_dma_complete; | |
458 | tspi->tx_dma_desc->callback_param = &tspi->tx_dma_complete; | |
459 | ||
460 | dmaengine_submit(tspi->tx_dma_desc); | |
461 | dma_async_issue_pending(tspi->tx_dma_chan); | |
462 | return 0; | |
463 | } | |
464 | ||
465 | static int tegra_slink_start_rx_dma(struct tegra_slink_data *tspi, int len) | |
466 | { | |
16735d02 | 467 | reinit_completion(&tspi->rx_dma_complete); |
dc4dc360 LD |
468 | tspi->rx_dma_desc = dmaengine_prep_slave_single(tspi->rx_dma_chan, |
469 | tspi->rx_dma_phys, len, DMA_DEV_TO_MEM, | |
72919f34 | 470 | DMA_PREP_INTERRUPT | DMA_CTRL_ACK); |
dc4dc360 LD |
471 | if (!tspi->rx_dma_desc) { |
472 | dev_err(tspi->dev, "Not able to get desc for Rx\n"); | |
473 | return -EIO; | |
474 | } | |
475 | ||
476 | tspi->rx_dma_desc->callback = tegra_slink_dma_complete; | |
477 | tspi->rx_dma_desc->callback_param = &tspi->rx_dma_complete; | |
478 | ||
479 | dmaengine_submit(tspi->rx_dma_desc); | |
480 | dma_async_issue_pending(tspi->rx_dma_chan); | |
481 | return 0; | |
482 | } | |
483 | ||
484 | static int tegra_slink_start_dma_based_transfer( | |
485 | struct tegra_slink_data *tspi, struct spi_transfer *t) | |
486 | { | |
5fd38677 | 487 | u32 val; |
dc4dc360 LD |
488 | unsigned int len; |
489 | int ret = 0; | |
5fd38677 | 490 | u32 status; |
dc4dc360 LD |
491 | |
492 | /* Make sure that Rx and Tx fifo are empty */ | |
493 | status = tegra_slink_readl(tspi, SLINK_STATUS); | |
494 | if ((status & SLINK_FIFO_EMPTY) != SLINK_FIFO_EMPTY) { | |
5fd38677 MN |
495 | dev_err(tspi->dev, "Rx/Tx fifo are not empty status 0x%08x\n", |
496 | (unsigned)status); | |
dc4dc360 LD |
497 | return -EIO; |
498 | } | |
499 | ||
500 | val = SLINK_DMA_BLOCK_SIZE(tspi->curr_dma_words - 1); | |
501 | val |= tspi->packed_size; | |
502 | if (tspi->is_packed) | |
503 | len = DIV_ROUND_UP(tspi->curr_dma_words * tspi->bytes_per_word, | |
504 | 4) * 4; | |
505 | else | |
506 | len = tspi->curr_dma_words * 4; | |
507 | ||
508 | /* Set attention level based on length of transfer */ | |
509 | if (len & 0xF) | |
510 | val |= SLINK_TX_TRIG_1 | SLINK_RX_TRIG_1; | |
511 | else if (((len) >> 4) & 0x1) | |
512 | val |= SLINK_TX_TRIG_4 | SLINK_RX_TRIG_4; | |
513 | else | |
514 | val |= SLINK_TX_TRIG_8 | SLINK_RX_TRIG_8; | |
515 | ||
516 | if (tspi->cur_direction & DATA_DIR_TX) | |
517 | val |= SLINK_IE_TXC; | |
518 | ||
519 | if (tspi->cur_direction & DATA_DIR_RX) | |
520 | val |= SLINK_IE_RXC; | |
521 | ||
522 | tegra_slink_writel(tspi, val, SLINK_DMA_CTL); | |
523 | tspi->dma_control_reg = val; | |
524 | ||
525 | if (tspi->cur_direction & DATA_DIR_TX) { | |
526 | tegra_slink_copy_client_txbuf_to_spi_txbuf(tspi, t); | |
527 | wmb(); | |
528 | ret = tegra_slink_start_tx_dma(tspi, len); | |
529 | if (ret < 0) { | |
530 | dev_err(tspi->dev, | |
531 | "Starting tx dma failed, err %d\n", ret); | |
532 | return ret; | |
533 | } | |
534 | ||
535 | /* Wait for tx fifo to be fill before starting slink */ | |
5fd38677 MN |
536 | status = tegra_slink_readl(tspi, SLINK_STATUS); |
537 | while (!(status & SLINK_TX_FULL)) | |
538 | status = tegra_slink_readl(tspi, SLINK_STATUS); | |
dc4dc360 LD |
539 | } |
540 | ||
541 | if (tspi->cur_direction & DATA_DIR_RX) { | |
542 | /* Make the dma buffer to read by dma */ | |
543 | dma_sync_single_for_device(tspi->dev, tspi->rx_dma_phys, | |
544 | tspi->dma_buf_size, DMA_FROM_DEVICE); | |
545 | ||
546 | ret = tegra_slink_start_rx_dma(tspi, len); | |
547 | if (ret < 0) { | |
548 | dev_err(tspi->dev, | |
549 | "Starting rx dma failed, err %d\n", ret); | |
550 | if (tspi->cur_direction & DATA_DIR_TX) | |
551 | dmaengine_terminate_all(tspi->tx_dma_chan); | |
552 | return ret; | |
553 | } | |
554 | } | |
555 | tspi->is_curr_dma_xfer = true; | |
556 | if (tspi->is_packed) { | |
557 | val |= SLINK_PACKED; | |
558 | tegra_slink_writel(tspi, val, SLINK_DMA_CTL); | |
559 | /* HW need small delay after settign Packed mode */ | |
560 | udelay(1); | |
561 | } | |
562 | tspi->dma_control_reg = val; | |
563 | ||
564 | val |= SLINK_DMA_EN; | |
565 | tegra_slink_writel(tspi, val, SLINK_DMA_CTL); | |
566 | return ret; | |
567 | } | |
568 | ||
569 | static int tegra_slink_start_cpu_based_transfer( | |
570 | struct tegra_slink_data *tspi, struct spi_transfer *t) | |
571 | { | |
5fd38677 | 572 | u32 val; |
dc4dc360 LD |
573 | unsigned cur_words; |
574 | ||
575 | val = tspi->packed_size; | |
576 | if (tspi->cur_direction & DATA_DIR_TX) | |
577 | val |= SLINK_IE_TXC; | |
578 | ||
579 | if (tspi->cur_direction & DATA_DIR_RX) | |
580 | val |= SLINK_IE_RXC; | |
581 | ||
582 | tegra_slink_writel(tspi, val, SLINK_DMA_CTL); | |
583 | tspi->dma_control_reg = val; | |
584 | ||
585 | if (tspi->cur_direction & DATA_DIR_TX) | |
586 | cur_words = tegra_slink_fill_tx_fifo_from_client_txbuf(tspi, t); | |
587 | else | |
588 | cur_words = tspi->curr_dma_words; | |
589 | val |= SLINK_DMA_BLOCK_SIZE(cur_words - 1); | |
590 | tegra_slink_writel(tspi, val, SLINK_DMA_CTL); | |
591 | tspi->dma_control_reg = val; | |
592 | ||
593 | tspi->is_curr_dma_xfer = false; | |
594 | if (tspi->is_packed) { | |
595 | val |= SLINK_PACKED; | |
596 | tegra_slink_writel(tspi, val, SLINK_DMA_CTL); | |
597 | udelay(1); | |
598 | wmb(); | |
599 | } | |
600 | tspi->dma_control_reg = val; | |
601 | val |= SLINK_DMA_EN; | |
602 | tegra_slink_writel(tspi, val, SLINK_DMA_CTL); | |
603 | return 0; | |
604 | } | |
605 | ||
606 | static int tegra_slink_init_dma_param(struct tegra_slink_data *tspi, | |
607 | bool dma_to_memory) | |
608 | { | |
609 | struct dma_chan *dma_chan; | |
610 | u32 *dma_buf; | |
611 | dma_addr_t dma_phys; | |
612 | int ret; | |
613 | struct dma_slave_config dma_sconfig; | |
dc4dc360 | 614 | |
8a0a1af3 DC |
615 | dma_chan = dma_request_slave_channel_reason(tspi->dev, |
616 | dma_to_memory ? "rx" : "tx"); | |
a915d150 SW |
617 | if (IS_ERR(dma_chan)) { |
618 | ret = PTR_ERR(dma_chan); | |
619 | if (ret != -EPROBE_DEFER) | |
620 | dev_err(tspi->dev, | |
621 | "Dma channel is not available: %d\n", ret); | |
622 | return ret; | |
dc4dc360 LD |
623 | } |
624 | ||
625 | dma_buf = dma_alloc_coherent(tspi->dev, tspi->dma_buf_size, | |
626 | &dma_phys, GFP_KERNEL); | |
627 | if (!dma_buf) { | |
628 | dev_err(tspi->dev, " Not able to allocate the dma buffer\n"); | |
629 | dma_release_channel(dma_chan); | |
630 | return -ENOMEM; | |
631 | } | |
632 | ||
dc4dc360 LD |
633 | if (dma_to_memory) { |
634 | dma_sconfig.src_addr = tspi->phys + SLINK_RX_FIFO; | |
635 | dma_sconfig.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; | |
636 | dma_sconfig.src_maxburst = 0; | |
637 | } else { | |
638 | dma_sconfig.dst_addr = tspi->phys + SLINK_TX_FIFO; | |
639 | dma_sconfig.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; | |
640 | dma_sconfig.dst_maxburst = 0; | |
641 | } | |
642 | ||
643 | ret = dmaengine_slave_config(dma_chan, &dma_sconfig); | |
644 | if (ret) | |
645 | goto scrub; | |
646 | if (dma_to_memory) { | |
647 | tspi->rx_dma_chan = dma_chan; | |
648 | tspi->rx_dma_buf = dma_buf; | |
649 | tspi->rx_dma_phys = dma_phys; | |
650 | } else { | |
651 | tspi->tx_dma_chan = dma_chan; | |
652 | tspi->tx_dma_buf = dma_buf; | |
653 | tspi->tx_dma_phys = dma_phys; | |
654 | } | |
655 | return 0; | |
656 | ||
657 | scrub: | |
658 | dma_free_coherent(tspi->dev, tspi->dma_buf_size, dma_buf, dma_phys); | |
659 | dma_release_channel(dma_chan); | |
660 | return ret; | |
661 | } | |
662 | ||
663 | static void tegra_slink_deinit_dma_param(struct tegra_slink_data *tspi, | |
664 | bool dma_to_memory) | |
665 | { | |
666 | u32 *dma_buf; | |
667 | dma_addr_t dma_phys; | |
668 | struct dma_chan *dma_chan; | |
669 | ||
670 | if (dma_to_memory) { | |
671 | dma_buf = tspi->rx_dma_buf; | |
672 | dma_chan = tspi->rx_dma_chan; | |
673 | dma_phys = tspi->rx_dma_phys; | |
674 | tspi->rx_dma_chan = NULL; | |
675 | tspi->rx_dma_buf = NULL; | |
676 | } else { | |
677 | dma_buf = tspi->tx_dma_buf; | |
678 | dma_chan = tspi->tx_dma_chan; | |
679 | dma_phys = tspi->tx_dma_phys; | |
680 | tspi->tx_dma_buf = NULL; | |
681 | tspi->tx_dma_chan = NULL; | |
682 | } | |
683 | if (!dma_chan) | |
684 | return; | |
685 | ||
686 | dma_free_coherent(tspi->dev, tspi->dma_buf_size, dma_buf, dma_phys); | |
687 | dma_release_channel(dma_chan); | |
688 | } | |
689 | ||
690 | static int tegra_slink_start_transfer_one(struct spi_device *spi, | |
f178e3de | 691 | struct spi_transfer *t) |
dc4dc360 LD |
692 | { |
693 | struct tegra_slink_data *tspi = spi_master_get_devdata(spi->master); | |
694 | u32 speed; | |
695 | u8 bits_per_word; | |
696 | unsigned total_fifo_words; | |
697 | int ret; | |
5fd38677 MN |
698 | u32 command; |
699 | u32 command2; | |
dc4dc360 | 700 | |
e6811d1d | 701 | bits_per_word = t->bits_per_word; |
beb96c2a | 702 | speed = t->speed_hz; |
dc4dc360 LD |
703 | if (speed != tspi->cur_speed) { |
704 | clk_set_rate(tspi->clk, speed * 4); | |
705 | tspi->cur_speed = speed; | |
706 | } | |
707 | ||
708 | tspi->cur_spi = spi; | |
709 | tspi->cur_pos = 0; | |
710 | tspi->cur_rx_pos = 0; | |
711 | tspi->cur_tx_pos = 0; | |
712 | tspi->curr_xfer = t; | |
713 | total_fifo_words = tegra_slink_calculate_curr_xfer_param(spi, tspi, t); | |
714 | ||
f178e3de MB |
715 | command = tspi->command_reg; |
716 | command &= ~SLINK_BIT_LENGTH(~0); | |
717 | command |= SLINK_BIT_LENGTH(bits_per_word - 1); | |
dc4dc360 | 718 | |
f178e3de MB |
719 | command2 = tspi->command2_reg; |
720 | command2 &= ~(SLINK_RXEN | SLINK_TXEN); | |
dc4dc360 LD |
721 | |
722 | tegra_slink_writel(tspi, command, SLINK_COMMAND); | |
723 | tspi->command_reg = command; | |
724 | ||
725 | tspi->cur_direction = 0; | |
726 | if (t->rx_buf) { | |
727 | command2 |= SLINK_RXEN; | |
728 | tspi->cur_direction |= DATA_DIR_RX; | |
729 | } | |
730 | if (t->tx_buf) { | |
731 | command2 |= SLINK_TXEN; | |
732 | tspi->cur_direction |= DATA_DIR_TX; | |
733 | } | |
734 | tegra_slink_writel(tspi, command2, SLINK_COMMAND2); | |
735 | tspi->command2_reg = command2; | |
736 | ||
737 | if (total_fifo_words > SLINK_FIFO_DEPTH) | |
738 | ret = tegra_slink_start_dma_based_transfer(tspi, t); | |
739 | else | |
740 | ret = tegra_slink_start_cpu_based_transfer(tspi, t); | |
741 | return ret; | |
742 | } | |
743 | ||
744 | static int tegra_slink_setup(struct spi_device *spi) | |
745 | { | |
5fd38677 | 746 | static const u32 cs_pol_bit[MAX_CHIP_SELECT] = { |
dc4dc360 LD |
747 | SLINK_CS_POLARITY, |
748 | SLINK_CS_POLARITY1, | |
749 | SLINK_CS_POLARITY2, | |
750 | SLINK_CS_POLARITY3, | |
751 | }; | |
752 | ||
5fd38677 MN |
753 | struct tegra_slink_data *tspi = spi_master_get_devdata(spi->master); |
754 | u32 val; | |
755 | unsigned long flags; | |
756 | int ret; | |
757 | ||
dc4dc360 LD |
758 | dev_dbg(&spi->dev, "setup %d bpw, %scpol, %scpha, %dHz\n", |
759 | spi->bits_per_word, | |
760 | spi->mode & SPI_CPOL ? "" : "~", | |
761 | spi->mode & SPI_CPHA ? "" : "~", | |
762 | spi->max_speed_hz); | |
763 | ||
764 | BUG_ON(spi->chip_select >= MAX_CHIP_SELECT); | |
765 | ||
beb96c2a LD |
766 | /* Set speed to the spi max fequency if spi device has not set */ |
767 | spi->max_speed_hz = spi->max_speed_hz ? : tspi->spi_max_frequency; | |
dc4dc360 LD |
768 | ret = pm_runtime_get_sync(tspi->dev); |
769 | if (ret < 0) { | |
770 | dev_err(tspi->dev, "pm runtime failed, e = %d\n", ret); | |
771 | return ret; | |
772 | } | |
773 | ||
774 | spin_lock_irqsave(&tspi->lock, flags); | |
775 | val = tspi->def_command_reg; | |
776 | if (spi->mode & SPI_CS_HIGH) | |
777 | val |= cs_pol_bit[spi->chip_select]; | |
778 | else | |
779 | val &= ~cs_pol_bit[spi->chip_select]; | |
780 | tspi->def_command_reg = val; | |
781 | tegra_slink_writel(tspi, tspi->def_command_reg, SLINK_COMMAND); | |
782 | spin_unlock_irqrestore(&tspi->lock, flags); | |
783 | ||
784 | pm_runtime_put(tspi->dev); | |
785 | return 0; | |
786 | } | |
787 | ||
63fc184c MB |
788 | static int tegra_slink_prepare_message(struct spi_master *master, |
789 | struct spi_message *msg) | |
dc4dc360 | 790 | { |
dc4dc360 | 791 | struct tegra_slink_data *tspi = spi_master_get_devdata(master); |
dc4dc360 | 792 | struct spi_device *spi = msg->spi; |
dc4dc360 | 793 | |
f178e3de | 794 | tegra_slink_clear_status(tspi); |
d558c473 | 795 | |
f178e3de MB |
796 | tspi->command_reg = tspi->def_command_reg; |
797 | tspi->command_reg |= SLINK_CS_SW | SLINK_CS_VALUE; | |
dc4dc360 | 798 | |
f178e3de MB |
799 | tspi->command2_reg = tspi->def_command2_reg; |
800 | tspi->command2_reg |= SLINK_SS_EN_CS(spi->chip_select); | |
801 | ||
802 | tspi->command_reg &= ~SLINK_MODES; | |
803 | if (spi->mode & SPI_CPHA) | |
804 | tspi->command_reg |= SLINK_CK_SDA; | |
805 | ||
806 | if (spi->mode & SPI_CPOL) | |
807 | tspi->command_reg |= SLINK_IDLE_SCLK_DRIVE_HIGH; | |
808 | else | |
809 | tspi->command_reg |= SLINK_IDLE_SCLK_DRIVE_LOW; | |
d558c473 | 810 | |
63fc184c MB |
811 | return 0; |
812 | } | |
dc4dc360 | 813 | |
63fc184c MB |
814 | static int tegra_slink_transfer_one(struct spi_master *master, |
815 | struct spi_device *spi, | |
816 | struct spi_transfer *xfer) | |
817 | { | |
818 | struct tegra_slink_data *tspi = spi_master_get_devdata(master); | |
819 | int ret; | |
820 | ||
16735d02 | 821 | reinit_completion(&tspi->xfer_completion); |
f178e3de | 822 | ret = tegra_slink_start_transfer_one(spi, xfer); |
63fc184c MB |
823 | if (ret < 0) { |
824 | dev_err(tspi->dev, | |
825 | "spi can not start transfer, err %d\n", ret); | |
826 | return ret; | |
dc4dc360 | 827 | } |
f178e3de | 828 | |
63fc184c MB |
829 | ret = wait_for_completion_timeout(&tspi->xfer_completion, |
830 | SLINK_DMA_TIMEOUT); | |
831 | if (WARN_ON(ret == 0)) { | |
832 | dev_err(tspi->dev, | |
833 | "spi trasfer timeout, err %d\n", ret); | |
834 | return -EIO; | |
835 | } | |
836 | ||
837 | if (tspi->tx_status) | |
838 | return tspi->tx_status; | |
839 | if (tspi->rx_status) | |
840 | return tspi->rx_status; | |
841 | ||
842 | return 0; | |
843 | } | |
844 | ||
845 | static int tegra_slink_unprepare_message(struct spi_master *master, | |
846 | struct spi_message *msg) | |
847 | { | |
848 | struct tegra_slink_data *tspi = spi_master_get_devdata(master); | |
849 | ||
dc4dc360 LD |
850 | tegra_slink_writel(tspi, tspi->def_command_reg, SLINK_COMMAND); |
851 | tegra_slink_writel(tspi, tspi->def_command2_reg, SLINK_COMMAND2); | |
63fc184c MB |
852 | |
853 | return 0; | |
dc4dc360 LD |
854 | } |
855 | ||
856 | static irqreturn_t handle_cpu_based_xfer(struct tegra_slink_data *tspi) | |
857 | { | |
858 | struct spi_transfer *t = tspi->curr_xfer; | |
859 | unsigned long flags; | |
860 | ||
861 | spin_lock_irqsave(&tspi->lock, flags); | |
862 | if (tspi->tx_status || tspi->rx_status || | |
863 | (tspi->status_reg & SLINK_BSY)) { | |
864 | dev_err(tspi->dev, | |
865 | "CpuXfer ERROR bit set 0x%x\n", tspi->status_reg); | |
866 | dev_err(tspi->dev, | |
867 | "CpuXfer 0x%08x:0x%08x:0x%08x\n", tspi->command_reg, | |
868 | tspi->command2_reg, tspi->dma_control_reg); | |
ff2251e3 | 869 | reset_control_assert(tspi->rst); |
dc4dc360 | 870 | udelay(2); |
ff2251e3 | 871 | reset_control_deassert(tspi->rst); |
dc4dc360 LD |
872 | complete(&tspi->xfer_completion); |
873 | goto exit; | |
874 | } | |
875 | ||
876 | if (tspi->cur_direction & DATA_DIR_RX) | |
877 | tegra_slink_read_rx_fifo_to_client_rxbuf(tspi, t); | |
878 | ||
879 | if (tspi->cur_direction & DATA_DIR_TX) | |
880 | tspi->cur_pos = tspi->cur_tx_pos; | |
881 | else | |
882 | tspi->cur_pos = tspi->cur_rx_pos; | |
883 | ||
884 | if (tspi->cur_pos == t->len) { | |
885 | complete(&tspi->xfer_completion); | |
886 | goto exit; | |
887 | } | |
888 | ||
889 | tegra_slink_calculate_curr_xfer_param(tspi->cur_spi, tspi, t); | |
890 | tegra_slink_start_cpu_based_transfer(tspi, t); | |
891 | exit: | |
892 | spin_unlock_irqrestore(&tspi->lock, flags); | |
893 | return IRQ_HANDLED; | |
894 | } | |
895 | ||
896 | static irqreturn_t handle_dma_based_xfer(struct tegra_slink_data *tspi) | |
897 | { | |
898 | struct spi_transfer *t = tspi->curr_xfer; | |
899 | long wait_status; | |
900 | int err = 0; | |
901 | unsigned total_fifo_words; | |
902 | unsigned long flags; | |
903 | ||
904 | /* Abort dmas if any error */ | |
905 | if (tspi->cur_direction & DATA_DIR_TX) { | |
906 | if (tspi->tx_status) { | |
907 | dmaengine_terminate_all(tspi->tx_dma_chan); | |
908 | err += 1; | |
909 | } else { | |
910 | wait_status = wait_for_completion_interruptible_timeout( | |
911 | &tspi->tx_dma_complete, SLINK_DMA_TIMEOUT); | |
912 | if (wait_status <= 0) { | |
913 | dmaengine_terminate_all(tspi->tx_dma_chan); | |
914 | dev_err(tspi->dev, "TxDma Xfer failed\n"); | |
915 | err += 1; | |
916 | } | |
917 | } | |
918 | } | |
919 | ||
920 | if (tspi->cur_direction & DATA_DIR_RX) { | |
921 | if (tspi->rx_status) { | |
922 | dmaengine_terminate_all(tspi->rx_dma_chan); | |
923 | err += 2; | |
924 | } else { | |
925 | wait_status = wait_for_completion_interruptible_timeout( | |
926 | &tspi->rx_dma_complete, SLINK_DMA_TIMEOUT); | |
927 | if (wait_status <= 0) { | |
928 | dmaengine_terminate_all(tspi->rx_dma_chan); | |
929 | dev_err(tspi->dev, "RxDma Xfer failed\n"); | |
930 | err += 2; | |
931 | } | |
932 | } | |
933 | } | |
934 | ||
935 | spin_lock_irqsave(&tspi->lock, flags); | |
936 | if (err) { | |
937 | dev_err(tspi->dev, | |
938 | "DmaXfer: ERROR bit set 0x%x\n", tspi->status_reg); | |
939 | dev_err(tspi->dev, | |
940 | "DmaXfer 0x%08x:0x%08x:0x%08x\n", tspi->command_reg, | |
941 | tspi->command2_reg, tspi->dma_control_reg); | |
ff2251e3 | 942 | reset_control_assert(tspi->rst); |
dc4dc360 | 943 | udelay(2); |
ff2251e3 | 944 | reset_control_assert(tspi->rst); |
dc4dc360 LD |
945 | complete(&tspi->xfer_completion); |
946 | spin_unlock_irqrestore(&tspi->lock, flags); | |
947 | return IRQ_HANDLED; | |
948 | } | |
949 | ||
950 | if (tspi->cur_direction & DATA_DIR_RX) | |
951 | tegra_slink_copy_spi_rxbuf_to_client_rxbuf(tspi, t); | |
952 | ||
953 | if (tspi->cur_direction & DATA_DIR_TX) | |
954 | tspi->cur_pos = tspi->cur_tx_pos; | |
955 | else | |
956 | tspi->cur_pos = tspi->cur_rx_pos; | |
957 | ||
958 | if (tspi->cur_pos == t->len) { | |
959 | complete(&tspi->xfer_completion); | |
960 | goto exit; | |
961 | } | |
962 | ||
963 | /* Continue transfer in current message */ | |
964 | total_fifo_words = tegra_slink_calculate_curr_xfer_param(tspi->cur_spi, | |
965 | tspi, t); | |
966 | if (total_fifo_words > SLINK_FIFO_DEPTH) | |
967 | err = tegra_slink_start_dma_based_transfer(tspi, t); | |
968 | else | |
969 | err = tegra_slink_start_cpu_based_transfer(tspi, t); | |
970 | ||
971 | exit: | |
972 | spin_unlock_irqrestore(&tspi->lock, flags); | |
973 | return IRQ_HANDLED; | |
974 | } | |
975 | ||
976 | static irqreturn_t tegra_slink_isr_thread(int irq, void *context_data) | |
977 | { | |
978 | struct tegra_slink_data *tspi = context_data; | |
979 | ||
980 | if (!tspi->is_curr_dma_xfer) | |
981 | return handle_cpu_based_xfer(tspi); | |
982 | return handle_dma_based_xfer(tspi); | |
983 | } | |
984 | ||
985 | static irqreturn_t tegra_slink_isr(int irq, void *context_data) | |
986 | { | |
987 | struct tegra_slink_data *tspi = context_data; | |
988 | ||
989 | tspi->status_reg = tegra_slink_readl(tspi, SLINK_STATUS); | |
990 | if (tspi->cur_direction & DATA_DIR_TX) | |
991 | tspi->tx_status = tspi->status_reg & | |
992 | (SLINK_TX_OVF | SLINK_TX_UNF); | |
993 | ||
994 | if (tspi->cur_direction & DATA_DIR_RX) | |
995 | tspi->rx_status = tspi->status_reg & | |
996 | (SLINK_RX_OVF | SLINK_RX_UNF); | |
997 | tegra_slink_clear_status(tspi); | |
998 | ||
999 | return IRQ_WAKE_THREAD; | |
1000 | } | |
1001 | ||
c60fea02 | 1002 | static void tegra_slink_parse_dt(struct tegra_slink_data *tspi) |
dc4dc360 | 1003 | { |
c60fea02 | 1004 | struct device_node *np = tspi->dev->of_node; |
dc4dc360 | 1005 | |
c60fea02 SW |
1006 | if (of_property_read_u32(np, "spi-max-frequency", |
1007 | &tspi->spi_max_frequency)) | |
1008 | tspi->spi_max_frequency = 25000000; /* 25MHz */ | |
dc4dc360 LD |
1009 | } |
1010 | ||
8b0bebe2 | 1011 | static const struct tegra_slink_chip_data tegra30_spi_cdata = { |
dc4dc360 LD |
1012 | .cs_hold_time = true, |
1013 | }; | |
1014 | ||
8b0bebe2 | 1015 | static const struct tegra_slink_chip_data tegra20_spi_cdata = { |
dc4dc360 LD |
1016 | .cs_hold_time = false, |
1017 | }; | |
1018 | ||
fd4a319b | 1019 | static struct of_device_id tegra_slink_of_match[] = { |
dc4dc360 | 1020 | { .compatible = "nvidia,tegra30-slink", .data = &tegra30_spi_cdata, }, |
24bc8971 | 1021 | { .compatible = "nvidia,tegra20-slink", .data = &tegra20_spi_cdata, }, |
dc4dc360 LD |
1022 | {} |
1023 | }; | |
1024 | MODULE_DEVICE_TABLE(of, tegra_slink_of_match); | |
1025 | ||
fd4a319b | 1026 | static int tegra_slink_probe(struct platform_device *pdev) |
dc4dc360 LD |
1027 | { |
1028 | struct spi_master *master; | |
1029 | struct tegra_slink_data *tspi; | |
1030 | struct resource *r; | |
dc4dc360 LD |
1031 | int ret, spi_irq; |
1032 | const struct tegra_slink_chip_data *cdata = NULL; | |
1033 | const struct of_device_id *match; | |
1034 | ||
c60fea02 | 1035 | match = of_match_device(tegra_slink_of_match, &pdev->dev); |
dc4dc360 LD |
1036 | if (!match) { |
1037 | dev_err(&pdev->dev, "Error: No device match found\n"); | |
1038 | return -ENODEV; | |
1039 | } | |
1040 | cdata = match->data; | |
dc4dc360 LD |
1041 | |
1042 | master = spi_alloc_master(&pdev->dev, sizeof(*tspi)); | |
1043 | if (!master) { | |
1044 | dev_err(&pdev->dev, "master allocation failed\n"); | |
1045 | return -ENOMEM; | |
1046 | } | |
1047 | ||
1048 | /* the spi->mode bits understood by this driver: */ | |
1049 | master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH; | |
1050 | master->setup = tegra_slink_setup; | |
63fc184c MB |
1051 | master->prepare_message = tegra_slink_prepare_message; |
1052 | master->transfer_one = tegra_slink_transfer_one; | |
1053 | master->unprepare_message = tegra_slink_unprepare_message; | |
ce74ac80 | 1054 | master->auto_runtime_pm = true; |
dc4dc360 LD |
1055 | master->num_chipselect = MAX_CHIP_SELECT; |
1056 | master->bus_num = -1; | |
1057 | ||
24b5a82c | 1058 | platform_set_drvdata(pdev, master); |
dc4dc360 LD |
1059 | tspi = spi_master_get_devdata(master); |
1060 | tspi->master = master; | |
dc4dc360 LD |
1061 | tspi->dev = &pdev->dev; |
1062 | tspi->chip_data = cdata; | |
1063 | spin_lock_init(&tspi->lock); | |
1064 | ||
c60fea02 SW |
1065 | tegra_slink_parse_dt(tspi); |
1066 | ||
dc4dc360 LD |
1067 | r = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
1068 | if (!r) { | |
1069 | dev_err(&pdev->dev, "No IO memory resource\n"); | |
1070 | ret = -ENODEV; | |
1071 | goto exit_free_master; | |
1072 | } | |
1073 | tspi->phys = r->start; | |
b0ee5605 TR |
1074 | tspi->base = devm_ioremap_resource(&pdev->dev, r); |
1075 | if (IS_ERR(tspi->base)) { | |
1076 | ret = PTR_ERR(tspi->base); | |
dc4dc360 LD |
1077 | goto exit_free_master; |
1078 | } | |
1079 | ||
1080 | spi_irq = platform_get_irq(pdev, 0); | |
1081 | tspi->irq = spi_irq; | |
1082 | ret = request_threaded_irq(tspi->irq, tegra_slink_isr, | |
1083 | tegra_slink_isr_thread, IRQF_ONESHOT, | |
1084 | dev_name(&pdev->dev), tspi); | |
1085 | if (ret < 0) { | |
1086 | dev_err(&pdev->dev, "Failed to register ISR for IRQ %d\n", | |
1087 | tspi->irq); | |
1088 | goto exit_free_master; | |
1089 | } | |
1090 | ||
3cb91902 | 1091 | tspi->clk = devm_clk_get(&pdev->dev, NULL); |
dc4dc360 LD |
1092 | if (IS_ERR(tspi->clk)) { |
1093 | dev_err(&pdev->dev, "can not get clock\n"); | |
1094 | ret = PTR_ERR(tspi->clk); | |
1095 | goto exit_free_irq; | |
1096 | } | |
1097 | ||
ff2251e3 SW |
1098 | tspi->rst = devm_reset_control_get(&pdev->dev, "spi"); |
1099 | if (IS_ERR(tspi->rst)) { | |
1100 | dev_err(&pdev->dev, "can not get reset\n"); | |
1101 | ret = PTR_ERR(tspi->rst); | |
1102 | goto exit_free_irq; | |
1103 | } | |
1104 | ||
dc4dc360 LD |
1105 | tspi->max_buf_size = SLINK_FIFO_DEPTH << 2; |
1106 | tspi->dma_buf_size = DEFAULT_SPI_DMA_BUF_LEN; | |
dc4dc360 | 1107 | |
a915d150 SW |
1108 | ret = tegra_slink_init_dma_param(tspi, true); |
1109 | if (ret < 0) | |
1110 | goto exit_free_irq; | |
1111 | ret = tegra_slink_init_dma_param(tspi, false); | |
1112 | if (ret < 0) | |
1113 | goto exit_rx_dma_free; | |
1114 | tspi->max_buf_size = tspi->dma_buf_size; | |
1115 | init_completion(&tspi->tx_dma_complete); | |
1116 | init_completion(&tspi->rx_dma_complete); | |
dc4dc360 LD |
1117 | |
1118 | init_completion(&tspi->xfer_completion); | |
1119 | ||
1120 | pm_runtime_enable(&pdev->dev); | |
1121 | if (!pm_runtime_enabled(&pdev->dev)) { | |
1122 | ret = tegra_slink_runtime_resume(&pdev->dev); | |
1123 | if (ret) | |
1124 | goto exit_pm_disable; | |
1125 | } | |
1126 | ||
1127 | ret = pm_runtime_get_sync(&pdev->dev); | |
1128 | if (ret < 0) { | |
1129 | dev_err(&pdev->dev, "pm runtime get failed, e = %d\n", ret); | |
1130 | goto exit_pm_disable; | |
1131 | } | |
1132 | tspi->def_command_reg = SLINK_M_S; | |
1133 | tspi->def_command2_reg = SLINK_CS_ACTIVE_BETWEEN; | |
1134 | tegra_slink_writel(tspi, tspi->def_command_reg, SLINK_COMMAND); | |
1135 | tegra_slink_writel(tspi, tspi->def_command2_reg, SLINK_COMMAND2); | |
1136 | pm_runtime_put(&pdev->dev); | |
1137 | ||
1138 | master->dev.of_node = pdev->dev.of_node; | |
716db5d6 | 1139 | ret = devm_spi_register_master(&pdev->dev, master); |
dc4dc360 LD |
1140 | if (ret < 0) { |
1141 | dev_err(&pdev->dev, "can not register to master err %d\n", ret); | |
1142 | goto exit_pm_disable; | |
1143 | } | |
1144 | return ret; | |
1145 | ||
1146 | exit_pm_disable: | |
1147 | pm_runtime_disable(&pdev->dev); | |
1148 | if (!pm_runtime_status_suspended(&pdev->dev)) | |
1149 | tegra_slink_runtime_suspend(&pdev->dev); | |
1150 | tegra_slink_deinit_dma_param(tspi, false); | |
1151 | exit_rx_dma_free: | |
1152 | tegra_slink_deinit_dma_param(tspi, true); | |
1153 | exit_free_irq: | |
1154 | free_irq(spi_irq, tspi); | |
1155 | exit_free_master: | |
1156 | spi_master_put(master); | |
1157 | return ret; | |
1158 | } | |
1159 | ||
fd4a319b | 1160 | static int tegra_slink_remove(struct platform_device *pdev) |
dc4dc360 | 1161 | { |
24b5a82c | 1162 | struct spi_master *master = platform_get_drvdata(pdev); |
dc4dc360 LD |
1163 | struct tegra_slink_data *tspi = spi_master_get_devdata(master); |
1164 | ||
1165 | free_irq(tspi->irq, tspi); | |
dc4dc360 LD |
1166 | |
1167 | if (tspi->tx_dma_chan) | |
1168 | tegra_slink_deinit_dma_param(tspi, false); | |
1169 | ||
1170 | if (tspi->rx_dma_chan) | |
1171 | tegra_slink_deinit_dma_param(tspi, true); | |
1172 | ||
1173 | pm_runtime_disable(&pdev->dev); | |
1174 | if (!pm_runtime_status_suspended(&pdev->dev)) | |
1175 | tegra_slink_runtime_suspend(&pdev->dev); | |
1176 | ||
1177 | return 0; | |
1178 | } | |
1179 | ||
1180 | #ifdef CONFIG_PM_SLEEP | |
1181 | static int tegra_slink_suspend(struct device *dev) | |
1182 | { | |
1183 | struct spi_master *master = dev_get_drvdata(dev); | |
1184 | ||
1185 | return spi_master_suspend(master); | |
1186 | } | |
1187 | ||
1188 | static int tegra_slink_resume(struct device *dev) | |
1189 | { | |
1190 | struct spi_master *master = dev_get_drvdata(dev); | |
1191 | struct tegra_slink_data *tspi = spi_master_get_devdata(master); | |
1192 | int ret; | |
1193 | ||
1194 | ret = pm_runtime_get_sync(dev); | |
1195 | if (ret < 0) { | |
1196 | dev_err(dev, "pm runtime failed, e = %d\n", ret); | |
1197 | return ret; | |
1198 | } | |
1199 | tegra_slink_writel(tspi, tspi->command_reg, SLINK_COMMAND); | |
1200 | tegra_slink_writel(tspi, tspi->command2_reg, SLINK_COMMAND2); | |
1201 | pm_runtime_put(dev); | |
1202 | ||
1203 | return spi_master_resume(master); | |
1204 | } | |
1205 | #endif | |
1206 | ||
1207 | static int tegra_slink_runtime_suspend(struct device *dev) | |
1208 | { | |
1209 | struct spi_master *master = dev_get_drvdata(dev); | |
1210 | struct tegra_slink_data *tspi = spi_master_get_devdata(master); | |
1211 | ||
1212 | /* Flush all write which are in PPSB queue by reading back */ | |
1213 | tegra_slink_readl(tspi, SLINK_MAS_DATA); | |
1214 | ||
1215 | clk_disable_unprepare(tspi->clk); | |
1216 | return 0; | |
1217 | } | |
1218 | ||
1219 | static int tegra_slink_runtime_resume(struct device *dev) | |
1220 | { | |
1221 | struct spi_master *master = dev_get_drvdata(dev); | |
1222 | struct tegra_slink_data *tspi = spi_master_get_devdata(master); | |
1223 | int ret; | |
1224 | ||
1225 | ret = clk_prepare_enable(tspi->clk); | |
1226 | if (ret < 0) { | |
1227 | dev_err(tspi->dev, "clk_prepare failed: %d\n", ret); | |
1228 | return ret; | |
1229 | } | |
1230 | return 0; | |
1231 | } | |
1232 | ||
1233 | static const struct dev_pm_ops slink_pm_ops = { | |
1234 | SET_RUNTIME_PM_OPS(tegra_slink_runtime_suspend, | |
1235 | tegra_slink_runtime_resume, NULL) | |
1236 | SET_SYSTEM_SLEEP_PM_OPS(tegra_slink_suspend, tegra_slink_resume) | |
1237 | }; | |
1238 | static struct platform_driver tegra_slink_driver = { | |
1239 | .driver = { | |
1240 | .name = "spi-tegra-slink", | |
1241 | .owner = THIS_MODULE, | |
1242 | .pm = &slink_pm_ops, | |
c60fea02 | 1243 | .of_match_table = tegra_slink_of_match, |
dc4dc360 LD |
1244 | }, |
1245 | .probe = tegra_slink_probe, | |
fd4a319b | 1246 | .remove = tegra_slink_remove, |
dc4dc360 LD |
1247 | }; |
1248 | module_platform_driver(tegra_slink_driver); | |
1249 | ||
1250 | MODULE_ALIAS("platform:spi-tegra-slink"); | |
1251 | MODULE_DESCRIPTION("NVIDIA Tegra20/Tegra30 SLINK Controller Driver"); | |
1252 | MODULE_AUTHOR("Laxman Dewangan <ldewangan@nvidia.com>"); | |
1253 | MODULE_LICENSE("GPL v2"); |