Commit | Line | Data |
---|---|---|
ae918c02 | 1 | /* |
ae918c02 AK |
2 | * Xilinx SPI controller driver (master mode only) |
3 | * | |
4 | * Author: MontaVista Software, Inc. | |
5 | * source@mvista.com | |
6 | * | |
8fd8821b GL |
7 | * Copyright (c) 2010 Secret Lab Technologies, Ltd. |
8 | * Copyright (c) 2009 Intel Corporation | |
9 | * 2002-2007 (c) MontaVista Software, Inc. | |
10 | ||
11 | * This program is free software; you can redistribute it and/or modify | |
12 | * it under the terms of the GNU General Public License version 2 as | |
13 | * published by the Free Software Foundation. | |
ae918c02 AK |
14 | */ |
15 | ||
16 | #include <linux/module.h> | |
ae918c02 | 17 | #include <linux/interrupt.h> |
eae6cb31 | 18 | #include <linux/of.h> |
8fd8821b | 19 | #include <linux/platform_device.h> |
ae918c02 AK |
20 | #include <linux/spi/spi.h> |
21 | #include <linux/spi/spi_bitbang.h> | |
d5af91a1 | 22 | #include <linux/spi/xilinx_spi.h> |
eae6cb31 | 23 | #include <linux/io.h> |
d5af91a1 | 24 | |
fc3ba952 | 25 | #define XILINX_SPI_NAME "xilinx_spi" |
ae918c02 AK |
26 | |
27 | /* Register definitions as per "OPB Serial Peripheral Interface (SPI) (v1.00e) | |
28 | * Product Specification", DS464 | |
29 | */ | |
c9da2e12 | 30 | #define XSPI_CR_OFFSET 0x60 /* Control Register */ |
ae918c02 | 31 | |
082339bc | 32 | #define XSPI_CR_LOOP 0x01 |
ae918c02 AK |
33 | #define XSPI_CR_ENABLE 0x02 |
34 | #define XSPI_CR_MASTER_MODE 0x04 | |
35 | #define XSPI_CR_CPOL 0x08 | |
36 | #define XSPI_CR_CPHA 0x10 | |
bca690db | 37 | #define XSPI_CR_MODE_MASK (XSPI_CR_CPHA | XSPI_CR_CPOL | \ |
0240f945 | 38 | XSPI_CR_LSB_FIRST | XSPI_CR_LOOP) |
ae918c02 AK |
39 | #define XSPI_CR_TXFIFO_RESET 0x20 |
40 | #define XSPI_CR_RXFIFO_RESET 0x40 | |
41 | #define XSPI_CR_MANUAL_SSELECT 0x80 | |
42 | #define XSPI_CR_TRANS_INHIBIT 0x100 | |
c9da2e12 | 43 | #define XSPI_CR_LSB_FIRST 0x200 |
ae918c02 | 44 | |
c9da2e12 | 45 | #define XSPI_SR_OFFSET 0x64 /* Status Register */ |
ae918c02 AK |
46 | |
47 | #define XSPI_SR_RX_EMPTY_MASK 0x01 /* Receive FIFO is empty */ | |
48 | #define XSPI_SR_RX_FULL_MASK 0x02 /* Receive FIFO is full */ | |
49 | #define XSPI_SR_TX_EMPTY_MASK 0x04 /* Transmit FIFO is empty */ | |
50 | #define XSPI_SR_TX_FULL_MASK 0x08 /* Transmit FIFO is full */ | |
51 | #define XSPI_SR_MODE_FAULT_MASK 0x10 /* Mode fault error */ | |
52 | ||
c9da2e12 RR |
53 | #define XSPI_TXD_OFFSET 0x68 /* Data Transmit Register */ |
54 | #define XSPI_RXD_OFFSET 0x6c /* Data Receive Register */ | |
ae918c02 AK |
55 | |
56 | #define XSPI_SSR_OFFSET 0x70 /* 32-bit Slave Select Register */ | |
57 | ||
58 | /* Register definitions as per "OPB IPIF (v3.01c) Product Specification", DS414 | |
59 | * IPIF registers are 32 bit | |
60 | */ | |
61 | #define XIPIF_V123B_DGIER_OFFSET 0x1c /* IPIF global int enable reg */ | |
62 | #define XIPIF_V123B_GINTR_ENABLE 0x80000000 | |
63 | ||
64 | #define XIPIF_V123B_IISR_OFFSET 0x20 /* IPIF interrupt status reg */ | |
65 | #define XIPIF_V123B_IIER_OFFSET 0x28 /* IPIF interrupt enable reg */ | |
66 | ||
67 | #define XSPI_INTR_MODE_FAULT 0x01 /* Mode fault error */ | |
68 | #define XSPI_INTR_SLAVE_MODE_FAULT 0x02 /* Selected as slave while | |
69 | * disabled */ | |
70 | #define XSPI_INTR_TX_EMPTY 0x04 /* TxFIFO is empty */ | |
71 | #define XSPI_INTR_TX_UNDERRUN 0x08 /* TxFIFO was underrun */ | |
72 | #define XSPI_INTR_RX_FULL 0x10 /* RxFIFO is full */ | |
73 | #define XSPI_INTR_RX_OVERRUN 0x20 /* RxFIFO was overrun */ | |
c9da2e12 | 74 | #define XSPI_INTR_TX_HALF_EMPTY 0x40 /* TxFIFO is half empty */ |
ae918c02 AK |
75 | |
76 | #define XIPIF_V123B_RESETR_OFFSET 0x40 /* IPIF reset register */ | |
77 | #define XIPIF_V123B_RESET_MASK 0x0a /* the value to write */ | |
78 | ||
79 | struct xilinx_spi { | |
80 | /* bitbang has to be first */ | |
81 | struct spi_bitbang bitbang; | |
82 | struct completion done; | |
ae918c02 AK |
83 | void __iomem *regs; /* virt. address of the control registers */ |
84 | ||
9ca1273b | 85 | int irq; |
ae918c02 | 86 | |
ae918c02 AK |
87 | u8 *rx_ptr; /* pointer in the Tx buffer */ |
88 | const u8 *tx_ptr; /* pointer in the Rx buffer */ | |
17aaaa80 | 89 | u8 bytes_per_word; |
4c9a7614 | 90 | int buffer_size; /* buffer size in words */ |
f9c6ef6c | 91 | u32 cs_inactive; /* Level of the CS pins when inactive*/ |
6ff8672a JH |
92 | unsigned int (*read_fn)(void __iomem *); |
93 | void (*write_fn)(u32, void __iomem *); | |
ae918c02 AK |
94 | }; |
95 | ||
24ba5e59 | 96 | static void xilinx_spi_tx(struct xilinx_spi *xspi) |
c9da2e12 | 97 | { |
c3092941 RRD |
98 | if (!xspi->tx_ptr) { |
99 | xspi->write_fn(0, xspi->regs + XSPI_TXD_OFFSET); | |
100 | return; | |
101 | } | |
c9da2e12 | 102 | xspi->write_fn(*(u32 *)(xspi->tx_ptr), xspi->regs + XSPI_TXD_OFFSET); |
17aaaa80 | 103 | xspi->tx_ptr += xspi->bytes_per_word; |
c9da2e12 RR |
104 | } |
105 | ||
24ba5e59 | 106 | static void xilinx_spi_rx(struct xilinx_spi *xspi) |
c9da2e12 RR |
107 | { |
108 | u32 data = xspi->read_fn(xspi->regs + XSPI_RXD_OFFSET); | |
c9da2e12 | 109 | |
24ba5e59 RRD |
110 | if (!xspi->rx_ptr) |
111 | return; | |
c9da2e12 | 112 | |
17aaaa80 RRD |
113 | switch (xspi->bytes_per_word) { |
114 | case 1: | |
24ba5e59 RRD |
115 | *(u8 *)(xspi->rx_ptr) = data; |
116 | break; | |
17aaaa80 | 117 | case 2: |
24ba5e59 RRD |
118 | *(u16 *)(xspi->rx_ptr) = data; |
119 | break; | |
17aaaa80 | 120 | case 4: |
c9da2e12 | 121 | *(u32 *)(xspi->rx_ptr) = data; |
24ba5e59 | 122 | break; |
c9da2e12 | 123 | } |
24ba5e59 | 124 | |
17aaaa80 | 125 | xspi->rx_ptr += xspi->bytes_per_word; |
c9da2e12 RR |
126 | } |
127 | ||
86fc5935 | 128 | static void xspi_init_hw(struct xilinx_spi *xspi) |
ae918c02 | 129 | { |
86fc5935 RR |
130 | void __iomem *regs_base = xspi->regs; |
131 | ||
ae918c02 | 132 | /* Reset the SPI device */ |
86fc5935 RR |
133 | xspi->write_fn(XIPIF_V123B_RESET_MASK, |
134 | regs_base + XIPIF_V123B_RESETR_OFFSET); | |
899929ba RRD |
135 | /* Enable the transmit empty interrupt, which we use to determine |
136 | * progress on the transmission. | |
137 | */ | |
138 | xspi->write_fn(XSPI_INTR_TX_EMPTY, | |
139 | regs_base + XIPIF_V123B_IIER_OFFSET); | |
22417352 RRD |
140 | /* Disable the global IPIF interrupt */ |
141 | xspi->write_fn(0, regs_base + XIPIF_V123B_DGIER_OFFSET); | |
ae918c02 | 142 | /* Deselect the slave on the SPI bus */ |
86fc5935 | 143 | xspi->write_fn(0xffff, regs_base + XSPI_SSR_OFFSET); |
ae918c02 AK |
144 | /* Disable the transmitter, enable Manual Slave Select Assertion, |
145 | * put SPI controller into master mode, and enable it */ | |
22417352 RRD |
146 | xspi->write_fn(XSPI_CR_MANUAL_SSELECT | XSPI_CR_MASTER_MODE | |
147 | XSPI_CR_ENABLE | XSPI_CR_TXFIFO_RESET | XSPI_CR_RXFIFO_RESET, | |
148 | regs_base + XSPI_CR_OFFSET); | |
ae918c02 AK |
149 | } |
150 | ||
151 | static void xilinx_spi_chipselect(struct spi_device *spi, int is_on) | |
152 | { | |
153 | struct xilinx_spi *xspi = spi_master_get_devdata(spi->master); | |
f9c6ef6c RRD |
154 | u16 cr; |
155 | u32 cs; | |
ae918c02 AK |
156 | |
157 | if (is_on == BITBANG_CS_INACTIVE) { | |
158 | /* Deselect the slave on the SPI bus */ | |
f9c6ef6c RRD |
159 | xspi->write_fn(xspi->cs_inactive, xspi->regs + XSPI_SSR_OFFSET); |
160 | return; | |
ae918c02 | 161 | } |
f9c6ef6c RRD |
162 | |
163 | /* Set the SPI clock phase and polarity */ | |
164 | cr = xspi->read_fn(xspi->regs + XSPI_CR_OFFSET) & ~XSPI_CR_MODE_MASK; | |
165 | if (spi->mode & SPI_CPHA) | |
166 | cr |= XSPI_CR_CPHA; | |
167 | if (spi->mode & SPI_CPOL) | |
168 | cr |= XSPI_CR_CPOL; | |
169 | if (spi->mode & SPI_LSB_FIRST) | |
170 | cr |= XSPI_CR_LSB_FIRST; | |
171 | if (spi->mode & SPI_LOOP) | |
172 | cr |= XSPI_CR_LOOP; | |
173 | xspi->write_fn(cr, xspi->regs + XSPI_CR_OFFSET); | |
174 | ||
175 | /* We do not check spi->max_speed_hz here as the SPI clock | |
176 | * frequency is not software programmable (the IP block design | |
177 | * parameter) | |
178 | */ | |
179 | ||
180 | cs = xspi->cs_inactive; | |
181 | cs ^= BIT(spi->chip_select); | |
182 | ||
183 | /* Activate the chip select */ | |
184 | xspi->write_fn(cs, xspi->regs + XSPI_SSR_OFFSET); | |
ae918c02 AK |
185 | } |
186 | ||
187 | /* spi_bitbang requires custom setup_transfer() to be defined if there is a | |
9bf46f6d | 188 | * custom txrx_bufs(). |
ae918c02 AK |
189 | */ |
190 | static int xilinx_spi_setup_transfer(struct spi_device *spi, | |
191 | struct spi_transfer *t) | |
192 | { | |
f9c6ef6c RRD |
193 | struct xilinx_spi *xspi = spi_master_get_devdata(spi->master); |
194 | ||
195 | if (spi->mode & SPI_CS_HIGH) | |
196 | xspi->cs_inactive &= ~BIT(spi->chip_select); | |
197 | else | |
198 | xspi->cs_inactive |= BIT(spi->chip_select); | |
199 | ||
ae918c02 AK |
200 | return 0; |
201 | } | |
202 | ||
ae918c02 AK |
203 | static int xilinx_spi_txrx_bufs(struct spi_device *spi, struct spi_transfer *t) |
204 | { | |
205 | struct xilinx_spi *xspi = spi_master_get_devdata(spi->master); | |
b563bfb8 | 206 | int remaining_words; /* the number of words left to transfer */ |
22417352 RRD |
207 | bool use_irq = false; |
208 | u16 cr = 0; | |
ae918c02 AK |
209 | |
210 | /* We get here with transmitter inhibited */ | |
211 | ||
212 | xspi->tx_ptr = t->tx_buf; | |
213 | xspi->rx_ptr = t->rx_buf; | |
b563bfb8 | 214 | remaining_words = t->len / xspi->bytes_per_word; |
16735d02 | 215 | reinit_completion(&xspi->done); |
ae918c02 | 216 | |
22417352 RRD |
217 | if (xspi->irq >= 0 && remaining_words > xspi->buffer_size) { |
218 | use_irq = true; | |
219 | xspi->write_fn(XSPI_INTR_TX_EMPTY, | |
220 | xspi->regs + XIPIF_V123B_IISR_OFFSET); | |
221 | /* Enable the global IPIF interrupt */ | |
222 | xspi->write_fn(XIPIF_V123B_GINTR_ENABLE, | |
223 | xspi->regs + XIPIF_V123B_DGIER_OFFSET); | |
224 | /* Inhibit irq to avoid spurious irqs on tx_empty*/ | |
225 | cr = xspi->read_fn(xspi->regs + XSPI_CR_OFFSET); | |
226 | xspi->write_fn(cr | XSPI_CR_TRANS_INHIBIT, | |
227 | xspi->regs + XSPI_CR_OFFSET); | |
228 | } | |
229 | ||
b563bfb8 | 230 | while (remaining_words) { |
b563bfb8 | 231 | int n_words, tx_words, rx_words; |
68c315bb | 232 | |
b563bfb8 | 233 | n_words = min(remaining_words, xspi->buffer_size); |
4c9a7614 | 234 | |
b563bfb8 RRD |
235 | tx_words = n_words; |
236 | while (tx_words--) | |
237 | xilinx_spi_tx(xspi); | |
68c315bb PC |
238 | |
239 | /* Start the transfer by not inhibiting the transmitter any | |
240 | * longer | |
241 | */ | |
68c315bb | 242 | |
22417352 | 243 | if (use_irq) { |
d9f58812 | 244 | xspi->write_fn(cr, xspi->regs + XSPI_CR_OFFSET); |
5fe11cc0 | 245 | wait_for_completion(&xspi->done); |
d9f58812 | 246 | } else |
5fe11cc0 RRD |
247 | while (!(xspi->read_fn(xspi->regs + XSPI_SR_OFFSET) & |
248 | XSPI_SR_TX_EMPTY_MASK)) | |
249 | ; | |
68c315bb PC |
250 | |
251 | /* A transmit has just completed. Process received data and | |
252 | * check for more data to transmit. Always inhibit the | |
253 | * transmitter while the Isr refills the transmit register/FIFO, | |
254 | * or make sure it is stopped if we're done. | |
255 | */ | |
22417352 | 256 | if (use_irq) |
d9f58812 | 257 | xspi->write_fn(cr | XSPI_CR_TRANS_INHIBIT, |
68c315bb PC |
258 | xspi->regs + XSPI_CR_OFFSET); |
259 | ||
260 | /* Read out all the data from the Rx FIFO */ | |
b563bfb8 RRD |
261 | rx_words = n_words; |
262 | while (rx_words--) | |
24ba5e59 | 263 | xilinx_spi_rx(xspi); |
b563bfb8 RRD |
264 | |
265 | remaining_words -= n_words; | |
68c315bb | 266 | } |
ae918c02 | 267 | |
22417352 RRD |
268 | if (use_irq) |
269 | xspi->write_fn(0, xspi->regs + XIPIF_V123B_DGIER_OFFSET); | |
270 | ||
d79b2d07 | 271 | return t->len; |
ae918c02 AK |
272 | } |
273 | ||
274 | ||
275 | /* This driver supports single master mode only. Hence Tx FIFO Empty | |
276 | * is the only interrupt we care about. | |
277 | * Receive FIFO Overrun, Transmit FIFO Underrun, Mode Fault, and Slave Mode | |
278 | * Fault are not to happen. | |
279 | */ | |
280 | static irqreturn_t xilinx_spi_irq(int irq, void *dev_id) | |
281 | { | |
282 | struct xilinx_spi *xspi = dev_id; | |
283 | u32 ipif_isr; | |
284 | ||
285 | /* Get the IPIF interrupts, and clear them immediately */ | |
86fc5935 RR |
286 | ipif_isr = xspi->read_fn(xspi->regs + XIPIF_V123B_IISR_OFFSET); |
287 | xspi->write_fn(ipif_isr, xspi->regs + XIPIF_V123B_IISR_OFFSET); | |
ae918c02 AK |
288 | |
289 | if (ipif_isr & XSPI_INTR_TX_EMPTY) { /* Transmission completed */ | |
68c315bb | 290 | complete(&xspi->done); |
ae918c02 AK |
291 | } |
292 | ||
293 | return IRQ_HANDLED; | |
294 | } | |
295 | ||
4c9a7614 RRD |
296 | static int xilinx_spi_find_buffer_size(struct xilinx_spi *xspi) |
297 | { | |
298 | u8 sr; | |
299 | int n_words = 0; | |
300 | ||
301 | /* | |
302 | * Before the buffer_size detection we reset the core | |
303 | * to make sure we start with a clean state. | |
304 | */ | |
305 | xspi->write_fn(XIPIF_V123B_RESET_MASK, | |
306 | xspi->regs + XIPIF_V123B_RESETR_OFFSET); | |
307 | ||
308 | /* Fill the Tx FIFO with as many words as possible */ | |
309 | do { | |
310 | xspi->write_fn(0, xspi->regs + XSPI_TXD_OFFSET); | |
311 | sr = xspi->read_fn(xspi->regs + XSPI_SR_OFFSET); | |
312 | n_words++; | |
313 | } while (!(sr & XSPI_SR_TX_FULL_MASK)); | |
314 | ||
315 | return n_words; | |
316 | } | |
317 | ||
eae6cb31 GL |
318 | static const struct of_device_id xilinx_spi_of_match[] = { |
319 | { .compatible = "xlnx,xps-spi-2.00.a", }, | |
320 | { .compatible = "xlnx,xps-spi-2.00.b", }, | |
321 | {} | |
322 | }; | |
323 | MODULE_DEVICE_TABLE(of, xilinx_spi_of_match); | |
eae6cb31 | 324 | |
7cb2abd0 | 325 | static int xilinx_spi_probe(struct platform_device *pdev) |
ae918c02 | 326 | { |
ae918c02 | 327 | struct xilinx_spi *xspi; |
d81c0bbb | 328 | struct xspi_platform_data *pdata; |
ad3fdbca | 329 | struct resource *res; |
7b3b7432 | 330 | int ret, num_cs = 0, bits_per_word = 8; |
d81c0bbb | 331 | struct spi_master *master; |
082339bc | 332 | u32 tmp; |
d81c0bbb MB |
333 | u8 i; |
334 | ||
8074cf06 | 335 | pdata = dev_get_platdata(&pdev->dev); |
d81c0bbb MB |
336 | if (pdata) { |
337 | num_cs = pdata->num_chipselect; | |
338 | bits_per_word = pdata->bits_per_word; | |
be3acdff MS |
339 | } else { |
340 | of_property_read_u32(pdev->dev.of_node, "xlnx,num-ss-bits", | |
341 | &num_cs); | |
d81c0bbb | 342 | } |
ae918c02 | 343 | |
d81c0bbb | 344 | if (!num_cs) { |
7cb2abd0 MB |
345 | dev_err(&pdev->dev, |
346 | "Missing slave select configuration data\n"); | |
d81c0bbb MB |
347 | return -EINVAL; |
348 | } | |
349 | ||
7cb2abd0 | 350 | master = spi_alloc_master(&pdev->dev, sizeof(struct xilinx_spi)); |
d5af91a1 | 351 | if (!master) |
d81c0bbb | 352 | return -ENODEV; |
ae918c02 | 353 | |
e7db06b5 | 354 | /* the spi->mode bits understood by this driver: */ |
f9c6ef6c RRD |
355 | master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_LSB_FIRST | SPI_LOOP | |
356 | SPI_CS_HIGH; | |
e7db06b5 | 357 | |
ae918c02 | 358 | xspi = spi_master_get_devdata(master); |
f9c6ef6c | 359 | xspi->cs_inactive = 0xffffffff; |
94c69f76 | 360 | xspi->bitbang.master = master; |
ae918c02 AK |
361 | xspi->bitbang.chipselect = xilinx_spi_chipselect; |
362 | xspi->bitbang.setup_transfer = xilinx_spi_setup_transfer; | |
363 | xspi->bitbang.txrx_bufs = xilinx_spi_txrx_bufs; | |
ae918c02 AK |
364 | init_completion(&xspi->done); |
365 | ||
ad3fdbca MS |
366 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
367 | xspi->regs = devm_ioremap_resource(&pdev->dev, res); | |
c40537d0 MB |
368 | if (IS_ERR(xspi->regs)) { |
369 | ret = PTR_ERR(xspi->regs); | |
ae918c02 | 370 | goto put_master; |
ae918c02 AK |
371 | } |
372 | ||
4b153a21 | 373 | master->bus_num = pdev->id; |
91565c40 | 374 | master->num_chipselect = num_cs; |
7cb2abd0 | 375 | master->dev.of_node = pdev->dev.of_node; |
082339bc MS |
376 | |
377 | /* | |
378 | * Detect endianess on the IP via loop bit in CR. Detection | |
379 | * must be done before reset is sent because incorrect reset | |
380 | * value generates error interrupt. | |
381 | * Setup little endian helper functions first and try to use them | |
382 | * and check if bit was correctly setup or not. | |
383 | */ | |
99082eab RRD |
384 | xspi->read_fn = ioread32; |
385 | xspi->write_fn = iowrite32; | |
082339bc MS |
386 | |
387 | xspi->write_fn(XSPI_CR_LOOP, xspi->regs + XSPI_CR_OFFSET); | |
388 | tmp = xspi->read_fn(xspi->regs + XSPI_CR_OFFSET); | |
389 | tmp &= XSPI_CR_LOOP; | |
390 | if (tmp != XSPI_CR_LOOP) { | |
99082eab RRD |
391 | xspi->read_fn = ioread32be; |
392 | xspi->write_fn = iowrite32be; | |
86fc5935 | 393 | } |
082339bc | 394 | |
9bf46f6d | 395 | master->bits_per_word_mask = SPI_BPW_MASK(bits_per_word); |
17aaaa80 | 396 | xspi->bytes_per_word = bits_per_word / 8; |
4c9a7614 RRD |
397 | xspi->buffer_size = xilinx_spi_find_buffer_size(xspi); |
398 | ||
7b3b7432 | 399 | xspi->irq = platform_get_irq(pdev, 0); |
5fe11cc0 RRD |
400 | if (xspi->irq >= 0) { |
401 | /* Register for SPI Interrupt */ | |
402 | ret = devm_request_irq(&pdev->dev, xspi->irq, xilinx_spi_irq, 0, | |
403 | dev_name(&pdev->dev), xspi); | |
404 | if (ret) | |
405 | goto put_master; | |
7b3b7432 MS |
406 | } |
407 | ||
5fe11cc0 RRD |
408 | /* SPI controller initializations */ |
409 | xspi_init_hw(xspi); | |
ae918c02 | 410 | |
d5af91a1 RR |
411 | ret = spi_bitbang_start(&xspi->bitbang); |
412 | if (ret) { | |
7cb2abd0 | 413 | dev_err(&pdev->dev, "spi_bitbang_start FAILED\n"); |
7b3b7432 | 414 | goto put_master; |
eae6cb31 GL |
415 | } |
416 | ||
7cb2abd0 | 417 | dev_info(&pdev->dev, "at 0x%08llX mapped to 0x%p, irq=%d\n", |
ad3fdbca | 418 | (unsigned long long)res->start, xspi->regs, xspi->irq); |
8fd8821b | 419 | |
eae6cb31 GL |
420 | if (pdata) { |
421 | for (i = 0; i < pdata->num_devices; i++) | |
422 | spi_new_device(master, pdata->devices + i); | |
423 | } | |
8fd8821b | 424 | |
7cb2abd0 | 425 | platform_set_drvdata(pdev, master); |
8fd8821b | 426 | return 0; |
ae918c02 | 427 | |
ae918c02 AK |
428 | put_master: |
429 | spi_master_put(master); | |
d81c0bbb MB |
430 | |
431 | return ret; | |
8fd8821b GL |
432 | } |
433 | ||
7cb2abd0 | 434 | static int xilinx_spi_remove(struct platform_device *pdev) |
8fd8821b | 435 | { |
7cb2abd0 | 436 | struct spi_master *master = platform_get_drvdata(pdev); |
d81c0bbb | 437 | struct xilinx_spi *xspi = spi_master_get_devdata(master); |
7b3b7432 | 438 | void __iomem *regs_base = xspi->regs; |
ae918c02 AK |
439 | |
440 | spi_bitbang_stop(&xspi->bitbang); | |
7b3b7432 MS |
441 | |
442 | /* Disable all the interrupts just in case */ | |
443 | xspi->write_fn(0, regs_base + XIPIF_V123B_IIER_OFFSET); | |
444 | /* Disable the global IPIF interrupt */ | |
445 | xspi->write_fn(0, regs_base + XIPIF_V123B_DGIER_OFFSET); | |
ff82c587 | 446 | |
d5af91a1 | 447 | spi_master_put(xspi->bitbang.master); |
8fd8821b GL |
448 | |
449 | return 0; | |
450 | } | |
451 | ||
452 | /* work with hotplug and coldplug */ | |
453 | MODULE_ALIAS("platform:" XILINX_SPI_NAME); | |
454 | ||
455 | static struct platform_driver xilinx_spi_driver = { | |
456 | .probe = xilinx_spi_probe, | |
fd4a319b | 457 | .remove = xilinx_spi_remove, |
8fd8821b GL |
458 | .driver = { |
459 | .name = XILINX_SPI_NAME, | |
eae6cb31 | 460 | .of_match_table = xilinx_spi_of_match, |
8fd8821b GL |
461 | }, |
462 | }; | |
940ab889 | 463 | module_platform_driver(xilinx_spi_driver); |
8fd8821b | 464 | |
ae918c02 AK |
465 | MODULE_AUTHOR("MontaVista Software, Inc. <source@mvista.com>"); |
466 | MODULE_DESCRIPTION("Xilinx SPI driver"); | |
467 | MODULE_LICENSE("GPL"); |