Commit | Line | Data |
---|---|---|
ae918c02 | 1 | /* |
ae918c02 AK |
2 | * Xilinx SPI controller driver (master mode only) |
3 | * | |
4 | * Author: MontaVista Software, Inc. | |
5 | * source@mvista.com | |
6 | * | |
8fd8821b GL |
7 | * Copyright (c) 2010 Secret Lab Technologies, Ltd. |
8 | * Copyright (c) 2009 Intel Corporation | |
9 | * 2002-2007 (c) MontaVista Software, Inc. | |
10 | ||
11 | * This program is free software; you can redistribute it and/or modify | |
12 | * it under the terms of the GNU General Public License version 2 as | |
13 | * published by the Free Software Foundation. | |
ae918c02 AK |
14 | */ |
15 | ||
16 | #include <linux/module.h> | |
ae918c02 | 17 | #include <linux/interrupt.h> |
eae6cb31 | 18 | #include <linux/of.h> |
8fd8821b | 19 | #include <linux/platform_device.h> |
ae918c02 AK |
20 | #include <linux/spi/spi.h> |
21 | #include <linux/spi/spi_bitbang.h> | |
d5af91a1 | 22 | #include <linux/spi/xilinx_spi.h> |
eae6cb31 | 23 | #include <linux/io.h> |
d5af91a1 | 24 | |
fc3ba952 | 25 | #define XILINX_SPI_NAME "xilinx_spi" |
ae918c02 AK |
26 | |
27 | /* Register definitions as per "OPB Serial Peripheral Interface (SPI) (v1.00e) | |
28 | * Product Specification", DS464 | |
29 | */ | |
c9da2e12 | 30 | #define XSPI_CR_OFFSET 0x60 /* Control Register */ |
ae918c02 | 31 | |
082339bc | 32 | #define XSPI_CR_LOOP 0x01 |
ae918c02 AK |
33 | #define XSPI_CR_ENABLE 0x02 |
34 | #define XSPI_CR_MASTER_MODE 0x04 | |
35 | #define XSPI_CR_CPOL 0x08 | |
36 | #define XSPI_CR_CPHA 0x10 | |
37 | #define XSPI_CR_MODE_MASK (XSPI_CR_CPHA | XSPI_CR_CPOL) | |
38 | #define XSPI_CR_TXFIFO_RESET 0x20 | |
39 | #define XSPI_CR_RXFIFO_RESET 0x40 | |
40 | #define XSPI_CR_MANUAL_SSELECT 0x80 | |
41 | #define XSPI_CR_TRANS_INHIBIT 0x100 | |
c9da2e12 | 42 | #define XSPI_CR_LSB_FIRST 0x200 |
ae918c02 | 43 | |
c9da2e12 | 44 | #define XSPI_SR_OFFSET 0x64 /* Status Register */ |
ae918c02 AK |
45 | |
46 | #define XSPI_SR_RX_EMPTY_MASK 0x01 /* Receive FIFO is empty */ | |
47 | #define XSPI_SR_RX_FULL_MASK 0x02 /* Receive FIFO is full */ | |
48 | #define XSPI_SR_TX_EMPTY_MASK 0x04 /* Transmit FIFO is empty */ | |
49 | #define XSPI_SR_TX_FULL_MASK 0x08 /* Transmit FIFO is full */ | |
50 | #define XSPI_SR_MODE_FAULT_MASK 0x10 /* Mode fault error */ | |
51 | ||
c9da2e12 RR |
52 | #define XSPI_TXD_OFFSET 0x68 /* Data Transmit Register */ |
53 | #define XSPI_RXD_OFFSET 0x6c /* Data Receive Register */ | |
ae918c02 AK |
54 | |
55 | #define XSPI_SSR_OFFSET 0x70 /* 32-bit Slave Select Register */ | |
56 | ||
57 | /* Register definitions as per "OPB IPIF (v3.01c) Product Specification", DS414 | |
58 | * IPIF registers are 32 bit | |
59 | */ | |
60 | #define XIPIF_V123B_DGIER_OFFSET 0x1c /* IPIF global int enable reg */ | |
61 | #define XIPIF_V123B_GINTR_ENABLE 0x80000000 | |
62 | ||
63 | #define XIPIF_V123B_IISR_OFFSET 0x20 /* IPIF interrupt status reg */ | |
64 | #define XIPIF_V123B_IIER_OFFSET 0x28 /* IPIF interrupt enable reg */ | |
65 | ||
66 | #define XSPI_INTR_MODE_FAULT 0x01 /* Mode fault error */ | |
67 | #define XSPI_INTR_SLAVE_MODE_FAULT 0x02 /* Selected as slave while | |
68 | * disabled */ | |
69 | #define XSPI_INTR_TX_EMPTY 0x04 /* TxFIFO is empty */ | |
70 | #define XSPI_INTR_TX_UNDERRUN 0x08 /* TxFIFO was underrun */ | |
71 | #define XSPI_INTR_RX_FULL 0x10 /* RxFIFO is full */ | |
72 | #define XSPI_INTR_RX_OVERRUN 0x20 /* RxFIFO was overrun */ | |
c9da2e12 | 73 | #define XSPI_INTR_TX_HALF_EMPTY 0x40 /* TxFIFO is half empty */ |
ae918c02 AK |
74 | |
75 | #define XIPIF_V123B_RESETR_OFFSET 0x40 /* IPIF reset register */ | |
76 | #define XIPIF_V123B_RESET_MASK 0x0a /* the value to write */ | |
77 | ||
78 | struct xilinx_spi { | |
79 | /* bitbang has to be first */ | |
80 | struct spi_bitbang bitbang; | |
81 | struct completion done; | |
ae918c02 AK |
82 | void __iomem *regs; /* virt. address of the control registers */ |
83 | ||
9ca1273b | 84 | int irq; |
ae918c02 | 85 | |
ae918c02 AK |
86 | u8 *rx_ptr; /* pointer in the Tx buffer */ |
87 | const u8 *tx_ptr; /* pointer in the Rx buffer */ | |
88 | int remaining_bytes; /* the number of bytes left to transfer */ | |
c9da2e12 | 89 | u8 bits_per_word; |
6ff8672a JH |
90 | unsigned int (*read_fn)(void __iomem *); |
91 | void (*write_fn)(u32, void __iomem *); | |
92 | void (*tx_fn)(struct xilinx_spi *); | |
93 | void (*rx_fn)(struct xilinx_spi *); | |
ae918c02 AK |
94 | }; |
95 | ||
97782149 PM |
96 | static void xspi_write32(u32 val, void __iomem *addr) |
97 | { | |
98 | iowrite32(val, addr); | |
99 | } | |
100 | ||
101 | static unsigned int xspi_read32(void __iomem *addr) | |
102 | { | |
103 | return ioread32(addr); | |
104 | } | |
105 | ||
106 | static void xspi_write32_be(u32 val, void __iomem *addr) | |
107 | { | |
108 | iowrite32be(val, addr); | |
109 | } | |
110 | ||
111 | static unsigned int xspi_read32_be(void __iomem *addr) | |
112 | { | |
113 | return ioread32be(addr); | |
114 | } | |
115 | ||
c9da2e12 RR |
116 | static void xspi_tx8(struct xilinx_spi *xspi) |
117 | { | |
118 | xspi->write_fn(*xspi->tx_ptr, xspi->regs + XSPI_TXD_OFFSET); | |
119 | xspi->tx_ptr++; | |
120 | } | |
121 | ||
122 | static void xspi_tx16(struct xilinx_spi *xspi) | |
123 | { | |
124 | xspi->write_fn(*(u16 *)(xspi->tx_ptr), xspi->regs + XSPI_TXD_OFFSET); | |
125 | xspi->tx_ptr += 2; | |
126 | } | |
127 | ||
128 | static void xspi_tx32(struct xilinx_spi *xspi) | |
129 | { | |
130 | xspi->write_fn(*(u32 *)(xspi->tx_ptr), xspi->regs + XSPI_TXD_OFFSET); | |
131 | xspi->tx_ptr += 4; | |
132 | } | |
133 | ||
134 | static void xspi_rx8(struct xilinx_spi *xspi) | |
135 | { | |
136 | u32 data = xspi->read_fn(xspi->regs + XSPI_RXD_OFFSET); | |
137 | if (xspi->rx_ptr) { | |
138 | *xspi->rx_ptr = data & 0xff; | |
139 | xspi->rx_ptr++; | |
140 | } | |
141 | } | |
142 | ||
143 | static void xspi_rx16(struct xilinx_spi *xspi) | |
144 | { | |
145 | u32 data = xspi->read_fn(xspi->regs + XSPI_RXD_OFFSET); | |
146 | if (xspi->rx_ptr) { | |
147 | *(u16 *)(xspi->rx_ptr) = data & 0xffff; | |
148 | xspi->rx_ptr += 2; | |
149 | } | |
150 | } | |
151 | ||
152 | static void xspi_rx32(struct xilinx_spi *xspi) | |
153 | { | |
154 | u32 data = xspi->read_fn(xspi->regs + XSPI_RXD_OFFSET); | |
155 | if (xspi->rx_ptr) { | |
156 | *(u32 *)(xspi->rx_ptr) = data; | |
157 | xspi->rx_ptr += 4; | |
158 | } | |
159 | } | |
160 | ||
86fc5935 | 161 | static void xspi_init_hw(struct xilinx_spi *xspi) |
ae918c02 | 162 | { |
86fc5935 RR |
163 | void __iomem *regs_base = xspi->regs; |
164 | ||
ae918c02 | 165 | /* Reset the SPI device */ |
86fc5935 RR |
166 | xspi->write_fn(XIPIF_V123B_RESET_MASK, |
167 | regs_base + XIPIF_V123B_RESETR_OFFSET); | |
ae918c02 | 168 | /* Disable all the interrupts just in case */ |
86fc5935 | 169 | xspi->write_fn(0, regs_base + XIPIF_V123B_IIER_OFFSET); |
ae918c02 | 170 | /* Enable the global IPIF interrupt */ |
86fc5935 RR |
171 | xspi->write_fn(XIPIF_V123B_GINTR_ENABLE, |
172 | regs_base + XIPIF_V123B_DGIER_OFFSET); | |
ae918c02 | 173 | /* Deselect the slave on the SPI bus */ |
86fc5935 | 174 | xspi->write_fn(0xffff, regs_base + XSPI_SSR_OFFSET); |
ae918c02 AK |
175 | /* Disable the transmitter, enable Manual Slave Select Assertion, |
176 | * put SPI controller into master mode, and enable it */ | |
86fc5935 | 177 | xspi->write_fn(XSPI_CR_TRANS_INHIBIT | XSPI_CR_MANUAL_SSELECT | |
c9da2e12 RR |
178 | XSPI_CR_MASTER_MODE | XSPI_CR_ENABLE | XSPI_CR_TXFIFO_RESET | |
179 | XSPI_CR_RXFIFO_RESET, regs_base + XSPI_CR_OFFSET); | |
ae918c02 AK |
180 | } |
181 | ||
182 | static void xilinx_spi_chipselect(struct spi_device *spi, int is_on) | |
183 | { | |
184 | struct xilinx_spi *xspi = spi_master_get_devdata(spi->master); | |
185 | ||
186 | if (is_on == BITBANG_CS_INACTIVE) { | |
187 | /* Deselect the slave on the SPI bus */ | |
86fc5935 | 188 | xspi->write_fn(0xffff, xspi->regs + XSPI_SSR_OFFSET); |
ae918c02 AK |
189 | } else if (is_on == BITBANG_CS_ACTIVE) { |
190 | /* Set the SPI clock phase and polarity */ | |
86fc5935 | 191 | u16 cr = xspi->read_fn(xspi->regs + XSPI_CR_OFFSET) |
ae918c02 AK |
192 | & ~XSPI_CR_MODE_MASK; |
193 | if (spi->mode & SPI_CPHA) | |
194 | cr |= XSPI_CR_CPHA; | |
195 | if (spi->mode & SPI_CPOL) | |
196 | cr |= XSPI_CR_CPOL; | |
86fc5935 | 197 | xspi->write_fn(cr, xspi->regs + XSPI_CR_OFFSET); |
ae918c02 AK |
198 | |
199 | /* We do not check spi->max_speed_hz here as the SPI clock | |
200 | * frequency is not software programmable (the IP block design | |
201 | * parameter) | |
202 | */ | |
203 | ||
204 | /* Activate the chip select */ | |
86fc5935 RR |
205 | xspi->write_fn(~(0x0001 << spi->chip_select), |
206 | xspi->regs + XSPI_SSR_OFFSET); | |
ae918c02 AK |
207 | } |
208 | } | |
209 | ||
210 | /* spi_bitbang requires custom setup_transfer() to be defined if there is a | |
9bf46f6d | 211 | * custom txrx_bufs(). |
ae918c02 AK |
212 | */ |
213 | static int xilinx_spi_setup_transfer(struct spi_device *spi, | |
214 | struct spi_transfer *t) | |
215 | { | |
ae918c02 AK |
216 | return 0; |
217 | } | |
218 | ||
ae918c02 AK |
219 | static void xilinx_spi_fill_tx_fifo(struct xilinx_spi *xspi) |
220 | { | |
221 | u8 sr; | |
222 | ||
223 | /* Fill the Tx FIFO with as many bytes as possible */ | |
86fc5935 | 224 | sr = xspi->read_fn(xspi->regs + XSPI_SR_OFFSET); |
ae918c02 | 225 | while ((sr & XSPI_SR_TX_FULL_MASK) == 0 && xspi->remaining_bytes > 0) { |
86fc5935 | 226 | if (xspi->tx_ptr) |
c9da2e12 | 227 | xspi->tx_fn(xspi); |
86fc5935 RR |
228 | else |
229 | xspi->write_fn(0, xspi->regs + XSPI_TXD_OFFSET); | |
c9da2e12 | 230 | xspi->remaining_bytes -= xspi->bits_per_word / 8; |
86fc5935 | 231 | sr = xspi->read_fn(xspi->regs + XSPI_SR_OFFSET); |
ae918c02 AK |
232 | } |
233 | } | |
234 | ||
235 | static int xilinx_spi_txrx_bufs(struct spi_device *spi, struct spi_transfer *t) | |
236 | { | |
237 | struct xilinx_spi *xspi = spi_master_get_devdata(spi->master); | |
238 | u32 ipif_ier; | |
ae918c02 AK |
239 | |
240 | /* We get here with transmitter inhibited */ | |
241 | ||
242 | xspi->tx_ptr = t->tx_buf; | |
243 | xspi->rx_ptr = t->rx_buf; | |
244 | xspi->remaining_bytes = t->len; | |
16735d02 | 245 | reinit_completion(&xspi->done); |
ae918c02 | 246 | |
ae918c02 AK |
247 | |
248 | /* Enable the transmit empty interrupt, which we use to determine | |
249 | * progress on the transmission. | |
250 | */ | |
86fc5935 RR |
251 | ipif_ier = xspi->read_fn(xspi->regs + XIPIF_V123B_IIER_OFFSET); |
252 | xspi->write_fn(ipif_ier | XSPI_INTR_TX_EMPTY, | |
253 | xspi->regs + XIPIF_V123B_IIER_OFFSET); | |
ae918c02 | 254 | |
68c315bb PC |
255 | for (;;) { |
256 | u16 cr; | |
257 | u8 sr; | |
258 | ||
259 | xilinx_spi_fill_tx_fifo(xspi); | |
260 | ||
261 | /* Start the transfer by not inhibiting the transmitter any | |
262 | * longer | |
263 | */ | |
264 | cr = xspi->read_fn(xspi->regs + XSPI_CR_OFFSET) & | |
265 | ~XSPI_CR_TRANS_INHIBIT; | |
266 | xspi->write_fn(cr, xspi->regs + XSPI_CR_OFFSET); | |
267 | ||
268 | wait_for_completion(&xspi->done); | |
269 | ||
270 | /* A transmit has just completed. Process received data and | |
271 | * check for more data to transmit. Always inhibit the | |
272 | * transmitter while the Isr refills the transmit register/FIFO, | |
273 | * or make sure it is stopped if we're done. | |
274 | */ | |
275 | cr = xspi->read_fn(xspi->regs + XSPI_CR_OFFSET); | |
276 | xspi->write_fn(cr | XSPI_CR_TRANS_INHIBIT, | |
277 | xspi->regs + XSPI_CR_OFFSET); | |
278 | ||
279 | /* Read out all the data from the Rx FIFO */ | |
280 | sr = xspi->read_fn(xspi->regs + XSPI_SR_OFFSET); | |
281 | while ((sr & XSPI_SR_RX_EMPTY_MASK) == 0) { | |
282 | xspi->rx_fn(xspi); | |
283 | sr = xspi->read_fn(xspi->regs + XSPI_SR_OFFSET); | |
284 | } | |
ae918c02 | 285 | |
68c315bb | 286 | /* See if there is more data to send */ |
e33d085d | 287 | if (xspi->remaining_bytes <= 0) |
68c315bb PC |
288 | break; |
289 | } | |
ae918c02 AK |
290 | |
291 | /* Disable the transmit empty interrupt */ | |
86fc5935 | 292 | xspi->write_fn(ipif_ier, xspi->regs + XIPIF_V123B_IIER_OFFSET); |
ae918c02 AK |
293 | |
294 | return t->len - xspi->remaining_bytes; | |
295 | } | |
296 | ||
297 | ||
298 | /* This driver supports single master mode only. Hence Tx FIFO Empty | |
299 | * is the only interrupt we care about. | |
300 | * Receive FIFO Overrun, Transmit FIFO Underrun, Mode Fault, and Slave Mode | |
301 | * Fault are not to happen. | |
302 | */ | |
303 | static irqreturn_t xilinx_spi_irq(int irq, void *dev_id) | |
304 | { | |
305 | struct xilinx_spi *xspi = dev_id; | |
306 | u32 ipif_isr; | |
307 | ||
308 | /* Get the IPIF interrupts, and clear them immediately */ | |
86fc5935 RR |
309 | ipif_isr = xspi->read_fn(xspi->regs + XIPIF_V123B_IISR_OFFSET); |
310 | xspi->write_fn(ipif_isr, xspi->regs + XIPIF_V123B_IISR_OFFSET); | |
ae918c02 AK |
311 | |
312 | if (ipif_isr & XSPI_INTR_TX_EMPTY) { /* Transmission completed */ | |
68c315bb | 313 | complete(&xspi->done); |
ae918c02 AK |
314 | } |
315 | ||
316 | return IRQ_HANDLED; | |
317 | } | |
318 | ||
eae6cb31 GL |
319 | static const struct of_device_id xilinx_spi_of_match[] = { |
320 | { .compatible = "xlnx,xps-spi-2.00.a", }, | |
321 | { .compatible = "xlnx,xps-spi-2.00.b", }, | |
322 | {} | |
323 | }; | |
324 | MODULE_DEVICE_TABLE(of, xilinx_spi_of_match); | |
eae6cb31 | 325 | |
7cb2abd0 | 326 | static int xilinx_spi_probe(struct platform_device *pdev) |
ae918c02 | 327 | { |
ae918c02 | 328 | struct xilinx_spi *xspi; |
d81c0bbb | 329 | struct xspi_platform_data *pdata; |
ad3fdbca | 330 | struct resource *res; |
7b3b7432 | 331 | int ret, num_cs = 0, bits_per_word = 8; |
d81c0bbb | 332 | struct spi_master *master; |
082339bc | 333 | u32 tmp; |
d81c0bbb MB |
334 | u8 i; |
335 | ||
8074cf06 | 336 | pdata = dev_get_platdata(&pdev->dev); |
d81c0bbb MB |
337 | if (pdata) { |
338 | num_cs = pdata->num_chipselect; | |
339 | bits_per_word = pdata->bits_per_word; | |
be3acdff MS |
340 | } else { |
341 | of_property_read_u32(pdev->dev.of_node, "xlnx,num-ss-bits", | |
342 | &num_cs); | |
d81c0bbb | 343 | } |
ae918c02 | 344 | |
d81c0bbb | 345 | if (!num_cs) { |
7cb2abd0 MB |
346 | dev_err(&pdev->dev, |
347 | "Missing slave select configuration data\n"); | |
d81c0bbb MB |
348 | return -EINVAL; |
349 | } | |
350 | ||
7cb2abd0 | 351 | master = spi_alloc_master(&pdev->dev, sizeof(struct xilinx_spi)); |
d5af91a1 | 352 | if (!master) |
d81c0bbb | 353 | return -ENODEV; |
ae918c02 | 354 | |
e7db06b5 DB |
355 | /* the spi->mode bits understood by this driver: */ |
356 | master->mode_bits = SPI_CPOL | SPI_CPHA; | |
357 | ||
ae918c02 | 358 | xspi = spi_master_get_devdata(master); |
94c69f76 | 359 | xspi->bitbang.master = master; |
ae918c02 AK |
360 | xspi->bitbang.chipselect = xilinx_spi_chipselect; |
361 | xspi->bitbang.setup_transfer = xilinx_spi_setup_transfer; | |
362 | xspi->bitbang.txrx_bufs = xilinx_spi_txrx_bufs; | |
ae918c02 AK |
363 | init_completion(&xspi->done); |
364 | ||
ad3fdbca MS |
365 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
366 | xspi->regs = devm_ioremap_resource(&pdev->dev, res); | |
c40537d0 MB |
367 | if (IS_ERR(xspi->regs)) { |
368 | ret = PTR_ERR(xspi->regs); | |
ae918c02 | 369 | goto put_master; |
ae918c02 AK |
370 | } |
371 | ||
4b153a21 | 372 | master->bus_num = pdev->id; |
91565c40 | 373 | master->num_chipselect = num_cs; |
7cb2abd0 | 374 | master->dev.of_node = pdev->dev.of_node; |
082339bc MS |
375 | |
376 | /* | |
377 | * Detect endianess on the IP via loop bit in CR. Detection | |
378 | * must be done before reset is sent because incorrect reset | |
379 | * value generates error interrupt. | |
380 | * Setup little endian helper functions first and try to use them | |
381 | * and check if bit was correctly setup or not. | |
382 | */ | |
383 | xspi->read_fn = xspi_read32; | |
384 | xspi->write_fn = xspi_write32; | |
385 | ||
386 | xspi->write_fn(XSPI_CR_LOOP, xspi->regs + XSPI_CR_OFFSET); | |
387 | tmp = xspi->read_fn(xspi->regs + XSPI_CR_OFFSET); | |
388 | tmp &= XSPI_CR_LOOP; | |
389 | if (tmp != XSPI_CR_LOOP) { | |
97782149 PM |
390 | xspi->read_fn = xspi_read32_be; |
391 | xspi->write_fn = xspi_write32_be; | |
86fc5935 | 392 | } |
082339bc | 393 | |
9bf46f6d | 394 | master->bits_per_word_mask = SPI_BPW_MASK(bits_per_word); |
91565c40 | 395 | xspi->bits_per_word = bits_per_word; |
c9da2e12 RR |
396 | if (xspi->bits_per_word == 8) { |
397 | xspi->tx_fn = xspi_tx8; | |
398 | xspi->rx_fn = xspi_rx8; | |
399 | } else if (xspi->bits_per_word == 16) { | |
400 | xspi->tx_fn = xspi_tx16; | |
401 | xspi->rx_fn = xspi_rx16; | |
402 | } else if (xspi->bits_per_word == 32) { | |
403 | xspi->tx_fn = xspi_tx32; | |
404 | xspi->rx_fn = xspi_rx32; | |
d81c0bbb MB |
405 | } else { |
406 | ret = -EINVAL; | |
c40537d0 | 407 | goto put_master; |
d81c0bbb | 408 | } |
ae918c02 AK |
409 | |
410 | /* SPI controller initializations */ | |
86fc5935 | 411 | xspi_init_hw(xspi); |
ae918c02 | 412 | |
7b3b7432 MS |
413 | xspi->irq = platform_get_irq(pdev, 0); |
414 | if (xspi->irq < 0) { | |
415 | ret = xspi->irq; | |
416 | goto put_master; | |
417 | } | |
418 | ||
ae918c02 | 419 | /* Register for SPI Interrupt */ |
7b3b7432 MS |
420 | ret = devm_request_irq(&pdev->dev, xspi->irq, xilinx_spi_irq, 0, |
421 | dev_name(&pdev->dev), xspi); | |
d5af91a1 | 422 | if (ret) |
c40537d0 | 423 | goto put_master; |
ae918c02 | 424 | |
d5af91a1 RR |
425 | ret = spi_bitbang_start(&xspi->bitbang); |
426 | if (ret) { | |
7cb2abd0 | 427 | dev_err(&pdev->dev, "spi_bitbang_start FAILED\n"); |
7b3b7432 | 428 | goto put_master; |
eae6cb31 GL |
429 | } |
430 | ||
7cb2abd0 | 431 | dev_info(&pdev->dev, "at 0x%08llX mapped to 0x%p, irq=%d\n", |
ad3fdbca | 432 | (unsigned long long)res->start, xspi->regs, xspi->irq); |
8fd8821b | 433 | |
eae6cb31 GL |
434 | if (pdata) { |
435 | for (i = 0; i < pdata->num_devices; i++) | |
436 | spi_new_device(master, pdata->devices + i); | |
437 | } | |
8fd8821b | 438 | |
7cb2abd0 | 439 | platform_set_drvdata(pdev, master); |
8fd8821b | 440 | return 0; |
ae918c02 | 441 | |
ae918c02 AK |
442 | put_master: |
443 | spi_master_put(master); | |
d81c0bbb MB |
444 | |
445 | return ret; | |
8fd8821b GL |
446 | } |
447 | ||
7cb2abd0 | 448 | static int xilinx_spi_remove(struct platform_device *pdev) |
8fd8821b | 449 | { |
7cb2abd0 | 450 | struct spi_master *master = platform_get_drvdata(pdev); |
d81c0bbb | 451 | struct xilinx_spi *xspi = spi_master_get_devdata(master); |
7b3b7432 | 452 | void __iomem *regs_base = xspi->regs; |
ae918c02 AK |
453 | |
454 | spi_bitbang_stop(&xspi->bitbang); | |
7b3b7432 MS |
455 | |
456 | /* Disable all the interrupts just in case */ | |
457 | xspi->write_fn(0, regs_base + XIPIF_V123B_IIER_OFFSET); | |
458 | /* Disable the global IPIF interrupt */ | |
459 | xspi->write_fn(0, regs_base + XIPIF_V123B_DGIER_OFFSET); | |
ff82c587 | 460 | |
d5af91a1 | 461 | spi_master_put(xspi->bitbang.master); |
8fd8821b GL |
462 | |
463 | return 0; | |
464 | } | |
465 | ||
466 | /* work with hotplug and coldplug */ | |
467 | MODULE_ALIAS("platform:" XILINX_SPI_NAME); | |
468 | ||
469 | static struct platform_driver xilinx_spi_driver = { | |
470 | .probe = xilinx_spi_probe, | |
fd4a319b | 471 | .remove = xilinx_spi_remove, |
8fd8821b GL |
472 | .driver = { |
473 | .name = XILINX_SPI_NAME, | |
eae6cb31 | 474 | .of_match_table = xilinx_spi_of_match, |
8fd8821b GL |
475 | }, |
476 | }; | |
940ab889 | 477 | module_platform_driver(xilinx_spi_driver); |
8fd8821b | 478 | |
ae918c02 AK |
479 | MODULE_AUTHOR("MontaVista Software, Inc. <source@mvista.com>"); |
480 | MODULE_DESCRIPTION("Xilinx SPI driver"); | |
481 | MODULE_LICENSE("GPL"); |