Commit | Line | Data |
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a5f6abd4 | 1 | /* |
131b17d4 BW |
2 | * File: drivers/spi/bfin5xx_spi.c |
3 | * Maintainer: | |
4 | * Bryan Wu <bryan.wu@analog.com> | |
5 | * Original Author: | |
6 | * Luke Yang (Analog Devices Inc.) | |
a5f6abd4 | 7 | * |
131b17d4 BW |
8 | * Created: March. 10th 2006 |
9 | * Description: SPI controller driver for Blackfin BF5xx | |
10 | * Bugs: Enter bugs at http://blackfin.uclinux.org/ | |
a5f6abd4 WB |
11 | * |
12 | * Modified: | |
13 | * March 10, 2006 bfin5xx_spi.c Created. (Luke Yang) | |
14 | * August 7, 2006 added full duplex mode (Axel Weiss & Luke Yang) | |
131b17d4 | 15 | * July 17, 2007 add support for BF54x SPI0 controller (Bryan Wu) |
a5f6abd4 | 16 | * |
131b17d4 | 17 | * Copyright 2004-2007 Analog Devices Inc. |
a5f6abd4 WB |
18 | * |
19 | * This program is free software ; you can redistribute it and/or modify | |
20 | * it under the terms of the GNU General Public License as published by | |
21 | * the Free Software Foundation ; either version 2, or (at your option) | |
22 | * any later version. | |
23 | * | |
24 | * This program is distributed in the hope that it will be useful, | |
25 | * but WITHOUT ANY WARRANTY ; without even the implied warranty of | |
26 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
27 | * GNU General Public License for more details. | |
28 | * | |
29 | * You should have received a copy of the GNU General Public License | |
30 | * along with this program ; see the file COPYING. | |
31 | * If not, write to the Free Software Foundation, | |
32 | * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. | |
33 | */ | |
34 | ||
35 | #include <linux/init.h> | |
36 | #include <linux/module.h> | |
131b17d4 | 37 | #include <linux/delay.h> |
a5f6abd4 | 38 | #include <linux/device.h> |
131b17d4 | 39 | #include <linux/io.h> |
a5f6abd4 | 40 | #include <linux/ioport.h> |
131b17d4 | 41 | #include <linux/irq.h> |
a5f6abd4 WB |
42 | #include <linux/errno.h> |
43 | #include <linux/interrupt.h> | |
44 | #include <linux/platform_device.h> | |
45 | #include <linux/dma-mapping.h> | |
46 | #include <linux/spi/spi.h> | |
47 | #include <linux/workqueue.h> | |
a5f6abd4 | 48 | |
a5f6abd4 | 49 | #include <asm/dma.h> |
131b17d4 | 50 | #include <asm/portmux.h> |
a5f6abd4 WB |
51 | #include <asm/bfin5xx_spi.h> |
52 | ||
131b17d4 BW |
53 | MODULE_AUTHOR("Bryan Wu, Luke Yang"); |
54 | MODULE_DESCRIPTION("Blackfin BF5xx SPI Contoller Driver"); | |
a5f6abd4 WB |
55 | MODULE_LICENSE("GPL"); |
56 | ||
131b17d4 | 57 | #define DRV_NAME "bfin-spi-master" |
a5f6abd4 WB |
58 | #define IS_DMA_ALIGNED(x) (((u32)(x)&0x07)==0) |
59 | ||
60 | #define DEFINE_SPI_REG(reg, off) \ | |
61 | static inline u16 read_##reg(void) \ | |
5fec5b5a | 62 | { return bfin_read16(SPI0_REGBASE + off); } \ |
a5f6abd4 | 63 | static inline void write_##reg(u16 v) \ |
5fec5b5a | 64 | {bfin_write16(SPI0_REGBASE + off, v); } |
a5f6abd4 WB |
65 | |
66 | DEFINE_SPI_REG(CTRL, 0x00) | |
67 | DEFINE_SPI_REG(FLAG, 0x04) | |
68 | DEFINE_SPI_REG(STAT, 0x08) | |
69 | DEFINE_SPI_REG(TDBR, 0x0C) | |
70 | DEFINE_SPI_REG(RDBR, 0x10) | |
71 | DEFINE_SPI_REG(BAUD, 0x14) | |
72 | DEFINE_SPI_REG(SHAW, 0x18) | |
73 | #define START_STATE ((void*)0) | |
74 | #define RUNNING_STATE ((void*)1) | |
75 | #define DONE_STATE ((void*)2) | |
76 | #define ERROR_STATE ((void*)-1) | |
77 | #define QUEUE_RUNNING 0 | |
78 | #define QUEUE_STOPPED 1 | |
79 | int dma_requested; | |
80 | ||
81 | struct driver_data { | |
82 | /* Driver model hookup */ | |
83 | struct platform_device *pdev; | |
84 | ||
85 | /* SPI framework hookup */ | |
86 | struct spi_master *master; | |
87 | ||
88 | /* BFIN hookup */ | |
89 | struct bfin5xx_spi_master *master_info; | |
90 | ||
91 | /* Driver message queue */ | |
92 | struct workqueue_struct *workqueue; | |
93 | struct work_struct pump_messages; | |
94 | spinlock_t lock; | |
95 | struct list_head queue; | |
96 | int busy; | |
97 | int run; | |
98 | ||
99 | /* Message Transfer pump */ | |
100 | struct tasklet_struct pump_transfers; | |
101 | ||
102 | /* Current message transfer state info */ | |
103 | struct spi_message *cur_msg; | |
104 | struct spi_transfer *cur_transfer; | |
105 | struct chip_data *cur_chip; | |
106 | size_t len_in_bytes; | |
107 | size_t len; | |
108 | void *tx; | |
109 | void *tx_end; | |
110 | void *rx; | |
111 | void *rx_end; | |
112 | int dma_mapped; | |
113 | dma_addr_t rx_dma; | |
114 | dma_addr_t tx_dma; | |
115 | size_t rx_map_len; | |
116 | size_t tx_map_len; | |
117 | u8 n_bytes; | |
fad91c89 | 118 | int cs_change; |
a5f6abd4 WB |
119 | void (*write) (struct driver_data *); |
120 | void (*read) (struct driver_data *); | |
121 | void (*duplex) (struct driver_data *); | |
122 | }; | |
123 | ||
124 | struct chip_data { | |
125 | u16 ctl_reg; | |
126 | u16 baud; | |
127 | u16 flag; | |
128 | ||
129 | u8 chip_select_num; | |
131b17d4 | 130 | u8 chip_select_requested; |
a5f6abd4 | 131 | u8 n_bytes; |
88b40369 | 132 | u8 width; /* 0 or 1 */ |
a5f6abd4 WB |
133 | u8 enable_dma; |
134 | u8 bits_per_word; /* 8 or 16 */ | |
135 | u8 cs_change_per_word; | |
136 | u8 cs_chg_udelay; | |
137 | void (*write) (struct driver_data *); | |
138 | void (*read) (struct driver_data *); | |
139 | void (*duplex) (struct driver_data *); | |
140 | }; | |
141 | ||
88b40369 | 142 | static void bfin_spi_enable(struct driver_data *drv_data) |
a5f6abd4 WB |
143 | { |
144 | u16 cr; | |
145 | ||
146 | cr = read_CTRL(); | |
147 | write_CTRL(cr | BIT_CTL_ENABLE); | |
a5f6abd4 WB |
148 | } |
149 | ||
88b40369 | 150 | static void bfin_spi_disable(struct driver_data *drv_data) |
a5f6abd4 WB |
151 | { |
152 | u16 cr; | |
153 | ||
154 | cr = read_CTRL(); | |
155 | write_CTRL(cr & (~BIT_CTL_ENABLE)); | |
a5f6abd4 WB |
156 | } |
157 | ||
158 | /* Caculate the SPI_BAUD register value based on input HZ */ | |
159 | static u16 hz_to_spi_baud(u32 speed_hz) | |
160 | { | |
161 | u_long sclk = get_sclk(); | |
162 | u16 spi_baud = (sclk / (2 * speed_hz)); | |
163 | ||
164 | if ((sclk % (2 * speed_hz)) > 0) | |
165 | spi_baud++; | |
166 | ||
a5f6abd4 WB |
167 | return spi_baud; |
168 | } | |
169 | ||
170 | static int flush(struct driver_data *drv_data) | |
171 | { | |
172 | unsigned long limit = loops_per_jiffy << 1; | |
173 | ||
174 | /* wait for stop and clear stat */ | |
175 | while (!(read_STAT() & BIT_STAT_SPIF) && limit--) | |
176 | continue; | |
177 | ||
178 | write_STAT(BIT_STAT_CLR); | |
179 | ||
180 | return limit; | |
181 | } | |
182 | ||
fad91c89 BW |
183 | /* Chip select operation functions for cs_change flag */ |
184 | static void cs_active(struct chip_data *chip) | |
185 | { | |
186 | u16 flag = read_FLAG(); | |
187 | ||
188 | flag |= chip->flag; | |
189 | flag &= ~(chip->flag << 8); | |
190 | ||
191 | write_FLAG(flag); | |
192 | } | |
193 | ||
194 | static void cs_deactive(struct chip_data *chip) | |
195 | { | |
196 | u16 flag = read_FLAG(); | |
197 | ||
198 | flag |= (chip->flag << 8); | |
199 | ||
200 | write_FLAG(flag); | |
201 | } | |
202 | ||
5fec5b5a BW |
203 | #define MAX_SPI0_SSEL 7 |
204 | ||
a5f6abd4 | 205 | /* stop controller and re-config current chip*/ |
5fec5b5a | 206 | static int restore_state(struct driver_data *drv_data) |
a5f6abd4 WB |
207 | { |
208 | struct chip_data *chip = drv_data->cur_chip; | |
5fec5b5a BW |
209 | int ret = 0; |
210 | u16 ssel[MAX_SPI0_SSEL] = {P_SPI0_SSEL1, P_SPI0_SSEL2, P_SPI0_SSEL3, | |
211 | P_SPI0_SSEL4, P_SPI0_SSEL5, | |
212 | P_SPI0_SSEL6, P_SPI0_SSEL7,}; | |
a5f6abd4 WB |
213 | |
214 | /* Clear status and disable clock */ | |
215 | write_STAT(BIT_STAT_CLR); | |
216 | bfin_spi_disable(drv_data); | |
88b40369 | 217 | dev_dbg(&drv_data->pdev->dev, "restoring spi ctl state\n"); |
a5f6abd4 | 218 | |
5fec5b5a BW |
219 | /* Load the registers */ |
220 | write_CTRL(chip->ctl_reg); | |
221 | write_BAUD(chip->baud); | |
fad91c89 | 222 | cs_active(chip); |
5fec5b5a | 223 | |
131b17d4 | 224 | if (!chip->chip_select_requested) { |
5fec5b5a | 225 | int i = chip->chip_select_num; |
a5f6abd4 | 226 | |
5fec5b5a BW |
227 | dev_dbg(&drv_data->pdev->dev, "chip select number is %d\n", i); |
228 | ||
229 | if ((i > 0) && (i <= MAX_SPI0_SSEL)) | |
230 | ret = peripheral_request(ssel[i-1], DRV_NAME); | |
a5f6abd4 | 231 | |
131b17d4 | 232 | chip->chip_select_requested = 1; |
a5f6abd4 | 233 | } |
a5f6abd4 | 234 | |
5fec5b5a BW |
235 | if (ret) |
236 | dev_dbg(&drv_data->pdev->dev, | |
237 | ": request chip select number %d failed\n", | |
238 | chip->chip_select_num); | |
239 | ||
240 | return ret; | |
a5f6abd4 WB |
241 | } |
242 | ||
243 | /* used to kick off transfer in rx mode */ | |
244 | static unsigned short dummy_read(void) | |
245 | { | |
246 | unsigned short tmp; | |
247 | tmp = read_RDBR(); | |
248 | return tmp; | |
249 | } | |
250 | ||
251 | static void null_writer(struct driver_data *drv_data) | |
252 | { | |
253 | u8 n_bytes = drv_data->n_bytes; | |
254 | ||
255 | while (drv_data->tx < drv_data->tx_end) { | |
256 | write_TDBR(0); | |
257 | while ((read_STAT() & BIT_STAT_TXS)) | |
258 | continue; | |
259 | drv_data->tx += n_bytes; | |
260 | } | |
261 | } | |
262 | ||
263 | static void null_reader(struct driver_data *drv_data) | |
264 | { | |
265 | u8 n_bytes = drv_data->n_bytes; | |
266 | dummy_read(); | |
267 | ||
268 | while (drv_data->rx < drv_data->rx_end) { | |
269 | while (!(read_STAT() & BIT_STAT_RXS)) | |
270 | continue; | |
271 | dummy_read(); | |
272 | drv_data->rx += n_bytes; | |
273 | } | |
274 | } | |
275 | ||
276 | static void u8_writer(struct driver_data *drv_data) | |
277 | { | |
131b17d4 | 278 | dev_dbg(&drv_data->pdev->dev, |
88b40369 | 279 | "cr8-s is 0x%x\n", read_STAT()); |
a5f6abd4 WB |
280 | while (drv_data->tx < drv_data->tx_end) { |
281 | write_TDBR(*(u8 *) (drv_data->tx)); | |
282 | while (read_STAT() & BIT_STAT_TXS) | |
283 | continue; | |
284 | ++drv_data->tx; | |
285 | } | |
286 | ||
287 | /* poll for SPI completion before returning */ | |
288 | while (!(read_STAT() & BIT_STAT_SPIF)) | |
289 | continue; | |
290 | } | |
291 | ||
292 | static void u8_cs_chg_writer(struct driver_data *drv_data) | |
293 | { | |
294 | struct chip_data *chip = drv_data->cur_chip; | |
295 | ||
296 | while (drv_data->tx < drv_data->tx_end) { | |
fad91c89 | 297 | cs_active(chip); |
a5f6abd4 WB |
298 | |
299 | write_TDBR(*(u8 *) (drv_data->tx)); | |
300 | while (read_STAT() & BIT_STAT_TXS) | |
301 | continue; | |
302 | while (!(read_STAT() & BIT_STAT_SPIF)) | |
303 | continue; | |
fad91c89 | 304 | cs_deactive(chip); |
5fec5b5a | 305 | |
a5f6abd4 WB |
306 | if (chip->cs_chg_udelay) |
307 | udelay(chip->cs_chg_udelay); | |
308 | ++drv_data->tx; | |
309 | } | |
fad91c89 | 310 | cs_deactive(chip); |
5fec5b5a | 311 | |
a5f6abd4 WB |
312 | } |
313 | ||
314 | static void u8_reader(struct driver_data *drv_data) | |
315 | { | |
131b17d4 | 316 | dev_dbg(&drv_data->pdev->dev, |
88b40369 | 317 | "cr-8 is 0x%x\n", read_STAT()); |
a5f6abd4 WB |
318 | |
319 | /* clear TDBR buffer before read(else it will be shifted out) */ | |
320 | write_TDBR(0xFFFF); | |
321 | ||
322 | dummy_read(); | |
323 | ||
324 | while (drv_data->rx < drv_data->rx_end - 1) { | |
325 | while (!(read_STAT() & BIT_STAT_RXS)) | |
326 | continue; | |
327 | *(u8 *) (drv_data->rx) = read_RDBR(); | |
328 | ++drv_data->rx; | |
329 | } | |
330 | ||
331 | while (!(read_STAT() & BIT_STAT_RXS)) | |
332 | continue; | |
333 | *(u8 *) (drv_data->rx) = read_SHAW(); | |
334 | ++drv_data->rx; | |
335 | } | |
336 | ||
337 | static void u8_cs_chg_reader(struct driver_data *drv_data) | |
338 | { | |
339 | struct chip_data *chip = drv_data->cur_chip; | |
340 | ||
341 | while (drv_data->rx < drv_data->rx_end) { | |
fad91c89 | 342 | cs_active(chip); |
a5f6abd4 WB |
343 | |
344 | read_RDBR(); /* kick off */ | |
345 | while (!(read_STAT() & BIT_STAT_RXS)) | |
346 | continue; | |
347 | while (!(read_STAT() & BIT_STAT_SPIF)) | |
348 | continue; | |
349 | *(u8 *) (drv_data->rx) = read_SHAW(); | |
fad91c89 | 350 | cs_deactive(chip); |
5fec5b5a | 351 | |
a5f6abd4 WB |
352 | if (chip->cs_chg_udelay) |
353 | udelay(chip->cs_chg_udelay); | |
354 | ++drv_data->rx; | |
355 | } | |
fad91c89 | 356 | cs_deactive(chip); |
5fec5b5a | 357 | |
a5f6abd4 WB |
358 | } |
359 | ||
360 | static void u8_duplex(struct driver_data *drv_data) | |
361 | { | |
362 | /* in duplex mode, clk is triggered by writing of TDBR */ | |
363 | while (drv_data->rx < drv_data->rx_end) { | |
364 | write_TDBR(*(u8 *) (drv_data->tx)); | |
365 | while (!(read_STAT() & BIT_STAT_SPIF)) | |
366 | continue; | |
367 | while (!(read_STAT() & BIT_STAT_RXS)) | |
368 | continue; | |
369 | *(u8 *) (drv_data->rx) = read_RDBR(); | |
370 | ++drv_data->rx; | |
371 | ++drv_data->tx; | |
372 | } | |
373 | } | |
374 | ||
375 | static void u8_cs_chg_duplex(struct driver_data *drv_data) | |
376 | { | |
377 | struct chip_data *chip = drv_data->cur_chip; | |
378 | ||
379 | while (drv_data->rx < drv_data->rx_end) { | |
fad91c89 | 380 | cs_active(chip); |
5fec5b5a | 381 | |
a5f6abd4 WB |
382 | |
383 | write_TDBR(*(u8 *) (drv_data->tx)); | |
384 | while (!(read_STAT() & BIT_STAT_SPIF)) | |
385 | continue; | |
386 | while (!(read_STAT() & BIT_STAT_RXS)) | |
387 | continue; | |
388 | *(u8 *) (drv_data->rx) = read_RDBR(); | |
fad91c89 | 389 | cs_deactive(chip); |
5fec5b5a | 390 | |
a5f6abd4 WB |
391 | if (chip->cs_chg_udelay) |
392 | udelay(chip->cs_chg_udelay); | |
393 | ++drv_data->rx; | |
394 | ++drv_data->tx; | |
395 | } | |
fad91c89 | 396 | cs_deactive(chip); |
a5f6abd4 WB |
397 | } |
398 | ||
399 | static void u16_writer(struct driver_data *drv_data) | |
400 | { | |
131b17d4 | 401 | dev_dbg(&drv_data->pdev->dev, |
88b40369 BW |
402 | "cr16 is 0x%x\n", read_STAT()); |
403 | ||
a5f6abd4 WB |
404 | while (drv_data->tx < drv_data->tx_end) { |
405 | write_TDBR(*(u16 *) (drv_data->tx)); | |
406 | while ((read_STAT() & BIT_STAT_TXS)) | |
407 | continue; | |
408 | drv_data->tx += 2; | |
409 | } | |
410 | ||
411 | /* poll for SPI completion before returning */ | |
412 | while (!(read_STAT() & BIT_STAT_SPIF)) | |
413 | continue; | |
414 | } | |
415 | ||
416 | static void u16_cs_chg_writer(struct driver_data *drv_data) | |
417 | { | |
418 | struct chip_data *chip = drv_data->cur_chip; | |
419 | ||
420 | while (drv_data->tx < drv_data->tx_end) { | |
fad91c89 | 421 | cs_active(chip); |
a5f6abd4 WB |
422 | |
423 | write_TDBR(*(u16 *) (drv_data->tx)); | |
424 | while ((read_STAT() & BIT_STAT_TXS)) | |
425 | continue; | |
426 | while (!(read_STAT() & BIT_STAT_SPIF)) | |
427 | continue; | |
fad91c89 | 428 | cs_deactive(chip); |
5fec5b5a | 429 | |
a5f6abd4 WB |
430 | if (chip->cs_chg_udelay) |
431 | udelay(chip->cs_chg_udelay); | |
432 | drv_data->tx += 2; | |
433 | } | |
fad91c89 | 434 | cs_deactive(chip); |
a5f6abd4 WB |
435 | } |
436 | ||
437 | static void u16_reader(struct driver_data *drv_data) | |
438 | { | |
88b40369 BW |
439 | dev_dbg(&drv_data->pdev->dev, |
440 | "cr-16 is 0x%x\n", read_STAT()); | |
a5f6abd4 WB |
441 | dummy_read(); |
442 | ||
443 | while (drv_data->rx < (drv_data->rx_end - 2)) { | |
444 | while (!(read_STAT() & BIT_STAT_RXS)) | |
445 | continue; | |
446 | *(u16 *) (drv_data->rx) = read_RDBR(); | |
447 | drv_data->rx += 2; | |
448 | } | |
449 | ||
450 | while (!(read_STAT() & BIT_STAT_RXS)) | |
451 | continue; | |
452 | *(u16 *) (drv_data->rx) = read_SHAW(); | |
453 | drv_data->rx += 2; | |
454 | } | |
455 | ||
456 | static void u16_cs_chg_reader(struct driver_data *drv_data) | |
457 | { | |
458 | struct chip_data *chip = drv_data->cur_chip; | |
459 | ||
460 | while (drv_data->rx < drv_data->rx_end) { | |
fad91c89 | 461 | cs_active(chip); |
a5f6abd4 WB |
462 | |
463 | read_RDBR(); /* kick off */ | |
464 | while (!(read_STAT() & BIT_STAT_RXS)) | |
465 | continue; | |
466 | while (!(read_STAT() & BIT_STAT_SPIF)) | |
467 | continue; | |
468 | *(u16 *) (drv_data->rx) = read_SHAW(); | |
fad91c89 | 469 | cs_deactive(chip); |
5fec5b5a | 470 | |
a5f6abd4 WB |
471 | if (chip->cs_chg_udelay) |
472 | udelay(chip->cs_chg_udelay); | |
473 | drv_data->rx += 2; | |
474 | } | |
fad91c89 | 475 | cs_deactive(chip); |
a5f6abd4 WB |
476 | } |
477 | ||
478 | static void u16_duplex(struct driver_data *drv_data) | |
479 | { | |
480 | /* in duplex mode, clk is triggered by writing of TDBR */ | |
481 | while (drv_data->tx < drv_data->tx_end) { | |
482 | write_TDBR(*(u16 *) (drv_data->tx)); | |
483 | while (!(read_STAT() & BIT_STAT_SPIF)) | |
484 | continue; | |
485 | while (!(read_STAT() & BIT_STAT_RXS)) | |
486 | continue; | |
487 | *(u16 *) (drv_data->rx) = read_RDBR(); | |
488 | drv_data->rx += 2; | |
489 | drv_data->tx += 2; | |
490 | } | |
491 | } | |
492 | ||
493 | static void u16_cs_chg_duplex(struct driver_data *drv_data) | |
494 | { | |
495 | struct chip_data *chip = drv_data->cur_chip; | |
496 | ||
497 | while (drv_data->tx < drv_data->tx_end) { | |
fad91c89 | 498 | cs_active(chip); |
a5f6abd4 WB |
499 | |
500 | write_TDBR(*(u16 *) (drv_data->tx)); | |
501 | while (!(read_STAT() & BIT_STAT_SPIF)) | |
502 | continue; | |
503 | while (!(read_STAT() & BIT_STAT_RXS)) | |
504 | continue; | |
505 | *(u16 *) (drv_data->rx) = read_RDBR(); | |
fad91c89 | 506 | cs_deactive(chip); |
5fec5b5a | 507 | |
a5f6abd4 WB |
508 | if (chip->cs_chg_udelay) |
509 | udelay(chip->cs_chg_udelay); | |
510 | drv_data->rx += 2; | |
511 | drv_data->tx += 2; | |
512 | } | |
fad91c89 | 513 | cs_deactive(chip); |
a5f6abd4 WB |
514 | } |
515 | ||
516 | /* test if ther is more transfer to be done */ | |
517 | static void *next_transfer(struct driver_data *drv_data) | |
518 | { | |
519 | struct spi_message *msg = drv_data->cur_msg; | |
520 | struct spi_transfer *trans = drv_data->cur_transfer; | |
521 | ||
522 | /* Move to next transfer */ | |
523 | if (trans->transfer_list.next != &msg->transfers) { | |
524 | drv_data->cur_transfer = | |
525 | list_entry(trans->transfer_list.next, | |
526 | struct spi_transfer, transfer_list); | |
527 | return RUNNING_STATE; | |
528 | } else | |
529 | return DONE_STATE; | |
530 | } | |
531 | ||
532 | /* | |
533 | * caller already set message->status; | |
534 | * dma and pio irqs are blocked give finished message back | |
535 | */ | |
536 | static void giveback(struct driver_data *drv_data) | |
537 | { | |
fad91c89 | 538 | struct chip_data *chip = drv_data->cur_chip; |
a5f6abd4 WB |
539 | struct spi_transfer *last_transfer; |
540 | unsigned long flags; | |
541 | struct spi_message *msg; | |
542 | ||
543 | spin_lock_irqsave(&drv_data->lock, flags); | |
544 | msg = drv_data->cur_msg; | |
545 | drv_data->cur_msg = NULL; | |
546 | drv_data->cur_transfer = NULL; | |
547 | drv_data->cur_chip = NULL; | |
548 | queue_work(drv_data->workqueue, &drv_data->pump_messages); | |
549 | spin_unlock_irqrestore(&drv_data->lock, flags); | |
550 | ||
551 | last_transfer = list_entry(msg->transfers.prev, | |
552 | struct spi_transfer, transfer_list); | |
553 | ||
554 | msg->state = NULL; | |
555 | ||
556 | /* disable chip select signal. And not stop spi in autobuffer mode */ | |
557 | if (drv_data->tx_dma != 0xFFFF) { | |
fad91c89 | 558 | cs_deactive(chip); |
a5f6abd4 WB |
559 | bfin_spi_disable(drv_data); |
560 | } | |
561 | ||
fad91c89 BW |
562 | if (!drv_data->cs_change) |
563 | cs_deactive(chip); | |
564 | ||
a5f6abd4 WB |
565 | if (msg->complete) |
566 | msg->complete(msg->context); | |
567 | } | |
568 | ||
88b40369 | 569 | static irqreturn_t dma_irq_handler(int irq, void *dev_id) |
a5f6abd4 WB |
570 | { |
571 | struct driver_data *drv_data = (struct driver_data *)dev_id; | |
572 | struct spi_message *msg = drv_data->cur_msg; | |
fad91c89 | 573 | struct chip_data *chip = drv_data->cur_chip; |
a5f6abd4 | 574 | |
88b40369 | 575 | dev_dbg(&drv_data->pdev->dev, "in dma_irq_handler\n"); |
a5f6abd4 WB |
576 | clear_dma_irqstat(CH_SPI); |
577 | ||
d6fe89b0 BW |
578 | /* Wait for DMA to complete */ |
579 | while (get_dma_curr_irqstat(CH_SPI) & DMA_RUN) | |
580 | continue; | |
581 | ||
a5f6abd4 | 582 | /* |
d6fe89b0 BW |
583 | * wait for the last transaction shifted out. HRM states: |
584 | * at this point there may still be data in the SPI DMA FIFO waiting | |
585 | * to be transmitted ... software needs to poll TXS in the SPI_STAT | |
586 | * register until it goes low for 2 successive reads | |
a5f6abd4 WB |
587 | */ |
588 | if (drv_data->tx != NULL) { | |
d6fe89b0 BW |
589 | while ((bfin_read_SPI_STAT() & TXS) || |
590 | (bfin_read_SPI_STAT() & TXS)) | |
a5f6abd4 WB |
591 | continue; |
592 | } | |
593 | ||
594 | while (!(bfin_read_SPI_STAT() & SPIF)) | |
595 | continue; | |
596 | ||
597 | bfin_spi_disable(drv_data); | |
598 | ||
599 | msg->actual_length += drv_data->len_in_bytes; | |
600 | ||
fad91c89 BW |
601 | if (drv_data->cs_change) |
602 | cs_deactive(chip); | |
603 | ||
a5f6abd4 WB |
604 | /* Move to next transfer */ |
605 | msg->state = next_transfer(drv_data); | |
606 | ||
607 | /* Schedule transfer tasklet */ | |
608 | tasklet_schedule(&drv_data->pump_transfers); | |
609 | ||
610 | /* free the irq handler before next transfer */ | |
88b40369 BW |
611 | dev_dbg(&drv_data->pdev->dev, |
612 | "disable dma channel irq%d\n", | |
613 | CH_SPI); | |
a5f6abd4 WB |
614 | dma_disable_irq(CH_SPI); |
615 | ||
616 | return IRQ_HANDLED; | |
617 | } | |
618 | ||
619 | static void pump_transfers(unsigned long data) | |
620 | { | |
621 | struct driver_data *drv_data = (struct driver_data *)data; | |
622 | struct spi_message *message = NULL; | |
623 | struct spi_transfer *transfer = NULL; | |
624 | struct spi_transfer *previous = NULL; | |
625 | struct chip_data *chip = NULL; | |
88b40369 BW |
626 | u8 width; |
627 | u16 cr, dma_width, dma_config; | |
a5f6abd4 WB |
628 | u32 tranf_success = 1; |
629 | ||
630 | /* Get current state information */ | |
631 | message = drv_data->cur_msg; | |
632 | transfer = drv_data->cur_transfer; | |
633 | chip = drv_data->cur_chip; | |
634 | ||
635 | /* | |
636 | * if msg is error or done, report it back using complete() callback | |
637 | */ | |
638 | ||
639 | /* Handle for abort */ | |
640 | if (message->state == ERROR_STATE) { | |
641 | message->status = -EIO; | |
642 | giveback(drv_data); | |
643 | return; | |
644 | } | |
645 | ||
646 | /* Handle end of message */ | |
647 | if (message->state == DONE_STATE) { | |
648 | message->status = 0; | |
649 | giveback(drv_data); | |
650 | return; | |
651 | } | |
652 | ||
653 | /* Delay if requested at end of transfer */ | |
654 | if (message->state == RUNNING_STATE) { | |
655 | previous = list_entry(transfer->transfer_list.prev, | |
656 | struct spi_transfer, transfer_list); | |
657 | if (previous->delay_usecs) | |
658 | udelay(previous->delay_usecs); | |
659 | } | |
660 | ||
661 | /* Setup the transfer state based on the type of transfer */ | |
662 | if (flush(drv_data) == 0) { | |
663 | dev_err(&drv_data->pdev->dev, "pump_transfers: flush failed\n"); | |
664 | message->status = -EIO; | |
665 | giveback(drv_data); | |
666 | return; | |
667 | } | |
668 | ||
669 | if (transfer->tx_buf != NULL) { | |
670 | drv_data->tx = (void *)transfer->tx_buf; | |
671 | drv_data->tx_end = drv_data->tx + transfer->len; | |
88b40369 BW |
672 | dev_dbg(&drv_data->pdev->dev, "tx_buf is %p, tx_end is %p\n", |
673 | transfer->tx_buf, drv_data->tx_end); | |
a5f6abd4 WB |
674 | } else { |
675 | drv_data->tx = NULL; | |
676 | } | |
677 | ||
678 | if (transfer->rx_buf != NULL) { | |
679 | drv_data->rx = transfer->rx_buf; | |
680 | drv_data->rx_end = drv_data->rx + transfer->len; | |
88b40369 BW |
681 | dev_dbg(&drv_data->pdev->dev, "rx_buf is %p, rx_end is %p\n", |
682 | transfer->rx_buf, drv_data->rx_end); | |
a5f6abd4 WB |
683 | } else { |
684 | drv_data->rx = NULL; | |
685 | } | |
686 | ||
687 | drv_data->rx_dma = transfer->rx_dma; | |
688 | drv_data->tx_dma = transfer->tx_dma; | |
689 | drv_data->len_in_bytes = transfer->len; | |
fad91c89 | 690 | drv_data->cs_change = transfer->cs_change; |
a5f6abd4 WB |
691 | |
692 | width = chip->width; | |
693 | if (width == CFG_SPI_WORDSIZE16) { | |
694 | drv_data->len = (transfer->len) >> 1; | |
695 | } else { | |
696 | drv_data->len = transfer->len; | |
697 | } | |
698 | drv_data->write = drv_data->tx ? chip->write : null_writer; | |
699 | drv_data->read = drv_data->rx ? chip->read : null_reader; | |
700 | drv_data->duplex = chip->duplex ? chip->duplex : null_writer; | |
131b17d4 BW |
701 | dev_dbg(&drv_data->pdev->dev, "transfer: ", |
702 | "drv_data->write is %p, chip->write is %p, null_wr is %p\n", | |
703 | drv_data->write, chip->write, null_writer); | |
a5f6abd4 WB |
704 | |
705 | /* speed and width has been set on per message */ | |
706 | message->state = RUNNING_STATE; | |
707 | dma_config = 0; | |
708 | ||
709 | /* restore spi status for each spi transfer */ | |
710 | if (transfer->speed_hz) { | |
711 | write_BAUD(hz_to_spi_baud(transfer->speed_hz)); | |
712 | } else { | |
713 | write_BAUD(chip->baud); | |
714 | } | |
fad91c89 | 715 | cs_active(chip); |
a5f6abd4 | 716 | |
88b40369 BW |
717 | dev_dbg(&drv_data->pdev->dev, |
718 | "now pumping a transfer: width is %d, len is %d\n", | |
719 | width, transfer->len); | |
a5f6abd4 WB |
720 | |
721 | /* | |
722 | * Try to map dma buffer and do a dma transfer if | |
723 | * successful use different way to r/w according to | |
724 | * drv_data->cur_chip->enable_dma | |
725 | */ | |
726 | if (drv_data->cur_chip->enable_dma && drv_data->len > 6) { | |
727 | ||
728 | write_STAT(BIT_STAT_CLR); | |
729 | disable_dma(CH_SPI); | |
730 | clear_dma_irqstat(CH_SPI); | |
731 | bfin_spi_disable(drv_data); | |
732 | ||
733 | /* config dma channel */ | |
88b40369 | 734 | dev_dbg(&drv_data->pdev->dev, "doing dma transfer\n"); |
a5f6abd4 WB |
735 | if (width == CFG_SPI_WORDSIZE16) { |
736 | set_dma_x_count(CH_SPI, drv_data->len); | |
737 | set_dma_x_modify(CH_SPI, 2); | |
738 | dma_width = WDSIZE_16; | |
739 | } else { | |
740 | set_dma_x_count(CH_SPI, drv_data->len); | |
741 | set_dma_x_modify(CH_SPI, 1); | |
742 | dma_width = WDSIZE_8; | |
743 | } | |
744 | ||
745 | /* set transfer width,direction. And enable spi */ | |
746 | cr = (read_CTRL() & (~BIT_CTL_TIMOD)); | |
747 | ||
748 | /* dirty hack for autobuffer DMA mode */ | |
749 | if (drv_data->tx_dma == 0xFFFF) { | |
88b40369 BW |
750 | dev_dbg(&drv_data->pdev->dev, |
751 | "doing autobuffer DMA out.\n"); | |
a5f6abd4 WB |
752 | |
753 | /* no irq in autobuffer mode */ | |
754 | dma_config = | |
755 | (DMAFLOW_AUTO | RESTART | dma_width | DI_EN); | |
756 | set_dma_config(CH_SPI, dma_config); | |
757 | set_dma_start_addr(CH_SPI, (unsigned long)drv_data->tx); | |
758 | enable_dma(CH_SPI); | |
759 | write_CTRL(cr | CFG_SPI_DMAWRITE | (width << 8) | | |
760 | (CFG_SPI_ENABLE << 14)); | |
761 | ||
762 | /* just return here, there can only be one transfer in this mode */ | |
763 | message->status = 0; | |
764 | giveback(drv_data); | |
765 | return; | |
766 | } | |
767 | ||
768 | /* In dma mode, rx or tx must be NULL in one transfer */ | |
769 | if (drv_data->rx != NULL) { | |
770 | /* set transfer mode, and enable SPI */ | |
88b40369 | 771 | dev_dbg(&drv_data->pdev->dev, "doing DMA in.\n"); |
a5f6abd4 WB |
772 | |
773 | /* disable SPI before write to TDBR */ | |
774 | write_CTRL(cr & ~BIT_CTL_ENABLE); | |
775 | ||
776 | /* clear tx reg soformer data is not shifted out */ | |
777 | write_TDBR(0xFF); | |
778 | ||
779 | set_dma_x_count(CH_SPI, drv_data->len); | |
780 | ||
781 | /* start dma */ | |
782 | dma_enable_irq(CH_SPI); | |
783 | dma_config = (WNR | RESTART | dma_width | DI_EN); | |
784 | set_dma_config(CH_SPI, dma_config); | |
785 | set_dma_start_addr(CH_SPI, (unsigned long)drv_data->rx); | |
786 | enable_dma(CH_SPI); | |
787 | ||
788 | cr |= | |
789 | CFG_SPI_DMAREAD | (width << 8) | (CFG_SPI_ENABLE << | |
790 | 14); | |
791 | /* set transfer mode, and enable SPI */ | |
792 | write_CTRL(cr); | |
793 | } else if (drv_data->tx != NULL) { | |
88b40369 | 794 | dev_dbg(&drv_data->pdev->dev, "doing DMA out.\n"); |
a5f6abd4 WB |
795 | |
796 | /* start dma */ | |
797 | dma_enable_irq(CH_SPI); | |
798 | dma_config = (RESTART | dma_width | DI_EN); | |
799 | set_dma_config(CH_SPI, dma_config); | |
800 | set_dma_start_addr(CH_SPI, (unsigned long)drv_data->tx); | |
801 | enable_dma(CH_SPI); | |
802 | ||
803 | write_CTRL(cr | CFG_SPI_DMAWRITE | (width << 8) | | |
804 | (CFG_SPI_ENABLE << 14)); | |
805 | ||
806 | } | |
807 | } else { | |
808 | /* IO mode write then read */ | |
88b40369 | 809 | dev_dbg(&drv_data->pdev->dev, "doing IO transfer\n"); |
a5f6abd4 WB |
810 | |
811 | write_STAT(BIT_STAT_CLR); | |
812 | ||
813 | if (drv_data->tx != NULL && drv_data->rx != NULL) { | |
814 | /* full duplex mode */ | |
815 | BUG_ON((drv_data->tx_end - drv_data->tx) != | |
816 | (drv_data->rx_end - drv_data->rx)); | |
131b17d4 | 817 | cr = (read_CTRL() & (~BIT_CTL_TIMOD)); |
88b40369 BW |
818 | cr |= CFG_SPI_WRITE | (width << 8) | |
819 | (CFG_SPI_ENABLE << 14); | |
820 | dev_dbg(&drv_data->pdev->dev, | |
821 | "IO duplex: cr is 0x%x\n", cr); | |
a5f6abd4 WB |
822 | |
823 | write_CTRL(cr); | |
a5f6abd4 WB |
824 | |
825 | drv_data->duplex(drv_data); | |
826 | ||
827 | if (drv_data->tx != drv_data->tx_end) | |
828 | tranf_success = 0; | |
829 | } else if (drv_data->tx != NULL) { | |
830 | /* write only half duplex */ | |
88b40369 BW |
831 | cr = (read_CTRL() & (~BIT_CTL_TIMOD)); |
832 | cr |= CFG_SPI_WRITE | (width << 8) | | |
833 | (CFG_SPI_ENABLE << 14); | |
131b17d4 | 834 | dev_dbg(&drv_data->pdev->dev, |
88b40369 | 835 | "IO write: cr is 0x%x\n", cr); |
a5f6abd4 WB |
836 | |
837 | write_CTRL(cr); | |
a5f6abd4 WB |
838 | |
839 | drv_data->write(drv_data); | |
840 | ||
841 | if (drv_data->tx != drv_data->tx_end) | |
842 | tranf_success = 0; | |
843 | } else if (drv_data->rx != NULL) { | |
844 | /* read only half duplex */ | |
88b40369 BW |
845 | cr = (read_CTRL() & (~BIT_CTL_TIMOD)); |
846 | cr |= CFG_SPI_READ | (width << 8) | | |
847 | (CFG_SPI_ENABLE << 14); | |
131b17d4 | 848 | dev_dbg(&drv_data->pdev->dev, |
88b40369 | 849 | "IO read: cr is 0x%x\n", cr); |
a5f6abd4 WB |
850 | |
851 | write_CTRL(cr); | |
a5f6abd4 WB |
852 | |
853 | drv_data->read(drv_data); | |
854 | if (drv_data->rx != drv_data->rx_end) | |
855 | tranf_success = 0; | |
856 | } | |
857 | ||
858 | if (!tranf_success) { | |
131b17d4 | 859 | dev_dbg(&drv_data->pdev->dev, |
88b40369 | 860 | "IO write error!\n"); |
a5f6abd4 WB |
861 | message->state = ERROR_STATE; |
862 | } else { | |
863 | /* Update total byte transfered */ | |
864 | message->actual_length += drv_data->len; | |
865 | ||
fad91c89 BW |
866 | if (drv_data->cs_change) |
867 | cs_deactive(chip); | |
868 | ||
a5f6abd4 WB |
869 | /* Move to next transfer of this msg */ |
870 | message->state = next_transfer(drv_data); | |
871 | } | |
872 | ||
873 | /* Schedule next transfer tasklet */ | |
874 | tasklet_schedule(&drv_data->pump_transfers); | |
875 | ||
876 | } | |
877 | } | |
878 | ||
879 | /* pop a msg from queue and kick off real transfer */ | |
880 | static void pump_messages(struct work_struct *work) | |
881 | { | |
131b17d4 | 882 | struct driver_data *drv_data; |
a5f6abd4 WB |
883 | unsigned long flags; |
884 | ||
131b17d4 BW |
885 | drv_data = container_of(work, struct driver_data, pump_messages); |
886 | ||
a5f6abd4 WB |
887 | /* Lock queue and check for queue work */ |
888 | spin_lock_irqsave(&drv_data->lock, flags); | |
889 | if (list_empty(&drv_data->queue) || drv_data->run == QUEUE_STOPPED) { | |
890 | /* pumper kicked off but no work to do */ | |
891 | drv_data->busy = 0; | |
892 | spin_unlock_irqrestore(&drv_data->lock, flags); | |
893 | return; | |
894 | } | |
895 | ||
896 | /* Make sure we are not already running a message */ | |
897 | if (drv_data->cur_msg) { | |
898 | spin_unlock_irqrestore(&drv_data->lock, flags); | |
899 | return; | |
900 | } | |
901 | ||
902 | /* Extract head of queue */ | |
903 | drv_data->cur_msg = list_entry(drv_data->queue.next, | |
904 | struct spi_message, queue); | |
5fec5b5a BW |
905 | |
906 | /* Setup the SSP using the per chip configuration */ | |
907 | drv_data->cur_chip = spi_get_ctldata(drv_data->cur_msg->spi); | |
908 | if (restore_state(drv_data)) { | |
909 | spin_unlock_irqrestore(&drv_data->lock, flags); | |
910 | return; | |
911 | }; | |
912 | ||
a5f6abd4 WB |
913 | list_del_init(&drv_data->cur_msg->queue); |
914 | ||
915 | /* Initial message state */ | |
916 | drv_data->cur_msg->state = START_STATE; | |
917 | drv_data->cur_transfer = list_entry(drv_data->cur_msg->transfers.next, | |
918 | struct spi_transfer, transfer_list); | |
919 | ||
5fec5b5a BW |
920 | dev_dbg(&drv_data->pdev->dev, "got a message to pump, " |
921 | "state is set to: baud %d, flag 0x%x, ctl 0x%x\n", | |
922 | drv_data->cur_chip->baud, drv_data->cur_chip->flag, | |
923 | drv_data->cur_chip->ctl_reg); | |
131b17d4 BW |
924 | |
925 | dev_dbg(&drv_data->pdev->dev, | |
88b40369 BW |
926 | "the first transfer len is %d\n", |
927 | drv_data->cur_transfer->len); | |
a5f6abd4 WB |
928 | |
929 | /* Mark as busy and launch transfers */ | |
930 | tasklet_schedule(&drv_data->pump_transfers); | |
931 | ||
932 | drv_data->busy = 1; | |
933 | spin_unlock_irqrestore(&drv_data->lock, flags); | |
934 | } | |
935 | ||
936 | /* | |
937 | * got a msg to transfer, queue it in drv_data->queue. | |
938 | * And kick off message pumper | |
939 | */ | |
940 | static int transfer(struct spi_device *spi, struct spi_message *msg) | |
941 | { | |
942 | struct driver_data *drv_data = spi_master_get_devdata(spi->master); | |
943 | unsigned long flags; | |
944 | ||
945 | spin_lock_irqsave(&drv_data->lock, flags); | |
946 | ||
947 | if (drv_data->run == QUEUE_STOPPED) { | |
948 | spin_unlock_irqrestore(&drv_data->lock, flags); | |
949 | return -ESHUTDOWN; | |
950 | } | |
951 | ||
952 | msg->actual_length = 0; | |
953 | msg->status = -EINPROGRESS; | |
954 | msg->state = START_STATE; | |
955 | ||
88b40369 | 956 | dev_dbg(&spi->dev, "adding an msg in transfer() \n"); |
a5f6abd4 WB |
957 | list_add_tail(&msg->queue, &drv_data->queue); |
958 | ||
959 | if (drv_data->run == QUEUE_RUNNING && !drv_data->busy) | |
960 | queue_work(drv_data->workqueue, &drv_data->pump_messages); | |
961 | ||
962 | spin_unlock_irqrestore(&drv_data->lock, flags); | |
963 | ||
964 | return 0; | |
965 | } | |
966 | ||
967 | /* first setup for new devices */ | |
968 | static int setup(struct spi_device *spi) | |
969 | { | |
970 | struct bfin5xx_spi_chip *chip_info = NULL; | |
971 | struct chip_data *chip; | |
972 | struct driver_data *drv_data = spi_master_get_devdata(spi->master); | |
973 | u8 spi_flg; | |
974 | ||
975 | /* Abort device setup if requested features are not supported */ | |
976 | if (spi->mode & ~(SPI_CPOL | SPI_CPHA | SPI_LSB_FIRST)) { | |
977 | dev_err(&spi->dev, "requested mode not fully supported\n"); | |
978 | return -EINVAL; | |
979 | } | |
980 | ||
981 | /* Zero (the default) here means 8 bits */ | |
982 | if (!spi->bits_per_word) | |
983 | spi->bits_per_word = 8; | |
984 | ||
985 | if (spi->bits_per_word != 8 && spi->bits_per_word != 16) | |
986 | return -EINVAL; | |
987 | ||
988 | /* Only alloc (or use chip_info) on first setup */ | |
989 | chip = spi_get_ctldata(spi); | |
990 | if (chip == NULL) { | |
991 | chip = kzalloc(sizeof(struct chip_data), GFP_KERNEL); | |
992 | if (!chip) | |
993 | return -ENOMEM; | |
994 | ||
995 | chip->enable_dma = 0; | |
996 | chip_info = spi->controller_data; | |
997 | } | |
998 | ||
999 | /* chip_info isn't always needed */ | |
1000 | if (chip_info) { | |
1001 | chip->enable_dma = chip_info->enable_dma != 0 | |
1002 | && drv_data->master_info->enable_dma; | |
1003 | chip->ctl_reg = chip_info->ctl_reg; | |
1004 | chip->bits_per_word = chip_info->bits_per_word; | |
1005 | chip->cs_change_per_word = chip_info->cs_change_per_word; | |
1006 | chip->cs_chg_udelay = chip_info->cs_chg_udelay; | |
1007 | } | |
1008 | ||
1009 | /* translate common spi framework into our register */ | |
1010 | if (spi->mode & SPI_CPOL) | |
1011 | chip->ctl_reg |= CPOL; | |
1012 | if (spi->mode & SPI_CPHA) | |
1013 | chip->ctl_reg |= CPHA; | |
1014 | if (spi->mode & SPI_LSB_FIRST) | |
1015 | chip->ctl_reg |= LSBF; | |
1016 | /* we dont support running in slave mode (yet?) */ | |
1017 | chip->ctl_reg |= MSTR; | |
1018 | ||
1019 | /* | |
1020 | * if any one SPI chip is registered and wants DMA, request the | |
1021 | * DMA channel for it | |
1022 | */ | |
1023 | if (chip->enable_dma && !dma_requested) { | |
1024 | /* register dma irq handler */ | |
1025 | if (request_dma(CH_SPI, "BF53x_SPI_DMA") < 0) { | |
88b40369 BW |
1026 | dev_dbg(&spi->dev, |
1027 | "Unable to request BlackFin SPI DMA channel\n"); | |
a5f6abd4 WB |
1028 | return -ENODEV; |
1029 | } | |
1030 | if (set_dma_callback(CH_SPI, (void *)dma_irq_handler, drv_data) | |
1031 | < 0) { | |
88b40369 | 1032 | dev_dbg(&spi->dev, "Unable to set dma callback\n"); |
a5f6abd4 WB |
1033 | return -EPERM; |
1034 | } | |
1035 | dma_disable_irq(CH_SPI); | |
1036 | dma_requested = 1; | |
1037 | } | |
1038 | ||
1039 | /* | |
1040 | * Notice: for blackfin, the speed_hz is the value of register | |
1041 | * SPI_BAUD, not the real baudrate | |
1042 | */ | |
1043 | chip->baud = hz_to_spi_baud(spi->max_speed_hz); | |
1044 | spi_flg = ~(1 << (spi->chip_select)); | |
1045 | chip->flag = ((u16) spi_flg << 8) | (1 << (spi->chip_select)); | |
1046 | chip->chip_select_num = spi->chip_select; | |
1047 | ||
1048 | switch (chip->bits_per_word) { | |
1049 | case 8: | |
1050 | chip->n_bytes = 1; | |
1051 | chip->width = CFG_SPI_WORDSIZE8; | |
1052 | chip->read = chip->cs_change_per_word ? | |
1053 | u8_cs_chg_reader : u8_reader; | |
1054 | chip->write = chip->cs_change_per_word ? | |
1055 | u8_cs_chg_writer : u8_writer; | |
1056 | chip->duplex = chip->cs_change_per_word ? | |
1057 | u8_cs_chg_duplex : u8_duplex; | |
1058 | break; | |
1059 | ||
1060 | case 16: | |
1061 | chip->n_bytes = 2; | |
1062 | chip->width = CFG_SPI_WORDSIZE16; | |
1063 | chip->read = chip->cs_change_per_word ? | |
1064 | u16_cs_chg_reader : u16_reader; | |
1065 | chip->write = chip->cs_change_per_word ? | |
1066 | u16_cs_chg_writer : u16_writer; | |
1067 | chip->duplex = chip->cs_change_per_word ? | |
1068 | u16_cs_chg_duplex : u16_duplex; | |
1069 | break; | |
1070 | ||
1071 | default: | |
1072 | dev_err(&spi->dev, "%d bits_per_word is not supported\n", | |
1073 | chip->bits_per_word); | |
1074 | kfree(chip); | |
1075 | return -ENODEV; | |
1076 | } | |
1077 | ||
898eb71c | 1078 | dev_dbg(&spi->dev, "setup spi chip %s, width is %d, dma is %d\n", |
a5f6abd4 | 1079 | spi->modalias, chip->width, chip->enable_dma); |
88b40369 | 1080 | dev_dbg(&spi->dev, "ctl_reg is 0x%x, flag_reg is 0x%x\n", |
a5f6abd4 WB |
1081 | chip->ctl_reg, chip->flag); |
1082 | ||
1083 | spi_set_ctldata(spi, chip); | |
1084 | ||
1085 | return 0; | |
1086 | } | |
1087 | ||
1088 | /* | |
1089 | * callback for spi framework. | |
1090 | * clean driver specific data | |
1091 | */ | |
88b40369 | 1092 | static void cleanup(struct spi_device *spi) |
a5f6abd4 | 1093 | { |
27bb9e79 | 1094 | struct chip_data *chip = spi_get_ctldata(spi); |
a5f6abd4 WB |
1095 | |
1096 | kfree(chip); | |
1097 | } | |
1098 | ||
1099 | static inline int init_queue(struct driver_data *drv_data) | |
1100 | { | |
1101 | INIT_LIST_HEAD(&drv_data->queue); | |
1102 | spin_lock_init(&drv_data->lock); | |
1103 | ||
1104 | drv_data->run = QUEUE_STOPPED; | |
1105 | drv_data->busy = 0; | |
1106 | ||
1107 | /* init transfer tasklet */ | |
1108 | tasklet_init(&drv_data->pump_transfers, | |
1109 | pump_transfers, (unsigned long)drv_data); | |
1110 | ||
1111 | /* init messages workqueue */ | |
1112 | INIT_WORK(&drv_data->pump_messages, pump_messages); | |
1113 | drv_data->workqueue = | |
49dce689 | 1114 | create_singlethread_workqueue(drv_data->master->dev.parent->bus_id); |
a5f6abd4 WB |
1115 | if (drv_data->workqueue == NULL) |
1116 | return -EBUSY; | |
1117 | ||
1118 | return 0; | |
1119 | } | |
1120 | ||
1121 | static inline int start_queue(struct driver_data *drv_data) | |
1122 | { | |
1123 | unsigned long flags; | |
1124 | ||
1125 | spin_lock_irqsave(&drv_data->lock, flags); | |
1126 | ||
1127 | if (drv_data->run == QUEUE_RUNNING || drv_data->busy) { | |
1128 | spin_unlock_irqrestore(&drv_data->lock, flags); | |
1129 | return -EBUSY; | |
1130 | } | |
1131 | ||
1132 | drv_data->run = QUEUE_RUNNING; | |
1133 | drv_data->cur_msg = NULL; | |
1134 | drv_data->cur_transfer = NULL; | |
1135 | drv_data->cur_chip = NULL; | |
1136 | spin_unlock_irqrestore(&drv_data->lock, flags); | |
1137 | ||
1138 | queue_work(drv_data->workqueue, &drv_data->pump_messages); | |
1139 | ||
1140 | return 0; | |
1141 | } | |
1142 | ||
1143 | static inline int stop_queue(struct driver_data *drv_data) | |
1144 | { | |
1145 | unsigned long flags; | |
1146 | unsigned limit = 500; | |
1147 | int status = 0; | |
1148 | ||
1149 | spin_lock_irqsave(&drv_data->lock, flags); | |
1150 | ||
1151 | /* | |
1152 | * This is a bit lame, but is optimized for the common execution path. | |
1153 | * A wait_queue on the drv_data->busy could be used, but then the common | |
1154 | * execution path (pump_messages) would be required to call wake_up or | |
1155 | * friends on every SPI message. Do this instead | |
1156 | */ | |
1157 | drv_data->run = QUEUE_STOPPED; | |
1158 | while (!list_empty(&drv_data->queue) && drv_data->busy && limit--) { | |
1159 | spin_unlock_irqrestore(&drv_data->lock, flags); | |
1160 | msleep(10); | |
1161 | spin_lock_irqsave(&drv_data->lock, flags); | |
1162 | } | |
1163 | ||
1164 | if (!list_empty(&drv_data->queue) || drv_data->busy) | |
1165 | status = -EBUSY; | |
1166 | ||
1167 | spin_unlock_irqrestore(&drv_data->lock, flags); | |
1168 | ||
1169 | return status; | |
1170 | } | |
1171 | ||
1172 | static inline int destroy_queue(struct driver_data *drv_data) | |
1173 | { | |
1174 | int status; | |
1175 | ||
1176 | status = stop_queue(drv_data); | |
1177 | if (status != 0) | |
1178 | return status; | |
1179 | ||
1180 | destroy_workqueue(drv_data->workqueue); | |
1181 | ||
1182 | return 0; | |
1183 | } | |
1184 | ||
cc2f81a6 MH |
1185 | static int setup_pin_mux(int action) |
1186 | { | |
1187 | ||
1188 | u16 pin_req[] = {P_SPI0_SCK, P_SPI0_MISO, P_SPI0_MOSI, 0}; | |
1189 | ||
1190 | if (action) { | |
1191 | if (peripheral_request_list(pin_req, DRV_NAME)) | |
1192 | return -EFAULT; | |
1193 | } else { | |
1194 | peripheral_free_list(pin_req); | |
1195 | } | |
1196 | ||
1197 | return 0; | |
1198 | } | |
1199 | ||
a5f6abd4 WB |
1200 | static int __init bfin5xx_spi_probe(struct platform_device *pdev) |
1201 | { | |
1202 | struct device *dev = &pdev->dev; | |
1203 | struct bfin5xx_spi_master *platform_info; | |
1204 | struct spi_master *master; | |
1205 | struct driver_data *drv_data = 0; | |
1206 | int status = 0; | |
1207 | ||
1208 | platform_info = dev->platform_data; | |
1209 | ||
1210 | /* Allocate master with space for drv_data */ | |
1211 | master = spi_alloc_master(dev, sizeof(struct driver_data) + 16); | |
1212 | if (!master) { | |
1213 | dev_err(&pdev->dev, "can not alloc spi_master\n"); | |
1214 | return -ENOMEM; | |
1215 | } | |
131b17d4 | 1216 | |
cc2f81a6 | 1217 | if (setup_pin_mux(1)) { |
131b17d4 | 1218 | dev_err(&pdev->dev, ": Requesting Peripherals failed\n"); |
cc2f81a6 | 1219 | goto out_error; |
131b17d4 BW |
1220 | } |
1221 | ||
a5f6abd4 WB |
1222 | drv_data = spi_master_get_devdata(master); |
1223 | drv_data->master = master; | |
1224 | drv_data->master_info = platform_info; | |
1225 | drv_data->pdev = pdev; | |
1226 | ||
1227 | master->bus_num = pdev->id; | |
1228 | master->num_chipselect = platform_info->num_chipselect; | |
1229 | master->cleanup = cleanup; | |
1230 | master->setup = setup; | |
1231 | master->transfer = transfer; | |
1232 | ||
1233 | /* Initial and start queue */ | |
1234 | status = init_queue(drv_data); | |
1235 | if (status != 0) { | |
1236 | dev_err(&pdev->dev, "problem initializing queue\n"); | |
1237 | goto out_error_queue_alloc; | |
1238 | } | |
1239 | status = start_queue(drv_data); | |
1240 | if (status != 0) { | |
1241 | dev_err(&pdev->dev, "problem starting queue\n"); | |
1242 | goto out_error_queue_alloc; | |
1243 | } | |
1244 | ||
1245 | /* Register with the SPI framework */ | |
1246 | platform_set_drvdata(pdev, drv_data); | |
1247 | status = spi_register_master(master); | |
1248 | if (status != 0) { | |
1249 | dev_err(&pdev->dev, "problem registering spi master\n"); | |
1250 | goto out_error_queue_alloc; | |
1251 | } | |
88b40369 | 1252 | dev_dbg(&pdev->dev, "controller probe successfully\n"); |
a5f6abd4 WB |
1253 | return status; |
1254 | ||
cc2f81a6 | 1255 | out_error_queue_alloc: |
a5f6abd4 | 1256 | destroy_queue(drv_data); |
cc2f81a6 | 1257 | out_error: |
a5f6abd4 | 1258 | spi_master_put(master); |
cc2f81a6 | 1259 | |
a5f6abd4 WB |
1260 | return status; |
1261 | } | |
1262 | ||
1263 | /* stop hardware and remove the driver */ | |
1264 | static int __devexit bfin5xx_spi_remove(struct platform_device *pdev) | |
1265 | { | |
1266 | struct driver_data *drv_data = platform_get_drvdata(pdev); | |
1267 | int status = 0; | |
1268 | ||
1269 | if (!drv_data) | |
1270 | return 0; | |
1271 | ||
1272 | /* Remove the queue */ | |
1273 | status = destroy_queue(drv_data); | |
1274 | if (status != 0) | |
1275 | return status; | |
1276 | ||
1277 | /* Disable the SSP at the peripheral and SOC level */ | |
1278 | bfin_spi_disable(drv_data); | |
1279 | ||
1280 | /* Release DMA */ | |
1281 | if (drv_data->master_info->enable_dma) { | |
1282 | if (dma_channel_active(CH_SPI)) | |
1283 | free_dma(CH_SPI); | |
1284 | } | |
1285 | ||
1286 | /* Disconnect from the SPI framework */ | |
1287 | spi_unregister_master(drv_data->master); | |
1288 | ||
cc2f81a6 MH |
1289 | setup_pin_mux(0); |
1290 | ||
a5f6abd4 WB |
1291 | /* Prevent double remove */ |
1292 | platform_set_drvdata(pdev, NULL); | |
1293 | ||
1294 | return 0; | |
1295 | } | |
1296 | ||
1297 | #ifdef CONFIG_PM | |
1298 | static int bfin5xx_spi_suspend(struct platform_device *pdev, pm_message_t state) | |
1299 | { | |
1300 | struct driver_data *drv_data = platform_get_drvdata(pdev); | |
1301 | int status = 0; | |
1302 | ||
1303 | status = stop_queue(drv_data); | |
1304 | if (status != 0) | |
1305 | return status; | |
1306 | ||
1307 | /* stop hardware */ | |
1308 | bfin_spi_disable(drv_data); | |
1309 | ||
1310 | return 0; | |
1311 | } | |
1312 | ||
1313 | static int bfin5xx_spi_resume(struct platform_device *pdev) | |
1314 | { | |
1315 | struct driver_data *drv_data = platform_get_drvdata(pdev); | |
1316 | int status = 0; | |
1317 | ||
1318 | /* Enable the SPI interface */ | |
1319 | bfin_spi_enable(drv_data); | |
1320 | ||
1321 | /* Start the queue running */ | |
1322 | status = start_queue(drv_data); | |
1323 | if (status != 0) { | |
1324 | dev_err(&pdev->dev, "problem starting queue (%d)\n", status); | |
1325 | return status; | |
1326 | } | |
1327 | ||
1328 | return 0; | |
1329 | } | |
1330 | #else | |
1331 | #define bfin5xx_spi_suspend NULL | |
1332 | #define bfin5xx_spi_resume NULL | |
1333 | #endif /* CONFIG_PM */ | |
1334 | ||
fc3ba952 | 1335 | MODULE_ALIAS("bfin-spi-master"); /* for platform bus hotplug */ |
a5f6abd4 | 1336 | static struct platform_driver bfin5xx_spi_driver = { |
fc3ba952 | 1337 | .driver = { |
88b40369 BW |
1338 | .name = "bfin-spi-master", |
1339 | .owner = THIS_MODULE, | |
1340 | }, | |
1341 | .suspend = bfin5xx_spi_suspend, | |
1342 | .resume = bfin5xx_spi_resume, | |
1343 | .remove = __devexit_p(bfin5xx_spi_remove), | |
a5f6abd4 WB |
1344 | }; |
1345 | ||
1346 | static int __init bfin5xx_spi_init(void) | |
1347 | { | |
88b40369 | 1348 | return platform_driver_probe(&bfin5xx_spi_driver, bfin5xx_spi_probe); |
a5f6abd4 | 1349 | } |
a5f6abd4 WB |
1350 | module_init(bfin5xx_spi_init); |
1351 | ||
1352 | static void __exit bfin5xx_spi_exit(void) | |
1353 | { | |
1354 | platform_driver_unregister(&bfin5xx_spi_driver); | |
1355 | } | |
a5f6abd4 | 1356 | module_exit(bfin5xx_spi_exit); |