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b5f3294f SH |
1 | /* |
2 | * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved. | |
3 | * Copyright (C) 2008 Juergen Beisert | |
4 | * | |
5 | * This program is free software; you can redistribute it and/or | |
6 | * modify it under the terms of the GNU General Public License | |
7 | * as published by the Free Software Foundation; either version 2 | |
8 | * of the License, or (at your option) any later version. | |
9 | * This program is distributed in the hope that it will be useful, | |
10 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
11 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
12 | * GNU General Public License for more details. | |
13 | * | |
14 | * You should have received a copy of the GNU General Public License | |
15 | * along with this program; if not, write to the | |
16 | * Free Software Foundation | |
17 | * 51 Franklin Street, Fifth Floor | |
18 | * Boston, MA 02110-1301, USA. | |
19 | */ | |
20 | ||
21 | #include <linux/clk.h> | |
22 | #include <linux/completion.h> | |
23 | #include <linux/delay.h> | |
24 | #include <linux/err.h> | |
25 | #include <linux/gpio.h> | |
26 | #include <linux/init.h> | |
27 | #include <linux/interrupt.h> | |
28 | #include <linux/io.h> | |
29 | #include <linux/irq.h> | |
30 | #include <linux/kernel.h> | |
31 | #include <linux/module.h> | |
32 | #include <linux/platform_device.h> | |
5a0e3ad6 | 33 | #include <linux/slab.h> |
b5f3294f SH |
34 | #include <linux/spi/spi.h> |
35 | #include <linux/spi/spi_bitbang.h> | |
36 | #include <linux/types.h> | |
37 | ||
38 | #include <mach/spi.h> | |
39 | ||
40 | #define DRIVER_NAME "spi_imx" | |
41 | ||
42 | #define MXC_CSPIRXDATA 0x00 | |
43 | #define MXC_CSPITXDATA 0x04 | |
44 | #define MXC_CSPICTRL 0x08 | |
45 | #define MXC_CSPIINT 0x0c | |
46 | #define MXC_RESET 0x1c | |
47 | ||
ce1807b2 DM |
48 | #define MX3_CSPISTAT 0x14 |
49 | #define MX3_CSPISTAT_RR (1 << 3) | |
50 | ||
b5f3294f SH |
51 | /* generic defines to abstract from the different register layouts */ |
52 | #define MXC_INT_RR (1 << 0) /* Receive data ready interrupt */ | |
53 | #define MXC_INT_TE (1 << 1) /* Transmit FIFO empty interrupt */ | |
54 | ||
6cdeb002 | 55 | struct spi_imx_config { |
b5f3294f SH |
56 | unsigned int speed_hz; |
57 | unsigned int bpw; | |
58 | unsigned int mode; | |
3b2aa89e | 59 | u8 cs; |
b5f3294f SH |
60 | }; |
61 | ||
f4ba6315 UKK |
62 | enum spi_imx_devtype { |
63 | SPI_IMX_VER_IMX1, | |
64 | SPI_IMX_VER_0_0, | |
65 | SPI_IMX_VER_0_4, | |
66 | SPI_IMX_VER_0_5, | |
67 | SPI_IMX_VER_0_7, | |
0b599603 | 68 | SPI_IMX_VER_2_3, |
f4ba6315 UKK |
69 | }; |
70 | ||
71 | struct spi_imx_data; | |
72 | ||
73 | struct spi_imx_devtype_data { | |
74 | void (*intctrl)(struct spi_imx_data *, int); | |
75 | int (*config)(struct spi_imx_data *, struct spi_imx_config *); | |
76 | void (*trigger)(struct spi_imx_data *); | |
77 | int (*rx_available)(struct spi_imx_data *); | |
1723e66b | 78 | void (*reset)(struct spi_imx_data *); |
6ff554e0 | 79 | unsigned int fifosize; |
f4ba6315 UKK |
80 | }; |
81 | ||
6cdeb002 | 82 | struct spi_imx_data { |
b5f3294f SH |
83 | struct spi_bitbang bitbang; |
84 | ||
85 | struct completion xfer_done; | |
86 | void *base; | |
87 | int irq; | |
88 | struct clk *clk; | |
89 | unsigned long spi_clk; | |
90 | int *chipselect; | |
91 | ||
92 | unsigned int count; | |
6cdeb002 UKK |
93 | void (*tx)(struct spi_imx_data *); |
94 | void (*rx)(struct spi_imx_data *); | |
b5f3294f SH |
95 | void *rx_buf; |
96 | const void *tx_buf; | |
97 | unsigned int txfifo; /* number of words pushed in tx FIFO */ | |
98 | ||
f4ba6315 | 99 | struct spi_imx_devtype_data devtype_data; |
b5f3294f SH |
100 | }; |
101 | ||
102 | #define MXC_SPI_BUF_RX(type) \ | |
6cdeb002 | 103 | static void spi_imx_buf_rx_##type(struct spi_imx_data *spi_imx) \ |
b5f3294f | 104 | { \ |
6cdeb002 | 105 | unsigned int val = readl(spi_imx->base + MXC_CSPIRXDATA); \ |
b5f3294f | 106 | \ |
6cdeb002 UKK |
107 | if (spi_imx->rx_buf) { \ |
108 | *(type *)spi_imx->rx_buf = val; \ | |
109 | spi_imx->rx_buf += sizeof(type); \ | |
b5f3294f SH |
110 | } \ |
111 | } | |
112 | ||
113 | #define MXC_SPI_BUF_TX(type) \ | |
6cdeb002 | 114 | static void spi_imx_buf_tx_##type(struct spi_imx_data *spi_imx) \ |
b5f3294f SH |
115 | { \ |
116 | type val = 0; \ | |
117 | \ | |
6cdeb002 UKK |
118 | if (spi_imx->tx_buf) { \ |
119 | val = *(type *)spi_imx->tx_buf; \ | |
120 | spi_imx->tx_buf += sizeof(type); \ | |
b5f3294f SH |
121 | } \ |
122 | \ | |
6cdeb002 | 123 | spi_imx->count -= sizeof(type); \ |
b5f3294f | 124 | \ |
6cdeb002 | 125 | writel(val, spi_imx->base + MXC_CSPITXDATA); \ |
b5f3294f SH |
126 | } |
127 | ||
128 | MXC_SPI_BUF_RX(u8) | |
129 | MXC_SPI_BUF_TX(u8) | |
130 | MXC_SPI_BUF_RX(u16) | |
131 | MXC_SPI_BUF_TX(u16) | |
132 | MXC_SPI_BUF_RX(u32) | |
133 | MXC_SPI_BUF_TX(u32) | |
134 | ||
135 | /* First entry is reserved, second entry is valid only if SDHC_SPIEN is set | |
136 | * (which is currently not the case in this driver) | |
137 | */ | |
138 | static int mxc_clkdivs[] = {0, 3, 4, 6, 8, 12, 16, 24, 32, 48, 64, 96, 128, 192, | |
139 | 256, 384, 512, 768, 1024}; | |
140 | ||
141 | /* MX21, MX27 */ | |
6cdeb002 | 142 | static unsigned int spi_imx_clkdiv_1(unsigned int fin, |
b5f3294f SH |
143 | unsigned int fspi) |
144 | { | |
145 | int i, max; | |
146 | ||
147 | if (cpu_is_mx21()) | |
148 | max = 18; | |
149 | else | |
150 | max = 16; | |
151 | ||
152 | for (i = 2; i < max; i++) | |
153 | if (fspi * mxc_clkdivs[i] >= fin) | |
154 | return i; | |
155 | ||
156 | return max; | |
157 | } | |
158 | ||
0b599603 | 159 | /* MX1, MX31, MX35, MX51 CSPI */ |
6cdeb002 | 160 | static unsigned int spi_imx_clkdiv_2(unsigned int fin, |
b5f3294f SH |
161 | unsigned int fspi) |
162 | { | |
163 | int i, div = 4; | |
164 | ||
165 | for (i = 0; i < 7; i++) { | |
166 | if (fspi * div >= fin) | |
167 | return i; | |
168 | div <<= 1; | |
169 | } | |
170 | ||
171 | return 7; | |
172 | } | |
173 | ||
0b599603 UKK |
174 | #define SPI_IMX2_3_CTRL 0x08 |
175 | #define SPI_IMX2_3_CTRL_ENABLE (1 << 0) | |
176 | #define SPI_IMX2_3_CTRL_XCH (1 << 2) | |
f020c39e | 177 | #define SPI_IMX2_3_CTRL_MODE_MASK (0xf << 4) |
0b599603 UKK |
178 | #define SPI_IMX2_3_CTRL_POSTDIV_OFFSET 8 |
179 | #define SPI_IMX2_3_CTRL_PREDIV_OFFSET 12 | |
180 | #define SPI_IMX2_3_CTRL_CS(cs) ((cs) << 18) | |
181 | #define SPI_IMX2_3_CTRL_BL_OFFSET 20 | |
182 | ||
183 | #define SPI_IMX2_3_CONFIG 0x0c | |
184 | #define SPI_IMX2_3_CONFIG_SCLKPHA(cs) (1 << ((cs) + 0)) | |
185 | #define SPI_IMX2_3_CONFIG_SCLKPOL(cs) (1 << ((cs) + 4)) | |
186 | #define SPI_IMX2_3_CONFIG_SBBCTRL(cs) (1 << ((cs) + 8)) | |
187 | #define SPI_IMX2_3_CONFIG_SSBPOL(cs) (1 << ((cs) + 12)) | |
188 | ||
189 | #define SPI_IMX2_3_INT 0x10 | |
190 | #define SPI_IMX2_3_INT_TEEN (1 << 0) | |
191 | #define SPI_IMX2_3_INT_RREN (1 << 3) | |
192 | ||
193 | #define SPI_IMX2_3_STAT 0x18 | |
194 | #define SPI_IMX2_3_STAT_RR (1 << 3) | |
195 | ||
196 | /* MX51 eCSPI */ | |
197 | static unsigned int spi_imx2_3_clkdiv(unsigned int fin, unsigned int fspi) | |
198 | { | |
199 | /* | |
200 | * there are two 4-bit dividers, the pre-divider divides by | |
201 | * $pre, the post-divider by 2^$post | |
202 | */ | |
203 | unsigned int pre, post; | |
204 | ||
205 | if (unlikely(fspi > fin)) | |
206 | return 0; | |
207 | ||
208 | post = fls(fin) - fls(fspi); | |
209 | if (fin > fspi << post) | |
210 | post++; | |
211 | ||
212 | /* now we have: (fin <= fspi << post) with post being minimal */ | |
213 | ||
214 | post = max(4U, post) - 4; | |
215 | if (unlikely(post > 0xf)) { | |
216 | pr_err("%s: cannot set clock freq: %u (base freq: %u)\n", | |
217 | __func__, fspi, fin); | |
218 | return 0xff; | |
219 | } | |
220 | ||
221 | pre = DIV_ROUND_UP(fin, fspi << post) - 1; | |
222 | ||
223 | pr_debug("%s: fin: %u, fspi: %u, post: %u, pre: %u\n", | |
224 | __func__, fin, fspi, post, pre); | |
225 | return (pre << SPI_IMX2_3_CTRL_PREDIV_OFFSET) | | |
226 | (post << SPI_IMX2_3_CTRL_POSTDIV_OFFSET); | |
227 | } | |
228 | ||
229 | static void __maybe_unused spi_imx2_3_intctrl(struct spi_imx_data *spi_imx, int enable) | |
230 | { | |
231 | unsigned val = 0; | |
232 | ||
233 | if (enable & MXC_INT_TE) | |
234 | val |= SPI_IMX2_3_INT_TEEN; | |
235 | ||
236 | if (enable & MXC_INT_RR) | |
237 | val |= SPI_IMX2_3_INT_RREN; | |
238 | ||
239 | writel(val, spi_imx->base + SPI_IMX2_3_INT); | |
240 | } | |
241 | ||
242 | static void __maybe_unused spi_imx2_3_trigger(struct spi_imx_data *spi_imx) | |
243 | { | |
244 | u32 reg; | |
245 | ||
246 | reg = readl(spi_imx->base + SPI_IMX2_3_CTRL); | |
247 | reg |= SPI_IMX2_3_CTRL_XCH; | |
248 | writel(reg, spi_imx->base + SPI_IMX2_3_CTRL); | |
249 | } | |
250 | ||
251 | static int __maybe_unused spi_imx2_3_config(struct spi_imx_data *spi_imx, | |
252 | struct spi_imx_config *config) | |
253 | { | |
254 | u32 ctrl = SPI_IMX2_3_CTRL_ENABLE, cfg = 0; | |
255 | ||
f020c39e SH |
256 | /* |
257 | * The hardware seems to have a race condition when changing modes. The | |
258 | * current assumption is that the selection of the channel arrives | |
259 | * earlier in the hardware than the mode bits when they are written at | |
260 | * the same time. | |
261 | * So set master mode for all channels as we do not support slave mode. | |
262 | */ | |
263 | ctrl |= SPI_IMX2_3_CTRL_MODE_MASK; | |
0b599603 UKK |
264 | |
265 | /* set clock speed */ | |
266 | ctrl |= spi_imx2_3_clkdiv(spi_imx->spi_clk, config->speed_hz); | |
267 | ||
268 | /* set chip select to use */ | |
269 | ctrl |= SPI_IMX2_3_CTRL_CS(config->cs); | |
270 | ||
271 | ctrl |= (config->bpw - 1) << SPI_IMX2_3_CTRL_BL_OFFSET; | |
272 | ||
273 | cfg |= SPI_IMX2_3_CONFIG_SBBCTRL(config->cs); | |
274 | ||
275 | if (config->mode & SPI_CPHA) | |
276 | cfg |= SPI_IMX2_3_CONFIG_SCLKPHA(config->cs); | |
277 | ||
278 | if (config->mode & SPI_CPOL) | |
279 | cfg |= SPI_IMX2_3_CONFIG_SCLKPOL(config->cs); | |
280 | ||
281 | if (config->mode & SPI_CS_HIGH) | |
282 | cfg |= SPI_IMX2_3_CONFIG_SSBPOL(config->cs); | |
283 | ||
284 | writel(ctrl, spi_imx->base + SPI_IMX2_3_CTRL); | |
285 | writel(cfg, spi_imx->base + SPI_IMX2_3_CONFIG); | |
286 | ||
287 | return 0; | |
288 | } | |
289 | ||
290 | static int __maybe_unused spi_imx2_3_rx_available(struct spi_imx_data *spi_imx) | |
291 | { | |
292 | return readl(spi_imx->base + SPI_IMX2_3_STAT) & SPI_IMX2_3_STAT_RR; | |
293 | } | |
294 | ||
295 | static void __maybe_unused spi_imx2_3_reset(struct spi_imx_data *spi_imx) | |
296 | { | |
297 | /* drain receive buffer */ | |
298 | while (spi_imx2_3_rx_available(spi_imx)) | |
299 | readl(spi_imx->base + MXC_CSPIRXDATA); | |
300 | } | |
301 | ||
b5f3294f SH |
302 | #define MX31_INTREG_TEEN (1 << 0) |
303 | #define MX31_INTREG_RREN (1 << 3) | |
304 | ||
305 | #define MX31_CSPICTRL_ENABLE (1 << 0) | |
306 | #define MX31_CSPICTRL_MASTER (1 << 1) | |
307 | #define MX31_CSPICTRL_XCH (1 << 2) | |
308 | #define MX31_CSPICTRL_POL (1 << 4) | |
309 | #define MX31_CSPICTRL_PHA (1 << 5) | |
310 | #define MX31_CSPICTRL_SSCTL (1 << 6) | |
311 | #define MX31_CSPICTRL_SSPOL (1 << 7) | |
312 | #define MX31_CSPICTRL_BC_SHIFT 8 | |
313 | #define MX35_CSPICTRL_BL_SHIFT 20 | |
314 | #define MX31_CSPICTRL_CS_SHIFT 24 | |
315 | #define MX35_CSPICTRL_CS_SHIFT 12 | |
316 | #define MX31_CSPICTRL_DR_SHIFT 16 | |
317 | ||
318 | #define MX31_CSPISTATUS 0x14 | |
319 | #define MX31_STATUS_RR (1 << 3) | |
320 | ||
321 | /* These functions also work for the i.MX35, but be aware that | |
322 | * the i.MX35 has a slightly different register layout for bits | |
323 | * we do not use here. | |
324 | */ | |
f4ba6315 | 325 | static void __maybe_unused mx31_intctrl(struct spi_imx_data *spi_imx, int enable) |
b5f3294f SH |
326 | { |
327 | unsigned int val = 0; | |
328 | ||
329 | if (enable & MXC_INT_TE) | |
330 | val |= MX31_INTREG_TEEN; | |
331 | if (enable & MXC_INT_RR) | |
332 | val |= MX31_INTREG_RREN; | |
333 | ||
6cdeb002 | 334 | writel(val, spi_imx->base + MXC_CSPIINT); |
b5f3294f SH |
335 | } |
336 | ||
f4ba6315 | 337 | static void __maybe_unused mx31_trigger(struct spi_imx_data *spi_imx) |
b5f3294f SH |
338 | { |
339 | unsigned int reg; | |
340 | ||
6cdeb002 | 341 | reg = readl(spi_imx->base + MXC_CSPICTRL); |
b5f3294f | 342 | reg |= MX31_CSPICTRL_XCH; |
6cdeb002 | 343 | writel(reg, spi_imx->base + MXC_CSPICTRL); |
b5f3294f SH |
344 | } |
345 | ||
1723e66b | 346 | static int __maybe_unused spi_imx0_4_config(struct spi_imx_data *spi_imx, |
6cdeb002 | 347 | struct spi_imx_config *config) |
b5f3294f SH |
348 | { |
349 | unsigned int reg = MX31_CSPICTRL_ENABLE | MX31_CSPICTRL_MASTER; | |
3b2aa89e | 350 | int cs = spi_imx->chipselect[config->cs]; |
b5f3294f | 351 | |
6cdeb002 | 352 | reg |= spi_imx_clkdiv_2(spi_imx->spi_clk, config->speed_hz) << |
b5f3294f SH |
353 | MX31_CSPICTRL_DR_SHIFT; |
354 | ||
1723e66b | 355 | reg |= (config->bpw - 1) << MX31_CSPICTRL_BC_SHIFT; |
b5f3294f SH |
356 | |
357 | if (config->mode & SPI_CPHA) | |
358 | reg |= MX31_CSPICTRL_PHA; | |
359 | if (config->mode & SPI_CPOL) | |
360 | reg |= MX31_CSPICTRL_POL; | |
361 | if (config->mode & SPI_CS_HIGH) | |
362 | reg |= MX31_CSPICTRL_SSPOL; | |
3b2aa89e UKK |
363 | if (cs < 0) |
364 | reg |= (cs + 32) << MX31_CSPICTRL_CS_SHIFT; | |
b5f3294f | 365 | |
6cdeb002 | 366 | writel(reg, spi_imx->base + MXC_CSPICTRL); |
b5f3294f SH |
367 | |
368 | return 0; | |
369 | } | |
370 | ||
1723e66b UKK |
371 | static int __maybe_unused spi_imx0_7_config(struct spi_imx_data *spi_imx, |
372 | struct spi_imx_config *config) | |
373 | { | |
374 | unsigned int reg = MX31_CSPICTRL_ENABLE | MX31_CSPICTRL_MASTER; | |
3b2aa89e | 375 | int cs = spi_imx->chipselect[config->cs]; |
1723e66b UKK |
376 | |
377 | reg |= spi_imx_clkdiv_2(spi_imx->spi_clk, config->speed_hz) << | |
378 | MX31_CSPICTRL_DR_SHIFT; | |
379 | ||
380 | reg |= (config->bpw - 1) << MX35_CSPICTRL_BL_SHIFT; | |
381 | reg |= MX31_CSPICTRL_SSCTL; | |
382 | ||
383 | if (config->mode & SPI_CPHA) | |
384 | reg |= MX31_CSPICTRL_PHA; | |
385 | if (config->mode & SPI_CPOL) | |
386 | reg |= MX31_CSPICTRL_POL; | |
387 | if (config->mode & SPI_CS_HIGH) | |
388 | reg |= MX31_CSPICTRL_SSPOL; | |
3b2aa89e UKK |
389 | if (cs < 0) |
390 | reg |= (cs + 32) << MX35_CSPICTRL_CS_SHIFT; | |
1723e66b UKK |
391 | |
392 | writel(reg, spi_imx->base + MXC_CSPICTRL); | |
393 | ||
394 | return 0; | |
395 | } | |
396 | ||
f4ba6315 | 397 | static int __maybe_unused mx31_rx_available(struct spi_imx_data *spi_imx) |
b5f3294f | 398 | { |
6cdeb002 | 399 | return readl(spi_imx->base + MX31_CSPISTATUS) & MX31_STATUS_RR; |
b5f3294f SH |
400 | } |
401 | ||
1723e66b UKK |
402 | static void __maybe_unused spi_imx0_4_reset(struct spi_imx_data *spi_imx) |
403 | { | |
404 | /* drain receive buffer */ | |
405 | while (readl(spi_imx->base + MX3_CSPISTAT) & MX3_CSPISTAT_RR) | |
406 | readl(spi_imx->base + MXC_CSPIRXDATA); | |
407 | } | |
408 | ||
b5f3294f SH |
409 | #define MX27_INTREG_RR (1 << 4) |
410 | #define MX27_INTREG_TEEN (1 << 9) | |
411 | #define MX27_INTREG_RREN (1 << 13) | |
412 | ||
413 | #define MX27_CSPICTRL_POL (1 << 5) | |
414 | #define MX27_CSPICTRL_PHA (1 << 6) | |
415 | #define MX27_CSPICTRL_SSPOL (1 << 8) | |
416 | #define MX27_CSPICTRL_XCH (1 << 9) | |
417 | #define MX27_CSPICTRL_ENABLE (1 << 10) | |
418 | #define MX27_CSPICTRL_MASTER (1 << 11) | |
419 | #define MX27_CSPICTRL_DR_SHIFT 14 | |
420 | #define MX27_CSPICTRL_CS_SHIFT 19 | |
421 | ||
f4ba6315 | 422 | static void __maybe_unused mx27_intctrl(struct spi_imx_data *spi_imx, int enable) |
b5f3294f SH |
423 | { |
424 | unsigned int val = 0; | |
425 | ||
426 | if (enable & MXC_INT_TE) | |
427 | val |= MX27_INTREG_TEEN; | |
428 | if (enable & MXC_INT_RR) | |
429 | val |= MX27_INTREG_RREN; | |
430 | ||
6cdeb002 | 431 | writel(val, spi_imx->base + MXC_CSPIINT); |
b5f3294f SH |
432 | } |
433 | ||
f4ba6315 | 434 | static void __maybe_unused mx27_trigger(struct spi_imx_data *spi_imx) |
b5f3294f SH |
435 | { |
436 | unsigned int reg; | |
437 | ||
6cdeb002 | 438 | reg = readl(spi_imx->base + MXC_CSPICTRL); |
b5f3294f | 439 | reg |= MX27_CSPICTRL_XCH; |
6cdeb002 | 440 | writel(reg, spi_imx->base + MXC_CSPICTRL); |
b5f3294f SH |
441 | } |
442 | ||
f4ba6315 | 443 | static int __maybe_unused mx27_config(struct spi_imx_data *spi_imx, |
6cdeb002 | 444 | struct spi_imx_config *config) |
b5f3294f SH |
445 | { |
446 | unsigned int reg = MX27_CSPICTRL_ENABLE | MX27_CSPICTRL_MASTER; | |
3b2aa89e | 447 | int cs = spi_imx->chipselect[config->cs]; |
b5f3294f | 448 | |
6cdeb002 | 449 | reg |= spi_imx_clkdiv_1(spi_imx->spi_clk, config->speed_hz) << |
b5f3294f SH |
450 | MX27_CSPICTRL_DR_SHIFT; |
451 | reg |= config->bpw - 1; | |
452 | ||
453 | if (config->mode & SPI_CPHA) | |
454 | reg |= MX27_CSPICTRL_PHA; | |
455 | if (config->mode & SPI_CPOL) | |
456 | reg |= MX27_CSPICTRL_POL; | |
457 | if (config->mode & SPI_CS_HIGH) | |
458 | reg |= MX27_CSPICTRL_SSPOL; | |
3b2aa89e UKK |
459 | if (cs < 0) |
460 | reg |= (cs + 32) << MX27_CSPICTRL_CS_SHIFT; | |
b5f3294f | 461 | |
6cdeb002 | 462 | writel(reg, spi_imx->base + MXC_CSPICTRL); |
b5f3294f SH |
463 | |
464 | return 0; | |
465 | } | |
466 | ||
f4ba6315 | 467 | static int __maybe_unused mx27_rx_available(struct spi_imx_data *spi_imx) |
b5f3294f | 468 | { |
6cdeb002 | 469 | return readl(spi_imx->base + MXC_CSPIINT) & MX27_INTREG_RR; |
b5f3294f SH |
470 | } |
471 | ||
1723e66b UKK |
472 | static void __maybe_unused spi_imx0_0_reset(struct spi_imx_data *spi_imx) |
473 | { | |
474 | writel(1, spi_imx->base + MXC_RESET); | |
475 | } | |
476 | ||
b5f3294f SH |
477 | #define MX1_INTREG_RR (1 << 3) |
478 | #define MX1_INTREG_TEEN (1 << 8) | |
479 | #define MX1_INTREG_RREN (1 << 11) | |
480 | ||
481 | #define MX1_CSPICTRL_POL (1 << 4) | |
482 | #define MX1_CSPICTRL_PHA (1 << 5) | |
483 | #define MX1_CSPICTRL_XCH (1 << 8) | |
484 | #define MX1_CSPICTRL_ENABLE (1 << 9) | |
485 | #define MX1_CSPICTRL_MASTER (1 << 10) | |
486 | #define MX1_CSPICTRL_DR_SHIFT 13 | |
487 | ||
f4ba6315 | 488 | static void __maybe_unused mx1_intctrl(struct spi_imx_data *spi_imx, int enable) |
b5f3294f SH |
489 | { |
490 | unsigned int val = 0; | |
491 | ||
492 | if (enable & MXC_INT_TE) | |
493 | val |= MX1_INTREG_TEEN; | |
494 | if (enable & MXC_INT_RR) | |
495 | val |= MX1_INTREG_RREN; | |
496 | ||
6cdeb002 | 497 | writel(val, spi_imx->base + MXC_CSPIINT); |
b5f3294f SH |
498 | } |
499 | ||
f4ba6315 | 500 | static void __maybe_unused mx1_trigger(struct spi_imx_data *spi_imx) |
b5f3294f SH |
501 | { |
502 | unsigned int reg; | |
503 | ||
6cdeb002 | 504 | reg = readl(spi_imx->base + MXC_CSPICTRL); |
b5f3294f | 505 | reg |= MX1_CSPICTRL_XCH; |
6cdeb002 | 506 | writel(reg, spi_imx->base + MXC_CSPICTRL); |
b5f3294f SH |
507 | } |
508 | ||
f4ba6315 | 509 | static int __maybe_unused mx1_config(struct spi_imx_data *spi_imx, |
6cdeb002 | 510 | struct spi_imx_config *config) |
b5f3294f SH |
511 | { |
512 | unsigned int reg = MX1_CSPICTRL_ENABLE | MX1_CSPICTRL_MASTER; | |
513 | ||
6cdeb002 | 514 | reg |= spi_imx_clkdiv_2(spi_imx->spi_clk, config->speed_hz) << |
b5f3294f SH |
515 | MX1_CSPICTRL_DR_SHIFT; |
516 | reg |= config->bpw - 1; | |
517 | ||
518 | if (config->mode & SPI_CPHA) | |
519 | reg |= MX1_CSPICTRL_PHA; | |
520 | if (config->mode & SPI_CPOL) | |
521 | reg |= MX1_CSPICTRL_POL; | |
522 | ||
6cdeb002 | 523 | writel(reg, spi_imx->base + MXC_CSPICTRL); |
b5f3294f SH |
524 | |
525 | return 0; | |
526 | } | |
527 | ||
f4ba6315 | 528 | static int __maybe_unused mx1_rx_available(struct spi_imx_data *spi_imx) |
b5f3294f | 529 | { |
6cdeb002 | 530 | return readl(spi_imx->base + MXC_CSPIINT) & MX1_INTREG_RR; |
b5f3294f SH |
531 | } |
532 | ||
1723e66b UKK |
533 | static void __maybe_unused mx1_reset(struct spi_imx_data *spi_imx) |
534 | { | |
535 | writel(1, spi_imx->base + MXC_RESET); | |
536 | } | |
537 | ||
f4ba6315 UKK |
538 | /* |
539 | * These version numbers are taken from the Freescale driver. Unfortunately it | |
540 | * doesn't support i.MX1, so this entry doesn't match the scheme. :-( | |
541 | */ | |
542 | static struct spi_imx_devtype_data spi_imx_devtype_data[] __devinitdata = { | |
543 | #ifdef CONFIG_SPI_IMX_VER_IMX1 | |
544 | [SPI_IMX_VER_IMX1] = { | |
545 | .intctrl = mx1_intctrl, | |
546 | .config = mx1_config, | |
547 | .trigger = mx1_trigger, | |
548 | .rx_available = mx1_rx_available, | |
1723e66b | 549 | .reset = mx1_reset, |
6ff554e0 | 550 | .fifosize = 8, |
f4ba6315 UKK |
551 | }, |
552 | #endif | |
553 | #ifdef CONFIG_SPI_IMX_VER_0_0 | |
554 | [SPI_IMX_VER_0_0] = { | |
555 | .intctrl = mx27_intctrl, | |
556 | .config = mx27_config, | |
557 | .trigger = mx27_trigger, | |
558 | .rx_available = mx27_rx_available, | |
1723e66b | 559 | .reset = spi_imx0_0_reset, |
6ff554e0 | 560 | .fifosize = 8, |
f4ba6315 UKK |
561 | }, |
562 | #endif | |
563 | #ifdef CONFIG_SPI_IMX_VER_0_4 | |
564 | [SPI_IMX_VER_0_4] = { | |
565 | .intctrl = mx31_intctrl, | |
1723e66b | 566 | .config = spi_imx0_4_config, |
f4ba6315 UKK |
567 | .trigger = mx31_trigger, |
568 | .rx_available = mx31_rx_available, | |
1723e66b | 569 | .reset = spi_imx0_4_reset, |
6ff554e0 | 570 | .fifosize = 8, |
f4ba6315 UKK |
571 | }, |
572 | #endif | |
573 | #ifdef CONFIG_SPI_IMX_VER_0_7 | |
574 | [SPI_IMX_VER_0_7] = { | |
575 | .intctrl = mx31_intctrl, | |
1723e66b | 576 | .config = spi_imx0_7_config, |
f4ba6315 UKK |
577 | .trigger = mx31_trigger, |
578 | .rx_available = mx31_rx_available, | |
1723e66b | 579 | .reset = spi_imx0_4_reset, |
6ff554e0 | 580 | .fifosize = 8, |
f4ba6315 UKK |
581 | }, |
582 | #endif | |
0b599603 UKK |
583 | #ifdef CONFIG_SPI_IMX_VER_2_3 |
584 | [SPI_IMX_VER_2_3] = { | |
585 | .intctrl = spi_imx2_3_intctrl, | |
586 | .config = spi_imx2_3_config, | |
587 | .trigger = spi_imx2_3_trigger, | |
588 | .rx_available = spi_imx2_3_rx_available, | |
589 | .reset = spi_imx2_3_reset, | |
6ff554e0 | 590 | .fifosize = 64, |
0b599603 UKK |
591 | }, |
592 | #endif | |
f4ba6315 UKK |
593 | }; |
594 | ||
6cdeb002 | 595 | static void spi_imx_chipselect(struct spi_device *spi, int is_active) |
b5f3294f | 596 | { |
6cdeb002 | 597 | struct spi_imx_data *spi_imx = spi_master_get_devdata(spi->master); |
6cdeb002 | 598 | int gpio = spi_imx->chipselect[spi->chip_select]; |
e6a0a8bf UKK |
599 | int active = is_active != BITBANG_CS_INACTIVE; |
600 | int dev_is_lowactive = !(spi->mode & SPI_CS_HIGH); | |
b5f3294f | 601 | |
e6a0a8bf | 602 | if (gpio < 0) |
b5f3294f | 603 | return; |
b5f3294f | 604 | |
e6a0a8bf | 605 | gpio_set_value(gpio, dev_is_lowactive ^ active); |
b5f3294f SH |
606 | } |
607 | ||
6cdeb002 | 608 | static void spi_imx_push(struct spi_imx_data *spi_imx) |
b5f3294f | 609 | { |
6ff554e0 | 610 | while (spi_imx->txfifo < spi_imx->devtype_data.fifosize) { |
6cdeb002 | 611 | if (!spi_imx->count) |
b5f3294f | 612 | break; |
6cdeb002 UKK |
613 | spi_imx->tx(spi_imx); |
614 | spi_imx->txfifo++; | |
b5f3294f SH |
615 | } |
616 | ||
f4ba6315 | 617 | spi_imx->devtype_data.trigger(spi_imx); |
b5f3294f SH |
618 | } |
619 | ||
6cdeb002 | 620 | static irqreturn_t spi_imx_isr(int irq, void *dev_id) |
b5f3294f | 621 | { |
6cdeb002 | 622 | struct spi_imx_data *spi_imx = dev_id; |
b5f3294f | 623 | |
f4ba6315 | 624 | while (spi_imx->devtype_data.rx_available(spi_imx)) { |
6cdeb002 UKK |
625 | spi_imx->rx(spi_imx); |
626 | spi_imx->txfifo--; | |
b5f3294f SH |
627 | } |
628 | ||
6cdeb002 UKK |
629 | if (spi_imx->count) { |
630 | spi_imx_push(spi_imx); | |
b5f3294f SH |
631 | return IRQ_HANDLED; |
632 | } | |
633 | ||
6cdeb002 | 634 | if (spi_imx->txfifo) { |
b5f3294f SH |
635 | /* No data left to push, but still waiting for rx data, |
636 | * enable receive data available interrupt. | |
637 | */ | |
f4ba6315 UKK |
638 | spi_imx->devtype_data.intctrl( |
639 | spi_imx, MXC_INT_RR); | |
b5f3294f SH |
640 | return IRQ_HANDLED; |
641 | } | |
642 | ||
f4ba6315 | 643 | spi_imx->devtype_data.intctrl(spi_imx, 0); |
6cdeb002 | 644 | complete(&spi_imx->xfer_done); |
b5f3294f SH |
645 | |
646 | return IRQ_HANDLED; | |
647 | } | |
648 | ||
6cdeb002 | 649 | static int spi_imx_setupxfer(struct spi_device *spi, |
b5f3294f SH |
650 | struct spi_transfer *t) |
651 | { | |
6cdeb002 UKK |
652 | struct spi_imx_data *spi_imx = spi_master_get_devdata(spi->master); |
653 | struct spi_imx_config config; | |
b5f3294f SH |
654 | |
655 | config.bpw = t ? t->bits_per_word : spi->bits_per_word; | |
656 | config.speed_hz = t ? t->speed_hz : spi->max_speed_hz; | |
657 | config.mode = spi->mode; | |
3b2aa89e | 658 | config.cs = spi->chip_select; |
b5f3294f | 659 | |
462d26b5 SH |
660 | if (!config.speed_hz) |
661 | config.speed_hz = spi->max_speed_hz; | |
662 | if (!config.bpw) | |
663 | config.bpw = spi->bits_per_word; | |
664 | if (!config.speed_hz) | |
665 | config.speed_hz = spi->max_speed_hz; | |
666 | ||
e6a0a8bf UKK |
667 | /* Initialize the functions for transfer */ |
668 | if (config.bpw <= 8) { | |
669 | spi_imx->rx = spi_imx_buf_rx_u8; | |
670 | spi_imx->tx = spi_imx_buf_tx_u8; | |
671 | } else if (config.bpw <= 16) { | |
672 | spi_imx->rx = spi_imx_buf_rx_u16; | |
673 | spi_imx->tx = spi_imx_buf_tx_u16; | |
674 | } else if (config.bpw <= 32) { | |
675 | spi_imx->rx = spi_imx_buf_rx_u32; | |
676 | spi_imx->tx = spi_imx_buf_tx_u32; | |
677 | } else | |
678 | BUG(); | |
679 | ||
f4ba6315 | 680 | spi_imx->devtype_data.config(spi_imx, &config); |
b5f3294f SH |
681 | |
682 | return 0; | |
683 | } | |
684 | ||
6cdeb002 | 685 | static int spi_imx_transfer(struct spi_device *spi, |
b5f3294f SH |
686 | struct spi_transfer *transfer) |
687 | { | |
6cdeb002 | 688 | struct spi_imx_data *spi_imx = spi_master_get_devdata(spi->master); |
b5f3294f | 689 | |
6cdeb002 UKK |
690 | spi_imx->tx_buf = transfer->tx_buf; |
691 | spi_imx->rx_buf = transfer->rx_buf; | |
692 | spi_imx->count = transfer->len; | |
693 | spi_imx->txfifo = 0; | |
b5f3294f | 694 | |
6cdeb002 | 695 | init_completion(&spi_imx->xfer_done); |
b5f3294f | 696 | |
6cdeb002 | 697 | spi_imx_push(spi_imx); |
b5f3294f | 698 | |
f4ba6315 | 699 | spi_imx->devtype_data.intctrl(spi_imx, MXC_INT_TE); |
b5f3294f | 700 | |
6cdeb002 | 701 | wait_for_completion(&spi_imx->xfer_done); |
b5f3294f SH |
702 | |
703 | return transfer->len; | |
704 | } | |
705 | ||
6cdeb002 | 706 | static int spi_imx_setup(struct spi_device *spi) |
b5f3294f | 707 | { |
6c23e5d4 SH |
708 | struct spi_imx_data *spi_imx = spi_master_get_devdata(spi->master); |
709 | int gpio = spi_imx->chipselect[spi->chip_select]; | |
710 | ||
f4d4ecfe | 711 | dev_dbg(&spi->dev, "%s: mode %d, %u bpw, %d hz\n", __func__, |
b5f3294f SH |
712 | spi->mode, spi->bits_per_word, spi->max_speed_hz); |
713 | ||
6c23e5d4 SH |
714 | if (gpio >= 0) |
715 | gpio_direction_output(gpio, spi->mode & SPI_CS_HIGH ? 0 : 1); | |
716 | ||
6cdeb002 | 717 | spi_imx_chipselect(spi, BITBANG_CS_INACTIVE); |
b5f3294f SH |
718 | |
719 | return 0; | |
720 | } | |
721 | ||
6cdeb002 | 722 | static void spi_imx_cleanup(struct spi_device *spi) |
b5f3294f SH |
723 | { |
724 | } | |
725 | ||
f4ba6315 UKK |
726 | static struct platform_device_id spi_imx_devtype[] = { |
727 | { | |
f4ba6315 UKK |
728 | .name = "imx1-cspi", |
729 | .driver_data = SPI_IMX_VER_IMX1, | |
730 | }, { | |
731 | .name = "imx21-cspi", | |
732 | .driver_data = SPI_IMX_VER_0_0, | |
733 | }, { | |
734 | .name = "imx25-cspi", | |
735 | .driver_data = SPI_IMX_VER_0_7, | |
736 | }, { | |
737 | .name = "imx27-cspi", | |
738 | .driver_data = SPI_IMX_VER_0_0, | |
739 | }, { | |
740 | .name = "imx31-cspi", | |
741 | .driver_data = SPI_IMX_VER_0_4, | |
742 | }, { | |
743 | .name = "imx35-cspi", | |
744 | .driver_data = SPI_IMX_VER_0_7, | |
0b599603 UKK |
745 | }, { |
746 | .name = "imx51-cspi", | |
747 | .driver_data = SPI_IMX_VER_0_7, | |
748 | }, { | |
749 | .name = "imx51-ecspi", | |
750 | .driver_data = SPI_IMX_VER_2_3, | |
77e7bc61 YS |
751 | }, { |
752 | .name = "imx53-cspi", | |
753 | .driver_data = SPI_IMX_VER_0_7, | |
754 | }, { | |
755 | .name = "imx53-ecspi", | |
756 | .driver_data = SPI_IMX_VER_2_3, | |
f4ba6315 UKK |
757 | }, { |
758 | /* sentinel */ | |
759 | } | |
760 | }; | |
761 | ||
965346e3 | 762 | static int __devinit spi_imx_probe(struct platform_device *pdev) |
b5f3294f SH |
763 | { |
764 | struct spi_imx_master *mxc_platform_info; | |
765 | struct spi_master *master; | |
6cdeb002 | 766 | struct spi_imx_data *spi_imx; |
b5f3294f SH |
767 | struct resource *res; |
768 | int i, ret; | |
769 | ||
980f3bee | 770 | mxc_platform_info = dev_get_platdata(&pdev->dev); |
b5f3294f SH |
771 | if (!mxc_platform_info) { |
772 | dev_err(&pdev->dev, "can't get the platform data\n"); | |
773 | return -EINVAL; | |
774 | } | |
775 | ||
6cdeb002 | 776 | master = spi_alloc_master(&pdev->dev, sizeof(struct spi_imx_data)); |
b5f3294f SH |
777 | if (!master) |
778 | return -ENOMEM; | |
779 | ||
780 | platform_set_drvdata(pdev, master); | |
781 | ||
782 | master->bus_num = pdev->id; | |
783 | master->num_chipselect = mxc_platform_info->num_chipselect; | |
784 | ||
6cdeb002 UKK |
785 | spi_imx = spi_master_get_devdata(master); |
786 | spi_imx->bitbang.master = spi_master_get(master); | |
787 | spi_imx->chipselect = mxc_platform_info->chipselect; | |
b5f3294f SH |
788 | |
789 | for (i = 0; i < master->num_chipselect; i++) { | |
6cdeb002 | 790 | if (spi_imx->chipselect[i] < 0) |
b5f3294f | 791 | continue; |
6cdeb002 | 792 | ret = gpio_request(spi_imx->chipselect[i], DRIVER_NAME); |
b5f3294f | 793 | if (ret) { |
bbd050af JO |
794 | while (i > 0) { |
795 | i--; | |
6cdeb002 | 796 | if (spi_imx->chipselect[i] >= 0) |
bbd050af JO |
797 | gpio_free(spi_imx->chipselect[i]); |
798 | } | |
799 | dev_err(&pdev->dev, "can't get cs gpios\n"); | |
b5f3294f SH |
800 | goto out_master_put; |
801 | } | |
b5f3294f SH |
802 | } |
803 | ||
6cdeb002 UKK |
804 | spi_imx->bitbang.chipselect = spi_imx_chipselect; |
805 | spi_imx->bitbang.setup_transfer = spi_imx_setupxfer; | |
806 | spi_imx->bitbang.txrx_bufs = spi_imx_transfer; | |
807 | spi_imx->bitbang.master->setup = spi_imx_setup; | |
808 | spi_imx->bitbang.master->cleanup = spi_imx_cleanup; | |
3910f2cf | 809 | spi_imx->bitbang.master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH; |
b5f3294f | 810 | |
6cdeb002 | 811 | init_completion(&spi_imx->xfer_done); |
b5f3294f | 812 | |
89342174 UKK |
813 | spi_imx->devtype_data = |
814 | spi_imx_devtype_data[pdev->id_entry->driver_data]; | |
f4ba6315 | 815 | |
b5f3294f SH |
816 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
817 | if (!res) { | |
818 | dev_err(&pdev->dev, "can't get platform resource\n"); | |
819 | ret = -ENOMEM; | |
820 | goto out_gpio_free; | |
821 | } | |
822 | ||
823 | if (!request_mem_region(res->start, resource_size(res), pdev->name)) { | |
824 | dev_err(&pdev->dev, "request_mem_region failed\n"); | |
825 | ret = -EBUSY; | |
826 | goto out_gpio_free; | |
827 | } | |
828 | ||
6cdeb002 UKK |
829 | spi_imx->base = ioremap(res->start, resource_size(res)); |
830 | if (!spi_imx->base) { | |
b5f3294f SH |
831 | ret = -EINVAL; |
832 | goto out_release_mem; | |
833 | } | |
834 | ||
6cdeb002 | 835 | spi_imx->irq = platform_get_irq(pdev, 0); |
73575938 | 836 | if (spi_imx->irq < 0) { |
b5f3294f SH |
837 | ret = -EINVAL; |
838 | goto out_iounmap; | |
839 | } | |
840 | ||
6cdeb002 | 841 | ret = request_irq(spi_imx->irq, spi_imx_isr, 0, DRIVER_NAME, spi_imx); |
b5f3294f | 842 | if (ret) { |
6cdeb002 | 843 | dev_err(&pdev->dev, "can't get irq%d: %d\n", spi_imx->irq, ret); |
b5f3294f SH |
844 | goto out_iounmap; |
845 | } | |
846 | ||
6cdeb002 UKK |
847 | spi_imx->clk = clk_get(&pdev->dev, NULL); |
848 | if (IS_ERR(spi_imx->clk)) { | |
b5f3294f | 849 | dev_err(&pdev->dev, "unable to get clock\n"); |
6cdeb002 | 850 | ret = PTR_ERR(spi_imx->clk); |
b5f3294f SH |
851 | goto out_free_irq; |
852 | } | |
853 | ||
6cdeb002 UKK |
854 | clk_enable(spi_imx->clk); |
855 | spi_imx->spi_clk = clk_get_rate(spi_imx->clk); | |
b5f3294f | 856 | |
1723e66b | 857 | spi_imx->devtype_data.reset(spi_imx); |
ce1807b2 | 858 | |
f4ba6315 | 859 | spi_imx->devtype_data.intctrl(spi_imx, 0); |
b5f3294f | 860 | |
6cdeb002 | 861 | ret = spi_bitbang_start(&spi_imx->bitbang); |
b5f3294f SH |
862 | if (ret) { |
863 | dev_err(&pdev->dev, "bitbang start failed with %d\n", ret); | |
864 | goto out_clk_put; | |
865 | } | |
866 | ||
867 | dev_info(&pdev->dev, "probed\n"); | |
868 | ||
869 | return ret; | |
870 | ||
871 | out_clk_put: | |
6cdeb002 UKK |
872 | clk_disable(spi_imx->clk); |
873 | clk_put(spi_imx->clk); | |
b5f3294f | 874 | out_free_irq: |
6cdeb002 | 875 | free_irq(spi_imx->irq, spi_imx); |
b5f3294f | 876 | out_iounmap: |
6cdeb002 | 877 | iounmap(spi_imx->base); |
b5f3294f SH |
878 | out_release_mem: |
879 | release_mem_region(res->start, resource_size(res)); | |
880 | out_gpio_free: | |
881 | for (i = 0; i < master->num_chipselect; i++) | |
6cdeb002 UKK |
882 | if (spi_imx->chipselect[i] >= 0) |
883 | gpio_free(spi_imx->chipselect[i]); | |
b5f3294f SH |
884 | out_master_put: |
885 | spi_master_put(master); | |
886 | kfree(master); | |
887 | platform_set_drvdata(pdev, NULL); | |
888 | return ret; | |
889 | } | |
890 | ||
965346e3 | 891 | static int __devexit spi_imx_remove(struct platform_device *pdev) |
b5f3294f SH |
892 | { |
893 | struct spi_master *master = platform_get_drvdata(pdev); | |
894 | struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
6cdeb002 | 895 | struct spi_imx_data *spi_imx = spi_master_get_devdata(master); |
b5f3294f SH |
896 | int i; |
897 | ||
6cdeb002 | 898 | spi_bitbang_stop(&spi_imx->bitbang); |
b5f3294f | 899 | |
6cdeb002 UKK |
900 | writel(0, spi_imx->base + MXC_CSPICTRL); |
901 | clk_disable(spi_imx->clk); | |
902 | clk_put(spi_imx->clk); | |
903 | free_irq(spi_imx->irq, spi_imx); | |
904 | iounmap(spi_imx->base); | |
b5f3294f SH |
905 | |
906 | for (i = 0; i < master->num_chipselect; i++) | |
6cdeb002 UKK |
907 | if (spi_imx->chipselect[i] >= 0) |
908 | gpio_free(spi_imx->chipselect[i]); | |
b5f3294f SH |
909 | |
910 | spi_master_put(master); | |
911 | ||
912 | release_mem_region(res->start, resource_size(res)); | |
913 | ||
914 | platform_set_drvdata(pdev, NULL); | |
915 | ||
916 | return 0; | |
917 | } | |
918 | ||
6cdeb002 | 919 | static struct platform_driver spi_imx_driver = { |
b5f3294f SH |
920 | .driver = { |
921 | .name = DRIVER_NAME, | |
922 | .owner = THIS_MODULE, | |
923 | }, | |
f4ba6315 | 924 | .id_table = spi_imx_devtype, |
6cdeb002 | 925 | .probe = spi_imx_probe, |
965346e3 | 926 | .remove = __devexit_p(spi_imx_remove), |
b5f3294f SH |
927 | }; |
928 | ||
6cdeb002 | 929 | static int __init spi_imx_init(void) |
b5f3294f | 930 | { |
6cdeb002 | 931 | return platform_driver_register(&spi_imx_driver); |
b5f3294f SH |
932 | } |
933 | ||
6cdeb002 | 934 | static void __exit spi_imx_exit(void) |
b5f3294f | 935 | { |
6cdeb002 | 936 | platform_driver_unregister(&spi_imx_driver); |
b5f3294f SH |
937 | } |
938 | ||
6cdeb002 UKK |
939 | module_init(spi_imx_init); |
940 | module_exit(spi_imx_exit); | |
b5f3294f SH |
941 | |
942 | MODULE_DESCRIPTION("SPI Master Controller driver"); | |
943 | MODULE_AUTHOR("Sascha Hauer, Pengutronix"); | |
944 | MODULE_LICENSE("GPL"); |