[deliverable/linux.git] / drivers / spi / spi_s3c24xx.c

/* linux/drivers/spi/spi_s3c24xx.c
 *
 * Copyright (c) 2006 Ben Dooks
 * Copyright (c) 2006 Simtec Electronics
 *	Ben Dooks <ben@simtec.co.uk>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
*/

#include <linux/init.h>
#include <linux/spinlock.h>
#include <linux/workqueue.h>
#include <linux/interrupt.h>
#include <linux/delay.h>
#include <linux/errno.h>
#include <linux/err.h>
#include <linux/clk.h>
#include <linux/platform_device.h>
#include <linux/gpio.h>

#include <linux/spi/spi.h>
#include <linux/spi/spi_bitbang.h>

#include <asm/io.h>
#include <asm/dma.h>
#include <mach/hardware.h>

#include <plat/regs-spi.h>
#include <mach/spi.h>

struct s3c24xx_spi {
	/* bitbang has to be first */
	struct spi_bitbang	 bitbang;
	struct completion	 done;

	void __iomem		*regs;
	int			 irq;
	int			 len;
	int			 count;

	void			(*set_cs)(struct s3c2410_spi_info *spi,
					  int cs, int pol);

	/* data buffers */
	const unsigned char	*tx;
	unsigned char		*rx;

	struct clk		*clk;
	struct resource		*ioarea;
	struct spi_master	*master;
	struct spi_device	*curdev;
	struct device		*dev;
	struct s3c2410_spi_info *pdata;
};

#define SPCON_DEFAULT (S3C2410_SPCON_MSTR | S3C2410_SPCON_SMOD_INT)
#define SPPIN_DEFAULT (S3C2410_SPPIN_KEEP)

static inline struct s3c24xx_spi *to_hw(struct spi_device *sdev)
{
	return spi_master_get_devdata(sdev->master);
}

static void s3c24xx_spi_gpiocs(struct s3c2410_spi_info *spi, int cs, int pol)
{
	gpio_set_value(spi->pin_cs, pol);
}

static void s3c24xx_spi_chipsel(struct spi_device *spi, int value)
{
	struct s3c24xx_spi *hw = to_hw(spi);
	unsigned int cspol = spi->mode & SPI_CS_HIGH ? 1 : 0;
	unsigned int spcon;

	switch (value) {
	case BITBANG_CS_INACTIVE:
		hw->set_cs(hw->pdata, spi->chip_select, cspol^1);
		break;

	case BITBANG_CS_ACTIVE:
		spcon = readb(hw->regs + S3C2410_SPCON);

		if (spi->mode & SPI_CPHA)
			spcon |= S3C2410_SPCON_CPHA_FMTB;
		else
			spcon &= ~S3C2410_SPCON_CPHA_FMTB;

		if (spi->mode & SPI_CPOL)
			spcon |= S3C2410_SPCON_CPOL_HIGH;
		else
			spcon &= ~S3C2410_SPCON_CPOL_HIGH;

		spcon |= S3C2410_SPCON_ENSCK;

		/* write new configration */

		writeb(spcon, hw->regs + S3C2410_SPCON);
		hw->set_cs(hw->pdata, spi->chip_select, cspol);

		break;
	}
}

static int s3c24xx_spi_setupxfer(struct spi_device *spi,
				 struct spi_transfer *t)
{
	struct s3c24xx_spi *hw = to_hw(spi);
	unsigned int bpw;
	unsigned int hz;
	unsigned int div;

	bpw = t ? t->bits_per_word : spi->bits_per_word;
	hz  = t ? t->speed_hz : spi->max_speed_hz;

	if (bpw != 8) {
		dev_err(&spi->dev, "invalid bits-per-word (%d)\n", bpw);
		return -EINVAL;
	}

	div = clk_get_rate(hw->clk) / hz;

	/* is clk = pclk / (2 * (pre+1)), or is it
	 *    clk = (pclk * 2) / ( pre + 1) */

	div /= 2;

	if (div > 0)
		div -= 1;

	if (div > 255)
		div = 255;

	dev_dbg(&spi->dev, "setting pre-scaler to %d (hz %d)\n", div, hz);
	writeb(div, hw->regs + S3C2410_SPPRE);

	spin_lock(&hw->bitbang.lock);
	if (!hw->bitbang.busy) {
		hw->bitbang.chipselect(spi, BITBANG_CS_INACTIVE);
		/* need to ndelay for 0.5 clocktick ? */
	}
	spin_unlock(&hw->bitbang.lock);

	return 0;
}

/* the spi->mode bits understood by this driver: */
#define MODEBITS (SPI_CPOL | SPI_CPHA | SPI_CS_HIGH)

static int s3c24xx_spi_setup(struct spi_device *spi)
{
	int ret;

	if (!spi->bits_per_word)
		spi->bits_per_word = 8;

	if (spi->mode & ~MODEBITS) {
		dev_dbg(&spi->dev, "setup: unsupported mode bits %x\n",
			spi->mode & ~MODEBITS);
		return -EINVAL;
	}

	ret = s3c24xx_spi_setupxfer(spi, NULL);
	if (ret < 0) {
		dev_err(&spi->dev, "setupxfer returned %d\n", ret);
		return ret;
	}

	dev_dbg(&spi->dev, "%s: mode %d, %u bpw, %d hz\n",
		__func__, spi->mode, spi->bits_per_word,
		spi->max_speed_hz);

	return 0;
}

static inline unsigned int hw_txbyte(struct s3c24xx_spi *hw, int count)
{
	return hw->tx ? hw->tx[count] : 0;
}

static int s3c24xx_spi_txrx(struct spi_device *spi, struct spi_transfer *t)
{
	struct s3c24xx_spi *hw = to_hw(spi);

	dev_dbg(&spi->dev, "txrx: tx %p, rx %p, len %d\n",
		t->tx_buf, t->rx_buf, t->len);

	hw->tx = t->tx_buf;
	hw->rx = t->rx_buf;
	hw->len = t->len;
	hw->count = 0;

	init_completion(&hw->done);

	/* send the first byte */
	writeb(hw_txbyte(hw, 0), hw->regs + S3C2410_SPTDAT);

	wait_for_completion(&hw->done);

	return hw->count;
}

static irqreturn_t s3c24xx_spi_irq(int irq, void *dev)
{
	struct s3c24xx_spi *hw = dev;
	unsigned int spsta = readb(hw->regs + S3C2410_SPSTA);
	unsigned int count = hw->count;

	if (spsta & S3C2410_SPSTA_DCOL) {
		dev_dbg(hw->dev, "data-collision\n");
		complete(&hw->done);
		goto irq_done;
	}

	if (!(spsta & S3C2410_SPSTA_READY)) {
		dev_dbg(hw->dev, "spi not ready for tx?\n");
		complete(&hw->done);
		goto irq_done;
	}

	hw->count++;

	if (hw->rx)
		hw->rx[count] = readb(hw->regs + S3C2410_SPRDAT);

	count++;

	if (count < hw->len)
		writeb(hw_txbyte(hw, count), hw->regs + S3C2410_SPTDAT);
	else
		complete(&hw->done);

 irq_done:
	return IRQ_HANDLED;
}

static void s3c24xx_spi_initialsetup(struct s3c24xx_spi *hw)
{
	/* for the moment, permanently enable the clock */

	clk_enable(hw->clk);

	/* program defaults into the registers */

	writeb(0xff, hw->regs + S3C2410_SPPRE);
	writeb(SPPIN_DEFAULT, hw->regs + S3C2410_SPPIN);
	writeb(SPCON_DEFAULT, hw->regs + S3C2410_SPCON);

	if (hw->pdata) {
		if (hw->set_cs == s3c24xx_spi_gpiocs)
			gpio_direction_output(hw->pdata->pin_cs, 1);

		if (hw->pdata->gpio_setup)
			hw->pdata->gpio_setup(hw->pdata, 1);
	}
}

static int __init s3c24xx_spi_probe(struct platform_device *pdev)
{
	struct s3c2410_spi_info *pdata;
	struct s3c24xx_spi *hw;
	struct spi_master *master;
	struct resource *res;
	int err = 0;

	master = spi_alloc_master(&pdev->dev, sizeof(struct s3c24xx_spi));
	if (master == NULL) {
		dev_err(&pdev->dev, "No memory for spi_master\n");
		err = -ENOMEM;
		goto err_nomem;
	}

	hw = spi_master_get_devdata(master);
	memset(hw, 0, sizeof(struct s3c24xx_spi));

	hw->master = spi_master_get(master);
	hw->pdata = pdata = pdev->dev.platform_data;
	hw->dev = &pdev->dev;

	if (pdata == NULL) {
		dev_err(&pdev->dev, "No platform data supplied\n");
		err = -ENOENT;
		goto err_no_pdata;
	}

	platform_set_drvdata(pdev, hw);
	init_completion(&hw->done);

	/* setup the master state. */

	master->num_chipselect = hw->pdata->num_cs;
	master->bus_num = pdata->bus_num;

	/* setup the state for the bitbang driver */

	hw->bitbang.master         = hw->master;
	hw->bitbang.setup_transfer = s3c24xx_spi_setupxfer;
	hw->bitbang.chipselect     = s3c24xx_spi_chipsel;
	hw->bitbang.txrx_bufs      = s3c24xx_spi_txrx;
	hw->bitbang.master->setup  = s3c24xx_spi_setup;

	dev_dbg(hw->dev, "bitbang at %p\n", &hw->bitbang);

	/* find and map our resources */

	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	if (res == NULL) {
		dev_err(&pdev->dev, "Cannot get IORESOURCE_MEM\n");
		err = -ENOENT;
		goto err_no_iores;
	}

	hw->ioarea = request_mem_region(res->start, (res->end - res->start)+1,
					pdev->name);

	if (hw->ioarea == NULL) {
		dev_err(&pdev->dev, "Cannot reserve region\n");
		err = -ENXIO;
		goto err_no_iores;
	}

	hw->regs = ioremap(res->start, (res->end - res->start)+1);
	if (hw->regs == NULL) {
		dev_err(&pdev->dev, "Cannot map IO\n");
		err = -ENXIO;
		goto err_no_iomap;
	}

	hw->irq = platform_get_irq(pdev, 0);
	if (hw->irq < 0) {
		dev_err(&pdev->dev, "No IRQ specified\n");
		err = -ENOENT;
		goto err_no_irq;
	}

	err = request_irq(hw->irq, s3c24xx_spi_irq, 0, pdev->name, hw);
	if (err) {
		dev_err(&pdev->dev, "Cannot claim IRQ\n");
		goto err_no_irq;
	}

	hw->clk = clk_get(&pdev->dev, "spi");
	if (IS_ERR(hw->clk)) {
		dev_err(&pdev->dev, "No clock for device\n");
		err = PTR_ERR(hw->clk);
		goto err_no_clk;
	}

	/* setup any gpio we can */

	if (!pdata->set_cs) {
		if (pdata->pin_cs < 0) {
			dev_err(&pdev->dev, "No chipselect pin\n");
			goto err_register;
		}

		err = gpio_request(pdata->pin_cs, dev_name(&pdev->dev));
		if (err) {
			dev_err(&pdev->dev, "Failed to get gpio for cs\n");
			goto err_register;
		}

		hw->set_cs = s3c24xx_spi_gpiocs;
		gpio_direction_output(pdata->pin_cs, 1);
	} else
		hw->set_cs = pdata->set_cs;

	s3c24xx_spi_initialsetup(hw);

	/* register our spi controller */

	err = spi_bitbang_start(&hw->bitbang);
	if (err) {
		dev_err(&pdev->dev, "Failed to register SPI master\n");
		goto err_register;
	}

	return 0;

 err_register:
	if (hw->set_cs == s3c24xx_spi_gpiocs)
		gpio_free(pdata->pin_cs);

	clk_disable(hw->clk);
	clk_put(hw->clk);

 err_no_clk:
	free_irq(hw->irq, hw);

 err_no_irq:
	iounmap(hw->regs);

 err_no_iomap:
	release_resource(hw->ioarea);
	kfree(hw->ioarea);

 err_no_iores:
 err_no_pdata:
	spi_master_put(hw->master);;

 err_nomem:
	return err;
}

static int __exit s3c24xx_spi_remove(struct platform_device *dev)
{
	struct s3c24xx_spi *hw = platform_get_drvdata(dev);

	platform_set_drvdata(dev, NULL);

	spi_unregister_master(hw->master);

	clk_disable(hw->clk);
	clk_put(hw->clk);

	free_irq(hw->irq, hw);
	iounmap(hw->regs);

	if (hw->set_cs == s3c24xx_spi_gpiocs)
		gpio_free(hw->pdata->pin_cs);

	release_resource(hw->ioarea);
	kfree(hw->ioarea);

	spi_master_put(hw->master);
	return 0;
}


#ifdef CONFIG_PM

static int s3c24xx_spi_suspend(struct platform_device *pdev, pm_message_t msg)
{
	struct s3c24xx_spi *hw = platform_get_drvdata(pdev);

	if (hw->pdata && hw->pdata->gpio_setup)
		hw->pdata->gpio_setup(hw->pdata, 0);

	clk_disable(hw->clk);
	return 0;
}

static int s3c24xx_spi_resume(struct platform_device *pdev)
{
	struct s3c24xx_spi *hw = platform_get_drvdata(pdev);

	s3c24xx_spi_initialsetup(hw);
	return 0;
}

#else
#define s3c24xx_spi_suspend NULL
#define s3c24xx_spi_resume  NULL
#endif

MODULE_ALIAS("platform:s3c2410-spi");
static struct platform_driver s3c24xx_spi_driver = {
	.remove		= __exit_p(s3c24xx_spi_remove),
	.suspend	= s3c24xx_spi_suspend,
	.resume		= s3c24xx_spi_resume,
	.driver		= {
		.name	= "s3c2410-spi",
		.owner	= THIS_MODULE,
	},
};

static int __init s3c24xx_spi_init(void)
{
        return platform_driver_probe(&s3c24xx_spi_driver, s3c24xx_spi_probe);
}

static void __exit s3c24xx_spi_exit(void)
{
        platform_driver_unregister(&s3c24xx_spi_driver);
}

module_init(s3c24xx_spi_init);
module_exit(s3c24xx_spi_exit);

MODULE_DESCRIPTION("S3C24XX SPI Driver");
MODULE_AUTHOR("Ben Dooks, <ben@simtec.co.uk>");
MODULE_LICENSE("GPL");
Commit	Line	Data
7fba5340 BD	1	/* linux/drivers/spi/spi_s3c24xx.c
	2	*
	3	* Copyright (c) 2006 Ben Dooks
	4	* Copyright (c) 2006 Simtec Electronics
	5	* Ben Dooks <ben@simtec.co.uk>
	6	*
	7	* This program is free software; you can redistribute it and/or modify
	8	* it under the terms of the GNU General Public License version 2 as
	9	* published by the Free Software Foundation.
	10	*
	11	*/
	12
7fba5340 BD	13	#include <linux/init.h>
	14	#include <linux/spinlock.h>
	15	#include <linux/workqueue.h>
	16	#include <linux/interrupt.h>
	17	#include <linux/delay.h>
	18	#include <linux/errno.h>
	19	#include <linux/err.h>
	20	#include <linux/clk.h>
	21	#include <linux/platform_device.h>
ee9c1fbf	22	#include <linux/gpio.h>
7fba5340 BD	23
	24	#include <linux/spi/spi.h>
	25	#include <linux/spi/spi_bitbang.h>
	26
	27	#include <asm/io.h>
	28	#include <asm/dma.h>
a09e64fb	29	#include <mach/hardware.h>
7fba5340	30
13622708	31	#include <plat/regs-spi.h>
a09e64fb	32	#include <mach/spi.h>
7fba5340 BD	33
	34	struct s3c24xx_spi {
	35	/* bitbang has to be first */
	36	struct spi_bitbang bitbang;
	37	struct completion done;
	38
	39	void __iomem *regs;
	40	int irq;
	41	int len;
	42	int count;
	43
6c912a3d	44	void (set_cs)(struct s3c2410_spi_info spi,
8736b927 BD	45	int cs, int pol);
8736b927 BD	46
7fba5340 BD	47	/* data buffers */
	48	const unsigned char *tx;
	49	unsigned char *rx;
	50
	51	struct clk *clk;
	52	struct resource *ioarea;
	53	struct spi_master *master;
	54	struct spi_device *curdev;
	55	struct device *dev;
	56	struct s3c2410_spi_info *pdata;
	57	};
	58
	59	#define SPCON_DEFAULT (S3C2410_SPCON_MSTR \| S3C2410_SPCON_SMOD_INT)
	60	#define SPPIN_DEFAULT (S3C2410_SPPIN_KEEP)
	61
	62	static inline struct s3c24xx_spi to_hw(struct spi_device sdev)
	63	{
	64	return spi_master_get_devdata(sdev->master);
	65	}
	66
8736b927 BD	67	static void s3c24xx_spi_gpiocs(struct s3c2410_spi_info *spi, int cs, int pol)
8736b927 BD	68	{
ee9c1fbf	69	gpio_set_value(spi->pin_cs, pol);
8736b927 BD	70	}
8736b927 BD	71
7fba5340 BD	72	static void s3c24xx_spi_chipsel(struct spi_device *spi, int value)
	73	{
	74	struct s3c24xx_spi *hw = to_hw(spi);
	75	unsigned int cspol = spi->mode & SPI_CS_HIGH ? 1 : 0;
	76	unsigned int spcon;
	77
	78	switch (value) {
	79	case BITBANG_CS_INACTIVE:
3d2c5b41	80	hw->set_cs(hw->pdata, spi->chip_select, cspol^1);
7fba5340 BD	81	break;
	82
	83	case BITBANG_CS_ACTIVE:
	84	spcon = readb(hw->regs + S3C2410_SPCON);
	85
	86	if (spi->mode & SPI_CPHA)
	87	spcon \|= S3C2410_SPCON_CPHA_FMTB;
	88	else
	89	spcon &= ~S3C2410_SPCON_CPHA_FMTB;
	90
	91	if (spi->mode & SPI_CPOL)
	92	spcon \|= S3C2410_SPCON_CPOL_HIGH;
	93	else
	94	spcon &= ~S3C2410_SPCON_CPOL_HIGH;
	95
	96	spcon \|= S3C2410_SPCON_ENSCK;
	97
	98	/* write new configration */
	99
	100	writeb(spcon, hw->regs + S3C2410_SPCON);
3d2c5b41	101	hw->set_cs(hw->pdata, spi->chip_select, cspol);
7fba5340 BD	102
7fba5340 BD	103	break;
7fba5340 BD	104	}
	105	}
	106
	107	static int s3c24xx_spi_setupxfer(struct spi_device *spi,
	108	struct spi_transfer *t)
	109	{
	110	struct s3c24xx_spi *hw = to_hw(spi);
	111	unsigned int bpw;
	112	unsigned int hz;
	113	unsigned int div;
	114
	115	bpw = t ? t->bits_per_word : spi->bits_per_word;
	116	hz = t ? t->speed_hz : spi->max_speed_hz;
	117
	118	if (bpw != 8) {
	119	dev_err(&spi->dev, "invalid bits-per-word (%d)\n", bpw);
	120	return -EINVAL;
	121	}
	122
	123	div = clk_get_rate(hw->clk) / hz;
	124
	125	/* is clk = pclk / (2 * (pre+1)), or is it
	126	* clk = (pclk * 2) / ( pre + 1) */
	127
0d34aa4d	128	div /= 2;
7fba5340	129
0d34aa4d MW	130	if (div > 0)
0d34aa4d MW	131	div -= 1;
7fba5340 BD	132
	133	if (div > 255)
	134	div = 255;
	135
	136	dev_dbg(&spi->dev, "setting pre-scaler to %d (hz %d)\n", div, hz);
	137	writeb(div, hw->regs + S3C2410_SPPRE);
	138
	139	spin_lock(&hw->bitbang.lock);
	140	if (!hw->bitbang.busy) {
	141	hw->bitbang.chipselect(spi, BITBANG_CS_INACTIVE);
	142	/* need to ndelay for 0.5 clocktick ? */
	143	}
	144	spin_unlock(&hw->bitbang.lock);
	145
	146	return 0;
	147	}
	148
dccd573b DB	149	/* the spi->mode bits understood by this driver: */
	150	#define MODEBITS (SPI_CPOL \| SPI_CPHA \| SPI_CS_HIGH)
	151
7fba5340 BD	152	static int s3c24xx_spi_setup(struct spi_device *spi)
	153	{
	154	int ret;
	155
	156	if (!spi->bits_per_word)
	157	spi->bits_per_word = 8;
	158
dccd573b DB	159	if (spi->mode & ~MODEBITS) {
	160	dev_dbg(&spi->dev, "setup: unsupported mode bits %x\n",
	161	spi->mode & ~MODEBITS);
7fba5340	162	return -EINVAL;
dccd573b	163	}
7fba5340 BD	164
	165	ret = s3c24xx_spi_setupxfer(spi, NULL);
	166	if (ret < 0) {
	167	dev_err(&spi->dev, "setupxfer returned %d\n", ret);
	168	return ret;
	169	}
	170
	171	dev_dbg(&spi->dev, "%s: mode %d, %u bpw, %d hz\n",
b687d2a8	172	__func__, spi->mode, spi->bits_per_word,
7fba5340 BD	173	spi->max_speed_hz);
	174
	175	return 0;
	176	}
	177
	178	static inline unsigned int hw_txbyte(struct s3c24xx_spi *hw, int count)
	179	{
4b1badf5	180	return hw->tx ? hw->tx[count] : 0;
7fba5340 BD	181	}
	182
	183	static int s3c24xx_spi_txrx(struct spi_device spi, struct spi_transfer t)
	184	{
	185	struct s3c24xx_spi *hw = to_hw(spi);
	186
	187	dev_dbg(&spi->dev, "txrx: tx %p, rx %p, len %d\n",
	188	t->tx_buf, t->rx_buf, t->len);
	189
	190	hw->tx = t->tx_buf;
	191	hw->rx = t->rx_buf;
	192	hw->len = t->len;
	193	hw->count = 0;
	194
4bb5eba0 BD	195	init_completion(&hw->done);
4bb5eba0 BD	196
7fba5340 BD	197	/* send the first byte */
7fba5340 BD	198	writeb(hw_txbyte(hw, 0), hw->regs + S3C2410_SPTDAT);
4bb5eba0	199
7fba5340 BD	200	wait_for_completion(&hw->done);
	201
	202	return hw->count;
	203	}
	204
7d12e780	205	static irqreturn_t s3c24xx_spi_irq(int irq, void *dev)
7fba5340 BD	206	{
	207	struct s3c24xx_spi *hw = dev;
	208	unsigned int spsta = readb(hw->regs + S3C2410_SPSTA);
	209	unsigned int count = hw->count;
	210
	211	if (spsta & S3C2410_SPSTA_DCOL) {
	212	dev_dbg(hw->dev, "data-collision\n");
	213	complete(&hw->done);
	214	goto irq_done;
	215	}
	216
	217	if (!(spsta & S3C2410_SPSTA_READY)) {
	218	dev_dbg(hw->dev, "spi not ready for tx?\n");
	219	complete(&hw->done);
	220	goto irq_done;
	221	}
	222
	223	hw->count++;
	224
	225	if (hw->rx)
	226	hw->rx[count] = readb(hw->regs + S3C2410_SPRDAT);
	227
	228	count++;
	229
	230	if (count < hw->len)
	231	writeb(hw_txbyte(hw, count), hw->regs + S3C2410_SPTDAT);
	232	else
	233	complete(&hw->done);
	234
	235	irq_done:
	236	return IRQ_HANDLED;
	237	}
	238
5aa6cf30 BD	239	static void s3c24xx_spi_initialsetup(struct s3c24xx_spi *hw)
	240	{
	241	/* for the moment, permanently enable the clock */
	242
	243	clk_enable(hw->clk);
	244
	245	/* program defaults into the registers */
	246
	247	writeb(0xff, hw->regs + S3C2410_SPPRE);
	248	writeb(SPPIN_DEFAULT, hw->regs + S3C2410_SPPIN);
	249	writeb(SPCON_DEFAULT, hw->regs + S3C2410_SPCON);
cf46b973	250
ee9c1fbf BD	251	if (hw->pdata) {
	252	if (hw->set_cs == s3c24xx_spi_gpiocs)
	253	gpio_direction_output(hw->pdata->pin_cs, 1);
	254
	255	if (hw->pdata->gpio_setup)
	256	hw->pdata->gpio_setup(hw->pdata, 1);
	257	}
5aa6cf30 BD	258	}
5aa6cf30 BD	259
d1e44d9c	260	static int __init s3c24xx_spi_probe(struct platform_device *pdev)
7fba5340	261	{
50f426b5	262	struct s3c2410_spi_info *pdata;
7fba5340 BD	263	struct s3c24xx_spi *hw;
7fba5340 BD	264	struct spi_master *master;
7fba5340 BD	265	struct resource *res;
7fba5340 BD	266	int err = 0;
7fba5340 BD	267
	268	master = spi_alloc_master(&pdev->dev, sizeof(struct s3c24xx_spi));
	269	if (master == NULL) {
	270	dev_err(&pdev->dev, "No memory for spi_master\n");
	271	err = -ENOMEM;
	272	goto err_nomem;
	273	}
	274
	275	hw = spi_master_get_devdata(master);
	276	memset(hw, 0, sizeof(struct s3c24xx_spi));
	277
	278	hw->master = spi_master_get(master);
50f426b5	279	hw->pdata = pdata = pdev->dev.platform_data;
7fba5340 BD	280	hw->dev = &pdev->dev;
7fba5340 BD	281
50f426b5	282	if (pdata == NULL) {
7fba5340 BD	283	dev_err(&pdev->dev, "No platform data supplied\n");
	284	err = -ENOENT;
	285	goto err_no_pdata;
	286	}
	287
	288	platform_set_drvdata(pdev, hw);
	289	init_completion(&hw->done);
	290
d1e77806 BD	291	/* setup the master state. */
	292
	293	master->num_chipselect = hw->pdata->num_cs;
cb1d0a7a	294	master->bus_num = pdata->bus_num;
d1e77806	295
7fba5340 BD	296	/* setup the state for the bitbang driver */
	297
	298	hw->bitbang.master = hw->master;
	299	hw->bitbang.setup_transfer = s3c24xx_spi_setupxfer;
	300	hw->bitbang.chipselect = s3c24xx_spi_chipsel;
	301	hw->bitbang.txrx_bufs = s3c24xx_spi_txrx;
	302	hw->bitbang.master->setup = s3c24xx_spi_setup;
	303
	304	dev_dbg(hw->dev, "bitbang at %p\n", &hw->bitbang);
	305
	306	/* find and map our resources */
	307
	308	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	309	if (res == NULL) {
	310	dev_err(&pdev->dev, "Cannot get IORESOURCE_MEM\n");
	311	err = -ENOENT;
	312	goto err_no_iores;
	313	}
	314
	315	hw->ioarea = request_mem_region(res->start, (res->end - res->start)+1,
	316	pdev->name);
	317
	318	if (hw->ioarea == NULL) {
	319	dev_err(&pdev->dev, "Cannot reserve region\n");
	320	err = -ENXIO;
	321	goto err_no_iores;
	322	}
	323
	324	hw->regs = ioremap(res->start, (res->end - res->start)+1);
	325	if (hw->regs == NULL) {
	326	dev_err(&pdev->dev, "Cannot map IO\n");
	327	err = -ENXIO;
	328	goto err_no_iomap;
	329	}
	330
	331	hw->irq = platform_get_irq(pdev, 0);
	332	if (hw->irq < 0) {
	333	dev_err(&pdev->dev, "No IRQ specified\n");
	334	err = -ENOENT;
	335	goto err_no_irq;
	336	}
	337
	338	err = request_irq(hw->irq, s3c24xx_spi_irq, 0, pdev->name, hw);
	339	if (err) {
	340	dev_err(&pdev->dev, "Cannot claim IRQ\n");
	341	goto err_no_irq;
	342	}
	343
	344	hw->clk = clk_get(&pdev->dev, "spi");
	345	if (IS_ERR(hw->clk)) {
	346	dev_err(&pdev->dev, "No clock for device\n");
	347	err = PTR_ERR(hw->clk);
	348	goto err_no_clk;
	349	}
	350
7fba5340 BD	351	/* setup any gpio we can */
7fba5340 BD	352
50f426b5	353	if (!pdata->set_cs) {
ee9c1fbf BD	354	if (pdata->pin_cs < 0) {
	355	dev_err(&pdev->dev, "No chipselect pin\n");
	356	goto err_register;
	357	}
8736b927	358
ee9c1fbf BD	359	err = gpio_request(pdata->pin_cs, dev_name(&pdev->dev));
	360	if (err) {
	361	dev_err(&pdev->dev, "Failed to get gpio for cs\n");
	362	goto err_register;
	363	}
	364
	365	hw->set_cs = s3c24xx_spi_gpiocs;
	366	gpio_direction_output(pdata->pin_cs, 1);
8736b927	367	} else
50f426b5	368	hw->set_cs = pdata->set_cs;
7fba5340	369
ee9c1fbf BD	370	s3c24xx_spi_initialsetup(hw);
ee9c1fbf BD	371
7fba5340 BD	372	/* register our spi controller */
	373
	374	err = spi_bitbang_start(&hw->bitbang);
	375	if (err) {
	376	dev_err(&pdev->dev, "Failed to register SPI master\n");
	377	goto err_register;
	378	}
	379
7fba5340 BD	380	return 0;
	381
	382	err_register:
ee9c1fbf BD	383	if (hw->set_cs == s3c24xx_spi_gpiocs)
	384	gpio_free(pdata->pin_cs);
	385
7fba5340 BD	386	clk_disable(hw->clk);
	387	clk_put(hw->clk);
	388
	389	err_no_clk:
	390	free_irq(hw->irq, hw);
	391
	392	err_no_irq:
	393	iounmap(hw->regs);
	394
	395	err_no_iomap:
	396	release_resource(hw->ioarea);
	397	kfree(hw->ioarea);
	398
	399	err_no_iores:
	400	err_no_pdata:
	401	spi_master_put(hw->master);;
	402
	403	err_nomem:
	404	return err;
	405	}
	406
d1e44d9c	407	static int __exit s3c24xx_spi_remove(struct platform_device *dev)
7fba5340 BD	408	{
	409	struct s3c24xx_spi *hw = platform_get_drvdata(dev);
	410
	411	platform_set_drvdata(dev, NULL);
	412
	413	spi_unregister_master(hw->master);
	414
	415	clk_disable(hw->clk);
	416	clk_put(hw->clk);
	417
	418	free_irq(hw->irq, hw);
	419	iounmap(hw->regs);
	420
ee9c1fbf BD	421	if (hw->set_cs == s3c24xx_spi_gpiocs)
	422	gpio_free(hw->pdata->pin_cs);
	423
7fba5340 BD	424	release_resource(hw->ioarea);
	425	kfree(hw->ioarea);
	426
	427	spi_master_put(hw->master);
	428	return 0;
	429	}
	430
	431
	432	#ifdef CONFIG_PM
	433
	434	static int s3c24xx_spi_suspend(struct platform_device *pdev, pm_message_t msg)
	435	{
ac88bcff	436	struct s3c24xx_spi *hw = platform_get_drvdata(pdev);
7fba5340	437
cf46b973 BD	438	if (hw->pdata && hw->pdata->gpio_setup)
	439	hw->pdata->gpio_setup(hw->pdata, 0);
	440
7fba5340 BD	441	clk_disable(hw->clk);
	442	return 0;
	443	}
	444
	445	static int s3c24xx_spi_resume(struct platform_device *pdev)
	446	{
ac88bcff	447	struct s3c24xx_spi *hw = platform_get_drvdata(pdev);
7fba5340	448
5aa6cf30	449	s3c24xx_spi_initialsetup(hw);
7fba5340 BD	450	return 0;
	451	}
	452
	453	#else
	454	#define s3c24xx_spi_suspend NULL
	455	#define s3c24xx_spi_resume NULL
	456	#endif
	457
7e38c3c4	458	MODULE_ALIAS("platform:s3c2410-spi");
42cde430	459	static struct platform_driver s3c24xx_spi_driver = {
d1e44d9c	460	.remove = __exit_p(s3c24xx_spi_remove),
7fba5340 BD	461	.suspend = s3c24xx_spi_suspend,
	462	.resume = s3c24xx_spi_resume,
	463	.driver = {
	464	.name = "s3c2410-spi",
	465	.owner = THIS_MODULE,
	466	},
	467	};
	468
	469	static int __init s3c24xx_spi_init(void)
	470	{
42cde430	471	return platform_driver_probe(&s3c24xx_spi_driver, s3c24xx_spi_probe);
7fba5340 BD	472	}
	473
	474	static void __exit s3c24xx_spi_exit(void)
	475	{
42cde430	476	platform_driver_unregister(&s3c24xx_spi_driver);
7fba5340 BD	477	}
	478
	479	module_init(s3c24xx_spi_init);
	480	module_exit(s3c24xx_spi_exit);
	481
	482	MODULE_DESCRIPTION("S3C24XX SPI Driver");
	483	MODULE_AUTHOR("Ben Dooks, <ben@simtec.co.uk>");
	484	MODULE_LICENSE("GPL");