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7fba5340 BD |
1 | /* linux/drivers/spi/spi_s3c24xx.c |
2 | * | |
3 | * Copyright (c) 2006 Ben Dooks | |
4 | * Copyright (c) 2006 Simtec Electronics | |
5 | * Ben Dooks <ben@simtec.co.uk> | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or modify | |
8 | * it under the terms of the GNU General Public License version 2 as | |
9 | * published by the Free Software Foundation. | |
10 | * | |
11 | */ | |
12 | ||
7fba5340 BD |
13 | #include <linux/init.h> |
14 | #include <linux/spinlock.h> | |
15 | #include <linux/workqueue.h> | |
16 | #include <linux/interrupt.h> | |
17 | #include <linux/delay.h> | |
18 | #include <linux/errno.h> | |
19 | #include <linux/err.h> | |
20 | #include <linux/clk.h> | |
21 | #include <linux/platform_device.h> | |
ee9c1fbf | 22 | #include <linux/gpio.h> |
1a0c220f | 23 | #include <linux/io.h> |
7fba5340 BD |
24 | |
25 | #include <linux/spi/spi.h> | |
26 | #include <linux/spi/spi_bitbang.h> | |
27 | ||
13622708 | 28 | #include <plat/regs-spi.h> |
a09e64fb | 29 | #include <mach/spi.h> |
7fba5340 | 30 | |
570327d9 BD |
31 | /** |
32 | * s3c24xx_spi_devstate - per device data | |
33 | * @hz: Last frequency calculated for @sppre field. | |
34 | * @mode: Last mode setting for the @spcon field. | |
35 | * @spcon: Value to write to the SPCON register. | |
36 | * @sppre: Value to write to the SPPRE register. | |
37 | */ | |
38 | struct s3c24xx_spi_devstate { | |
39 | unsigned int hz; | |
40 | unsigned int mode; | |
41 | u8 spcon; | |
42 | u8 sppre; | |
43 | }; | |
44 | ||
7fba5340 BD |
45 | struct s3c24xx_spi { |
46 | /* bitbang has to be first */ | |
47 | struct spi_bitbang bitbang; | |
48 | struct completion done; | |
49 | ||
50 | void __iomem *regs; | |
51 | int irq; | |
52 | int len; | |
53 | int count; | |
54 | ||
6c912a3d | 55 | void (*set_cs)(struct s3c2410_spi_info *spi, |
8736b927 BD |
56 | int cs, int pol); |
57 | ||
7fba5340 BD |
58 | /* data buffers */ |
59 | const unsigned char *tx; | |
60 | unsigned char *rx; | |
61 | ||
62 | struct clk *clk; | |
63 | struct resource *ioarea; | |
64 | struct spi_master *master; | |
65 | struct spi_device *curdev; | |
66 | struct device *dev; | |
67 | struct s3c2410_spi_info *pdata; | |
68 | }; | |
69 | ||
70 | #define SPCON_DEFAULT (S3C2410_SPCON_MSTR | S3C2410_SPCON_SMOD_INT) | |
71 | #define SPPIN_DEFAULT (S3C2410_SPPIN_KEEP) | |
72 | ||
73 | static inline struct s3c24xx_spi *to_hw(struct spi_device *sdev) | |
74 | { | |
75 | return spi_master_get_devdata(sdev->master); | |
76 | } | |
77 | ||
8736b927 BD |
78 | static void s3c24xx_spi_gpiocs(struct s3c2410_spi_info *spi, int cs, int pol) |
79 | { | |
ee9c1fbf | 80 | gpio_set_value(spi->pin_cs, pol); |
8736b927 BD |
81 | } |
82 | ||
7fba5340 BD |
83 | static void s3c24xx_spi_chipsel(struct spi_device *spi, int value) |
84 | { | |
570327d9 | 85 | struct s3c24xx_spi_devstate *cs = spi->controller_state; |
7fba5340 BD |
86 | struct s3c24xx_spi *hw = to_hw(spi); |
87 | unsigned int cspol = spi->mode & SPI_CS_HIGH ? 1 : 0; | |
570327d9 BD |
88 | |
89 | /* change the chipselect state and the state of the spi engine clock */ | |
7fba5340 BD |
90 | |
91 | switch (value) { | |
92 | case BITBANG_CS_INACTIVE: | |
3d2c5b41 | 93 | hw->set_cs(hw->pdata, spi->chip_select, cspol^1); |
570327d9 | 94 | writeb(cs->spcon, hw->regs + S3C2410_SPCON); |
7fba5340 BD |
95 | break; |
96 | ||
97 | case BITBANG_CS_ACTIVE: | |
570327d9 BD |
98 | writeb(cs->spcon | S3C2410_SPCON_ENSCK, |
99 | hw->regs + S3C2410_SPCON); | |
3d2c5b41 | 100 | hw->set_cs(hw->pdata, spi->chip_select, cspol); |
7fba5340 | 101 | break; |
7fba5340 BD |
102 | } |
103 | } | |
104 | ||
570327d9 BD |
105 | static int s3c24xx_spi_update_state(struct spi_device *spi, |
106 | struct spi_transfer *t) | |
7fba5340 BD |
107 | { |
108 | struct s3c24xx_spi *hw = to_hw(spi); | |
570327d9 | 109 | struct s3c24xx_spi_devstate *cs = spi->controller_state; |
7fba5340 BD |
110 | unsigned int bpw; |
111 | unsigned int hz; | |
112 | unsigned int div; | |
b8978784 | 113 | unsigned long clk; |
7fba5340 BD |
114 | |
115 | bpw = t ? t->bits_per_word : spi->bits_per_word; | |
116 | hz = t ? t->speed_hz : spi->max_speed_hz; | |
117 | ||
19152975 BD |
118 | if (!bpw) |
119 | bpw = 8; | |
120 | ||
121 | if (!hz) | |
122 | hz = spi->max_speed_hz; | |
123 | ||
7fba5340 BD |
124 | if (bpw != 8) { |
125 | dev_err(&spi->dev, "invalid bits-per-word (%d)\n", bpw); | |
126 | return -EINVAL; | |
127 | } | |
128 | ||
570327d9 BD |
129 | if (spi->mode != cs->mode) { |
130 | u8 spcon = SPCON_DEFAULT; | |
131 | ||
132 | if (spi->mode & SPI_CPHA) | |
133 | spcon |= S3C2410_SPCON_CPHA_FMTB; | |
7fba5340 | 134 | |
570327d9 BD |
135 | if (spi->mode & SPI_CPOL) |
136 | spcon |= S3C2410_SPCON_CPOL_HIGH; | |
7fba5340 | 137 | |
570327d9 BD |
138 | cs->mode = spi->mode; |
139 | cs->spcon = spcon; | |
140 | } | |
b8978784 | 141 | |
570327d9 BD |
142 | if (cs->hz != hz) { |
143 | clk = clk_get_rate(hw->clk); | |
144 | div = DIV_ROUND_UP(clk, hz * 2) - 1; | |
b8978784 | 145 | |
570327d9 BD |
146 | if (div > 255) |
147 | div = 255; | |
7fba5340 | 148 | |
570327d9 BD |
149 | dev_dbg(&spi->dev, "pre-scaler=%d (wanted %d, got %ld)\n", |
150 | div, hz, clk / (2 * (div + 1))); | |
151 | ||
152 | cs->hz = hz; | |
153 | cs->sppre = div; | |
7fba5340 | 154 | } |
7fba5340 BD |
155 | |
156 | return 0; | |
157 | } | |
158 | ||
570327d9 BD |
159 | static int s3c24xx_spi_setupxfer(struct spi_device *spi, |
160 | struct spi_transfer *t) | |
161 | { | |
162 | struct s3c24xx_spi_devstate *cs = spi->controller_state; | |
163 | struct s3c24xx_spi *hw = to_hw(spi); | |
164 | int ret; | |
165 | ||
166 | ret = s3c24xx_spi_update_state(spi, t); | |
167 | if (!ret) | |
168 | writeb(cs->sppre, hw->regs + S3C2410_SPPRE); | |
169 | ||
170 | return ret; | |
171 | } | |
172 | ||
7fba5340 BD |
173 | static int s3c24xx_spi_setup(struct spi_device *spi) |
174 | { | |
570327d9 BD |
175 | struct s3c24xx_spi_devstate *cs = spi->controller_state; |
176 | struct s3c24xx_spi *hw = to_hw(spi); | |
7fba5340 BD |
177 | int ret; |
178 | ||
570327d9 BD |
179 | /* allocate settings on the first call */ |
180 | if (!cs) { | |
181 | cs = kzalloc(sizeof(struct s3c24xx_spi_devstate), GFP_KERNEL); | |
182 | if (!cs) { | |
183 | dev_err(&spi->dev, "no memory for controller state\n"); | |
184 | return -ENOMEM; | |
185 | } | |
186 | ||
187 | cs->spcon = SPCON_DEFAULT; | |
188 | cs->hz = -1; | |
189 | spi->controller_state = cs; | |
190 | } | |
191 | ||
192 | /* initialise the state from the device */ | |
193 | ret = s3c24xx_spi_update_state(spi, NULL); | |
194 | if (ret) | |
7fba5340 | 195 | return ret; |
570327d9 BD |
196 | |
197 | spin_lock(&hw->bitbang.lock); | |
198 | if (!hw->bitbang.busy) { | |
199 | hw->bitbang.chipselect(spi, BITBANG_CS_INACTIVE); | |
200 | /* need to ndelay for 0.5 clocktick ? */ | |
7fba5340 | 201 | } |
570327d9 | 202 | spin_unlock(&hw->bitbang.lock); |
7fba5340 | 203 | |
7fba5340 BD |
204 | return 0; |
205 | } | |
206 | ||
570327d9 BD |
207 | static void s3c24xx_spi_cleanup(struct spi_device *spi) |
208 | { | |
209 | kfree(spi->controller_state); | |
210 | } | |
211 | ||
7fba5340 BD |
212 | static inline unsigned int hw_txbyte(struct s3c24xx_spi *hw, int count) |
213 | { | |
4b1badf5 | 214 | return hw->tx ? hw->tx[count] : 0; |
7fba5340 BD |
215 | } |
216 | ||
217 | static int s3c24xx_spi_txrx(struct spi_device *spi, struct spi_transfer *t) | |
218 | { | |
219 | struct s3c24xx_spi *hw = to_hw(spi); | |
220 | ||
221 | dev_dbg(&spi->dev, "txrx: tx %p, rx %p, len %d\n", | |
222 | t->tx_buf, t->rx_buf, t->len); | |
223 | ||
224 | hw->tx = t->tx_buf; | |
225 | hw->rx = t->rx_buf; | |
226 | hw->len = t->len; | |
227 | hw->count = 0; | |
228 | ||
4bb5eba0 BD |
229 | init_completion(&hw->done); |
230 | ||
7fba5340 BD |
231 | /* send the first byte */ |
232 | writeb(hw_txbyte(hw, 0), hw->regs + S3C2410_SPTDAT); | |
4bb5eba0 | 233 | |
7fba5340 BD |
234 | wait_for_completion(&hw->done); |
235 | ||
236 | return hw->count; | |
237 | } | |
238 | ||
7d12e780 | 239 | static irqreturn_t s3c24xx_spi_irq(int irq, void *dev) |
7fba5340 BD |
240 | { |
241 | struct s3c24xx_spi *hw = dev; | |
242 | unsigned int spsta = readb(hw->regs + S3C2410_SPSTA); | |
243 | unsigned int count = hw->count; | |
244 | ||
245 | if (spsta & S3C2410_SPSTA_DCOL) { | |
246 | dev_dbg(hw->dev, "data-collision\n"); | |
247 | complete(&hw->done); | |
248 | goto irq_done; | |
249 | } | |
250 | ||
251 | if (!(spsta & S3C2410_SPSTA_READY)) { | |
252 | dev_dbg(hw->dev, "spi not ready for tx?\n"); | |
253 | complete(&hw->done); | |
254 | goto irq_done; | |
255 | } | |
256 | ||
257 | hw->count++; | |
258 | ||
259 | if (hw->rx) | |
260 | hw->rx[count] = readb(hw->regs + S3C2410_SPRDAT); | |
261 | ||
262 | count++; | |
263 | ||
264 | if (count < hw->len) | |
265 | writeb(hw_txbyte(hw, count), hw->regs + S3C2410_SPTDAT); | |
266 | else | |
267 | complete(&hw->done); | |
268 | ||
269 | irq_done: | |
270 | return IRQ_HANDLED; | |
271 | } | |
272 | ||
5aa6cf30 BD |
273 | static void s3c24xx_spi_initialsetup(struct s3c24xx_spi *hw) |
274 | { | |
275 | /* for the moment, permanently enable the clock */ | |
276 | ||
277 | clk_enable(hw->clk); | |
278 | ||
279 | /* program defaults into the registers */ | |
280 | ||
281 | writeb(0xff, hw->regs + S3C2410_SPPRE); | |
282 | writeb(SPPIN_DEFAULT, hw->regs + S3C2410_SPPIN); | |
283 | writeb(SPCON_DEFAULT, hw->regs + S3C2410_SPCON); | |
cf46b973 | 284 | |
ee9c1fbf BD |
285 | if (hw->pdata) { |
286 | if (hw->set_cs == s3c24xx_spi_gpiocs) | |
287 | gpio_direction_output(hw->pdata->pin_cs, 1); | |
288 | ||
289 | if (hw->pdata->gpio_setup) | |
290 | hw->pdata->gpio_setup(hw->pdata, 1); | |
291 | } | |
5aa6cf30 BD |
292 | } |
293 | ||
d1e44d9c | 294 | static int __init s3c24xx_spi_probe(struct platform_device *pdev) |
7fba5340 | 295 | { |
50f426b5 | 296 | struct s3c2410_spi_info *pdata; |
7fba5340 BD |
297 | struct s3c24xx_spi *hw; |
298 | struct spi_master *master; | |
7fba5340 BD |
299 | struct resource *res; |
300 | int err = 0; | |
7fba5340 BD |
301 | |
302 | master = spi_alloc_master(&pdev->dev, sizeof(struct s3c24xx_spi)); | |
303 | if (master == NULL) { | |
304 | dev_err(&pdev->dev, "No memory for spi_master\n"); | |
305 | err = -ENOMEM; | |
306 | goto err_nomem; | |
307 | } | |
308 | ||
309 | hw = spi_master_get_devdata(master); | |
310 | memset(hw, 0, sizeof(struct s3c24xx_spi)); | |
311 | ||
312 | hw->master = spi_master_get(master); | |
50f426b5 | 313 | hw->pdata = pdata = pdev->dev.platform_data; |
7fba5340 BD |
314 | hw->dev = &pdev->dev; |
315 | ||
50f426b5 | 316 | if (pdata == NULL) { |
7fba5340 BD |
317 | dev_err(&pdev->dev, "No platform data supplied\n"); |
318 | err = -ENOENT; | |
319 | goto err_no_pdata; | |
320 | } | |
321 | ||
322 | platform_set_drvdata(pdev, hw); | |
323 | init_completion(&hw->done); | |
324 | ||
d1e77806 BD |
325 | /* setup the master state. */ |
326 | ||
e7db06b5 DB |
327 | /* the spi->mode bits understood by this driver: */ |
328 | master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH; | |
329 | ||
d1e77806 | 330 | master->num_chipselect = hw->pdata->num_cs; |
cb1d0a7a | 331 | master->bus_num = pdata->bus_num; |
d1e77806 | 332 | |
7fba5340 BD |
333 | /* setup the state for the bitbang driver */ |
334 | ||
335 | hw->bitbang.master = hw->master; | |
336 | hw->bitbang.setup_transfer = s3c24xx_spi_setupxfer; | |
337 | hw->bitbang.chipselect = s3c24xx_spi_chipsel; | |
338 | hw->bitbang.txrx_bufs = s3c24xx_spi_txrx; | |
570327d9 BD |
339 | |
340 | hw->master->setup = s3c24xx_spi_setup; | |
341 | hw->master->cleanup = s3c24xx_spi_cleanup; | |
7fba5340 BD |
342 | |
343 | dev_dbg(hw->dev, "bitbang at %p\n", &hw->bitbang); | |
344 | ||
345 | /* find and map our resources */ | |
346 | ||
347 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
348 | if (res == NULL) { | |
349 | dev_err(&pdev->dev, "Cannot get IORESOURCE_MEM\n"); | |
350 | err = -ENOENT; | |
351 | goto err_no_iores; | |
352 | } | |
353 | ||
b5e3afb5 | 354 | hw->ioarea = request_mem_region(res->start, resource_size(res), |
7fba5340 BD |
355 | pdev->name); |
356 | ||
357 | if (hw->ioarea == NULL) { | |
358 | dev_err(&pdev->dev, "Cannot reserve region\n"); | |
359 | err = -ENXIO; | |
360 | goto err_no_iores; | |
361 | } | |
362 | ||
b5e3afb5 | 363 | hw->regs = ioremap(res->start, resource_size(res)); |
7fba5340 BD |
364 | if (hw->regs == NULL) { |
365 | dev_err(&pdev->dev, "Cannot map IO\n"); | |
366 | err = -ENXIO; | |
367 | goto err_no_iomap; | |
368 | } | |
369 | ||
370 | hw->irq = platform_get_irq(pdev, 0); | |
371 | if (hw->irq < 0) { | |
372 | dev_err(&pdev->dev, "No IRQ specified\n"); | |
373 | err = -ENOENT; | |
374 | goto err_no_irq; | |
375 | } | |
376 | ||
377 | err = request_irq(hw->irq, s3c24xx_spi_irq, 0, pdev->name, hw); | |
378 | if (err) { | |
379 | dev_err(&pdev->dev, "Cannot claim IRQ\n"); | |
380 | goto err_no_irq; | |
381 | } | |
382 | ||
383 | hw->clk = clk_get(&pdev->dev, "spi"); | |
384 | if (IS_ERR(hw->clk)) { | |
385 | dev_err(&pdev->dev, "No clock for device\n"); | |
386 | err = PTR_ERR(hw->clk); | |
387 | goto err_no_clk; | |
388 | } | |
389 | ||
7fba5340 BD |
390 | /* setup any gpio we can */ |
391 | ||
50f426b5 | 392 | if (!pdata->set_cs) { |
ee9c1fbf BD |
393 | if (pdata->pin_cs < 0) { |
394 | dev_err(&pdev->dev, "No chipselect pin\n"); | |
395 | goto err_register; | |
396 | } | |
8736b927 | 397 | |
ee9c1fbf BD |
398 | err = gpio_request(pdata->pin_cs, dev_name(&pdev->dev)); |
399 | if (err) { | |
400 | dev_err(&pdev->dev, "Failed to get gpio for cs\n"); | |
401 | goto err_register; | |
402 | } | |
403 | ||
404 | hw->set_cs = s3c24xx_spi_gpiocs; | |
405 | gpio_direction_output(pdata->pin_cs, 1); | |
8736b927 | 406 | } else |
50f426b5 | 407 | hw->set_cs = pdata->set_cs; |
7fba5340 | 408 | |
ee9c1fbf BD |
409 | s3c24xx_spi_initialsetup(hw); |
410 | ||
7fba5340 BD |
411 | /* register our spi controller */ |
412 | ||
413 | err = spi_bitbang_start(&hw->bitbang); | |
414 | if (err) { | |
415 | dev_err(&pdev->dev, "Failed to register SPI master\n"); | |
416 | goto err_register; | |
417 | } | |
418 | ||
7fba5340 BD |
419 | return 0; |
420 | ||
421 | err_register: | |
ee9c1fbf BD |
422 | if (hw->set_cs == s3c24xx_spi_gpiocs) |
423 | gpio_free(pdata->pin_cs); | |
424 | ||
7fba5340 BD |
425 | clk_disable(hw->clk); |
426 | clk_put(hw->clk); | |
427 | ||
428 | err_no_clk: | |
429 | free_irq(hw->irq, hw); | |
430 | ||
431 | err_no_irq: | |
432 | iounmap(hw->regs); | |
433 | ||
434 | err_no_iomap: | |
435 | release_resource(hw->ioarea); | |
436 | kfree(hw->ioarea); | |
437 | ||
438 | err_no_iores: | |
439 | err_no_pdata: | |
a419aef8 | 440 | spi_master_put(hw->master); |
7fba5340 BD |
441 | |
442 | err_nomem: | |
443 | return err; | |
444 | } | |
445 | ||
d1e44d9c | 446 | static int __exit s3c24xx_spi_remove(struct platform_device *dev) |
7fba5340 BD |
447 | { |
448 | struct s3c24xx_spi *hw = platform_get_drvdata(dev); | |
449 | ||
450 | platform_set_drvdata(dev, NULL); | |
451 | ||
452 | spi_unregister_master(hw->master); | |
453 | ||
454 | clk_disable(hw->clk); | |
455 | clk_put(hw->clk); | |
456 | ||
457 | free_irq(hw->irq, hw); | |
458 | iounmap(hw->regs); | |
459 | ||
ee9c1fbf BD |
460 | if (hw->set_cs == s3c24xx_spi_gpiocs) |
461 | gpio_free(hw->pdata->pin_cs); | |
462 | ||
7fba5340 BD |
463 | release_resource(hw->ioarea); |
464 | kfree(hw->ioarea); | |
465 | ||
466 | spi_master_put(hw->master); | |
467 | return 0; | |
468 | } | |
469 | ||
470 | ||
471 | #ifdef CONFIG_PM | |
472 | ||
6d613207 | 473 | static int s3c24xx_spi_suspend(struct device *dev) |
7fba5340 | 474 | { |
6d613207 | 475 | struct s3c24xx_spi *hw = platform_get_drvdata(to_platform_device(dev)); |
7fba5340 | 476 | |
cf46b973 BD |
477 | if (hw->pdata && hw->pdata->gpio_setup) |
478 | hw->pdata->gpio_setup(hw->pdata, 0); | |
479 | ||
7fba5340 BD |
480 | clk_disable(hw->clk); |
481 | return 0; | |
482 | } | |
483 | ||
6d613207 | 484 | static int s3c24xx_spi_resume(struct device *dev) |
7fba5340 | 485 | { |
6d613207 | 486 | struct s3c24xx_spi *hw = platform_get_drvdata(to_platform_device(dev)); |
7fba5340 | 487 | |
5aa6cf30 | 488 | s3c24xx_spi_initialsetup(hw); |
7fba5340 BD |
489 | return 0; |
490 | } | |
491 | ||
47145210 | 492 | static const struct dev_pm_ops s3c24xx_spi_pmops = { |
6d613207 BD |
493 | .suspend = s3c24xx_spi_suspend, |
494 | .resume = s3c24xx_spi_resume, | |
495 | }; | |
496 | ||
497 | #define S3C24XX_SPI_PMOPS &s3c24xx_spi_pmops | |
7fba5340 | 498 | #else |
6d613207 BD |
499 | #define S3C24XX_SPI_PMOPS NULL |
500 | #endif /* CONFIG_PM */ | |
7fba5340 | 501 | |
7e38c3c4 | 502 | MODULE_ALIAS("platform:s3c2410-spi"); |
42cde430 | 503 | static struct platform_driver s3c24xx_spi_driver = { |
d1e44d9c | 504 | .remove = __exit_p(s3c24xx_spi_remove), |
7fba5340 BD |
505 | .driver = { |
506 | .name = "s3c2410-spi", | |
507 | .owner = THIS_MODULE, | |
6d613207 | 508 | .pm = S3C24XX_SPI_PMOPS, |
7fba5340 BD |
509 | }, |
510 | }; | |
511 | ||
512 | static int __init s3c24xx_spi_init(void) | |
513 | { | |
42cde430 | 514 | return platform_driver_probe(&s3c24xx_spi_driver, s3c24xx_spi_probe); |
7fba5340 BD |
515 | } |
516 | ||
517 | static void __exit s3c24xx_spi_exit(void) | |
518 | { | |
42cde430 | 519 | platform_driver_unregister(&s3c24xx_spi_driver); |
7fba5340 BD |
520 | } |
521 | ||
522 | module_init(s3c24xx_spi_init); | |
523 | module_exit(s3c24xx_spi_exit); | |
524 | ||
525 | MODULE_DESCRIPTION("S3C24XX SPI Driver"); | |
526 | MODULE_AUTHOR("Ben Dooks, <ben@simtec.co.uk>"); | |
527 | MODULE_LICENSE("GPL"); |