[deliverable/linux.git] / drivers / spi / xilinx_spi.c

/*
 * xilinx_spi.c
 *
 * Xilinx SPI controller driver (master mode only)
 *
 * Author: MontaVista Software, Inc.
 *	source@mvista.com
 *
 * 2002-2007 (c) MontaVista Software, Inc.  This file is licensed under the
 * terms of the GNU General Public License version 2.  This program is licensed
 * "as is" without any warranty of any kind, whether express or implied.
 */

#include <linux/module.h>
#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/platform_device.h>
#include <linux/spi/spi.h>
#include <linux/spi/spi_bitbang.h>
#include <linux/io.h>

#include <syslib/virtex_devices.h>

#define XILINX_SPI_NAME "xilinx_spi"

/* Register definitions as per "OPB Serial Peripheral Interface (SPI) (v1.00e)
 * Product Specification", DS464
 */
#define XSPI_CR_OFFSET		0x62	/* 16-bit Control Register */

#define XSPI_CR_ENABLE		0x02
#define XSPI_CR_MASTER_MODE	0x04
#define XSPI_CR_CPOL		0x08
#define XSPI_CR_CPHA		0x10
#define XSPI_CR_MODE_MASK	(XSPI_CR_CPHA | XSPI_CR_CPOL)
#define XSPI_CR_TXFIFO_RESET	0x20
#define XSPI_CR_RXFIFO_RESET	0x40
#define XSPI_CR_MANUAL_SSELECT	0x80
#define XSPI_CR_TRANS_INHIBIT	0x100

#define XSPI_SR_OFFSET		0x67	/* 8-bit Status Register */

#define XSPI_SR_RX_EMPTY_MASK	0x01	/* Receive FIFO is empty */
#define XSPI_SR_RX_FULL_MASK	0x02	/* Receive FIFO is full */
#define XSPI_SR_TX_EMPTY_MASK	0x04	/* Transmit FIFO is empty */
#define XSPI_SR_TX_FULL_MASK	0x08	/* Transmit FIFO is full */
#define XSPI_SR_MODE_FAULT_MASK	0x10	/* Mode fault error */

#define XSPI_TXD_OFFSET		0x6b	/* 8-bit Data Transmit Register */
#define XSPI_RXD_OFFSET		0x6f	/* 8-bit Data Receive Register */

#define XSPI_SSR_OFFSET		0x70	/* 32-bit Slave Select Register */

/* Register definitions as per "OPB IPIF (v3.01c) Product Specification", DS414
 * IPIF registers are 32 bit
 */
#define XIPIF_V123B_DGIER_OFFSET	0x1c	/* IPIF global int enable reg */
#define XIPIF_V123B_GINTR_ENABLE	0x80000000

#define XIPIF_V123B_IISR_OFFSET		0x20	/* IPIF interrupt status reg */
#define XIPIF_V123B_IIER_OFFSET		0x28	/* IPIF interrupt enable reg */

#define XSPI_INTR_MODE_FAULT		0x01	/* Mode fault error */
#define XSPI_INTR_SLAVE_MODE_FAULT	0x02	/* Selected as slave while
						 * disabled */
#define XSPI_INTR_TX_EMPTY		0x04	/* TxFIFO is empty */
#define XSPI_INTR_TX_UNDERRUN		0x08	/* TxFIFO was underrun */
#define XSPI_INTR_RX_FULL		0x10	/* RxFIFO is full */
#define XSPI_INTR_RX_OVERRUN		0x20	/* RxFIFO was overrun */

#define XIPIF_V123B_RESETR_OFFSET	0x40	/* IPIF reset register */
#define XIPIF_V123B_RESET_MASK		0x0a	/* the value to write */

struct xilinx_spi {
	/* bitbang has to be first */
	struct spi_bitbang bitbang;
	struct completion done;

	void __iomem	*regs;	/* virt. address of the control registers */

	u32		irq;

	u32		speed_hz; /* SCK has a fixed frequency of speed_hz Hz */

	u8 *rx_ptr;		/* pointer in the Tx buffer */
	const u8 *tx_ptr;	/* pointer in the Rx buffer */
	int remaining_bytes;	/* the number of bytes left to transfer */
};

static void xspi_init_hw(void __iomem *regs_base)
{
	/* Reset the SPI device */
	out_be32(regs_base + XIPIF_V123B_RESETR_OFFSET,
		 XIPIF_V123B_RESET_MASK);
	/* Disable all the interrupts just in case */
	out_be32(regs_base + XIPIF_V123B_IIER_OFFSET, 0);
	/* Enable the global IPIF interrupt */
	out_be32(regs_base + XIPIF_V123B_DGIER_OFFSET,
		 XIPIF_V123B_GINTR_ENABLE);
	/* Deselect the slave on the SPI bus */
	out_be32(regs_base + XSPI_SSR_OFFSET, 0xffff);
	/* Disable the transmitter, enable Manual Slave Select Assertion,
	 * put SPI controller into master mode, and enable it */
	out_be16(regs_base + XSPI_CR_OFFSET,
		 XSPI_CR_TRANS_INHIBIT | XSPI_CR_MANUAL_SSELECT
		 | XSPI_CR_MASTER_MODE | XSPI_CR_ENABLE);
}

static void xilinx_spi_chipselect(struct spi_device *spi, int is_on)
{
	struct xilinx_spi *xspi = spi_master_get_devdata(spi->master);

	if (is_on == BITBANG_CS_INACTIVE) {
		/* Deselect the slave on the SPI bus */
		out_be32(xspi->regs + XSPI_SSR_OFFSET, 0xffff);
	} else if (is_on == BITBANG_CS_ACTIVE) {
		/* Set the SPI clock phase and polarity */
		u16 cr = in_be16(xspi->regs + XSPI_CR_OFFSET)
			 & ~XSPI_CR_MODE_MASK;
		if (spi->mode & SPI_CPHA)
			cr |= XSPI_CR_CPHA;
		if (spi->mode & SPI_CPOL)
			cr |= XSPI_CR_CPOL;
		out_be16(xspi->regs + XSPI_CR_OFFSET, cr);

		/* We do not check spi->max_speed_hz here as the SPI clock
		 * frequency is not software programmable (the IP block design
		 * parameter)
		 */

		/* Activate the chip select */
		out_be32(xspi->regs + XSPI_SSR_OFFSET,
			 ~(0x0001 << spi->chip_select));
	}
}

/* spi_bitbang requires custom setup_transfer() to be defined if there is a
 * custom txrx_bufs(). We have nothing to setup here as the SPI IP block
 * supports just 8 bits per word, and SPI clock can't be changed in software.
 * Check for 8 bits per word. Chip select delay calculations could be
 * added here as soon as bitbang_work() can be made aware of the delay value.
 */
static int xilinx_spi_setup_transfer(struct spi_device *spi,
		struct spi_transfer *t)
{
	u8 bits_per_word;
	u32 hz;
	struct xilinx_spi *xspi = spi_master_get_devdata(spi->master);

	bits_per_word = (t) ? t->bits_per_word : spi->bits_per_word;
	hz = (t) ? t->speed_hz : spi->max_speed_hz;
	if (bits_per_word != 8) {
		dev_err(&spi->dev, "%s, unsupported bits_per_word=%d\n",
			__func__, bits_per_word);
		return -EINVAL;
	}

	if (hz && xspi->speed_hz > hz) {
		dev_err(&spi->dev, "%s, unsupported clock rate %uHz\n",
			__func__, hz);
		return -EINVAL;
	}

	return 0;
}

/* the spi->mode bits understood by this driver: */
#define MODEBITS (SPI_CPOL | SPI_CPHA)

static int xilinx_spi_setup(struct spi_device *spi)
{
	struct spi_bitbang *bitbang;
	struct xilinx_spi *xspi;
	int retval;

	xspi = spi_master_get_devdata(spi->master);
	bitbang = &xspi->bitbang;

	if (!spi->bits_per_word)
		spi->bits_per_word = 8;

	if (spi->mode & ~MODEBITS) {
		dev_err(&spi->dev, "%s, unsupported mode bits %x\n",
			__func__, spi->mode & ~MODEBITS);
		return -EINVAL;
	}

	retval = xilinx_spi_setup_transfer(spi, NULL);
	if (retval < 0)
		return retval;

	dev_dbg(&spi->dev, "%s, mode %d, %u bits/w, %u nsec/bit\n",
		__func__, spi->mode & MODEBITS, spi->bits_per_word, 0);

	return 0;
}

static void xilinx_spi_fill_tx_fifo(struct xilinx_spi *xspi)
{
	u8 sr;

	/* Fill the Tx FIFO with as many bytes as possible */
	sr = in_8(xspi->regs + XSPI_SR_OFFSET);
	while ((sr & XSPI_SR_TX_FULL_MASK) == 0 && xspi->remaining_bytes > 0) {
		if (xspi->tx_ptr) {
			out_8(xspi->regs + XSPI_TXD_OFFSET, *xspi->tx_ptr++);
		} else {
			out_8(xspi->regs + XSPI_TXD_OFFSET, 0);
		}
		xspi->remaining_bytes--;
		sr = in_8(xspi->regs + XSPI_SR_OFFSET);
	}
}

static int xilinx_spi_txrx_bufs(struct spi_device *spi, struct spi_transfer *t)
{
	struct xilinx_spi *xspi = spi_master_get_devdata(spi->master);
	u32 ipif_ier;
	u16 cr;

	/* We get here with transmitter inhibited */

	xspi->tx_ptr = t->tx_buf;
	xspi->rx_ptr = t->rx_buf;
	xspi->remaining_bytes = t->len;
	INIT_COMPLETION(xspi->done);

	xilinx_spi_fill_tx_fifo(xspi);

	/* Enable the transmit empty interrupt, which we use to determine
	 * progress on the transmission.
	 */
	ipif_ier = in_be32(xspi->regs + XIPIF_V123B_IIER_OFFSET);
	out_be32(xspi->regs + XIPIF_V123B_IIER_OFFSET,
		 ipif_ier | XSPI_INTR_TX_EMPTY);

	/* Start the transfer by not inhibiting the transmitter any longer */
	cr = in_be16(xspi->regs + XSPI_CR_OFFSET) & ~XSPI_CR_TRANS_INHIBIT;
	out_be16(xspi->regs + XSPI_CR_OFFSET, cr);

	wait_for_completion(&xspi->done);

	/* Disable the transmit empty interrupt */
	out_be32(xspi->regs + XIPIF_V123B_IIER_OFFSET, ipif_ier);

	return t->len - xspi->remaining_bytes;
}


/* This driver supports single master mode only. Hence Tx FIFO Empty
 * is the only interrupt we care about.
 * Receive FIFO Overrun, Transmit FIFO Underrun, Mode Fault, and Slave Mode
 * Fault are not to happen.
 */
static irqreturn_t xilinx_spi_irq(int irq, void *dev_id)
{
	struct xilinx_spi *xspi = dev_id;
	u32 ipif_isr;

	/* Get the IPIF interrupts, and clear them immediately */
	ipif_isr = in_be32(xspi->regs + XIPIF_V123B_IISR_OFFSET);
	out_be32(xspi->regs + XIPIF_V123B_IISR_OFFSET, ipif_isr);

	if (ipif_isr & XSPI_INTR_TX_EMPTY) {	/* Transmission completed */
		u16 cr;
		u8 sr;

		/* A transmit has just completed. Process received data and
		 * check for more data to transmit. Always inhibit the
		 * transmitter while the Isr refills the transmit register/FIFO,
		 * or make sure it is stopped if we're done.
		 */
		cr = in_be16(xspi->regs + XSPI_CR_OFFSET);
		out_be16(xspi->regs + XSPI_CR_OFFSET,
			 cr | XSPI_CR_TRANS_INHIBIT);

		/* Read out all the data from the Rx FIFO */
		sr = in_8(xspi->regs + XSPI_SR_OFFSET);
		while ((sr & XSPI_SR_RX_EMPTY_MASK) == 0) {
			u8 data;

			data = in_8(xspi->regs + XSPI_RXD_OFFSET);
			if (xspi->rx_ptr) {
				*xspi->rx_ptr++ = data;
			}
			sr = in_8(xspi->regs + XSPI_SR_OFFSET);
		}

		/* See if there is more data to send */
		if (xspi->remaining_bytes > 0) {
			xilinx_spi_fill_tx_fifo(xspi);
			/* Start the transfer by not inhibiting the
			 * transmitter any longer
			 */
			out_be16(xspi->regs + XSPI_CR_OFFSET, cr);
		} else {
			/* No more data to send.
			 * Indicate the transfer is completed.
			 */
			complete(&xspi->done);
		}
	}

	return IRQ_HANDLED;
}

static int __init xilinx_spi_probe(struct platform_device *dev)
{
	int ret = 0;
	struct spi_master *master;
	struct xilinx_spi *xspi;
	struct xspi_platform_data *pdata;
	struct resource *r;

	/* Get resources(memory, IRQ) associated with the device */
	master = spi_alloc_master(&dev->dev, sizeof(struct xilinx_spi));

	if (master == NULL) {
		return -ENOMEM;
	}

	platform_set_drvdata(dev, master);
	pdata = dev->dev.platform_data;

	if (pdata == NULL) {
		ret = -ENODEV;
		goto put_master;
	}

	r = platform_get_resource(dev, IORESOURCE_MEM, 0);
	if (r == NULL) {
		ret = -ENODEV;
		goto put_master;
	}

	xspi = spi_master_get_devdata(master);
	xspi->bitbang.master = spi_master_get(master);
	xspi->bitbang.chipselect = xilinx_spi_chipselect;
	xspi->bitbang.setup_transfer = xilinx_spi_setup_transfer;
	xspi->bitbang.txrx_bufs = xilinx_spi_txrx_bufs;
	xspi->bitbang.master->setup = xilinx_spi_setup;
	init_completion(&xspi->done);

	if (!request_mem_region(r->start,
			r->end - r->start + 1, XILINX_SPI_NAME)) {
		ret = -ENXIO;
		goto put_master;
	}

	xspi->regs = ioremap(r->start, r->end - r->start + 1);
	if (xspi->regs == NULL) {
		ret = -ENOMEM;
		goto put_master;
	}

	ret = platform_get_irq(dev, 0);
	if (ret < 0) {
		ret = -ENXIO;
		goto unmap_io;
	}
	xspi->irq = ret;

	master->bus_num = pdata->bus_num;
	master->num_chipselect = pdata->num_chipselect;
	xspi->speed_hz = pdata->speed_hz;

	/* SPI controller initializations */
	xspi_init_hw(xspi->regs);

	/* Register for SPI Interrupt */
	ret = request_irq(xspi->irq, xilinx_spi_irq, 0, XILINX_SPI_NAME, xspi);
	if (ret != 0)
		goto unmap_io;

	ret = spi_bitbang_start(&xspi->bitbang);
	if (ret != 0) {
		dev_err(&dev->dev, "spi_bitbang_start FAILED\n");
		goto free_irq;
	}

	dev_info(&dev->dev, "at 0x%08X mapped to 0x%08X, irq=%d\n",
			r->start, (u32)xspi->regs, xspi->irq);

	return ret;

free_irq:
	free_irq(xspi->irq, xspi);
unmap_io:
	iounmap(xspi->regs);
put_master:
	spi_master_put(master);
	return ret;
}

static int __devexit xilinx_spi_remove(struct platform_device *dev)
{
	struct xilinx_spi *xspi;
	struct spi_master *master;

	master = platform_get_drvdata(dev);
	xspi = spi_master_get_devdata(master);

	spi_bitbang_stop(&xspi->bitbang);
	free_irq(xspi->irq, xspi);
	iounmap(xspi->regs);
	platform_set_drvdata(dev, 0);
	spi_master_put(xspi->bitbang.master);

	return 0;
}

/* work with hotplug and coldplug */
MODULE_ALIAS("platform:" XILINX_SPI_NAME);

static struct platform_driver xilinx_spi_driver = {
	.probe	= xilinx_spi_probe,
	.remove	= __devexit_p(xilinx_spi_remove),
	.driver = {
		.name = XILINX_SPI_NAME,
		.owner = THIS_MODULE,
	},
};

static int __init xilinx_spi_init(void)
{
	return platform_driver_register(&xilinx_spi_driver);
}
module_init(xilinx_spi_init);

static void __exit xilinx_spi_exit(void)
{
	platform_driver_unregister(&xilinx_spi_driver);
}
module_exit(xilinx_spi_exit);

MODULE_AUTHOR("MontaVista Software, Inc. <source@mvista.com>");
MODULE_DESCRIPTION("Xilinx SPI driver");
MODULE_LICENSE("GPL");
Commit	Line	Data
ae918c02 AK	1	/*
	2	* xilinx_spi.c
	3	*
	4	* Xilinx SPI controller driver (master mode only)
	5	*
	6	* Author: MontaVista Software, Inc.
	7	* source@mvista.com
	8	*
	9	* 2002-2007 (c) MontaVista Software, Inc. This file is licensed under the
	10	* terms of the GNU General Public License version 2. This program is licensed
	11	* "as is" without any warranty of any kind, whether express or implied.
	12	*/
	13
	14	#include <linux/module.h>
	15	#include <linux/init.h>
	16	#include <linux/interrupt.h>
	17	#include <linux/platform_device.h>
	18	#include <linux/spi/spi.h>
	19	#include <linux/spi/spi_bitbang.h>
	20	#include <linux/io.h>
	21
	22	#include <syslib/virtex_devices.h>
	23
fc3ba952	24	#define XILINX_SPI_NAME "xilinx_spi"
ae918c02 AK	25
	26	/* Register definitions as per "OPB Serial Peripheral Interface (SPI) (v1.00e)
	27	* Product Specification", DS464
	28	*/
	29	#define XSPI_CR_OFFSET 0x62 /* 16-bit Control Register */
	30
	31	#define XSPI_CR_ENABLE 0x02
	32	#define XSPI_CR_MASTER_MODE 0x04
	33	#define XSPI_CR_CPOL 0x08
	34	#define XSPI_CR_CPHA 0x10
	35	#define XSPI_CR_MODE_MASK (XSPI_CR_CPHA \| XSPI_CR_CPOL)
	36	#define XSPI_CR_TXFIFO_RESET 0x20
	37	#define XSPI_CR_RXFIFO_RESET 0x40
	38	#define XSPI_CR_MANUAL_SSELECT 0x80
	39	#define XSPI_CR_TRANS_INHIBIT 0x100
	40
	41	#define XSPI_SR_OFFSET 0x67 /* 8-bit Status Register */
	42
	43	#define XSPI_SR_RX_EMPTY_MASK 0x01 /* Receive FIFO is empty */
	44	#define XSPI_SR_RX_FULL_MASK 0x02 /* Receive FIFO is full */
	45	#define XSPI_SR_TX_EMPTY_MASK 0x04 /* Transmit FIFO is empty */
	46	#define XSPI_SR_TX_FULL_MASK 0x08 /* Transmit FIFO is full */
	47	#define XSPI_SR_MODE_FAULT_MASK 0x10 /* Mode fault error */
	48
	49	#define XSPI_TXD_OFFSET 0x6b /* 8-bit Data Transmit Register */
	50	#define XSPI_RXD_OFFSET 0x6f /* 8-bit Data Receive Register */
	51
	52	#define XSPI_SSR_OFFSET 0x70 /* 32-bit Slave Select Register */
	53
	54	/* Register definitions as per "OPB IPIF (v3.01c) Product Specification", DS414
	55	* IPIF registers are 32 bit
	56	*/
	57	#define XIPIF_V123B_DGIER_OFFSET 0x1c /* IPIF global int enable reg */
	58	#define XIPIF_V123B_GINTR_ENABLE 0x80000000
	59
	60	#define XIPIF_V123B_IISR_OFFSET 0x20 /* IPIF interrupt status reg */
	61	#define XIPIF_V123B_IIER_OFFSET 0x28 /* IPIF interrupt enable reg */
	62
	63	#define XSPI_INTR_MODE_FAULT 0x01 /* Mode fault error */
	64	#define XSPI_INTR_SLAVE_MODE_FAULT 0x02 /* Selected as slave while
	65	* disabled */
	66	#define XSPI_INTR_TX_EMPTY 0x04 /* TxFIFO is empty */
	67	#define XSPI_INTR_TX_UNDERRUN 0x08 /* TxFIFO was underrun */
	68	#define XSPI_INTR_RX_FULL 0x10 /* RxFIFO is full */
	69	#define XSPI_INTR_RX_OVERRUN 0x20 /* RxFIFO was overrun */
	70
	71	#define XIPIF_V123B_RESETR_OFFSET 0x40 /* IPIF reset register */
	72	#define XIPIF_V123B_RESET_MASK 0x0a /* the value to write */
	73
	74	struct xilinx_spi {
	75	/* bitbang has to be first */
	76	struct spi_bitbang bitbang;
	77	struct completion done;
	78
	79	void __iomem regs; / virt. address of the control registers */
	80
	81	u32 irq;
	82
	83	u32 speed_hz; /* SCK has a fixed frequency of speed_hz Hz */
	84
	85	u8 rx_ptr; / pointer in the Tx buffer */
	86	const u8 tx_ptr; / pointer in the Rx buffer */
	87	int remaining_bytes; /* the number of bytes left to transfer */
	88	};
89
90	static void xspi_init_hw(void __iomem *regs_base)
91	{
92	/* Reset the SPI device */
93	out_be32(regs_base + XIPIF_V123B_RESETR_OFFSET,
94	XIPIF_V123B_RESET_MASK);
95	/* Disable all the interrupts just in case */
96	out_be32(regs_base + XIPIF_V123B_IIER_OFFSET, 0);
97	/* Enable the global IPIF interrupt */
98	out_be32(regs_base + XIPIF_V123B_DGIER_OFFSET,
99	XIPIF_V123B_GINTR_ENABLE);
100	/* Deselect the slave on the SPI bus */
101	out_be32(regs_base + XSPI_SSR_OFFSET, 0xffff);
102	/* Disable the transmitter, enable Manual Slave Select Assertion,
103	* put SPI controller into master mode, and enable it */
104	out_be16(regs_base + XSPI_CR_OFFSET,
105	XSPI_CR_TRANS_INHIBIT \| XSPI_CR_MANUAL_SSELECT
106	\| XSPI_CR_MASTER_MODE \| XSPI_CR_ENABLE);
107	}
108
109	static void xilinx_spi_chipselect(struct spi_device *spi, int is_on)
110	{
111	struct xilinx_spi *xspi = spi_master_get_devdata(spi->master);
112
113	if (is_on == BITBANG_CS_INACTIVE) {
114	/* Deselect the slave on the SPI bus */
115	out_be32(xspi->regs + XSPI_SSR_OFFSET, 0xffff);
116	} else if (is_on == BITBANG_CS_ACTIVE) {
117	/* Set the SPI clock phase and polarity */
118	u16 cr = in_be16(xspi->regs + XSPI_CR_OFFSET)
119	& ~XSPI_CR_MODE_MASK;
120	if (spi->mode & SPI_CPHA)
121	cr \|= XSPI_CR_CPHA;
122	if (spi->mode & SPI_CPOL)
123	cr \|= XSPI_CR_CPOL;
124	out_be16(xspi->regs + XSPI_CR_OFFSET, cr);
125
126	/* We do not check spi->max_speed_hz here as the SPI clock
127	* frequency is not software programmable (the IP block design
128	* parameter)
129	*/
130
131	/* Activate the chip select */
132	out_be32(xspi->regs + XSPI_SSR_OFFSET,
133	~(0x0001 << spi->chip_select));
134	}
135	}
136
137	/* spi_bitbang requires custom setup_transfer() to be defined if there is a
138	* custom txrx_bufs(). We have nothing to setup here as the SPI IP block
139	* supports just 8 bits per word, and SPI clock can't be changed in software.
140	* Check for 8 bits per word. Chip select delay calculations could be
141	* added here as soon as bitbang_work() can be made aware of the delay value.
142	*/
143	static int xilinx_spi_setup_transfer(struct spi_device *spi,
144	struct spi_transfer *t)
145	{
146	u8 bits_per_word;
147	u32 hz;
148	struct xilinx_spi *xspi = spi_master_get_devdata(spi->master);
149
150	bits_per_word = (t) ? t->bits_per_word : spi->bits_per_word;
151	hz = (t) ? t->speed_hz : spi->max_speed_hz;
152	if (bits_per_word != 8) {
153	dev_err(&spi->dev, "%s, unsupported bits_per_word=%d\n",
b687d2a8	154	__func__, bits_per_word);
ae918c02 AK	155	return -EINVAL;
	156	}
	157
	158	if (hz && xspi->speed_hz > hz) {
	159	dev_err(&spi->dev, "%s, unsupported clock rate %uHz\n",
b687d2a8	160	__func__, hz);
ae918c02 AK	161	return -EINVAL;
	162	}
	163
	164	return 0;
	165	}
	166
	167	/* the spi->mode bits understood by this driver: */
	168	#define MODEBITS (SPI_CPOL \| SPI_CPHA)
	169
	170	static int xilinx_spi_setup(struct spi_device *spi)
	171	{
	172	struct spi_bitbang *bitbang;
	173	struct xilinx_spi *xspi;
	174	int retval;
	175
	176	xspi = spi_master_get_devdata(spi->master);
	177	bitbang = &xspi->bitbang;
	178
	179	if (!spi->bits_per_word)
	180	spi->bits_per_word = 8;
	181
	182	if (spi->mode & ~MODEBITS) {
	183	dev_err(&spi->dev, "%s, unsupported mode bits %x\n",
b687d2a8	184	__func__, spi->mode & ~MODEBITS);
ae918c02 AK	185	return -EINVAL;
	186	}
	187
	188	retval = xilinx_spi_setup_transfer(spi, NULL);
	189	if (retval < 0)
	190	return retval;
	191
	192	dev_dbg(&spi->dev, "%s, mode %d, %u bits/w, %u nsec/bit\n",
b687d2a8	193	__func__, spi->mode & MODEBITS, spi->bits_per_word, 0);
ae918c02 AK	194
	195	return 0;
	196	}
	197
	198	static void xilinx_spi_fill_tx_fifo(struct xilinx_spi *xspi)
	199	{
	200	u8 sr;
	201
	202	/* Fill the Tx FIFO with as many bytes as possible */
	203	sr = in_8(xspi->regs + XSPI_SR_OFFSET);
	204	while ((sr & XSPI_SR_TX_FULL_MASK) == 0 && xspi->remaining_bytes > 0) {
	205	if (xspi->tx_ptr) {
	206	out_8(xspi->regs + XSPI_TXD_OFFSET, *xspi->tx_ptr++);
	207	} else {
	208	out_8(xspi->regs + XSPI_TXD_OFFSET, 0);
	209	}
	210	xspi->remaining_bytes--;
	211	sr = in_8(xspi->regs + XSPI_SR_OFFSET);
	212	}
	213	}
	214
	215	static int xilinx_spi_txrx_bufs(struct spi_device spi, struct spi_transfer t)
	216	{
	217	struct xilinx_spi *xspi = spi_master_get_devdata(spi->master);
	218	u32 ipif_ier;
	219	u16 cr;
	220
	221	/* We get here with transmitter inhibited */
	222
	223	xspi->tx_ptr = t->tx_buf;
	224	xspi->rx_ptr = t->rx_buf;
	225	xspi->remaining_bytes = t->len;
	226	INIT_COMPLETION(xspi->done);
	227
	228	xilinx_spi_fill_tx_fifo(xspi);
	229
	230	/* Enable the transmit empty interrupt, which we use to determine
	231	* progress on the transmission.
	232	*/
	233	ipif_ier = in_be32(xspi->regs + XIPIF_V123B_IIER_OFFSET);
	234	out_be32(xspi->regs + XIPIF_V123B_IIER_OFFSET,
	235	ipif_ier \| XSPI_INTR_TX_EMPTY);
	236
	237	/* Start the transfer by not inhibiting the transmitter any longer */
	238	cr = in_be16(xspi->regs + XSPI_CR_OFFSET) & ~XSPI_CR_TRANS_INHIBIT;
	239	out_be16(xspi->regs + XSPI_CR_OFFSET, cr);
	240
	241	wait_for_completion(&xspi->done);
	242
	243	/* Disable the transmit empty interrupt */
	244	out_be32(xspi->regs + XIPIF_V123B_IIER_OFFSET, ipif_ier);
	245
	246	return t->len - xspi->remaining_bytes;
	247	}
	248
	249
	250	/* This driver supports single master mode only. Hence Tx FIFO Empty
	251	* is the only interrupt we care about.
	252	* Receive FIFO Overrun, Transmit FIFO Underrun, Mode Fault, and Slave Mode
	253	* Fault are not to happen.
	254	*/
	255	static irqreturn_t xilinx_spi_irq(int irq, void *dev_id)
	256	{
	257	struct xilinx_spi *xspi = dev_id;
258	u32 ipif_isr;
259
260	/* Get the IPIF interrupts, and clear them immediately */
261	ipif_isr = in_be32(xspi->regs + XIPIF_V123B_IISR_OFFSET);
262	out_be32(xspi->regs + XIPIF_V123B_IISR_OFFSET, ipif_isr);
263
264	if (ipif_isr & XSPI_INTR_TX_EMPTY) { /* Transmission completed */
265	u16 cr;
266	u8 sr;
267
268	/* A transmit has just completed. Process received data and
269	* check for more data to transmit. Always inhibit the
270	* transmitter while the Isr refills the transmit register/FIFO,
271	* or make sure it is stopped if we're done.
272	*/
273	cr = in_be16(xspi->regs + XSPI_CR_OFFSET);
274	out_be16(xspi->regs + XSPI_CR_OFFSET,
275	cr \| XSPI_CR_TRANS_INHIBIT);
276
277	/* Read out all the data from the Rx FIFO */
278	sr = in_8(xspi->regs + XSPI_SR_OFFSET);
279	while ((sr & XSPI_SR_RX_EMPTY_MASK) == 0) {
280	u8 data;
281
282	data = in_8(xspi->regs + XSPI_RXD_OFFSET);
283	if (xspi->rx_ptr) {
284	*xspi->rx_ptr++ = data;
285	}
286	sr = in_8(xspi->regs + XSPI_SR_OFFSET);
287	}
288
289	/* See if there is more data to send */
290	if (xspi->remaining_bytes > 0) {
291	xilinx_spi_fill_tx_fifo(xspi);
292	/* Start the transfer by not inhibiting the
293	* transmitter any longer
294	*/
295	out_be16(xspi->regs + XSPI_CR_OFFSET, cr);
296	} else {
297	/* No more data to send.
298	* Indicate the transfer is completed.
299	*/
300	complete(&xspi->done);
301	}
302	}
303
304	return IRQ_HANDLED;
305	}
306
307	static int __init xilinx_spi_probe(struct platform_device *dev)
308	{
309	int ret = 0;
310	struct spi_master *master;
311	struct xilinx_spi *xspi;
312	struct xspi_platform_data *pdata;
313	struct resource *r;
314
315	/* Get resources(memory, IRQ) associated with the device */
316	master = spi_alloc_master(&dev->dev, sizeof(struct xilinx_spi));
317
318	if (master == NULL) {
319	return -ENOMEM;
320	}
321
322	platform_set_drvdata(dev, master);
323	pdata = dev->dev.platform_data;
324
325	if (pdata == NULL) {
326	ret = -ENODEV;
327	goto put_master;
328	}
329
330	r = platform_get_resource(dev, IORESOURCE_MEM, 0);
331	if (r == NULL) {
332	ret = -ENODEV;
333	goto put_master;
334	}
335
336	xspi = spi_master_get_devdata(master);
337	xspi->bitbang.master = spi_master_get(master);
338	xspi->bitbang.chipselect = xilinx_spi_chipselect;
339	xspi->bitbang.setup_transfer = xilinx_spi_setup_transfer;
340	xspi->bitbang.txrx_bufs = xilinx_spi_txrx_bufs;
341	xspi->bitbang.master->setup = xilinx_spi_setup;
342	init_completion(&xspi->done);
343
344	if (!request_mem_region(r->start,
345	r->end - r->start + 1, XILINX_SPI_NAME)) {
346	ret = -ENXIO;
347	goto put_master;
348	}
349
350	xspi->regs = ioremap(r->start, r->end - r->start + 1);
351	if (xspi->regs == NULL) {
352	ret = -ENOMEM;
353	goto put_master;
354	}
355
166a375b RK	356	ret = platform_get_irq(dev, 0);
166a375b RK	357	if (ret < 0) {
ae918c02 AK	358	ret = -ENXIO;
	359	goto unmap_io;
	360	}
166a375b	361	xspi->irq = ret;
ae918c02 AK	362
	363	master->bus_num = pdata->bus_num;
	364	master->num_chipselect = pdata->num_chipselect;
	365	xspi->speed_hz = pdata->speed_hz;
	366
	367	/* SPI controller initializations */
	368	xspi_init_hw(xspi->regs);
	369
	370	/* Register for SPI Interrupt */
	371	ret = request_irq(xspi->irq, xilinx_spi_irq, 0, XILINX_SPI_NAME, xspi);
	372	if (ret != 0)
	373	goto unmap_io;
	374
	375	ret = spi_bitbang_start(&xspi->bitbang);
	376	if (ret != 0) {
	377	dev_err(&dev->dev, "spi_bitbang_start FAILED\n");
	378	goto free_irq;
	379	}
	380
	381	dev_info(&dev->dev, "at 0x%08X mapped to 0x%08X, irq=%d\n",
	382	r->start, (u32)xspi->regs, xspi->irq);
	383
	384	return ret;
	385
	386	free_irq:
	387	free_irq(xspi->irq, xspi);
	388	unmap_io:
	389	iounmap(xspi->regs);
	390	put_master:
	391	spi_master_put(master);
	392	return ret;
	393	}
	394
	395	static int __devexit xilinx_spi_remove(struct platform_device *dev)
	396	{
	397	struct xilinx_spi *xspi;
	398	struct spi_master *master;
	399
	400	master = platform_get_drvdata(dev);
	401	xspi = spi_master_get_devdata(master);
	402
	403	spi_bitbang_stop(&xspi->bitbang);
	404	free_irq(xspi->irq, xspi);
	405	iounmap(xspi->regs);
	406	platform_set_drvdata(dev, 0);
	407	spi_master_put(xspi->bitbang.master);
	408
	409	return 0;
	410	}
	411
7e38c3c4 KS	412	/* work with hotplug and coldplug */
	413	MODULE_ALIAS("platform:" XILINX_SPI_NAME);
	414
ae918c02 AK	415	static struct platform_driver xilinx_spi_driver = {
	416	.probe = xilinx_spi_probe,
	417	.remove = __devexit_p(xilinx_spi_remove),
	418	.driver = {
	419	.name = XILINX_SPI_NAME,
	420	.owner = THIS_MODULE,
	421	},
	422	};
	423
	424	static int __init xilinx_spi_init(void)
	425	{
	426	return platform_driver_register(&xilinx_spi_driver);
	427	}
	428	module_init(xilinx_spi_init);
	429
	430	static void __exit xilinx_spi_exit(void)
	431	{
	432	platform_driver_unregister(&xilinx_spi_driver);
	433	}
	434	module_exit(xilinx_spi_exit);
	435
	436	MODULE_AUTHOR("MontaVista Software, Inc. <source@mvista.com>");
	437	MODULE_DESCRIPTION("Xilinx SPI driver");
	438	MODULE_LICENSE("GPL");