Commit | Line | Data |
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61e115a5 MB |
1 | /* |
2 | * Sonics Silicon Backplane | |
3 | * Broadcom ChipCommon core driver | |
4 | * | |
5 | * Copyright 2005, Broadcom Corporation | |
6 | * Copyright 2006, 2007, Michael Buesch <mb@bu3sch.de> | |
7 | * | |
8 | * Licensed under the GNU/GPL. See COPYING for details. | |
9 | */ | |
10 | ||
11 | #include <linux/ssb/ssb.h> | |
12 | #include <linux/ssb/ssb_regs.h> | |
13 | #include <linux/pci.h> | |
14 | ||
15 | #include "ssb_private.h" | |
16 | ||
17 | ||
18 | /* Clock sources */ | |
19 | enum ssb_clksrc { | |
20 | /* PCI clock */ | |
21 | SSB_CHIPCO_CLKSRC_PCI, | |
22 | /* Crystal slow clock oscillator */ | |
23 | SSB_CHIPCO_CLKSRC_XTALOS, | |
24 | /* Low power oscillator */ | |
25 | SSB_CHIPCO_CLKSRC_LOPWROS, | |
26 | }; | |
27 | ||
28 | ||
c2bcbe65 MB |
29 | static inline u32 chipco_write32_masked(struct ssb_chipcommon *cc, u16 offset, |
30 | u32 mask, u32 value) | |
61e115a5 MB |
31 | { |
32 | value &= mask; | |
33 | value |= chipco_read32(cc, offset) & ~mask; | |
34 | chipco_write32(cc, offset, value); | |
c2bcbe65 MB |
35 | |
36 | return value; | |
61e115a5 MB |
37 | } |
38 | ||
39 | void ssb_chipco_set_clockmode(struct ssb_chipcommon *cc, | |
40 | enum ssb_clkmode mode) | |
41 | { | |
42 | struct ssb_device *ccdev = cc->dev; | |
43 | struct ssb_bus *bus; | |
44 | u32 tmp; | |
45 | ||
46 | if (!ccdev) | |
47 | return; | |
48 | bus = ccdev->bus; | |
49 | /* chipcommon cores prior to rev6 don't support dynamic clock control */ | |
50 | if (ccdev->id.revision < 6) | |
51 | return; | |
52 | /* chipcommon cores rev10 are a whole new ball game */ | |
53 | if (ccdev->id.revision >= 10) | |
54 | return; | |
55 | if (!(cc->capabilities & SSB_CHIPCO_CAP_PCTL)) | |
56 | return; | |
57 | ||
58 | switch (mode) { | |
59 | case SSB_CLKMODE_SLOW: | |
60 | tmp = chipco_read32(cc, SSB_CHIPCO_SLOWCLKCTL); | |
61 | tmp |= SSB_CHIPCO_SLOWCLKCTL_FSLOW; | |
62 | chipco_write32(cc, SSB_CHIPCO_SLOWCLKCTL, tmp); | |
63 | break; | |
64 | case SSB_CLKMODE_FAST: | |
65 | ssb_pci_xtal(bus, SSB_GPIO_XTAL, 1); /* Force crystal on */ | |
66 | tmp = chipco_read32(cc, SSB_CHIPCO_SLOWCLKCTL); | |
67 | tmp &= ~SSB_CHIPCO_SLOWCLKCTL_FSLOW; | |
68 | tmp |= SSB_CHIPCO_SLOWCLKCTL_IPLL; | |
69 | chipco_write32(cc, SSB_CHIPCO_SLOWCLKCTL, tmp); | |
70 | break; | |
71 | case SSB_CLKMODE_DYNAMIC: | |
72 | tmp = chipco_read32(cc, SSB_CHIPCO_SLOWCLKCTL); | |
73 | tmp &= ~SSB_CHIPCO_SLOWCLKCTL_FSLOW; | |
74 | tmp &= ~SSB_CHIPCO_SLOWCLKCTL_IPLL; | |
75 | tmp &= ~SSB_CHIPCO_SLOWCLKCTL_ENXTAL; | |
76 | if ((tmp & SSB_CHIPCO_SLOWCLKCTL_SRC) != SSB_CHIPCO_SLOWCLKCTL_SRC_XTAL) | |
77 | tmp |= SSB_CHIPCO_SLOWCLKCTL_ENXTAL; | |
78 | chipco_write32(cc, SSB_CHIPCO_SLOWCLKCTL, tmp); | |
79 | ||
80 | /* for dynamic control, we have to release our xtal_pu "force on" */ | |
81 | if (tmp & SSB_CHIPCO_SLOWCLKCTL_ENXTAL) | |
82 | ssb_pci_xtal(bus, SSB_GPIO_XTAL, 0); | |
83 | break; | |
84 | default: | |
85 | SSB_WARN_ON(1); | |
86 | } | |
87 | } | |
88 | ||
89 | /* Get the Slow Clock Source */ | |
90 | static enum ssb_clksrc chipco_pctl_get_slowclksrc(struct ssb_chipcommon *cc) | |
91 | { | |
92 | struct ssb_bus *bus = cc->dev->bus; | |
93 | u32 uninitialized_var(tmp); | |
94 | ||
95 | if (cc->dev->id.revision < 6) { | |
96 | if (bus->bustype == SSB_BUSTYPE_SSB || | |
97 | bus->bustype == SSB_BUSTYPE_PCMCIA) | |
98 | return SSB_CHIPCO_CLKSRC_XTALOS; | |
99 | if (bus->bustype == SSB_BUSTYPE_PCI) { | |
100 | pci_read_config_dword(bus->host_pci, SSB_GPIO_OUT, &tmp); | |
101 | if (tmp & 0x10) | |
102 | return SSB_CHIPCO_CLKSRC_PCI; | |
103 | return SSB_CHIPCO_CLKSRC_XTALOS; | |
104 | } | |
105 | } | |
106 | if (cc->dev->id.revision < 10) { | |
107 | tmp = chipco_read32(cc, SSB_CHIPCO_SLOWCLKCTL); | |
108 | tmp &= 0x7; | |
109 | if (tmp == 0) | |
110 | return SSB_CHIPCO_CLKSRC_LOPWROS; | |
111 | if (tmp == 1) | |
112 | return SSB_CHIPCO_CLKSRC_XTALOS; | |
113 | if (tmp == 2) | |
114 | return SSB_CHIPCO_CLKSRC_PCI; | |
115 | } | |
116 | ||
117 | return SSB_CHIPCO_CLKSRC_XTALOS; | |
118 | } | |
119 | ||
120 | /* Get maximum or minimum (depending on get_max flag) slowclock frequency. */ | |
121 | static int chipco_pctl_clockfreqlimit(struct ssb_chipcommon *cc, int get_max) | |
122 | { | |
123 | int uninitialized_var(limit); | |
124 | enum ssb_clksrc clocksrc; | |
125 | int divisor = 1; | |
126 | u32 tmp; | |
127 | ||
128 | clocksrc = chipco_pctl_get_slowclksrc(cc); | |
129 | if (cc->dev->id.revision < 6) { | |
130 | switch (clocksrc) { | |
131 | case SSB_CHIPCO_CLKSRC_PCI: | |
132 | divisor = 64; | |
133 | break; | |
134 | case SSB_CHIPCO_CLKSRC_XTALOS: | |
135 | divisor = 32; | |
136 | break; | |
137 | default: | |
138 | SSB_WARN_ON(1); | |
139 | } | |
140 | } else if (cc->dev->id.revision < 10) { | |
141 | switch (clocksrc) { | |
142 | case SSB_CHIPCO_CLKSRC_LOPWROS: | |
143 | break; | |
144 | case SSB_CHIPCO_CLKSRC_XTALOS: | |
145 | case SSB_CHIPCO_CLKSRC_PCI: | |
146 | tmp = chipco_read32(cc, SSB_CHIPCO_SLOWCLKCTL); | |
147 | divisor = (tmp >> 16) + 1; | |
148 | divisor *= 4; | |
149 | break; | |
150 | } | |
151 | } else { | |
152 | tmp = chipco_read32(cc, SSB_CHIPCO_SYSCLKCTL); | |
153 | divisor = (tmp >> 16) + 1; | |
154 | divisor *= 4; | |
155 | } | |
156 | ||
157 | switch (clocksrc) { | |
158 | case SSB_CHIPCO_CLKSRC_LOPWROS: | |
159 | if (get_max) | |
160 | limit = 43000; | |
161 | else | |
162 | limit = 25000; | |
163 | break; | |
164 | case SSB_CHIPCO_CLKSRC_XTALOS: | |
165 | if (get_max) | |
166 | limit = 20200000; | |
167 | else | |
168 | limit = 19800000; | |
169 | break; | |
170 | case SSB_CHIPCO_CLKSRC_PCI: | |
171 | if (get_max) | |
172 | limit = 34000000; | |
173 | else | |
174 | limit = 25000000; | |
175 | break; | |
176 | } | |
177 | limit /= divisor; | |
178 | ||
179 | return limit; | |
180 | } | |
181 | ||
182 | static void chipco_powercontrol_init(struct ssb_chipcommon *cc) | |
183 | { | |
184 | struct ssb_bus *bus = cc->dev->bus; | |
185 | ||
186 | if (bus->chip_id == 0x4321) { | |
187 | if (bus->chip_rev == 0) | |
188 | chipco_write32(cc, SSB_CHIPCO_CHIPCTL, 0x3A4); | |
189 | else if (bus->chip_rev == 1) | |
190 | chipco_write32(cc, SSB_CHIPCO_CHIPCTL, 0xA4); | |
191 | } | |
192 | ||
193 | if (!(cc->capabilities & SSB_CHIPCO_CAP_PCTL)) | |
194 | return; | |
195 | ||
196 | if (cc->dev->id.revision >= 10) { | |
197 | /* Set Idle Power clock rate to 1Mhz */ | |
198 | chipco_write32(cc, SSB_CHIPCO_SYSCLKCTL, | |
199 | (chipco_read32(cc, SSB_CHIPCO_SYSCLKCTL) & | |
200 | 0x0000FFFF) | 0x00040000); | |
201 | } else { | |
202 | int maxfreq; | |
203 | ||
204 | maxfreq = chipco_pctl_clockfreqlimit(cc, 1); | |
205 | chipco_write32(cc, SSB_CHIPCO_PLLONDELAY, | |
206 | (maxfreq * 150 + 999999) / 1000000); | |
207 | chipco_write32(cc, SSB_CHIPCO_FREFSELDELAY, | |
208 | (maxfreq * 15 + 999999) / 1000000); | |
209 | } | |
210 | } | |
211 | ||
fd515941 RM |
212 | /* http://bcm-v4.sipsolutions.net/802.11/PmuFastPwrupDelay */ |
213 | static u16 pmu_fast_powerup_delay(struct ssb_chipcommon *cc) | |
214 | { | |
215 | struct ssb_bus *bus = cc->dev->bus; | |
216 | ||
217 | switch (bus->chip_id) { | |
218 | case 0x4312: | |
219 | case 0x4322: | |
220 | case 0x4328: | |
221 | return 7000; | |
222 | case 0x4325: | |
223 | /* TODO: */ | |
224 | default: | |
225 | return 15000; | |
226 | } | |
227 | } | |
228 | ||
229 | /* http://bcm-v4.sipsolutions.net/802.11/ClkctlFastPwrupDelay */ | |
61e115a5 MB |
230 | static void calc_fast_powerup_delay(struct ssb_chipcommon *cc) |
231 | { | |
232 | struct ssb_bus *bus = cc->dev->bus; | |
233 | int minfreq; | |
234 | unsigned int tmp; | |
235 | u32 pll_on_delay; | |
236 | ||
237 | if (bus->bustype != SSB_BUSTYPE_PCI) | |
238 | return; | |
fd515941 RM |
239 | |
240 | if (cc->capabilities & SSB_CHIPCO_CAP_PMU) { | |
241 | cc->fast_pwrup_delay = pmu_fast_powerup_delay(cc); | |
242 | return; | |
243 | } | |
244 | ||
61e115a5 MB |
245 | if (!(cc->capabilities & SSB_CHIPCO_CAP_PCTL)) |
246 | return; | |
247 | ||
248 | minfreq = chipco_pctl_clockfreqlimit(cc, 0); | |
249 | pll_on_delay = chipco_read32(cc, SSB_CHIPCO_PLLONDELAY); | |
250 | tmp = (((pll_on_delay + 2) * 1000000) + (minfreq - 1)) / minfreq; | |
251 | SSB_WARN_ON(tmp & ~0xFFFF); | |
252 | ||
253 | cc->fast_pwrup_delay = tmp; | |
254 | } | |
255 | ||
256 | void ssb_chipcommon_init(struct ssb_chipcommon *cc) | |
257 | { | |
258 | if (!cc->dev) | |
259 | return; /* We don't have a ChipCommon */ | |
d53cdbb9 JL |
260 | if (cc->dev->id.revision >= 11) |
261 | cc->status = chipco_read32(cc, SSB_CHIPCO_CHIPSTAT); | |
c9703146 | 262 | ssb_pmu_init(cc); |
61e115a5 MB |
263 | chipco_powercontrol_init(cc); |
264 | ssb_chipco_set_clockmode(cc, SSB_CLKMODE_FAST); | |
265 | calc_fast_powerup_delay(cc); | |
266 | } | |
267 | ||
8fe2b65a | 268 | void ssb_chipco_suspend(struct ssb_chipcommon *cc) |
61e115a5 MB |
269 | { |
270 | if (!cc->dev) | |
271 | return; | |
272 | ssb_chipco_set_clockmode(cc, SSB_CLKMODE_SLOW); | |
273 | } | |
274 | ||
275 | void ssb_chipco_resume(struct ssb_chipcommon *cc) | |
276 | { | |
277 | if (!cc->dev) | |
278 | return; | |
279 | chipco_powercontrol_init(cc); | |
280 | ssb_chipco_set_clockmode(cc, SSB_CLKMODE_FAST); | |
281 | } | |
282 | ||
283 | /* Get the processor clock */ | |
284 | void ssb_chipco_get_clockcpu(struct ssb_chipcommon *cc, | |
285 | u32 *plltype, u32 *n, u32 *m) | |
286 | { | |
287 | *n = chipco_read32(cc, SSB_CHIPCO_CLOCK_N); | |
288 | *plltype = (cc->capabilities & SSB_CHIPCO_CAP_PLLT); | |
289 | switch (*plltype) { | |
290 | case SSB_PLLTYPE_2: | |
291 | case SSB_PLLTYPE_4: | |
292 | case SSB_PLLTYPE_6: | |
293 | case SSB_PLLTYPE_7: | |
294 | *m = chipco_read32(cc, SSB_CHIPCO_CLOCK_MIPS); | |
295 | break; | |
296 | case SSB_PLLTYPE_3: | |
297 | /* 5350 uses m2 to control mips */ | |
298 | *m = chipco_read32(cc, SSB_CHIPCO_CLOCK_M2); | |
299 | break; | |
300 | default: | |
301 | *m = chipco_read32(cc, SSB_CHIPCO_CLOCK_SB); | |
302 | break; | |
303 | } | |
304 | } | |
305 | ||
306 | /* Get the bus clock */ | |
307 | void ssb_chipco_get_clockcontrol(struct ssb_chipcommon *cc, | |
308 | u32 *plltype, u32 *n, u32 *m) | |
309 | { | |
310 | *n = chipco_read32(cc, SSB_CHIPCO_CLOCK_N); | |
311 | *plltype = (cc->capabilities & SSB_CHIPCO_CAP_PLLT); | |
312 | switch (*plltype) { | |
313 | case SSB_PLLTYPE_6: /* 100/200 or 120/240 only */ | |
314 | *m = chipco_read32(cc, SSB_CHIPCO_CLOCK_MIPS); | |
315 | break; | |
316 | case SSB_PLLTYPE_3: /* 25Mhz, 2 dividers */ | |
317 | if (cc->dev->bus->chip_id != 0x5365) { | |
318 | *m = chipco_read32(cc, SSB_CHIPCO_CLOCK_M2); | |
319 | break; | |
320 | } | |
321 | /* Fallthough */ | |
322 | default: | |
323 | *m = chipco_read32(cc, SSB_CHIPCO_CLOCK_SB); | |
324 | } | |
325 | } | |
326 | ||
327 | void ssb_chipco_timing_init(struct ssb_chipcommon *cc, | |
328 | unsigned long ns) | |
329 | { | |
330 | struct ssb_device *dev = cc->dev; | |
331 | struct ssb_bus *bus = dev->bus; | |
332 | u32 tmp; | |
333 | ||
334 | /* set register for external IO to control LED. */ | |
335 | chipco_write32(cc, SSB_CHIPCO_PROG_CFG, 0x11); | |
336 | tmp = DIV_ROUND_UP(10, ns) << SSB_PROG_WCNT_3_SHIFT; /* Waitcount-3 = 10ns */ | |
337 | tmp |= DIV_ROUND_UP(40, ns) << SSB_PROG_WCNT_1_SHIFT; /* Waitcount-1 = 40ns */ | |
338 | tmp |= DIV_ROUND_UP(240, ns); /* Waitcount-0 = 240ns */ | |
339 | chipco_write32(cc, SSB_CHIPCO_PROG_WAITCNT, tmp); /* 0x01020a0c for a 100Mhz clock */ | |
340 | ||
341 | /* Set timing for the flash */ | |
342 | tmp = DIV_ROUND_UP(10, ns) << SSB_FLASH_WCNT_3_SHIFT; /* Waitcount-3 = 10nS */ | |
343 | tmp |= DIV_ROUND_UP(10, ns) << SSB_FLASH_WCNT_1_SHIFT; /* Waitcount-1 = 10nS */ | |
344 | tmp |= DIV_ROUND_UP(120, ns); /* Waitcount-0 = 120nS */ | |
345 | if ((bus->chip_id == 0x5365) || | |
346 | (dev->id.revision < 9)) | |
347 | chipco_write32(cc, SSB_CHIPCO_FLASH_WAITCNT, tmp); | |
348 | if ((bus->chip_id == 0x5365) || | |
349 | (dev->id.revision < 9) || | |
350 | ((bus->chip_id == 0x5350) && (bus->chip_rev == 0))) | |
351 | chipco_write32(cc, SSB_CHIPCO_PCMCIA_MEMWAIT, tmp); | |
352 | ||
353 | if (bus->chip_id == 0x5350) { | |
354 | /* Enable EXTIF */ | |
355 | tmp = DIV_ROUND_UP(10, ns) << SSB_PROG_WCNT_3_SHIFT; /* Waitcount-3 = 10ns */ | |
356 | tmp |= DIV_ROUND_UP(20, ns) << SSB_PROG_WCNT_2_SHIFT; /* Waitcount-2 = 20ns */ | |
357 | tmp |= DIV_ROUND_UP(100, ns) << SSB_PROG_WCNT_1_SHIFT; /* Waitcount-1 = 100ns */ | |
358 | tmp |= DIV_ROUND_UP(120, ns); /* Waitcount-0 = 120ns */ | |
359 | chipco_write32(cc, SSB_CHIPCO_PROG_WAITCNT, tmp); /* 0x01020a0c for a 100Mhz clock */ | |
360 | } | |
361 | } | |
362 | ||
363 | /* Set chip watchdog reset timer to fire in 'ticks' backplane cycles */ | |
6b9bafec | 364 | void ssb_chipco_watchdog_timer_set(struct ssb_chipcommon *cc, u32 ticks) |
61e115a5 MB |
365 | { |
366 | /* instant NMI */ | |
367 | chipco_write32(cc, SSB_CHIPCO_WATCHDOG, ticks); | |
368 | } | |
369 | ||
28de57d1 AJ |
370 | void ssb_chipco_irq_mask(struct ssb_chipcommon *cc, u32 mask, u32 value) |
371 | { | |
372 | chipco_write32_masked(cc, SSB_CHIPCO_IRQMASK, mask, value); | |
373 | } | |
374 | ||
375 | u32 ssb_chipco_irq_status(struct ssb_chipcommon *cc, u32 mask) | |
376 | { | |
377 | return chipco_read32(cc, SSB_CHIPCO_IRQSTAT) & mask; | |
378 | } | |
379 | ||
61e115a5 MB |
380 | u32 ssb_chipco_gpio_in(struct ssb_chipcommon *cc, u32 mask) |
381 | { | |
382 | return chipco_read32(cc, SSB_CHIPCO_GPIOIN) & mask; | |
383 | } | |
c2bcbe65 MB |
384 | |
385 | u32 ssb_chipco_gpio_out(struct ssb_chipcommon *cc, u32 mask, u32 value) | |
386 | { | |
387 | return chipco_write32_masked(cc, SSB_CHIPCO_GPIOOUT, mask, value); | |
388 | } | |
c2bcbe65 MB |
389 | |
390 | u32 ssb_chipco_gpio_outen(struct ssb_chipcommon *cc, u32 mask, u32 value) | |
391 | { | |
392 | return chipco_write32_masked(cc, SSB_CHIPCO_GPIOOUTEN, mask, value); | |
393 | } | |
c2bcbe65 MB |
394 | |
395 | u32 ssb_chipco_gpio_control(struct ssb_chipcommon *cc, u32 mask, u32 value) | |
396 | { | |
397 | return chipco_write32_masked(cc, SSB_CHIPCO_GPIOCTL, mask, value); | |
398 | } | |
85373ee8 | 399 | EXPORT_SYMBOL(ssb_chipco_gpio_control); |
61e115a5 | 400 | |
c2bcbe65 | 401 | u32 ssb_chipco_gpio_intmask(struct ssb_chipcommon *cc, u32 mask, u32 value) |
61e115a5 | 402 | { |
c2bcbe65 | 403 | return chipco_write32_masked(cc, SSB_CHIPCO_GPIOIRQ, mask, value); |
61e115a5 MB |
404 | } |
405 | ||
c2bcbe65 | 406 | u32 ssb_chipco_gpio_polarity(struct ssb_chipcommon *cc, u32 mask, u32 value) |
61e115a5 | 407 | { |
c2bcbe65 | 408 | return chipco_write32_masked(cc, SSB_CHIPCO_GPIOPOL, mask, value); |
61e115a5 MB |
409 | } |
410 | ||
411 | #ifdef CONFIG_SSB_SERIAL | |
412 | int ssb_chipco_serial_init(struct ssb_chipcommon *cc, | |
413 | struct ssb_serial_port *ports) | |
414 | { | |
415 | struct ssb_bus *bus = cc->dev->bus; | |
416 | int nr_ports = 0; | |
417 | u32 plltype; | |
418 | unsigned int irq; | |
419 | u32 baud_base, div; | |
420 | u32 i, n; | |
58ff70d4 | 421 | unsigned int ccrev = cc->dev->id.revision; |
61e115a5 MB |
422 | |
423 | plltype = (cc->capabilities & SSB_CHIPCO_CAP_PLLT); | |
424 | irq = ssb_mips_irq(cc->dev); | |
425 | ||
426 | if (plltype == SSB_PLLTYPE_1) { | |
427 | /* PLL clock */ | |
428 | baud_base = ssb_calc_clock_rate(plltype, | |
429 | chipco_read32(cc, SSB_CHIPCO_CLOCK_N), | |
430 | chipco_read32(cc, SSB_CHIPCO_CLOCK_M2)); | |
431 | div = 1; | |
432 | } else { | |
58ff70d4 MB |
433 | if (ccrev == 20) { |
434 | /* BCM5354 uses constant 25MHz clock */ | |
435 | baud_base = 25000000; | |
436 | div = 48; | |
437 | /* Set the override bit so we don't divide it */ | |
438 | chipco_write32(cc, SSB_CHIPCO_CORECTL, | |
439 | chipco_read32(cc, SSB_CHIPCO_CORECTL) | |
440 | | SSB_CHIPCO_CORECTL_UARTCLK0); | |
441 | } else if ((ccrev >= 11) && (ccrev != 15)) { | |
61e115a5 MB |
442 | /* Fixed ALP clock */ |
443 | baud_base = 20000000; | |
58ff70d4 MB |
444 | if (cc->capabilities & SSB_CHIPCO_CAP_PMU) { |
445 | /* FIXME: baud_base is different for devices with a PMU */ | |
446 | SSB_WARN_ON(1); | |
447 | } | |
61e115a5 | 448 | div = 1; |
58ff70d4 MB |
449 | if (ccrev >= 21) { |
450 | /* Turn off UART clock before switching clocksource. */ | |
451 | chipco_write32(cc, SSB_CHIPCO_CORECTL, | |
452 | chipco_read32(cc, SSB_CHIPCO_CORECTL) | |
453 | & ~SSB_CHIPCO_CORECTL_UARTCLKEN); | |
454 | } | |
61e115a5 MB |
455 | /* Set the override bit so we don't divide it */ |
456 | chipco_write32(cc, SSB_CHIPCO_CORECTL, | |
58ff70d4 MB |
457 | chipco_read32(cc, SSB_CHIPCO_CORECTL) |
458 | | SSB_CHIPCO_CORECTL_UARTCLK0); | |
459 | if (ccrev >= 21) { | |
460 | /* Re-enable the UART clock. */ | |
461 | chipco_write32(cc, SSB_CHIPCO_CORECTL, | |
462 | chipco_read32(cc, SSB_CHIPCO_CORECTL) | |
463 | | SSB_CHIPCO_CORECTL_UARTCLKEN); | |
464 | } | |
465 | } else if (ccrev >= 3) { | |
61e115a5 MB |
466 | /* Internal backplane clock */ |
467 | baud_base = ssb_clockspeed(bus); | |
468 | div = chipco_read32(cc, SSB_CHIPCO_CLKDIV) | |
469 | & SSB_CHIPCO_CLKDIV_UART; | |
470 | } else { | |
471 | /* Fixed internal backplane clock */ | |
472 | baud_base = 88000000; | |
473 | div = 48; | |
474 | } | |
475 | ||
476 | /* Clock source depends on strapping if UartClkOverride is unset */ | |
58ff70d4 | 477 | if ((ccrev > 0) && |
61e115a5 MB |
478 | !(chipco_read32(cc, SSB_CHIPCO_CORECTL) & SSB_CHIPCO_CORECTL_UARTCLK0)) { |
479 | if ((cc->capabilities & SSB_CHIPCO_CAP_UARTCLK) == | |
480 | SSB_CHIPCO_CAP_UARTCLK_INT) { | |
481 | /* Internal divided backplane clock */ | |
482 | baud_base /= div; | |
483 | } else { | |
484 | /* Assume external clock of 1.8432 MHz */ | |
485 | baud_base = 1843200; | |
486 | } | |
487 | } | |
488 | } | |
489 | ||
490 | /* Determine the registers of the UARTs */ | |
491 | n = (cc->capabilities & SSB_CHIPCO_CAP_NRUART); | |
492 | for (i = 0; i < n; i++) { | |
493 | void __iomem *cc_mmio; | |
494 | void __iomem *uart_regs; | |
495 | ||
496 | cc_mmio = cc->dev->bus->mmio + (cc->dev->core_index * SSB_CORE_SIZE); | |
497 | uart_regs = cc_mmio + SSB_CHIPCO_UART0_DATA; | |
498 | /* Offset changed at after rev 0 */ | |
58ff70d4 | 499 | if (ccrev == 0) |
61e115a5 MB |
500 | uart_regs += (i * 8); |
501 | else | |
502 | uart_regs += (i * 256); | |
503 | ||
504 | nr_ports++; | |
505 | ports[i].regs = uart_regs; | |
506 | ports[i].irq = irq; | |
507 | ports[i].baud_base = baud_base; | |
508 | ports[i].reg_shift = 0; | |
509 | } | |
510 | ||
511 | return nr_ports; | |
512 | } | |
513 | #endif /* CONFIG_SSB_SERIAL */ |