[deliverable/linux.git] / drivers / staging / bcm / Ioctl.h

#ifndef _IOCTL_H_
#define _IOCTL_H_

typedef struct rdmbuffer {
	unsigned long Register;
	unsigned long Length;
} __packed RDM_BUFFER, *PRDM_BUFFER;

typedef struct wrmbuffer {
	unsigned long Register;
	unsigned long Length;
	unsigned char Data[4];
} __packed WRM_BUFFER, *PWRM_BUFFER;

typedef struct ioctlbuffer {
	void __user *InputBuffer;
	unsigned long InputLength;
	void __user *OutputBuffer;
	unsigned long OutputLength;
} __packed IOCTL_BUFFER, *PIOCTL_BUFFER;

typedef struct stGPIOInfo {
	unsigned int uiGpioNumber; /* valid numbers 0-15 */
	unsigned int uiGpioValue; /* 1 set ; 0 not  set */
} __packed GPIO_INFO, *PGPIO_INFO;

typedef struct stUserThreadReq {
	/* 0->Inactivate LED thread. */
	/* 1->Activate the LED thread */
	unsigned int ThreadState;
} __packed USER_THREAD_REQ, *PUSER_THREAD_REQ;

#define LED_THREAD_ACTIVATION_REQ  1
#define BCM_IOCTL				'k'
#define IOCTL_SEND_CONTROL_MESSAGE		_IOW(BCM_IOCTL,	0x801, int)
#define IOCTL_BCM_REGISTER_WRITE		_IOW(BCM_IOCTL, 0x802, int)
#define IOCTL_BCM_REGISTER_READ			_IOR(BCM_IOCTL, 0x803, int)
#define IOCTL_BCM_COMMON_MEMORY_WRITE		_IOW(BCM_IOCTL, 0x804, int)
#define IOCTL_BCM_COMMON_MEMORY_READ		_IOR(BCM_IOCTL, 0x805, int)
#define IOCTL_GET_CONTROL_MESSAGE		_IOR(BCM_IOCTL,	0x806, int)
#define IOCTL_BCM_FIRMWARE_DOWNLOAD		_IOW(BCM_IOCTL, 0x807, int)
#define IOCTL_BCM_SET_SEND_VCID			_IOW(BCM_IOCTL,	0x808, int)
#define IOCTL_BCM_SWITCH_TRANSFER_MODE		_IOW(BCM_IOCTL, 0x809, int)
#define IOCTL_LINK_REQ				_IOW(BCM_IOCTL, 0x80A, int)
#define IOCTL_RSSI_LEVEL_REQ			_IOW(BCM_IOCTL, 0x80B, int)
#define IOCTL_IDLE_REQ				_IOW(BCM_IOCTL, 0x80C, int)
#define IOCTL_SS_INFO_REQ			_IOW(BCM_IOCTL, 0x80D, int)
#define IOCTL_GET_STATISTICS_POINTER		_IOW(BCM_IOCTL, 0x80E, int)
#define IOCTL_CM_REQUEST			_IOW(BCM_IOCTL, 0x80F, int)
#define IOCTL_INIT_PARAM_REQ			_IOW(BCM_IOCTL, 0x810, int)
#define IOCTL_MAC_ADDR_REQ			_IOW(BCM_IOCTL, 0x811, int)
#define IOCTL_MAC_ADDR_RESP			_IOWR(BCM_IOCTL, 0x812, int)
#define IOCTL_CLASSIFICATION_RULE		_IOW(BCM_IOCTL, 0x813, char)
#define IOCTL_CLOSE_NOTIFICATION		_IO(BCM_IOCTL, 0x814)
#define IOCTL_LINK_UP				_IO(BCM_IOCTL, 0x815)
#define IOCTL_LINK_DOWN				_IO(BCM_IOCTL, 0x816, IOCTL_BUFFER)
#define IOCTL_CHIP_RESET			_IO(BCM_IOCTL, 0x816)
#define IOCTL_CINR_LEVEL_REQ			_IOW(BCM_IOCTL, 0x817, char)
#define IOCTL_WTM_CONTROL_REQ			_IOW(BCM_IOCTL, 0x817, char)
#define IOCTL_BE_BUCKET_SIZE			_IOW(BCM_IOCTL, 0x818, unsigned long)
#define IOCTL_RTPS_BUCKET_SIZE			_IOW(BCM_IOCTL, 0x819, unsigned long)
#define IOCTL_QOS_THRESHOLD			_IOW(BCM_IOCTL, 0x820, unsigned long)
#define IOCTL_DUMP_PACKET_INFO			_IO(BCM_IOCTL, 0x821)
#define IOCTL_GET_PACK_INFO			_IOR(BCM_IOCTL, 0x823, int)
#define IOCTL_BCM_GET_DRIVER_VERSION		_IOR(BCM_IOCTL, 0x829, int)
#define IOCTL_BCM_GET_CURRENT_STATUS		_IOW(BCM_IOCTL, 0x828, int)
#define IOCTL_BCM_GPIO_SET_REQUEST		_IOW(BCM_IOCTL, 0x82A, int)
#define IOCTL_BCM_GPIO_STATUS_REQUEST		_IOW(BCM_IOCTL, 0x82b, int)
#define IOCTL_BCM_GET_DSX_INDICATION		_IOR(BCM_IOCTL, 0x854, int)
#define IOCTL_BCM_BUFFER_DOWNLOAD_START		_IOW(BCM_IOCTL, 0x855, int)
#define IOCTL_BCM_BUFFER_DOWNLOAD		_IOW(BCM_IOCTL, 0x856, int)
#define IOCTL_BCM_BUFFER_DOWNLOAD_STOP		_IOW(BCM_IOCTL, 0x857, int)
#define IOCTL_BCM_REGISTER_WRITE_PRIVATE	_IOW(BCM_IOCTL, 0x826, char)
#define IOCTL_BCM_REGISTER_READ_PRIVATE		_IOW(BCM_IOCTL, 0x827, char)
#define IOCTL_BCM_SET_DEBUG			_IOW(BCM_IOCTL, 0x824, IOCTL_BUFFER)
#define IOCTL_BCM_EEPROM_REGISTER_WRITE		_IOW(BCM_IOCTL, 0x858, int)
#define IOCTL_BCM_EEPROM_REGISTER_READ		_IOR(BCM_IOCTL, 0x859, int)
#define IOCTL_BCM_WAKE_UP_DEVICE_FROM_IDLE	_IOR(BCM_IOCTL, 0x860, int)
#define IOCTL_BCM_SET_MAC_TRACING		_IOW(BCM_IOCTL, 0x82c, int)
#define IOCTL_BCM_GET_HOST_MIBS			_IOW(BCM_IOCTL, 0x853, int)
#define IOCTL_BCM_NVM_READ			_IOR(BCM_IOCTL, 0x861, int)
#define IOCTL_BCM_NVM_WRITE			_IOW(BCM_IOCTL, 0x862, int)
#define IOCTL_BCM_GET_NVM_SIZE			_IOR(BCM_IOCTL, 0x863, int)
#define IOCTL_BCM_CAL_INIT			_IOR(BCM_IOCTL, 0x864, int)
#define IOCTL_BCM_BULK_WRM			_IOW(BCM_IOCTL, 0x90B, int)
#define IOCTL_BCM_FLASH2X_SECTION_READ		_IOR(BCM_IOCTL, 0x865, int)
#define IOCTL_BCM_FLASH2X_SECTION_WRITE		_IOW(BCM_IOCTL, 0x866, int)
#define IOCTL_BCM_GET_FLASH2X_SECTION_BITMAP	_IOR(BCM_IOCTL, 0x867, int)
#define IOCTL_BCM_SET_ACTIVE_SECTION		_IOW(BCM_IOCTL, 0x868, int)
#define	IOCTL_BCM_IDENTIFY_ACTIVE_SECTION	_IO(BCM_IOCTL, 0x869)
#define IOCTL_BCM_COPY_SECTION			_IOW(BCM_IOCTL, 0x870, int)
#define	IOCTL_BCM_GET_FLASH_CS_INFO		_IOR(BCM_IOCTL, 0x871, int)
#define IOCTL_BCM_SELECT_DSD			_IOW(BCM_IOCTL, 0x872, int)
#define IOCTL_BCM_NVM_RAW_READ			_IOR(BCM_IOCTL, 0x875, int)
#define IOCTL_BCM_CNTRLMSG_MASK			_IOW(BCM_IOCTL, 0x874, int)
#define IOCTL_BCM_GET_DEVICE_DRIVER_INFO	_IOR(BCM_IOCTL, 0x877, int)
#define IOCTL_BCM_TIME_SINCE_NET_ENTRY		_IOR(BCM_IOCTL, 0x876, int)
#define BCM_LED_THREAD_STATE_CHANGE_REQ		_IOW(BCM_IOCTL, 0x878, int)
#define IOCTL_BCM_GPIO_MULTI_REQUEST		_IOW(BCM_IOCTL, 0x82D, IOCTL_BUFFER)
#define IOCTL_BCM_GPIO_MODE_REQUEST		_IOW(BCM_IOCTL, 0x82E, IOCTL_BUFFER)

typedef enum _BCM_INTERFACE_TYPE {
	BCM_MII,
	BCM_CARDBUS,
	BCM_USB,
	BCM_SDIO,
	BCM_PCMCIA
} BCM_INTERFACE_TYPE;

typedef struct _DEVICE_DRIVER_INFO {
	NVM_TYPE	u32NVMType;
	unsigned int		MaxRDMBufferSize;
	BCM_INTERFACE_TYPE	u32InterfaceType;
	unsigned int		u32DSDStartOffset;
	unsigned int		u32RxAlignmentCorrection;
	unsigned int		u32Reserved[10];
} DEVICE_DRIVER_INFO;

typedef  struct _NVM_READWRITE {
	void __user *pBuffer;
	uint32_t  uiOffset;
	uint32_t uiNumBytes;
	bool bVerify;
} NVM_READWRITE, *PNVM_READWRITE;

typedef struct bulkwrmbuffer {
	unsigned long Register;
	unsigned long SwapEndian;
	unsigned long Values[1];

} BULKWRM_BUFFER, *PBULKWRM_BUFFER;

typedef enum _FLASH2X_SECTION_VAL {
	NO_SECTION_VAL = 0, /* no section is chosen when absolute offset is given for RD/WR */
	ISO_IMAGE1,
	ISO_IMAGE2,
	DSD0,
	DSD1,
	DSD2,
	VSA0,
	VSA1,
	VSA2,
	SCSI,
	CONTROL_SECTION,
	ISO_IMAGE1_PART2,
	ISO_IMAGE1_PART3,
	ISO_IMAGE2_PART2,
	ISO_IMAGE2_PART3,
	TOTAL_SECTIONS
} FLASH2X_SECTION_VAL;

/*
 * Structure used for READ/WRITE Flash Map2.x
 */
typedef struct _FLASH2X_READWRITE {
	FLASH2X_SECTION_VAL Section; /* which section has to be read/written */
	u32 offset;	     /* Offset within Section. */
	u32 numOfBytes;	     /* NOB from the offset */
	u32 bVerify;
	void __user *pDataBuff;	     /* Buffer for reading/writing */
} FLASH2X_READWRITE, *PFLASH2X_READWRITE;

/*
 * This structure is used for coping one section to other.
 * there are two ways to copy one section to other.
 * it NOB =0, complete section will be copied on to other.
 * if NOB !=0, only NOB will be copied from the given offset.
 */

typedef struct _FLASH2X_COPY_SECTION {
	FLASH2X_SECTION_VAL SrcSection;
	FLASH2X_SECTION_VAL DstSection;
	u32 offset;
	u32 numOfBytes;
} FLASH2X_COPY_SECTION, *PFLASH2X_COPY_SECTION;

typedef enum _SECTION_TYPE {
	ISO = 0,
	VSA = 1,
	DSD = 2
} SECTION_TYPE, *PSECTION_TYPE;

/*
 * This section provide the complete bitmap of the Flash.
 * using this map lib/APP will isssue read/write command.
 * Fields are defined as :
 * Bit [0] = section is present  //1:present, 0: Not present
 * Bit [1] = section is valid  //1: valid, 0: not valid
 * Bit [2] = Section is R/W  //0: RW, 1: RO
 * Bit [3] = Section is Active or not 1 means Active, 0->inactive
 * Bit [7...3] = Reserved
 */

typedef struct _FLASH2X_BITMAP {
	unsigned char ISO_IMAGE1;
	unsigned char ISO_IMAGE2;
	unsigned char DSD0;
	unsigned char DSD1;
	unsigned char DSD2;
	unsigned char VSA0;
	unsigned char VSA1;
	unsigned char VSA2;
	unsigned char SCSI;
	unsigned char CONTROL_SECTION;
	/* Reserved for future use */
	unsigned char Reserved0;
	unsigned char Reserved1;
	unsigned char Reserved2;
} FLASH2X_BITMAP, *PFLASH2X_BITMAP;

typedef struct _ST_TIME_ELAPSED_ {
	unsigned long long ul64TimeElapsedSinceNetEntry;
	u32  uiReserved[4];
} ST_TIME_ELAPSED, *PST_TIME_ELAPSED;

enum {
	WIMAX_IDX = 0,  /* To access WiMAX chip GPIO's for GPIO_MULTI_INFO or GPIO_MULTI_MODE */
	HOST_IDX,	/* To access Host chip GPIO's for GPIO_MULTI_INFO or GPIO_MULTI_MODE */
	MAX_IDX
};

struct bcm_gpio_multi_info {
	unsigned int uiGPIOCommand; /* 1 for set and 0 for get */
	unsigned int uiGPIOMask;    /* set the correspondig bit to 1 to access GPIO */
	unsigned int uiGPIOValue;   /* 0 or 1; value to be set when command is 1. */
} __packed;

struct bcm_gpio_multi_mode {
	unsigned int uiGPIOMode;    /* 1 for OUT mode, 0 for IN mode */
	unsigned int uiGPIOMask;    /* GPIO mask to set mode */
} __packed;

#endif
Commit	Line	Data
f8942e07 SH	1	#ifndef _IOCTL_H_
	2	#define _IOCTL_H_
	3
25d41e2c	4	typedef struct rdmbuffer {
1bb052b7 KM	5	unsigned long Register;
1bb052b7 KM	6	unsigned long Length;
d53fbe34	7	} __packed RDM_BUFFER, *PRDM_BUFFER;
f8942e07	8
25d41e2c	9	typedef struct wrmbuffer {
1bb052b7 KM	10	unsigned long Register;
1bb052b7 KM	11	unsigned long Length;
0b512e49	12	unsigned char Data[4];
d53fbe34	13	} __packed WRM_BUFFER, *PWRM_BUFFER;
f8942e07	14
25d41e2c	15	typedef struct ioctlbuffer {
44a17eff	16	void __user *InputBuffer;
1bb052b7	17	unsigned long InputLength;
44a17eff	18	void __user *OutputBuffer;
1bb052b7	19	unsigned long OutputLength;
d53fbe34	20	} __packed IOCTL_BUFFER, *PIOCTL_BUFFER;
f8942e07	21
25d41e2c	22	typedef struct stGPIOInfo {
fb0b0765 KM	23	unsigned int uiGpioNumber; /* valid numbers 0-15 */
fb0b0765 KM	24	unsigned int uiGpioValue; /* 1 set ; 0 not set */
d53fbe34	25	} __packed GPIO_INFO, *PGPIO_INFO;
bce0f9f5	26
25d41e2c	27	typedef struct stUserThreadReq {
6117c1f3 KM	28	/* 0->Inactivate LED thread. */
6117c1f3 KM	29	/* 1->Activate the LED thread */
fb0b0765	30	unsigned int ThreadState;
d53fbe34	31	} __packed USER_THREAD_REQ, *PUSER_THREAD_REQ;
f8942e07	32
6117c1f3	33	#define LED_THREAD_ACTIVATION_REQ 1
bce0f9f5	34	#define BCM_IOCTL 'k'
bce0f9f5	35	#define IOCTL_SEND_CONTROL_MESSAGE _IOW(BCM_IOCTL, 0x801, int)
6117c1f3 KM	36	#define IOCTL_BCM_REGISTER_WRITE _IOW(BCM_IOCTL, 0x802, int)
	37	#define IOCTL_BCM_REGISTER_READ _IOR(BCM_IOCTL, 0x803, int)
	38	#define IOCTL_BCM_COMMON_MEMORY_WRITE _IOW(BCM_IOCTL, 0x804, int)
	39	#define IOCTL_BCM_COMMON_MEMORY_READ _IOR(BCM_IOCTL, 0x805, int)
	40	#define IOCTL_GET_CONTROL_MESSAGE _IOR(BCM_IOCTL, 0x806, int)
	41	#define IOCTL_BCM_FIRMWARE_DOWNLOAD _IOW(BCM_IOCTL, 0x807, int)
bce0f9f5	42	#define IOCTL_BCM_SET_SEND_VCID _IOW(BCM_IOCTL, 0x808, int)
bce0f9f5	43	#define IOCTL_BCM_SWITCH_TRANSFER_MODE _IOW(BCM_IOCTL, 0x809, int)
bce0f9f5	44	#define IOCTL_LINK_REQ _IOW(BCM_IOCTL, 0x80A, int)
bce0f9f5	45	#define IOCTL_RSSI_LEVEL_REQ _IOW(BCM_IOCTL, 0x80B, int)
bce0f9f5	46	#define IOCTL_IDLE_REQ _IOW(BCM_IOCTL, 0x80C, int)
bce0f9f5	47	#define IOCTL_SS_INFO_REQ _IOW(BCM_IOCTL, 0x80D, int)
f8942e07	48	#define IOCTL_GET_STATISTICS_POINTER _IOW(BCM_IOCTL, 0x80E, int)
bce0f9f5 KM	49	#define IOCTL_CM_REQUEST _IOW(BCM_IOCTL, 0x80F, int)
	50	#define IOCTL_INIT_PARAM_REQ _IOW(BCM_IOCTL, 0x810, int)
	51	#define IOCTL_MAC_ADDR_REQ _IOW(BCM_IOCTL, 0x811, int)
	52	#define IOCTL_MAC_ADDR_RESP _IOWR(BCM_IOCTL, 0x812, int)
	53	#define IOCTL_CLASSIFICATION_RULE _IOW(BCM_IOCTL, 0x813, char)
f8942e07	54	#define IOCTL_CLOSE_NOTIFICATION _IO(BCM_IOCTL, 0x814)
bce0f9f5 KM	55	#define IOCTL_LINK_UP _IO(BCM_IOCTL, 0x815)
	56	#define IOCTL_LINK_DOWN _IO(BCM_IOCTL, 0x816, IOCTL_BUFFER)
	57	#define IOCTL_CHIP_RESET _IO(BCM_IOCTL, 0x816)
f8942e07	58	#define IOCTL_CINR_LEVEL_REQ _IOW(BCM_IOCTL, 0x817, char)
bce0f9f5	59	#define IOCTL_WTM_CONTROL_REQ _IOW(BCM_IOCTL, 0x817, char)
f8942e07	60	#define IOCTL_BE_BUCKET_SIZE _IOW(BCM_IOCTL, 0x818, unsigned long)
f8942e07	61	#define IOCTL_RTPS_BUCKET_SIZE _IOW(BCM_IOCTL, 0x819, unsigned long)
bce0f9f5 KM	62	#define IOCTL_QOS_THRESHOLD _IOW(BCM_IOCTL, 0x820, unsigned long)
	63	#define IOCTL_DUMP_PACKET_INFO _IO(BCM_IOCTL, 0x821)
	64	#define IOCTL_GET_PACK_INFO _IOR(BCM_IOCTL, 0x823, int)
f8942e07	65	#define IOCTL_BCM_GET_DRIVER_VERSION _IOR(BCM_IOCTL, 0x829, int)
bce0f9f5 KM	66	#define IOCTL_BCM_GET_CURRENT_STATUS _IOW(BCM_IOCTL, 0x828, int)
	67	#define IOCTL_BCM_GPIO_SET_REQUEST _IOW(BCM_IOCTL, 0x82A, int)
	68	#define IOCTL_BCM_GPIO_STATUS_REQUEST _IOW(BCM_IOCTL, 0x82b, int)
	69	#define IOCTL_BCM_GET_DSX_INDICATION _IOR(BCM_IOCTL, 0x854, int)
	70	#define IOCTL_BCM_BUFFER_DOWNLOAD_START _IOW(BCM_IOCTL, 0x855, int)
	71	#define IOCTL_BCM_BUFFER_DOWNLOAD _IOW(BCM_IOCTL, 0x856, int)
	72	#define IOCTL_BCM_BUFFER_DOWNLOAD_STOP _IOW(BCM_IOCTL, 0x857, int)
	73	#define IOCTL_BCM_REGISTER_WRITE_PRIVATE _IOW(BCM_IOCTL, 0x826, char)
f8942e07	74	#define IOCTL_BCM_REGISTER_READ_PRIVATE _IOW(BCM_IOCTL, 0x827, char)
bce0f9f5 KM	75	#define IOCTL_BCM_SET_DEBUG _IOW(BCM_IOCTL, 0x824, IOCTL_BUFFER)
	76	#define IOCTL_BCM_EEPROM_REGISTER_WRITE _IOW(BCM_IOCTL, 0x858, int)
	77	#define IOCTL_BCM_EEPROM_REGISTER_READ _IOR(BCM_IOCTL, 0x859, int)
f8942e07	78	#define IOCTL_BCM_WAKE_UP_DEVICE_FROM_IDLE _IOR(BCM_IOCTL, 0x860, int)
bce0f9f5 KM	79	#define IOCTL_BCM_SET_MAC_TRACING _IOW(BCM_IOCTL, 0x82c, int)
	80	#define IOCTL_BCM_GET_HOST_MIBS _IOW(BCM_IOCTL, 0x853, int)
	81	#define IOCTL_BCM_NVM_READ _IOR(BCM_IOCTL, 0x861, int)
	82	#define IOCTL_BCM_NVM_WRITE _IOW(BCM_IOCTL, 0x862, int)
	83	#define IOCTL_BCM_GET_NVM_SIZE _IOR(BCM_IOCTL, 0x863, int)
	84	#define IOCTL_BCM_CAL_INIT _IOR(BCM_IOCTL, 0x864, int)
	85	#define IOCTL_BCM_BULK_WRM _IOW(BCM_IOCTL, 0x90B, int)
	86	#define IOCTL_BCM_FLASH2X_SECTION_READ _IOR(BCM_IOCTL, 0x865, int)
f8942e07	87	#define IOCTL_BCM_FLASH2X_SECTION_WRITE _IOW(BCM_IOCTL, 0x866, int)
bce0f9f5 KM	88	#define IOCTL_BCM_GET_FLASH2X_SECTION_BITMAP _IOR(BCM_IOCTL, 0x867, int)
	89	#define IOCTL_BCM_SET_ACTIVE_SECTION _IOW(BCM_IOCTL, 0x868, int)
	90	#define IOCTL_BCM_IDENTIFY_ACTIVE_SECTION _IO(BCM_IOCTL, 0x869)
	91	#define IOCTL_BCM_COPY_SECTION _IOW(BCM_IOCTL, 0x870, int)
	92	#define IOCTL_BCM_GET_FLASH_CS_INFO _IOR(BCM_IOCTL, 0x871, int)
	93	#define IOCTL_BCM_SELECT_DSD _IOW(BCM_IOCTL, 0x872, int)
	94	#define IOCTL_BCM_NVM_RAW_READ _IOR(BCM_IOCTL, 0x875, int)
	95	#define IOCTL_BCM_CNTRLMSG_MASK _IOW(BCM_IOCTL, 0x874, int)
	96	#define IOCTL_BCM_GET_DEVICE_DRIVER_INFO _IOR(BCM_IOCTL, 0x877, int)
	97	#define IOCTL_BCM_TIME_SINCE_NET_ENTRY _IOR(BCM_IOCTL, 0x876, int)
	98	#define BCM_LED_THREAD_STATE_CHANGE_REQ _IOW(BCM_IOCTL, 0x878, int)
f8942e07	99	#define IOCTL_BCM_GPIO_MULTI_REQUEST _IOW(BCM_IOCTL, 0x82D, IOCTL_BUFFER)
bce0f9f5	100	#define IOCTL_BCM_GPIO_MODE_REQUEST _IOW(BCM_IOCTL, 0x82E, IOCTL_BUFFER)
f8942e07	101
25d41e2c	102	typedef enum _BCM_INTERFACE_TYPE {
bce0f9f5 KM	103	BCM_MII,
	104	BCM_CARDBUS,
	105	BCM_USB,
	106	BCM_SDIO,
	107	BCM_PCMCIA
	108	} BCM_INTERFACE_TYPE;
f8942e07	109
25d41e2c	110	typedef struct _DEVICE_DRIVER_INFO {
bce0f9f5	111	NVM_TYPE u32NVMType;
fb0b0765	112	unsigned int MaxRDMBufferSize;
bce0f9f5	113	BCM_INTERFACE_TYPE u32InterfaceType;
fb0b0765 KM	114	unsigned int u32DSDStartOffset;
	115	unsigned int u32RxAlignmentCorrection;
	116	unsigned int u32Reserved[10];
f8942e07 SH	117	} DEVICE_DRIVER_INFO;
f8942e07 SH	118
25d41e2c	119	typedef struct _NVM_READWRITE {
44a17eff	120	void __user *pBuffer;
f8942e07	121	uint32_t uiOffset;
bce0f9f5	122	uint32_t uiNumBytes;
bce0f9f5	123	bool bVerify;
bce0f9f5	124	} NVM_READWRITE, *PNVM_READWRITE;
f8942e07	125
25d41e2c	126	typedef struct bulkwrmbuffer {
1bb052b7 KM	127	unsigned long Register;
	128	unsigned long SwapEndian;
	129	unsigned long Values[1];
f8942e07	130
bce0f9f5	131	} BULKWRM_BUFFER, *PBULKWRM_BUFFER;
f8942e07	132
25d41e2c	133	typedef enum _FLASH2X_SECTION_VAL {
6117c1f3	134	NO_SECTION_VAL = 0, /* no section is chosen when absolute offset is given for RD/WR */
f8942e07 SH	135	ISO_IMAGE1,
	136	ISO_IMAGE2,
	137	DSD0,
	138	DSD1,
	139	DSD2,
	140	VSA0,
	141	VSA1,
	142	VSA2,
	143	SCSI,
	144	CONTROL_SECTION,
	145	ISO_IMAGE1_PART2,
	146	ISO_IMAGE1_PART3,
	147	ISO_IMAGE2_PART2,
	148	ISO_IMAGE2_PART3,
	149	TOTAL_SECTIONS
bce0f9f5	150	} FLASH2X_SECTION_VAL;
f8942e07 SH	151
f8942e07 SH	152	/*
6117c1f3 KM	153	* Structure used for READ/WRITE Flash Map2.x
6117c1f3 KM	154	*/
25d41e2c	155	typedef struct _FLASH2X_READWRITE {
6117c1f3	156	FLASH2X_SECTION_VAL Section; /* which section has to be read/written */
2314894f KM	157	u32 offset; /* Offset within Section. */
	158	u32 numOfBytes; /* NOB from the offset */
	159	u32 bVerify;
6117c1f3	160	void __user pDataBuff; / Buffer for reading/writing */
bce0f9f5	161	} FLASH2X_READWRITE, *PFLASH2X_READWRITE;
6117c1f3	162
f8942e07	163	/*
6117c1f3 KM	164	* This structure is used for coping one section to other.
	165	* there are two ways to copy one section to other.
	166	* it NOB =0, complete section will be copied on to other.
	167	* if NOB !=0, only NOB will be copied from the given offset.
	168	*/
f8942e07	169
25d41e2c	170	typedef struct _FLASH2X_COPY_SECTION {
f8942e07	171	FLASH2X_SECTION_VAL SrcSection;
f8942e07	172	FLASH2X_SECTION_VAL DstSection;
2314894f KM	173	u32 offset;
2314894f KM	174	u32 numOfBytes;
f8942e07 SH	175	} FLASH2X_COPY_SECTION, *PFLASH2X_COPY_SECTION;
f8942e07 SH	176
25d41e2c	177	typedef enum _SECTION_TYPE {
f8942e07 SH	178	ISO = 0,
	179	VSA = 1,
	180	DSD = 2
	181	} SECTION_TYPE, *PSECTION_TYPE;
	182
	183	/*
6117c1f3 KM	184	* This section provide the complete bitmap of the Flash.
	185	* using this map lib/APP will isssue read/write command.
	186	* Fields are defined as :
	187	* Bit [0] = section is present //1:present, 0: Not present
	188	* Bit [1] = section is valid //1: valid, 0: not valid
	189	* Bit [2] = Section is R/W //0: RW, 1: RO
	190	* Bit [3] = Section is Active or not 1 means Active, 0->inactive
	191	* Bit [7...3] = Reserved
	192	*/
f8942e07	193
25d41e2c	194	typedef struct _FLASH2X_BITMAP {
0b512e49 KM	195	unsigned char ISO_IMAGE1;
	196	unsigned char ISO_IMAGE2;
	197	unsigned char DSD0;
	198	unsigned char DSD1;
	199	unsigned char DSD2;
	200	unsigned char VSA0;
	201	unsigned char VSA1;
	202	unsigned char VSA2;
	203	unsigned char SCSI;
	204	unsigned char CONTROL_SECTION;
6117c1f3	205	/* Reserved for future use */
0b512e49 KM	206	unsigned char Reserved0;
	207	unsigned char Reserved1;
	208	unsigned char Reserved2;
bce0f9f5	209	} FLASH2X_BITMAP, *PFLASH2X_BITMAP;
f8942e07	210
25d41e2c	211	typedef struct _ST_TIME_ELAPSED_ {
15b18b46	212	unsigned long long ul64TimeElapsedSinceNetEntry;
73f44785	213	u32 uiReserved[4];
bce0f9f5	214	} ST_TIME_ELAPSED, *PST_TIME_ELAPSED;
f8942e07 SH	215
f8942e07 SH	216	enum {
6117c1f3 KM	217	WIMAX_IDX = 0, /* To access WiMAX chip GPIO's for GPIO_MULTI_INFO or GPIO_MULTI_MODE */
6117c1f3 KM	218	HOST_IDX, /* To access Host chip GPIO's for GPIO_MULTI_INFO or GPIO_MULTI_MODE */
bce0f9f5	219	MAX_IDX
f8942e07	220	};
bce0f9f5	221
63df64a2	222	struct bcm_gpio_multi_info {
fb0b0765 KM	223	unsigned int uiGPIOCommand; /* 1 for set and 0 for get */
	224	unsigned int uiGPIOMask; /* set the correspondig bit to 1 to access GPIO */
	225	unsigned int uiGPIOValue; /* 0 or 1; value to be set when command is 1. */
63df64a2	226	} __packed;
f8942e07	227
9e91edb7	228	struct bcm_gpio_multi_mode {
fb0b0765 KM	229	unsigned int uiGPIOMode; /* 1 for OUT mode, 0 for IN mode */
fb0b0765 KM	230	unsigned int uiGPIOMask; /* GPIO mask to set mode */
9e91edb7	231	} __packed;
f8942e07 SH	232
f8942e07 SH	233	#endif