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staging: brcm80211: add fullmac driver
[deliverable/linux.git] / drivers / staging / brcm80211 / brcmfmac / dhd_sdio.c
CommitLineData
cf2b4488
HP		 1/*
2 * Copyright (c) 2010 Broadcom Corporation
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
11 * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
13 * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
14 * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17#include <typedefs.h>
18#include <osl.h>
19#include <bcmsdh.h>
20
21#ifdef BCMEMBEDIMAGE
22#include BCMEMBEDIMAGE
23#endif /* BCMEMBEDIMAGE */
24
25#include <bcmdefs.h>
26#include <bcmutils.h>
27#include <bcmendian.h>
28#include <bcmdevs.h>
29
30#include <siutils.h>
31#include <hndpmu.h>
32#include <hndsoc.h>
33#ifdef DHD_DEBUG
34#include <hndrte_armtrap.h>
35#include <hndrte_cons.h>
36#endif /* DHD_DEBUG */
37#include <sbchipc.h>
38#include <sbhnddma.h>
39
40#include <sdio.h>
41#include <sbsdio.h>
42#include <sbsdpcmdev.h>
43#include <bcmsdpcm.h>
44
45#include <proto/ethernet.h>
46#include <proto/802.1d.h>
47#include <proto/802.11.h>
48
49#include <dngl_stats.h>
50#include <dhd.h>
51#include <dhd_bus.h>
52#include <dhd_proto.h>
53#include <dhd_dbg.h>
54#include <dhdioctl.h>
55#include <sdiovar.h>
56#include <siutils_priv.h>
57
58#ifndef DHDSDIO_MEM_DUMP_FNAME
59#define DHDSDIO_MEM_DUMP_FNAME "mem_dump"
60#endif
61
62#define QLEN 256 /* bulk rx and tx queue lengths */
63#define FCHI (QLEN - 10)
64#define FCLOW (FCHI / 2)
65#define PRIOMASK 7
66
67#define TXRETRIES 2 /* # of retries for tx frames */
68
69#if defined(CONFIG_MACH_SANDGATE2G)
70#define DHD_RXBOUND 250 /* Default for max rx frames in
71 one scheduling */
72#else
73#define DHD_RXBOUND 50 /* Default for max rx frames in
74 one scheduling */
75#endif /* defined(CONFIG_MACH_SANDGATE2G) */
76
77#define DHD_TXBOUND 20 /* Default for max tx frames in
78 one scheduling */
79
80#define DHD_TXMINMAX 1 /* Max tx frames if rx still pending */
81
82#define MEMBLOCK 2048 /* Block size used for downloading
83 of dongle image */
84#define MAX_DATA_BUF (32 * 1024) /* Must be large enough to hold
85 biggest possible glom */
86
87/* Packet alignment for most efficient SDIO (can change based on platform) */
88#ifndef DHD_SDALIGN
89#define DHD_SDALIGN 32
90#endif
91#if !ISPOWEROF2(DHD_SDALIGN)
92#error DHD_SDALIGN is not a power of 2!
93#endif
94
95#ifndef DHD_FIRSTREAD
96#define DHD_FIRSTREAD 32
97#endif
98#if !ISPOWEROF2(DHD_FIRSTREAD)
99#error DHD_FIRSTREAD is not a power of 2!
100#endif
101
102/* Total length of frame header for dongle protocol */
103#define SDPCM_HDRLEN (SDPCM_FRAMETAG_LEN + SDPCM_SWHEADER_LEN)
104#ifdef SDTEST
105#define SDPCM_RESERVE (SDPCM_HDRLEN + SDPCM_TEST_HDRLEN + DHD_SDALIGN)
106#else
107#define SDPCM_RESERVE (SDPCM_HDRLEN + DHD_SDALIGN)
108#endif
109
110/* Space for header read, limit for data packets */
111#ifndef MAX_HDR_READ
112#define MAX_HDR_READ 32
113#endif
114#if !ISPOWEROF2(MAX_HDR_READ)
115#error MAX_HDR_READ is not a power of 2!
116#endif
117
118#define MAX_RX_DATASZ 2048
119
120/* Maximum milliseconds to wait for F2 to come up */
121#define DHD_WAIT_F2RDY 3000
122
123/* Bump up limit on waiting for HT to account for first startup;
124 * if the image is doing a CRC calculation before programming the PMU
125 * for HT availability, it could take a couple hundred ms more, so
126 * max out at a 1 second (1000000us).
127 */
128#if (PMU_MAX_TRANSITION_DLY <= 1000000)
129#undef PMU_MAX_TRANSITION_DLY
130#define PMU_MAX_TRANSITION_DLY 1000000
131#endif
132
133/* Value for ChipClockCSR during initial setup */
134#define DHD_INIT_CLKCTL1 (SBSDIO_FORCE_HW_CLKREQ_OFF | \
135 SBSDIO_ALP_AVAIL_REQ)
136#define DHD_INIT_CLKCTL2 (SBSDIO_FORCE_HW_CLKREQ_OFF | SBSDIO_FORCE_ALP)
137
138/* Flags for SDH calls */
139#define F2SYNC (SDIO_REQ_4BYTE | SDIO_REQ_FIXED)
140
141/* Packet free applicable unconditionally for sdio and sdspi. Conditional if
142 * bufpool was present for gspi bus.
143 */
144#define PKTFREE2() if ((bus->bus != SPI_BUS) || bus->usebufpool) \
145 PKTFREE(bus->dhd->osh, pkt, FALSE);
146DHD_SPINWAIT_SLEEP_INIT(sdioh_spinwait_sleep);
147extern int dhdcdc_set_ioctl(dhd_pub_t *dhd, int ifidx, uint cmd, void *buf,
148 uint len);
149
150#ifdef DHD_DEBUG
151/* Device console log buffer state */
152typedef struct dhd_console {
153 uint count; /* Poll interval msec counter */
154 uint log_addr; /* Log struct address (fixed) */
155 hndrte_log_t log; /* Log struct (host copy) */
156 uint bufsize; /* Size of log buffer */
157 uint8 *buf; /* Log buffer (host copy) */
158 uint last; /* Last buffer read index */
159} dhd_console_t;
160#endif /* DHD_DEBUG */
161
162/* Private data for SDIO bus interaction */
163typedef struct dhd_bus {
164 dhd_pub_t *dhd;
165
166 bcmsdh_info_t *sdh; /* Handle for BCMSDH calls */
167 si_t *sih; /* Handle for SI calls */
168 char *vars; /* Variables (from CIS and/or other) */
169 uint varsz; /* Size of variables buffer */
170 uint32 sbaddr; /* Current SB window pointer (-1, invalid) */
171
172 sdpcmd_regs_t *regs; /* Registers for SDIO core */
173 uint sdpcmrev; /* SDIO core revision */
174 uint armrev; /* CPU core revision */
175 uint ramrev; /* SOCRAM core revision */
176 uint32 ramsize; /* Size of RAM in SOCRAM (bytes) */
177 uint32 orig_ramsize; /* Size of RAM in SOCRAM (bytes) */
178
179 uint32 bus; /* gSPI or SDIO bus */
180 uint32 hostintmask; /* Copy of Host Interrupt Mask */
181 uint32 intstatus; /* Intstatus bits (events) pending */
182 bool dpc_sched; /* Indicates DPC schedule (intrpt rcvd) */
183 bool fcstate; /* State of dongle flow-control */
184
185 uint16 cl_devid; /* cached devid for dhdsdio_probe_attach() */
186 char *fw_path; /* module_param: path to firmware image */
187 char *nv_path; /* module_param: path to nvram vars file */
188 const char *nvram_params; /* user specified nvram params. */
189
190 uint blocksize; /* Block size of SDIO transfers */
191 uint roundup; /* Max roundup limit */
192
193 struct pktq txq; /* Queue length used for flow-control */
194 uint8 flowcontrol; /* per prio flow control bitmask */
195 uint8 tx_seq; /* Transmit sequence number (next) */
196 uint8 tx_max; /* Maximum transmit sequence allowed */
197
198 uint8 hdrbuf[MAX_HDR_READ + DHD_SDALIGN];
199 uint8 *rxhdr; /* Header of current rx frame (in hdrbuf) */
200 uint16 nextlen; /* Next Read Len from last header */
201 uint8 rx_seq; /* Receive sequence number (expected) */
202 bool rxskip; /* Skip receive (awaiting NAK ACK) */
203
204 void *glomd; /* Packet containing glomming descriptor */
205 void *glom; /* Packet chain for glommed superframe */
206 uint glomerr; /* Glom packet read errors */
207
208 uint8 *rxbuf; /* Buffer for receiving control packets */
209 uint rxblen; /* Allocated length of rxbuf */
210 uint8 *rxctl; /* Aligned pointer into rxbuf */
211 uint8 *databuf; /* Buffer for receiving big glom packet */
212 uint8 *dataptr; /* Aligned pointer into databuf */
213 uint rxlen; /* Length of valid data in buffer */
214
215 uint8 sdpcm_ver; /* Bus protocol reported by dongle */
216
217 bool intr; /* Use interrupts */
218 bool poll; /* Use polling */
219 bool ipend; /* Device interrupt is pending */
220 bool intdis; /* Interrupts disabled by isr */
221 uint intrcount; /* Count of device interrupt callbacks */
222 uint lastintrs; /* Count as of last watchdog timer */
223 uint spurious; /* Count of spurious interrupts */
224 uint pollrate; /* Ticks between device polls */
225 uint polltick; /* Tick counter */
226 uint pollcnt; /* Count of active polls */
227
228#ifdef DHD_DEBUG
229 dhd_console_t console; /* Console output polling support */
230 uint console_addr; /* Console address from shared struct */
231#endif /* DHD_DEBUG */
232
233 uint regfails; /* Count of R_REG/W_REG failures */
234
235 uint clkstate; /* State of sd and backplane clock(s) */
236 bool activity; /* Activity flag for clock down */
237 int32 idletime; /* Control for activity timeout */
238 int32 idlecount; /* Activity timeout counter */
239 int32 idleclock; /* How to set bus driver when idle */
240 int32 sd_divisor; /* Speed control to bus driver */
241 int32 sd_mode; /* Mode control to bus driver */
242 int32 sd_rxchain; /* If bcmsdh api accepts PKT chains */
243 bool use_rxchain; /* If dhd should use PKT chains */
244 bool sleeping; /* Is SDIO bus sleeping? */
245 bool rxflow_mode; /* Rx flow control mode */
246 bool rxflow; /* Is rx flow control on */
247 uint prev_rxlim_hit; /* Is prev rx limit exceeded
248 (per dpc schedule) */
249 bool alp_only; /* Don't use HT clock (ALP only) */
250/* Field to decide if rx of control frames happen in rxbuf or lb-pool */
251 bool usebufpool;
252
253#ifdef SDTEST
254 /* external loopback */
255 bool ext_loop;
256 uint8 loopid;
257
258 /* pktgen configuration */
259 uint pktgen_freq; /* Ticks between bursts */
260 uint pktgen_count; /* Packets to send each burst */
261 uint pktgen_print; /* Bursts between count displays */
262 uint pktgen_total; /* Stop after this many */
263 uint pktgen_minlen; /* Minimum packet data len */
264 uint pktgen_maxlen; /* Maximum packet data len */
265 uint pktgen_mode; /* Configured mode: tx, rx, or echo */
266 uint pktgen_stop; /* Number of tx failures causing stop */
267
268 /* active pktgen fields */
269 uint pktgen_tick; /* Tick counter for bursts */
270 uint pktgen_ptick; /* Burst counter for printing */
271 uint pktgen_sent; /* Number of test packets generated */
272 uint pktgen_rcvd; /* Number of test packets received */
273 uint pktgen_fail; /* Number of failed send attempts */
274 uint16 pktgen_len; /* Length of next packet to send */
275#endif /* SDTEST */
276
277 /* Some additional counters */
278 uint tx_sderrs; /* Count of tx attempts with sd errors */
279 uint fcqueued; /* Tx packets that got queued */
280 uint rxrtx; /* Count of rtx requests (NAK to dongle) */
281 uint rx_toolong; /* Receive frames too long to receive */
282 uint rxc_errors; /* SDIO errors when reading control frames */
283 uint rx_hdrfail; /* SDIO errors on header reads */
284 uint rx_badhdr; /* Bad received headers (roosync?) */
285 uint rx_badseq; /* Mismatched rx sequence number */
286 uint fc_rcvd; /* Number of flow-control events received */
287 uint fc_xoff; /* Number which turned on flow-control */
288 uint fc_xon; /* Number which turned off flow-control */
289 uint rxglomfail; /* Failed deglom attempts */
290 uint rxglomframes; /* Number of glom frames (superframes) */
291 uint rxglompkts; /* Number of packets from glom frames */
292 uint f2rxhdrs; /* Number of header reads */
293 uint f2rxdata; /* Number of frame data reads */
294 uint f2txdata; /* Number of f2 frame writes */
295 uint f1regdata; /* Number of f1 register accesses */
296
297 uint8 *ctrl_frame_buf;
298 uint32 ctrl_frame_len;
299 bool ctrl_frame_stat;
300} dhd_bus_t;
301
302/* clkstate */
303#define CLK_NONE 0
304#define CLK_SDONLY 1
305#define CLK_PENDING 2 /* Not used yet */
306#define CLK_AVAIL 3
307
308#define DHD_NOPMU(dhd) (FALSE)
309
310#ifdef DHD_DEBUG
311static int qcount[NUMPRIO];
312static int tx_packets[NUMPRIO];
313#endif /* DHD_DEBUG */
314
315/* Deferred transmit */
316const uint dhd_deferred_tx = 1;
317
318extern uint dhd_watchdog_ms;
319extern void dhd_os_wd_timer(void *bus, uint wdtick);
320
321/* Tx/Rx bounds */
322uint dhd_txbound;
323uint dhd_rxbound;
324uint dhd_txminmax;
325
326/* override the RAM size if possible */
327#define DONGLE_MIN_MEMSIZE (128 * 1024)
328int dhd_dongle_memsize;
329
330static bool dhd_doflow;
331static bool dhd_alignctl;
332
333static bool sd1idle;
334
335static bool retrydata;
336#define RETRYCHAN(chan) (((chan) == SDPCM_EVENT_CHANNEL) || retrydata)
337
338static const uint watermark = 8;
339static const uint firstread = DHD_FIRSTREAD;
340
341#define HDATLEN (firstread - (SDPCM_HDRLEN))
342
343/* Retry count for register access failures */
344static const uint retry_limit = 2;
345
346/* Force even SD lengths (some host controllers mess up on odd bytes) */
347static bool forcealign;
348
349#define ALIGNMENT 4
350
351#if defined(OOB_INTR_ONLY) && defined(HW_OOB)
352extern void bcmsdh_enable_hw_oob_intr(void *sdh, bool enable);
353#endif
354
355#if defined(OOB_INTR_ONLY) && defined(SDIO_ISR_THREAD)
356#error OOB_INTR_ONLY is NOT working with SDIO_ISR_THREAD
357#endif /* defined(OOB_INTR_ONLY) && defined(SDIO_ISR_THREAD) */
358#define PKTALIGN(osh, p, len, align) \
359 do { \
360 uint datalign; \
361 datalign = (uintptr)PKTDATA((p)); \
362 datalign = ROUNDUP(datalign, (align)) - datalign; \
363 ASSERT(datalign < (align)); \
364 ASSERT(PKTLEN((p)) >= ((len) + datalign)); \
365 if (datalign) \
366 PKTPULL((p), datalign); \
367 PKTSETLEN((p), (len)); \
368 } while (0)
369
370/* Limit on rounding up frames */
371static const uint max_roundup = 512;
372
373/* Try doing readahead */
374static bool dhd_readahead;
375
376/* To check if there's window offered */
377#define DATAOK(bus) \
378 (((uint8)(bus->tx_max - bus->tx_seq) != 0) && \
379 (((uint8)(bus->tx_max - bus->tx_seq) & 0x80) == 0))
380
381/* Macros to get register read/write status */
382/* NOTE: these assume a local dhdsdio_bus_t *bus! */
383#define R_SDREG(regvar, regaddr, retryvar) \
384do { \
385 retryvar = 0; \
386 do { \
387 regvar = R_REG(bus->dhd->osh, regaddr); \
388 } while (bcmsdh_regfail(bus->sdh) && (++retryvar <= retry_limit)); \
389 if (retryvar) { \
390 bus->regfails += (retryvar-1); \
391 if (retryvar > retry_limit) { \
392 DHD_ERROR(("%s: FAILED" #regvar "READ, LINE %d\n", \
393 __func__, __LINE__)); \
394 regvar = 0; \
395 } \
396 } \
397} while (0)
398
399#define W_SDREG(regval, regaddr, retryvar) \
400do { \
401 retryvar = 0; \
402 do { \
403 W_REG(bus->dhd->osh, regaddr, regval); \
404 } while (bcmsdh_regfail(bus->sdh) && (++retryvar <= retry_limit)); \
405 if (retryvar) { \
406 bus->regfails += (retryvar-1); \
407 if (retryvar > retry_limit) \
408 DHD_ERROR(("%s: FAILED REGISTER WRITE, LINE %d\n", \
409 __func__, __LINE__)); \
410 } \
411} while (0)
412
413#define DHD_BUS SDIO_BUS
414
415#define PKT_AVAILABLE() (intstatus & I_HMB_FRAME_IND)
416
417#define HOSTINTMASK (I_HMB_SW_MASK | I_CHIPACTIVE)
418
419#define GSPI_PR55150_BAILOUT
420
421#ifdef SDTEST
422static void dhdsdio_testrcv(dhd_bus_t *bus, void *pkt, uint seq);
423static void dhdsdio_sdtest_set(dhd_bus_t *bus, bool start);
424#endif
425
426#ifdef DHD_DEBUG
427static int dhdsdio_checkdied(dhd_bus_t *bus, uint8 *data, uint size);
428static int dhdsdio_mem_dump(dhd_bus_t *bus);
429#endif /* DHD_DEBUG */
430static int dhdsdio_download_state(dhd_bus_t *bus, bool enter);
431
432static void dhdsdio_release(dhd_bus_t *bus, osl_t *osh);
433static void dhdsdio_release_malloc(dhd_bus_t *bus, osl_t *osh);
434static void dhdsdio_disconnect(void *ptr);
435static bool dhdsdio_chipmatch(uint16 chipid);
436static bool dhdsdio_probe_attach(dhd_bus_t *bus, osl_t *osh, void *sdh,
437 void *regsva, uint16 devid);
438static bool dhdsdio_probe_malloc(dhd_bus_t *bus, osl_t *osh, void *sdh);
439static bool dhdsdio_probe_init(dhd_bus_t *bus, osl_t *osh, void *sdh);
440static void dhdsdio_release_dongle(dhd_bus_t *bus, osl_t * osh);
441
442static uint process_nvram_vars(char *varbuf, uint len);
443
444static void dhd_dongle_setmemsize(struct dhd_bus *bus, int mem_size);
445static int dhd_bcmsdh_recv_buf(dhd_bus_t *bus, uint32 addr, uint fn,
446 uint flags, uint8 *buf, uint nbytes, void *pkt,
447 bcmsdh_cmplt_fn_t complete, void *handle);
448static int dhd_bcmsdh_send_buf(dhd_bus_t *bus, uint32 addr, uint fn,
449 uint flags, uint8 *buf, uint nbytes, void *pkt,
450 bcmsdh_cmplt_fn_t complete, void *handle);
451
452static bool dhdsdio_download_firmware(struct dhd_bus *bus, osl_t *osh,
453 void *sdh);
454static int _dhdsdio_download_firmware(struct dhd_bus *bus);
455
456static int dhdsdio_download_code_file(struct dhd_bus *bus, char *image_path);
457static int dhdsdio_download_nvram(struct dhd_bus *bus);
458#ifdef BCMEMBEDIMAGE
459static int dhdsdio_download_code_array(struct dhd_bus *bus);
460#endif
461
462static void dhd_dongle_setmemsize(struct dhd_bus *bus, int mem_size)
463{
464 int32 min_size = DONGLE_MIN_MEMSIZE;
465 /* Restrict the memsize to user specified limit */
466 DHD_ERROR(("user: Restrict the dongle ram size to %d, min %d\n",
467 dhd_dongle_memsize, min_size));
468 if ((dhd_dongle_memsize > min_size) &&
469 (dhd_dongle_memsize < (int32) bus->orig_ramsize))
470 bus->ramsize = dhd_dongle_memsize;
471}
472
473static int dhdsdio_set_siaddr_window(dhd_bus_t *bus, uint32 address)
474{
475 int err = 0;
476 bcmsdh_cfg_write(bus->sdh, SDIO_FUNC_1, SBSDIO_FUNC1_SBADDRLOW,
477 (address >> 8) & SBSDIO_SBADDRLOW_MASK, &err);
478 if (!err)
479 bcmsdh_cfg_write(bus->sdh, SDIO_FUNC_1, SBSDIO_FUNC1_SBADDRMID,
480 (address >> 16) & SBSDIO_SBADDRMID_MASK, &err);
481 if (!err)
482 bcmsdh_cfg_write(bus->sdh, SDIO_FUNC_1, SBSDIO_FUNC1_SBADDRHIGH,
483 (address >> 24) & SBSDIO_SBADDRHIGH_MASK,
484 &err);
485 return err;
486}
487
488/* Turn backplane clock on or off */
489static int dhdsdio_htclk(dhd_bus_t *bus, bool on, bool pendok)
490{
491 int err;
492 uint8 clkctl, clkreq, devctl;
493 bcmsdh_info_t *sdh;
494
495 DHD_TRACE(("%s: Enter\n", __func__));
496
497#if defined(OOB_INTR_ONLY)
498 pendok = FALSE;
499#endif
500 clkctl = 0;
501 sdh = bus->sdh;
502
503 if (on) {
504 /* Request HT Avail */
505 clkreq =
506 bus->alp_only ? SBSDIO_ALP_AVAIL_REQ : SBSDIO_HT_AVAIL_REQ;
507
508 if ((bus->sih->chip == BCM4329_CHIP_ID)
509 && (bus->sih->chiprev == 0))
510 clkreq |= SBSDIO_FORCE_ALP;
511
512 bcmsdh_cfg_write(sdh, SDIO_FUNC_1, SBSDIO_FUNC1_CHIPCLKCSR,
513 clkreq, &err);
514 if (err) {
515 DHD_ERROR(("%s: HT Avail request error: %d\n",
516 __func__, err));
517 return BCME_ERROR;
518 }
519
520 if (pendok && ((bus->sih->buscoretype == PCMCIA_CORE_ID)
521 && (bus->sih->buscorerev == 9))) {
522 uint32 dummy, retries;
523 R_SDREG(dummy, &bus->regs->clockctlstatus, retries);
524 }
525
526 /* Check current status */
527 clkctl =
528 bcmsdh_cfg_read(sdh, SDIO_FUNC_1, SBSDIO_FUNC1_CHIPCLKCSR,
529 &err);
530 if (err) {
531 DHD_ERROR(("%s: HT Avail read error: %d\n",
532 __func__, err));
533 return BCME_ERROR;
534 }
535
536 /* Go to pending and await interrupt if appropriate */
537 if (!SBSDIO_CLKAV(clkctl, bus->alp_only) && pendok) {
538 /* Allow only clock-available interrupt */
539 devctl =
540 bcmsdh_cfg_read(sdh, SDIO_FUNC_1, SBSDIO_DEVICE_CTL,
541 &err);
542 if (err) {
543 DHD_ERROR(("%s: Devctl error setting CA: %d\n",
544 __func__, err));
545 return BCME_ERROR;
546 }
547
548 devctl |= SBSDIO_DEVCTL_CA_INT_ONLY;
549 bcmsdh_cfg_write(sdh, SDIO_FUNC_1, SBSDIO_DEVICE_CTL,
550 devctl, &err);
551 DHD_INFO(("CLKCTL: set PENDING\n"));
552 bus->clkstate = CLK_PENDING;
553
554 return BCME_OK;
555 } else if (bus->clkstate == CLK_PENDING) {
556 /* Cancel CA-only interrupt filter */
557 devctl =
558 bcmsdh_cfg_read(sdh, SDIO_FUNC_1, SBSDIO_DEVICE_CTL,
559 &err);
560 devctl &= ~SBSDIO_DEVCTL_CA_INT_ONLY;
561 bcmsdh_cfg_write(sdh, SDIO_FUNC_1, SBSDIO_DEVICE_CTL,
562 devctl, &err);
563 }
564
565 /* Otherwise, wait here (polling) for HT Avail */
566 if (!SBSDIO_CLKAV(clkctl, bus->alp_only)) {
567 SPINWAIT_SLEEP(sdioh_spinwait_sleep,
568 ((clkctl =
569 bcmsdh_cfg_read(sdh, SDIO_FUNC_1,
570 SBSDIO_FUNC1_CHIPCLKCSR,
571 &err)),
572 !SBSDIO_CLKAV(clkctl, bus->alp_only)),
573 PMU_MAX_TRANSITION_DLY);
574 }
575 if (err) {
576 DHD_ERROR(("%s: HT Avail request error: %d\n",
577 __func__, err));
578 return BCME_ERROR;
579 }
580 if (!SBSDIO_CLKAV(clkctl, bus->alp_only)) {
581 DHD_ERROR(("%s: HT Avail timeout (%d): clkctl 0x%02x\n",
582 __func__, PMU_MAX_TRANSITION_DLY, clkctl));
583 return BCME_ERROR;
584 }
585
586 /* Mark clock available */
587 bus->clkstate = CLK_AVAIL;
588 DHD_INFO(("CLKCTL: turned ON\n"));
589
590#if defined(DHD_DEBUG)
591 if (bus->alp_only == TRUE) {
592#if !defined(BCMLXSDMMC)
593 if (!SBSDIO_ALPONLY(clkctl)) {
594 DHD_ERROR(("%s: HT Clock, when ALP Only\n",
595 __func__));
596 }
597#endif /* !defined(BCMLXSDMMC) */
598 } else {
599 if (SBSDIO_ALPONLY(clkctl)) {
600 DHD_ERROR(("%s: HT Clock should be on.\n",
601 __func__));
602 }
603 }
604#endif /* defined (DHD_DEBUG) */
605
606 bus->activity = TRUE;
607 } else {
608 clkreq = 0;
609
610 if (bus->clkstate == CLK_PENDING) {
611 /* Cancel CA-only interrupt filter */
612 devctl =
613 bcmsdh_cfg_read(sdh, SDIO_FUNC_1, SBSDIO_DEVICE_CTL,
614 &err);
615 devctl &= ~SBSDIO_DEVCTL_CA_INT_ONLY;
616 bcmsdh_cfg_write(sdh, SDIO_FUNC_1, SBSDIO_DEVICE_CTL,
617 devctl, &err);
618 }
619
620 bus->clkstate = CLK_SDONLY;
621 bcmsdh_cfg_write(sdh, SDIO_FUNC_1, SBSDIO_FUNC1_CHIPCLKCSR,
622 clkreq, &err);
623 DHD_INFO(("CLKCTL: turned OFF\n"));
624 if (err) {
625 DHD_ERROR(("%s: Failed access turning clock off: %d\n",
626 __func__, err));
627 return BCME_ERROR;
628 }
629 }
630 return BCME_OK;
631}
632
633/* Change idle/active SD state */
634static int dhdsdio_sdclk(dhd_bus_t *bus, bool on)
635{
636 int err;
637 int32 iovalue;
638
639 DHD_TRACE(("%s: Enter\n", __func__));
640
641 if (on) {
642 if (bus->idleclock == DHD_IDLE_STOP) {
643 /* Turn on clock and restore mode */
644 iovalue = 1;
645 err = bcmsdh_iovar_op(bus->sdh, "sd_clock", NULL, 0,
646 &iovalue, sizeof(iovalue), TRUE);
647 if (err) {
648 DHD_ERROR(("%s: error enabling sd_clock: %d\n",
649 __func__, err));
650 return BCME_ERROR;
651 }
652
653 iovalue = bus->sd_mode;
654 err = bcmsdh_iovar_op(bus->sdh, "sd_mode", NULL, 0,
655 &iovalue, sizeof(iovalue), TRUE);
656 if (err) {
657 DHD_ERROR(("%s: error changing sd_mode: %d\n",
658 __func__, err));
659 return BCME_ERROR;
660 }
661 } else if (bus->idleclock != DHD_IDLE_ACTIVE) {
662 /* Restore clock speed */
663 iovalue = bus->sd_divisor;
664 err = bcmsdh_iovar_op(bus->sdh, "sd_divisor", NULL, 0,
665 &iovalue, sizeof(iovalue), TRUE);
666 if (err) {
667 DHD_ERROR(("%s: error restoring sd_divisor: %d\n",
668 __func__, err));
669 return BCME_ERROR;
670 }
671 }
672 bus->clkstate = CLK_SDONLY;
673 } else {
674 /* Stop or slow the SD clock itself */
675 if ((bus->sd_divisor == -1) || (bus->sd_mode == -1)) {
676 DHD_TRACE(("%s: can't idle clock, divisor %d mode %d\n",
677 __func__, bus->sd_divisor, bus->sd_mode));
678 return BCME_ERROR;
679 }
680 if (bus->idleclock == DHD_IDLE_STOP) {
681 if (sd1idle) {
682 /* Change to SD1 mode and turn off clock */
683 iovalue = 1;
684 err =
685 bcmsdh_iovar_op(bus->sdh, "sd_mode", NULL,
686 0, &iovalue,
687 sizeof(iovalue), TRUE);
688 if (err) {
689 DHD_ERROR(("%s: error changing sd_clock: %d\n",
690 __func__, err));
691 return BCME_ERROR;
692 }
693 }
694
695 iovalue = 0;
696 err = bcmsdh_iovar_op(bus->sdh, "sd_clock", NULL, 0,
697 &iovalue, sizeof(iovalue), TRUE);
698 if (err) {
699 DHD_ERROR(("%s: error disabling sd_clock: %d\n",
700 __func__, err));
701 return BCME_ERROR;
702 }
703 } else if (bus->idleclock != DHD_IDLE_ACTIVE) {
704 /* Set divisor to idle value */
705 iovalue = bus->idleclock;
706 err = bcmsdh_iovar_op(bus->sdh, "sd_divisor", NULL, 0,
707 &iovalue, sizeof(iovalue), TRUE);
708 if (err) {
709 DHD_ERROR(("%s: error changing sd_divisor: %d\n",
710 __func__, err));
711 return BCME_ERROR;
712 }
713 }
714 bus->clkstate = CLK_NONE;
715 }
716
717 return BCME_OK;
718}
719
720/* Transition SD and backplane clock readiness */
721static int dhdsdio_clkctl(dhd_bus_t *bus, uint target, bool pendok)
722{
723#ifdef DHD_DEBUG
724 uint oldstate = bus->clkstate;
725#endif /* DHD_DEBUG */
726
727 DHD_TRACE(("%s: Enter\n", __func__));
728
729 /* Early exit if we're already there */
730 if (bus->clkstate == target) {
731 if (target == CLK_AVAIL) {
732 dhd_os_wd_timer(bus->dhd, dhd_watchdog_ms);
733 bus->activity = TRUE;
734 }
735 return BCME_OK;
736 }
737
738 switch (target) {
739 case CLK_AVAIL:
740 /* Make sure SD clock is available */
741 if (bus->clkstate == CLK_NONE)
742 dhdsdio_sdclk(bus, TRUE);
743 /* Now request HT Avail on the backplane */
744 dhdsdio_htclk(bus, TRUE, pendok);
745 dhd_os_wd_timer(bus->dhd, dhd_watchdog_ms);
746 bus->activity = TRUE;
747 break;
748
749 case CLK_SDONLY:
750 /* Remove HT request, or bring up SD clock */
751 if (bus->clkstate == CLK_NONE)
752 dhdsdio_sdclk(bus, TRUE);
753 else if (bus->clkstate == CLK_AVAIL)
754 dhdsdio_htclk(bus, FALSE, FALSE);
755 else
756 DHD_ERROR(("dhdsdio_clkctl: request for %d -> %d\n",
757 bus->clkstate, target));
758 dhd_os_wd_timer(bus->dhd, dhd_watchdog_ms);
759 break;
760
761 case CLK_NONE:
762 /* Make sure to remove HT request */
763 if (bus->clkstate == CLK_AVAIL)
764 dhdsdio_htclk(bus, FALSE, FALSE);
765 /* Now remove the SD clock */
766 dhdsdio_sdclk(bus, FALSE);
767 dhd_os_wd_timer(bus->dhd, 0);
768 break;
769 }
770#ifdef DHD_DEBUG
771 DHD_INFO(("dhdsdio_clkctl: %d -> %d\n", oldstate, bus->clkstate));
772#endif /* DHD_DEBUG */
773
774 return BCME_OK;
775}
776
777int dhdsdio_bussleep(dhd_bus_t *bus, bool sleep)
778{
779 bcmsdh_info_t *sdh = bus->sdh;
780 sdpcmd_regs_t *regs = bus->regs;
781 uint retries = 0;
782
783 DHD_INFO(("dhdsdio_bussleep: request %s (currently %s)\n",
784 (sleep ? "SLEEP" : "WAKE"),
785 (bus->sleeping ? "SLEEP" : "WAKE")));
786
787 /* Done if we're already in the requested state */
788 if (sleep == bus->sleeping)
789 return BCME_OK;
790
791 /* Going to sleep: set the alarm and turn off the lights... */
792 if (sleep) {
793 /* Don't sleep if something is pending */
794 if (bus->dpc_sched || bus->rxskip || pktq_len(&bus->txq))
795 return BCME_BUSY;
796
797 /* Disable SDIO interrupts (no longer interested) */
798 bcmsdh_intr_disable(bus->sdh);
799
800 /* Make sure the controller has the bus up */
801 dhdsdio_clkctl(bus, CLK_AVAIL, FALSE);
802
803 /* Tell device to start using OOB wakeup */
804 W_SDREG(SMB_USE_OOB, &regs->tosbmailbox, retries);
805 if (retries > retry_limit)
806 DHD_ERROR(("CANNOT SIGNAL CHIP, WILL NOT WAKE UP!!\n"));
807
808 /* Turn off our contribution to the HT clock request */
809 dhdsdio_clkctl(bus, CLK_SDONLY, FALSE);
810
811 bcmsdh_cfg_write(sdh, SDIO_FUNC_1, SBSDIO_FUNC1_CHIPCLKCSR,
812 SBSDIO_FORCE_HW_CLKREQ_OFF, NULL);
813
814 /* Isolate the bus */
815 if (bus->sih->chip != BCM4329_CHIP_ID
816 && bus->sih->chip != BCM4319_CHIP_ID) {
817 bcmsdh_cfg_write(sdh, SDIO_FUNC_1, SBSDIO_DEVICE_CTL,
818 SBSDIO_DEVCTL_PADS_ISO, NULL);
819 }
820
821 /* Change state */
822 bus->sleeping = TRUE;
823
824 } else {
825 /* Waking up: bus power up is ok, set local state */
826
827 bcmsdh_cfg_write(sdh, SDIO_FUNC_1, SBSDIO_FUNC1_CHIPCLKCSR,
828 0, NULL);
829
830 /* Force pad isolation off if possible
831 (in case power never toggled) */
832 if ((bus->sih->buscoretype == PCMCIA_CORE_ID)
833 && (bus->sih->buscorerev >= 10))
834 bcmsdh_cfg_write(sdh, SDIO_FUNC_1, SBSDIO_DEVICE_CTL, 0,
835 NULL);
836
837 /* Make sure the controller has the bus up */
838 dhdsdio_clkctl(bus, CLK_AVAIL, FALSE);
839
840 /* Send misc interrupt to indicate OOB not needed */
841 W_SDREG(0, &regs->tosbmailboxdata, retries);
842 if (retries <= retry_limit)
843 W_SDREG(SMB_DEV_INT, &regs->tosbmailbox, retries);
844
845 if (retries > retry_limit)
846 DHD_ERROR(("CANNOT SIGNAL CHIP TO CLEAR OOB!!\n"));
847
848 /* Make sure we have SD bus access */
849 dhdsdio_clkctl(bus, CLK_SDONLY, FALSE);
850
851 /* Change state */
852 bus->sleeping = FALSE;
853
854 /* Enable interrupts again */
855 if (bus->intr && (bus->dhd->busstate == DHD_BUS_DATA)) {
856 bus->intdis = FALSE;
857 bcmsdh_intr_enable(bus->sdh);
858 }
859 }
860
861 return BCME_OK;
862}
863
864#if defined(OOB_INTR_ONLY)
865void dhd_enable_oob_intr(struct dhd_bus *bus, bool enable)
866{
867#if defined(HW_OOB)
868 bcmsdh_enable_hw_oob_intr(bus->sdh, enable);
869#else
870 sdpcmd_regs_t *regs = bus->regs;
871 uint retries = 0;
872
873 dhdsdio_clkctl(bus, CLK_AVAIL, FALSE);
874 if (enable == TRUE) {
875
876 /* Tell device to start using OOB wakeup */
877 W_SDREG(SMB_USE_OOB, &regs->tosbmailbox, retries);
878 if (retries > retry_limit)
879 DHD_ERROR(("CANNOT SIGNAL CHIP, WILL NOT WAKE UP!!\n"));
880
881 } else {
882 /* Send misc interrupt to indicate OOB not needed */
883 W_SDREG(0, &regs->tosbmailboxdata, retries);
884 if (retries <= retry_limit)
885 W_SDREG(SMB_DEV_INT, &regs->tosbmailbox, retries);
886 }
887
888 /* Turn off our contribution to the HT clock request */
889 dhdsdio_clkctl(bus, CLK_SDONLY, FALSE);
890#endif /* !defined(HW_OOB) */
891}
892#endif /* defined(OOB_INTR_ONLY) */
893
894#define BUS_WAKE(bus) \
895 do { \
896 if ((bus)->sleeping) \
897 dhdsdio_bussleep((bus), FALSE); \
898 } while (0);
899
900/* Writes a HW/SW header into the packet and sends it. */
901/* Assumes: (a) header space already there, (b) caller holds lock */
902static int dhdsdio_txpkt(dhd_bus_t *bus, void *pkt, uint chan, bool free_pkt)
903{
904 int ret;
905 osl_t *osh;
906 uint8 *frame;
907 uint16 len, pad = 0;
908 uint32 swheader;
909 uint retries = 0;
910 bcmsdh_info_t *sdh;
911 void *new;
912 int i;
913
914 DHD_TRACE(("%s: Enter\n", __func__));
915
916 sdh = bus->sdh;
917 osh = bus->dhd->osh;
918
919 if (bus->dhd->dongle_reset) {
920 ret = BCME_NOTREADY;
921 goto done;
922 }
923
924 frame = (uint8 *) PKTDATA(pkt);
925
926 /* Add alignment padding, allocate new packet if needed */
927 pad = ((uintptr) frame % DHD_SDALIGN);
928 if (pad) {
929 if (PKTHEADROOM(pkt) < pad) {
930 DHD_INFO(("%s: insufficient headroom %d for %d pad\n",
931 __func__, (int)PKTHEADROOM(pkt), pad));
932 bus->dhd->tx_realloc++;
933 new = PKTGET(osh, (PKTLEN(pkt) + DHD_SDALIGN), TRUE);
934 if (!new) {
935 DHD_ERROR(("%s: couldn't allocate new %d-byte "
936 "packet\n",
937 __func__, PKTLEN(pkt) + DHD_SDALIGN));
938 ret = BCME_NOMEM;
939 goto done;
940 }
941
942 PKTALIGN(osh, new, PKTLEN(pkt), DHD_SDALIGN);
943 bcopy(PKTDATA(pkt), PKTDATA(new), PKTLEN(pkt));
944 if (free_pkt)
945 PKTFREE(osh, pkt, TRUE);
946 /* free the pkt if canned one is not used */
947 free_pkt = TRUE;
948 pkt = new;
949 frame = (uint8 *) PKTDATA(pkt);
950 ASSERT(((uintptr) frame % DHD_SDALIGN) == 0);
951 pad = 0;
952 } else {
953 PKTPUSH(pkt, pad);
954 frame = (uint8 *) PKTDATA(pkt);
955
956 ASSERT((pad + SDPCM_HDRLEN) <= (int)PKTLEN(pkt));
957 bzero(frame, pad + SDPCM_HDRLEN);
958 }
959 }
960 ASSERT(pad < DHD_SDALIGN);
961
962 /* Hardware tag: 2 byte len followed by 2 byte ~len check (all LE) */
963 len = (uint16) PKTLEN(pkt);
964 *(uint16 *) frame = htol16(len);
965 *(((uint16 *) frame) + 1) = htol16(~len);
966
967 /* Software tag: channel, sequence number, data offset */
968 swheader =
969 ((chan << SDPCM_CHANNEL_SHIFT) & SDPCM_CHANNEL_MASK) | bus->tx_seq |
970 (((pad +
971 SDPCM_HDRLEN) << SDPCM_DOFFSET_SHIFT) & SDPCM_DOFFSET_MASK);
972 htol32_ua_store(swheader, frame + SDPCM_FRAMETAG_LEN);
973 htol32_ua_store(0, frame + SDPCM_FRAMETAG_LEN + sizeof(swheader));
974
975#ifdef DHD_DEBUG
976 tx_packets[PKTPRIO(pkt)]++;
977 if (DHD_BYTES_ON() &&
978 (((DHD_CTL_ON() && (chan == SDPCM_CONTROL_CHANNEL)) ||
979 (DHD_DATA_ON() && (chan != SDPCM_CONTROL_CHANNEL))))) {
980 prhex("Tx Frame", frame, len);
981 } else if (DHD_HDRS_ON()) {
982 prhex("TxHdr", frame, MIN(len, 16));
983 }
984#endif
985
986 /* Raise len to next SDIO block to eliminate tail command */
987 if (bus->roundup && bus->blocksize && (len > bus->blocksize)) {
988 uint16 pad = bus->blocksize - (len % bus->blocksize);
989 if ((pad <= bus->roundup) && (pad < bus->blocksize))
990#ifdef NOTUSED
991 if (pad <= PKTTAILROOM(pkt))
992#endif /* NOTUSED */
993 len += pad;
994 } else if (len % DHD_SDALIGN) {
995 len += DHD_SDALIGN - (len % DHD_SDALIGN);
996 }
997
998 /* Some controllers have trouble with odd bytes -- round to even */
999 if (forcealign && (len & (ALIGNMENT - 1))) {
1000#ifdef NOTUSED
1001 if (PKTTAILROOM(pkt))
1002#endif
1003 len = ROUNDUP(len, ALIGNMENT);
1004#ifdef NOTUSED
1005 else
1006 DHD_ERROR(("%s: sending unrounded %d-byte packet\n",
1007 __func__, len));
1008#endif
1009 }
1010
1011 do {
1012 ret =
1013 dhd_bcmsdh_send_buf(bus, bcmsdh_cur_sbwad(sdh), SDIO_FUNC_2,
1014 F2SYNC, frame, len, pkt, NULL, NULL);
1015 bus->f2txdata++;
1016 ASSERT(ret != BCME_PENDING);
1017
1018 if (ret < 0) {
1019 /* On failure, abort the command
1020 and terminate the frame */
1021 DHD_INFO(("%s: sdio error %d, abort command and "
1022 "terminate frame.\n", __func__, ret));
1023 bus->tx_sderrs++;
1024
1025 bcmsdh_abort(sdh, SDIO_FUNC_2);
1026 bcmsdh_cfg_write(sdh, SDIO_FUNC_1,
1027 SBSDIO_FUNC1_FRAMECTRL, SFC_WF_TERM,
1028 NULL);
1029 bus->f1regdata++;
1030
1031 for (i = 0; i < 3; i++) {
1032 uint8 hi, lo;
1033 hi = bcmsdh_cfg_read(sdh, SDIO_FUNC_1,
1034 SBSDIO_FUNC1_WFRAMEBCHI,
1035 NULL);
1036 lo = bcmsdh_cfg_read(sdh, SDIO_FUNC_1,
1037 SBSDIO_FUNC1_WFRAMEBCLO,
1038 NULL);
1039 bus->f1regdata += 2;
1040 if ((hi == 0) && (lo == 0))
1041 break;
1042 }
1043
1044 }
1045 if (ret == 0)
1046 bus->tx_seq = (bus->tx_seq + 1) % SDPCM_SEQUENCE_WRAP;
1047
1048 } while ((ret < 0) && retrydata && retries++ < TXRETRIES);
1049
1050done:
1051 /* restore pkt buffer pointer before calling tx complete routine */
1052 PKTPULL(pkt, SDPCM_HDRLEN + pad);
1053 dhd_os_sdunlock(bus->dhd);
1054 dhd_txcomplete(bus->dhd, pkt, ret != 0);
1055 dhd_os_sdlock(bus->dhd);
1056
1057 if (free_pkt)
1058 PKTFREE(osh, pkt, TRUE);
1059
1060 return ret;
1061}
1062
1063int dhd_bus_txdata(struct dhd_bus *bus, void *pkt)
1064{
1065 int ret = BCME_ERROR;
1066 osl_t *osh;
1067 uint datalen, prec;
1068
1069 DHD_TRACE(("%s: Enter\n", __func__));
1070
1071 osh = bus->dhd->osh;
1072 datalen = PKTLEN(pkt);
1073
1074#ifdef SDTEST
1075 /* Push the test header if doing loopback */
1076 if (bus->ext_loop) {
1077 uint8 *data;
1078 PKTPUSH(pkt, SDPCM_TEST_HDRLEN);
1079 data = PKTDATA(pkt);
1080 *data++ = SDPCM_TEST_ECHOREQ;
1081 *data++ = (uint8) bus->loopid++;
1082 *data++ = (datalen >> 0);
1083 *data++ = (datalen >> 8);
1084 datalen += SDPCM_TEST_HDRLEN;
1085 }
1086#endif /* SDTEST */
1087
1088 /* Add space for the header */
1089 PKTPUSH(pkt, SDPCM_HDRLEN);
1090 ASSERT(ISALIGNED((uintptr) PKTDATA(pkt), 2));
1091
1092 prec = PRIO2PREC((PKTPRIO(pkt) & PRIOMASK));
1093
1094 /* Check for existing queue, current flow-control,
1095 pending event, or pending clock */
1096 if (dhd_deferred_tx || bus->fcstate || pktq_len(&bus->txq)
1097 || bus->dpc_sched || (!DATAOK(bus))
1098 || (bus->flowcontrol & NBITVAL(prec))
1099 || (bus->clkstate != CLK_AVAIL)) {
1100 DHD_TRACE(("%s: deferring pktq len %d\n", __func__,
1101 pktq_len(&bus->txq)));
1102 bus->fcqueued++;
1103
1104 /* Priority based enq */
1105 dhd_os_sdlock_txq(bus->dhd);
1106 if (dhd_prec_enq(bus->dhd, &bus->txq, pkt, prec) == FALSE) {
1107 PKTPULL(pkt, SDPCM_HDRLEN);
1108 dhd_txcomplete(bus->dhd, pkt, FALSE);
1109 PKTFREE(osh, pkt, TRUE);
1110 DHD_ERROR(("%s: out of bus->txq !!!\n", __func__));
1111 ret = BCME_NORESOURCE;
1112 } else {
1113 ret = BCME_OK;
1114 }
1115 dhd_os_sdunlock_txq(bus->dhd);
1116
1117 if ((pktq_len(&bus->txq) >= FCHI) && dhd_doflow)
1118 dhd_txflowcontrol(bus->dhd, 0, ON);
1119
1120#ifdef DHD_DEBUG
1121 if (pktq_plen(&bus->txq, prec) > qcount[prec])
1122 qcount[prec] = pktq_plen(&bus->txq, prec);
1123#endif
1124 /* Schedule DPC if needed to send queued packet(s) */
1125 if (dhd_deferred_tx && !bus->dpc_sched) {
1126 bus->dpc_sched = TRUE;
1127 dhd_sched_dpc(bus->dhd);
1128 }
1129 } else {
1130 /* Lock: we're about to use shared data/code (and SDIO) */
1131 dhd_os_sdlock(bus->dhd);
1132
1133 /* Otherwise, send it now */
1134 BUS_WAKE(bus);
1135 /* Make sure back plane ht clk is on, no pending allowed */
1136 dhdsdio_clkctl(bus, CLK_AVAIL, TRUE);
1137
1138#ifndef SDTEST
1139 DHD_TRACE(("%s: calling txpkt\n", __func__));
1140 ret = dhdsdio_txpkt(bus, pkt, SDPCM_DATA_CHANNEL, TRUE);
1141#else
1142 ret = dhdsdio_txpkt(bus, pkt,
1143 (bus->ext_loop ? SDPCM_TEST_CHANNEL :
1144 SDPCM_DATA_CHANNEL), TRUE);
1145#endif
1146 if (ret)
1147 bus->dhd->tx_errors++;
1148 else
1149 bus->dhd->dstats.tx_bytes += datalen;
1150
1151 if ((bus->idletime == DHD_IDLE_IMMEDIATE) && !bus->dpc_sched) {
1152 bus->activity = FALSE;
1153 dhdsdio_clkctl(bus, CLK_NONE, TRUE);
1154 }
1155
1156 dhd_os_sdunlock(bus->dhd);
1157 }
1158
1159 return ret;
1160}
1161
1162static uint dhdsdio_sendfromq(dhd_bus_t *bus, uint maxframes)
1163{
1164 void *pkt;
1165 uint32 intstatus = 0;
1166 uint retries = 0;
1167 int ret = 0, prec_out;
1168 uint cnt = 0;
1169 uint datalen;
1170 uint8 tx_prec_map;
1171
1172 dhd_pub_t *dhd = bus->dhd;
1173 sdpcmd_regs_t *regs = bus->regs;
1174
1175 DHD_TRACE(("%s: Enter\n", __func__));
1176
1177 tx_prec_map = ~bus->flowcontrol;
1178
1179 /* Send frames until the limit or some other event */
1180 for (cnt = 0; (cnt < maxframes) && DATAOK(bus); cnt++) {
1181 dhd_os_sdlock_txq(bus->dhd);
1182 pkt = pktq_mdeq(&bus->txq, tx_prec_map, &prec_out);
1183 if (pkt == NULL) {
1184 dhd_os_sdunlock_txq(bus->dhd);
1185 break;
1186 }
1187 dhd_os_sdunlock_txq(bus->dhd);
1188 datalen = PKTLEN(pkt) - SDPCM_HDRLEN;
1189
1190#ifndef SDTEST
1191 ret = dhdsdio_txpkt(bus, pkt, SDPCM_DATA_CHANNEL, TRUE);
1192#else
1193 ret = dhdsdio_txpkt(bus, pkt,
1194 (bus->ext_loop ? SDPCM_TEST_CHANNEL :
1195 SDPCM_DATA_CHANNEL), TRUE);
1196#endif
1197 if (ret)
1198 bus->dhd->tx_errors++;
1199 else
1200 bus->dhd->dstats.tx_bytes += datalen;
1201
1202 /* In poll mode, need to check for other events */
1203 if (!bus->intr && cnt) {
1204 /* Check device status, signal pending interrupt */
1205 R_SDREG(intstatus, &regs->intstatus, retries);
1206 bus->f2txdata++;
1207 if (bcmsdh_regfail(bus->sdh))
1208 break;
1209 if (intstatus & bus->hostintmask)
1210 bus->ipend = TRUE;
1211 }
1212 }
1213
1214 /* Deflow-control stack if needed */
1215 if (dhd_doflow && dhd->up && (dhd->busstate == DHD_BUS_DATA) &&
1216 dhd->txoff && (pktq_len(&bus->txq) < FCLOW))
1217 dhd_txflowcontrol(dhd, 0, OFF);
1218
1219 return cnt;
1220}
1221
1222int dhd_bus_txctl(struct dhd_bus *bus, uchar *msg, uint msglen)
1223{
1224 uint8 *frame;
1225 uint16 len;
1226 uint32 swheader;
1227 uint retries = 0;
1228 bcmsdh_info_t *sdh = bus->sdh;
1229 uint8 doff = 0;
1230 int ret = -1;
1231 int i;
1232
1233 DHD_TRACE(("%s: Enter\n", __func__));
1234
1235 if (bus->dhd->dongle_reset)
1236 return -EIO;
1237
1238 /* Back the pointer to make a room for bus header */
1239 frame = msg - SDPCM_HDRLEN;
1240 len = (msglen += SDPCM_HDRLEN);
1241
1242 /* Add alignment padding (optional for ctl frames) */
1243 if (dhd_alignctl) {
1244 if ((doff = ((uintptr) frame % DHD_SDALIGN))) {
1245 frame -= doff;
1246 len += doff;
1247 msglen += doff;
1248 bzero(frame, doff + SDPCM_HDRLEN);
1249 }
1250 ASSERT(doff < DHD_SDALIGN);
1251 }
1252 doff += SDPCM_HDRLEN;
1253
1254 /* Round send length to next SDIO block */
1255 if (bus->roundup && bus->blocksize && (len > bus->blocksize)) {
1256 uint16 pad = bus->blocksize - (len % bus->blocksize);
1257 if ((pad <= bus->roundup) && (pad < bus->blocksize))
1258 len += pad;
1259 } else if (len % DHD_SDALIGN) {
1260 len += DHD_SDALIGN - (len % DHD_SDALIGN);
1261 }
1262
1263 /* Satisfy length-alignment requirements */
1264 if (forcealign && (len & (ALIGNMENT - 1)))
1265 len = ROUNDUP(len, ALIGNMENT);
1266
1267 ASSERT(ISALIGNED((uintptr) frame, 2));
1268
1269 /* Need to lock here to protect txseq and SDIO tx calls */
1270 dhd_os_sdlock(bus->dhd);
1271
1272 BUS_WAKE(bus);
1273
1274 /* Make sure backplane clock is on */
1275 dhdsdio_clkctl(bus, CLK_AVAIL, FALSE);
1276
1277 /* Hardware tag: 2 byte len followed by 2 byte ~len check (all LE) */
1278 *(uint16 *) frame = htol16((uint16) msglen);
1279 *(((uint16 *) frame) + 1) = htol16(~msglen);
1280
1281 /* Software tag: channel, sequence number, data offset */
1282 swheader =
1283 ((SDPCM_CONTROL_CHANNEL << SDPCM_CHANNEL_SHIFT) &
1284 SDPCM_CHANNEL_MASK)
1285 | bus->tx_seq | ((doff << SDPCM_DOFFSET_SHIFT) &
1286 SDPCM_DOFFSET_MASK);
1287 htol32_ua_store(swheader, frame + SDPCM_FRAMETAG_LEN);
1288 htol32_ua_store(0, frame + SDPCM_FRAMETAG_LEN + sizeof(swheader));
1289
1290 if (!DATAOK(bus)) {
1291 DHD_INFO(("%s: No bus credit bus->tx_max %d, bus->tx_seq %d\n",
1292 __func__, bus->tx_max, bus->tx_seq));
1293 bus->ctrl_frame_stat = TRUE;
1294 /* Send from dpc */
1295 bus->ctrl_frame_buf = frame;
1296 bus->ctrl_frame_len = len;
1297
1298 dhd_wait_for_event(bus->dhd, &bus->ctrl_frame_stat);
1299
1300 if (bus->ctrl_frame_stat == FALSE) {
1301 DHD_INFO(("%s: ctrl_frame_stat == FALSE\n", __func__));
1302 ret = 0;
1303 } else {
1304 DHD_INFO(("%s: ctrl_frame_stat == TRUE\n", __func__));
1305 ret = -1;
1306 }
1307 }
1308
1309 if (ret == -1) {
1310#ifdef DHD_DEBUG
1311 if (DHD_BYTES_ON() && DHD_CTL_ON())
1312 prhex("Tx Frame", frame, len);
1313 else if (DHD_HDRS_ON())
1314 prhex("TxHdr", frame, MIN(len, 16));
1315#endif
1316
1317 do {
1318 bus->ctrl_frame_stat = FALSE;
1319 ret =
1320 dhd_bcmsdh_send_buf(bus, bcmsdh_cur_sbwad(sdh),
1321 SDIO_FUNC_2, F2SYNC, frame, len,
1322 NULL, NULL, NULL);
1323
1324 ASSERT(ret != BCME_PENDING);
1325
1326 if (ret < 0) {
1327 /* On failure, abort the command and
1328 terminate the frame */
1329 DHD_INFO(("%s: sdio error %d, abort command and terminate frame.\n",
1330 __func__, ret));
1331 bus->tx_sderrs++;
1332
1333 bcmsdh_abort(sdh, SDIO_FUNC_2);
1334
1335 bcmsdh_cfg_write(sdh, SDIO_FUNC_1,
1336 SBSDIO_FUNC1_FRAMECTRL,
1337 SFC_WF_TERM, NULL);
1338 bus->f1regdata++;
1339
1340 for (i = 0; i < 3; i++) {
1341 uint8 hi, lo;
1342 hi = bcmsdh_cfg_read(sdh, SDIO_FUNC_1,
1343 SBSDIO_FUNC1_WFRAMEBCHI,
1344 NULL);
1345 lo = bcmsdh_cfg_read(sdh, SDIO_FUNC_1,
1346 SBSDIO_FUNC1_WFRAMEBCLO,
1347 NULL);
1348 bus->f1regdata += 2;
1349 if ((hi == 0) && (lo == 0))
1350 break;
1351 }
1352
1353 }
1354 if (ret == 0) {
1355 bus->tx_seq =
1356 (bus->tx_seq + 1) % SDPCM_SEQUENCE_WRAP;
1357 }
1358 } while ((ret < 0) && retries++ < TXRETRIES);
1359 }
1360
1361 if ((bus->idletime == DHD_IDLE_IMMEDIATE) && !bus->dpc_sched) {
1362 bus->activity = FALSE;
1363 dhdsdio_clkctl(bus, CLK_NONE, TRUE);
1364 }
1365
1366 dhd_os_sdunlock(bus->dhd);
1367
1368 if (ret)
1369 bus->dhd->tx_ctlerrs++;
1370 else
1371 bus->dhd->tx_ctlpkts++;
1372
1373 return ret ? -EIO : 0;
1374}
1375
1376int dhd_bus_rxctl(struct dhd_bus *bus, uchar *msg, uint msglen)
1377{
1378 int timeleft;
1379 uint rxlen = 0;
1380 bool pending;
1381
1382 DHD_TRACE(("%s: Enter\n", __func__));
1383
1384 if (bus->dhd->dongle_reset)
1385 return -EIO;
1386
1387 /* Wait until control frame is available */
1388 timeleft = dhd_os_ioctl_resp_wait(bus->dhd, &bus->rxlen, &pending);
1389
1390 dhd_os_sdlock(bus->dhd);
1391 rxlen = bus->rxlen;
1392 bcopy(bus->rxctl, msg, MIN(msglen, rxlen));
1393 bus->rxlen = 0;
1394 dhd_os_sdunlock(bus->dhd);
1395
1396 if (rxlen) {
1397 DHD_CTL(("%s: resumed on rxctl frame, got %d expected %d\n",
1398 __func__, rxlen, msglen));
1399 } else if (timeleft == 0) {
1400 DHD_ERROR(("%s: resumed on timeout\n", __func__));
1401#ifdef DHD_DEBUG
1402 dhd_os_sdlock(bus->dhd);
1403 dhdsdio_checkdied(bus, NULL, 0);
1404 dhd_os_sdunlock(bus->dhd);
1405#endif /* DHD_DEBUG */
1406 } else if (pending == TRUE) {
1407 DHD_CTL(("%s: cancelled\n", __func__));
1408 return -ERESTARTSYS;
1409 } else {
1410 DHD_CTL(("%s: resumed for unknown reason?\n", __func__));
1411#ifdef DHD_DEBUG
1412 dhd_os_sdlock(bus->dhd);
1413 dhdsdio_checkdied(bus, NULL, 0);
1414 dhd_os_sdunlock(bus->dhd);
1415#endif /* DHD_DEBUG */
1416 }
1417
1418 if (rxlen)
1419 bus->dhd->rx_ctlpkts++;
1420 else
1421 bus->dhd->rx_ctlerrs++;
1422
1423 return rxlen ? (int)rxlen:-ETIMEDOUT;
1424}
1425
1426/* IOVar table */
1427enum {
1428 IOV_INTR = 1,
1429 IOV_POLLRATE,
1430 IOV_SDREG,
1431 IOV_SBREG,
1432 IOV_SDCIS,
1433 IOV_MEMBYTES,
1434 IOV_MEMSIZE,
1435#ifdef DHD_DEBUG
1436 IOV_CHECKDIED,
1437#endif
1438 IOV_DOWNLOAD,
1439 IOV_FORCEEVEN,
1440 IOV_SDIOD_DRIVE,
1441 IOV_READAHEAD,
1442 IOV_SDRXCHAIN,
1443 IOV_ALIGNCTL,
1444 IOV_SDALIGN,
1445 IOV_DEVRESET,
1446 IOV_CPU,
1447#ifdef SDTEST
1448 IOV_PKTGEN,
1449 IOV_EXTLOOP,
1450#endif /* SDTEST */
1451 IOV_SPROM,
1452 IOV_TXBOUND,
1453 IOV_RXBOUND,
1454 IOV_TXMINMAX,
1455 IOV_IDLETIME,
1456 IOV_IDLECLOCK,
1457 IOV_SD1IDLE,
1458 IOV_SLEEP,
1459 IOV_VARS
1460};
1461
1462const bcm_iovar_t dhdsdio_iovars[] = {
1463 {"intr", IOV_INTR, 0, IOVT_BOOL, 0},
1464 {"sleep", IOV_SLEEP, 0, IOVT_BOOL, 0},
1465 {"pollrate", IOV_POLLRATE, 0, IOVT_UINT32, 0},
1466 {"idletime", IOV_IDLETIME, 0, IOVT_INT32, 0},
1467 {"idleclock", IOV_IDLECLOCK, 0, IOVT_INT32, 0},
1468 {"sd1idle", IOV_SD1IDLE, 0, IOVT_BOOL, 0},
1469 {"membytes", IOV_MEMBYTES, 0, IOVT_BUFFER, 2 * sizeof(int)},
1470 {"memsize", IOV_MEMSIZE, 0, IOVT_UINT32, 0},
1471 {"download", IOV_DOWNLOAD, 0, IOVT_BOOL, 0},
1472 {"vars", IOV_VARS, 0, IOVT_BUFFER, 0},
1473 {"sdiod_drive", IOV_SDIOD_DRIVE, 0, IOVT_UINT32, 0},
1474 {"readahead", IOV_READAHEAD, 0, IOVT_BOOL, 0},
1475 {"sdrxchain", IOV_SDRXCHAIN, 0, IOVT_BOOL, 0},
1476 {"alignctl", IOV_ALIGNCTL, 0, IOVT_BOOL, 0},
1477 {"sdalign", IOV_SDALIGN, 0, IOVT_BOOL, 0},
1478 {"devreset", IOV_DEVRESET, 0, IOVT_BOOL, 0},
1479#ifdef DHD_DEBUG
1480 {"sdreg", IOV_SDREG, 0, IOVT_BUFFER, sizeof(sdreg_t)}
1481 ,
1482 {"sbreg", IOV_SBREG, 0, IOVT_BUFFER, sizeof(sdreg_t)}
1483 ,
1484 {"sd_cis", IOV_SDCIS, 0, IOVT_BUFFER, DHD_IOCTL_MAXLEN}
1485 ,
1486 {"forcealign", IOV_FORCEEVEN, 0, IOVT_BOOL, 0}
1487 ,
1488 {"txbound", IOV_TXBOUND, 0, IOVT_UINT32, 0}
1489 ,
1490 {"rxbound", IOV_RXBOUND, 0, IOVT_UINT32, 0}
1491 ,
1492 {"txminmax", IOV_TXMINMAX, 0, IOVT_UINT32, 0}
1493 ,
1494 {"cpu", IOV_CPU, 0, IOVT_BOOL, 0}
1495 ,
1496#ifdef DHD_DEBUG
1497 {"checkdied", IOV_CHECKDIED, 0, IOVT_BUFFER, 0}
1498 ,
1499#endif /* DHD_DEBUG */
1500#endif /* DHD_DEBUG */
1501#ifdef SDTEST
1502 {"extloop", IOV_EXTLOOP, 0, IOVT_BOOL, 0}
1503 ,
1504 {"pktgen", IOV_PKTGEN, 0, IOVT_BUFFER, sizeof(dhd_pktgen_t)}
1505 ,
1506#endif /* SDTEST */
1507
1508 {NULL, 0, 0, 0, 0}
1509};
1510
1511static void
1512dhd_dump_pct(struct bcmstrbuf *strbuf, char *desc, uint num, uint div)
1513{
1514 uint q1, q2;
1515
1516 if (!div) {
1517 bcm_bprintf(strbuf, "%s N/A", desc);
1518 } else {
1519 q1 = num / div;
1520 q2 = (100 * (num - (q1 * div))) / div;
1521 bcm_bprintf(strbuf, "%s %d.%02d", desc, q1, q2);
1522 }
1523}
1524
1525void dhd_bus_dump(dhd_pub_t *dhdp, struct bcmstrbuf *strbuf)
1526{
1527 dhd_bus_t *bus = dhdp->bus;
1528
1529 bcm_bprintf(strbuf, "Bus SDIO structure:\n");
1530 bcm_bprintf(strbuf,
1531 "hostintmask 0x%08x intstatus 0x%08x sdpcm_ver %d\n",
1532 bus->hostintmask, bus->intstatus, bus->sdpcm_ver);
1533 bcm_bprintf(strbuf,
1534 "fcstate %d qlen %d tx_seq %d, max %d, rxskip %d rxlen %d rx_seq %d\n",
1535 bus->fcstate, pktq_len(&bus->txq), bus->tx_seq, bus->tx_max,
1536 bus->rxskip, bus->rxlen, bus->rx_seq);
1537 bcm_bprintf(strbuf, "intr %d intrcount %d lastintrs %d spurious %d\n",
1538 bus->intr, bus->intrcount, bus->lastintrs, bus->spurious);
1539 bcm_bprintf(strbuf, "pollrate %d pollcnt %d regfails %d\n",
1540 bus->pollrate, bus->pollcnt, bus->regfails);
1541
1542 bcm_bprintf(strbuf, "\nAdditional counters:\n");
1543 bcm_bprintf(strbuf,
1544 "tx_sderrs %d fcqueued %d rxrtx %d rx_toolong %d rxc_errors %d\n",
1545 bus->tx_sderrs, bus->fcqueued, bus->rxrtx, bus->rx_toolong,
1546 bus->rxc_errors);
1547 bcm_bprintf(strbuf, "rx_hdrfail %d badhdr %d badseq %d\n",
1548 bus->rx_hdrfail, bus->rx_badhdr, bus->rx_badseq);
1549 bcm_bprintf(strbuf, "fc_rcvd %d, fc_xoff %d, fc_xon %d\n", bus->fc_rcvd,
1550 bus->fc_xoff, bus->fc_xon);
1551 bcm_bprintf(strbuf, "rxglomfail %d, rxglomframes %d, rxglompkts %d\n",
1552 bus->rxglomfail, bus->rxglomframes, bus->rxglompkts);
1553 bcm_bprintf(strbuf, "f2rx (hdrs/data) %d (%d/%d), f2tx %d f1regs %d\n",
1554 (bus->f2rxhdrs + bus->f2rxdata), bus->f2rxhdrs,
1555 bus->f2rxdata, bus->f2txdata, bus->f1regdata);
1556 {
1557 dhd_dump_pct(strbuf, "\nRx: pkts/f2rd", bus->dhd->rx_packets,
1558 (bus->f2rxhdrs + bus->f2rxdata));
1559 dhd_dump_pct(strbuf, ", pkts/f1sd", bus->dhd->rx_packets,
1560 bus->f1regdata);
1561 dhd_dump_pct(strbuf, ", pkts/sd", bus->dhd->rx_packets,
1562 (bus->f2rxhdrs + bus->f2rxdata + bus->f1regdata));
1563 dhd_dump_pct(strbuf, ", pkts/int", bus->dhd->rx_packets,
1564 bus->intrcount);
1565 bcm_bprintf(strbuf, "\n");
1566
1567 dhd_dump_pct(strbuf, "Rx: glom pct", (100 * bus->rxglompkts),
1568 bus->dhd->rx_packets);
1569 dhd_dump_pct(strbuf, ", pkts/glom", bus->rxglompkts,
1570 bus->rxglomframes);
1571 bcm_bprintf(strbuf, "\n");
1572
1573 dhd_dump_pct(strbuf, "Tx: pkts/f2wr", bus->dhd->tx_packets,
1574 bus->f2txdata);
1575 dhd_dump_pct(strbuf, ", pkts/f1sd", bus->dhd->tx_packets,
1576 bus->f1regdata);
1577 dhd_dump_pct(strbuf, ", pkts/sd", bus->dhd->tx_packets,
1578 (bus->f2txdata + bus->f1regdata));
1579 dhd_dump_pct(strbuf, ", pkts/int", bus->dhd->tx_packets,
1580 bus->intrcount);
1581 bcm_bprintf(strbuf, "\n");
1582
1583 dhd_dump_pct(strbuf, "Total: pkts/f2rw",
1584 (bus->dhd->tx_packets + bus->dhd->rx_packets),
1585 (bus->f2txdata + bus->f2rxhdrs + bus->f2rxdata));
1586 dhd_dump_pct(strbuf, ", pkts/f1sd",
1587 (bus->dhd->tx_packets + bus->dhd->rx_packets),
1588 bus->f1regdata);
1589 dhd_dump_pct(strbuf, ", pkts/sd",
1590 (bus->dhd->tx_packets + bus->dhd->rx_packets),
1591 (bus->f2txdata + bus->f2rxhdrs + bus->f2rxdata +
1592 bus->f1regdata));
1593 dhd_dump_pct(strbuf, ", pkts/int",
1594 (bus->dhd->tx_packets + bus->dhd->rx_packets),
1595 bus->intrcount);
1596 bcm_bprintf(strbuf, "\n\n");
1597 }
1598
1599#ifdef SDTEST
1600 if (bus->pktgen_count) {
1601 bcm_bprintf(strbuf, "pktgen config and count:\n");
1602 bcm_bprintf(strbuf,
1603 "freq %d count %d print %d total %d min %d len %d\n",
1604 bus->pktgen_freq, bus->pktgen_count,
1605 bus->pktgen_print, bus->pktgen_total,
1606 bus->pktgen_minlen, bus->pktgen_maxlen);
1607 bcm_bprintf(strbuf, "send attempts %d rcvd %d fail %d\n",
1608 bus->pktgen_sent, bus->pktgen_rcvd,
1609 bus->pktgen_fail);
1610 }
1611#endif /* SDTEST */
1612#ifdef DHD_DEBUG
1613 bcm_bprintf(strbuf, "dpc_sched %d host interrupt%spending\n",
1614 bus->dpc_sched,
1615 (bcmsdh_intr_pending(bus->sdh) ? " " : " not "));
1616 bcm_bprintf(strbuf, "blocksize %d roundup %d\n", bus->blocksize,
1617 bus->roundup);
1618#endif /* DHD_DEBUG */
1619 bcm_bprintf(strbuf,
1620 "clkstate %d activity %d idletime %d idlecount %d sleeping %d\n",
1621 bus->clkstate, bus->activity, bus->idletime, bus->idlecount,
1622 bus->sleeping);
1623}
1624
1625void dhd_bus_clearcounts(dhd_pub_t *dhdp)
1626{
1627 dhd_bus_t *bus = (dhd_bus_t *) dhdp->bus;
1628
1629 bus->intrcount = bus->lastintrs = bus->spurious = bus->regfails = 0;
1630 bus->rxrtx = bus->rx_toolong = bus->rxc_errors = 0;
1631 bus->rx_hdrfail = bus->rx_badhdr = bus->rx_badseq = 0;
1632 bus->tx_sderrs = bus->fc_rcvd = bus->fc_xoff = bus->fc_xon = 0;
1633 bus->rxglomfail = bus->rxglomframes = bus->rxglompkts = 0;
1634 bus->f2rxhdrs = bus->f2rxdata = bus->f2txdata = bus->f1regdata = 0;
1635}
1636
1637#ifdef SDTEST
1638static int dhdsdio_pktgen_get(dhd_bus_t *bus, uint8 *arg)
1639{
1640 dhd_pktgen_t pktgen;
1641
1642 pktgen.version = DHD_PKTGEN_VERSION;
1643 pktgen.freq = bus->pktgen_freq;
1644 pktgen.count = bus->pktgen_count;
1645 pktgen.print = bus->pktgen_print;
1646 pktgen.total = bus->pktgen_total;
1647 pktgen.minlen = bus->pktgen_minlen;
1648 pktgen.maxlen = bus->pktgen_maxlen;
1649 pktgen.numsent = bus->pktgen_sent;
1650 pktgen.numrcvd = bus->pktgen_rcvd;
1651 pktgen.numfail = bus->pktgen_fail;
1652 pktgen.mode = bus->pktgen_mode;
1653 pktgen.stop = bus->pktgen_stop;
1654
1655 bcopy(&pktgen, arg, sizeof(pktgen));
1656
1657 return 0;
1658}
1659
1660static int dhdsdio_pktgen_set(dhd_bus_t *bus, uint8 *arg)
1661{
1662 dhd_pktgen_t pktgen;
1663 uint oldcnt, oldmode;
1664
1665 bcopy(arg, &pktgen, sizeof(pktgen));
1666 if (pktgen.version != DHD_PKTGEN_VERSION)
1667 return BCME_BADARG;
1668
1669 oldcnt = bus->pktgen_count;
1670 oldmode = bus->pktgen_mode;
1671
1672 bus->pktgen_freq = pktgen.freq;
1673 bus->pktgen_count = pktgen.count;
1674 bus->pktgen_print = pktgen.print;
1675 bus->pktgen_total = pktgen.total;
1676 bus->pktgen_minlen = pktgen.minlen;
1677 bus->pktgen_maxlen = pktgen.maxlen;
1678 bus->pktgen_mode = pktgen.mode;
1679 bus->pktgen_stop = pktgen.stop;
1680
1681 bus->pktgen_tick = bus->pktgen_ptick = 0;
1682 bus->pktgen_len = MAX(bus->pktgen_len, bus->pktgen_minlen);
1683 bus->pktgen_len = MIN(bus->pktgen_len, bus->pktgen_maxlen);
1684
1685 /* Clear counts for a new pktgen (mode change, or was stopped) */
1686 if (bus->pktgen_count && (!oldcnt || oldmode != bus->pktgen_mode))
1687 bus->pktgen_sent = bus->pktgen_rcvd = bus->pktgen_fail = 0;
1688
1689 return 0;
1690}
1691#endif /* SDTEST */
1692
1693static int
1694dhdsdio_membytes(dhd_bus_t *bus, bool write, uint32 address, uint8 *data,
1695 uint size)
1696{
1697 int bcmerror = 0;
1698 uint32 sdaddr;
1699 uint dsize;
1700
1701 /* Determine initial transfer parameters */
1702 sdaddr = address & SBSDIO_SB_OFT_ADDR_MASK;
1703 if ((sdaddr + size) & SBSDIO_SBWINDOW_MASK)
1704 dsize = (SBSDIO_SB_OFT_ADDR_LIMIT - sdaddr);
1705 else
1706 dsize = size;
1707
1708 /* Set the backplane window to include the start address */
1709 bcmerror = dhdsdio_set_siaddr_window(bus, address);
1710 if (bcmerror) {
1711 DHD_ERROR(("%s: window change failed\n", __func__));
1712 goto xfer_done;
1713 }
1714
1715 /* Do the transfer(s) */
1716 while (size) {
1717 DHD_INFO(("%s: %s %d bytes at offset 0x%08x in window 0x%08x\n",
1718 __func__, (write ? "write" : "read"), dsize,
1719 sdaddr, (address & SBSDIO_SBWINDOW_MASK)));
1720 bcmerror =
1721 bcmsdh_rwdata(bus->sdh, write, sdaddr, data, dsize);
1722 if (bcmerror) {
1723 DHD_ERROR(("%s: membytes transfer failed\n", __func__));
1724 break;
1725 }
1726
1727 /* Adjust for next transfer (if any) */
1728 size -= dsize;
1729 if (size) {
1730 data += dsize;
1731 address += dsize;
1732 bcmerror = dhdsdio_set_siaddr_window(bus, address);
1733 if (bcmerror) {
1734 DHD_ERROR(("%s: window change failed\n",
1735 __func__));
1736 break;
1737 }
1738 sdaddr = 0;
1739 dsize = MIN(SBSDIO_SB_OFT_ADDR_LIMIT, size);
1740 }
1741 }
1742
1743xfer_done:
1744 /* Return the window to backplane enumeration space for core access */
1745 if (dhdsdio_set_siaddr_window(bus, bcmsdh_cur_sbwad(bus->sdh))) {
1746 DHD_ERROR(("%s: FAILED to set window back to 0x%x\n",
1747 __func__, bcmsdh_cur_sbwad(bus->sdh)));
1748 }
1749
1750 return bcmerror;
1751}
1752
1753#ifdef DHD_DEBUG
1754static int dhdsdio_readshared(dhd_bus_t *bus, sdpcm_shared_t *sh)
1755{
1756 uint32 addr;
1757 int rv;
1758
1759 /* Read last word in memory to determine address of
1760 sdpcm_shared structure */
1761 if ((rv =
1762 dhdsdio_membytes(bus, FALSE, bus->ramsize - 4, (uint8 *)&addr,
1763 4)) < 0)
1764 return rv;
1765
1766 addr = ltoh32(addr);
1767
1768 DHD_INFO(("sdpcm_shared address 0x%08X\n", addr));
1769
1770 /*
1771 * Check if addr is valid.
1772 * NVRAM length at the end of memory should have been overwritten.
1773 */
1774 if (addr == 0 || ((~addr >> 16) & 0xffff) == (addr & 0xffff)) {
1775 DHD_ERROR(("%s: address (0x%08x) of sdpcm_shared invalid\n",
1776 __func__, addr));
1777 return BCME_ERROR;
1778 }
1779
1780 /* Read hndrte_shared structure */
1781 rv = dhdsdio_membytes(bus, FALSE, addr, (uint8 *) sh,
1782 sizeof(sdpcm_shared_t));
1783 if (rv < 0)
1784 return rv;
1785
1786 /* Endianness */
1787 sh->flags = ltoh32(sh->flags);
1788 sh->trap_addr = ltoh32(sh->trap_addr);
1789 sh->assert_exp_addr = ltoh32(sh->assert_exp_addr);
1790 sh->assert_file_addr = ltoh32(sh->assert_file_addr);
1791 sh->assert_line = ltoh32(sh->assert_line);
1792 sh->console_addr = ltoh32(sh->console_addr);
1793 sh->msgtrace_addr = ltoh32(sh->msgtrace_addr);
1794
1795 if ((sh->flags & SDPCM_SHARED_VERSION_MASK) != SDPCM_SHARED_VERSION) {
1796 DHD_ERROR(("%s: sdpcm_shared version %d in dhd "
1797 "is different than sdpcm_shared version %d in dongle\n",
1798 __func__, SDPCM_SHARED_VERSION,
1799 sh->flags & SDPCM_SHARED_VERSION_MASK));
1800 return BCME_ERROR;
1801 }
1802
1803 return BCME_OK;
1804}
1805
1806static int dhdsdio_checkdied(dhd_bus_t *bus, uint8 *data, uint size)
1807{
1808 int bcmerror = 0;
1809 uint msize = 512;
1810 char *mbuffer = NULL;
1811 uint maxstrlen = 256;
1812 char *str = NULL;
1813 trap_t tr;
1814 sdpcm_shared_t sdpcm_shared;
1815 struct bcmstrbuf strbuf;
1816
1817 DHD_TRACE(("%s: Enter\n", __func__));
1818
1819 if (data == NULL) {
1820 /*
1821 * Called after a rx ctrl timeout. "data" is NULL.
1822 * allocate memory to trace the trap or assert.
1823 */
1824 size = msize;
1825 mbuffer = data = MALLOC(bus->dhd->osh, msize);
1826 if (mbuffer == NULL) {
1827 DHD_ERROR(("%s: MALLOC(%d) failed\n", __func__,
1828 msize));
1829 bcmerror = BCME_NOMEM;
1830 goto done;
1831 }
1832 }
1833
1834 if ((str = MALLOC(bus->dhd->osh, maxstrlen)) == NULL) {
1835 DHD_ERROR(("%s: MALLOC(%d) failed\n", __func__, maxstrlen));
1836 bcmerror = BCME_NOMEM;
1837 goto done;
1838 }
1839
1840 if ((bcmerror = dhdsdio_readshared(bus, &sdpcm_shared)) < 0)
1841 goto done;
1842
1843 bcm_binit(&strbuf, data, size);
1844
1845 bcm_bprintf(&strbuf,
1846 "msgtrace address : 0x%08X\nconsole address : 0x%08X\n",
1847 sdpcm_shared.msgtrace_addr, sdpcm_shared.console_addr);
1848
1849 if ((sdpcm_shared.flags & SDPCM_SHARED_ASSERT_BUILT) == 0) {
1850 /* NOTE: Misspelled assert is intentional - DO NOT FIX.
1851 * (Avoids conflict with real asserts for programmatic
1852 * parsing of output.)
1853 */
1854 bcm_bprintf(&strbuf, "Assrt not built in dongle\n");
1855 }
1856
1857 if ((sdpcm_shared.flags & (SDPCM_SHARED_ASSERT | SDPCM_SHARED_TRAP)) ==
1858 0) {
1859 /* NOTE: Misspelled assert is intentional - DO NOT FIX.
1860 * (Avoids conflict with real asserts for programmatic
1861 * parsing of output.)
1862 */
1863 bcm_bprintf(&strbuf, "No trap%s in dongle",
1864 (sdpcm_shared.flags & SDPCM_SHARED_ASSERT_BUILT)
1865 ? "/assrt" : "");
1866 } else {
1867 if (sdpcm_shared.flags & SDPCM_SHARED_ASSERT) {
1868 /* Download assert */
1869 bcm_bprintf(&strbuf, "Dongle assert");
1870 if (sdpcm_shared.assert_exp_addr != 0) {
1871 str[0] = '\0';
1872 if ((bcmerror = dhdsdio_membytes(bus, FALSE,
1873 sdpcm_shared.assert_exp_addr,
1874 (uint8 *) str,
1875 maxstrlen)) < 0)
1876 goto done;
1877
1878 str[maxstrlen - 1] = '\0';
1879 bcm_bprintf(&strbuf, " expr \"%s\"", str);
1880 }
1881
1882 if (sdpcm_shared.assert_file_addr != 0) {
1883 str[0] = '\0';
1884 if ((bcmerror = dhdsdio_membytes(bus, FALSE,
1885 sdpcm_shared.assert_file_addr,
1886 (uint8 *) str,
1887 maxstrlen)) < 0)
1888 goto done;
1889
1890 str[maxstrlen - 1] = '\0';
1891 bcm_bprintf(&strbuf, " file \"%s\"", str);
1892 }
1893
1894 bcm_bprintf(&strbuf, " line %d ",
1895 sdpcm_shared.assert_line);
1896 }
1897
1898 if (sdpcm_shared.flags & SDPCM_SHARED_TRAP) {
1899 if ((bcmerror = dhdsdio_membytes(bus, FALSE,
1900 sdpcm_shared.trap_addr,
1901 (uint8 *)&tr,
1902 sizeof(trap_t))) < 0)
1903 goto done;
1904
1905 bcm_bprintf(&strbuf,
1906 "Dongle trap type 0x%x @ epc 0x%x, cpsr 0x%x, spsr 0x%x, sp 0x%x,"
1907 "lp 0x%x, rpc 0x%x Trap offset 0x%x, "
1908 "r0 0x%x, r1 0x%x, r2 0x%x, r3 0x%x, r4 0x%x, r5 0x%x, r6 0x%x, r7 0x%x\n",
1909 tr.type, tr.epc, tr.cpsr, tr.spsr, tr.r13,
1910 tr.r14, tr.pc, sdpcm_shared.trap_addr,
1911 tr.r0, tr.r1, tr.r2, tr.r3, tr.r4, tr.r5,
1912 tr.r6, tr.r7);
1913 }
1914 }
1915
1916 if (sdpcm_shared.flags & (SDPCM_SHARED_ASSERT | SDPCM_SHARED_TRAP))
1917 DHD_ERROR(("%s: %s\n", __func__, strbuf.origbuf));
1918
1919#ifdef DHD_DEBUG
1920 if (sdpcm_shared.flags & SDPCM_SHARED_TRAP) {
1921 /* Mem dump to a file on device */
1922 dhdsdio_mem_dump(bus);
1923 }
1924#endif /* DHD_DEBUG */
1925
1926done:
1927 if (mbuffer)
1928 MFREE(bus->dhd->osh, mbuffer, msize);
1929 if (str)
1930 MFREE(bus->dhd->osh, str, maxstrlen);
1931
1932 return bcmerror;
1933}
1934
1935static int dhdsdio_mem_dump(dhd_bus_t *bus)
1936{
1937 int ret = 0;
1938 int size; /* Full mem size */
1939 int start = 0; /* Start address */
1940 int read_size = 0; /* Read size of each iteration */
1941 uint8 *buf = NULL, *databuf = NULL;
1942
1943 /* Get full mem size */
1944 size = bus->ramsize;
1945 buf = MALLOC(bus->dhd->osh, size);
1946 if (!buf) {
1947 printf("%s: Out of memory (%d bytes)\n", __func__, size);
1948 return -1;
1949 }
1950
1951 /* Read mem content */
1952 printf("Dump dongle memory");
1953 databuf = buf;
1954 while (size) {
1955 read_size = MIN(MEMBLOCK, size);
1956 ret = dhdsdio_membytes(bus, FALSE, start, databuf, read_size);
1957 if (ret) {
1958 printf("%s: Error membytes %d\n", __func__, ret);
1959 if (buf)
1960 MFREE(bus->dhd->osh, buf, size);
1961 return -1;
1962 }
1963 printf(".");
1964
1965 /* Decrement size and increment start address */
1966 size -= read_size;
1967 start += read_size;
1968 databuf += read_size;
1969 }
1970 printf("Done\n");
1971
1972 /* free buf before return !!! */
1973 if (write_to_file(bus->dhd, buf, bus->ramsize)) {
1974 printf("%s: Error writing to files\n", __func__);
1975 return -1;
1976 }
1977
1978 /* buf free handled in write_to_file, not here */
1979 return 0;
1980}
1981
1982#define CONSOLE_LINE_MAX 192
1983
1984static int dhdsdio_readconsole(dhd_bus_t *bus)
1985{
1986 dhd_console_t *c = &bus->console;
1987 uint8 line[CONSOLE_LINE_MAX], ch;
1988 uint32 n, idx, addr;
1989 int rv;
1990
1991 /* Don't do anything until FWREADY updates console address */
1992 if (bus->console_addr == 0)
1993 return 0;
1994
1995 /* Read console log struct */
1996 addr = bus->console_addr + OFFSETOF(hndrte_cons_t, log);
1997 if ((rv =
1998 dhdsdio_membytes(bus, FALSE, addr, (uint8 *)&c->log,
1999 sizeof(c->log))) < 0)
2000 return rv;
2001
2002 /* Allocate console buffer (one time only) */
2003 if (c->buf == NULL) {
2004 c->bufsize = ltoh32(c->log.buf_size);
2005 if ((c->buf = MALLOC(bus->dhd->osh, c->bufsize)) == NULL)
2006 return BCME_NOMEM;
2007 }
2008
2009 idx = ltoh32(c->log.idx);
2010
2011 /* Protect against corrupt value */
2012 if (idx > c->bufsize)
2013 return BCME_ERROR;
2014
2015 /* Skip reading the console buffer if the index pointer
2016 has not moved */
2017 if (idx == c->last)
2018 return BCME_OK;
2019
2020 /* Read the console buffer */
2021 addr = ltoh32(c->log.buf);
2022 rv = dhdsdio_membytes(bus, FALSE, addr, c->buf, c->bufsize);
2023 if (rv < 0)
2024 return rv;
2025
2026 while (c->last != idx) {
2027 for (n = 0; n < CONSOLE_LINE_MAX - 2; n++) {
2028 if (c->last == idx) {
2029 /* This would output a partial line.
2030 * Instead, back up
2031 * the buffer pointer and output this
2032 * line next time around.
2033 */
2034 if (c->last >= n)
2035 c->last -= n;
2036 else
2037 c->last = c->bufsize - n;
2038 goto break2;
2039 }
2040 ch = c->buf[c->last];
2041 c->last = (c->last + 1) % c->bufsize;
2042 if (ch == '\n')
2043 break;
2044 line[n] = ch;
2045 }
2046
2047 if (n > 0) {
2048 if (line[n - 1] == '\r')
2049 n--;
2050 line[n] = 0;
2051 printf("CONSOLE: %s\n", line);
2052 }
2053 }
2054break2:
2055
2056 return BCME_OK;
2057}
2058#endif /* DHD_DEBUG */
2059
2060int dhdsdio_downloadvars(dhd_bus_t *bus, void *arg, int len)
2061{
2062 int bcmerror = BCME_OK;
2063
2064 DHD_TRACE(("%s: Enter\n", __func__));
2065
2066 /* Basic sanity checks */
2067 if (bus->dhd->up) {
2068 bcmerror = BCME_NOTDOWN;
2069 goto err;
2070 }
2071 if (!len) {
2072 bcmerror = BCME_BUFTOOSHORT;
2073 goto err;
2074 }
2075
2076 /* Free the old ones and replace with passed variables */
2077 if (bus->vars)
2078 MFREE(bus->dhd->osh, bus->vars, bus->varsz);
2079
2080 bus->vars = MALLOC(bus->dhd->osh, len);
2081 bus->varsz = bus->vars ? len : 0;
2082 if (bus->vars == NULL) {
2083 bcmerror = BCME_NOMEM;
2084 goto err;
2085 }
2086
2087 /* Copy the passed variables, which should include the
2088 terminating double-null */
2089 bcopy(arg, bus->vars, bus->varsz);
2090err:
2091 return bcmerror;
2092}
2093
2094static int
2095dhdsdio_doiovar(dhd_bus_t *bus, const bcm_iovar_t *vi, uint32 actionid,
2096 const char *name, void *params, int plen, void *arg, int len,
2097 int val_size)
2098{
2099 int bcmerror = 0;
2100 int32 int_val = 0;
2101 bool bool_val = 0;
2102
2103 DHD_TRACE(("%s: Enter, action %d name %s params %p plen %d arg %p "
2104 "len %d val_size %d\n",
2105 __func__, actionid, name, params, plen, arg, len, val_size));
2106
2107 bcmerror = bcm_iovar_lencheck(vi, arg, len, IOV_ISSET(actionid));
2108 if (bcmerror != 0)
2109 goto exit;
2110
2111 if (plen >= (int)sizeof(int_val))
2112 bcopy(params, &int_val, sizeof(int_val));
2113
2114 bool_val = (int_val != 0) ? TRUE : FALSE;
2115
2116 /* Some ioctls use the bus */
2117 dhd_os_sdlock(bus->dhd);
2118
2119 /* Check if dongle is in reset. If so, only allow DEVRESET iovars */
2120 if (bus->dhd->dongle_reset && !(actionid == IOV_SVAL(IOV_DEVRESET) ||
2121 actionid == IOV_GVAL(IOV_DEVRESET))) {
2122 bcmerror = BCME_NOTREADY;
2123 goto exit;
2124 }
2125
2126 /* Handle sleep stuff before any clock mucking */
2127 if (vi->varid == IOV_SLEEP) {
2128 if (IOV_ISSET(actionid)) {
2129 bcmerror = dhdsdio_bussleep(bus, bool_val);
2130 } else {
2131 int_val = (int32) bus->sleeping;
2132 bcopy(&int_val, arg, val_size);
2133 }
2134 goto exit;
2135 }
2136
2137 /* Request clock to allow SDIO accesses */
2138 if (!bus->dhd->dongle_reset) {
2139 BUS_WAKE(bus);
2140 dhdsdio_clkctl(bus, CLK_AVAIL, FALSE);
2141 }
2142
2143 switch (actionid) {
2144 case IOV_GVAL(IOV_INTR):
2145 int_val = (int32) bus->intr;
2146 bcopy(&int_val, arg, val_size);
2147 break;
2148
2149 case IOV_SVAL(IOV_INTR):
2150 bus->intr = bool_val;
2151 bus->intdis = FALSE;
2152 if (bus->dhd->up) {
2153 if (bus->intr) {
2154 DHD_INTR(("%s: enable SDIO device interrupts\n",
2155 __func__));
2156 bcmsdh_intr_enable(bus->sdh);
2157 } else {
2158 DHD_INTR(("%s: disable SDIO interrupts\n",
2159 __func__));
2160 bcmsdh_intr_disable(bus->sdh);
2161 }
2162 }
2163 break;
2164
2165 case IOV_GVAL(IOV_POLLRATE):
2166 int_val = (int32) bus->pollrate;
2167 bcopy(&int_val, arg, val_size);
2168 break;
2169
2170 case IOV_SVAL(IOV_POLLRATE):
2171 bus->pollrate = (uint) int_val;
2172 bus->poll = (bus->pollrate != 0);
2173 break;
2174
2175 case IOV_GVAL(IOV_IDLETIME):
2176 int_val = bus->idletime;
2177 bcopy(&int_val, arg, val_size);
2178 break;
2179
2180 case IOV_SVAL(IOV_IDLETIME):
2181 if ((int_val < 0) && (int_val != DHD_IDLE_IMMEDIATE))
2182 bcmerror = BCME_BADARG;
2183 else
2184 bus->idletime = int_val;
2185 break;
2186
2187 case IOV_GVAL(IOV_IDLECLOCK):
2188 int_val = (int32) bus->idleclock;
2189 bcopy(&int_val, arg, val_size);
2190 break;
2191
2192 case IOV_SVAL(IOV_IDLECLOCK):
2193 bus->idleclock = int_val;
2194 break;
2195
2196 case IOV_GVAL(IOV_SD1IDLE):
2197 int_val = (int32) sd1idle;
2198 bcopy(&int_val, arg, val_size);
2199 break;
2200
2201 case IOV_SVAL(IOV_SD1IDLE):
2202 sd1idle = bool_val;
2203 break;
2204
2205 case IOV_SVAL(IOV_MEMBYTES):
2206 case IOV_GVAL(IOV_MEMBYTES):
2207 {
2208 uint32 address;
2209 uint size, dsize;
2210 uint8 *data;
2211
2212 bool set = (actionid == IOV_SVAL(IOV_MEMBYTES));
2213
2214 ASSERT(plen >= 2 * sizeof(int));
2215
2216 address = (uint32) int_val;
2217 bcopy((char *)params + sizeof(int_val), &int_val,
2218 sizeof(int_val));
2219 size = (uint) int_val;
2220
2221 /* Do some validation */
2222 dsize = set ? plen - (2 * sizeof(int)) : len;
2223 if (dsize < size) {
2224 DHD_ERROR(("%s: error on %s membytes, addr "
2225 "0x%08x size %d dsize %d\n",
2226 __func__, (set ? "set" : "get"),
2227 address, size, dsize));
2228 bcmerror = BCME_BADARG;
2229 break;
2230 }
2231
2232 DHD_INFO(("%s: Request to %s %d bytes at address "
2233 "0x%08x\n",
2234 __func__, (set ? "write" : "read"), size, address));
2235
2236 /* If we know about SOCRAM, check for a fit */
2237 if ((bus->orig_ramsize) &&
2238 ((address > bus->orig_ramsize)
2239 || (address + size > bus->orig_ramsize))) {
2240 DHD_ERROR(("%s: ramsize 0x%08x doesn't have %d "
2241 "bytes at 0x%08x\n",
2242 __func__, bus->orig_ramsize, size, address));
2243 bcmerror = BCME_BADARG;
2244 break;
2245 }
2246
2247 /* Generate the actual data pointer */
2248 data =
2249 set ? (uint8 *) params +
2250 2 * sizeof(int) : (uint8 *) arg;
2251
2252 /* Call to do the transfer */
2253 bcmerror =
2254 dhdsdio_membytes(bus, set, address, data, size);
2255
2256 break;
2257 }
2258
2259 case IOV_GVAL(IOV_MEMSIZE):
2260 int_val = (int32) bus->ramsize;
2261 bcopy(&int_val, arg, val_size);
2262 break;
2263
2264 case IOV_GVAL(IOV_SDIOD_DRIVE):
2265 int_val = (int32) dhd_sdiod_drive_strength;
2266 bcopy(&int_val, arg, val_size);
2267 break;
2268
2269 case IOV_SVAL(IOV_SDIOD_DRIVE):
2270 dhd_sdiod_drive_strength = int_val;
2271 si_sdiod_drive_strength_init(bus->sih, bus->dhd->osh,
2272 dhd_sdiod_drive_strength);
2273 break;
2274
2275 case IOV_SVAL(IOV_DOWNLOAD):
2276 bcmerror = dhdsdio_download_state(bus, bool_val);
2277 break;
2278
2279 case IOV_SVAL(IOV_VARS):
2280 bcmerror = dhdsdio_downloadvars(bus, arg, len);
2281 break;
2282
2283 case IOV_GVAL(IOV_READAHEAD):
2284 int_val = (int32) dhd_readahead;
2285 bcopy(&int_val, arg, val_size);
2286 break;
2287
2288 case IOV_SVAL(IOV_READAHEAD):
2289 if (bool_val && !dhd_readahead)
2290 bus->nextlen = 0;
2291 dhd_readahead = bool_val;
2292 break;
2293
2294 case IOV_GVAL(IOV_SDRXCHAIN):
2295 int_val = (int32) bus->use_rxchain;
2296 bcopy(&int_val, arg, val_size);
2297 break;
2298
2299 case IOV_SVAL(IOV_SDRXCHAIN):
2300 if (bool_val && !bus->sd_rxchain)
2301 bcmerror = BCME_UNSUPPORTED;
2302 else
2303 bus->use_rxchain = bool_val;
2304 break;
2305 case IOV_GVAL(IOV_ALIGNCTL):
2306 int_val = (int32) dhd_alignctl;
2307 bcopy(&int_val, arg, val_size);
2308 break;
2309
2310 case IOV_SVAL(IOV_ALIGNCTL):
2311 dhd_alignctl = bool_val;
2312 break;
2313
2314 case IOV_GVAL(IOV_SDALIGN):
2315 int_val = DHD_SDALIGN;
2316 bcopy(&int_val, arg, val_size);
2317 break;
2318
2319#ifdef DHD_DEBUG
2320 case IOV_GVAL(IOV_VARS):
2321 if (bus->varsz < (uint) len)
2322 bcopy(bus->vars, arg, bus->varsz);
2323 else
2324 bcmerror = BCME_BUFTOOSHORT;
2325 break;
2326#endif /* DHD_DEBUG */
2327
2328#ifdef DHD_DEBUG
2329 case IOV_GVAL(IOV_SDREG):
2330 {
2331 sdreg_t *sd_ptr;
2332 uint32 addr, size;
2333
2334 sd_ptr = (sdreg_t *) params;
2335
2336 addr = (uintptr) bus->regs + sd_ptr->offset;
2337 size = sd_ptr->func;
2338 int_val = (int32) bcmsdh_reg_read(bus->sdh, addr, size);
2339 if (bcmsdh_regfail(bus->sdh))
2340 bcmerror = BCME_SDIO_ERROR;
2341 bcopy(&int_val, arg, sizeof(int32));
2342 break;
2343 }
2344
2345 case IOV_SVAL(IOV_SDREG):
2346 {
2347 sdreg_t *sd_ptr;
2348 uint32 addr, size;
2349
2350 sd_ptr = (sdreg_t *) params;
2351
2352 addr = (uintptr) bus->regs + sd_ptr->offset;
2353 size = sd_ptr->func;
2354 bcmsdh_reg_write(bus->sdh, addr, size, sd_ptr->value);
2355 if (bcmsdh_regfail(bus->sdh))
2356 bcmerror = BCME_SDIO_ERROR;
2357 break;
2358 }
2359
2360 /* Same as above, but offset is not backplane
2361 (not SDIO core) */
2362 case IOV_GVAL(IOV_SBREG):
2363 {
2364 sdreg_t sdreg;
2365 uint32 addr, size;
2366
2367 bcopy(params, &sdreg, sizeof(sdreg));
2368
2369 addr = SI_ENUM_BASE + sdreg.offset;
2370 size = sdreg.func;
2371 int_val = (int32) bcmsdh_reg_read(bus->sdh, addr, size);
2372 if (bcmsdh_regfail(bus->sdh))
2373 bcmerror = BCME_SDIO_ERROR;
2374 bcopy(&int_val, arg, sizeof(int32));
2375 break;
2376 }
2377
2378 case IOV_SVAL(IOV_SBREG):
2379 {
2380 sdreg_t sdreg;
2381 uint32 addr, size;
2382
2383 bcopy(params, &sdreg, sizeof(sdreg));
2384
2385 addr = SI_ENUM_BASE + sdreg.offset;
2386 size = sdreg.func;
2387 bcmsdh_reg_write(bus->sdh, addr, size, sdreg.value);
2388 if (bcmsdh_regfail(bus->sdh))
2389 bcmerror = BCME_SDIO_ERROR;
2390 break;
2391 }
2392
2393 case IOV_GVAL(IOV_SDCIS):
2394 {
2395 *(char *)arg = 0;
2396
2397 bcmstrcat(arg, "\nFunc 0\n");
2398 bcmsdh_cis_read(bus->sdh, 0x10,
2399 (uint8 *) arg + strlen(arg),
2400 SBSDIO_CIS_SIZE_LIMIT);
2401 bcmstrcat(arg, "\nFunc 1\n");
2402 bcmsdh_cis_read(bus->sdh, 0x11,
2403 (uint8 *) arg + strlen(arg),
2404 SBSDIO_CIS_SIZE_LIMIT);
2405 bcmstrcat(arg, "\nFunc 2\n");
2406 bcmsdh_cis_read(bus->sdh, 0x12,
2407 (uint8 *) arg + strlen(arg),
2408 SBSDIO_CIS_SIZE_LIMIT);
2409 break;
2410 }
2411
2412 case IOV_GVAL(IOV_FORCEEVEN):
2413 int_val = (int32) forcealign;
2414 bcopy(&int_val, arg, val_size);
2415 break;
2416
2417 case IOV_SVAL(IOV_FORCEEVEN):
2418 forcealign = bool_val;
2419 break;
2420
2421 case IOV_GVAL(IOV_TXBOUND):
2422 int_val = (int32) dhd_txbound;
2423 bcopy(&int_val, arg, val_size);
2424 break;
2425
2426 case IOV_SVAL(IOV_TXBOUND):
2427 dhd_txbound = (uint) int_val;
2428 break;
2429
2430 case IOV_GVAL(IOV_RXBOUND):
2431 int_val = (int32) dhd_rxbound;
2432 bcopy(&int_val, arg, val_size);
2433 break;
2434
2435 case IOV_SVAL(IOV_RXBOUND):
2436 dhd_rxbound = (uint) int_val;
2437 break;
2438
2439 case IOV_GVAL(IOV_TXMINMAX):
2440 int_val = (int32) dhd_txminmax;
2441 bcopy(&int_val, arg, val_size);
2442 break;
2443
2444 case IOV_SVAL(IOV_TXMINMAX):
2445 dhd_txminmax = (uint) int_val;
2446 break;
2447#endif /* DHD_DEBUG */
2448
2449#ifdef SDTEST
2450 case IOV_GVAL(IOV_EXTLOOP):
2451 int_val = (int32) bus->ext_loop;
2452 bcopy(&int_val, arg, val_size);
2453 break;
2454
2455 case IOV_SVAL(IOV_EXTLOOP):
2456 bus->ext_loop = bool_val;
2457 break;
2458
2459 case IOV_GVAL(IOV_PKTGEN):
2460 bcmerror = dhdsdio_pktgen_get(bus, arg);
2461 break;
2462
2463 case IOV_SVAL(IOV_PKTGEN):
2464 bcmerror = dhdsdio_pktgen_set(bus, arg);
2465 break;
2466#endif /* SDTEST */
2467
2468 case IOV_SVAL(IOV_DEVRESET):
2469 DHD_TRACE(("%s: Called set IOV_DEVRESET=%d dongle_reset=%d "
2470 "busstate=%d\n",
2471 __func__, bool_val, bus->dhd->dongle_reset,
2472 bus->dhd->busstate));
2473
2474 ASSERT(bus->dhd->osh);
2475 /* ASSERT(bus->cl_devid); */
2476
2477 dhd_bus_devreset(bus->dhd, (uint8) bool_val);
2478
2479 break;
2480
2481 case IOV_GVAL(IOV_DEVRESET):
2482 DHD_TRACE(("%s: Called get IOV_DEVRESET\n", __func__));
2483
2484 /* Get its status */
2485 int_val = (bool) bus->dhd->dongle_reset;
2486 bcopy(&int_val, arg, val_size);
2487
2488 break;
2489
2490 default:
2491 bcmerror = BCME_UNSUPPORTED;
2492 break;
2493 }
2494
2495exit:
2496 if ((bus->idletime == DHD_IDLE_IMMEDIATE) && !bus->dpc_sched) {
2497 bus->activity = FALSE;
2498 dhdsdio_clkctl(bus, CLK_NONE, TRUE);
2499 }
2500
2501 dhd_os_sdunlock(bus->dhd);
2502
2503 if (actionid == IOV_SVAL(IOV_DEVRESET) && bool_val == FALSE)
2504 dhd_preinit_ioctls((dhd_pub_t *) bus->dhd);
2505
2506 return bcmerror;
2507}
2508
2509static int dhdsdio_write_vars(dhd_bus_t *bus)
2510{
2511 int bcmerror = 0;
2512 uint32 varsize;
2513 uint32 varaddr;
2514 uint8 *vbuffer;
2515 uint32 varsizew;
2516#ifdef DHD_DEBUG
2517 char *nvram_ularray;
2518#endif /* DHD_DEBUG */
2519
2520 /* Even if there are no vars are to be written, we still
2521 need to set the ramsize. */
2522 varsize = bus->varsz ? ROUNDUP(bus->varsz, 4) : 0;
2523 varaddr = (bus->ramsize - 4) - varsize;
2524
2525 if (bus->vars) {
2526 vbuffer = (uint8 *) MALLOC(bus->dhd->osh, varsize);
2527 if (!vbuffer)
2528 return BCME_NOMEM;
2529
2530 bzero(vbuffer, varsize);
2531 bcopy(bus->vars, vbuffer, bus->varsz);
2532
2533 /* Write the vars list */
2534 bcmerror =
2535 dhdsdio_membytes(bus, TRUE, varaddr, vbuffer, varsize);
2536#ifdef DHD_DEBUG
2537 /* Verify NVRAM bytes */
2538 DHD_INFO(("Compare NVRAM dl & ul; varsize=%d\n", varsize));
2539 nvram_ularray = (char *)MALLOC(bus->dhd->osh, varsize);
2540 if (!nvram_ularray)
2541 return BCME_NOMEM;
2542
2543 /* Upload image to verify downloaded contents. */
2544 memset(nvram_ularray, 0xaa, varsize);
2545
2546 /* Read the vars list to temp buffer for comparison */
2547 bcmerror =
2548 dhdsdio_membytes(bus, FALSE, varaddr, nvram_ularray,
2549 varsize);
2550 if (bcmerror) {
2551 DHD_ERROR(("%s: error %d on reading %d nvram bytes at "
2552 "0x%08x\n", __func__, bcmerror, varsize, varaddr));
2553 }
2554 /* Compare the org NVRAM with the one read from RAM */
2555 if (memcmp(vbuffer, nvram_ularray, varsize)) {
2556 DHD_ERROR(("%s: Downloaded NVRAM image is corrupted.\n",
2557 __func__));
2558 } else
2559 DHD_ERROR(("%s: Download/Upload/Compare of NVRAM ok.\n",
2560 __func__));
2561
2562 MFREE(bus->dhd->osh, nvram_ularray, varsize);
2563#endif /* DHD_DEBUG */
2564
2565 MFREE(bus->dhd->osh, vbuffer, varsize);
2566 }
2567
2568 /* adjust to the user specified RAM */
2569 DHD_INFO(("Physical memory size: %d, usable memory size: %d\n",
2570 bus->orig_ramsize, bus->ramsize));
2571 DHD_INFO(("Vars are at %d, orig varsize is %d\n", varaddr, varsize));
2572 varsize = ((bus->orig_ramsize - 4) - varaddr);
2573
2574 /*
2575 * Determine the length token:
2576 * Varsize, converted to words, in lower 16-bits, checksum
2577 * in upper 16-bits.
2578 */
2579 if (bcmerror) {
2580 varsizew = 0;
2581 } else {
2582 varsizew = varsize / 4;
2583 varsizew = (~varsizew << 16) | (varsizew & 0x0000FFFF);
2584 varsizew = htol32(varsizew);
2585 }
2586
2587 DHD_INFO(("New varsize is %d, length token=0x%08x\n", varsize,
2588 varsizew));
2589
2590 /* Write the length token to the last word */
2591 bcmerror = dhdsdio_membytes(bus, TRUE, (bus->orig_ramsize - 4),
2592 (uint8 *)&varsizew, 4);
2593
2594 return bcmerror;
2595}
2596
2597static int dhdsdio_download_state(dhd_bus_t *bus, bool enter)
2598{
2599 uint retries;
2600 int bcmerror = 0;
2601
2602 /* To enter download state, disable ARM and reset SOCRAM.
2603 * To exit download state, simply reset ARM (default is RAM boot).
2604 */
2605 if (enter) {
2606
2607 bus->alp_only = TRUE;
2608
2609 if (!(si_setcore(bus->sih, ARM7S_CORE_ID, 0)) &&
2610 !(si_setcore(bus->sih, ARMCM3_CORE_ID, 0))) {
2611 DHD_ERROR(("%s: Failed to find ARM core!\n", __func__));
2612 bcmerror = BCME_ERROR;
2613 goto fail;
2614 }
2615
2616 si_core_disable(bus->sih, 0);
2617 if (bcmsdh_regfail(bus->sdh)) {
2618 bcmerror = BCME_SDIO_ERROR;
2619 goto fail;
2620 }
2621
2622 if (!(si_setcore(bus->sih, SOCRAM_CORE_ID, 0))) {
2623 DHD_ERROR(("%s: Failed to find SOCRAM core!\n",
2624 __func__));
2625 bcmerror = BCME_ERROR;
2626 goto fail;
2627 }
2628
2629 si_core_reset(bus->sih, 0, 0);
2630 if (bcmsdh_regfail(bus->sdh)) {
2631 DHD_ERROR(("%s: Failure trying reset SOCRAM core?\n",
2632 __func__));
2633 bcmerror = BCME_SDIO_ERROR;
2634 goto fail;
2635 }
2636
2637 /* Clear the top bit of memory */
2638 if (bus->ramsize) {
2639 uint32 zeros = 0;
2640 dhdsdio_membytes(bus, TRUE, bus->ramsize - 4,
2641 (uint8 *)&zeros, 4);
2642 }
2643 } else {
2644 if (!(si_setcore(bus->sih, SOCRAM_CORE_ID, 0))) {
2645 DHD_ERROR(("%s: Failed to find SOCRAM core!\n",
2646 __func__));
2647 bcmerror = BCME_ERROR;
2648 goto fail;
2649 }
2650
2651 if (!si_iscoreup(bus->sih)) {
2652 DHD_ERROR(("%s: SOCRAM core is down after reset?\n",
2653 __func__));
2654 bcmerror = BCME_ERROR;
2655 goto fail;
2656 }
2657
2658 bcmerror = dhdsdio_write_vars(bus);
2659 if (bcmerror) {
2660 DHD_ERROR(("%s: no vars written to RAM\n", __func__));
2661 bcmerror = 0;
2662 }
2663
2664 if (!si_setcore(bus->sih, PCMCIA_CORE_ID, 0) &&
2665 !si_setcore(bus->sih, SDIOD_CORE_ID, 0)) {
2666 DHD_ERROR(("%s: Can't change back to SDIO core?\n",
2667 __func__));
2668 bcmerror = BCME_ERROR;
2669 goto fail;
2670 }
2671 W_SDREG(0xFFFFFFFF, &bus->regs->intstatus, retries);
2672
2673 if (!(si_setcore(bus->sih, ARM7S_CORE_ID, 0)) &&
2674 !(si_setcore(bus->sih, ARMCM3_CORE_ID, 0))) {
2675 DHD_ERROR(("%s: Failed to find ARM core!\n", __func__));
2676 bcmerror = BCME_ERROR;
2677 goto fail;
2678 }
2679
2680 si_core_reset(bus->sih, 0, 0);
2681 if (bcmsdh_regfail(bus->sdh)) {
2682 DHD_ERROR(("%s: Failure trying to reset ARM core?\n",
2683 __func__));
2684 bcmerror = BCME_SDIO_ERROR;
2685 goto fail;
2686 }
2687
2688 /* Allow HT Clock now that the ARM is running. */
2689 bus->alp_only = FALSE;
2690
2691 bus->dhd->busstate = DHD_BUS_LOAD;
2692 }
2693
2694fail:
2695 /* Always return to SDIOD core */
2696 if (!si_setcore(bus->sih, PCMCIA_CORE_ID, 0))
2697 si_setcore(bus->sih, SDIOD_CORE_ID, 0);
2698
2699 return bcmerror;
2700}
2701
2702int
2703dhd_bus_iovar_op(dhd_pub_t *dhdp, const char *name,
2704 void *params, int plen, void *arg, int len, bool set)
2705{
2706 dhd_bus_t *bus = dhdp->bus;
2707 const bcm_iovar_t *vi = NULL;
2708 int bcmerror = 0;
2709 int val_size;
2710 uint32 actionid;
2711
2712 DHD_TRACE(("%s: Enter\n", __func__));
2713
2714 ASSERT(name);
2715 ASSERT(len >= 0);
2716
2717 /* Get MUST have return space */
2718 ASSERT(set || (arg && len));
2719
2720 /* Set does NOT take qualifiers */
2721 ASSERT(!set || (!params && !plen));
2722
2723 /* Look up var locally; if not found pass to host driver */
2724 vi = bcm_iovar_lookup(dhdsdio_iovars, name);
2725 if (vi == NULL) {
2726 dhd_os_sdlock(bus->dhd);
2727
2728 BUS_WAKE(bus);
2729
2730 /* Turn on clock in case SD command needs backplane */
2731 dhdsdio_clkctl(bus, CLK_AVAIL, FALSE);
2732
2733 bcmerror =
2734 bcmsdh_iovar_op(bus->sdh, name, params, plen, arg, len,
2735 set);
2736
2737 /* Check for bus configuration changes of interest */
2738
2739 /* If it was divisor change, read the new one */
2740 if (set && strcmp(name, "sd_divisor") == 0) {
2741 if (bcmsdh_iovar_op(bus->sdh, "sd_divisor", NULL, 0,
2742 &bus->sd_divisor, sizeof(int32),
2743 FALSE) != BCME_OK) {
2744 bus->sd_divisor = -1;
2745 DHD_ERROR(("%s: fail on %s get\n", __func__,
2746 name));
2747 } else {
2748 DHD_INFO(("%s: noted %s update, value now %d\n",
2749 __func__, name, bus->sd_divisor));
2750 }
2751 }
2752 /* If it was a mode change, read the new one */
2753 if (set && strcmp(name, "sd_mode") == 0) {
2754 if (bcmsdh_iovar_op(bus->sdh, "sd_mode", NULL, 0,
2755 &bus->sd_mode, sizeof(int32),
2756 FALSE) != BCME_OK) {
2757 bus->sd_mode = -1;
2758 DHD_ERROR(("%s: fail on %s get\n", __func__,
2759 name));
2760 } else {
2761 DHD_INFO(("%s: noted %s update, value now %d\n",
2762 __func__, name, bus->sd_mode));
2763 }
2764 }
2765 /* Similar check for blocksize change */
2766 if (set && strcmp(name, "sd_blocksize") == 0) {
2767 int32 fnum = 2;
2768 if (bcmsdh_iovar_op
2769 (bus->sdh, "sd_blocksize", &fnum, sizeof(int32),
2770 &bus->blocksize, sizeof(int32),
2771 FALSE) != BCME_OK) {
2772 bus->blocksize = 0;
2773 DHD_ERROR(("%s: fail on %s get\n", __func__,
2774 "sd_blocksize"));
2775 } else {
2776 DHD_INFO(("%s: noted %s update, value now %d\n",
2777 __func__, "sd_blocksize",
2778 bus->blocksize));
2779 }
2780 }
2781 bus->roundup = MIN(max_roundup, bus->blocksize);
2782
2783 if ((bus->idletime == DHD_IDLE_IMMEDIATE) && !bus->dpc_sched) {
2784 bus->activity = FALSE;
2785 dhdsdio_clkctl(bus, CLK_NONE, TRUE);
2786 }
2787
2788 dhd_os_sdunlock(bus->dhd);
2789 goto exit;
2790 }
2791
2792 DHD_CTL(("%s: %s %s, len %d plen %d\n", __func__,
2793 name, (set ? "set" : "get"), len, plen));
2794
2795 /* set up 'params' pointer in case this is a set command so that
2796 * the convenience int and bool code can be common to set and get
2797 */
2798 if (params == NULL) {
2799 params = arg;
2800 plen = len;
2801 }
2802
2803 if (vi->type == IOVT_VOID)
2804 val_size = 0;
2805 else if (vi->type == IOVT_BUFFER)
2806 val_size = len;
2807 else
2808 /* all other types are integer sized */
2809 val_size = sizeof(int);
2810
2811 actionid = set ? IOV_SVAL(vi->varid) : IOV_GVAL(vi->varid);
2812 bcmerror =
2813 dhdsdio_doiovar(bus, vi, actionid, name, params, plen, arg, len,
2814 val_size);
2815
2816exit:
2817 return bcmerror;
2818}
2819
2820void dhd_bus_stop(struct dhd_bus *bus, bool enforce_mutex)
2821{
2822 osl_t *osh = bus->dhd->osh;
2823 uint32 local_hostintmask;
2824 uint8 saveclk;
2825 uint retries;
2826 int err;
2827
2828 DHD_TRACE(("%s: Enter\n", __func__));
2829
2830 if (enforce_mutex)
2831 dhd_os_sdlock(bus->dhd);
2832
2833 BUS_WAKE(bus);
2834
2835 /* Enable clock for device interrupts */
2836 dhdsdio_clkctl(bus, CLK_AVAIL, FALSE);
2837
2838 /* Disable and clear interrupts at the chip level also */
2839 W_SDREG(0, &bus->regs->hostintmask, retries);
2840 local_hostintmask = bus->hostintmask;
2841 bus->hostintmask = 0;
2842
2843 /* Change our idea of bus state */
2844 bus->dhd->busstate = DHD_BUS_DOWN;
2845
2846 /* Force clocks on backplane to be sure F2 interrupt propagates */
2847 saveclk =
2848 bcmsdh_cfg_read(bus->sdh, SDIO_FUNC_1, SBSDIO_FUNC1_CHIPCLKCSR,
2849 &err);
2850 if (!err) {
2851 bcmsdh_cfg_write(bus->sdh, SDIO_FUNC_1, SBSDIO_FUNC1_CHIPCLKCSR,
2852 (saveclk | SBSDIO_FORCE_HT), &err);
2853 }
2854 if (err) {
2855 DHD_ERROR(("%s: Failed to force clock for F2: err %d\n",
2856 __func__, err));
2857 }
2858
2859 /* Turn off the bus (F2), free any pending packets */
2860 DHD_INTR(("%s: disable SDIO interrupts\n", __func__));
2861 bcmsdh_intr_disable(bus->sdh);
2862 bcmsdh_cfg_write(bus->sdh, SDIO_FUNC_0, SDIOD_CCCR_IOEN,
2863 SDIO_FUNC_ENABLE_1, NULL);
2864
2865 /* Clear any pending interrupts now that F2 is disabled */
2866 W_SDREG(local_hostintmask, &bus->regs->intstatus, retries);
2867
2868 /* Turn off the backplane clock (only) */
2869 dhdsdio_clkctl(bus, CLK_SDONLY, FALSE);
2870
2871 /* Clear the data packet queues */
2872 pktq_flush(osh, &bus->txq, TRUE);
2873
2874 /* Clear any held glomming stuff */
2875 if (bus->glomd)
2876 PKTFREE(osh, bus->glomd, FALSE);
2877
2878 if (bus->glom)
2879 PKTFREE(osh, bus->glom, FALSE);
2880
2881 bus->glom = bus->glomd = NULL;
2882
2883 /* Clear rx control and wake any waiters */
2884 bus->rxlen = 0;
2885 dhd_os_ioctl_resp_wake(bus->dhd);
2886
2887 /* Reset some F2 state stuff */
2888 bus->rxskip = FALSE;
2889 bus->tx_seq = bus->rx_seq = 0;
2890
2891 if (enforce_mutex)
2892 dhd_os_sdunlock(bus->dhd);
2893}
2894
2895int dhd_bus_init(dhd_pub_t *dhdp, bool enforce_mutex)
2896{
2897 dhd_bus_t *bus = dhdp->bus;
2898 dhd_timeout_t tmo;
2899 uint retries = 0;
2900 uint8 ready, enable;
2901 int err, ret = 0;
2902 uint8 saveclk;
2903
2904 DHD_TRACE(("%s: Enter\n", __func__));
2905
2906 ASSERT(bus->dhd);
2907 if (!bus->dhd)
2908 return 0;
2909
2910 if (enforce_mutex)
2911 dhd_os_sdlock(bus->dhd);
2912
2913 /* Make sure backplane clock is on, needed to generate F2 interrupt */
2914 dhdsdio_clkctl(bus, CLK_AVAIL, FALSE);
2915 if (bus->clkstate != CLK_AVAIL)
2916 goto exit;
2917
2918 /* Force clocks on backplane to be sure F2 interrupt propagates */
2919 saveclk =
2920 bcmsdh_cfg_read(bus->sdh, SDIO_FUNC_1, SBSDIO_FUNC1_CHIPCLKCSR,
2921 &err);
2922 if (!err) {
2923 bcmsdh_cfg_write(bus->sdh, SDIO_FUNC_1, SBSDIO_FUNC1_CHIPCLKCSR,
2924 (saveclk | SBSDIO_FORCE_HT), &err);
2925 }
2926 if (err) {
2927 DHD_ERROR(("%s: Failed to force clock for F2: err %d\n",
2928 __func__, err));
2929 goto exit;
2930 }
2931
2932 /* Enable function 2 (frame transfers) */
2933 W_SDREG((SDPCM_PROT_VERSION << SMB_DATA_VERSION_SHIFT),
2934 &bus->regs->tosbmailboxdata, retries);
2935 enable = (SDIO_FUNC_ENABLE_1 | SDIO_FUNC_ENABLE_2);
2936
2937 bcmsdh_cfg_write(bus->sdh, SDIO_FUNC_0, SDIOD_CCCR_IOEN, enable, NULL);
2938
2939 /* Give the dongle some time to do its thing and set IOR2 */
2940 dhd_timeout_start(&tmo, DHD_WAIT_F2RDY * 1000);
2941
2942 ready = 0;
2943 while (ready != enable && !dhd_timeout_expired(&tmo))
2944 ready =
2945 bcmsdh_cfg_read(bus->sdh, SDIO_FUNC_0, SDIOD_CCCR_IORDY,
2946 NULL);
2947
2948 DHD_INFO(("%s: enable 0x%02x, ready 0x%02x (waited %uus)\n",
2949 __func__, enable, ready, tmo.elapsed));
2950
2951 /* If F2 successfully enabled, set core and enable interrupts */
2952 if (ready == enable) {
2953 /* Make sure we're talking to the core. */
2954 bus->regs = si_setcore(bus->sih, PCMCIA_CORE_ID, 0);
2955 if (!(bus->regs))
2956 bus->regs = si_setcore(bus->sih, SDIOD_CORE_ID, 0);
2957
2958 /* Set up the interrupt mask and enable interrupts */
2959 bus->hostintmask = HOSTINTMASK;
2960 W_SDREG(bus->hostintmask, &bus->regs->hostintmask, retries);
2961
2962 bcmsdh_cfg_write(bus->sdh, SDIO_FUNC_1, SBSDIO_WATERMARK,
2963 (uint8) watermark, &err);
2964
2965 /* Set bus state according to enable result */
2966 dhdp->busstate = DHD_BUS_DATA;
2967
2968 /* bcmsdh_intr_unmask(bus->sdh); */
2969
2970 bus->intdis = FALSE;
2971 if (bus->intr) {
2972 DHD_INTR(("%s: enable SDIO device interrupts\n",
2973 __func__));
2974 bcmsdh_intr_enable(bus->sdh);
2975 } else {
2976 DHD_INTR(("%s: disable SDIO interrupts\n", __func__));
2977 bcmsdh_intr_disable(bus->sdh);
2978 }
2979
2980 }
2981
2982 else {
2983 /* Disable F2 again */
2984 enable = SDIO_FUNC_ENABLE_1;
2985 bcmsdh_cfg_write(bus->sdh, SDIO_FUNC_0, SDIOD_CCCR_IOEN, enable,
2986 NULL);
2987 }
2988
2989 /* Restore previous clock setting */
2990 bcmsdh_cfg_write(bus->sdh, SDIO_FUNC_1, SBSDIO_FUNC1_CHIPCLKCSR,
2991 saveclk, &err);
2992
2993 /* If we didn't come up, turn off backplane clock */
2994 if (dhdp->busstate != DHD_BUS_DATA)
2995 dhdsdio_clkctl(bus, CLK_NONE, FALSE);
2996
2997exit:
2998 if (enforce_mutex)
2999 dhd_os_sdunlock(bus->dhd);
3000
3001 return ret;
3002}
3003
3004static void dhdsdio_rxfail(dhd_bus_t *bus, bool abort, bool rtx)
3005{
3006 bcmsdh_info_t *sdh = bus->sdh;
3007 sdpcmd_regs_t *regs = bus->regs;
3008 uint retries = 0;
3009 uint16 lastrbc;
3010 uint8 hi, lo;
3011 int err;
3012
3013 DHD_ERROR(("%s: %sterminate frame%s\n", __func__,
3014 (abort ? "abort command, " : ""),
3015 (rtx ? ", send NAK" : "")));
3016
3017 if (abort)
3018 bcmsdh_abort(sdh, SDIO_FUNC_2);
3019
3020 bcmsdh_cfg_write(sdh, SDIO_FUNC_1, SBSDIO_FUNC1_FRAMECTRL, SFC_RF_TERM,
3021 &err);
3022 bus->f1regdata++;
3023
3024 /* Wait until the packet has been flushed (device/FIFO stable) */
3025 for (lastrbc = retries = 0xffff; retries > 0; retries--) {
3026 hi = bcmsdh_cfg_read(sdh, SDIO_FUNC_1, SBSDIO_FUNC1_RFRAMEBCHI,
3027 NULL);
3028 lo = bcmsdh_cfg_read(sdh, SDIO_FUNC_1, SBSDIO_FUNC1_RFRAMEBCLO,
3029 NULL);
3030 bus->f1regdata += 2;
3031
3032 if ((hi == 0) && (lo == 0))
3033 break;
3034
3035 if ((hi > (lastrbc >> 8)) && (lo > (lastrbc & 0x00ff))) {
3036 DHD_ERROR(("%s: count growing: last 0x%04x now "
3037 "0x%04x\n",
3038 __func__, lastrbc, ((hi << 8) + lo)));
3039 }
3040 lastrbc = (hi << 8) + lo;
3041 }
3042
3043 if (!retries) {
3044 DHD_ERROR(("%s: count never zeroed: last 0x%04x\n",
3045 __func__, lastrbc));
3046 } else {
3047 DHD_INFO(("%s: flush took %d iterations\n", __func__,
3048 (0xffff - retries)));
3049 }
3050
3051 if (rtx) {
3052 bus->rxrtx++;
3053 W_SDREG(SMB_NAK, &regs->tosbmailbox, retries);
3054 bus->f1regdata++;
3055 if (retries <= retry_limit)
3056 bus->rxskip = TRUE;
3057 }
3058
3059 /* Clear partial in any case */
3060 bus->nextlen = 0;
3061
3062 /* If we can't reach the device, signal failure */
3063 if (err || bcmsdh_regfail(sdh))
3064 bus->dhd->busstate = DHD_BUS_DOWN;
3065}
3066
3067static void
3068dhdsdio_read_control(dhd_bus_t *bus, uint8 *hdr, uint len, uint doff)
3069{
3070 bcmsdh_info_t *sdh = bus->sdh;
3071 uint rdlen, pad;
3072
3073 int sdret;
3074
3075 DHD_TRACE(("%s: Enter\n", __func__));
3076
3077 /* Control data already received in aligned rxctl */
3078 if ((bus->bus == SPI_BUS) && (!bus->usebufpool))
3079 goto gotpkt;
3080
3081 ASSERT(bus->rxbuf);
3082 /* Set rxctl for frame (w/optional alignment) */
3083 bus->rxctl = bus->rxbuf;
3084 if (dhd_alignctl) {
3085 bus->rxctl += firstread;
3086 pad = ((uintptr) bus->rxctl % DHD_SDALIGN);
3087 if (pad)
3088 bus->rxctl += (DHD_SDALIGN - pad);
3089 bus->rxctl -= firstread;
3090 }
3091 ASSERT(bus->rxctl >= bus->rxbuf);
3092
3093 /* Copy the already-read portion over */
3094 bcopy(hdr, bus->rxctl, firstread);
3095 if (len <= firstread)
3096 goto gotpkt;
3097
3098 /* Copy the full data pkt in gSPI case and process ioctl. */
3099 if (bus->bus == SPI_BUS) {
3100 bcopy(hdr, bus->rxctl, len);
3101 goto gotpkt;
3102 }
3103
3104 /* Raise rdlen to next SDIO block to avoid tail command */
3105 rdlen = len - firstread;
3106 if (bus->roundup && bus->blocksize && (rdlen > bus->blocksize)) {
3107 pad = bus->blocksize - (rdlen % bus->blocksize);
3108 if ((pad <= bus->roundup) && (pad < bus->blocksize) &&
3109 ((len + pad) < bus->dhd->maxctl))
3110 rdlen += pad;
3111 } else if (rdlen % DHD_SDALIGN) {
3112 rdlen += DHD_SDALIGN - (rdlen % DHD_SDALIGN);
3113 }
3114
3115 /* Satisfy length-alignment requirements */
3116 if (forcealign && (rdlen & (ALIGNMENT - 1)))
3117 rdlen = ROUNDUP(rdlen, ALIGNMENT);
3118
3119 /* Drop if the read is too big or it exceeds our maximum */
3120 if ((rdlen + firstread) > bus->dhd->maxctl) {
3121 DHD_ERROR(("%s: %d-byte control read exceeds %d-byte buffer\n",
3122 __func__, rdlen, bus->dhd->maxctl));
3123 bus->dhd->rx_errors++;
3124 dhdsdio_rxfail(bus, FALSE, FALSE);
3125 goto done;
3126 }
3127
3128 if ((len - doff) > bus->dhd->maxctl) {
3129 DHD_ERROR(("%s: %d-byte ctl frame (%d-byte ctl data) exceeds "
3130 "%d-byte limit\n",
3131 __func__, len, (len - doff), bus->dhd->maxctl));
3132 bus->dhd->rx_errors++;
3133 bus->rx_toolong++;
3134 dhdsdio_rxfail(bus, FALSE, FALSE);
3135 goto done;
3136 }
3137
3138 /* Read remainder of frame body into the rxctl buffer */
3139 sdret =
3140 dhd_bcmsdh_recv_buf(bus, bcmsdh_cur_sbwad(sdh), SDIO_FUNC_2, F2SYNC,
3141 (bus->rxctl + firstread), rdlen, NULL, NULL,
3142 NULL);
3143 bus->f2rxdata++;
3144 ASSERT(sdret != BCME_PENDING);
3145
3146 /* Control frame failures need retransmission */
3147 if (sdret < 0) {
3148 DHD_ERROR(("%s: read %d control bytes failed: %d\n",
3149 __func__, rdlen, sdret));
3150 bus->rxc_errors++; /* dhd.rx_ctlerrs is higher level */
3151 dhdsdio_rxfail(bus, TRUE, TRUE);
3152 goto done;
3153 }
3154
3155gotpkt:
3156
3157#ifdef DHD_DEBUG
3158 if (DHD_BYTES_ON() && DHD_CTL_ON())
3159 prhex("RxCtrl", bus->rxctl, len);
3160#endif
3161
3162 /* Point to valid data and indicate its length */
3163 bus->rxctl += doff;
3164 bus->rxlen = len - doff;
3165
3166done:
3167 /* Awake any waiters */
3168 dhd_os_ioctl_resp_wake(bus->dhd);
3169}
3170
3171static uint8 dhdsdio_rxglom(dhd_bus_t *bus, uint8 rxseq)
3172{
3173 uint16 dlen, totlen;
3174 uint8 *dptr, num = 0;
3175
3176 uint16 sublen, check;
3177 void *pfirst, *plast, *pnext, *save_pfirst;
3178 osl_t *osh = bus->dhd->osh;
3179
3180 int errcode;
3181 uint8 chan, seq, doff, sfdoff;
3182 uint8 txmax;
3183
3184 int ifidx = 0;
3185 bool usechain = bus->use_rxchain;
3186
3187 /* If packets, issue read(s) and send up packet chain */
3188 /* Return sequence numbers consumed? */
3189
3190 DHD_TRACE(("dhdsdio_rxglom: start: glomd %p glom %p\n", bus->glomd,
3191 bus->glom));
3192
3193 /* If there's a descriptor, generate the packet chain */
3194 if (bus->glomd) {
3195 dhd_os_sdlock_rxq(bus->dhd);
3196
3197 pfirst = plast = pnext = NULL;
3198 dlen = (uint16) PKTLEN(bus->glomd);
3199 dptr = PKTDATA(bus->glomd);
3200 if (!dlen || (dlen & 1)) {
3201 DHD_ERROR(("%s: bad glomd len(%d), ignore descriptor\n",
3202 __func__, dlen));
3203 dlen = 0;
3204 }
3205
3206 for (totlen = num = 0; dlen; num++) {
3207 /* Get (and move past) next length */
3208 sublen = ltoh16_ua(dptr);
3209 dlen -= sizeof(uint16);
3210 dptr += sizeof(uint16);
3211 if ((sublen < SDPCM_HDRLEN) ||
3212 ((num == 0) && (sublen < (2 * SDPCM_HDRLEN)))) {
3213 DHD_ERROR(("%s: descriptor len %d bad: %d\n",
3214 __func__, num, sublen));
3215 pnext = NULL;
3216 break;
3217 }
3218 if (sublen % DHD_SDALIGN) {
3219 DHD_ERROR(("%s: sublen %d not multiple of %d\n",
3220 __func__, sublen, DHD_SDALIGN));
3221 usechain = FALSE;
3222 }
3223 totlen += sublen;
3224
3225 /* For last frame, adjust read len so total
3226 is a block multiple */
3227 if (!dlen) {
3228 sublen +=
3229 (ROUNDUP(totlen, bus->blocksize) - totlen);
3230 totlen = ROUNDUP(totlen, bus->blocksize);
3231 }
3232
3233 /* Allocate/chain packet for next subframe */
3234 pnext = PKTGET(osh, sublen + DHD_SDALIGN, FALSE);
3235 if (pnext == NULL) {
3236 DHD_ERROR(("%s: PKTGET failed, num %d len %d\n",
3237 __func__, num, sublen));
3238 break;
3239 }
3240 ASSERT(!PKTLINK(pnext));
3241 if (!pfirst) {
3242 ASSERT(!plast);
3243 pfirst = plast = pnext;
3244 } else {
3245 ASSERT(plast);
3246 PKTSETNEXT(plast, pnext);
3247 plast = pnext;
3248 }
3249
3250 /* Adhere to start alignment requirements */
3251 PKTALIGN(osh, pnext, sublen, DHD_SDALIGN);
3252 }
3253
3254 /* If all allocations succeeded, save packet chain
3255 in bus structure */
3256 if (pnext) {
3257 DHD_GLOM(("%s: allocated %d-byte packet chain for %d "
3258 "subframes\n", __func__, totlen, num));
3259 if (DHD_GLOM_ON() && bus->nextlen) {
3260 if (totlen != bus->nextlen) {
3261 DHD_GLOM(("%s: glomdesc mismatch: nextlen %d glomdesc %d " "rxseq %d\n",
3262 __func__, bus->nextlen,
3263 totlen, rxseq));
3264 }
3265 }
3266 bus->glom = pfirst;
3267 pfirst = pnext = NULL;
3268 } else {
3269 if (pfirst)
3270 PKTFREE(osh, pfirst, FALSE);
3271 bus->glom = NULL;
3272 num = 0;
3273 }
3274
3275 /* Done with descriptor packet */
3276 PKTFREE(osh, bus->glomd, FALSE);
3277 bus->glomd = NULL;
3278 bus->nextlen = 0;
3279
3280 dhd_os_sdunlock_rxq(bus->dhd);
3281 }
3282
3283 /* Ok -- either we just generated a packet chain,
3284 or had one from before */
3285 if (bus->glom) {
3286 if (DHD_GLOM_ON()) {
3287 DHD_GLOM(("%s: try superframe read, packet chain:\n",
3288 __func__));
3289 for (pnext = bus->glom; pnext; pnext = PKTNEXT(pnext)) {
3290 DHD_GLOM((" %p: %p len 0x%04x (%d)\n",
3291 pnext, (uint8 *) PKTDATA(pnext),
3292 PKTLEN(pnext), PKTLEN(pnext)));
3293 }
3294 }
3295
3296 pfirst = bus->glom;
3297 dlen = (uint16) pkttotlen(osh, pfirst);
3298
3299 /* Do an SDIO read for the superframe. Configurable iovar to
3300 * read directly into the chained packet, or allocate a large
3301 * packet and and copy into the chain.
3302 */
3303 if (usechain) {
3304 errcode = dhd_bcmsdh_recv_buf(bus,
3305 bcmsdh_cur_sbwad
3306 (bus->sdh), SDIO_FUNC_2,
3307 F2SYNC,
3308 (uint8 *) PKTDATA(pfirst),
3309 dlen, pfirst, NULL, NULL);
3310 } else if (bus->dataptr) {
3311 errcode = dhd_bcmsdh_recv_buf(bus,
3312 bcmsdh_cur_sbwad
3313 (bus->sdh), SDIO_FUNC_2,
3314 F2SYNC, bus->dataptr,
3315 dlen, NULL, NULL, NULL);
3316 sublen =
3317 (uint16) pktfrombuf(osh, pfirst, 0, dlen,
3318 bus->dataptr);
3319 if (sublen != dlen) {
3320 DHD_ERROR(("%s: FAILED TO COPY, dlen %d sublen %d\n",
3321 __func__, dlen, sublen));
3322 errcode = -1;
3323 }
3324 pnext = NULL;
3325 } else {
3326 DHD_ERROR(("COULDN'T ALLOC %d-BYTE GLOM, FORCE FAILURE\n",
3327 dlen));
3328 errcode = -1;
3329 }
3330 bus->f2rxdata++;
3331 ASSERT(errcode != BCME_PENDING);
3332
3333 /* On failure, kill the superframe, allow a couple retries */
3334 if (errcode < 0) {
3335 DHD_ERROR(("%s: glom read of %d bytes failed: %d\n",
3336 __func__, dlen, errcode));
3337 bus->dhd->rx_errors++;
3338
3339 if (bus->glomerr++ < 3) {
3340 dhdsdio_rxfail(bus, TRUE, TRUE);
3341 } else {
3342 bus->glomerr = 0;
3343 dhdsdio_rxfail(bus, TRUE, FALSE);
3344 dhd_os_sdlock_rxq(bus->dhd);
3345 PKTFREE(osh, bus->glom, FALSE);
3346 dhd_os_sdunlock_rxq(bus->dhd);
3347 bus->rxglomfail++;
3348 bus->glom = NULL;
3349 }
3350 return 0;
3351 }
3352#ifdef DHD_DEBUG
3353 if (DHD_GLOM_ON()) {
3354 prhex("SUPERFRAME", PKTDATA(pfirst),
3355 MIN(PKTLEN(pfirst), 48));
3356 }
3357#endif
3358
3359 /* Validate the superframe header */
3360 dptr = (uint8 *) PKTDATA(pfirst);
3361 sublen = ltoh16_ua(dptr);
3362 check = ltoh16_ua(dptr + sizeof(uint16));
3363
3364 chan = SDPCM_PACKET_CHANNEL(&dptr[SDPCM_FRAMETAG_LEN]);
3365 seq = SDPCM_PACKET_SEQUENCE(&dptr[SDPCM_FRAMETAG_LEN]);
3366 bus->nextlen = dptr[SDPCM_FRAMETAG_LEN + SDPCM_NEXTLEN_OFFSET];
3367 if ((bus->nextlen << 4) > MAX_RX_DATASZ) {
3368 DHD_INFO(("%s: nextlen too large (%d) seq %d\n",
3369 __func__, bus->nextlen, seq));
3370 bus->nextlen = 0;
3371 }
3372 doff = SDPCM_DOFFSET_VALUE(&dptr[SDPCM_FRAMETAG_LEN]);
3373 txmax = SDPCM_WINDOW_VALUE(&dptr[SDPCM_FRAMETAG_LEN]);
3374
3375 errcode = 0;
3376 if ((uint16)~(sublen ^ check)) {
3377 DHD_ERROR(("%s (superframe): HW hdr error: len/check "
3378 "0x%04x/0x%04x\n", __func__, sublen, check));
3379 errcode = -1;
3380 } else if (ROUNDUP(sublen, bus->blocksize) != dlen) {
3381 DHD_ERROR(("%s (superframe): len 0x%04x, rounded "
3382 "0x%04x, expect 0x%04x\n",
3383 __func__, sublen,
3384 ROUNDUP(sublen, bus->blocksize), dlen));
3385 errcode = -1;
3386 } else if (SDPCM_PACKET_CHANNEL(&dptr[SDPCM_FRAMETAG_LEN]) !=
3387 SDPCM_GLOM_CHANNEL) {
3388 DHD_ERROR(("%s (superframe): bad channel %d\n",
3389 __func__,
3390 SDPCM_PACKET_CHANNEL(&dptr
3391 [SDPCM_FRAMETAG_LEN])));
3392 errcode = -1;
3393 } else if (SDPCM_GLOMDESC(&dptr[SDPCM_FRAMETAG_LEN])) {
3394 DHD_ERROR(("%s (superframe): got second descriptor?\n",
3395 __func__));
3396 errcode = -1;
3397 } else if ((doff < SDPCM_HDRLEN) ||
3398 (doff > (PKTLEN(pfirst) - SDPCM_HDRLEN))) {
3399 DHD_ERROR(("%s (superframe): Bad data offset %d: HW %d "
3400 "pkt %d min %d\n",
3401 __func__, doff, sublen,
3402 PKTLEN(pfirst), SDPCM_HDRLEN));
3403 errcode = -1;
3404 }
3405
3406 /* Check sequence number of superframe SW header */
3407 if (rxseq != seq) {
3408 DHD_INFO(("%s: (superframe) rx_seq %d, expected %d\n",
3409 __func__, seq, rxseq));
3410 bus->rx_badseq++;
3411 rxseq = seq;
3412 }
3413
3414 /* Check window for sanity */
3415 if ((uint8) (txmax - bus->tx_seq) > 0x40) {
3416 DHD_ERROR(("%s: unlikely tx max %d with tx_seq %d\n",
3417 __func__, txmax, bus->tx_seq));
3418 txmax = bus->tx_seq + 2;
3419 }
3420 bus->tx_max = txmax;
3421
3422 /* Remove superframe header, remember offset */
3423 PKTPULL(pfirst, doff);
3424 sfdoff = doff;
3425
3426 /* Validate all the subframe headers */
3427 for (num = 0, pnext = pfirst; pnext && !errcode;
3428 num++, pnext = PKTNEXT(pnext)) {
3429 dptr = (uint8 *) PKTDATA(pnext);
3430 dlen = (uint16) PKTLEN(pnext);
3431 sublen = ltoh16_ua(dptr);
3432 check = ltoh16_ua(dptr + sizeof(uint16));
3433 chan = SDPCM_PACKET_CHANNEL(&dptr[SDPCM_FRAMETAG_LEN]);
3434 doff = SDPCM_DOFFSET_VALUE(&dptr[SDPCM_FRAMETAG_LEN]);
3435#ifdef DHD_DEBUG
3436 if (DHD_GLOM_ON())
3437 prhex("subframe", dptr, 32);
3438#endif
3439
3440 if ((uint16)~(sublen ^ check)) {
3441 DHD_ERROR(("%s (subframe %d): HW hdr error: "
3442 "len/check 0x%04x/0x%04x\n",
3443 __func__, num, sublen, check));
3444 errcode = -1;
3445 } else if ((sublen > dlen) || (sublen < SDPCM_HDRLEN)) {
3446 DHD_ERROR(("%s (subframe %d): length mismatch: "
3447 "len 0x%04x, expect 0x%04x\n",
3448 __func__, num, sublen, dlen));
3449 errcode = -1;
3450 } else if ((chan != SDPCM_DATA_CHANNEL) &&
3451 (chan != SDPCM_EVENT_CHANNEL)) {
3452 DHD_ERROR(("%s (subframe %d): bad channel %d\n",
3453 __func__, num, chan));
3454 errcode = -1;
3455 } else if ((doff < SDPCM_HDRLEN) || (doff > sublen)) {
3456 DHD_ERROR(("%s (subframe %d): Bad data offset %d: HW %d min %d\n",
3457 __func__, num, doff, sublen,
3458 SDPCM_HDRLEN));
3459 errcode = -1;
3460 }
3461 }
3462
3463 if (errcode) {
3464 /* Terminate frame on error, request
3465 a couple retries */
3466 if (bus->glomerr++ < 3) {
3467 /* Restore superframe header space */
3468 PKTPUSH(pfirst, sfdoff);
3469 dhdsdio_rxfail(bus, TRUE, TRUE);
3470 } else {
3471 bus->glomerr = 0;
3472 dhdsdio_rxfail(bus, TRUE, FALSE);
3473 dhd_os_sdlock_rxq(bus->dhd);
3474 PKTFREE(osh, bus->glom, FALSE);
3475 dhd_os_sdunlock_rxq(bus->dhd);
3476 bus->rxglomfail++;
3477 bus->glom = NULL;
3478 }
3479 bus->nextlen = 0;
3480 return 0;
3481 }
3482
3483 /* Basic SD framing looks ok - process each packet (header) */
3484 save_pfirst = pfirst;
3485 bus->glom = NULL;
3486 plast = NULL;
3487
3488 dhd_os_sdlock_rxq(bus->dhd);
3489 for (num = 0; pfirst; rxseq++, pfirst = pnext) {
3490 pnext = PKTNEXT(pfirst);
3491 PKTSETNEXT(pfirst, NULL);
3492
3493 dptr = (uint8 *) PKTDATA(pfirst);
3494 sublen = ltoh16_ua(dptr);
3495 chan = SDPCM_PACKET_CHANNEL(&dptr[SDPCM_FRAMETAG_LEN]);
3496 seq = SDPCM_PACKET_SEQUENCE(&dptr[SDPCM_FRAMETAG_LEN]);
3497 doff = SDPCM_DOFFSET_VALUE(&dptr[SDPCM_FRAMETAG_LEN]);
3498
3499 DHD_GLOM(("%s: Get subframe %d, %p(%p/%d), sublen %d "
3500 "chan %d seq %d\n",
3501 __func__, num, pfirst, PKTDATA(pfirst),
3502 PKTLEN(pfirst), sublen, chan, seq));
3503
3504 ASSERT((chan == SDPCM_DATA_CHANNEL)
3505 || (chan == SDPCM_EVENT_CHANNEL));
3506
3507 if (rxseq != seq) {
3508 DHD_GLOM(("%s: rx_seq %d, expected %d\n",
3509 __func__, seq, rxseq));
3510 bus->rx_badseq++;
3511 rxseq = seq;
3512 }
3513#ifdef DHD_DEBUG
3514 if (DHD_BYTES_ON() && DHD_DATA_ON())
3515 prhex("Rx Subframe Data", dptr, dlen);
3516#endif
3517
3518 PKTSETLEN(pfirst, sublen);
3519 PKTPULL(pfirst, doff);
3520
3521 if (PKTLEN(pfirst) == 0) {
3522 PKTFREE(bus->dhd->osh, pfirst, FALSE);
3523 if (plast) {
3524 PKTSETNEXT(plast, pnext);
3525 } else {
3526 ASSERT(save_pfirst == pfirst);
3527 save_pfirst = pnext;
3528 }
3529 continue;
3530 } else if (dhd_prot_hdrpull(bus->dhd, &ifidx, pfirst) !=
3531 0) {
3532 DHD_ERROR(("%s: rx protocol error\n",
3533 __func__));
3534 bus->dhd->rx_errors++;
3535 PKTFREE(osh, pfirst, FALSE);
3536 if (plast) {
3537 PKTSETNEXT(plast, pnext);
3538 } else {
3539 ASSERT(save_pfirst == pfirst);
3540 save_pfirst = pnext;
3541 }
3542 continue;
3543 }
3544
3545 /* this packet will go up, link back into
3546 chain and count it */
3547 PKTSETNEXT(pfirst, pnext);
3548 plast = pfirst;
3549 num++;
3550
3551#ifdef DHD_DEBUG
3552 if (DHD_GLOM_ON()) {
3553 DHD_GLOM(("%s subframe %d to stack, %p(%p/%d) "
3554 "nxt/lnk %p/%p\n",
3555 __func__, num, pfirst, PKTDATA(pfirst),
3556 PKTLEN(pfirst), PKTNEXT(pfirst),
3557 PKTLINK(pfirst)));
3558 prhex("", (uint8 *) PKTDATA(pfirst),
3559 MIN(PKTLEN(pfirst), 32));
3560 }
3561#endif /* DHD_DEBUG */
3562 }
3563 dhd_os_sdunlock_rxq(bus->dhd);
3564 if (num) {
3565 dhd_os_sdunlock(bus->dhd);
3566 dhd_rx_frame(bus->dhd, ifidx, save_pfirst, num);
3567 dhd_os_sdlock(bus->dhd);
3568 }
3569
3570 bus->rxglomframes++;
3571 bus->rxglompkts += num;
3572 }
3573 return num;
3574}
3575
3576/* Return TRUE if there may be more frames to read */
3577static uint dhdsdio_readframes(dhd_bus_t *bus, uint maxframes, bool *finished)
3578{
3579 osl_t *osh = bus->dhd->osh;
3580 bcmsdh_info_t *sdh = bus->sdh;
3581
3582 uint16 len, check; /* Extracted hardware header fields */
3583 uint8 chan, seq, doff; /* Extracted software header fields */
3584 uint8 fcbits; /* Extracted fcbits from software header */
3585 uint8 delta;
3586
3587 void *pkt; /* Packet for event or data frames */
3588 uint16 pad; /* Number of pad bytes to read */
3589 uint16 rdlen; /* Total number of bytes to read */
3590 uint8 rxseq; /* Next sequence number to expect */
3591 uint rxleft = 0; /* Remaining number of frames allowed */
3592 int sdret; /* Return code from bcmsdh calls */
3593 uint8 txmax; /* Maximum tx sequence offered */
3594 bool len_consistent; /* Result of comparing readahead len and
3595 len from hw-hdr */
3596 uint8 *rxbuf;
3597 int ifidx = 0;
3598 uint rxcount = 0; /* Total frames read */
3599
3600#if defined(DHD_DEBUG) || defined(SDTEST)
3601 bool sdtest = FALSE; /* To limit message spew from test mode */
3602#endif
3603
3604 DHD_TRACE(("%s: Enter\n", __func__));
3605
3606 ASSERT(maxframes);
3607
3608#ifdef SDTEST
3609 /* Allow pktgen to override maxframes */
3610 if (bus->pktgen_count && (bus->pktgen_mode == DHD_PKTGEN_RECV)) {
3611 maxframes = bus->pktgen_count;
3612 sdtest = TRUE;
3613 }
3614#endif
3615
3616 /* Not finished unless we encounter no more frames indication */
3617 *finished = FALSE;
3618
3619 for (rxseq = bus->rx_seq, rxleft = maxframes;
3620 !bus->rxskip && rxleft && bus->dhd->busstate != DHD_BUS_DOWN;
3621 rxseq++, rxleft--) {
3622
3623 /* Handle glomming separately */
3624 if (bus->glom || bus->glomd) {
3625 uint8 cnt;
3626 DHD_GLOM(("%s: calling rxglom: glomd %p, glom %p\n",
3627 __func__, bus->glomd, bus->glom));
3628 cnt = dhdsdio_rxglom(bus, rxseq);
3629 DHD_GLOM(("%s: rxglom returned %d\n", __func__, cnt));
3630 rxseq += cnt - 1;
3631 rxleft = (rxleft > cnt) ? (rxleft - cnt) : 1;
3632 continue;
3633 }
3634
3635 /* Try doing single read if we can */
3636 if (dhd_readahead && bus->nextlen) {
3637 uint16 nextlen = bus->nextlen;
3638 bus->nextlen = 0;
3639
3640 if (bus->bus == SPI_BUS) {
3641 rdlen = len = nextlen;
3642 } else {
3643 rdlen = len = nextlen << 4;
3644
3645 /* Pad read to blocksize for efficiency */
3646 if (bus->roundup && bus->blocksize
3647 && (rdlen > bus->blocksize)) {
3648 pad =
3649 bus->blocksize -
3650 (rdlen % bus->blocksize);
3651 if ((pad <= bus->roundup)
3652 && (pad < bus->blocksize)
3653 && ((rdlen + pad + firstread) <
3654 MAX_RX_DATASZ))
3655 rdlen += pad;
3656 } else if (rdlen % DHD_SDALIGN) {
3657 rdlen +=
3658 DHD_SDALIGN - (rdlen % DHD_SDALIGN);
3659 }
3660 }
3661
3662 /* We use bus->rxctl buffer in WinXP for initial
3663 * control pkt receives.
3664 * Later we use buffer-poll for data as well
3665 * as control packets.
3666 * This is required becuase dhd receives full
3667 * frame in gSPI unlike SDIO.
3668 * After the frame is received we have to
3669 * distinguish whether it is data
3670 * or non-data frame.
3671 */
3672 /* Allocate a packet buffer */
3673 dhd_os_sdlock_rxq(bus->dhd);
3674 pkt = PKTGET(osh, rdlen + DHD_SDALIGN, FALSE);
3675 if (!pkt) {
3676 if (bus->bus == SPI_BUS) {
3677 bus->usebufpool = FALSE;
3678 bus->rxctl = bus->rxbuf;
3679 if (dhd_alignctl) {
3680 bus->rxctl += firstread;
3681 pad = ((uintptr) bus->rxctl %
3682 DHD_SDALIGN);
3683 if (pad)
3684 bus->rxctl +=
3685 (DHD_SDALIGN - pad);
3686 bus->rxctl -= firstread;
3687 }
3688 ASSERT(bus->rxctl >= bus->rxbuf);
3689 rxbuf = bus->rxctl;
3690 /* Read the entire frame */
3691 sdret = dhd_bcmsdh_recv_buf(bus,
3692 bcmsdh_cur_sbwad
3693 (sdh),
3694 SDIO_FUNC_2,
3695 F2SYNC,
3696 rxbuf,
3697 rdlen, NULL,
3698 NULL, NULL);
3699 bus->f2rxdata++;
3700 ASSERT(sdret != BCME_PENDING);
3701
3702 /* Control frame failures need
3703 retransmission */
3704 if (sdret < 0) {
3705 DHD_ERROR(("%s: read %d control bytes failed: %d\n",
3706 __func__,
3707 rdlen, sdret));
3708 /* dhd.rx_ctlerrs is higher */
3709 bus->rxc_errors++;
3710 dhd_os_sdunlock_rxq(bus->dhd);
3711 dhdsdio_rxfail(bus, TRUE,
3712 (bus->bus ==
3713 SPI_BUS) ? FALSE
3714 : TRUE);
3715 continue;
3716 }
3717 } else {
3718 /* Give up on data,
3719 request rtx of events */
3720 DHD_ERROR(("%s (nextlen): PKTGET failed: len %d rdlen %d " "expected rxseq %d\n",
3721 __func__, len, rdlen, rxseq));
3722 /* Just go try again w/normal
3723 header read */
3724 dhd_os_sdunlock_rxq(bus->dhd);
3725 continue;
3726 }
3727 } else {
3728 if (bus->bus == SPI_BUS)
3729 bus->usebufpool = TRUE;
3730
3731 ASSERT(!PKTLINK(pkt));
3732 PKTALIGN(osh, pkt, rdlen, DHD_SDALIGN);
3733 rxbuf = (uint8 *) PKTDATA(pkt);
3734 /* Read the entire frame */
3735 sdret =
3736 dhd_bcmsdh_recv_buf(bus,
3737 bcmsdh_cur_sbwad(sdh),
3738 SDIO_FUNC_2, F2SYNC,
3739 rxbuf, rdlen, pkt, NULL,
3740 NULL);
3741 bus->f2rxdata++;
3742 ASSERT(sdret != BCME_PENDING);
3743
3744 if (sdret < 0) {
3745 DHD_ERROR(("%s (nextlen): read %d bytes failed: %d\n",
3746 __func__, rdlen, sdret));
3747 PKTFREE(bus->dhd->osh, pkt, FALSE);
3748 bus->dhd->rx_errors++;
3749 dhd_os_sdunlock_rxq(bus->dhd);
3750 /* Force retry w/normal header read.
3751 * Don't attemp NAK for
3752 * gSPI
3753 */
3754 dhdsdio_rxfail(bus, TRUE,
3755 (bus->bus ==
3756 SPI_BUS) ? FALSE :
3757 TRUE);
3758 continue;
3759 }
3760 }
3761 dhd_os_sdunlock_rxq(bus->dhd);
3762
3763 /* Now check the header */
3764 bcopy(rxbuf, bus->rxhdr, SDPCM_HDRLEN);
3765
3766 /* Extract hardware header fields */
3767 len = ltoh16_ua(bus->rxhdr);
3768 check = ltoh16_ua(bus->rxhdr + sizeof(uint16));
3769
3770 /* All zeros means readahead info was bad */
3771 if (!(len | check)) {
3772 DHD_INFO(("%s (nextlen): read zeros in HW "
3773 "header???\n", __func__));
3774 dhd_os_sdlock_rxq(bus->dhd);
3775 PKTFREE2();
3776 dhd_os_sdunlock_rxq(bus->dhd);
3777 GSPI_PR55150_BAILOUT;
3778 continue;
3779 }
3780
3781 /* Validate check bytes */
3782 if ((uint16)~(len ^ check)) {
3783 DHD_ERROR(("%s (nextlen): HW hdr error: nextlen/len/check" " 0x%04x/0x%04x/0x%04x\n",
3784 __func__, nextlen, len, check));
3785 dhd_os_sdlock_rxq(bus->dhd);
3786 PKTFREE2();
3787 dhd_os_sdunlock_rxq(bus->dhd);
3788 bus->rx_badhdr++;
3789 dhdsdio_rxfail(bus, FALSE, FALSE);
3790 GSPI_PR55150_BAILOUT;
3791 continue;
3792 }
3793
3794 /* Validate frame length */
3795 if (len < SDPCM_HDRLEN) {
3796 DHD_ERROR(("%s (nextlen): HW hdr length "
3797 "invalid: %d\n", __func__, len));
3798 dhd_os_sdlock_rxq(bus->dhd);
3799 PKTFREE2();
3800 dhd_os_sdunlock_rxq(bus->dhd);
3801 GSPI_PR55150_BAILOUT;
3802 continue;
3803 }
3804
3805 /* Check for consistency withreadahead info */
3806 len_consistent = (nextlen != (ROUNDUP(len, 16) >> 4));
3807 if (len_consistent) {
3808 /* Mismatch, force retry w/normal
3809 header (may be >4K) */
3810 DHD_ERROR(("%s (nextlen): mismatch, nextlen %d len %d rnd %d; " "expected rxseq %d\n",
3811 __func__, nextlen,
3812 len, ROUNDUP(len, 16), rxseq));
3813 dhd_os_sdlock_rxq(bus->dhd);
3814 PKTFREE2();
3815 dhd_os_sdunlock_rxq(bus->dhd);
3816 dhdsdio_rxfail(bus, TRUE,
3817 (bus->bus ==
3818 SPI_BUS) ? FALSE : TRUE);
3819 GSPI_PR55150_BAILOUT;
3820 continue;
3821 }
3822
3823 /* Extract software header fields */
3824 chan =
3825 SDPCM_PACKET_CHANNEL(&bus->rxhdr
3826 [SDPCM_FRAMETAG_LEN]);
3827 seq =
3828 SDPCM_PACKET_SEQUENCE(&bus->rxhdr
3829 [SDPCM_FRAMETAG_LEN]);
3830 doff =
3831 SDPCM_DOFFSET_VALUE(&bus->rxhdr
3832 [SDPCM_FRAMETAG_LEN]);
3833 txmax =
3834 SDPCM_WINDOW_VALUE(&bus->rxhdr[SDPCM_FRAMETAG_LEN]);
3835
3836 bus->nextlen =
3837 bus->rxhdr[SDPCM_FRAMETAG_LEN +
3838 SDPCM_NEXTLEN_OFFSET];
3839 if ((bus->nextlen << 4) > MAX_RX_DATASZ) {
3840 DHD_INFO(("%s (nextlen): got frame w/nextlen too large" " (%d), seq %d\n",
3841 __func__, bus->nextlen, seq));
3842 bus->nextlen = 0;
3843 }
3844
3845 bus->dhd->rx_readahead_cnt++;
3846 /* Handle Flow Control */
3847 fcbits =
3848 SDPCM_FCMASK_VALUE(&bus->rxhdr[SDPCM_FRAMETAG_LEN]);
3849
3850 delta = 0;
3851 if (~bus->flowcontrol & fcbits) {
3852 bus->fc_xoff++;
3853 delta = 1;
3854 }
3855 if (bus->flowcontrol & ~fcbits) {
3856 bus->fc_xon++;
3857 delta = 1;
3858 }
3859
3860 if (delta) {
3861 bus->fc_rcvd++;
3862 bus->flowcontrol = fcbits;
3863 }
3864
3865 /* Check and update sequence number */
3866 if (rxseq != seq) {
3867 DHD_INFO(("%s (nextlen): rx_seq %d, expected "
3868 "%d\n", __func__, seq, rxseq));
3869 bus->rx_badseq++;
3870 rxseq = seq;
3871 }
3872
3873 /* Check window for sanity */
3874 if ((uint8) (txmax - bus->tx_seq) > 0x40) {
3875 DHD_ERROR(("%s: got unlikely tx max %d with "
3876 "tx_seq %d\n",
3877 __func__, txmax, bus->tx_seq));
3878 txmax = bus->tx_seq + 2;
3879 }
3880 bus->tx_max = txmax;
3881
3882#ifdef DHD_DEBUG
3883 if (DHD_BYTES_ON() && DHD_DATA_ON())
3884 prhex("Rx Data", rxbuf, len);
3885 else if (DHD_HDRS_ON())
3886 prhex("RxHdr", bus->rxhdr, SDPCM_HDRLEN);
3887#endif
3888
3889 if (chan == SDPCM_CONTROL_CHANNEL) {
3890 if (bus->bus == SPI_BUS) {
3891 dhdsdio_read_control(bus, rxbuf, len,
3892 doff);
3893 if (bus->usebufpool) {
3894 dhd_os_sdlock_rxq(bus->dhd);
3895 PKTFREE(bus->dhd->osh, pkt,
3896 FALSE);
3897 dhd_os_sdunlock_rxq(bus->dhd);
3898 }
3899 continue;
3900 } else {
3901 DHD_ERROR(("%s (nextlen): readahead on control" " packet %d?\n",
3902 __func__, seq));
3903 /* Force retry w/normal header read */
3904 bus->nextlen = 0;
3905 dhdsdio_rxfail(bus, FALSE, TRUE);
3906 dhd_os_sdlock_rxq(bus->dhd);
3907 PKTFREE2();
3908 dhd_os_sdunlock_rxq(bus->dhd);
3909 continue;
3910 }
3911 }
3912
3913 if ((bus->bus == SPI_BUS) && !bus->usebufpool) {
3914 DHD_ERROR(("Received %d bytes on %d channel. Running out of " "rx pktbuf's or not yet malloced.\n",
3915 len, chan));
3916 continue;
3917 }
3918
3919 /* Validate data offset */
3920 if ((doff < SDPCM_HDRLEN) || (doff > len)) {
3921 DHD_ERROR(("%s (nextlen): bad data offset %d: HW len %d min %d\n",
3922 __func__, doff, len, SDPCM_HDRLEN));
3923 dhd_os_sdlock_rxq(bus->dhd);
3924 PKTFREE2();
3925 dhd_os_sdunlock_rxq(bus->dhd);
3926 ASSERT(0);
3927 dhdsdio_rxfail(bus, FALSE, FALSE);
3928 continue;
3929 }
3930
3931 /* All done with this one -- now deliver the packet */
3932 goto deliver;
3933 }
3934 /* gSPI frames should not be handled in fractions */
3935 if (bus->bus == SPI_BUS)
3936 break;
3937
3938 /* Read frame header (hardware and software) */
3939 sdret =
3940 dhd_bcmsdh_recv_buf(bus, bcmsdh_cur_sbwad(sdh), SDIO_FUNC_2,
3941 F2SYNC, bus->rxhdr, firstread, NULL,
3942 NULL, NULL);
3943 bus->f2rxhdrs++;
3944 ASSERT(sdret != BCME_PENDING);
3945
3946 if (sdret < 0) {
3947 DHD_ERROR(("%s: RXHEADER FAILED: %d\n", __func__,
3948 sdret));
3949 bus->rx_hdrfail++;
3950 dhdsdio_rxfail(bus, TRUE, TRUE);
3951 continue;
3952 }
3953#ifdef DHD_DEBUG
3954 if (DHD_BYTES_ON() || DHD_HDRS_ON())
3955 prhex("RxHdr", bus->rxhdr, SDPCM_HDRLEN);
3956#endif
3957
3958 /* Extract hardware header fields */
3959 len = ltoh16_ua(bus->rxhdr);
3960 check = ltoh16_ua(bus->rxhdr + sizeof(uint16));
3961
3962 /* All zeros means no more frames */
3963 if (!(len | check)) {
3964 *finished = TRUE;
3965 break;
3966 }
3967
3968 /* Validate check bytes */
3969 if ((uint16) ~ (len ^ check)) {
3970 DHD_ERROR(("%s: HW hdr err: len/check 0x%04x/0x%04x\n",
3971 __func__, len, check));
3972 bus->rx_badhdr++;
3973 dhdsdio_rxfail(bus, FALSE, FALSE);
3974 continue;
3975 }
3976
3977 /* Validate frame length */
3978 if (len < SDPCM_HDRLEN) {
3979 DHD_ERROR(("%s: HW hdr length invalid: %d\n",
3980 __func__, len));
3981 continue;
3982 }
3983
3984 /* Extract software header fields */
3985 chan = SDPCM_PACKET_CHANNEL(&bus->rxhdr[SDPCM_FRAMETAG_LEN]);
3986 seq = SDPCM_PACKET_SEQUENCE(&bus->rxhdr[SDPCM_FRAMETAG_LEN]);
3987 doff = SDPCM_DOFFSET_VALUE(&bus->rxhdr[SDPCM_FRAMETAG_LEN]);
3988 txmax = SDPCM_WINDOW_VALUE(&bus->rxhdr[SDPCM_FRAMETAG_LEN]);
3989
3990 /* Validate data offset */
3991 if ((doff < SDPCM_HDRLEN) || (doff > len)) {
3992 DHD_ERROR(("%s: Bad data offset %d: HW len %d, min %d "
3993 "seq %d\n",
3994 __func__, doff, len, SDPCM_HDRLEN, seq));
3995 bus->rx_badhdr++;
3996 ASSERT(0);
3997 dhdsdio_rxfail(bus, FALSE, FALSE);
3998 continue;
3999 }
4000
4001 /* Save the readahead length if there is one */
4002 bus->nextlen =
4003 bus->rxhdr[SDPCM_FRAMETAG_LEN + SDPCM_NEXTLEN_OFFSET];
4004 if ((bus->nextlen << 4) > MAX_RX_DATASZ) {
4005 DHD_INFO(("%s (nextlen): got frame w/nextlen too large "
4006 "(%d), seq %d\n",
4007 __func__, bus->nextlen, seq));
4008 bus->nextlen = 0;
4009 }
4010
4011 /* Handle Flow Control */
4012 fcbits = SDPCM_FCMASK_VALUE(&bus->rxhdr[SDPCM_FRAMETAG_LEN]);
4013
4014 delta = 0;
4015 if (~bus->flowcontrol & fcbits) {
4016 bus->fc_xoff++;
4017 delta = 1;
4018 }
4019 if (bus->flowcontrol & ~fcbits) {
4020 bus->fc_xon++;
4021 delta = 1;
4022 }
4023
4024 if (delta) {
4025 bus->fc_rcvd++;
4026 bus->flowcontrol = fcbits;
4027 }
4028
4029 /* Check and update sequence number */
4030 if (rxseq != seq) {
4031 DHD_INFO(("%s: rx_seq %d, expected %d\n", __func__,
4032 seq, rxseq));
4033 bus->rx_badseq++;
4034 rxseq = seq;
4035 }
4036
4037 /* Check window for sanity */
4038 if ((uint8) (txmax - bus->tx_seq) > 0x40) {
4039 DHD_ERROR(("%s: unlikely tx max %d with tx_seq %d\n",
4040 __func__, txmax, bus->tx_seq));
4041 txmax = bus->tx_seq + 2;
4042 }
4043 bus->tx_max = txmax;
4044
4045 /* Call a separate function for control frames */
4046 if (chan == SDPCM_CONTROL_CHANNEL) {
4047 dhdsdio_read_control(bus, bus->rxhdr, len, doff);
4048 continue;
4049 }
4050
4051 ASSERT((chan == SDPCM_DATA_CHANNEL)
4052 || (chan == SDPCM_EVENT_CHANNEL)
4053 || (chan == SDPCM_TEST_CHANNEL)
4054 || (chan == SDPCM_GLOM_CHANNEL));
4055
4056 /* Length to read */
4057 rdlen = (len > firstread) ? (len - firstread) : 0;
4058
4059 /* May pad read to blocksize for efficiency */
4060 if (bus->roundup && bus->blocksize &&
4061 (rdlen > bus->blocksize)) {
4062 pad = bus->blocksize - (rdlen % bus->blocksize);
4063 if ((pad <= bus->roundup) && (pad < bus->blocksize) &&
4064 ((rdlen + pad + firstread) < MAX_RX_DATASZ))
4065 rdlen += pad;
4066 } else if (rdlen % DHD_SDALIGN) {
4067 rdlen += DHD_SDALIGN - (rdlen % DHD_SDALIGN);
4068 }
4069
4070 /* Satisfy length-alignment requirements */
4071 if (forcealign && (rdlen & (ALIGNMENT - 1)))
4072 rdlen = ROUNDUP(rdlen, ALIGNMENT);
4073
4074 if ((rdlen + firstread) > MAX_RX_DATASZ) {
4075 /* Too long -- skip this frame */
4076 DHD_ERROR(("%s: too long: len %d rdlen %d\n",
4077 __func__, len, rdlen));
4078 bus->dhd->rx_errors++;
4079 bus->rx_toolong++;
4080 dhdsdio_rxfail(bus, FALSE, FALSE);
4081 continue;
4082 }
4083
4084 dhd_os_sdlock_rxq(bus->dhd);
4085 pkt = PKTGET(osh, (rdlen + firstread + DHD_SDALIGN), FALSE);
4086 if (!pkt) {
4087 /* Give up on data, request rtx of events */
4088 DHD_ERROR(("%s: PKTGET failed: rdlen %d chan %d\n",
4089 __func__, rdlen, chan));
4090 bus->dhd->rx_dropped++;
4091 dhd_os_sdunlock_rxq(bus->dhd);
4092 dhdsdio_rxfail(bus, FALSE, RETRYCHAN(chan));
4093 continue;
4094 }
4095 dhd_os_sdunlock_rxq(bus->dhd);
4096
4097 ASSERT(!PKTLINK(pkt));
4098
4099 /* Leave room for what we already read, and align remainder */
4100 ASSERT(firstread < (PKTLEN(pkt)));
4101 PKTPULL(pkt, firstread);
4102 PKTALIGN(osh, pkt, rdlen, DHD_SDALIGN);
4103
4104 /* Read the remaining frame data */
4105 sdret =
4106 dhd_bcmsdh_recv_buf(bus, bcmsdh_cur_sbwad(sdh), SDIO_FUNC_2,
4107 F2SYNC, ((uint8 *) PKTDATA(pkt)), rdlen,
4108 pkt, NULL, NULL);
4109 bus->f2rxdata++;
4110 ASSERT(sdret != BCME_PENDING);
4111
4112 if (sdret < 0) {
4113 DHD_ERROR(("%s: read %d %s bytes failed: %d\n",
4114 __func__, rdlen,
4115 ((chan ==
4116 SDPCM_EVENT_CHANNEL) ? "event" : ((chan ==
4117 SDPCM_DATA_CHANNEL)
4118 ? "data" : "test")),
4119 sdret));
4120 dhd_os_sdlock_rxq(bus->dhd);
4121 PKTFREE(bus->dhd->osh, pkt, FALSE);
4122 dhd_os_sdunlock_rxq(bus->dhd);
4123 bus->dhd->rx_errors++;
4124 dhdsdio_rxfail(bus, TRUE, RETRYCHAN(chan));
4125 continue;
4126 }
4127
4128 /* Copy the already-read portion */
4129 PKTPUSH(pkt, firstread);
4130 bcopy(bus->rxhdr, PKTDATA(pkt), firstread);
4131
4132#ifdef DHD_DEBUG
4133 if (DHD_BYTES_ON() && DHD_DATA_ON())
4134 prhex("Rx Data", PKTDATA(pkt), len);
4135#endif
4136
4137deliver:
4138 /* Save superframe descriptor and allocate packet frame */
4139 if (chan == SDPCM_GLOM_CHANNEL) {
4140 if (SDPCM_GLOMDESC(&bus->rxhdr[SDPCM_FRAMETAG_LEN])) {
4141 DHD_GLOM(("%s: glom descriptor, %d bytes:\n",
4142 __func__, len));
4143#ifdef DHD_DEBUG
4144 if (DHD_GLOM_ON()) {
4145 prhex("Glom Data", PKTDATA(pkt), len);
4146 }
4147#endif
4148 PKTSETLEN(pkt, len);
4149 ASSERT(doff == SDPCM_HDRLEN);
4150 PKTPULL(pkt, SDPCM_HDRLEN);
4151 bus->glomd = pkt;
4152 } else {
4153 DHD_ERROR(("%s: glom superframe w/o "
4154 "descriptor!\n", __func__));
4155 dhdsdio_rxfail(bus, FALSE, FALSE);
4156 }
4157 continue;
4158 }
4159
4160 /* Fill in packet len and prio, deliver upward */
4161 PKTSETLEN(pkt, len);
4162 PKTPULL(pkt, doff);
4163
4164#ifdef SDTEST
4165 /* Test channel packets are processed separately */
4166 if (chan == SDPCM_TEST_CHANNEL) {
4167 dhdsdio_testrcv(bus, pkt, seq);
4168 continue;
4169 }
4170#endif /* SDTEST */
4171
4172 if (PKTLEN(pkt) == 0) {
4173 dhd_os_sdlock_rxq(bus->dhd);
4174 PKTFREE(bus->dhd->osh, pkt, FALSE);
4175 dhd_os_sdunlock_rxq(bus->dhd);
4176 continue;
4177 } else if (dhd_prot_hdrpull(bus->dhd, &ifidx, pkt) != 0) {
4178 DHD_ERROR(("%s: rx protocol error\n", __func__));
4179 dhd_os_sdlock_rxq(bus->dhd);
4180 PKTFREE(bus->dhd->osh, pkt, FALSE);
4181 dhd_os_sdunlock_rxq(bus->dhd);
4182 bus->dhd->rx_errors++;
4183 continue;
4184 }
4185
4186 /* Unlock during rx call */
4187 dhd_os_sdunlock(bus->dhd);
4188 dhd_rx_frame(bus->dhd, ifidx, pkt, 1);
4189 dhd_os_sdlock(bus->dhd);
4190 }
4191 rxcount = maxframes - rxleft;
4192#ifdef DHD_DEBUG
4193 /* Message if we hit the limit */
4194 if (!rxleft && !sdtest)
4195 DHD_DATA(("%s: hit rx limit of %d frames\n", __func__,
4196 maxframes));
4197 else
4198#endif /* DHD_DEBUG */
4199 DHD_DATA(("%s: processed %d frames\n", __func__, rxcount));
4200 /* Back off rxseq if awaiting rtx, update rx_seq */
4201 if (bus->rxskip)
4202 rxseq--;
4203 bus->rx_seq = rxseq;
4204
4205 return rxcount;
4206}
4207
4208static uint32 dhdsdio_hostmail(dhd_bus_t *bus)
4209{
4210 sdpcmd_regs_t *regs = bus->regs;
4211 uint32 intstatus = 0;
4212 uint32 hmb_data;
4213 uint8 fcbits;
4214 uint retries = 0;
4215
4216 DHD_TRACE(("%s: Enter\n", __func__));
4217
4218 /* Read mailbox data and ack that we did so */
4219 R_SDREG(hmb_data, &regs->tohostmailboxdata, retries);
4220 if (retries <= retry_limit)
4221 W_SDREG(SMB_INT_ACK, &regs->tosbmailbox, retries);
4222 bus->f1regdata += 2;
4223
4224 /* Dongle recomposed rx frames, accept them again */
4225 if (hmb_data & HMB_DATA_NAKHANDLED) {
4226 DHD_INFO(("Dongle reports NAK handled, expect rtx of %d\n",
4227 bus->rx_seq));
4228 if (!bus->rxskip)
4229 DHD_ERROR(("%s: unexpected NAKHANDLED!\n", __func__));
4230
4231 bus->rxskip = FALSE;
4232 intstatus |= I_HMB_FRAME_IND;
4233 }
4234
4235 /*
4236 * DEVREADY does not occur with gSPI.
4237 */
4238 if (hmb_data & (HMB_DATA_DEVREADY | HMB_DATA_FWREADY)) {
4239 bus->sdpcm_ver =
4240 (hmb_data & HMB_DATA_VERSION_MASK) >>
4241 HMB_DATA_VERSION_SHIFT;
4242 if (bus->sdpcm_ver != SDPCM_PROT_VERSION)
4243 DHD_ERROR(("Version mismatch, dongle reports %d, "
4244 "expecting %d\n",
4245 bus->sdpcm_ver, SDPCM_PROT_VERSION));
4246 else
4247 DHD_INFO(("Dongle ready, protocol version %d\n",
4248 bus->sdpcm_ver));
4249 }
4250
4251 /*
4252 * Flow Control has been moved into the RX headers and this out of band
4253 * method isn't used any more. Leae this here for possibly
4254 * remaining backward
4255 * compatible with older dongles
4256 */
4257 if (hmb_data & HMB_DATA_FC) {
4258 fcbits =
4259 (hmb_data & HMB_DATA_FCDATA_MASK) >> HMB_DATA_FCDATA_SHIFT;
4260
4261 if (fcbits & ~bus->flowcontrol)
4262 bus->fc_xoff++;
4263 if (bus->flowcontrol & ~fcbits)
4264 bus->fc_xon++;
4265
4266 bus->fc_rcvd++;
4267 bus->flowcontrol = fcbits;
4268 }
4269
4270 /* Shouldn't be any others */
4271 if (hmb_data & ~(HMB_DATA_DEVREADY |
4272 HMB_DATA_NAKHANDLED |
4273 HMB_DATA_FC |
4274 HMB_DATA_FWREADY |
4275 HMB_DATA_FCDATA_MASK | HMB_DATA_VERSION_MASK)) {
4276 DHD_ERROR(("Unknown mailbox data content: 0x%02x\n", hmb_data));
4277 }
4278
4279 return intstatus;
4280}
4281
4282bool dhdsdio_dpc(dhd_bus_t *bus)
4283{
4284 bcmsdh_info_t *sdh = bus->sdh;
4285 sdpcmd_regs_t *regs = bus->regs;
4286 uint32 intstatus, newstatus = 0;
4287 uint retries = 0;
4288 uint rxlimit = dhd_rxbound; /* Rx frames to read before resched */
4289 uint txlimit = dhd_txbound; /* Tx frames to send before resched */
4290 uint framecnt = 0; /* Temporary counter of tx/rx frames */
4291 bool rxdone = TRUE; /* Flag for no more read data */
4292 bool resched = FALSE; /* Flag indicating resched wanted */
4293
4294 DHD_TRACE(("%s: Enter\n", __func__));
4295
4296 /* Start with leftover status bits */
4297 intstatus = bus->intstatus;
4298
4299 dhd_os_sdlock(bus->dhd);
4300
4301 /* If waiting for HTAVAIL, check status */
4302 if (bus->clkstate == CLK_PENDING) {
4303 int err;
4304 uint8 clkctl, devctl = 0;
4305
4306#ifdef DHD_DEBUG
4307 /* Check for inconsistent device control */
4308 devctl =
4309 bcmsdh_cfg_read(sdh, SDIO_FUNC_1, SBSDIO_DEVICE_CTL, &err);
4310 if (err) {
4311 DHD_ERROR(("%s: error reading DEVCTL: %d\n",
4312 __func__, err));
4313 bus->dhd->busstate = DHD_BUS_DOWN;
4314 } else {
4315 ASSERT(devctl & SBSDIO_DEVCTL_CA_INT_ONLY);
4316 }
4317#endif /* DHD_DEBUG */
4318
4319 /* Read CSR, if clock on switch to AVAIL, else ignore */
4320 clkctl =
4321 bcmsdh_cfg_read(sdh, SDIO_FUNC_1, SBSDIO_FUNC1_CHIPCLKCSR,
4322 &err);
4323 if (err) {
4324 DHD_ERROR(("%s: error reading CSR: %d\n", __func__,
4325 err));
4326 bus->dhd->busstate = DHD_BUS_DOWN;
4327 }
4328
4329 DHD_INFO(("DPC: PENDING, devctl 0x%02x clkctl 0x%02x\n", devctl,
4330 clkctl));
4331
4332 if (SBSDIO_HTAV(clkctl)) {
4333 devctl =
4334 bcmsdh_cfg_read(sdh, SDIO_FUNC_1, SBSDIO_DEVICE_CTL,
4335 &err);
4336 if (err) {
4337 DHD_ERROR(("%s: error reading DEVCTL: %d\n",
4338 __func__, err));
4339 bus->dhd->busstate = DHD_BUS_DOWN;
4340 }
4341 devctl &= ~SBSDIO_DEVCTL_CA_INT_ONLY;
4342 bcmsdh_cfg_write(sdh, SDIO_FUNC_1, SBSDIO_DEVICE_CTL,
4343 devctl, &err);
4344 if (err) {
4345 DHD_ERROR(("%s: error writing DEVCTL: %d\n",
4346 __func__, err));
4347 bus->dhd->busstate = DHD_BUS_DOWN;
4348 }
4349 bus->clkstate = CLK_AVAIL;
4350 } else {
4351 goto clkwait;
4352 }
4353 }
4354
4355 BUS_WAKE(bus);
4356
4357 /* Make sure backplane clock is on */
4358 dhdsdio_clkctl(bus, CLK_AVAIL, TRUE);
4359 if (bus->clkstate == CLK_PENDING)
4360 goto clkwait;
4361
4362 /* Pending interrupt indicates new device status */
4363 if (bus->ipend) {
4364 bus->ipend = FALSE;
4365 R_SDREG(newstatus, &regs->intstatus, retries);
4366 bus->f1regdata++;
4367 if (bcmsdh_regfail(bus->sdh))
4368 newstatus = 0;
4369 newstatus &= bus->hostintmask;
4370 bus->fcstate = !!(newstatus & I_HMB_FC_STATE);
4371 if (newstatus) {
4372 W_SDREG(newstatus, &regs->intstatus, retries);
4373 bus->f1regdata++;
4374 }
4375 }
4376
4377 /* Merge new bits with previous */
4378 intstatus |= newstatus;
4379 bus->intstatus = 0;
4380
4381 /* Handle flow-control change: read new state in case our ack
4382 * crossed another change interrupt. If change still set, assume
4383 * FC ON for safety, let next loop through do the debounce.
4384 */
4385 if (intstatus & I_HMB_FC_CHANGE) {
4386 intstatus &= ~I_HMB_FC_CHANGE;
4387 W_SDREG(I_HMB_FC_CHANGE, &regs->intstatus, retries);
4388 R_SDREG(newstatus, &regs->intstatus, retries);
4389 bus->f1regdata += 2;
4390 bus->fcstate =
4391 !!(newstatus & (I_HMB_FC_STATE | I_HMB_FC_CHANGE));
4392 intstatus |= (newstatus & bus->hostintmask);
4393 }
4394
4395 /* Handle host mailbox indication */
4396 if (intstatus & I_HMB_HOST_INT) {
4397 intstatus &= ~I_HMB_HOST_INT;
4398 intstatus |= dhdsdio_hostmail(bus);
4399 }
4400
4401 /* Generally don't ask for these, can get CRC errors... */
4402 if (intstatus & I_WR_OOSYNC) {
4403 DHD_ERROR(("Dongle reports WR_OOSYNC\n"));
4404 intstatus &= ~I_WR_OOSYNC;
4405 }
4406
4407 if (intstatus & I_RD_OOSYNC) {
4408 DHD_ERROR(("Dongle reports RD_OOSYNC\n"));
4409 intstatus &= ~I_RD_OOSYNC;
4410 }
4411
4412 if (intstatus & I_SBINT) {
4413 DHD_ERROR(("Dongle reports SBINT\n"));
4414 intstatus &= ~I_SBINT;
4415 }
4416
4417 /* Would be active due to wake-wlan in gSPI */
4418 if (intstatus & I_CHIPACTIVE) {
4419 DHD_INFO(("Dongle reports CHIPACTIVE\n"));
4420 intstatus &= ~I_CHIPACTIVE;
4421 }
4422
4423 /* Ignore frame indications if rxskip is set */
4424 if (bus->rxskip)
4425 intstatus &= ~I_HMB_FRAME_IND;
4426
4427 /* On frame indication, read available frames */
4428 if (PKT_AVAILABLE()) {
4429 framecnt = dhdsdio_readframes(bus, rxlimit, &rxdone);
4430 if (rxdone || bus->rxskip)
4431 intstatus &= ~I_HMB_FRAME_IND;
4432 rxlimit -= MIN(framecnt, rxlimit);
4433 }
4434
4435 /* Keep still-pending events for next scheduling */
4436 bus->intstatus = intstatus;
4437
4438clkwait:
4439#if defined(OOB_INTR_ONLY)
4440 bcmsdh_oob_intr_set(1);
4441#endif /* (OOB_INTR_ONLY) */
4442 /* Re-enable interrupts to detect new device events (mailbox, rx frame)
4443 * or clock availability. (Allows tx loop to check ipend if desired.)
4444 * (Unless register access seems hosed, as we may not be able to ACK...)
4445 */
4446 if (bus->intr && bus->intdis && !bcmsdh_regfail(sdh)) {
4447 DHD_INTR(("%s: enable SDIO interrupts, rxdone %d framecnt %d\n",
4448 __func__, rxdone, framecnt));
4449 bus->intdis = FALSE;
4450 bcmsdh_intr_enable(sdh);
4451 }
4452
4453 if (DATAOK(bus) && bus->ctrl_frame_stat &&
4454 (bus->clkstate == CLK_AVAIL)) {
4455 int ret, i;
4456
4457 ret =
4458 dhd_bcmsdh_send_buf(bus, bcmsdh_cur_sbwad(sdh), SDIO_FUNC_2,
4459 F2SYNC, (uint8 *) bus->ctrl_frame_buf,
4460 (uint32) bus->ctrl_frame_len, NULL,
4461 NULL, NULL);
4462 ASSERT(ret != BCME_PENDING);
4463
4464 if (ret < 0) {
4465 /* On failure, abort the command and
4466 terminate the frame */
4467 DHD_INFO(("%s: sdio error %d, abort command and "
4468 "terminate frame.\n", __func__, ret));
4469 bus->tx_sderrs++;
4470
4471 bcmsdh_abort(sdh, SDIO_FUNC_2);
4472
4473 bcmsdh_cfg_write(sdh, SDIO_FUNC_1,
4474 SBSDIO_FUNC1_FRAMECTRL, SFC_WF_TERM,
4475 NULL);
4476 bus->f1regdata++;
4477
4478 for (i = 0; i < 3; i++) {
4479 uint8 hi, lo;
4480 hi = bcmsdh_cfg_read(sdh, SDIO_FUNC_1,
4481 SBSDIO_FUNC1_WFRAMEBCHI,
4482 NULL);
4483 lo = bcmsdh_cfg_read(sdh, SDIO_FUNC_1,
4484 SBSDIO_FUNC1_WFRAMEBCLO,
4485 NULL);
4486 bus->f1regdata += 2;
4487 if ((hi == 0) && (lo == 0))
4488 break;
4489 }
4490
4491 }
4492 if (ret == 0)
4493 bus->tx_seq = (bus->tx_seq + 1) % SDPCM_SEQUENCE_WRAP;
4494
4495 printf("Return_dpc value is : %d\n", ret);
4496 bus->ctrl_frame_stat = FALSE;
4497 dhd_wait_event_wakeup(bus->dhd);
4498 }
4499 /* Send queued frames (limit 1 if rx may still be pending) */
4500 else if ((bus->clkstate == CLK_AVAIL) && !bus->fcstate &&
4501 pktq_mlen(&bus->txq, ~bus->flowcontrol) && txlimit
4502 && DATAOK(bus)) {
4503 framecnt = rxdone ? txlimit : MIN(txlimit, dhd_txminmax);
4504 framecnt = dhdsdio_sendfromq(bus, framecnt);
4505 txlimit -= framecnt;
4506 }
4507
4508 /* Resched if events or tx frames are pending,
4509 else await next interrupt */
4510 /* On failed register access, all bets are off:
4511 no resched or interrupts */
4512 if ((bus->dhd->busstate == DHD_BUS_DOWN) || bcmsdh_regfail(sdh)) {
4513 DHD_ERROR(("%s: failed backplane access over SDIO, halting "
4514 "operation %d\n", __func__, bcmsdh_regfail(sdh)));
4515 bus->dhd->busstate = DHD_BUS_DOWN;
4516 bus->intstatus = 0;
4517 } else if (bus->clkstate == CLK_PENDING) {
4518 DHD_INFO(("%s: rescheduled due to CLK_PENDING awaiting "
4519 "I_CHIPACTIVE interrupt\n", __func__));
4520 resched = TRUE;
4521 } else if (bus->intstatus || bus->ipend ||
4522 (!bus->fcstate && pktq_mlen(&bus->txq, ~bus->flowcontrol) &&
4523 DATAOK(bus)) || PKT_AVAILABLE()) {
4524 resched = TRUE;
4525 }
4526
4527 bus->dpc_sched = resched;
4528
4529 /* If we're done for now, turn off clock request. */
4530 if ((bus->clkstate != CLK_PENDING)
4531 && bus->idletime == DHD_IDLE_IMMEDIATE) {
4532 bus->activity = FALSE;
4533 dhdsdio_clkctl(bus, CLK_NONE, FALSE);
4534 }
4535
4536 dhd_os_sdunlock(bus->dhd);
4537
4538 return resched;
4539}
4540
4541bool dhd_bus_dpc(struct dhd_bus *bus)
4542{
4543 bool resched;
4544
4545 /* Call the DPC directly. */
4546 DHD_TRACE(("Calling dhdsdio_dpc() from %s\n", __func__));
4547 resched = dhdsdio_dpc(bus);
4548
4549 return resched;
4550}
4551
4552void dhdsdio_isr(void *arg)
4553{
4554 dhd_bus_t *bus = (dhd_bus_t *) arg;
4555 bcmsdh_info_t *sdh;
4556
4557 DHD_TRACE(("%s: Enter\n", __func__));
4558
4559 if (!bus) {
4560 DHD_ERROR(("%s : bus is null pointer , exit\n", __func__));
4561 return;
4562 }
4563 sdh = bus->sdh;
4564
4565 if (bus->dhd->busstate == DHD_BUS_DOWN) {
4566 DHD_ERROR(("%s : bus is down. we have nothing to do\n",
4567 __func__));
4568 return;
4569 }
4570 /* Count the interrupt call */
4571 bus->intrcount++;
4572 bus->ipend = TRUE;
4573
4574 /* Shouldn't get this interrupt if we're sleeping? */
4575 if (bus->sleeping) {
4576 DHD_ERROR(("INTERRUPT WHILE SLEEPING??\n"));
4577 return;
4578 }
4579
4580 /* Disable additional interrupts (is this needed now)? */
4581 if (bus->intr)
4582 DHD_INTR(("%s: disable SDIO interrupts\n", __func__));
4583 else
4584 DHD_ERROR(("dhdsdio_isr() w/o interrupt configured!\n"));
4585
4586 bcmsdh_intr_disable(sdh);
4587 bus->intdis = TRUE;
4588
4589#if defined(SDIO_ISR_THREAD)
4590 DHD_TRACE(("Calling dhdsdio_dpc() from %s\n", __func__));
4591 while (dhdsdio_dpc(bus))
4592 ;
4593#else
4594 bus->dpc_sched = TRUE;
4595 dhd_sched_dpc(bus->dhd);
4596#endif
4597
4598}
4599
4600#ifdef SDTEST
4601static void dhdsdio_pktgen_init(dhd_bus_t *bus)
4602{
4603 /* Default to specified length, or full range */
4604 if (dhd_pktgen_len) {
4605 bus->pktgen_maxlen = MIN(dhd_pktgen_len, MAX_PKTGEN_LEN);
4606 bus->pktgen_minlen = bus->pktgen_maxlen;
4607 } else {
4608 bus->pktgen_maxlen = MAX_PKTGEN_LEN;
4609 bus->pktgen_minlen = 0;
4610 }
4611 bus->pktgen_len = (uint16) bus->pktgen_minlen;
4612
4613 /* Default to per-watchdog burst with 10s print time */
4614 bus->pktgen_freq = 1;
4615 bus->pktgen_print = 10000 / dhd_watchdog_ms;
4616 bus->pktgen_count = (dhd_pktgen * dhd_watchdog_ms + 999) / 1000;
4617
4618 /* Default to echo mode */
4619 bus->pktgen_mode = DHD_PKTGEN_ECHO;
4620 bus->pktgen_stop = 1;
4621}
4622
4623static void dhdsdio_pktgen(dhd_bus_t *bus)
4624{
4625 void *pkt;
4626 uint8 *data;
4627 uint pktcount;
4628 uint fillbyte;
4629 osl_t *osh = bus->dhd->osh;
4630 uint16 len;
4631
4632 /* Display current count if appropriate */
4633 if (bus->pktgen_print && (++bus->pktgen_ptick >= bus->pktgen_print)) {
4634 bus->pktgen_ptick = 0;
4635 printf("%s: send attempts %d rcvd %d\n",
4636 __func__, bus->pktgen_sent, bus->pktgen_rcvd);
4637 }
4638
4639 /* For recv mode, just make sure dongle has started sending */
4640 if (bus->pktgen_mode == DHD_PKTGEN_RECV) {
4641 if (!bus->pktgen_rcvd)
4642 dhdsdio_sdtest_set(bus, TRUE);
4643 return;
4644 }
4645
4646 /* Otherwise, generate or request the specified number of packets */
4647 for (pktcount = 0; pktcount < bus->pktgen_count; pktcount++) {
4648 /* Stop if total has been reached */
4649 if (bus->pktgen_total
4650 && (bus->pktgen_sent >= bus->pktgen_total)) {
4651 bus->pktgen_count = 0;
4652 break;
4653 }
4654
4655 /* Allocate an appropriate-sized packet */
4656 len = bus->pktgen_len;
4657 if (!(pkt = PKTGET(osh,
4658 (len + SDPCM_HDRLEN + SDPCM_TEST_HDRLEN +
4659 DHD_SDALIGN), TRUE))) {
4660 DHD_ERROR(("%s: PKTGET failed!\n", __func__));
4661 break;
4662 }
4663 PKTALIGN(osh, pkt, (len + SDPCM_HDRLEN + SDPCM_TEST_HDRLEN),
4664 DHD_SDALIGN);
4665 data = (uint8 *) PKTDATA(pkt) + SDPCM_HDRLEN;
4666
4667 /* Write test header cmd and extra based on mode */
4668 switch (bus->pktgen_mode) {
4669 case DHD_PKTGEN_ECHO:
4670 *data++ = SDPCM_TEST_ECHOREQ;
4671 *data++ = (uint8) bus->pktgen_sent;
4672 break;
4673
4674 case DHD_PKTGEN_SEND:
4675 *data++ = SDPCM_TEST_DISCARD;
4676 *data++ = (uint8) bus->pktgen_sent;
4677 break;
4678
4679 case DHD_PKTGEN_RXBURST:
4680 *data++ = SDPCM_TEST_BURST;
4681 *data++ = (uint8) bus->pktgen_count;
4682 break;
4683
4684 default:
4685 DHD_ERROR(("Unrecognized pktgen mode %d\n",
4686 bus->pktgen_mode));
4687 PKTFREE(osh, pkt, TRUE);
4688 bus->pktgen_count = 0;
4689 return;
4690 }
4691
4692 /* Write test header length field */
4693 *data++ = (len >> 0);
4694 *data++ = (len >> 8);
4695
4696 /* Then fill in the remainder -- N/A for burst,
4697 but who cares... */
4698 for (fillbyte = 0; fillbyte < len; fillbyte++)
4699 *data++ =
4700 SDPCM_TEST_FILL(fillbyte, (uint8) bus->pktgen_sent);
4701
4702#ifdef DHD_DEBUG
4703 if (DHD_BYTES_ON() && DHD_DATA_ON()) {
4704 data = (uint8 *) PKTDATA(pkt) + SDPCM_HDRLEN;
4705 prhex("dhdsdio_pktgen: Tx Data", data,
4706 PKTLEN(pkt) - SDPCM_HDRLEN);
4707 }
4708#endif
4709
4710 /* Send it */
4711 if (dhdsdio_txpkt(bus, pkt, SDPCM_TEST_CHANNEL, TRUE)) {
4712 bus->pktgen_fail++;
4713 if (bus->pktgen_stop
4714 && bus->pktgen_stop == bus->pktgen_fail)
4715 bus->pktgen_count = 0;
4716 }
4717 bus->pktgen_sent++;
4718
4719 /* Bump length if not fixed, wrap at max */
4720 if (++bus->pktgen_len > bus->pktgen_maxlen)
4721 bus->pktgen_len = (uint16) bus->pktgen_minlen;
4722
4723 /* Special case for burst mode: just send one request! */
4724 if (bus->pktgen_mode == DHD_PKTGEN_RXBURST)
4725 break;
4726 }
4727}
4728
4729static void dhdsdio_sdtest_set(dhd_bus_t *bus, bool start)
4730{
4731 void *pkt;
4732 uint8 *data;
4733 osl_t *osh = bus->dhd->osh;
4734
4735 /* Allocate the packet */
4736 if (!
4737 (pkt =
4738 PKTGET(osh, SDPCM_HDRLEN + SDPCM_TEST_HDRLEN + DHD_SDALIGN,
4739 TRUE))) {
4740 DHD_ERROR(("%s: PKTGET failed!\n", __func__));
4741 return;
4742 }
4743 PKTALIGN(osh, pkt, (SDPCM_HDRLEN + SDPCM_TEST_HDRLEN), DHD_SDALIGN);
4744 data = (uint8 *) PKTDATA(pkt) + SDPCM_HDRLEN;
4745
4746 /* Fill in the test header */
4747 *data++ = SDPCM_TEST_SEND;
4748 *data++ = start;
4749 *data++ = (bus->pktgen_maxlen >> 0);
4750 *data++ = (bus->pktgen_maxlen >> 8);
4751
4752 /* Send it */
4753 if (dhdsdio_txpkt(bus, pkt, SDPCM_TEST_CHANNEL, TRUE))
4754 bus->pktgen_fail++;
4755}
4756
4757static void dhdsdio_testrcv(dhd_bus_t *bus, void *pkt, uint seq)
4758{
4759 osl_t *osh = bus->dhd->osh;
4760 uint8 *data;
4761 uint pktlen;
4762
4763 uint8 cmd;
4764 uint8 extra;
4765 uint16 len;
4766 uint16 offset;
4767
4768 /* Check for min length */
4769 pktlen = PKTLEN(pkt);
4770 if (pktlen < SDPCM_TEST_HDRLEN) {
4771 DHD_ERROR(("dhdsdio_restrcv: toss runt frame, pktlen %d\n",
4772 pktlen));
4773 PKTFREE(osh, pkt, FALSE);
4774 return;
4775 }
4776
4777 /* Extract header fields */
4778 data = PKTDATA(pkt);
4779 cmd = *data++;
4780 extra = *data++;
4781 len = *data++;
4782 len += *data++ << 8;
4783
4784 /* Check length for relevant commands */
4785 if (cmd == SDPCM_TEST_DISCARD || cmd == SDPCM_TEST_ECHOREQ
4786 || cmd == SDPCM_TEST_ECHORSP) {
4787 if (pktlen != len + SDPCM_TEST_HDRLEN) {
4788 DHD_ERROR(("dhdsdio_testrcv: frame length mismatch, "
4789 "pktlen %d seq %d" " cmd %d extra %d len %d\n",
4790 pktlen, seq, cmd, extra, len));
4791 PKTFREE(osh, pkt, FALSE);
4792 return;
4793 }
4794 }
4795
4796 /* Process as per command */
4797 switch (cmd) {
4798 case SDPCM_TEST_ECHOREQ:
4799 /* Rx->Tx turnaround ok (even on NDIS w/current
4800 implementation) */
4801 *(uint8 *) (PKTDATA(pkt)) = SDPCM_TEST_ECHORSP;
4802 if (dhdsdio_txpkt(bus, pkt, SDPCM_TEST_CHANNEL, TRUE) == 0) {
4803 bus->pktgen_sent++;
4804 } else {
4805 bus->pktgen_fail++;
4806 PKTFREE(osh, pkt, FALSE);
4807 }
4808 bus->pktgen_rcvd++;
4809 break;
4810
4811 case SDPCM_TEST_ECHORSP:
4812 if (bus->ext_loop) {
4813 PKTFREE(osh, pkt, FALSE);
4814 bus->pktgen_rcvd++;
4815 break;
4816 }
4817
4818 for (offset = 0; offset < len; offset++, data++) {
4819 if (*data != SDPCM_TEST_FILL(offset, extra)) {
4820 DHD_ERROR(("dhdsdio_testrcv: echo data mismatch: " "offset %d (len %d) expect 0x%02x rcvd 0x%02x\n",
4821 offset, len,
4822 SDPCM_TEST_FILL(offset, extra), *data));
4823 break;
4824 }
4825 }
4826 PKTFREE(osh, pkt, FALSE);
4827 bus->pktgen_rcvd++;
4828 break;
4829
4830 case SDPCM_TEST_DISCARD:
4831 PKTFREE(osh, pkt, FALSE);
4832 bus->pktgen_rcvd++;
4833 break;
4834
4835 case SDPCM_TEST_BURST:
4836 case SDPCM_TEST_SEND:
4837 default:
4838 DHD_INFO(("dhdsdio_testrcv: unsupported or unknown command, "
4839 "pktlen %d seq %d" " cmd %d extra %d len %d\n",
4840 pktlen, seq, cmd, extra, len));
4841 PKTFREE(osh, pkt, FALSE);
4842 break;
4843 }
4844
4845 /* For recv mode, stop at limie (and tell dongle to stop sending) */
4846 if (bus->pktgen_mode == DHD_PKTGEN_RECV) {
4847 if (bus->pktgen_total
4848 && (bus->pktgen_rcvd >= bus->pktgen_total)) {
4849 bus->pktgen_count = 0;
4850 dhdsdio_sdtest_set(bus, FALSE);
4851 }
4852 }
4853}
4854#endif /* SDTEST */
4855
4856extern bool dhd_bus_watchdog(dhd_pub_t *dhdp)
4857{
4858 dhd_bus_t *bus;
4859
4860 DHD_TIMER(("%s: Enter\n", __func__));
4861
4862 bus = dhdp->bus;
4863
4864 if (bus->dhd->dongle_reset)
4865 return FALSE;
4866
4867 /* Ignore the timer if simulating bus down */
4868 if (bus->sleeping)
4869 return FALSE;
4870
4871 dhd_os_sdlock(bus->dhd);
4872
4873 /* Poll period: check device if appropriate. */
4874 if (bus->poll && (++bus->polltick >= bus->pollrate)) {
4875 uint32 intstatus = 0;
4876
4877 /* Reset poll tick */
4878 bus->polltick = 0;
4879
4880 /* Check device if no interrupts */
4881 if (!bus->intr || (bus->intrcount == bus->lastintrs)) {
4882
4883 if (!bus->dpc_sched) {
4884 uint8 devpend;
4885 devpend = bcmsdh_cfg_read(bus->sdh, SDIO_FUNC_0,
4886 SDIOD_CCCR_INTPEND,
4887 NULL);
4888 intstatus =
4889 devpend & (INTR_STATUS_FUNC1 |
4890 INTR_STATUS_FUNC2);
4891 }
4892
4893 /* If there is something, make like the ISR and
4894 schedule the DPC */
4895 if (intstatus) {
4896 bus->pollcnt++;
4897 bus->ipend = TRUE;
4898 if (bus->intr)
4899 bcmsdh_intr_disable(bus->sdh);
4900
4901 bus->dpc_sched = TRUE;
4902 dhd_sched_dpc(bus->dhd);
4903
4904 }
4905 }
4906
4907 /* Update interrupt tracking */
4908 bus->lastintrs = bus->intrcount;
4909 }
4910#ifdef DHD_DEBUG
4911 /* Poll for console output periodically */
4912 if (dhdp->busstate == DHD_BUS_DATA && dhd_console_ms != 0) {
4913 bus->console.count += dhd_watchdog_ms;
4914 if (bus->console.count >= dhd_console_ms) {
4915 bus->console.count -= dhd_console_ms;
4916 /* Make sure backplane clock is on */
4917 dhdsdio_clkctl(bus, CLK_AVAIL, FALSE);
4918 if (dhdsdio_readconsole(bus) < 0)
4919 dhd_console_ms = 0; /* On error,
4920 stop trying */
4921 }
4922 }
4923#endif /* DHD_DEBUG */
4924
4925#ifdef SDTEST
4926 /* Generate packets if configured */
4927 if (bus->pktgen_count && (++bus->pktgen_tick >= bus->pktgen_freq)) {
4928 /* Make sure backplane clock is on */
4929 dhdsdio_clkctl(bus, CLK_AVAIL, FALSE);
4930 bus->pktgen_tick = 0;
4931 dhdsdio_pktgen(bus);
4932 }
4933#endif
4934
4935 /* On idle timeout clear activity flag and/or turn off clock */
4936 if ((bus->idletime > 0) && (bus->clkstate == CLK_AVAIL)) {
4937 if (++bus->idlecount >= bus->idletime) {
4938 bus->idlecount = 0;
4939 if (bus->activity) {
4940 bus->activity = FALSE;
4941 dhd_os_wd_timer(bus->dhd, dhd_watchdog_ms);
4942 } else {
4943 dhdsdio_clkctl(bus, CLK_NONE, FALSE);
4944 }
4945 }
4946 }
4947
4948 dhd_os_sdunlock(bus->dhd);
4949
4950 return bus->ipend;
4951}
4952
4953#ifdef DHD_DEBUG
4954extern int dhd_bus_console_in(dhd_pub_t *dhdp, uchar *msg, uint msglen)
4955{
4956 dhd_bus_t *bus = dhdp->bus;
4957 uint32 addr, val;
4958 int rv;
4959 void *pkt;
4960
4961 /* Address could be zero if CONSOLE := 0 in dongle Makefile */
4962 if (bus->console_addr == 0)
4963 return BCME_UNSUPPORTED;
4964
4965 /* Exclusive bus access */
4966 dhd_os_sdlock(bus->dhd);
4967
4968 /* Don't allow input if dongle is in reset */
4969 if (bus->dhd->dongle_reset) {
4970 dhd_os_sdunlock(bus->dhd);
4971 return BCME_NOTREADY;
4972 }
4973
4974 /* Request clock to allow SDIO accesses */
4975 BUS_WAKE(bus);
4976 /* No pend allowed since txpkt is called later, ht clk has to be on */
4977 dhdsdio_clkctl(bus, CLK_AVAIL, FALSE);
4978
4979 /* Zero cbuf_index */
4980 addr = bus->console_addr + OFFSETOF(hndrte_cons_t, cbuf_idx);
4981 val = htol32(0);
4982 if ((rv =
4983 dhdsdio_membytes(bus, TRUE, addr, (uint8 *)&val,
4984 sizeof(val))) < 0)
4985 goto done;
4986
4987 /* Write message into cbuf */
4988 addr = bus->console_addr + OFFSETOF(hndrte_cons_t, cbuf);
4989 if ((rv = dhdsdio_membytes(bus, TRUE, addr, (uint8 *)msg, msglen)) < 0)
4990 goto done;
4991
4992 /* Write length into vcons_in */
4993 addr = bus->console_addr + OFFSETOF(hndrte_cons_t, vcons_in);
4994 val = htol32(msglen);
4995 if ((rv =
4996 dhdsdio_membytes(bus, TRUE, addr, (uint8 *)&val,
4997 sizeof(val))) < 0)
4998 goto done;
4999
5000 /* Bump dongle by sending an empty event pkt.
5001 * sdpcm_sendup (RX) checks for virtual console input.
5002 */
5003 if (((pkt = PKTGET(bus->dhd->osh, 4 + SDPCM_RESERVE, TRUE)) != NULL) &&
5004 bus->clkstate == CLK_AVAIL)
5005 dhdsdio_txpkt(bus, pkt, SDPCM_EVENT_CHANNEL, TRUE);
5006
5007done:
5008 if ((bus->idletime == DHD_IDLE_IMMEDIATE) && !bus->dpc_sched) {
5009 bus->activity = FALSE;
5010 dhdsdio_clkctl(bus, CLK_NONE, TRUE);
5011 }
5012
5013 dhd_os_sdunlock(bus->dhd);
5014
5015 return rv;
5016}
5017#endif /* DHD_DEBUG */
5018
5019#ifdef DHD_DEBUG
5020static void dhd_dump_cis(uint fn, uint8 *cis)
5021{
5022 uint byte, tag, tdata;
5023 DHD_INFO(("Function %d CIS:\n", fn));
5024
5025 for (tdata = byte = 0; byte < SBSDIO_CIS_SIZE_LIMIT; byte++) {
5026 if ((byte % 16) == 0)
5027 DHD_INFO((" "));
5028 DHD_INFO(("%02x ", cis[byte]));
5029 if ((byte % 16) == 15)
5030 DHD_INFO(("\n"));
5031 if (!tdata--) {
5032 tag = cis[byte];
5033 if (tag == 0xff)
5034 break;
5035 else if (!tag)
5036 tdata = 0;
5037 else if ((byte + 1) < SBSDIO_CIS_SIZE_LIMIT)
5038 tdata = cis[byte + 1] + 1;
5039 else
5040 DHD_INFO(("]"));
5041 }
5042 }
5043 if ((byte % 16) != 15)
5044 DHD_INFO(("\n"));
5045}
5046#endif /* DHD_DEBUG */
5047
5048static bool dhdsdio_chipmatch(uint16 chipid)
5049{
5050 if (chipid == BCM4325_CHIP_ID)
5051 return TRUE;
5052 if (chipid == BCM4329_CHIP_ID)
5053 return TRUE;
5054 if (chipid == BCM4319_CHIP_ID)
5055 return TRUE;
5056 return FALSE;
5057}
5058
5059static void *dhdsdio_probe(uint16 venid, uint16 devid, uint16 bus_no,
5060 uint16 slot, uint16 func, uint bustype, void *regsva,
5061 osl_t *osh, void *sdh)
5062{
5063 int ret;
5064 dhd_bus_t *bus;
5065
5066 /* Init global variables at run-time, not as part of the declaration.
5067 * This is required to support init/de-init of the driver.
5068 * Initialization
5069 * of globals as part of the declaration results in non-deterministic
5070 * behavior since the value of the globals may be different on the
5071 * first time that the driver is initialized vs subsequent
5072 * initializations.
5073 */
5074 dhd_txbound = DHD_TXBOUND;
5075 dhd_rxbound = DHD_RXBOUND;
5076 dhd_alignctl = TRUE;
5077 sd1idle = TRUE;
5078 dhd_readahead = TRUE;
5079 retrydata = FALSE;
5080 dhd_doflow = FALSE;
5081 dhd_dongle_memsize = 0;
5082 dhd_txminmax = DHD_TXMINMAX;
5083
5084 forcealign = TRUE;
5085
5086 dhd_common_init();
5087
5088 DHD_TRACE(("%s: Enter\n", __func__));
5089 DHD_INFO(("%s: venid 0x%04x devid 0x%04x\n", __func__, venid, devid));
5090
5091 /* We make assumptions about address window mappings */
5092 ASSERT((uintptr) regsva == SI_ENUM_BASE);
5093
5094 /* BCMSDH passes venid and devid based on CIS parsing -- but
5095 * low-power start
5096 * means early parse could fail, so here we should get either an ID
5097 * we recognize OR (-1) indicating we must request power first.
5098 */
5099 /* Check the Vendor ID */
5100 switch (venid) {
5101 case 0x0000:
5102 case VENDOR_BROADCOM:
5103 break;
5104 default:
5105 DHD_ERROR(("%s: unknown vendor: 0x%04x\n", __func__, venid));
5106 return NULL;
5107 }
5108
5109 /* Check the Device ID and make sure it's one that we support */
5110 switch (devid) {
5111 case BCM4325_D11DUAL_ID: /* 4325 802.11a/g id */
5112 case BCM4325_D11G_ID: /* 4325 802.11g 2.4Ghz band id */
5113 case BCM4325_D11A_ID: /* 4325 802.11a 5Ghz band id */
5114 DHD_INFO(("%s: found 4325 Dongle\n", __func__));
5115 break;
5116 case BCM4329_D11NDUAL_ID: /* 4329 802.11n dualband device */
5117 case BCM4329_D11N2G_ID: /* 4329 802.11n 2.4G device */
5118 case BCM4329_D11N5G_ID: /* 4329 802.11n 5G device */
5119 case 0x4329:
5120 DHD_INFO(("%s: found 4329 Dongle\n", __func__));
5121 break;
5122 case BCM4319_D11N_ID: /* 4319 802.11n id */
5123 case BCM4319_D11N2G_ID: /* 4319 802.11n2g id */
5124 case BCM4319_D11N5G_ID: /* 4319 802.11n5g id */
5125 DHD_INFO(("%s: found 4319 Dongle\n", __func__));
5126 break;
5127 case 0:
5128 DHD_INFO(("%s: allow device id 0, will check chip internals\n",
5129 __func__));
5130 break;
5131
5132 default:
5133 DHD_ERROR(("%s: skipping 0x%04x/0x%04x, not a dongle\n",
5134 __func__, venid, devid));
5135 return NULL;
5136 }
5137
5138 if (osh == NULL) {
5139 /* Ask the OS interface part for an OSL handle */
5140 osh = dhd_osl_attach(sdh, DHD_BUS);
5141 if (!osh) {
5142 DHD_ERROR(("%s: osl_attach failed!\n", __func__));
5143 return NULL;
5144 }
5145 }
5146
5147 /* Allocate private bus interface state */
5148 bus = MALLOC(osh, sizeof(dhd_bus_t));
5149 if (!bus) {
5150 DHD_ERROR(("%s: MALLOC of dhd_bus_t failed\n", __func__));
5151 goto fail;
5152 }
5153 bzero(bus, sizeof(dhd_bus_t));
5154 bus->sdh = sdh;
5155 bus->cl_devid = (uint16) devid;
5156 bus->bus = DHD_BUS;
5157 bus->tx_seq = SDPCM_SEQUENCE_WRAP - 1;
5158 bus->usebufpool = FALSE; /* Use bufpool if allocated,
5159 else use locally malloced rxbuf */
5160
5161 /* attempt to attach to the dongle */
5162 if (!(dhdsdio_probe_attach(bus, osh, sdh, regsva, devid))) {
5163 DHD_ERROR(("%s: dhdsdio_probe_attach failed\n", __func__));
5164 goto fail;
5165 }
5166
5167 /* Attach to the dhd/OS/network interface */
5168 bus->dhd = dhd_attach(osh, bus, SDPCM_RESERVE);
5169 if (!bus->dhd) {
5170 DHD_ERROR(("%s: dhd_attach failed\n", __func__));
5171 goto fail;
5172 }
5173
5174 /* Allocate buffers */
5175 if (!(dhdsdio_probe_malloc(bus, osh, sdh))) {
5176 DHD_ERROR(("%s: dhdsdio_probe_malloc failed\n", __func__));
5177 goto fail;
5178 }
5179
5180 if (!(dhdsdio_probe_init(bus, osh, sdh))) {
5181 DHD_ERROR(("%s: dhdsdio_probe_init failed\n", __func__));
5182 goto fail;
5183 }
5184
5185 /* Register interrupt callback, but mask it (not operational yet). */
5186 DHD_INTR(("%s: disable SDIO interrupts (not interested yet)\n",
5187 __func__));
5188 bcmsdh_intr_disable(sdh);
5189 ret = bcmsdh_intr_reg(sdh, dhdsdio_isr, bus);
5190 if (ret != 0) {
5191 DHD_ERROR(("%s: FAILED: bcmsdh_intr_reg returned %d\n",
5192 __func__, ret));
5193 goto fail;
5194 }
5195 DHD_INTR(("%s: registered SDIO interrupt function ok\n", __func__));
5196
5197 DHD_INFO(("%s: completed!!\n", __func__));
5198
5199 /* if firmware path present try to download and bring up bus */
5200 if ((ret = dhd_bus_start(bus->dhd)) != 0) {
5201 if (ret == BCME_NOTUP) {
5202 DHD_ERROR(("%s: dongle is not responding\n", __func__));
5203 goto fail;
5204 }
5205 }
5206 /* Ok, have the per-port tell the stack we're open for business */
5207 if (dhd_net_attach(bus->dhd, 0) != 0) {
5208 DHD_ERROR(("%s: Net attach failed!!\n", __func__));
5209 goto fail;
5210 }
5211
5212 return bus;
5213
5214fail:
5215 dhdsdio_release(bus, osh);
5216 return NULL;
5217}
5218
5219static bool
5220dhdsdio_probe_attach(struct dhd_bus *bus, osl_t *osh, void *sdh, void *regsva,
5221 uint16 devid)
5222{
5223 uint8 clkctl = 0;
5224 int err = 0;
5225
5226 bus->alp_only = TRUE;
5227
5228 /* Return the window to backplane enumeration space for core access */
5229 if (dhdsdio_set_siaddr_window(bus, SI_ENUM_BASE))
5230 DHD_ERROR(("%s: FAILED to return to SI_ENUM_BASE\n", __func__));
5231
5232#ifdef DHD_DEBUG
5233 printf("F1 signature read @0x18000000=0x%4x\n",
5234 bcmsdh_reg_read(bus->sdh, SI_ENUM_BASE, 4));
5235
5236#endif /* DHD_DEBUG */
5237
5238 /* Force PLL off until si_attach() programs PLL control regs */
5239
5240 bcmsdh_cfg_write(sdh, SDIO_FUNC_1, SBSDIO_FUNC1_CHIPCLKCSR,
5241 DHD_INIT_CLKCTL1, &err);
5242 if (!err)
5243 clkctl =
5244 bcmsdh_cfg_read(sdh, SDIO_FUNC_1, SBSDIO_FUNC1_CHIPCLKCSR,
5245 &err);
5246
5247 if (err || ((clkctl & ~SBSDIO_AVBITS) != DHD_INIT_CLKCTL1)) {
5248 DHD_ERROR(("dhdsdio_probe: ChipClkCSR access: err %d wrote "
5249 "0x%02x read 0x%02x\n",
5250 err, DHD_INIT_CLKCTL1, clkctl));
5251 goto fail;
5252 }
5253#ifdef DHD_DEBUG
5254 if (DHD_INFO_ON()) {
5255 uint fn, numfn;
5256 uint8 *cis[SDIOD_MAX_IOFUNCS];
5257 int err = 0;
5258
5259 numfn = bcmsdh_query_iofnum(sdh);
5260 ASSERT(numfn <= SDIOD_MAX_IOFUNCS);
5261
5262 /* Make sure ALP is available before trying to read CIS */
5263 SPINWAIT(((clkctl = bcmsdh_cfg_read(sdh, SDIO_FUNC_1,
5264 SBSDIO_FUNC1_CHIPCLKCSR,
5265 NULL)),
5266 !SBSDIO_ALPAV(clkctl)), PMU_MAX_TRANSITION_DLY);
5267
5268 /* Now request ALP be put on the bus */
5269 bcmsdh_cfg_write(sdh, SDIO_FUNC_1, SBSDIO_FUNC1_CHIPCLKCSR,
5270 DHD_INIT_CLKCTL2, &err);
5271 OSL_DELAY(65);
5272
5273 for (fn = 0; fn <= numfn; fn++) {
5274 if (!(cis[fn] = MALLOC(osh, SBSDIO_CIS_SIZE_LIMIT))) {
5275 DHD_INFO(("dhdsdio_probe: fn %d cis malloc "
5276 "failed\n", fn));
5277 break;
5278 }
5279 bzero(cis[fn], SBSDIO_CIS_SIZE_LIMIT);
5280
5281 if ((err =
5282 bcmsdh_cis_read(sdh, fn, cis[fn],
5283 SBSDIO_CIS_SIZE_LIMIT))) {
5284 DHD_INFO(("dhdsdio_probe: fn %d cis read "
5285 "err %d\n", fn, err));
5286 MFREE(osh, cis[fn], SBSDIO_CIS_SIZE_LIMIT);
5287 break;
5288 }
5289 dhd_dump_cis(fn, cis[fn]);
5290 }
5291
5292 while (fn-- > 0) {
5293 ASSERT(cis[fn]);
5294 MFREE(osh, cis[fn], SBSDIO_CIS_SIZE_LIMIT);
5295 }
5296
5297 if (err) {
5298 DHD_ERROR(("dhdsdio_probe: error read/parsing CIS\n"));
5299 goto fail;
5300 }
5301 }
5302#endif /* DHD_DEBUG */
5303
5304 /* si_attach() will provide an SI handle and scan the backplane */
5305 bus->sih = si_attach((uint) devid, osh, regsva, DHD_BUS, sdh,
5306 &bus->vars, &bus->varsz);
5307 if (!(bus->sih)) {
5308 DHD_ERROR(("%s: si_attach failed!\n", __func__));
5309 goto fail;
5310 }
5311
5312 bcmsdh_chipinfo(sdh, bus->sih->chip, bus->sih->chiprev);
5313
5314 if (!dhdsdio_chipmatch((uint16) bus->sih->chip)) {
5315 DHD_ERROR(("%s: unsupported chip: 0x%04x\n",
5316 __func__, bus->sih->chip));
5317 goto fail;
5318 }
5319
5320 si_sdiod_drive_strength_init(bus->sih, osh, dhd_sdiod_drive_strength);
5321
5322 /* Get info on the ARM and SOCRAM cores... */
5323 if (!DHD_NOPMU(bus)) {
5324 if ((si_setcore(bus->sih, ARM7S_CORE_ID, 0)) ||
5325 (si_setcore(bus->sih, ARMCM3_CORE_ID, 0))) {
5326 bus->armrev = si_corerev(bus->sih);
5327 } else {
5328 DHD_ERROR(("%s: failed to find ARM core!\n", __func__));
5329 goto fail;
5330 }
5331 bus->orig_ramsize = si_socram_size(bus->sih);
5332 if (!(bus->orig_ramsize)) {
5333 DHD_ERROR(("%s: failed to find SOCRAM memory!\n",
5334 __func__));
5335 goto fail;
5336 }
5337 bus->ramsize = bus->orig_ramsize;
5338 if (dhd_dongle_memsize)
5339 dhd_dongle_setmemsize(bus, dhd_dongle_memsize);
5340
5341 DHD_ERROR(("DHD: dongle ram size is set to %d(orig %d)\n",
5342 bus->ramsize, bus->orig_ramsize));
5343 }
5344
5345 /* ...but normally deal with the SDPCMDEV core */
5346 if (!(bus->regs = si_setcore(bus->sih, PCMCIA_CORE_ID, 0)) &&
5347 !(bus->regs = si_setcore(bus->sih, SDIOD_CORE_ID, 0))) {
5348 DHD_ERROR(("%s: failed to find SDIODEV core!\n", __func__));
5349 goto fail;
5350 }
5351 bus->sdpcmrev = si_corerev(bus->sih);
5352
5353 /* Set core control so an SDIO reset does a backplane reset */
5354 OR_REG(osh, &bus->regs->corecontrol, CC_BPRESEN);
5355
5356 pktq_init(&bus->txq, (PRIOMASK + 1), QLEN);
5357
5358 /* Locate an appropriately-aligned portion of hdrbuf */
5359 bus->rxhdr = (uint8 *) ROUNDUP((uintptr)&bus->hdrbuf[0], DHD_SDALIGN);
5360
5361 /* Set the poll and/or interrupt flags */
5362 bus->intr = (bool) dhd_intr;
5363 if ((bus->poll = (bool) dhd_poll))
5364 bus->pollrate = 1;
5365
5366 return TRUE;
5367
5368fail:
5369 return FALSE;
5370}
5371
5372static bool dhdsdio_probe_malloc(dhd_bus_t *bus, osl_t *osh, void *sdh)
5373{
5374 DHD_TRACE(("%s: Enter\n", __func__));
5375
5376#ifndef DHD_USE_STATIC_BUF
5377 if (bus->dhd->maxctl) {
5378 bus->rxblen =
5379 ROUNDUP((bus->dhd->maxctl + SDPCM_HDRLEN),
5380 ALIGNMENT) + DHD_SDALIGN;
5381 bus->rxbuf = MALLOC(osh, bus->rxblen);
5382 if (!(bus->rxbuf)) {
5383 DHD_ERROR(("%s: MALLOC of %d-byte rxbuf failed\n",
5384 __func__, bus->rxblen));
5385 goto fail;
5386 }
5387 }
5388
5389 /* Allocate buffer to receive glomed packet */
5390 bus->databuf = MALLOC(osh, MAX_DATA_BUF);
5391 if (!(bus->databuf)) {
5392 DHD_ERROR(("%s: MALLOC of %d-byte databuf failed\n",
5393 __func__, MAX_DATA_BUF));
5394 /* release rxbuf which was already located as above */
5395 if (!bus->rxblen)
5396 MFREE(osh, bus->rxbuf, bus->rxblen);
5397 goto fail;
5398 }
5399#else
5400 if (bus->dhd->maxctl) {
5401 bus->rxblen =
5402 ROUNDUP((bus->dhd->maxctl + SDPCM_HDRLEN),
5403 ALIGNMENT) + DHD_SDALIGN;
5404 bus->rxbuf = dhd_os_prealloc(DHD_PREALLOC_RXBUF, bus->rxblen);
5405 if (!(bus->rxbuf)) {
5406 DHD_ERROR(("%s: MALLOC of %d-byte rxbuf failed\n",
5407 __func__, bus->rxblen));
5408 goto fail;
5409 }
5410 }
5411 /* Allocate buffer to receive glomed packet */
5412 bus->databuf = dhd_os_prealloc(DHD_PREALLOC_DATABUF, MAX_DATA_BUF);
5413 if (!(bus->databuf)) {
5414 DHD_ERROR(("%s: MALLOC of %d-byte databuf failed\n",
5415 __func__, MAX_DATA_BUF));
5416 goto fail;
5417 }
5418#endif /* DHD_USE_STATIC_BUF */
5419
5420 /* Align the buffer */
5421 if ((uintptr) bus->databuf % DHD_SDALIGN)
5422 bus->dataptr =
5423 bus->databuf + (DHD_SDALIGN -
5424 ((uintptr) bus->databuf % DHD_SDALIGN));
5425 else
5426 bus->dataptr = bus->databuf;
5427
5428 return TRUE;
5429
5430fail:
5431 return FALSE;
5432}
5433
5434static bool dhdsdio_probe_init(dhd_bus_t *bus, osl_t *osh, void *sdh)
5435{
5436 int32 fnum;
5437
5438 DHD_TRACE(("%s: Enter\n", __func__));
5439
5440#ifdef SDTEST
5441 dhdsdio_pktgen_init(bus);
5442#endif /* SDTEST */
5443
5444 /* Disable F2 to clear any intermediate frame state on the dongle */
5445 bcmsdh_cfg_write(sdh, SDIO_FUNC_0, SDIOD_CCCR_IOEN, SDIO_FUNC_ENABLE_1,
5446 NULL);
5447
5448 bus->dhd->busstate = DHD_BUS_DOWN;
5449 bus->sleeping = FALSE;
5450 bus->rxflow = FALSE;
5451 bus->prev_rxlim_hit = 0;
5452
5453 /* Done with backplane-dependent accesses, can drop clock... */
5454 bcmsdh_cfg_write(sdh, SDIO_FUNC_1, SBSDIO_FUNC1_CHIPCLKCSR, 0, NULL);
5455
5456 /* ...and initialize clock/power states */
5457 bus->clkstate = CLK_SDONLY;
5458 bus->idletime = (int32) dhd_idletime;
5459 bus->idleclock = DHD_IDLE_ACTIVE;
5460
5461 /* Query the SD clock speed */
5462 if (bcmsdh_iovar_op(sdh, "sd_divisor", NULL, 0,
5463 &bus->sd_divisor, sizeof(int32),
5464 FALSE) != BCME_OK) {
5465 DHD_ERROR(("%s: fail on %s get\n", __func__, "sd_divisor"));
5466 bus->sd_divisor = -1;
5467 } else {
5468 DHD_INFO(("%s: Initial value for %s is %d\n",
5469 __func__, "sd_divisor", bus->sd_divisor));
5470 }
5471
5472 /* Query the SD bus mode */
5473 if (bcmsdh_iovar_op(sdh, "sd_mode", NULL, 0,
5474 &bus->sd_mode, sizeof(int32), FALSE) != BCME_OK) {
5475 DHD_ERROR(("%s: fail on %s get\n", __func__, "sd_mode"));
5476 bus->sd_mode = -1;
5477 } else {
5478 DHD_INFO(("%s: Initial value for %s is %d\n",
5479 __func__, "sd_mode", bus->sd_mode));
5480 }
5481
5482 /* Query the F2 block size, set roundup accordingly */
5483 fnum = 2;
5484 if (bcmsdh_iovar_op(sdh, "sd_blocksize", &fnum, sizeof(int32),
5485 &bus->blocksize, sizeof(int32), FALSE) != BCME_OK) {
5486 bus->blocksize = 0;
5487 DHD_ERROR(("%s: fail on %s get\n", __func__, "sd_blocksize"));
5488 } else {
5489 DHD_INFO(("%s: Initial value for %s is %d\n",
5490 __func__, "sd_blocksize", bus->blocksize));
5491 }
5492 bus->roundup = MIN(max_roundup, bus->blocksize);
5493
5494 /* Query if bus module supports packet chaining,
5495 default to use if supported */
5496 if (bcmsdh_iovar_op(sdh, "sd_rxchain", NULL, 0,
5497 &bus->sd_rxchain, sizeof(int32),
5498 FALSE) != BCME_OK) {
5499 bus->sd_rxchain = FALSE;
5500 } else {
5501 DHD_INFO(("%s: bus module (through bcmsdh API) %s chaining\n",
5502 __func__,
5503 (bus->sd_rxchain ? "supports" : "does not support")));
5504 }
5505 bus->use_rxchain = (bool) bus->sd_rxchain;
5506
5507 return TRUE;
5508}
5509
5510bool
5511dhd_bus_download_firmware(struct dhd_bus *bus, osl_t *osh,
5512 char *fw_path, char *nv_path)
5513{
5514 bool ret;
5515 bus->fw_path = fw_path;
5516 bus->nv_path = nv_path;
5517
5518 ret = dhdsdio_download_firmware(bus, osh, bus->sdh);
5519
5520 return ret;
5521}
5522
5523static bool
5524dhdsdio_download_firmware(struct dhd_bus *bus, osl_t *osh, void *sdh)
5525{
5526 bool ret;
5527
5528 /* Download the firmware */
5529 dhdsdio_clkctl(bus, CLK_AVAIL, FALSE);
5530
5531 ret = _dhdsdio_download_firmware(bus) == 0;
5532
5533 dhdsdio_clkctl(bus, CLK_SDONLY, FALSE);
5534
5535 return ret;
5536}
5537
5538/* Detach and free everything */
5539static void dhdsdio_release(dhd_bus_t *bus, osl_t *osh)
5540{
5541 DHD_TRACE(("%s: Enter\n", __func__));
5542
5543 if (bus) {
5544 ASSERT(osh);
5545
5546 /* De-register interrupt handler */
5547 bcmsdh_intr_disable(bus->sdh);
5548 bcmsdh_intr_dereg(bus->sdh);
5549
5550 if (bus->dhd) {
5551
5552 dhdsdio_release_dongle(bus, osh);
5553
5554 dhd_detach(bus->dhd);
5555 bus->dhd = NULL;
5556 }
5557
5558 dhdsdio_release_malloc(bus, osh);
5559
5560 MFREE(osh, bus, sizeof(dhd_bus_t));
5561 }
5562
5563 if (osh)
5564 dhd_osl_detach(osh);
5565
5566 DHD_TRACE(("%s: Disconnected\n", __func__));
5567}
5568
5569static void dhdsdio_release_malloc(dhd_bus_t *bus, osl_t *osh)
5570{
5571 DHD_TRACE(("%s: Enter\n", __func__));
5572
5573 if (bus->dhd && bus->dhd->dongle_reset)
5574 return;
5575
5576 if (bus->rxbuf) {
5577#ifndef DHD_USE_STATIC_BUF
5578 MFREE(osh, bus->rxbuf, bus->rxblen);
5579#endif
5580 bus->rxctl = bus->rxbuf = NULL;
5581 bus->rxlen = 0;
5582 }
5583
5584 if (bus->databuf) {
5585#ifndef DHD_USE_STATIC_BUF
5586 MFREE(osh, bus->databuf, MAX_DATA_BUF);
5587#endif
5588 bus->databuf = NULL;
5589 }
5590}
5591
5592static void dhdsdio_release_dongle(dhd_bus_t *bus, osl_t *osh)
5593{
5594 DHD_TRACE(("%s: Enter\n", __func__));
5595
5596 if (bus->dhd && bus->dhd->dongle_reset)
5597 return;
5598
5599 if (bus->sih) {
5600 dhdsdio_clkctl(bus, CLK_AVAIL, FALSE);
5601#if !defined(BCMLXSDMMC)
5602 si_watchdog(bus->sih, 4);
5603#endif /* !defined(BCMLXSDMMC) */
5604 dhdsdio_clkctl(bus, CLK_NONE, FALSE);
5605 si_detach(bus->sih);
5606 if (bus->vars && bus->varsz)
5607 MFREE(osh, bus->vars, bus->varsz);
5608 bus->vars = NULL;
5609 }
5610
5611 DHD_TRACE(("%s: Disconnected\n", __func__));
5612}
5613
5614static void dhdsdio_disconnect(void *ptr)
5615{
5616 dhd_bus_t *bus = (dhd_bus_t *)ptr;
5617
5618 DHD_TRACE(("%s: Enter\n", __func__));
5619
5620 if (bus) {
5621 ASSERT(bus->dhd);
5622 dhdsdio_release(bus, bus->dhd->osh);
5623 }
5624
5625 DHD_TRACE(("%s: Disconnected\n", __func__));
5626}
5627
5628/* Register/Unregister functions are called by the main DHD entry
5629 * point (e.g. module insertion) to link with the bus driver, in
5630 * order to look for or await the device.
5631 */
5632
5633static bcmsdh_driver_t dhd_sdio = {
5634 dhdsdio_probe,
5635 dhdsdio_disconnect
5636};
5637
5638int dhd_bus_register(void)
5639{
5640 DHD_TRACE(("%s: Enter\n", __func__));
5641
5642 return bcmsdh_register(&dhd_sdio);
5643}
5644
5645void dhd_bus_unregister(void)
5646{
5647 DHD_TRACE(("%s: Enter\n", __func__));
5648
5649 bcmsdh_unregister();
5650}
5651
5652#ifdef BCMEMBEDIMAGE
5653static int dhdsdio_download_code_array(struct dhd_bus *bus)
5654{
5655 int bcmerror = -1;
5656 int offset = 0;
5657
5658 DHD_INFO(("%s: download embedded firmware...\n", __func__));
5659
5660 /* Download image */
5661 while ((offset + MEMBLOCK) < sizeof(dlarray)) {
5662 bcmerror =
5663 dhdsdio_membytes(bus, TRUE, offset, dlarray + offset,
5664 MEMBLOCK);
5665 if (bcmerror) {
5666 DHD_ERROR(("%s: error %d on writing %d membytes at "
5667 "0x%08x\n",
5668 __func__, bcmerror, MEMBLOCK, offset));
5669 goto err;
5670 }
5671
5672 offset += MEMBLOCK;
5673 }
5674
5675 if (offset < sizeof(dlarray)) {
5676 bcmerror = dhdsdio_membytes(bus, TRUE, offset,
5677 dlarray + offset,
5678 sizeof(dlarray) - offset);
5679 if (bcmerror) {
5680 DHD_ERROR(("%s: error %d on writing %d membytes at "
5681 "0x%08x\n", __func__, bcmerror,
5682 sizeof(dlarray) - offset, offset));
5683 goto err;
5684 }
5685 }
5686#ifdef DHD_DEBUG
5687 /* Upload and compare the downloaded code */
5688 {
5689 unsigned char *ularray;
5690
5691 ularray = MALLOC(bus->dhd->osh, bus->ramsize);
5692 /* Upload image to verify downloaded contents. */
5693 offset = 0;
5694 memset(ularray, 0xaa, bus->ramsize);
5695 while ((offset + MEMBLOCK) < sizeof(dlarray)) {
5696 bcmerror =
5697 dhdsdio_membytes(bus, FALSE, offset,
5698 ularray + offset, MEMBLOCK);
5699 if (bcmerror) {
5700 DHD_ERROR(("%s: error %d on reading %d membytes"
5701 " at 0x%08x\n",
5702 __func__, bcmerror, MEMBLOCK, offset));
5703 goto err;
5704 }
5705
5706 offset += MEMBLOCK;
5707 }
5708
5709 if (offset < sizeof(dlarray)) {
5710 bcmerror = dhdsdio_membytes(bus, FALSE, offset,
5711 ularray + offset,
5712 sizeof(dlarray) - offset);
5713 if (bcmerror) {
5714 DHD_ERROR(("%s: error %d on reading %d membytes at 0x%08x\n",
5715 __func__, bcmerror,
5716 sizeof(dlarray) - offset, offset));
5717 goto err;
5718 }
5719 }
5720
5721 if (memcmp(dlarray, ularray, sizeof(dlarray))) {
5722 DHD_ERROR(("%s: Downloaded image is corrupted.\n",
5723 __func__));
5724 ASSERT(0);
5725 goto err;
5726 } else
5727 DHD_ERROR(("%s: Download/Upload/Compare succeeded.\n",
5728 __func__));
5729
5730 MFREE(bus->dhd->osh, ularray, bus->ramsize);
5731 }
5732#endif /* DHD_DEBUG */
5733
5734err:
5735 return bcmerror;
5736}
5737#endif /* BCMEMBEDIMAGE */
5738
5739static int dhdsdio_download_code_file(struct dhd_bus *bus, char *fw_path)
5740{
5741 int bcmerror = -1;
5742 int offset = 0;
5743 uint len;
5744 void *image = NULL;
5745 uint8 *memblock = NULL, *memptr;
5746
5747 DHD_INFO(("%s: download firmware %s\n", __func__, fw_path));
5748
5749 image = dhd_os_open_image(fw_path);
5750 if (image == NULL)
5751 goto err;
5752
5753 memptr = memblock = MALLOC(bus->dhd->osh, MEMBLOCK + DHD_SDALIGN);
5754 if (memblock == NULL) {
5755 DHD_ERROR(("%s: Failed to allocate memory %d bytes\n",
5756 __func__, MEMBLOCK));
5757 goto err;
5758 }
5759 if ((uint32) (uintptr) memblock % DHD_SDALIGN)
5760 memptr +=
5761 (DHD_SDALIGN - ((uint32) (uintptr) memblock % DHD_SDALIGN));
5762
5763 /* Download image */
5764 while ((len =
5765 dhd_os_get_image_block((char *)memptr, MEMBLOCK, image))) {
5766 bcmerror = dhdsdio_membytes(bus, TRUE, offset, memptr, len);
5767 if (bcmerror) {
5768 DHD_ERROR(("%s: error %d on writing %d membytes at "
5769 "0x%08x\n", __func__, bcmerror, MEMBLOCK, offset));
5770 goto err;
5771 }
5772
5773 offset += MEMBLOCK;
5774 }
5775
5776err:
5777 if (memblock)
5778 MFREE(bus->dhd->osh, memblock, MEMBLOCK + DHD_SDALIGN);
5779
5780 if (image)
5781 dhd_os_close_image(image);
5782
5783 return bcmerror;
5784}
5785
5786/*
5787 * ProcessVars:Takes a buffer of "<var>=<value>\n" lines read from a file
5788 * and ending in a NUL.
5789 * Removes carriage returns, empty lines, comment lines, and converts
5790 * newlines to NULs.
5791 * Shortens buffer as needed and pads with NULs. End of buffer is marked
5792 * by two NULs.
5793*/
5794
5795static uint process_nvram_vars(char *varbuf, uint len)
5796{
5797 char *dp;
5798 bool findNewline;
5799 int column;
5800 uint buf_len, n;
5801
5802 dp = varbuf;
5803
5804 findNewline = FALSE;
5805 column = 0;
5806
5807 for (n = 0; n < len; n++) {
5808 if (varbuf[n] == 0)
5809 break;
5810 if (varbuf[n] == '\r')
5811 continue;
5812 if (findNewline && varbuf[n] != '\n')
5813 continue;
5814 findNewline = FALSE;
5815 if (varbuf[n] == '#') {
5816 findNewline = TRUE;
5817 continue;
5818 }
5819 if (varbuf[n] == '\n') {
5820 if (column == 0)
5821 continue;
5822 *dp++ = 0;
5823 column = 0;
5824 continue;
5825 }
5826 *dp++ = varbuf[n];
5827 column++;
5828 }
5829 buf_len = dp - varbuf;
5830
5831 while (dp < varbuf + n)
5832 *dp++ = 0;
5833
5834 return buf_len;
5835}
5836
5837/*
5838 EXAMPLE: nvram_array
5839 nvram_arry format:
5840 name=value
5841 Use carriage return at the end of each assignment,
5842 and an empty string with
5843 carriage return at the end of array.
5844
5845 For example:
5846 unsigned char nvram_array[] = {"name1=value1\n",
5847 "name2=value2\n", "\n"};
5848 Hex values start with 0x, and mac addr format: xx:xx:xx:xx:xx:xx.
5849
5850 Search "EXAMPLE: nvram_array" to see how the array is activated.
5851*/
5852
5853void dhd_bus_set_nvram_params(struct dhd_bus *bus, const char *nvram_params)
5854{
5855 bus->nvram_params = nvram_params;
5856}
5857
5858static int dhdsdio_download_nvram(struct dhd_bus *bus)
5859{
5860 int bcmerror = -1;
5861 uint len;
5862 void *image = NULL;
5863 char *memblock = NULL;
5864 char *bufp;
5865 char *nv_path;
5866 bool nvram_file_exists;
5867
5868 nv_path = bus->nv_path;
5869
5870 nvram_file_exists = ((nv_path != NULL) && (nv_path[0] != '\0'));
5871 if (!nvram_file_exists && (bus->nvram_params == NULL))
5872 return 0;
5873
5874 if (nvram_file_exists) {
5875 image = dhd_os_open_image(nv_path);
5876 if (image == NULL)
5877 goto err;
5878 }
5879
5880 memblock = MALLOC(bus->dhd->osh, MEMBLOCK);
5881 if (memblock == NULL) {
5882 DHD_ERROR(("%s: Failed to allocate memory %d bytes\n",
5883 __func__, MEMBLOCK));
5884 goto err;
5885 }
5886
5887 /* Download variables */
5888 if (nvram_file_exists) {
5889 len = dhd_os_get_image_block(memblock, MEMBLOCK, image);
5890 } else {
5891 len = strlen(bus->nvram_params);
5892 ASSERT(len <= MEMBLOCK);
5893 if (len > MEMBLOCK)
5894 len = MEMBLOCK;
5895 memcpy(memblock, bus->nvram_params, len);
5896 }
5897
5898 if (len > 0 && len < MEMBLOCK) {
5899 bufp = (char *)memblock;
5900 bufp[len] = 0;
5901 len = process_nvram_vars(bufp, len);
5902 bufp += len;
5903 *bufp++ = 0;
5904 if (len)
5905 bcmerror = dhdsdio_downloadvars(bus, memblock, len + 1);
5906 if (bcmerror) {
5907 DHD_ERROR(("%s: error downloading vars: %d\n",
5908 __func__, bcmerror));
5909 }
5910 } else {
5911 DHD_ERROR(("%s: error reading nvram file: %d\n",
5912 __func__, len));
5913 bcmerror = BCME_SDIO_ERROR;
5914 }
5915
5916err:
5917 if (memblock)
5918 MFREE(bus->dhd->osh, memblock, MEMBLOCK);
5919
5920 if (image)
5921 dhd_os_close_image(image);
5922
5923 return bcmerror;
5924}
5925
5926static int _dhdsdio_download_firmware(struct dhd_bus *bus)
5927{
5928 int bcmerror = -1;
5929
5930 bool embed = FALSE; /* download embedded firmware */
5931 bool dlok = FALSE; /* download firmware succeeded */
5932
5933 /* Out immediately if no image to download */
5934 if ((bus->fw_path == NULL) || (bus->fw_path[0] == '\0')) {
5935#ifdef BCMEMBEDIMAGE
5936 embed = TRUE;
5937#else
5938 return bcmerror;
5939#endif
5940 }
5941
5942 /* Keep arm in reset */
5943 if (dhdsdio_download_state(bus, TRUE)) {
5944 DHD_ERROR(("%s: error placing ARM core in reset\n", __func__));
5945 goto err;
5946 }
5947
5948 /* External image takes precedence if specified */
5949 if ((bus->fw_path != NULL) && (bus->fw_path[0] != '\0')) {
5950 if (dhdsdio_download_code_file(bus, bus->fw_path)) {
5951 DHD_ERROR(("%s: dongle image file download failed\n",
5952 __func__));
5953#ifdef BCMEMBEDIMAGE
5954 embed = TRUE;
5955#else
5956 goto err;
5957#endif
5958 } else {
5959 embed = FALSE;
5960 dlok = TRUE;
5961 }
5962 }
5963#ifdef BCMEMBEDIMAGE
5964 if (embed) {
5965 if (dhdsdio_download_code_array(bus)) {
5966 DHD_ERROR(("%s: dongle image array download failed\n",
5967 __func__));
5968 goto err;
5969 } else {
5970 dlok = TRUE;
5971 }
5972 }
5973#endif
5974 if (!dlok) {
5975 DHD_ERROR(("%s: dongle image download failed\n", __func__));
5976 goto err;
5977 }
5978
5979 /* EXAMPLE: nvram_array */
5980 /* If a valid nvram_arry is specified as above, it can be passed
5981 down to dongle */
5982 /* dhd_bus_set_nvram_params(bus, (char *)&nvram_array); */
5983
5984 /* External nvram takes precedence if specified */
5985 if (dhdsdio_download_nvram(bus)) {
5986 DHD_ERROR(("%s: dongle nvram file download failed\n",
5987 __func__));
5988 }
5989
5990 /* Take arm out of reset */
5991 if (dhdsdio_download_state(bus, FALSE)) {
5992 DHD_ERROR(("%s: error getting out of ARM core reset\n",
5993 __func__));
5994 goto err;
5995 }
5996
5997 bcmerror = 0;
5998
5999err:
6000 return bcmerror;
6001}
6002
6003static int
6004dhd_bcmsdh_recv_buf(dhd_bus_t *bus, uint32 addr, uint fn, uint flags,
6005 uint8 *buf, uint nbytes, void *pkt,
6006 bcmsdh_cmplt_fn_t complete, void *handle)
6007{
6008 int status;
6009
6010 /* 4329: GSPI check */
6011 status =
6012 bcmsdh_recv_buf(bus->sdh, addr, fn, flags, buf, nbytes, pkt,
6013 complete, handle);
6014 return status;
6015}
6016
6017static int
6018dhd_bcmsdh_send_buf(dhd_bus_t *bus, uint32 addr, uint fn, uint flags,
6019 uint8 *buf, uint nbytes, void *pkt,
6020 bcmsdh_cmplt_fn_t complete, void *handle)
6021{
6022 return bcmsdh_send_buf
6023 (bus->sdh, addr, fn, flags, buf, nbytes, pkt, complete,
6024 handle);
6025}
6026
6027uint dhd_bus_chip(struct dhd_bus *bus)
6028{
6029 ASSERT(bus->sih != NULL);
6030 return bus->sih->chip;
6031}
6032
6033void *dhd_bus_pub(struct dhd_bus *bus)
6034{
6035 return bus->dhd;
6036}
6037
6038void *dhd_bus_txq(struct dhd_bus *bus)
6039{
6040 return &bus->txq;
6041}
6042
6043uint dhd_bus_hdrlen(struct dhd_bus *bus)
6044{
6045 return SDPCM_HDRLEN;
6046}
6047
6048int dhd_bus_devreset(dhd_pub_t *dhdp, uint8 flag)
6049{
6050 int bcmerror = 0;
6051 dhd_bus_t *bus;
6052
6053 bus = dhdp->bus;
6054
6055 if (flag == TRUE) {
6056 if (!bus->dhd->dongle_reset) {
6057 /* Expect app to have torn down any
6058 connection before calling */
6059 /* Stop the bus, disable F2 */
6060 dhd_bus_stop(bus, FALSE);
6061
6062 /* Clean tx/rx buffer pointers,
6063 detach from the dongle */
6064 dhdsdio_release_dongle(bus, bus->dhd->osh);
6065
6066 bus->dhd->dongle_reset = TRUE;
6067 bus->dhd->up = FALSE;
6068
6069 DHD_TRACE(("%s: WLAN OFF DONE\n", __func__));
6070 /* App can now remove power from device */
6071 } else
6072 bcmerror = BCME_SDIO_ERROR;
6073 } else {
6074 /* App must have restored power to device before calling */
6075
6076 DHD_TRACE(("\n\n%s: == WLAN ON ==\n", __func__));
6077
6078 if (bus->dhd->dongle_reset) {
6079 /* Turn on WLAN */
6080 /* Reset SD client */
6081 bcmsdh_reset(bus->sdh);
6082
6083 /* Attempt to re-attach & download */
6084 if (dhdsdio_probe_attach(bus, bus->dhd->osh, bus->sdh,
6085 (uint32 *) SI_ENUM_BASE,
6086 bus->cl_devid)) {
6087 /* Attempt to download binary to the dongle */
6088 if (dhdsdio_probe_init
6089 (bus, bus->dhd->osh, bus->sdh)
6090 && dhdsdio_download_firmware(bus,
6091 bus->dhd->osh,
6092 bus->sdh)) {
6093
6094 /* Re-init bus, enable F2 transfer */
6095 dhd_bus_init((dhd_pub_t *) bus->dhd,
6096 FALSE);
6097
6098#if defined(OOB_INTR_ONLY)
6099 dhd_enable_oob_intr(bus, TRUE);
6100#endif /* defined(OOB_INTR_ONLY) */
6101
6102 bus->dhd->dongle_reset = FALSE;
6103 bus->dhd->up = TRUE;
6104
6105 DHD_TRACE(("%s: WLAN ON DONE\n",
6106 __func__));
6107 } else
6108 bcmerror = BCME_SDIO_ERROR;
6109 } else
6110 bcmerror = BCME_SDIO_ERROR;
6111 } else {
6112 bcmerror = BCME_NOTDOWN;
6113 DHD_ERROR(("%s: Set DEVRESET=FALSE invoked when device "
6114 "is on\n", __func__));
6115 bcmerror = BCME_SDIO_ERROR;
6116 }
6117 }
6118 return bcmerror;
6119}
Linux kernel - Deliverables
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