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staging: brcm80211: cleanup function prototypes in header files
[deliverable/linux.git] / drivers / staging / brcm80211 / brcmsmac / d11.h
CommitLineData
a9533e7e
HP		 1/*
2 * Copyright (c) 2010 Broadcom Corporation
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
11 * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
13 * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
14 * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17#ifndef _D11_H
18#define _D11_H
19
a9533e7e
HP		 20#ifndef WL_RSSI_ANT_MAX
21#define WL_RSSI_ANT_MAX 4 /* max possible rx antennas */
22#elif WL_RSSI_ANT_MAX != 4
23#error "WL_RSSI_ANT_MAX does not match"
24#endif
25
26/* cpp contortions to concatenate w/arg prescan */
27#ifndef PAD
28#define _PADLINE(line) pad ## line
29#define _XSTR(line) _PADLINE(line)
30#define PAD _XSTR(__LINE__)
31#endif
32
33#define BCN_TMPL_LEN 512 /* length of the BCN template area */
34
35/* RX FIFO numbers */
36#define RX_FIFO 0 /* data and ctl frames */
37#define RX_TXSTATUS_FIFO 3 /* RX fifo for tx status packages */
38
39/* TX FIFO numbers using WME Access Classes */
40#define TX_AC_BK_FIFO 0 /* Access Category Background TX FIFO */
41#define TX_AC_BE_FIFO 1 /* Access Category Best-Effort TX FIFO */
42#define TX_AC_VI_FIFO 2 /* Access Class Video TX FIFO */
43#define TX_AC_VO_FIFO 3 /* Access Class Voice TX FIFO */
44#define TX_BCMC_FIFO 4 /* Broadcast/Multicast TX FIFO */
45#define TX_ATIM_FIFO 5 /* TX fifo for ATIM window info */
46
47/* Addr is byte address used by SW; offset is word offset used by uCode */
48
49/* Per AC TX limit settings */
50#define M_AC_TXLMT_BASE_ADDR (0x180 * 2)
51#define M_AC_TXLMT_ADDR(_ac) (M_AC_TXLMT_BASE_ADDR + (2 * (_ac)))
52
53/* Legacy TX FIFO numbers */
54#define TX_DATA_FIFO TX_AC_BE_FIFO
55#define TX_CTL_FIFO TX_AC_VO_FIFO
56
57typedef volatile struct {
66cbd3ab
GKH		 58 u32 intstatus;
59 u32 intmask;
a9533e7e
HP		 60} intctrlregs_t;
61
62/* read: 32-bit register that can be read as 32-bit or as 2 16-bit
63 * write: only low 16b-it half can be written
64 */
65typedef volatile union {
66cbd3ab 66 u32 pmqhostdata; /* read only! */
a9533e7e 67 struct {
7d4df48e
GKH		 68 u16 pmqctrlstatus; /* read/write */
69 u16 PAD;
a9533e7e
HP		 70 } w;
71} pmqreg_t;
72
a9533e7e
HP		 73typedef volatile struct {
74 dma64regs_t dmaxmt; /* dma tx */
75 pio4regs_t piotx; /* pio tx */
76 dma64regs_t dmarcv; /* dma rx */
77 pio4regs_t piorx; /* pio rx */
78} fifo64_t;
79
80/*
81 * Host Interface Registers
82 * - primed from hnd_cores/dot11mac/systemC/registers/ihr.h
83 * - but definitely not complete
84 */
85typedef volatile struct _d11regs {
86 /* Device Control ("semi-standard host registers") */
66cbd3ab
GKH		 87 u32 PAD[3]; /* 0x0 - 0x8 */
88 u32 biststatus; /* 0xC */
89 u32 biststatus2; /* 0x10 */
90 u32 PAD; /* 0x14 */
3746507a 91 u32 gptimer; /* 0x18 */
66cbd3ab 92 u32 usectimer; /* 0x1c *//* for corerev >= 26 */
a9533e7e
HP		 93
94 /* Interrupt Control *//* 0x20 */
95 intctrlregs_t intctrlregs[8];
96
66cbd3ab 97 u32 PAD[40]; /* 0x60 - 0xFC */
a9533e7e 98
66cbd3ab 99 u32 intrcvlazy[4]; /* 0x100 - 0x10C */
a9533e7e 100
66cbd3ab 101 u32 PAD[4]; /* 0x110 - 0x11c */
a9533e7e 102
66cbd3ab
GKH		 103 u32 maccontrol; /* 0x120 */
104 u32 maccommand; /* 0x124 */
105 u32 macintstatus; /* 0x128 */
106 u32 macintmask; /* 0x12C */
a9533e7e
HP		 107
108 /* Transmit Template Access */
66cbd3ab
GKH		 109 u32 tplatewrptr; /* 0x130 */
110 u32 tplatewrdata; /* 0x134 */
111 u32 PAD[2]; /* 0x138 - 0x13C */
a9533e7e
HP		 112
113 /* PMQ registers */
114 pmqreg_t pmqreg; /* 0x140 */
66cbd3ab
GKH		 115 u32 pmqpatl; /* 0x144 */
116 u32 pmqpath; /* 0x148 */
117 u32 PAD; /* 0x14C */
a9533e7e 118
66cbd3ab 119 u32 chnstatus; /* 0x150 */
3746507a
RV		 120 u32 psmdebug; /* 0x154 */
121 u32 phydebug; /* 0x158 */
122 u32 machwcap; /* 0x15C */
a9533e7e
HP		 123
124 /* Extended Internal Objects */
66cbd3ab
GKH		 125 u32 objaddr; /* 0x160 */
126 u32 objdata; /* 0x164 */
127 u32 PAD[2]; /* 0x168 - 0x16c */
a9533e7e 128
66cbd3ab
GKH		 129 u32 frmtxstatus; /* 0x170 */
130 u32 frmtxstatus2; /* 0x174 */
131 u32 PAD[2]; /* 0x178 - 0x17c */
a9533e7e 132
3746507a 133 /* TSF host access */
66cbd3ab
GKH		 134 u32 tsf_timerlow; /* 0x180 */
135 u32 tsf_timerhigh; /* 0x184 */
136 u32 tsf_cfprep; /* 0x188 */
137 u32 tsf_cfpstart; /* 0x18c */
138 u32 tsf_cfpmaxdur32; /* 0x190 */
139 u32 PAD[3]; /* 0x194 - 0x19c */
a9533e7e 140
66cbd3ab
GKH		 141 u32 maccontrol1; /* 0x1a0 */
142 u32 machwcap1; /* 0x1a4 */
143 u32 PAD[14]; /* 0x1a8 - 0x1dc */
a9533e7e 144
3746507a 145 /* Clock control and hardware workarounds*/
66cbd3ab
GKH		 146 u32 clk_ctl_st; /* 0x1e0 */
147 u32 hw_war;
3746507a
RV		 148 u32 d11_phypllctl; /* the phypll request/avail bits are
149 * moved to clk_ctl_st
a9533e7e 150 */
66cbd3ab 151 u32 PAD[5]; /* 0x1ec - 0x1fc */
a9533e7e
HP		 152
153 /* 0x200-0x37F dma/pio registers */
02aed8f3 154 fifo64_t fifo64regs[6];
a9533e7e
HP		 155
156 /* FIFO diagnostic port access */
157 dma32diag_t dmafifo; /* 0x380 - 0x38C */
158
66cbd3ab
GKH		 159 u32 aggfifocnt; /* 0x390 */
160 u32 aggfifodata; /* 0x394 */
161 u32 PAD[16]; /* 0x398 - 0x3d4 */
7d4df48e
GKH		 162 u16 radioregaddr; /* 0x3d8 */
163 u16 radioregdata; /* 0x3da */
a9533e7e 164
3746507a
RV		 165 /*
166 * time delay between the change on rf disable input and
167 * radio shutdown
168 */
66cbd3ab 169 u32 rfdisabledly; /* 0x3DC */
a9533e7e
HP		 170
171 /* PHY register access */
7d4df48e
GKH		 172 u16 phyversion; /* 0x3e0 - 0x0 */
173 u16 phybbconfig; /* 0x3e2 - 0x1 */
174 u16 phyadcbias; /* 0x3e4 - 0x2 Bphy only */
175 u16 phyanacore; /* 0x3e6 - 0x3 pwwrdwn on aphy */
176 u16 phyrxstatus0; /* 0x3e8 - 0x4 */
177 u16 phyrxstatus1; /* 0x3ea - 0x5 */
178 u16 phycrsth; /* 0x3ec - 0x6 */
179 u16 phytxerror; /* 0x3ee - 0x7 */
180 u16 phychannel; /* 0x3f0 - 0x8 */
181 u16 PAD[1]; /* 0x3f2 - 0x9 */
182 u16 phytest; /* 0x3f4 - 0xa */
183 u16 phy4waddr; /* 0x3f6 - 0xb */
184 u16 phy4wdatahi; /* 0x3f8 - 0xc */
185 u16 phy4wdatalo; /* 0x3fa - 0xd */
186 u16 phyregaddr; /* 0x3fc - 0xe */
187 u16 phyregdata; /* 0x3fe - 0xf */
a9533e7e
HP		 188
189 /* IHR *//* 0x400 - 0x7FE */
190
191 /* RXE Block */
7d4df48e
GKH		 192 u16 PAD[3]; /* 0x400 - 0x406 */
193 u16 rcv_fifo_ctl; /* 0x406 */
194 u16 PAD; /* 0x408 - 0x40a */
195 u16 rcv_frm_cnt; /* 0x40a */
196 u16 PAD[4]; /* 0x40a - 0x414 */
197 u16 rssi; /* 0x414 */
198 u16 PAD[5]; /* 0x414 - 0x420 */
199 u16 rcm_ctl; /* 0x420 */
200 u16 rcm_mat_data; /* 0x422 */
201 u16 rcm_mat_mask; /* 0x424 */
202 u16 rcm_mat_dly; /* 0x426 */
203 u16 rcm_cond_mask_l; /* 0x428 */
204 u16 rcm_cond_mask_h; /* 0x42A */
205 u16 rcm_cond_dly; /* 0x42C */
206 u16 PAD[1]; /* 0x42E */
207 u16 ext_ihr_addr; /* 0x430 */
208 u16 ext_ihr_data; /* 0x432 */
209 u16 rxe_phyrs_2; /* 0x434 */
210 u16 rxe_phyrs_3; /* 0x436 */
211 u16 phy_mode; /* 0x438 */
212 u16 rcmta_ctl; /* 0x43a */
213 u16 rcmta_size; /* 0x43c */
214 u16 rcmta_addr0; /* 0x43e */
215 u16 rcmta_addr1; /* 0x440 */
216 u16 rcmta_addr2; /* 0x442 */
217 u16 PAD[30]; /* 0x444 - 0x480 */
a9533e7e
HP		 218
219 /* PSM Block *//* 0x480 - 0x500 */
220
7d4df48e
GKH		 221 u16 PAD; /* 0x480 */
222 u16 psm_maccontrol_h; /* 0x482 */
223 u16 psm_macintstatus_l; /* 0x484 */
224 u16 psm_macintstatus_h; /* 0x486 */
225 u16 psm_macintmask_l; /* 0x488 */
226 u16 psm_macintmask_h; /* 0x48A */
227 u16 PAD; /* 0x48C */
228 u16 psm_maccommand; /* 0x48E */
229 u16 psm_brc; /* 0x490 */
230 u16 psm_phy_hdr_param; /* 0x492 */
231 u16 psm_postcard; /* 0x494 */
232 u16 psm_pcard_loc_l; /* 0x496 */
233 u16 psm_pcard_loc_h; /* 0x498 */
234 u16 psm_gpio_in; /* 0x49A */
235 u16 psm_gpio_out; /* 0x49C */
236 u16 psm_gpio_oe; /* 0x49E */
237
238 u16 psm_bred_0; /* 0x4A0 */
239 u16 psm_bred_1; /* 0x4A2 */
240 u16 psm_bred_2; /* 0x4A4 */
241 u16 psm_bred_3; /* 0x4A6 */
242 u16 psm_brcl_0; /* 0x4A8 */
243 u16 psm_brcl_1; /* 0x4AA */
244 u16 psm_brcl_2; /* 0x4AC */
245 u16 psm_brcl_3; /* 0x4AE */
246 u16 psm_brpo_0; /* 0x4B0 */
247 u16 psm_brpo_1; /* 0x4B2 */
248 u16 psm_brpo_2; /* 0x4B4 */
249 u16 psm_brpo_3; /* 0x4B6 */
250 u16 psm_brwk_0; /* 0x4B8 */
251 u16 psm_brwk_1; /* 0x4BA */
252 u16 psm_brwk_2; /* 0x4BC */
253 u16 psm_brwk_3; /* 0x4BE */
254
255 u16 psm_base_0; /* 0x4C0 */
256 u16 psm_base_1; /* 0x4C2 */
257 u16 psm_base_2; /* 0x4C4 */
258 u16 psm_base_3; /* 0x4C6 */
259 u16 psm_base_4; /* 0x4C8 */
260 u16 psm_base_5; /* 0x4CA */
261 u16 psm_base_6; /* 0x4CC */
262 u16 psm_pc_reg_0; /* 0x4CE */
263 u16 psm_pc_reg_1; /* 0x4D0 */
264 u16 psm_pc_reg_2; /* 0x4D2 */
265 u16 psm_pc_reg_3; /* 0x4D4 */
266 u16 PAD[0xD]; /* 0x4D6 - 0x4DE */
267 u16 psm_corectlsts; /* 0x4f0 *//* Corerev >= 13 */
268 u16 PAD[0x7]; /* 0x4f2 - 0x4fE */
a9533e7e
HP		 269
270 /* TXE0 Block *//* 0x500 - 0x580 */
7d4df48e
GKH		 271 u16 txe_ctl; /* 0x500 */
272 u16 txe_aux; /* 0x502 */
273 u16 txe_ts_loc; /* 0x504 */
274 u16 txe_time_out; /* 0x506 */
275 u16 txe_wm_0; /* 0x508 */
276 u16 txe_wm_1; /* 0x50A */
277 u16 txe_phyctl; /* 0x50C */
278 u16 txe_status; /* 0x50E */
279 u16 txe_mmplcp0; /* 0x510 */
280 u16 txe_mmplcp1; /* 0x512 */
281 u16 txe_phyctl1; /* 0x514 */
282
283 u16 PAD[0x05]; /* 0x510 - 0x51E */
a9533e7e
HP		 284
285 /* Transmit control */
7d4df48e
GKH		 286 u16 xmtfifodef; /* 0x520 */
287 u16 xmtfifo_frame_cnt; /* 0x522 *//* Corerev >= 16 */
288 u16 xmtfifo_byte_cnt; /* 0x524 *//* Corerev >= 16 */
289 u16 xmtfifo_head; /* 0x526 *//* Corerev >= 16 */
290 u16 xmtfifo_rd_ptr; /* 0x528 *//* Corerev >= 16 */
291 u16 xmtfifo_wr_ptr; /* 0x52A *//* Corerev >= 16 */
292 u16 xmtfifodef1; /* 0x52C *//* Corerev >= 16 */
293
294 u16 PAD[0x09]; /* 0x52E - 0x53E */
295
296 u16 xmtfifocmd; /* 0x540 */
297 u16 xmtfifoflush; /* 0x542 */
298 u16 xmtfifothresh; /* 0x544 */
299 u16 xmtfifordy; /* 0x546 */
300 u16 xmtfifoprirdy; /* 0x548 */
301 u16 xmtfiforqpri; /* 0x54A */
302 u16 xmttplatetxptr; /* 0x54C */
303 u16 PAD; /* 0x54E */
304 u16 xmttplateptr; /* 0x550 */
305 u16 smpl_clct_strptr; /* 0x552 *//* Corerev >= 22 */
306 u16 smpl_clct_stpptr; /* 0x554 *//* Corerev >= 22 */
307 u16 smpl_clct_curptr; /* 0x556 *//* Corerev >= 22 */
308 u16 PAD[0x04]; /* 0x558 - 0x55E */
309 u16 xmttplatedatalo; /* 0x560 */
310 u16 xmttplatedatahi; /* 0x562 */
311
312 u16 PAD[2]; /* 0x564 - 0x566 */
313
314 u16 xmtsel; /* 0x568 */
315 u16 xmttxcnt; /* 0x56A */
316 u16 xmttxshmaddr; /* 0x56C */
317
318 u16 PAD[0x09]; /* 0x56E - 0x57E */
a9533e7e
HP		 319
320 /* TXE1 Block */
7d4df48e 321 u16 PAD[0x40]; /* 0x580 - 0x5FE */
a9533e7e
HP		 322
323 /* TSF Block */
7d4df48e
GKH		 324 u16 PAD[0X02]; /* 0x600 - 0x602 */
325 u16 tsf_cfpstrt_l; /* 0x604 */
326 u16 tsf_cfpstrt_h; /* 0x606 */
327 u16 PAD[0X05]; /* 0x608 - 0x610 */
328 u16 tsf_cfppretbtt; /* 0x612 */
329 u16 PAD[0XD]; /* 0x614 - 0x62C */
330 u16 tsf_clk_frac_l; /* 0x62E */
331 u16 tsf_clk_frac_h; /* 0x630 */
332 u16 PAD[0X14]; /* 0x632 - 0x658 */
333 u16 tsf_random; /* 0x65A */
334 u16 PAD[0x05]; /* 0x65C - 0x664 */
3746507a 335 /* GPTimer 2 registers */
7d4df48e
GKH		 336 u16 tsf_gpt2_stat; /* 0x666 */
337 u16 tsf_gpt2_ctr_l; /* 0x668 */
338 u16 tsf_gpt2_ctr_h; /* 0x66A */
339 u16 tsf_gpt2_val_l; /* 0x66C */
340 u16 tsf_gpt2_val_h; /* 0x66E */
341 u16 tsf_gptall_stat; /* 0x670 */
342 u16 PAD[0x07]; /* 0x672 - 0x67E */
a9533e7e
HP		 343
344 /* IFS Block */
7d4df48e
GKH		 345 u16 ifs_sifs_rx_tx_tx; /* 0x680 */
346 u16 ifs_sifs_nav_tx; /* 0x682 */
347 u16 ifs_slot; /* 0x684 */
348 u16 PAD; /* 0x686 */
349 u16 ifs_ctl; /* 0x688 */
350 u16 PAD[0x3]; /* 0x68a - 0x68F */
351 u16 ifsstat; /* 0x690 */
352 u16 ifsmedbusyctl; /* 0x692 */
353 u16 iftxdur; /* 0x694 */
354 u16 PAD[0x3]; /* 0x696 - 0x69b */
3746507a 355 /* EDCF support in dot11macs */
7d4df48e
GKH		 356 u16 ifs_aifsn; /* 0x69c */
357 u16 ifs_ctl1; /* 0x69e */
a9533e7e 358
3746507a 359 /* slow clock registers */
7d4df48e
GKH		 360 u16 scc_ctl; /* 0x6a0 */
361 u16 scc_timer_l; /* 0x6a2 */
362 u16 scc_timer_h; /* 0x6a4 */
363 u16 scc_frac; /* 0x6a6 */
364 u16 scc_fastpwrup_dly; /* 0x6a8 */
365 u16 scc_per; /* 0x6aa */
366 u16 scc_per_frac; /* 0x6ac */
367 u16 scc_cal_timer_l; /* 0x6ae */
368 u16 scc_cal_timer_h; /* 0x6b0 */
369 u16 PAD; /* 0x6b2 */
370
371 u16 PAD[0x26];
a9533e7e
HP		 372
373 /* NAV Block */
7d4df48e
GKH		 374 u16 nav_ctl; /* 0x700 */
375 u16 navstat; /* 0x702 */
376 u16 PAD[0x3e]; /* 0x702 - 0x77E */
a9533e7e
HP		 377
378 /* WEP/PMQ Block *//* 0x780 - 0x7FE */
7d4df48e
GKH		 379 u16 PAD[0x20]; /* 0x780 - 0x7BE */
380
381 u16 wepctl; /* 0x7C0 */
382 u16 wepivloc; /* 0x7C2 */
383 u16 wepivkey; /* 0x7C4 */
384 u16 wepwkey; /* 0x7C6 */
385
386 u16 PAD[4]; /* 0x7C8 - 0x7CE */
387 u16 pcmctl; /* 0X7D0 */
388 u16 pcmstat; /* 0X7D2 */
389 u16 PAD[6]; /* 0x7D4 - 0x7DE */
390
391 u16 pmqctl; /* 0x7E0 */
392 u16 pmqstatus; /* 0x7E2 */
393 u16 pmqpat0; /* 0x7E4 */
394 u16 pmqpat1; /* 0x7E6 */
395 u16 pmqpat2; /* 0x7E8 */
396
397 u16 pmqdat; /* 0x7EA */
398 u16 pmqdator; /* 0x7EC */
399 u16 pmqhst; /* 0x7EE */
400 u16 pmqpath0; /* 0x7F0 */
401 u16 pmqpath1; /* 0x7F2 */
402 u16 pmqpath2; /* 0x7F4 */
403 u16 pmqdath; /* 0x7F6 */
404
405 u16 PAD[0x04]; /* 0x7F8 - 0x7FE */
a9533e7e
HP		 406
407 /* SHM *//* 0x800 - 0xEFE */
7d4df48e 408 u16 PAD[0x380]; /* 0x800 - 0xEFE */
a9533e7e
HP		 409
410 /* SB configuration registers: 0xF00 */
411 sbconfig_t sbconfig; /* sb config regs occupy top 256 bytes */
412} d11regs_t;
413
414#define PIHR_BASE 0x0400 /* byte address of packed IHR region */
415
416/* biststatus */
417#define BT_DONE (1U << 31) /* bist done */
418#define BT_B2S (1 << 30) /* bist2 ram summary bit */
419
420/* intstatus and intmask */
421#define I_PC (1 << 10) /* pci descriptor error */
422#define I_PD (1 << 11) /* pci data error */
423#define I_DE (1 << 12) /* descriptor protocol error */
424#define I_RU (1 << 13) /* receive descriptor underflow */
425#define I_RO (1 << 14) /* receive fifo overflow */
426#define I_XU (1 << 15) /* transmit fifo underflow */
427#define I_RI (1 << 16) /* receive interrupt */
428#define I_XI (1 << 24) /* transmit interrupt */
429
430/* interrupt receive lazy */
431#define IRL_TO_MASK 0x00ffffff /* timeout */
432#define IRL_FC_MASK 0xff000000 /* frame count */
433#define IRL_FC_SHIFT 24 /* frame count */
434
435/* maccontrol register */
436#define MCTL_GMODE (1U << 31)
437#define MCTL_DISCARD_PMQ (1 << 30)
438#define MCTL_WAKE (1 << 26)
439#define MCTL_HPS (1 << 25)
440#define MCTL_PROMISC (1 << 24)
441#define MCTL_KEEPBADFCS (1 << 23)
442#define MCTL_KEEPCONTROL (1 << 22)
443#define MCTL_PHYLOCK (1 << 21)
444#define MCTL_BCNS_PROMISC (1 << 20)
445#define MCTL_LOCK_RADIO (1 << 19)
446#define MCTL_AP (1 << 18)
447#define MCTL_INFRA (1 << 17)
448#define MCTL_BIGEND (1 << 16)
449#define MCTL_GPOUT_SEL_MASK (3 << 14)
450#define MCTL_GPOUT_SEL_SHIFT 14
451#define MCTL_EN_PSMDBG (1 << 13)
452#define MCTL_IHR_EN (1 << 10)
453#define MCTL_SHM_UPPER (1 << 9)
454#define MCTL_SHM_EN (1 << 8)
455#define MCTL_PSM_JMP_0 (1 << 2)
456#define MCTL_PSM_RUN (1 << 1)
457#define MCTL_EN_MAC (1 << 0)
458
459/* maccommand register */
460#define MCMD_BCN0VLD (1 << 0)
461#define MCMD_BCN1VLD (1 << 1)
462#define MCMD_DIRFRMQVAL (1 << 2)
463#define MCMD_CCA (1 << 3)
464#define MCMD_BG_NOISE (1 << 4)
465#define MCMD_SKIP_SHMINIT (1 << 5) /* only used for simulation */
466#define MCMD_SAMPLECOLL MCMD_SKIP_SHMINIT /* reuse for sample collect */
467
468/* macintstatus/macintmask */
469#define MI_MACSSPNDD (1 << 0) /* MAC has gracefully suspended */
470#define MI_BCNTPL (1 << 1) /* beacon template available */
471#define MI_TBTT (1 << 2) /* TBTT indication */
472#define MI_BCNSUCCESS (1 << 3) /* beacon successfully tx'd */
473#define MI_BCNCANCLD (1 << 4) /* beacon canceled (IBSS) */
474#define MI_ATIMWINEND (1 << 5) /* end of ATIM-window (IBSS) */
475#define MI_PMQ (1 << 6) /* PMQ entries available */
476#define MI_NSPECGEN_0 (1 << 7) /* non-specific gen-stat bits that are set by PSM */
477#define MI_NSPECGEN_1 (1 << 8) /* non-specific gen-stat bits that are set by PSM */
478#define MI_MACTXERR (1 << 9) /* MAC level Tx error */
479#define MI_NSPECGEN_3 (1 << 10) /* non-specific gen-stat bits that are set by PSM */
480#define MI_PHYTXERR (1 << 11) /* PHY Tx error */
481#define MI_PME (1 << 12) /* Power Management Event */
482#define MI_GP0 (1 << 13) /* General-purpose timer0 */
483#define MI_GP1 (1 << 14) /* General-purpose timer1 */
484#define MI_DMAINT (1 << 15) /* (ORed) DMA-interrupts */
485#define MI_TXSTOP (1 << 16) /* MAC has completed a TX FIFO Suspend/Flush */
486#define MI_CCA (1 << 17) /* MAC has completed a CCA measurement */
487#define MI_BG_NOISE (1 << 18) /* MAC has collected background noise samples */
488#define MI_DTIM_TBTT (1 << 19) /* MBSS DTIM TBTT indication */
489#define MI_PRQ (1 << 20) /* Probe response queue needs attention */
490#define MI_PWRUP (1 << 21) /* Radio/PHY has been powered back up. */
491#define MI_RESERVED3 (1 << 22)
492#define MI_RESERVED2 (1 << 23)
493#define MI_RESERVED1 (1 << 25)
3746507a
RV		 494/* MAC detected change on RF Disable input*/
495#define MI_RFDISABLE (1 << 28)
496#define MI_TFS (1 << 29) /* MAC has completed a TX */
a9533e7e 497#define MI_PHYCHANGED (1 << 30) /* A phy status change wrt G mode */
3746507a 498#define MI_TO (1U << 31) /* general purpose timeout */
a9533e7e
HP		 499
500/* Mac capabilities registers */
501/* machwcap */
502#define MCAP_TKIPMIC 0x80000000 /* TKIP MIC hardware present */
503
504/* pmqhost data */
505#define PMQH_DATA_MASK 0xffff0000 /* data entry of head pmq entry */
506#define PMQH_BSSCFG 0x00100000 /* PM entry for BSS config */
507#define PMQH_PMOFF 0x00010000 /* PM Mode OFF: power save off */
508#define PMQH_PMON 0x00020000 /* PM Mode ON: power save on */
509#define PMQH_DASAT 0x00040000 /* Dis-associated or De-authenticated */
510#define PMQH_ATIMFAIL 0x00080000 /* ATIM not acknowledged */
511#define PMQH_DEL_ENTRY 0x00000001 /* delete head entry */
512#define PMQH_DEL_MULT 0x00000002 /* delete head entry to cur read pointer -1 */
513#define PMQH_OFLO 0x00000004 /* pmq overflow indication */
514#define PMQH_NOT_EMPTY 0x00000008 /* entries are present in pmq */
515
3746507a 516/* phydebug */
a9533e7e
HP		 517#define PDBG_CRS (1 << 0) /* phy is asserting carrier sense */
518#define PDBG_TXA (1 << 1) /* phy is taking xmit byte from mac this cycle */
519#define PDBG_TXF (1 << 2) /* mac is instructing the phy to transmit a frame */
520#define PDBG_TXE (1 << 3) /* phy is signalling a transmit Error to the mac */
521#define PDBG_RXF (1 << 4) /* phy detected the end of a valid frame preamble */
522#define PDBG_RXS (1 << 5) /* phy detected the end of a valid PLCP header */
523#define PDBG_RXFRG (1 << 6) /* rx start not asserted */
524#define PDBG_RXV (1 << 7) /* mac is taking receive byte from phy this cycle */
525#define PDBG_RFD (1 << 16) /* RF portion of the radio is disabled */
526
527/* objaddr register */
528#define OBJADDR_SEL_MASK 0x000F0000
529#define OBJADDR_UCM_SEL 0x00000000
530#define OBJADDR_SHM_SEL 0x00010000
531#define OBJADDR_SCR_SEL 0x00020000
532#define OBJADDR_IHR_SEL 0x00030000
533#define OBJADDR_RCMTA_SEL 0x00040000
534#define OBJADDR_SRCHM_SEL 0x00060000
535#define OBJADDR_WINC 0x01000000
536#define OBJADDR_RINC 0x02000000
537#define OBJADDR_AUTO_INC 0x03000000
538
539#define WEP_PCMADDR 0x07d4
540#define WEP_PCMDATA 0x07d6
541
542/* frmtxstatus */
543#define TXS_V (1 << 0) /* valid bit */
544#define TXS_STATUS_MASK 0xffff
a9533e7e
HP		 545#define TXS_FID_MASK 0xffff0000
546#define TXS_FID_SHIFT 16
547
548/* frmtxstatus2 */
549#define TXS_SEQ_MASK 0xffff
550#define TXS_PTX_MASK 0xff0000
551#define TXS_PTX_SHIFT 16
552#define TXS_MU_MASK 0x01000000
553#define TXS_MU_SHIFT 24
554
3746507a 555/* clk_ctl_st */
a9533e7e
HP		 556#define CCS_ERSRC_REQ_D11PLL 0x00000100 /* d11 core pll request */
557#define CCS_ERSRC_REQ_PHYPLL 0x00000200 /* PHY pll request */
558#define CCS_ERSRC_AVAIL_D11PLL 0x01000000 /* d11 core pll available */
559#define CCS_ERSRC_AVAIL_PHYPLL 0x02000000 /* PHY pll available */
560
561/* HT Cloclk Ctrl and Clock Avail for 4313 */
562#define CCS_ERSRC_REQ_HT 0x00000010 /* HT avail request */
563#define CCS_ERSRC_AVAIL_HT 0x00020000 /* HT clock available */
564
a9533e7e
HP		 565/* tsf_cfprep register */
566#define CFPREP_CBI_MASK 0xffffffc0
567#define CFPREP_CBI_SHIFT 6
568#define CFPREP_CFPP 0x00000001
569
a9533e7e
HP		 570/* tx fifo sizes values are in terms of 256 byte blocks */
571#define TXFIFOCMD_RESET_MASK (1 << 15) /* reset */
572#define TXFIFOCMD_FIFOSEL_SHIFT 8 /* fifo */
573#define TXFIFO_FIFOTOP_SHIFT 8 /* fifo start */
574
575#define TXFIFO_START_BLK16 65 /* Base address + 32 * 512 B/P */
576#define TXFIFO_START_BLK 6 /* Base address + 6 * 256 B */
577#define TXFIFO_SIZE_UNIT 256 /* one unit corresponds to 256 bytes */
578#define MBSS16_TEMPLMEM_MINBLKS 65 /* one unit corresponds to 256 bytes */
579
580/* phy versions, PhyVersion:Revision field */
581#define PV_AV_MASK 0xf000 /* analog block version */
582#define PV_AV_SHIFT 12 /* analog block version bitfield offset */
583#define PV_PT_MASK 0x0f00 /* phy type */
584#define PV_PT_SHIFT 8 /* phy type bitfield offset */
585#define PV_PV_MASK 0x000f /* phy version */
586#define PHY_TYPE(v) ((v & PV_PT_MASK) >> PV_PT_SHIFT)
587
588/* phy types, PhyVersion:PhyType field */
589#define PHY_TYPE_N 4 /* N-Phy value */
590#define PHY_TYPE_SSN 6 /* SSLPN-Phy value */
591#define PHY_TYPE_LCN 8 /* LCN-Phy value */
592#define PHY_TYPE_LCNXN 9 /* LCNXN-Phy value */
593#define PHY_TYPE_NULL 0xf /* Invalid Phy value */
594
595/* analog types, PhyVersion:AnalogType field */
596#define ANA_11N_013 5
597
598/* 802.11a PLCP header def */
599typedef struct ofdm_phy_hdr ofdm_phy_hdr_t;
1e661086 600struct ofdm_phy_hdr {
de9bca63 601 u8 rlpt[3]; /* rate, length, parity, tail */
7d4df48e 602 u16 service;
de9bca63 603 u8 pad;
1e661086 604} __attribute__((packed));
a9533e7e
HP		 605
606#define D11A_PHY_HDR_GRATE(phdr) ((phdr)->rlpt[0] & 0x0f)
607#define D11A_PHY_HDR_GRES(phdr) (((phdr)->rlpt[0] >> 4) & 0x01)
66cbd3ab 608#define D11A_PHY_HDR_GLENGTH(phdr) (((u32 *)((phdr)->rlpt) >> 5) & 0x0fff)
a9533e7e
HP		 609#define D11A_PHY_HDR_GPARITY(phdr) (((phdr)->rlpt[3] >> 1) & 0x01)
610#define D11A_PHY_HDR_GTAIL(phdr) (((phdr)->rlpt[3] >> 2) & 0x3f)
611
612/* rate encoded per 802.11a-1999 sec 17.3.4.1 */
613#define D11A_PHY_HDR_SRATE(phdr, rate) \
614 ((phdr)->rlpt[0] = ((phdr)->rlpt[0] & 0xf0) | ((rate) & 0xf))
615/* set reserved field to zero */
616#define D11A_PHY_HDR_SRES(phdr) ((phdr)->rlpt[0] &= 0xef)
617/* length is number of octets in PSDU */
618#define D11A_PHY_HDR_SLENGTH(phdr, length) \
66cbd3ab 619 (*(u32 *)((phdr)->rlpt) = *(u32 *)((phdr)->rlpt) | \
a9533e7e
HP		 620 (((length) & 0x0fff) << 5))
621/* set the tail to all zeros */
622#define D11A_PHY_HDR_STAIL(phdr) ((phdr)->rlpt[3] &= 0x03)
623
624#define D11A_PHY_HDR_LEN_L 3 /* low-rate part of PLCP header */
625#define D11A_PHY_HDR_LEN_R 2 /* high-rate part of PLCP header */
626
627#define D11A_PHY_TX_DELAY (2) /* 2.1 usec */
628
629#define D11A_PHY_HDR_TIME (4) /* low-rate part of PLCP header */
630#define D11A_PHY_PRE_TIME (16)
631#define D11A_PHY_PREHDR_TIME (D11A_PHY_PRE_TIME + D11A_PHY_HDR_TIME)
632
633/* 802.11b PLCP header def */
634typedef struct cck_phy_hdr cck_phy_hdr_t;
1e661086 635struct cck_phy_hdr {
de9bca63
GKH		 636 u8 signal;
637 u8 service;
7d4df48e
GKH		 638 u16 length;
639 u16 crc;
1e661086 640} __attribute__((packed));
a9533e7e
HP		 641
642#define D11B_PHY_HDR_LEN 6
643
644#define D11B_PHY_TX_DELAY (3) /* 3.4 usec */
645
646#define D11B_PHY_LHDR_TIME (D11B_PHY_HDR_LEN << 3)
647#define D11B_PHY_LPRE_TIME (144)
648#define D11B_PHY_LPREHDR_TIME (D11B_PHY_LPRE_TIME + D11B_PHY_LHDR_TIME)
649
650#define D11B_PHY_SHDR_TIME (D11B_PHY_LHDR_TIME >> 1)
651#define D11B_PHY_SPRE_TIME (D11B_PHY_LPRE_TIME >> 1)
652#define D11B_PHY_SPREHDR_TIME (D11B_PHY_SPRE_TIME + D11B_PHY_SHDR_TIME)
653
654#define D11B_PLCP_SIGNAL_LOCKED (1 << 2)
655#define D11B_PLCP_SIGNAL_LE (1 << 7)
656
657#define MIMO_PLCP_MCS_MASK 0x7f /* mcs index */
658#define MIMO_PLCP_40MHZ 0x80 /* 40 Hz frame */
659#define MIMO_PLCP_AMPDU 0x08 /* ampdu */
660
661#define WLC_GET_CCK_PLCP_LEN(plcp) (plcp[4] + (plcp[5] << 8))
662#define WLC_GET_MIMO_PLCP_LEN(plcp) (plcp[1] + (plcp[2] << 8))
663#define WLC_SET_MIMO_PLCP_LEN(plcp, len) \
c5fe41c3
JC		 664 do { \
665 plcp[1] = len & 0xff; \
666 plcp[2] = ((len >> 8) & 0xff); \
667 } while (0);
a9533e7e
HP		 668
669#define WLC_SET_MIMO_PLCP_AMPDU(plcp) (plcp[3] |= MIMO_PLCP_AMPDU)
670#define WLC_CLR_MIMO_PLCP_AMPDU(plcp) (plcp[3] &= ~MIMO_PLCP_AMPDU)
671#define WLC_IS_MIMO_PLCP_AMPDU(plcp) (plcp[3] & MIMO_PLCP_AMPDU)
672
673/* The dot11a PLCP header is 5 bytes. To simplify the software (so that we
674 * don't need e.g. different tx DMA headers for 11a and 11b), the PLCP header has
675 * padding added in the ucode.
676 */
677#define D11_PHY_HDR_LEN 6
678
679/* TX DMA buffer header */
680typedef struct d11txh d11txh_t;
1e661086 681struct d11txh {
7d4df48e
GKH		 682 u16 MacTxControlLow; /* 0x0 */
683 u16 MacTxControlHigh; /* 0x1 */
684 u16 MacFrameControl; /* 0x2 */
685 u16 TxFesTimeNormal; /* 0x3 */
686 u16 PhyTxControlWord; /* 0x4 */
687 u16 PhyTxControlWord_1; /* 0x5 */
688 u16 PhyTxControlWord_1_Fbr; /* 0x6 */
689 u16 PhyTxControlWord_1_Rts; /* 0x7 */
690 u16 PhyTxControlWord_1_FbrRts; /* 0x8 */
691 u16 MainRates; /* 0x9 */
692 u16 XtraFrameTypes; /* 0xa */
de9bca63
GKH		 693 u8 IV[16]; /* 0x0b - 0x12 */
694 u8 TxFrameRA[6]; /* 0x13 - 0x15 */
7d4df48e 695 u16 TxFesTimeFallback; /* 0x16 */
de9bca63 696 u8 RTSPLCPFallback[6]; /* 0x17 - 0x19 */
7d4df48e 697 u16 RTSDurFallback; /* 0x1a */
de9bca63 698 u8 FragPLCPFallback[6]; /* 0x1b - 1d */
7d4df48e
GKH		 699 u16 FragDurFallback; /* 0x1e */
700 u16 MModeLen; /* 0x1f */
701 u16 MModeFbrLen; /* 0x20 */
702 u16 TstampLow; /* 0x21 */
703 u16 TstampHigh; /* 0x22 */
704 u16 ABI_MimoAntSel; /* 0x23 */
705 u16 PreloadSize; /* 0x24 */
706 u16 AmpduSeqCtl; /* 0x25 */
707 u16 TxFrameID; /* 0x26 */
708 u16 TxStatus; /* 0x27 */
3746507a
RV		 709 u16 MaxNMpdus; /* 0x28 */
710 u16 MaxABytes_MRT; /* 0x29 */
711 u16 MaxABytes_FBR; /* 0x2a */
712 u16 MinMBytes; /* 0x2b */
de9bca63 713 u8 RTSPhyHeader[D11_PHY_HDR_LEN]; /* 0x2c - 0x2e */
f3dc3ea4 714 struct ieee80211_rts rts_frame; /* 0x2f - 0x36 */
7d4df48e 715 u16 PAD; /* 0x37 */
1e661086 716} __attribute__((packed));
a9533e7e
HP		 717
718#define D11_TXH_LEN 112 /* bytes */
719
720/* Frame Types */
721#define FT_CCK 0
722#define FT_OFDM 1
723#define FT_HT 2
724#define FT_N 3
725
726/* Position of MPDU inside A-MPDU; indicated with bits 10:9 of MacTxControlLow */
727#define TXC_AMPDU_SHIFT 9 /* shift for ampdu settings */
728#define TXC_AMPDU_NONE 0 /* Regular MPDU, not an A-MPDU */
729#define TXC_AMPDU_FIRST 1 /* first MPDU of an A-MPDU */
730#define TXC_AMPDU_MIDDLE 2 /* intermediate MPDU of an A-MPDU */
731#define TXC_AMPDU_LAST 3 /* last (or single) MPDU of an A-MPDU */
732
733/* MacTxControlLow */
734#define TXC_AMIC 0x8000
735#define TXC_SENDCTS 0x0800
736#define TXC_AMPDU_MASK 0x0600
737#define TXC_BW_40 0x0100
738#define TXC_FREQBAND_5G 0x0080
739#define TXC_DFCS 0x0040
740#define TXC_IGNOREPMQ 0x0020
741#define TXC_HWSEQ 0x0010
742#define TXC_STARTMSDU 0x0008
743#define TXC_SENDRTS 0x0004
744#define TXC_LONGFRAME 0x0002
745#define TXC_IMMEDACK 0x0001
746
747/* MacTxControlHigh */
748#define TXC_PREAMBLE_RTS_FB_SHORT 0x8000 /* RTS fallback preamble type 1 = SHORT 0 = LONG */
749#define TXC_PREAMBLE_RTS_MAIN_SHORT 0x4000 /* RTS main rate preamble type 1 = SHORT 0 = LONG */
750#define TXC_PREAMBLE_DATA_FB_SHORT 0x2000 /* Main fallback rate preamble type
751 * 1 = SHORT for OFDM/GF for MIMO
752 * 0 = LONG for CCK/MM for MIMO
753 */
754/* TXC_PREAMBLE_DATA_MAIN is in PhyTxControl bit 5 */
755#define TXC_AMPDU_FBR 0x1000 /* use fallback rate for this AMPDU */
756#define TXC_SECKEY_MASK 0x0FF0
757#define TXC_SECKEY_SHIFT 4
758#define TXC_ALT_TXPWR 0x0008 /* Use alternate txpwr defined at loc. M_ALT_TXPWR_IDX */
759#define TXC_SECTYPE_MASK 0x0007
760#define TXC_SECTYPE_SHIFT 0
761
762/* Null delimiter for Fallback rate */
763#define AMPDU_FBR_NULL_DELIM 5 /* Location of Null delimiter count for AMPDU */
764
765/* PhyTxControl for Mimophy */
766#define PHY_TXC_PWR_MASK 0xFC00
767#define PHY_TXC_PWR_SHIFT 10
768#define PHY_TXC_ANT_MASK 0x03C0 /* bit 6, 7, 8, 9 */
769#define PHY_TXC_ANT_SHIFT 6
770#define PHY_TXC_ANT_0_1 0x00C0 /* auto, last rx */
771#define PHY_TXC_LCNPHY_ANT_LAST 0x0000
772#define PHY_TXC_ANT_3 0x0200 /* virtual antenna 3 */
773#define PHY_TXC_ANT_2 0x0100 /* virtual antenna 2 */
774#define PHY_TXC_ANT_1 0x0080 /* virtual antenna 1 */
775#define PHY_TXC_ANT_0 0x0040 /* virtual antenna 0 */
776#define PHY_TXC_SHORT_HDR 0x0010
777
778#define PHY_TXC_OLD_ANT_0 0x0000
779#define PHY_TXC_OLD_ANT_1 0x0100
780#define PHY_TXC_OLD_ANT_LAST 0x0300
781
782/* PhyTxControl_1 for Mimophy */
783#define PHY_TXC1_BW_MASK 0x0007
784#define PHY_TXC1_BW_10MHZ 0
785#define PHY_TXC1_BW_10MHZ_UP 1
786#define PHY_TXC1_BW_20MHZ 2
787#define PHY_TXC1_BW_20MHZ_UP 3
788#define PHY_TXC1_BW_40MHZ 4
789#define PHY_TXC1_BW_40MHZ_DUP 5
790#define PHY_TXC1_MODE_SHIFT 3
791#define PHY_TXC1_MODE_MASK 0x0038
792#define PHY_TXC1_MODE_SISO 0
793#define PHY_TXC1_MODE_CDD 1
794#define PHY_TXC1_MODE_STBC 2
795#define PHY_TXC1_MODE_SDM 3
796
797/* PhyTxControl for HTphy that are different from Mimophy */
798#define PHY_TXC_HTANT_MASK 0x3fC0 /* bit 6, 7, 8, 9, 10, 11, 12, 13 */
799
800/* XtraFrameTypes */
801#define XFTS_RTS_FT_SHIFT 2
802#define XFTS_FBRRTS_FT_SHIFT 4
803#define XFTS_CHANNEL_SHIFT 8
804
805/* Antenna diversity bit in ant_wr_settle */
806#define PHY_AWS_ANTDIV 0x2000
807
808/* IFS ctl */
809#define IFS_USEEDCF (1 << 2)
810
811/* IFS ctl1 */
812#define IFS_CTL1_EDCRS (1 << 3)
813#define IFS_CTL1_EDCRS_20L (1 << 4)
814#define IFS_CTL1_EDCRS_40 (1 << 5)
815
816/* ABI_MimoAntSel */
817#define ABI_MAS_ADDR_BMP_IDX_MASK 0x0f00
818#define ABI_MAS_ADDR_BMP_IDX_SHIFT 8
819#define ABI_MAS_FBR_ANT_PTN_MASK 0x00f0
820#define ABI_MAS_FBR_ANT_PTN_SHIFT 4
821#define ABI_MAS_MRT_ANT_PTN_MASK 0x000f
822
823/* tx status packet */
824typedef struct tx_status tx_status_t;
1e661086 825struct tx_status {
7d4df48e
GKH		 826 u16 framelen;
827 u16 PAD;
828 u16 frameid;
829 u16 status;
830 u16 lasttxtime;
831 u16 sequence;
832 u16 phyerr;
833 u16 ackphyrxsh;
1e661086 834} __attribute__((packed));
a9533e7e
HP		 835
836#define TXSTATUS_LEN 16
837
838/* status field bit definitions */
839#define TX_STATUS_FRM_RTX_MASK 0xF000
840#define TX_STATUS_FRM_RTX_SHIFT 12
841#define TX_STATUS_RTS_RTX_MASK 0x0F00
842#define TX_STATUS_RTS_RTX_SHIFT 8
843#define TX_STATUS_MASK 0x00FE
844#define TX_STATUS_PMINDCTD (1 << 7) /* PM mode indicated to AP */
845#define TX_STATUS_INTERMEDIATE (1 << 6) /* intermediate or 1st ampdu pkg */
846#define TX_STATUS_AMPDU (1 << 5) /* AMPDU status */
847#define TX_STATUS_SUPR_MASK 0x1C /* suppress status bits (4:2) */
848#define TX_STATUS_SUPR_SHIFT 2
849#define TX_STATUS_ACK_RCV (1 << 1) /* ACK received */
3746507a 850#define TX_STATUS_VALID (1 << 0) /* Tx status valid */
a9533e7e
HP		 851#define TX_STATUS_NO_ACK 0
852
853/* suppress status reason codes */
854#define TX_STATUS_SUPR_PMQ (1 << 2) /* PMQ entry */
855#define TX_STATUS_SUPR_FLUSH (2 << 2) /* flush request */
856#define TX_STATUS_SUPR_FRAG (3 << 2) /* previous frag failure */
857#define TX_STATUS_SUPR_TBTT (3 << 2) /* SHARED: Probe response supr for TBTT */
858#define TX_STATUS_SUPR_BADCH (4 << 2) /* channel mismatch */
859#define TX_STATUS_SUPR_EXPTIME (5 << 2) /* lifetime expiry */
860#define TX_STATUS_SUPR_UF (6 << 2) /* underflow */
861
862/* Unexpected tx status for rate update */
863#define TX_STATUS_UNEXP(status) \
864 ((((status) & TX_STATUS_INTERMEDIATE) != 0) && \
865 TX_STATUS_UNEXP_AMPDU(status))
866
867/* Unexpected tx status for A-MPDU rate update */
868#define TX_STATUS_UNEXP_AMPDU(status) \
869 ((((status) & TX_STATUS_SUPR_MASK) != 0) && \
870 (((status) & TX_STATUS_SUPR_MASK) != TX_STATUS_SUPR_EXPTIME))
871
872#define TX_STATUS_BA_BMAP03_MASK 0xF000 /* ba bitmap 0:3 in 1st pkg */
873#define TX_STATUS_BA_BMAP03_SHIFT 12 /* ba bitmap 0:3 in 1st pkg */
874#define TX_STATUS_BA_BMAP47_MASK 0x001E /* ba bitmap 4:7 in 2nd pkg */
875#define TX_STATUS_BA_BMAP47_SHIFT 3 /* ba bitmap 4:7 in 2nd pkg */
876
877/* RXE (Receive Engine) */
878
879/* RCM_CTL */
880#define RCM_INC_MASK_H 0x0080
881#define RCM_INC_MASK_L 0x0040
882#define RCM_INC_DATA 0x0020
883#define RCM_INDEX_MASK 0x001F
884#define RCM_SIZE 15
885
886#define RCM_MAC_OFFSET 0 /* current MAC address */
887#define RCM_BSSID_OFFSET 3 /* current BSSID address */
888#define RCM_F_BSSID_0_OFFSET 6 /* foreign BSS CFP tracking */
889#define RCM_F_BSSID_1_OFFSET 9 /* foreign BSS CFP tracking */
890#define RCM_F_BSSID_2_OFFSET 12 /* foreign BSS CFP tracking */
891
892#define RCM_WEP_TA0_OFFSET 16
893#define RCM_WEP_TA1_OFFSET 19
894#define RCM_WEP_TA2_OFFSET 22
895#define RCM_WEP_TA3_OFFSET 25
896
897/* PSM Block */
898
899/* psm_phy_hdr_param bits */
900#define MAC_PHY_RESET 1
901#define MAC_PHY_CLOCK_EN 2
902#define MAC_PHY_FORCE_CLK 4
903
904/* WEP Block */
905
906/* WEP_WKEY */
907#define WKEY_START (1 << 8)
908#define WKEY_SEL_MASK 0x1F
909
910/* WEP data formats */
911
912/* the number of RCMTA entries */
913#define RCMTA_SIZE 50
914
915#define M_ADDR_BMP_BLK (0x37e * 2)
916#define M_ADDR_BMP_BLK_SZ 12
917
918#define ADDR_BMP_RA (1 << 0) /* Receiver Address (RA) */
919#define ADDR_BMP_TA (1 << 1) /* Transmitter Address (TA) */
920#define ADDR_BMP_BSSID (1 << 2) /* BSSID */
921#define ADDR_BMP_AP (1 << 3) /* Infra-BSS Access Point (AP) */
922#define ADDR_BMP_STA (1 << 4) /* Infra-BSS Station (STA) */
923#define ADDR_BMP_RESERVED1 (1 << 5)
924#define ADDR_BMP_RESERVED2 (1 << 6)
925#define ADDR_BMP_RESERVED3 (1 << 7)
926#define ADDR_BMP_BSS_IDX_MASK (3 << 8) /* BSS control block index */
927#define ADDR_BMP_BSS_IDX_SHIFT 8
928
929#define WSEC_MAX_RCMTA_KEYS 54
930
931/* max keys in M_TKMICKEYS_BLK */
932#define WSEC_MAX_TKMIC_ENGINE_KEYS 12 /* 8 + 4 default */
933
934/* max RXE match registers */
935#define WSEC_MAX_RXE_KEYS 4
936
937/* SECKINDXALGO (Security Key Index & Algorithm Block) word format */
938/* SKL (Security Key Lookup) */
939#define SKL_ALGO_MASK 0x0007
940#define SKL_ALGO_SHIFT 0
941#define SKL_KEYID_MASK 0x0008
942#define SKL_KEYID_SHIFT 3
943#define SKL_INDEX_MASK 0x03F0
944#define SKL_INDEX_SHIFT 4
945#define SKL_GRP_ALGO_MASK 0x1c00
946#define SKL_GRP_ALGO_SHIFT 10
947
948/* additional bits defined for IBSS group key support */
949#define SKL_IBSS_INDEX_MASK 0x01F0
950#define SKL_IBSS_INDEX_SHIFT 4
951#define SKL_IBSS_KEYID1_MASK 0x0600
952#define SKL_IBSS_KEYID1_SHIFT 9
953#define SKL_IBSS_KEYID2_MASK 0x1800
954#define SKL_IBSS_KEYID2_SHIFT 11
955#define SKL_IBSS_KEYALGO_MASK 0xE000
956#define SKL_IBSS_KEYALGO_SHIFT 13
957
958#define WSEC_MODE_OFF 0
959#define WSEC_MODE_HW 1
960#define WSEC_MODE_SW 2
961
962#define WSEC_ALGO_OFF 0
963#define WSEC_ALGO_WEP1 1
964#define WSEC_ALGO_TKIP 2
965#define WSEC_ALGO_AES 3
966#define WSEC_ALGO_WEP128 4
967#define WSEC_ALGO_AES_LEGACY 5
968#define WSEC_ALGO_NALG 6
969
970#define AES_MODE_NONE 0
971#define AES_MODE_CCM 1
972
973/* WEP_CTL (Rev 0) */
974#define WECR0_KEYREG_SHIFT 0
975#define WECR0_KEYREG_MASK 0x7
976#define WECR0_DECRYPT (1 << 3)
977#define WECR0_IVINLINE (1 << 4)
978#define WECR0_WEPALG_SHIFT 5
979#define WECR0_WEPALG_MASK (0x7 << 5)
980#define WECR0_WKEYSEL_SHIFT 8
981#define WECR0_WKEYSEL_MASK (0x7 << 8)
982#define WECR0_WKEYSTART (1 << 11)
983#define WECR0_WEPINIT (1 << 14)
984#define WECR0_ICVERR (1 << 15)
985
986/* Frame template map byte offsets */
987#define T_ACTS_TPL_BASE (0)
988#define T_NULL_TPL_BASE (0xc * 2)
989#define T_QNULL_TPL_BASE (0x1c * 2)
990#define T_RR_TPL_BASE (0x2c * 2)
991#define T_BCN0_TPL_BASE (0x34 * 2)
992#define T_PRS_TPL_BASE (0x134 * 2)
993#define T_BCN1_TPL_BASE (0x234 * 2)
994#define T_TX_FIFO_TXRAM_BASE (T_ACTS_TPL_BASE + (TXFIFO_START_BLK * TXFIFO_SIZE_UNIT))
995
996#define T_BA_TPL_BASE T_QNULL_TPL_BASE /* template area for BA */
997
998#define T_RAM_ACCESS_SZ 4 /* template ram is 4 byte access only */
999
1000/* Shared Mem byte offsets */
1001
1002/* Location where the ucode expects the corerev */
1003#define M_MACHW_VER (0x00b * 2)
1004
1005/* Location where the ucode expects the MAC capabilities */
1006#define M_MACHW_CAP_L (0x060 * 2)
1007#define M_MACHW_CAP_H (0x061 * 2)
1008
1009/* WME shared memory */
1010#define M_EDCF_STATUS_OFF (0x007 * 2)
1011#define M_TXF_CUR_INDEX (0x018 * 2)
1012#define M_EDCF_QINFO (0x120 * 2)
1013
1014/* PS-mode related parameters */
1015#define M_DOT11_SLOT (0x008 * 2)
1016#define M_DOT11_DTIMPERIOD (0x009 * 2)
1017#define M_NOSLPZNATDTIM (0x026 * 2)
1018
1019/* Beacon-related parameters */
1020#define M_BCN0_FRM_BYTESZ (0x00c * 2) /* Bcn 0 template length */
1021#define M_BCN1_FRM_BYTESZ (0x00d * 2) /* Bcn 1 template length */
1022#define M_BCN_TXTSF_OFFSET (0x00e * 2)
1023#define M_TIMBPOS_INBEACON (0x00f * 2)
1024#define M_SFRMTXCNTFBRTHSD (0x022 * 2)
1025#define M_LFRMTXCNTFBRTHSD (0x023 * 2)
1026#define M_BCN_PCTLWD (0x02a * 2)
1027#define M_BCN_LI (0x05b * 2) /* beacon listen interval */
1028
1029/* MAX Rx Frame len */
1030#define M_MAXRXFRM_LEN (0x010 * 2)
1031
1032/* ACK/CTS related params */
1033#define M_RSP_PCTLWD (0x011 * 2)
1034
1035/* Hardware Power Control */
1036#define M_TXPWR_N (0x012 * 2)
1037#define M_TXPWR_TARGET (0x013 * 2)
1038#define M_TXPWR_MAX (0x014 * 2)
1039#define M_TXPWR_CUR (0x019 * 2)
1040
1041/* Rx-related parameters */
1042#define M_RX_PAD_DATA_OFFSET (0x01a * 2)
1043
1044/* WEP Shared mem data */
1045#define M_SEC_DEFIVLOC (0x01e * 2)
1046#define M_SEC_VALNUMSOFTMCHTA (0x01f * 2)
1047#define M_PHYVER (0x028 * 2)
1048#define M_PHYTYPE (0x029 * 2)
1049#define M_SECRXKEYS_PTR (0x02b * 2)
1050#define M_TKMICKEYS_PTR (0x059 * 2)
1051#define M_SECKINDXALGO_BLK (0x2ea * 2)
1052#define M_SECKINDXALGO_BLK_SZ 54
1053#define M_SECPSMRXTAMCH_BLK (0x2fa * 2)
1054#define M_TKIP_TSC_TTAK (0x18c * 2)
1055#define D11_MAX_KEY_SIZE 16
1056
1057#define M_MAX_ANTCNT (0x02e * 2) /* antenna swap threshold */
1058
1059/* Probe response related parameters */
1060#define M_SSIDLEN (0x024 * 2)
1061#define M_PRB_RESP_FRM_LEN (0x025 * 2)
1062#define M_PRS_MAXTIME (0x03a * 2)
1063#define M_SSID (0xb0 * 2)
1064#define M_CTXPRS_BLK (0xc0 * 2)
1065#define C_CTX_PCTLWD_POS (0x4 * 2)
1066
1067/* Delta between OFDM and CCK power in CCK power boost mode */
1068#define M_OFDM_OFFSET (0x027 * 2)
1069
1070/* TSSI for last 4 11b/g CCK packets transmitted */
1071#define M_B_TSSI_0 (0x02c * 2)
1072#define M_B_TSSI_1 (0x02d * 2)
1073
1074/* Host flags to turn on ucode options */
1075#define M_HOST_FLAGS1 (0x02f * 2)
1076#define M_HOST_FLAGS2 (0x030 * 2)
1077#define M_HOST_FLAGS3 (0x031 * 2)
1078#define M_HOST_FLAGS4 (0x03c * 2)
1079#define M_HOST_FLAGS5 (0x06a * 2)
1080#define M_HOST_FLAGS_SZ 16
1081
1082#define M_RADAR_REG (0x033 * 2)
1083
1084/* TSSI for last 4 11a OFDM packets transmitted */
1085#define M_A_TSSI_0 (0x034 * 2)
1086#define M_A_TSSI_1 (0x035 * 2)
1087
1088/* noise interference measurement */
1089#define M_NOISE_IF_COUNT (0x034 * 2)
1090#define M_NOISE_IF_TIMEOUT (0x035 * 2)
1091
1092#define M_RF_RX_SP_REG1 (0x036 * 2)
1093
1094/* TSSI for last 4 11g OFDM packets transmitted */
1095#define M_G_TSSI_0 (0x038 * 2)
1096#define M_G_TSSI_1 (0x039 * 2)
1097
1098/* Background noise measure */
1099#define M_JSSI_0 (0x44 * 2)
1100#define M_JSSI_1 (0x45 * 2)
1101#define M_JSSI_AUX (0x46 * 2)
1102
1103#define M_CUR_2050_RADIOCODE (0x47 * 2)
1104
1105/* TX fifo sizes */
1106#define M_FIFOSIZE0 (0x4c * 2)
1107#define M_FIFOSIZE1 (0x4d * 2)
1108#define M_FIFOSIZE2 (0x4e * 2)
1109#define M_FIFOSIZE3 (0x4f * 2)
1110#define D11_MAX_TX_FRMS 32 /* max frames allowed in tx fifo */
1111
1112/* Current channel number plus upper bits */
1113#define M_CURCHANNEL (0x50 * 2)
1114#define D11_CURCHANNEL_5G 0x0100;
1115#define D11_CURCHANNEL_40 0x0200;
1116#define D11_CURCHANNEL_MAX 0x00FF;
1117
1118/* last posted frameid on the bcmc fifo */
1119#define M_BCMC_FID (0x54 * 2)
1120#define INVALIDFID 0xffff
1121
1122/* extended beacon phyctl bytes for 11N */
1123#define M_BCN_PCTL1WD (0x058 * 2)
1124
1125/* idle busy ratio to duty_cycle requirement */
1126#define M_TX_IDLE_BUSY_RATIO_X_16_CCK (0x52 * 2)
1127#define M_TX_IDLE_BUSY_RATIO_X_16_OFDM (0x5A * 2)
1128
1129/* CW RSSI for LCNPHY */
1130#define M_LCN_RSSI_0 0x1332
1131#define M_LCN_RSSI_1 0x1338
1132#define M_LCN_RSSI_2 0x133e
1133#define M_LCN_RSSI_3 0x1344
1134
1135/* SNR for LCNPHY */
1136#define M_LCN_SNR_A_0 0x1334
1137#define M_LCN_SNR_B_0 0x1336
1138
1139#define M_LCN_SNR_A_1 0x133a
1140#define M_LCN_SNR_B_1 0x133c
1141
1142#define M_LCN_SNR_A_2 0x1340
1143#define M_LCN_SNR_B_2 0x1342
1144
1145#define M_LCN_SNR_A_3 0x1346
1146#define M_LCN_SNR_B_3 0x1348
1147
1148#define M_LCN_LAST_RESET (81*2)
1149#define M_LCN_LAST_LOC (63*2)
1150#define M_LCNPHY_RESET_STATUS (4902)
1151#define M_LCNPHY_DSC_TIME (0x98d*2)
1152#define M_LCNPHY_RESET_CNT_DSC (0x98b*2)
1153#define M_LCNPHY_RESET_CNT (0x98c*2)
1154
1155/* Rate table offsets */
1156#define M_RT_DIRMAP_A (0xe0 * 2)
1157#define M_RT_BBRSMAP_A (0xf0 * 2)
1158#define M_RT_DIRMAP_B (0x100 * 2)
1159#define M_RT_BBRSMAP_B (0x110 * 2)
1160
1161/* Rate table entry offsets */
1162#define M_RT_PRS_PLCP_POS 10
1163#define M_RT_PRS_DUR_POS 16
1164#define M_RT_OFDM_PCTL1_POS 18
1165
1166#define M_20IN40_IQ (0x380 * 2)
1167
1168/* SHM locations where ucode stores the current power index */
198bd4d6
JC		 1169#define M_CURR_IDX1 (0x384 * 2)
1170#define M_CURR_IDX2 (0x387 * 2)
a9533e7e
HP		 1171
1172#define M_BSCALE_ANT0 (0x5e * 2)
1173#define M_BSCALE_ANT1 (0x5f * 2)
1174
1175/* Antenna Diversity Testing */
1176#define M_MIMO_ANTSEL_RXDFLT (0x63 * 2)
1177#define M_ANTSEL_CLKDIV (0x61 * 2)
1178#define M_MIMO_ANTSEL_TXDFLT (0x64 * 2)
1179
1180#define M_MIMO_MAXSYM (0x5d * 2)
1181#define MIMO_MAXSYM_DEF 0x8000 /* 32k */
1182#define MIMO_MAXSYM_MAX 0xffff /* 64k */
1183
1184#define M_WATCHDOG_8TU (0x1e * 2)
1185#define WATCHDOG_8TU_DEF 5
1186#define WATCHDOG_8TU_MAX 10
1187
1188/* Manufacturing Test Variables */
1189#define M_PKTENG_CTRL (0x6c * 2) /* PER test mode */
1190#define M_PKTENG_IFS (0x6d * 2) /* IFS for TX mode */
1191#define M_PKTENG_FRMCNT_LO (0x6e * 2) /* Lower word of tx frmcnt/rx lostcnt */
1192#define M_PKTENG_FRMCNT_HI (0x6f * 2) /* Upper word of tx frmcnt/rx lostcnt */
1193
1194/* Index variation in vbat ripple */
1195#define M_LCN_PWR_IDX_MAX (0x67 * 2) /* highest index read by ucode */
1196#define M_LCN_PWR_IDX_MIN (0x66 * 2) /* lowest index read by ucode */
1197
1198/* M_PKTENG_CTRL bit definitions */
1199#define M_PKTENG_MODE_TX 0x0001
1200#define M_PKTENG_MODE_TX_RIFS 0x0004
1201#define M_PKTENG_MODE_TX_CTS 0x0008
1202#define M_PKTENG_MODE_RX 0x0002
1203#define M_PKTENG_MODE_RX_WITH_ACK 0x0402
1204#define M_PKTENG_MODE_MASK 0x0003
1205#define M_PKTENG_FRMCNT_VLD 0x0100 /* TX frames indicated in the frmcnt reg */
1206
1207/* Sample Collect parameters (bitmap and type) */
1208#define M_SMPL_COL_BMP (0x37d * 2) /* Trigger bitmap for sample collect */
1209#define M_SMPL_COL_CTL (0x3b2 * 2) /* Sample collect type */
1210
1211#define ANTSEL_CLKDIV_4MHZ 6
1212#define MIMO_ANTSEL_BUSY 0x4000 /* bit 14 (busy) */
1213#define MIMO_ANTSEL_SEL 0x8000 /* bit 15 write the value */
1214#define MIMO_ANTSEL_WAIT 50 /* 50us wait */
1215#define MIMO_ANTSEL_OVERRIDE 0x8000 /* flag */
1216
1217typedef struct shm_acparams shm_acparams_t;
1e661086 1218struct shm_acparams {
7d4df48e
GKH		 1219 u16 txop;
1220 u16 cwmin;
1221 u16 cwmax;
1222 u16 cwcur;
1223 u16 aifs;
1224 u16 bslots;
1225 u16 reggap;
1226 u16 status;
1227 u16 rsvd[8];
1e661086 1228} __attribute__((packed));
a9533e7e
HP		 1229#define M_EDCF_QLEN (16 * 2)
1230
1231#define WME_STATUS_NEWAC (1 << 8)
1232
1233/* M_HOST_FLAGS */
7d4df48e 1234#define MHFMAX 5 /* Number of valid hostflag half-word (u16) */
a9533e7e
HP		 1235#define MHF1 0 /* Hostflag 1 index */
1236#define MHF2 1 /* Hostflag 2 index */
1237#define MHF3 2 /* Hostflag 3 index */
1238#define MHF4 3 /* Hostflag 4 index */
1239#define MHF5 4 /* Hostflag 5 index */
1240
1241/* Flags in M_HOST_FLAGS */
1242#define MHF1_ANTDIV 0x0001 /* Enable ucode antenna diversity help */
1243#define MHF1_EDCF 0x0100 /* Enable EDCF access control */
1244#define MHF1_IQSWAP_WAR 0x0200
1245#define MHF1_FORCEFASTCLK 0x0400 /* Disable Slow clock request, for corerev < 11 */
1246
1247/* Flags in M_HOST_FLAGS2 */
1248#define MHF2_PCISLOWCLKWAR 0x0008 /* PR16165WAR : Enable ucode PCI slow clock WAR */
1249#define MHF2_TXBCMC_NOW 0x0040 /* Flush BCMC FIFO immediately */
1250#define MHF2_HWPWRCTL 0x0080 /* Enable ucode/hw power control */
1251#define MHF2_NPHY40MHZ_WAR 0x0800
1252
1253/* Flags in M_HOST_FLAGS3 */
1254#define MHF3_ANTSEL_EN 0x0001 /* enabled mimo antenna selection */
1255#define MHF3_ANTSEL_MODE 0x0002 /* antenna selection mode: 0: 2x3, 1: 2x4 */
1256#define MHF3_RESERVED1 0x0004
1257#define MHF3_RESERVED2 0x0008
1258#define MHF3_NPHY_MLADV_WAR 0x0010
1259
1260/* Flags in M_HOST_FLAGS4 */
1261#define MHF4_BPHY_TXCORE0 0x0080 /* force bphy Tx on core 0 (board level WAR) */
1262#define MHF4_EXTPA_ENABLE 0x4000 /* for 4313A0 FEM boards */
1263
1264/* Flags in M_HOST_FLAGS5 */
1265#define MHF5_4313_GPIOCTRL 0x0001
1266#define MHF5_RESERVED1 0x0002
1267#define MHF5_RESERVED2 0x0004
1268/* Radio power setting for ucode */
1269#define M_RADIO_PWR (0x32 * 2)
1270
1271/* phy noise recorded by ucode right after tx */
1272#define M_PHY_NOISE (0x037 * 2)
1273#define PHY_NOISE_MASK 0x00ff
1274
1275/* Receive Frame Data Header for 802.11b DCF-only frames */
1276typedef struct d11rxhdr d11rxhdr_t;
1e661086 1277struct d11rxhdr {
7d4df48e
GKH		 1278 u16 RxFrameSize; /* Actual byte length of the frame data received */
1279 u16 PAD;
1280 u16 PhyRxStatus_0; /* PhyRxStatus 15:0 */
1281 u16 PhyRxStatus_1; /* PhyRxStatus 31:16 */
1282 u16 PhyRxStatus_2; /* PhyRxStatus 47:32 */
1283 u16 PhyRxStatus_3; /* PhyRxStatus 63:48 */
1284 u16 PhyRxStatus_4; /* PhyRxStatus 79:64 */
1285 u16 PhyRxStatus_5; /* PhyRxStatus 95:80 */
1286 u16 RxStatus1; /* MAC Rx Status */
1287 u16 RxStatus2; /* extended MAC Rx status */
1288 u16 RxTSFTime; /* RxTSFTime time of first MAC symbol + M_PHY_PLCPRX_DLY */
1289 u16 RxChan; /* gain code, channel radio code, and phy type */
1e661086 1290} __attribute__((packed));
a9533e7e
HP		 1291
1292#define RXHDR_LEN 24 /* sizeof d11rxhdr_t */
1293#define FRAMELEN(h) ((h)->RxFrameSize)
1294
1295typedef struct wlc_d11rxhdr wlc_d11rxhdr_t;
1e661086 1296struct wlc_d11rxhdr {
a9533e7e 1297 d11rxhdr_t rxhdr;
66cbd3ab 1298 u32 tsf_l; /* TSF_L reading */
562c8850
GKH		 1299 s8 rssi; /* computed instanteneous rssi in BMAC */
1300 s8 rxpwr0; /* obsoleted, place holder for legacy ROM code. use rxpwr[] */
1301 s8 rxpwr1; /* obsoleted, place holder for legacy ROM code. use rxpwr[] */
1302 s8 do_rssi_ma; /* do per-pkt sampling for per-antenna ma in HIGH */
1303 s8 rxpwr[WL_RSSI_ANT_MAX]; /* rssi for supported antennas */
1e661086 1304} __attribute__((packed));
a9533e7e
HP		 1305
1306/* PhyRxStatus_0: */
1307#define PRXS0_FT_MASK 0x0003 /* NPHY only: CCK, OFDM, preN, N */
1308#define PRXS0_CLIP_MASK 0x000C /* NPHY only: clip count adjustment steps by AGC */
1309#define PRXS0_CLIP_SHIFT 2
1310#define PRXS0_UNSRATE 0x0010 /* PHY received a frame with unsupported rate */
1311#define PRXS0_RXANT_UPSUBBAND 0x0020 /* GPHY: rx ant, NPHY: upper sideband */
1312#define PRXS0_LCRS 0x0040 /* CCK frame only: lost crs during cck frame reception */
1313#define PRXS0_SHORTH 0x0080 /* Short Preamble */
1314#define PRXS0_PLCPFV 0x0100 /* PLCP violation */
1315#define PRXS0_PLCPHCF 0x0200 /* PLCP header integrity check failed */
1316#define PRXS0_GAIN_CTL 0x4000 /* legacy PHY gain control */
1317#define PRXS0_ANTSEL_MASK 0xF000 /* NPHY: Antennas used for received frame, bitmask */
1318#define PRXS0_ANTSEL_SHIFT 0x12
1319
1320/* subfield PRXS0_FT_MASK */
1321#define PRXS0_CCK 0x0000
1322#define PRXS0_OFDM 0x0001 /* valid only for G phy, use rxh->RxChan for A phy */
1323#define PRXS0_PREN 0x0002
1324#define PRXS0_STDN 0x0003
1325
1326/* subfield PRXS0_ANTSEL_MASK */
1327#define PRXS0_ANTSEL_0 0x0 /* antenna 0 is used */
1328#define PRXS0_ANTSEL_1 0x2 /* antenna 1 is used */
1329#define PRXS0_ANTSEL_2 0x4 /* antenna 2 is used */
1330#define PRXS0_ANTSEL_3 0x8 /* antenna 3 is used */
1331
1332/* PhyRxStatus_1: */
1333#define PRXS1_JSSI_MASK 0x00FF
1334#define PRXS1_JSSI_SHIFT 0
1335#define PRXS1_SQ_MASK 0xFF00
1336#define PRXS1_SQ_SHIFT 8
1337
1338/* nphy PhyRxStatus_1: */
1339#define PRXS1_nphy_PWR0_MASK 0x00FF
1340#define PRXS1_nphy_PWR1_MASK 0xFF00
1341
1342/* HTPHY Rx Status defines */
1343/* htphy PhyRxStatus_0: those bit are overlapped with PhyRxStatus_0 */
1344#define PRXS0_BAND 0x0400 /* 0 = 2.4G, 1 = 5G */
1345#define PRXS0_RSVD 0x0800 /* reserved; set to 0 */
1346#define PRXS0_UNUSED 0xF000 /* unused and not defined; set to 0 */
1347
1348/* htphy PhyRxStatus_1: */
1349#define PRXS1_HTPHY_CORE_MASK 0x000F /* core enables for {3..0}, 0=disabled, 1=enabled */
1350#define PRXS1_HTPHY_ANTCFG_MASK 0x00F0 /* antenna configation */
1351#define PRXS1_HTPHY_MMPLCPLenL_MASK 0xFF00 /* Mixmode PLCP Length low byte mask */
1352
1353/* htphy PhyRxStatus_2: */
1354#define PRXS2_HTPHY_MMPLCPLenH_MASK 0x000F /* Mixmode PLCP Length high byte maskw */
1355#define PRXS2_HTPHY_MMPLCH_RATE_MASK 0x00F0 /* Mixmode PLCP rate mask */
1356#define PRXS2_HTPHY_RXPWR_ANT0 0xFF00 /* Rx power on core 0 */
1357
1358/* htphy PhyRxStatus_3: */
1359#define PRXS3_HTPHY_RXPWR_ANT1 0x00FF /* Rx power on core 1 */
1360#define PRXS3_HTPHY_RXPWR_ANT2 0xFF00 /* Rx power on core 2 */
1361
1362/* htphy PhyRxStatus_4: */
1363#define PRXS4_HTPHY_RXPWR_ANT3 0x00FF /* Rx power on core 3 */
1364#define PRXS4_HTPHY_CFO 0xFF00 /* Coarse frequency offset */
1365
1366/* htphy PhyRxStatus_5: */
1367#define PRXS5_HTPHY_FFO 0x00FF /* Fine frequency offset */
1368#define PRXS5_HTPHY_AR 0xFF00 /* Advance Retard */
1369
1370#define HTPHY_MMPLCPLen(rxs) ((((rxs)->PhyRxStatus_1 & PRXS1_HTPHY_MMPLCPLenL_MASK) >> 8) | \
1371 (((rxs)->PhyRxStatus_2 & PRXS2_HTPHY_MMPLCPLenH_MASK) << 8))
1372/* Get Rx power on core 0 */
1373#define HTPHY_RXPWR_ANT0(rxs) ((((rxs)->PhyRxStatus_2) & PRXS2_HTPHY_RXPWR_ANT0) >> 8)
1374/* Get Rx power on core 1 */
1375#define HTPHY_RXPWR_ANT1(rxs) (((rxs)->PhyRxStatus_3) & PRXS3_HTPHY_RXPWR_ANT1)
1376/* Get Rx power on core 2 */
1377#define HTPHY_RXPWR_ANT2(rxs) ((((rxs)->PhyRxStatus_3) & PRXS3_HTPHY_RXPWR_ANT2) >> 8)
1378
1379/* ucode RxStatus1: */
1380#define RXS_BCNSENT 0x8000
1381#define RXS_SECKINDX_MASK 0x07e0
1382#define RXS_SECKINDX_SHIFT 5
1383#define RXS_DECERR (1 << 4)
1384#define RXS_DECATMPT (1 << 3)
1385#define RXS_PBPRES (1 << 2) /* PAD bytes to make IP data 4 bytes aligned */
1386#define RXS_RESPFRAMETX (1 << 1)
1387#define RXS_FCSERR (1 << 0)
1388
1389/* ucode RxStatus2: */
1390#define RXS_AMSDU_MASK 1
1391#define RXS_AGGTYPE_MASK 0x6
1392#define RXS_AGGTYPE_SHIFT 1
1393#define RXS_PHYRXST_VALID (1 << 8)
1394#define RXS_RXANT_MASK 0x3
1395#define RXS_RXANT_SHIFT 12
1396
1397/* RxChan */
1398#define RXS_CHAN_40 0x1000
1399#define RXS_CHAN_5G 0x0800
1400#define RXS_CHAN_ID_MASK 0x07f8
1401#define RXS_CHAN_ID_SHIFT 3
1402#define RXS_CHAN_PHYTYPE_MASK 0x0007
1403#define RXS_CHAN_PHYTYPE_SHIFT 0
1404
1405/* Index of attenuations used during ucode power control. */
1406#define M_PWRIND_BLKS (0x184 * 2)
1407#define M_PWRIND_MAP0 (M_PWRIND_BLKS + 0x0)
1408#define M_PWRIND_MAP1 (M_PWRIND_BLKS + 0x2)
1409#define M_PWRIND_MAP2 (M_PWRIND_BLKS + 0x4)
1410#define M_PWRIND_MAP3 (M_PWRIND_BLKS + 0x6)
1411/* M_PWRIND_MAP(core) macro */
1412#define M_PWRIND_MAP(core) (M_PWRIND_BLKS + ((core)<<1))
1413
1414/* PSM SHM variable offsets */
1415#define M_PSM_SOFT_REGS 0x0
1416#define M_BOM_REV_MAJOR (M_PSM_SOFT_REGS + 0x0)
1417#define M_BOM_REV_MINOR (M_PSM_SOFT_REGS + 0x2)
1418#define M_UCODE_DBGST (M_PSM_SOFT_REGS + 0x40) /* ucode debug status code */
1419#define M_UCODE_MACSTAT (M_PSM_SOFT_REGS + 0xE0) /* macstat counters */
1420
1421#define M_AGING_THRSH (0x3e * 2) /* max time waiting for medium before tx */
1422#define M_MBURST_SIZE (0x40 * 2) /* max frames in a frameburst */
1423#define M_MBURST_TXOP (0x41 * 2) /* max frameburst TXOP in unit of us */
1424#define M_SYNTHPU_DLY (0x4a * 2) /* pre-wakeup for synthpu, default: 500 */
1425#define M_PRETBTT (0x4b * 2)
1426
1427#define M_ALT_TXPWR_IDX (M_PSM_SOFT_REGS + (0x3b * 2)) /* offset to the target txpwr */
1428#define M_PHY_TX_FLT_PTR (M_PSM_SOFT_REGS + (0x3d * 2))
1429#define M_CTS_DURATION (M_PSM_SOFT_REGS + (0x5c * 2))
1430#define M_LP_RCCAL_OVR (M_PSM_SOFT_REGS + (0x6b * 2))
1431
1432/* PKTENG Rx Stats Block */
1433#define M_RXSTATS_BLK_PTR (M_PSM_SOFT_REGS + (0x65 * 2))
1434
1435/* ucode debug status codes */
1436#define DBGST_INACTIVE 0 /* not valid really */
1437#define DBGST_INIT 1 /* after zeroing SHM, before suspending at init */
1438#define DBGST_ACTIVE 2 /* "normal" state */
1439#define DBGST_SUSPENDED 3 /* suspended */
1440#define DBGST_ASLEEP 4 /* asleep (PS mode) */
1441
1442/* Scratch Reg defs */
1443typedef enum {
1444 S_RSV0 = 0,
1445 S_RSV1,
1446 S_RSV2,
1447
1448 /* scratch registers for Dot11-contants */
1449 S_DOT11_CWMIN, /* CW-minimum 0x03 */
1450 S_DOT11_CWMAX, /* CW-maximum 0x04 */
1451 S_DOT11_CWCUR, /* CW-current 0x05 */
1452 S_DOT11_SRC_LMT, /* short retry count limit 0x06 */
1453 S_DOT11_LRC_LMT, /* long retry count limit 0x07 */
1454 S_DOT11_DTIMCOUNT, /* DTIM-count 0x08 */
1455
1456 /* Tx-side scratch registers */
1457 S_SEQ_NUM, /* hardware sequence number reg 0x09 */
1458 S_SEQ_NUM_FRAG, /* seq-num for frags (Set at the start os MSDU 0x0A */
1459 S_FRMRETX_CNT, /* frame retx count 0x0B */
1460 S_SSRC, /* Station short retry count 0x0C */
1461 S_SLRC, /* Station long retry count 0x0D */
1462 S_EXP_RSP, /* Expected response frame 0x0E */
1463 S_OLD_BREM, /* Remaining backoff ctr 0x0F */
1464 S_OLD_CWWIN, /* saved-off CW-cur 0x10 */
1465 S_TXECTL, /* TXE-Ctl word constructed in scr-pad 0x11 */
1466 S_CTXTST, /* frm type-subtype as read from Tx-descr 0x12 */
1467
1468 /* Rx-side scratch registers */
1469 S_RXTST, /* Type and subtype in Rxframe 0x13 */
1470
1471 /* Global state register */
1472 S_STREG, /* state storage actual bit maps below 0x14 */
1473
1474 S_TXPWR_SUM, /* Tx power control: accumulator 0x15 */
1475 S_TXPWR_ITER, /* Tx power control: iteration 0x16 */
1476 S_RX_FRMTYPE, /* Rate and PHY type for frames 0x17 */
1477 S_THIS_AGG, /* Size of this AGG (A-MSDU) 0x18 */
1478
1479 S_KEYINDX, /* 0x19 */
1480 S_RXFRMLEN, /* Receive MPDU length in bytes 0x1A */
1481
1482 /* Receive TSF time stored in SCR */
1483 S_RXTSFTMRVAL_WD3, /* TSF value at the start of rx 0x1B */
1484 S_RXTSFTMRVAL_WD2, /* TSF value at the start of rx 0x1C */
1485 S_RXTSFTMRVAL_WD1, /* TSF value at the start of rx 0x1D */
1486 S_RXTSFTMRVAL_WD0, /* TSF value at the start of rx 0x1E */
1487 S_RXSSN, /* Received start seq number for A-MPDU BA 0x1F */
1488 S_RXQOSFLD, /* Rx-QoS field (if present) 0x20 */
1489
1490 /* Scratch pad regs used in microcode as temp storage */
1491 S_TMP0, /* stmp0 0x21 */
1492 S_TMP1, /* stmp1 0x22 */
1493 S_TMP2, /* stmp2 0x23 */
1494 S_TMP3, /* stmp3 0x24 */
1495 S_TMP4, /* stmp4 0x25 */
1496 S_TMP5, /* stmp5 0x26 */
1497 S_PRQPENALTY_CTR, /* Probe response queue penalty counter 0x27 */
1498 S_ANTCNT, /* unsuccessful attempts on current ant. 0x28 */
1499 S_SYMBOL, /* flag for possible symbol ctl frames 0x29 */
1500 S_RXTP, /* rx frame type 0x2A */
1501 S_STREG2, /* extra state storage 0x2B */
1502 S_STREG3, /* even more extra state storage 0x2C */
1503 S_STREG4, /* ... 0x2D */
1504 S_STREG5, /* remember to initialize it to zero 0x2E */
1505
1506 S_ADJPWR_IDX,
1507 S_CUR_PTR, /* Temp pointer for A-MPDU re-Tx SHM table 0x32 */
1508 S_REVID4, /* 0x33 */
1509 S_INDX, /* 0x34 */
1510 S_ADDR0, /* 0x35 */
1511 S_ADDR1, /* 0x36 */
1512 S_ADDR2, /* 0x37 */
1513 S_ADDR3, /* 0x38 */
1514 S_ADDR4, /* 0x39 */
1515 S_ADDR5, /* 0x3A */
1516 S_TMP6, /* 0x3B */
1517 S_KEYINDX_BU, /* Backup for Key index 0x3C */
1518 S_MFGTEST_TMP0, /* Temp register used for RX test calculations 0x3D */
1519 S_RXESN, /* Received end sequence number for A-MPDU BA 0x3E */
1520 S_STREG6, /* 0x3F */
1521} ePsmScratchPadRegDefinitions;
1522
1523#define S_BEACON_INDX S_OLD_BREM
1524#define S_PRS_INDX S_OLD_CWWIN
1525#define S_PHYTYPE S_SSRC
1526#define S_PHYVER S_SLRC
1527
1528/* IHR SLOW_CTRL values */
1529#define SLOW_CTRL_PDE (1 << 0)
1530#define SLOW_CTRL_FD (1 << 8)
1531
1532/* ucode mac statistic counters in shared memory */
1533typedef struct macstat {
7d4df48e
GKH		 1534 u16 txallfrm; /* 0x80 */
1535 u16 txrtsfrm; /* 0x82 */
1536 u16 txctsfrm; /* 0x84 */
1537 u16 txackfrm; /* 0x86 */
1538 u16 txdnlfrm; /* 0x88 */
1539 u16 txbcnfrm; /* 0x8a */
1540 u16 txfunfl[8]; /* 0x8c - 0x9b */
1541 u16 txtplunfl; /* 0x9c */
1542 u16 txphyerr; /* 0x9e */
1543 u16 pktengrxducast; /* 0xa0 */
1544 u16 pktengrxdmcast; /* 0xa2 */
1545 u16 rxfrmtoolong; /* 0xa4 */
1546 u16 rxfrmtooshrt; /* 0xa6 */
1547 u16 rxinvmachdr; /* 0xa8 */
1548 u16 rxbadfcs; /* 0xaa */
1549 u16 rxbadplcp; /* 0xac */
1550 u16 rxcrsglitch; /* 0xae */
1551 u16 rxstrt; /* 0xb0 */
1552 u16 rxdfrmucastmbss; /* 0xb2 */
1553 u16 rxmfrmucastmbss; /* 0xb4 */
1554 u16 rxcfrmucast; /* 0xb6 */
1555 u16 rxrtsucast; /* 0xb8 */
1556 u16 rxctsucast; /* 0xba */
1557 u16 rxackucast; /* 0xbc */
1558 u16 rxdfrmocast; /* 0xbe */
1559 u16 rxmfrmocast; /* 0xc0 */
1560 u16 rxcfrmocast; /* 0xc2 */
1561 u16 rxrtsocast; /* 0xc4 */
1562 u16 rxctsocast; /* 0xc6 */
1563 u16 rxdfrmmcast; /* 0xc8 */
1564 u16 rxmfrmmcast; /* 0xca */
1565 u16 rxcfrmmcast; /* 0xcc */
1566 u16 rxbeaconmbss; /* 0xce */
1567 u16 rxdfrmucastobss; /* 0xd0 */
1568 u16 rxbeaconobss; /* 0xd2 */
1569 u16 rxrsptmout; /* 0xd4 */
1570 u16 bcntxcancl; /* 0xd6 */
1571 u16 PAD;
1572 u16 rxf0ovfl; /* 0xda */
1573 u16 rxf1ovfl; /* 0xdc */
1574 u16 rxf2ovfl; /* 0xde */
1575 u16 txsfovfl; /* 0xe0 */
1576 u16 pmqovfl; /* 0xe2 */
1577 u16 rxcgprqfrm; /* 0xe4 */
1578 u16 rxcgprsqovfl; /* 0xe6 */
1579 u16 txcgprsfail; /* 0xe8 */
1580 u16 txcgprssuc; /* 0xea */
1581 u16 prs_timeout; /* 0xec */
1582 u16 rxnack;
1583 u16 frmscons;
1584 u16 txnack;
1585 u16 txglitch_nack;
1586 u16 txburst; /* 0xf6 # tx bursts */
1587 u16 bphy_rxcrsglitch; /* bphy rx crs glitch */
1588 u16 phywatchdog; /* 0xfa # of phy watchdog events */
1589 u16 PAD;
1590 u16 bphy_badplcp; /* bphy bad plcp */
a9533e7e
HP		 1591} macstat_t;
1592
1593/* dot11 core-specific control flags */
1594#define SICF_PCLKE 0x0004 /* PHY clock enable */
1595#define SICF_PRST 0x0008 /* PHY reset */
1596#define SICF_MPCLKE 0x0010 /* MAC PHY clockcontrol enable */
3746507a 1597#define SICF_FREF 0x0020 /* PLL FreqRefSelect */
a9533e7e 1598/* NOTE: the following bw bits only apply when the core is attached
3746507a 1599 * to a NPHY
a9533e7e
HP		 1600 */
1601#define SICF_BWMASK 0x00c0 /* phy clock mask (b6 & b7) */
1602#define SICF_BW40 0x0080 /* 40MHz BW (160MHz phyclk) */
1603#define SICF_BW20 0x0040 /* 20MHz BW (80MHz phyclk) */
1604#define SICF_BW10 0x0000 /* 10MHz BW (40MHz phyclk) */
1605#define SICF_GMODE 0x2000 /* gmode enable */
1606
1607/* dot11 core-specific status flags */
3746507a
RV		 1608#define SISF_2G_PHY 0x0001 /* 2.4G capable phy */
1609#define SISF_5G_PHY 0x0002 /* 5G capable phy */
1610#define SISF_FCLKA 0x0004 /* FastClkAvailable */
1611#define SISF_DB_PHY 0x0008 /* Dualband phy */
a9533e7e
HP		 1612
1613/* === End of MAC reg, Beginning of PHY(b/a/g/n) reg, radio and LPPHY regs are separated === */
1614
1615#define BPHY_REG_OFT_BASE 0x0
1616/* offsets for indirect access to bphy registers */
1617#define BPHY_BB_CONFIG 0x01
1618#define BPHY_ADCBIAS 0x02
1619#define BPHY_ANACORE 0x03
1620#define BPHY_PHYCRSTH 0x06
1621#define BPHY_TEST 0x0a
1622#define BPHY_PA_TX_TO 0x10
1623#define BPHY_SYNTH_DC_TO 0x11
1624#define BPHY_PA_TX_TIME_UP 0x12
1625#define BPHY_RX_FLTR_TIME_UP 0x13
1626#define BPHY_TX_POWER_OVERRIDE 0x14
1627#define BPHY_RF_OVERRIDE 0x15
1628#define BPHY_RF_TR_LOOKUP1 0x16
1629#define BPHY_RF_TR_LOOKUP2 0x17
1630#define BPHY_COEFFS 0x18
1631#define BPHY_PLL_OUT 0x19
1632#define BPHY_REFRESH_MAIN 0x1a
1633#define BPHY_REFRESH_TO0 0x1b
1634#define BPHY_REFRESH_TO1 0x1c
1635#define BPHY_RSSI_TRESH 0x20
1636#define BPHY_IQ_TRESH_HH 0x21
1637#define BPHY_IQ_TRESH_H 0x22
1638#define BPHY_IQ_TRESH_L 0x23
1639#define BPHY_IQ_TRESH_LL 0x24
1640#define BPHY_GAIN 0x25
1641#define BPHY_LNA_GAIN_RANGE 0x26
1642#define BPHY_JSSI 0x27
1643#define BPHY_TSSI_CTL 0x28
1644#define BPHY_TSSI 0x29
1645#define BPHY_TR_LOSS_CTL 0x2a
1646#define BPHY_LO_LEAKAGE 0x2b
1647#define BPHY_LO_RSSI_ACC 0x2c
1648#define BPHY_LO_IQMAG_ACC 0x2d
1649#define BPHY_TX_DC_OFF1 0x2e
1650#define BPHY_TX_DC_OFF2 0x2f
1651#define BPHY_PEAK_CNT_THRESH 0x30
1652#define BPHY_FREQ_OFFSET 0x31
1653#define BPHY_DIVERSITY_CTL 0x32
1654#define BPHY_PEAK_ENERGY_LO 0x33
1655#define BPHY_PEAK_ENERGY_HI 0x34
1656#define BPHY_SYNC_CTL 0x35
1657#define BPHY_TX_PWR_CTRL 0x36
1658#define BPHY_TX_EST_PWR 0x37
1659#define BPHY_STEP 0x38
1660#define BPHY_WARMUP 0x39
1661#define BPHY_LMS_CFF_READ 0x3a
1662#define BPHY_LMS_COEFF_I 0x3b
1663#define BPHY_LMS_COEFF_Q 0x3c
1664#define BPHY_SIG_POW 0x3d
1665#define BPHY_RFDC_CANCEL_CTL 0x3e
1666#define BPHY_HDR_TYPE 0x40
1667#define BPHY_SFD_TO 0x41
1668#define BPHY_SFD_CTL 0x42
1669#define BPHY_DEBUG 0x43
1670#define BPHY_RX_DELAY_COMP 0x44
1671#define BPHY_CRS_DROP_TO 0x45
1672#define BPHY_SHORT_SFD_NZEROS 0x46
1673#define BPHY_DSSS_COEFF1 0x48
1674#define BPHY_DSSS_COEFF2 0x49
1675#define BPHY_CCK_COEFF1 0x4a
1676#define BPHY_CCK_COEFF2 0x4b
1677#define BPHY_TR_CORR 0x4c
1678#define BPHY_ANGLE_SCALE 0x4d
1679#define BPHY_TX_PWR_BASE_IDX 0x4e
1680#define BPHY_OPTIONAL_MODES2 0x4f
1681#define BPHY_CCK_LMS_STEP 0x50
1682#define BPHY_BYPASS 0x51
1683#define BPHY_CCK_DELAY_LONG 0x52
1684#define BPHY_CCK_DELAY_SHORT 0x53
1685#define BPHY_PPROC_CHAN_DELAY 0x54
1686#define BPHY_DDFS_ENABLE 0x58
1687#define BPHY_PHASE_SCALE 0x59
1688#define BPHY_FREQ_CONTROL 0x5a
1689#define BPHY_LNA_GAIN_RANGE_10 0x5b
1690#define BPHY_LNA_GAIN_RANGE_32 0x5c
1691#define BPHY_OPTIONAL_MODES 0x5d
1692#define BPHY_RX_STATUS2 0x5e
1693#define BPHY_RX_STATUS3 0x5f
1694#define BPHY_DAC_CONTROL 0x60
1695#define BPHY_ANA11G_FILT_CTRL 0x62
1696#define BPHY_REFRESH_CTRL 0x64
1697#define BPHY_RF_OVERRIDE2 0x65
1698#define BPHY_SPUR_CANCEL_CTRL 0x66
1699#define BPHY_FINE_DIGIGAIN_CTRL 0x67
1700#define BPHY_RSSI_LUT 0x88
1701#define BPHY_RSSI_LUT_END 0xa7
1702#define BPHY_TSSI_LUT 0xa8
1703#define BPHY_TSSI_LUT_END 0xc7
1704#define BPHY_TSSI2PWR_LUT 0x380
1705#define BPHY_TSSI2PWR_LUT_END 0x39f
1706#define BPHY_LOCOMP_LUT 0x3a0
1707#define BPHY_LOCOMP_LUT_END 0x3bf
1708#define BPHY_TXGAIN_LUT 0x3c0
1709#define BPHY_TXGAIN_LUT_END 0x3ff
1710
1711/* Bits in BB_CONFIG: */
1712#define PHY_BBC_ANT_MASK 0x0180
1713#define PHY_BBC_ANT_SHIFT 7
1714#define BB_DARWIN 0x1000
1715#define BBCFG_RESETCCA 0x4000
1716#define BBCFG_RESETRX 0x8000
1717
1718/* Bits in phytest(0x0a): */
1719#define TST_DDFS 0x2000
1720#define TST_TXFILT1 0x0800
1721#define TST_UNSCRAM 0x0400
1722#define TST_CARR_SUPP 0x0200
1723#define TST_DC_COMP_LOOP 0x0100
1724#define TST_LOOPBACK 0x0080
1725#define TST_TXFILT0 0x0040
1726#define TST_TXTEST_ENABLE 0x0020
1727#define TST_TXTEST_RATE 0x0018
1728#define TST_TXTEST_PHASE 0x0007
1729
1730/* phytest txTestRate values */
1731#define TST_TXTEST_RATE_1MBPS 0
1732#define TST_TXTEST_RATE_2MBPS 1
1733#define TST_TXTEST_RATE_5_5MBPS 2
1734#define TST_TXTEST_RATE_11MBPS 3
1735#define TST_TXTEST_RATE_SHIFT 3
1736
a9533e7e
HP		 1737#define SHM_BYT_CNT 0x2 /* IHR location */
1738#define MAX_BYT_CNT 0x600 /* Maximum frame len */
1739
1740#endif /* _D11_H */
Linux kernel - Deliverables
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