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staging: brcm80211: replaced 5Ghz specific wf_channel2mhz()
[deliverable/linux.git] / drivers / staging / brcm80211 / include / d11.h
CommitLineData
a9533e7e
HP		 1/*
2 * Copyright (c) 2010 Broadcom Corporation
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
11 * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
13 * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
14 * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17#ifndef _D11_H
18#define _D11_H
19
a9533e7e
HP		 20#ifndef WL_RSSI_ANT_MAX
21#define WL_RSSI_ANT_MAX 4 /* max possible rx antennas */
22#elif WL_RSSI_ANT_MAX != 4
23#error "WL_RSSI_ANT_MAX does not match"
24#endif
25
26/* cpp contortions to concatenate w/arg prescan */
27#ifndef PAD
28#define _PADLINE(line) pad ## line
29#define _XSTR(line) _PADLINE(line)
30#define PAD _XSTR(__LINE__)
31#endif
32
33#define BCN_TMPL_LEN 512 /* length of the BCN template area */
34
35/* RX FIFO numbers */
36#define RX_FIFO 0 /* data and ctl frames */
37#define RX_TXSTATUS_FIFO 3 /* RX fifo for tx status packages */
38
39/* TX FIFO numbers using WME Access Classes */
40#define TX_AC_BK_FIFO 0 /* Access Category Background TX FIFO */
41#define TX_AC_BE_FIFO 1 /* Access Category Best-Effort TX FIFO */
42#define TX_AC_VI_FIFO 2 /* Access Class Video TX FIFO */
43#define TX_AC_VO_FIFO 3 /* Access Class Voice TX FIFO */
44#define TX_BCMC_FIFO 4 /* Broadcast/Multicast TX FIFO */
45#define TX_ATIM_FIFO 5 /* TX fifo for ATIM window info */
46
47/* Addr is byte address used by SW; offset is word offset used by uCode */
48
49/* Per AC TX limit settings */
50#define M_AC_TXLMT_BASE_ADDR (0x180 * 2)
51#define M_AC_TXLMT_ADDR(_ac) (M_AC_TXLMT_BASE_ADDR + (2 * (_ac)))
52
53/* Legacy TX FIFO numbers */
54#define TX_DATA_FIFO TX_AC_BE_FIFO
55#define TX_CTL_FIFO TX_AC_VO_FIFO
56
57typedef volatile struct {
66cbd3ab
GKH		 58 u32 intstatus;
59 u32 intmask;
a9533e7e
HP		 60} intctrlregs_t;
61
62/* read: 32-bit register that can be read as 32-bit or as 2 16-bit
63 * write: only low 16b-it half can be written
64 */
65typedef volatile union {
66cbd3ab 66 u32 pmqhostdata; /* read only! */
a9533e7e 67 struct {
7d4df48e
GKH		 68 u16 pmqctrlstatus; /* read/write */
69 u16 PAD;
a9533e7e
HP		 70 } w;
71} pmqreg_t;
72
73/* pio register set 2/4 bytes union for d11 fifo */
74typedef volatile union {
75 pio2regp_t b2; /* < corerev 8 */
76 pio4regp_t b4; /* >= corerev 8 */
77} u_pioreg_t;
78
79/* dma/pio corerev < 11 */
80typedef volatile struct {
81 dma32regp_t dmaregs[8]; /* 0x200 - 0x2fc */
82 u_pioreg_t pioregs[8]; /* 0x300 */
83} fifo32_t;
84
85/* dma/pio corerev >= 11 */
86typedef volatile struct {
87 dma64regs_t dmaxmt; /* dma tx */
88 pio4regs_t piotx; /* pio tx */
89 dma64regs_t dmarcv; /* dma rx */
90 pio4regs_t piorx; /* pio rx */
91} fifo64_t;
92
93/*
94 * Host Interface Registers
95 * - primed from hnd_cores/dot11mac/systemC/registers/ihr.h
96 * - but definitely not complete
97 */
98typedef volatile struct _d11regs {
99 /* Device Control ("semi-standard host registers") */
66cbd3ab
GKH		 100 u32 PAD[3]; /* 0x0 - 0x8 */
101 u32 biststatus; /* 0xC */
102 u32 biststatus2; /* 0x10 */
103 u32 PAD; /* 0x14 */
104 u32 gptimer; /* 0x18 *//* for corerev >= 3 */
105 u32 usectimer; /* 0x1c *//* for corerev >= 26 */
a9533e7e
HP		 106
107 /* Interrupt Control *//* 0x20 */
108 intctrlregs_t intctrlregs[8];
109
66cbd3ab 110 u32 PAD[40]; /* 0x60 - 0xFC */
a9533e7e
HP		 111
112 /* tx fifos 6-7 and rx fifos 1-3 removed in corerev 5 */
66cbd3ab 113 u32 intrcvlazy[4]; /* 0x100 - 0x10C */
a9533e7e 114
66cbd3ab 115 u32 PAD[4]; /* 0x110 - 0x11c */
a9533e7e 116
66cbd3ab
GKH		 117 u32 maccontrol; /* 0x120 */
118 u32 maccommand; /* 0x124 */
119 u32 macintstatus; /* 0x128 */
120 u32 macintmask; /* 0x12C */
a9533e7e
HP		 121
122 /* Transmit Template Access */
66cbd3ab
GKH		 123 u32 tplatewrptr; /* 0x130 */
124 u32 tplatewrdata; /* 0x134 */
125 u32 PAD[2]; /* 0x138 - 0x13C */
a9533e7e
HP		 126
127 /* PMQ registers */
128 pmqreg_t pmqreg; /* 0x140 */
66cbd3ab
GKH		 129 u32 pmqpatl; /* 0x144 */
130 u32 pmqpath; /* 0x148 */
131 u32 PAD; /* 0x14C */
a9533e7e 132
66cbd3ab
GKH		 133 u32 chnstatus; /* 0x150 */
134 u32 psmdebug; /* 0x154 *//* for corerev >= 3 */
135 u32 phydebug; /* 0x158 *//* for corerev >= 3 */
136 u32 machwcap; /* 0x15C *//* Corerev >= 13 */
a9533e7e
HP		 137
138 /* Extended Internal Objects */
66cbd3ab
GKH		 139 u32 objaddr; /* 0x160 */
140 u32 objdata; /* 0x164 */
141 u32 PAD[2]; /* 0x168 - 0x16c */
a9533e7e
HP		 142
143 /* New txstatus registers on corerev >= 5 */
66cbd3ab
GKH		 144 u32 frmtxstatus; /* 0x170 */
145 u32 frmtxstatus2; /* 0x174 */
146 u32 PAD[2]; /* 0x178 - 0x17c */
a9533e7e
HP		 147
148 /* New TSF host access on corerev >= 3 */
149
66cbd3ab
GKH		 150 u32 tsf_timerlow; /* 0x180 */
151 u32 tsf_timerhigh; /* 0x184 */
152 u32 tsf_cfprep; /* 0x188 */
153 u32 tsf_cfpstart; /* 0x18c */
154 u32 tsf_cfpmaxdur32; /* 0x190 */
155 u32 PAD[3]; /* 0x194 - 0x19c */
a9533e7e 156
66cbd3ab
GKH		 157 u32 maccontrol1; /* 0x1a0 */
158 u32 machwcap1; /* 0x1a4 */
159 u32 PAD[14]; /* 0x1a8 - 0x1dc */
a9533e7e
HP		 160
161 /* Clock control and hardware workarounds (corerev >= 13) */
66cbd3ab
GKH		 162 u32 clk_ctl_st; /* 0x1e0 */
163 u32 hw_war;
164 u32 d11_phypllctl; /* 0x1e8 (corerev == 16), the phypll request/avail bits are
a9533e7e
HP		 165 * moved to clk_ctl_st for corerev >= 17
166 */
66cbd3ab 167 u32 PAD[5]; /* 0x1ec - 0x1fc */
a9533e7e
HP		 168
169 /* 0x200-0x37F dma/pio registers */
170 volatile union {
171 fifo32_t f32regs; /* tx fifos 6-7 and rx fifos 1-3 (corerev < 5) */
172 fifo64_t f64regs[6]; /* on corerev >= 11 */
173 } fifo;
174
175 /* FIFO diagnostic port access */
176 dma32diag_t dmafifo; /* 0x380 - 0x38C */
177
66cbd3ab
GKH		 178 u32 aggfifocnt; /* 0x390 */
179 u32 aggfifodata; /* 0x394 */
180 u32 PAD[16]; /* 0x398 - 0x3d4 */
7d4df48e
GKH		 181 u16 radioregaddr; /* 0x3d8 */
182 u16 radioregdata; /* 0x3da */
a9533e7e
HP		 183
184 /* time delay between the change on rf disable input and radio shutdown corerev 10 */
66cbd3ab 185 u32 rfdisabledly; /* 0x3DC */
a9533e7e
HP		 186
187 /* PHY register access */
7d4df48e
GKH		 188 u16 phyversion; /* 0x3e0 - 0x0 */
189 u16 phybbconfig; /* 0x3e2 - 0x1 */
190 u16 phyadcbias; /* 0x3e4 - 0x2 Bphy only */
191 u16 phyanacore; /* 0x3e6 - 0x3 pwwrdwn on aphy */
192 u16 phyrxstatus0; /* 0x3e8 - 0x4 */
193 u16 phyrxstatus1; /* 0x3ea - 0x5 */
194 u16 phycrsth; /* 0x3ec - 0x6 */
195 u16 phytxerror; /* 0x3ee - 0x7 */
196 u16 phychannel; /* 0x3f0 - 0x8 */
197 u16 PAD[1]; /* 0x3f2 - 0x9 */
198 u16 phytest; /* 0x3f4 - 0xa */
199 u16 phy4waddr; /* 0x3f6 - 0xb */
200 u16 phy4wdatahi; /* 0x3f8 - 0xc */
201 u16 phy4wdatalo; /* 0x3fa - 0xd */
202 u16 phyregaddr; /* 0x3fc - 0xe */
203 u16 phyregdata; /* 0x3fe - 0xf */
a9533e7e
HP		 204
205 /* IHR *//* 0x400 - 0x7FE */
206
207 /* RXE Block */
7d4df48e
GKH		 208 u16 PAD[3]; /* 0x400 - 0x406 */
209 u16 rcv_fifo_ctl; /* 0x406 */
210 u16 PAD; /* 0x408 - 0x40a */
211 u16 rcv_frm_cnt; /* 0x40a */
212 u16 PAD[4]; /* 0x40a - 0x414 */
213 u16 rssi; /* 0x414 */
214 u16 PAD[5]; /* 0x414 - 0x420 */
215 u16 rcm_ctl; /* 0x420 */
216 u16 rcm_mat_data; /* 0x422 */
217 u16 rcm_mat_mask; /* 0x424 */
218 u16 rcm_mat_dly; /* 0x426 */
219 u16 rcm_cond_mask_l; /* 0x428 */
220 u16 rcm_cond_mask_h; /* 0x42A */
221 u16 rcm_cond_dly; /* 0x42C */
222 u16 PAD[1]; /* 0x42E */
223 u16 ext_ihr_addr; /* 0x430 */
224 u16 ext_ihr_data; /* 0x432 */
225 u16 rxe_phyrs_2; /* 0x434 */
226 u16 rxe_phyrs_3; /* 0x436 */
227 u16 phy_mode; /* 0x438 */
228 u16 rcmta_ctl; /* 0x43a */
229 u16 rcmta_size; /* 0x43c */
230 u16 rcmta_addr0; /* 0x43e */
231 u16 rcmta_addr1; /* 0x440 */
232 u16 rcmta_addr2; /* 0x442 */
233 u16 PAD[30]; /* 0x444 - 0x480 */
a9533e7e
HP		 234
235 /* PSM Block *//* 0x480 - 0x500 */
236
7d4df48e
GKH		 237 u16 PAD; /* 0x480 */
238 u16 psm_maccontrol_h; /* 0x482 */
239 u16 psm_macintstatus_l; /* 0x484 */
240 u16 psm_macintstatus_h; /* 0x486 */
241 u16 psm_macintmask_l; /* 0x488 */
242 u16 psm_macintmask_h; /* 0x48A */
243 u16 PAD; /* 0x48C */
244 u16 psm_maccommand; /* 0x48E */
245 u16 psm_brc; /* 0x490 */
246 u16 psm_phy_hdr_param; /* 0x492 */
247 u16 psm_postcard; /* 0x494 */
248 u16 psm_pcard_loc_l; /* 0x496 */
249 u16 psm_pcard_loc_h; /* 0x498 */
250 u16 psm_gpio_in; /* 0x49A */
251 u16 psm_gpio_out; /* 0x49C */
252 u16 psm_gpio_oe; /* 0x49E */
253
254 u16 psm_bred_0; /* 0x4A0 */
255 u16 psm_bred_1; /* 0x4A2 */
256 u16 psm_bred_2; /* 0x4A4 */
257 u16 psm_bred_3; /* 0x4A6 */
258 u16 psm_brcl_0; /* 0x4A8 */
259 u16 psm_brcl_1; /* 0x4AA */
260 u16 psm_brcl_2; /* 0x4AC */
261 u16 psm_brcl_3; /* 0x4AE */
262 u16 psm_brpo_0; /* 0x4B0 */
263 u16 psm_brpo_1; /* 0x4B2 */
264 u16 psm_brpo_2; /* 0x4B4 */
265 u16 psm_brpo_3; /* 0x4B6 */
266 u16 psm_brwk_0; /* 0x4B8 */
267 u16 psm_brwk_1; /* 0x4BA */
268 u16 psm_brwk_2; /* 0x4BC */
269 u16 psm_brwk_3; /* 0x4BE */
270
271 u16 psm_base_0; /* 0x4C0 */
272 u16 psm_base_1; /* 0x4C2 */
273 u16 psm_base_2; /* 0x4C4 */
274 u16 psm_base_3; /* 0x4C6 */
275 u16 psm_base_4; /* 0x4C8 */
276 u16 psm_base_5; /* 0x4CA */
277 u16 psm_base_6; /* 0x4CC */
278 u16 psm_pc_reg_0; /* 0x4CE */
279 u16 psm_pc_reg_1; /* 0x4D0 */
280 u16 psm_pc_reg_2; /* 0x4D2 */
281 u16 psm_pc_reg_3; /* 0x4D4 */
282 u16 PAD[0xD]; /* 0x4D6 - 0x4DE */
283 u16 psm_corectlsts; /* 0x4f0 *//* Corerev >= 13 */
284 u16 PAD[0x7]; /* 0x4f2 - 0x4fE */
a9533e7e
HP		 285
286 /* TXE0 Block *//* 0x500 - 0x580 */
7d4df48e
GKH		 287 u16 txe_ctl; /* 0x500 */
288 u16 txe_aux; /* 0x502 */
289 u16 txe_ts_loc; /* 0x504 */
290 u16 txe_time_out; /* 0x506 */
291 u16 txe_wm_0; /* 0x508 */
292 u16 txe_wm_1; /* 0x50A */
293 u16 txe_phyctl; /* 0x50C */
294 u16 txe_status; /* 0x50E */
295 u16 txe_mmplcp0; /* 0x510 */
296 u16 txe_mmplcp1; /* 0x512 */
297 u16 txe_phyctl1; /* 0x514 */
298
299 u16 PAD[0x05]; /* 0x510 - 0x51E */
a9533e7e
HP		 300
301 /* Transmit control */
7d4df48e
GKH		 302 u16 xmtfifodef; /* 0x520 */
303 u16 xmtfifo_frame_cnt; /* 0x522 *//* Corerev >= 16 */
304 u16 xmtfifo_byte_cnt; /* 0x524 *//* Corerev >= 16 */
305 u16 xmtfifo_head; /* 0x526 *//* Corerev >= 16 */
306 u16 xmtfifo_rd_ptr; /* 0x528 *//* Corerev >= 16 */
307 u16 xmtfifo_wr_ptr; /* 0x52A *//* Corerev >= 16 */
308 u16 xmtfifodef1; /* 0x52C *//* Corerev >= 16 */
309
310 u16 PAD[0x09]; /* 0x52E - 0x53E */
311
312 u16 xmtfifocmd; /* 0x540 */
313 u16 xmtfifoflush; /* 0x542 */
314 u16 xmtfifothresh; /* 0x544 */
315 u16 xmtfifordy; /* 0x546 */
316 u16 xmtfifoprirdy; /* 0x548 */
317 u16 xmtfiforqpri; /* 0x54A */
318 u16 xmttplatetxptr; /* 0x54C */
319 u16 PAD; /* 0x54E */
320 u16 xmttplateptr; /* 0x550 */
321 u16 smpl_clct_strptr; /* 0x552 *//* Corerev >= 22 */
322 u16 smpl_clct_stpptr; /* 0x554 *//* Corerev >= 22 */
323 u16 smpl_clct_curptr; /* 0x556 *//* Corerev >= 22 */
324 u16 PAD[0x04]; /* 0x558 - 0x55E */
325 u16 xmttplatedatalo; /* 0x560 */
326 u16 xmttplatedatahi; /* 0x562 */
327
328 u16 PAD[2]; /* 0x564 - 0x566 */
329
330 u16 xmtsel; /* 0x568 */
331 u16 xmttxcnt; /* 0x56A */
332 u16 xmttxshmaddr; /* 0x56C */
333
334 u16 PAD[0x09]; /* 0x56E - 0x57E */
a9533e7e
HP		 335
336 /* TXE1 Block */
7d4df48e 337 u16 PAD[0x40]; /* 0x580 - 0x5FE */
a9533e7e
HP		 338
339 /* TSF Block */
7d4df48e
GKH		 340 u16 PAD[0X02]; /* 0x600 - 0x602 */
341 u16 tsf_cfpstrt_l; /* 0x604 */
342 u16 tsf_cfpstrt_h; /* 0x606 */
343 u16 PAD[0X05]; /* 0x608 - 0x610 */
344 u16 tsf_cfppretbtt; /* 0x612 */
345 u16 PAD[0XD]; /* 0x614 - 0x62C */
346 u16 tsf_clk_frac_l; /* 0x62E */
347 u16 tsf_clk_frac_h; /* 0x630 */
348 u16 PAD[0X14]; /* 0x632 - 0x658 */
349 u16 tsf_random; /* 0x65A */
350 u16 PAD[0x05]; /* 0x65C - 0x664 */
a9533e7e 351 /* GPTimer 2 registers are corerev >= 3 */
7d4df48e
GKH		 352 u16 tsf_gpt2_stat; /* 0x666 */
353 u16 tsf_gpt2_ctr_l; /* 0x668 */
354 u16 tsf_gpt2_ctr_h; /* 0x66A */
355 u16 tsf_gpt2_val_l; /* 0x66C */
356 u16 tsf_gpt2_val_h; /* 0x66E */
357 u16 tsf_gptall_stat; /* 0x670 */
358 u16 PAD[0x07]; /* 0x672 - 0x67E */
a9533e7e
HP		 359
360 /* IFS Block */
7d4df48e
GKH		 361 u16 ifs_sifs_rx_tx_tx; /* 0x680 */
362 u16 ifs_sifs_nav_tx; /* 0x682 */
363 u16 ifs_slot; /* 0x684 */
364 u16 PAD; /* 0x686 */
365 u16 ifs_ctl; /* 0x688 */
366 u16 PAD[0x3]; /* 0x68a - 0x68F */
367 u16 ifsstat; /* 0x690 */
368 u16 ifsmedbusyctl; /* 0x692 */
369 u16 iftxdur; /* 0x694 */
370 u16 PAD[0x3]; /* 0x696 - 0x69b */
a9533e7e 371 /* EDCF support in dot11macs with corerevs >= 16 */
7d4df48e
GKH		 372 u16 ifs_aifsn; /* 0x69c */
373 u16 ifs_ctl1; /* 0x69e */
a9533e7e
HP		 374
375 /* New slow clock registers on corerev >= 5 */
7d4df48e
GKH		 376 u16 scc_ctl; /* 0x6a0 */
377 u16 scc_timer_l; /* 0x6a2 */
378 u16 scc_timer_h; /* 0x6a4 */
379 u16 scc_frac; /* 0x6a6 */
380 u16 scc_fastpwrup_dly; /* 0x6a8 */
381 u16 scc_per; /* 0x6aa */
382 u16 scc_per_frac; /* 0x6ac */
383 u16 scc_cal_timer_l; /* 0x6ae */
384 u16 scc_cal_timer_h; /* 0x6b0 */
385 u16 PAD; /* 0x6b2 */
386
387 u16 PAD[0x26];
a9533e7e
HP		 388
389 /* NAV Block */
7d4df48e
GKH		 390 u16 nav_ctl; /* 0x700 */
391 u16 navstat; /* 0x702 */
392 u16 PAD[0x3e]; /* 0x702 - 0x77E */
a9533e7e
HP		 393
394 /* WEP/PMQ Block *//* 0x780 - 0x7FE */
7d4df48e
GKH		 395 u16 PAD[0x20]; /* 0x780 - 0x7BE */
396
397 u16 wepctl; /* 0x7C0 */
398 u16 wepivloc; /* 0x7C2 */
399 u16 wepivkey; /* 0x7C4 */
400 u16 wepwkey; /* 0x7C6 */
401
402 u16 PAD[4]; /* 0x7C8 - 0x7CE */
403 u16 pcmctl; /* 0X7D0 */
404 u16 pcmstat; /* 0X7D2 */
405 u16 PAD[6]; /* 0x7D4 - 0x7DE */
406
407 u16 pmqctl; /* 0x7E0 */
408 u16 pmqstatus; /* 0x7E2 */
409 u16 pmqpat0; /* 0x7E4 */
410 u16 pmqpat1; /* 0x7E6 */
411 u16 pmqpat2; /* 0x7E8 */
412
413 u16 pmqdat; /* 0x7EA */
414 u16 pmqdator; /* 0x7EC */
415 u16 pmqhst; /* 0x7EE */
416 u16 pmqpath0; /* 0x7F0 */
417 u16 pmqpath1; /* 0x7F2 */
418 u16 pmqpath2; /* 0x7F4 */
419 u16 pmqdath; /* 0x7F6 */
420
421 u16 PAD[0x04]; /* 0x7F8 - 0x7FE */
a9533e7e
HP		 422
423 /* SHM *//* 0x800 - 0xEFE */
7d4df48e 424 u16 PAD[0x380]; /* 0x800 - 0xEFE */
a9533e7e
HP		 425
426 /* SB configuration registers: 0xF00 */
427 sbconfig_t sbconfig; /* sb config regs occupy top 256 bytes */
428} d11regs_t;
429
430#define PIHR_BASE 0x0400 /* byte address of packed IHR region */
431
432/* biststatus */
433#define BT_DONE (1U << 31) /* bist done */
434#define BT_B2S (1 << 30) /* bist2 ram summary bit */
435
436/* intstatus and intmask */
437#define I_PC (1 << 10) /* pci descriptor error */
438#define I_PD (1 << 11) /* pci data error */
439#define I_DE (1 << 12) /* descriptor protocol error */
440#define I_RU (1 << 13) /* receive descriptor underflow */
441#define I_RO (1 << 14) /* receive fifo overflow */
442#define I_XU (1 << 15) /* transmit fifo underflow */
443#define I_RI (1 << 16) /* receive interrupt */
444#define I_XI (1 << 24) /* transmit interrupt */
445
446/* interrupt receive lazy */
447#define IRL_TO_MASK 0x00ffffff /* timeout */
448#define IRL_FC_MASK 0xff000000 /* frame count */
449#define IRL_FC_SHIFT 24 /* frame count */
450
451/* maccontrol register */
452#define MCTL_GMODE (1U << 31)
453#define MCTL_DISCARD_PMQ (1 << 30)
454#define MCTL_WAKE (1 << 26)
455#define MCTL_HPS (1 << 25)
456#define MCTL_PROMISC (1 << 24)
457#define MCTL_KEEPBADFCS (1 << 23)
458#define MCTL_KEEPCONTROL (1 << 22)
459#define MCTL_PHYLOCK (1 << 21)
460#define MCTL_BCNS_PROMISC (1 << 20)
461#define MCTL_LOCK_RADIO (1 << 19)
462#define MCTL_AP (1 << 18)
463#define MCTL_INFRA (1 << 17)
464#define MCTL_BIGEND (1 << 16)
465#define MCTL_GPOUT_SEL_MASK (3 << 14)
466#define MCTL_GPOUT_SEL_SHIFT 14
467#define MCTL_EN_PSMDBG (1 << 13)
468#define MCTL_IHR_EN (1 << 10)
469#define MCTL_SHM_UPPER (1 << 9)
470#define MCTL_SHM_EN (1 << 8)
471#define MCTL_PSM_JMP_0 (1 << 2)
472#define MCTL_PSM_RUN (1 << 1)
473#define MCTL_EN_MAC (1 << 0)
474
475/* maccommand register */
476#define MCMD_BCN0VLD (1 << 0)
477#define MCMD_BCN1VLD (1 << 1)
478#define MCMD_DIRFRMQVAL (1 << 2)
479#define MCMD_CCA (1 << 3)
480#define MCMD_BG_NOISE (1 << 4)
481#define MCMD_SKIP_SHMINIT (1 << 5) /* only used for simulation */
482#define MCMD_SAMPLECOLL MCMD_SKIP_SHMINIT /* reuse for sample collect */
483
484/* macintstatus/macintmask */
485#define MI_MACSSPNDD (1 << 0) /* MAC has gracefully suspended */
486#define MI_BCNTPL (1 << 1) /* beacon template available */
487#define MI_TBTT (1 << 2) /* TBTT indication */
488#define MI_BCNSUCCESS (1 << 3) /* beacon successfully tx'd */
489#define MI_BCNCANCLD (1 << 4) /* beacon canceled (IBSS) */
490#define MI_ATIMWINEND (1 << 5) /* end of ATIM-window (IBSS) */
491#define MI_PMQ (1 << 6) /* PMQ entries available */
492#define MI_NSPECGEN_0 (1 << 7) /* non-specific gen-stat bits that are set by PSM */
493#define MI_NSPECGEN_1 (1 << 8) /* non-specific gen-stat bits that are set by PSM */
494#define MI_MACTXERR (1 << 9) /* MAC level Tx error */
495#define MI_NSPECGEN_3 (1 << 10) /* non-specific gen-stat bits that are set by PSM */
496#define MI_PHYTXERR (1 << 11) /* PHY Tx error */
497#define MI_PME (1 << 12) /* Power Management Event */
498#define MI_GP0 (1 << 13) /* General-purpose timer0 */
499#define MI_GP1 (1 << 14) /* General-purpose timer1 */
500#define MI_DMAINT (1 << 15) /* (ORed) DMA-interrupts */
501#define MI_TXSTOP (1 << 16) /* MAC has completed a TX FIFO Suspend/Flush */
502#define MI_CCA (1 << 17) /* MAC has completed a CCA measurement */
503#define MI_BG_NOISE (1 << 18) /* MAC has collected background noise samples */
504#define MI_DTIM_TBTT (1 << 19) /* MBSS DTIM TBTT indication */
505#define MI_PRQ (1 << 20) /* Probe response queue needs attention */
506#define MI_PWRUP (1 << 21) /* Radio/PHY has been powered back up. */
507#define MI_RESERVED3 (1 << 22)
508#define MI_RESERVED2 (1 << 23)
509#define MI_RESERVED1 (1 << 25)
510#define MI_RFDISABLE (1 << 28) /* MAC detected a change on RF Disable input
511 * (corerev >= 10)
512 */
513#define MI_TFS (1 << 29) /* MAC has completed a TX (corerev >= 5) */
514#define MI_PHYCHANGED (1 << 30) /* A phy status change wrt G mode */
515#define MI_TO (1U << 31) /* general purpose timeout (corerev >= 3) */
516
517/* Mac capabilities registers */
518/* machwcap */
519#define MCAP_TKIPMIC 0x80000000 /* TKIP MIC hardware present */
520
521/* pmqhost data */
522#define PMQH_DATA_MASK 0xffff0000 /* data entry of head pmq entry */
523#define PMQH_BSSCFG 0x00100000 /* PM entry for BSS config */
524#define PMQH_PMOFF 0x00010000 /* PM Mode OFF: power save off */
525#define PMQH_PMON 0x00020000 /* PM Mode ON: power save on */
526#define PMQH_DASAT 0x00040000 /* Dis-associated or De-authenticated */
527#define PMQH_ATIMFAIL 0x00080000 /* ATIM not acknowledged */
528#define PMQH_DEL_ENTRY 0x00000001 /* delete head entry */
529#define PMQH_DEL_MULT 0x00000002 /* delete head entry to cur read pointer -1 */
530#define PMQH_OFLO 0x00000004 /* pmq overflow indication */
531#define PMQH_NOT_EMPTY 0x00000008 /* entries are present in pmq */
532
533/* phydebug (corerev >= 3) */
534#define PDBG_CRS (1 << 0) /* phy is asserting carrier sense */
535#define PDBG_TXA (1 << 1) /* phy is taking xmit byte from mac this cycle */
536#define PDBG_TXF (1 << 2) /* mac is instructing the phy to transmit a frame */
537#define PDBG_TXE (1 << 3) /* phy is signalling a transmit Error to the mac */
538#define PDBG_RXF (1 << 4) /* phy detected the end of a valid frame preamble */
539#define PDBG_RXS (1 << 5) /* phy detected the end of a valid PLCP header */
540#define PDBG_RXFRG (1 << 6) /* rx start not asserted */
541#define PDBG_RXV (1 << 7) /* mac is taking receive byte from phy this cycle */
542#define PDBG_RFD (1 << 16) /* RF portion of the radio is disabled */
543
544/* objaddr register */
545#define OBJADDR_SEL_MASK 0x000F0000
546#define OBJADDR_UCM_SEL 0x00000000
547#define OBJADDR_SHM_SEL 0x00010000
548#define OBJADDR_SCR_SEL 0x00020000
549#define OBJADDR_IHR_SEL 0x00030000
550#define OBJADDR_RCMTA_SEL 0x00040000
551#define OBJADDR_SRCHM_SEL 0x00060000
552#define OBJADDR_WINC 0x01000000
553#define OBJADDR_RINC 0x02000000
554#define OBJADDR_AUTO_INC 0x03000000
555
556#define WEP_PCMADDR 0x07d4
557#define WEP_PCMDATA 0x07d6
558
559/* frmtxstatus */
560#define TXS_V (1 << 0) /* valid bit */
561#define TXS_STATUS_MASK 0xffff
562/* sw mask to map txstatus for corerevs <= 4 to be the same as for corerev > 4 */
563#define TXS_COMPAT_MASK 0x3
564#define TXS_COMPAT_SHIFT 1
565#define TXS_FID_MASK 0xffff0000
566#define TXS_FID_SHIFT 16
567
568/* frmtxstatus2 */
569#define TXS_SEQ_MASK 0xffff
570#define TXS_PTX_MASK 0xff0000
571#define TXS_PTX_SHIFT 16
572#define TXS_MU_MASK 0x01000000
573#define TXS_MU_SHIFT 24
574
575/* clk_ctl_st, corerev >= 17 */
576#define CCS_ERSRC_REQ_D11PLL 0x00000100 /* d11 core pll request */
577#define CCS_ERSRC_REQ_PHYPLL 0x00000200 /* PHY pll request */
578#define CCS_ERSRC_AVAIL_D11PLL 0x01000000 /* d11 core pll available */
579#define CCS_ERSRC_AVAIL_PHYPLL 0x02000000 /* PHY pll available */
580
581/* HT Cloclk Ctrl and Clock Avail for 4313 */
582#define CCS_ERSRC_REQ_HT 0x00000010 /* HT avail request */
583#define CCS_ERSRC_AVAIL_HT 0x00020000 /* HT clock available */
584
585/* d11_pwrctl, corerev16 only */
586#define D11_PHYPLL_AVAIL_REQ 0x000010000 /* request PHY PLL resource */
587#define D11_PHYPLL_AVAIL_STS 0x001000000 /* PHY PLL is available */
588
589/* tsf_cfprep register */
590#define CFPREP_CBI_MASK 0xffffffc0
591#define CFPREP_CBI_SHIFT 6
592#define CFPREP_CFPP 0x00000001
593
594/* tx fifo sizes for corerev >= 9 */
595/* tx fifo sizes values are in terms of 256 byte blocks */
596#define TXFIFOCMD_RESET_MASK (1 << 15) /* reset */
597#define TXFIFOCMD_FIFOSEL_SHIFT 8 /* fifo */
598#define TXFIFO_FIFOTOP_SHIFT 8 /* fifo start */
599
600#define TXFIFO_START_BLK16 65 /* Base address + 32 * 512 B/P */
601#define TXFIFO_START_BLK 6 /* Base address + 6 * 256 B */
602#define TXFIFO_SIZE_UNIT 256 /* one unit corresponds to 256 bytes */
603#define MBSS16_TEMPLMEM_MINBLKS 65 /* one unit corresponds to 256 bytes */
604
605/* phy versions, PhyVersion:Revision field */
606#define PV_AV_MASK 0xf000 /* analog block version */
607#define PV_AV_SHIFT 12 /* analog block version bitfield offset */
608#define PV_PT_MASK 0x0f00 /* phy type */
609#define PV_PT_SHIFT 8 /* phy type bitfield offset */
610#define PV_PV_MASK 0x000f /* phy version */
611#define PHY_TYPE(v) ((v & PV_PT_MASK) >> PV_PT_SHIFT)
612
613/* phy types, PhyVersion:PhyType field */
614#define PHY_TYPE_N 4 /* N-Phy value */
615#define PHY_TYPE_SSN 6 /* SSLPN-Phy value */
616#define PHY_TYPE_LCN 8 /* LCN-Phy value */
617#define PHY_TYPE_LCNXN 9 /* LCNXN-Phy value */
618#define PHY_TYPE_NULL 0xf /* Invalid Phy value */
619
620/* analog types, PhyVersion:AnalogType field */
621#define ANA_11N_013 5
622
623/* 802.11a PLCP header def */
624typedef struct ofdm_phy_hdr ofdm_phy_hdr_t;
1e661086 625struct ofdm_phy_hdr {
de9bca63 626 u8 rlpt[3]; /* rate, length, parity, tail */
7d4df48e 627 u16 service;
de9bca63 628 u8 pad;
1e661086 629} __attribute__((packed));
a9533e7e
HP		 630
631#define D11A_PHY_HDR_GRATE(phdr) ((phdr)->rlpt[0] & 0x0f)
632#define D11A_PHY_HDR_GRES(phdr) (((phdr)->rlpt[0] >> 4) & 0x01)
66cbd3ab 633#define D11A_PHY_HDR_GLENGTH(phdr) (((u32 *)((phdr)->rlpt) >> 5) & 0x0fff)
a9533e7e
HP		 634#define D11A_PHY_HDR_GPARITY(phdr) (((phdr)->rlpt[3] >> 1) & 0x01)
635#define D11A_PHY_HDR_GTAIL(phdr) (((phdr)->rlpt[3] >> 2) & 0x3f)
636
637/* rate encoded per 802.11a-1999 sec 17.3.4.1 */
638#define D11A_PHY_HDR_SRATE(phdr, rate) \
639 ((phdr)->rlpt[0] = ((phdr)->rlpt[0] & 0xf0) | ((rate) & 0xf))
640/* set reserved field to zero */
641#define D11A_PHY_HDR_SRES(phdr) ((phdr)->rlpt[0] &= 0xef)
642/* length is number of octets in PSDU */
643#define D11A_PHY_HDR_SLENGTH(phdr, length) \
66cbd3ab 644 (*(u32 *)((phdr)->rlpt) = *(u32 *)((phdr)->rlpt) | \
a9533e7e
HP		 645 (((length) & 0x0fff) << 5))
646/* set the tail to all zeros */
647#define D11A_PHY_HDR_STAIL(phdr) ((phdr)->rlpt[3] &= 0x03)
648
649#define D11A_PHY_HDR_LEN_L 3 /* low-rate part of PLCP header */
650#define D11A_PHY_HDR_LEN_R 2 /* high-rate part of PLCP header */
651
652#define D11A_PHY_TX_DELAY (2) /* 2.1 usec */
653
654#define D11A_PHY_HDR_TIME (4) /* low-rate part of PLCP header */
655#define D11A_PHY_PRE_TIME (16)
656#define D11A_PHY_PREHDR_TIME (D11A_PHY_PRE_TIME + D11A_PHY_HDR_TIME)
657
658/* 802.11b PLCP header def */
659typedef struct cck_phy_hdr cck_phy_hdr_t;
1e661086 660struct cck_phy_hdr {
de9bca63
GKH		 661 u8 signal;
662 u8 service;
7d4df48e
GKH		 663 u16 length;
664 u16 crc;
1e661086 665} __attribute__((packed));
a9533e7e
HP		 666
667#define D11B_PHY_HDR_LEN 6
668
669#define D11B_PHY_TX_DELAY (3) /* 3.4 usec */
670
671#define D11B_PHY_LHDR_TIME (D11B_PHY_HDR_LEN << 3)
672#define D11B_PHY_LPRE_TIME (144)
673#define D11B_PHY_LPREHDR_TIME (D11B_PHY_LPRE_TIME + D11B_PHY_LHDR_TIME)
674
675#define D11B_PHY_SHDR_TIME (D11B_PHY_LHDR_TIME >> 1)
676#define D11B_PHY_SPRE_TIME (D11B_PHY_LPRE_TIME >> 1)
677#define D11B_PHY_SPREHDR_TIME (D11B_PHY_SPRE_TIME + D11B_PHY_SHDR_TIME)
678
679#define D11B_PLCP_SIGNAL_LOCKED (1 << 2)
680#define D11B_PLCP_SIGNAL_LE (1 << 7)
681
682#define MIMO_PLCP_MCS_MASK 0x7f /* mcs index */
683#define MIMO_PLCP_40MHZ 0x80 /* 40 Hz frame */
684#define MIMO_PLCP_AMPDU 0x08 /* ampdu */
685
686#define WLC_GET_CCK_PLCP_LEN(plcp) (plcp[4] + (plcp[5] << 8))
687#define WLC_GET_MIMO_PLCP_LEN(plcp) (plcp[1] + (plcp[2] << 8))
688#define WLC_SET_MIMO_PLCP_LEN(plcp, len) \
c5fe41c3
JC		 689 do { \
690 plcp[1] = len & 0xff; \
691 plcp[2] = ((len >> 8) & 0xff); \
692 } while (0);
a9533e7e
HP		 693
694#define WLC_SET_MIMO_PLCP_AMPDU(plcp) (plcp[3] |= MIMO_PLCP_AMPDU)
695#define WLC_CLR_MIMO_PLCP_AMPDU(plcp) (plcp[3] &= ~MIMO_PLCP_AMPDU)
696#define WLC_IS_MIMO_PLCP_AMPDU(plcp) (plcp[3] & MIMO_PLCP_AMPDU)
697
698/* The dot11a PLCP header is 5 bytes. To simplify the software (so that we
699 * don't need e.g. different tx DMA headers for 11a and 11b), the PLCP header has
700 * padding added in the ucode.
701 */
702#define D11_PHY_HDR_LEN 6
703
704/* TX DMA buffer header */
705typedef struct d11txh d11txh_t;
1e661086 706struct d11txh {
7d4df48e
GKH		 707 u16 MacTxControlLow; /* 0x0 */
708 u16 MacTxControlHigh; /* 0x1 */
709 u16 MacFrameControl; /* 0x2 */
710 u16 TxFesTimeNormal; /* 0x3 */
711 u16 PhyTxControlWord; /* 0x4 */
712 u16 PhyTxControlWord_1; /* 0x5 */
713 u16 PhyTxControlWord_1_Fbr; /* 0x6 */
714 u16 PhyTxControlWord_1_Rts; /* 0x7 */
715 u16 PhyTxControlWord_1_FbrRts; /* 0x8 */
716 u16 MainRates; /* 0x9 */
717 u16 XtraFrameTypes; /* 0xa */
de9bca63
GKH		 718 u8 IV[16]; /* 0x0b - 0x12 */
719 u8 TxFrameRA[6]; /* 0x13 - 0x15 */
7d4df48e 720 u16 TxFesTimeFallback; /* 0x16 */
de9bca63 721 u8 RTSPLCPFallback[6]; /* 0x17 - 0x19 */
7d4df48e 722 u16 RTSDurFallback; /* 0x1a */
de9bca63 723 u8 FragPLCPFallback[6]; /* 0x1b - 1d */
7d4df48e
GKH		 724 u16 FragDurFallback; /* 0x1e */
725 u16 MModeLen; /* 0x1f */
726 u16 MModeFbrLen; /* 0x20 */
727 u16 TstampLow; /* 0x21 */
728 u16 TstampHigh; /* 0x22 */
729 u16 ABI_MimoAntSel; /* 0x23 */
730 u16 PreloadSize; /* 0x24 */
731 u16 AmpduSeqCtl; /* 0x25 */
732 u16 TxFrameID; /* 0x26 */
733 u16 TxStatus; /* 0x27 */
734 u16 MaxNMpdus; /* 0x28 corerev >=16 */
735 u16 MaxABytes_MRT; /* 0x29 corerev >=16 */
736 u16 MaxABytes_FBR; /* 0x2a corerev >=16 */
737 u16 MinMBytes; /* 0x2b corerev >=16 */
de9bca63 738 u8 RTSPhyHeader[D11_PHY_HDR_LEN]; /* 0x2c - 0x2e */
a9533e7e 739 struct dot11_rts_frame rts_frame; /* 0x2f - 0x36 */
7d4df48e 740 u16 PAD; /* 0x37 */
1e661086 741} __attribute__((packed));
a9533e7e
HP		 742
743#define D11_TXH_LEN 112 /* bytes */
744
745/* Frame Types */
746#define FT_CCK 0
747#define FT_OFDM 1
748#define FT_HT 2
749#define FT_N 3
750
751/* Position of MPDU inside A-MPDU; indicated with bits 10:9 of MacTxControlLow */
752#define TXC_AMPDU_SHIFT 9 /* shift for ampdu settings */
753#define TXC_AMPDU_NONE 0 /* Regular MPDU, not an A-MPDU */
754#define TXC_AMPDU_FIRST 1 /* first MPDU of an A-MPDU */
755#define TXC_AMPDU_MIDDLE 2 /* intermediate MPDU of an A-MPDU */
756#define TXC_AMPDU_LAST 3 /* last (or single) MPDU of an A-MPDU */
757
758/* MacTxControlLow */
759#define TXC_AMIC 0x8000
760#define TXC_SENDCTS 0x0800
761#define TXC_AMPDU_MASK 0x0600
762#define TXC_BW_40 0x0100
763#define TXC_FREQBAND_5G 0x0080
764#define TXC_DFCS 0x0040
765#define TXC_IGNOREPMQ 0x0020
766#define TXC_HWSEQ 0x0010
767#define TXC_STARTMSDU 0x0008
768#define TXC_SENDRTS 0x0004
769#define TXC_LONGFRAME 0x0002
770#define TXC_IMMEDACK 0x0001
771
772/* MacTxControlHigh */
773#define TXC_PREAMBLE_RTS_FB_SHORT 0x8000 /* RTS fallback preamble type 1 = SHORT 0 = LONG */
774#define TXC_PREAMBLE_RTS_MAIN_SHORT 0x4000 /* RTS main rate preamble type 1 = SHORT 0 = LONG */
775#define TXC_PREAMBLE_DATA_FB_SHORT 0x2000 /* Main fallback rate preamble type
776 * 1 = SHORT for OFDM/GF for MIMO
777 * 0 = LONG for CCK/MM for MIMO
778 */
779/* TXC_PREAMBLE_DATA_MAIN is in PhyTxControl bit 5 */
780#define TXC_AMPDU_FBR 0x1000 /* use fallback rate for this AMPDU */
781#define TXC_SECKEY_MASK 0x0FF0
782#define TXC_SECKEY_SHIFT 4
783#define TXC_ALT_TXPWR 0x0008 /* Use alternate txpwr defined at loc. M_ALT_TXPWR_IDX */
784#define TXC_SECTYPE_MASK 0x0007
785#define TXC_SECTYPE_SHIFT 0
786
787/* Null delimiter for Fallback rate */
788#define AMPDU_FBR_NULL_DELIM 5 /* Location of Null delimiter count for AMPDU */
789
790/* PhyTxControl for Mimophy */
791#define PHY_TXC_PWR_MASK 0xFC00
792#define PHY_TXC_PWR_SHIFT 10
793#define PHY_TXC_ANT_MASK 0x03C0 /* bit 6, 7, 8, 9 */
794#define PHY_TXC_ANT_SHIFT 6
795#define PHY_TXC_ANT_0_1 0x00C0 /* auto, last rx */
796#define PHY_TXC_LCNPHY_ANT_LAST 0x0000
797#define PHY_TXC_ANT_3 0x0200 /* virtual antenna 3 */
798#define PHY_TXC_ANT_2 0x0100 /* virtual antenna 2 */
799#define PHY_TXC_ANT_1 0x0080 /* virtual antenna 1 */
800#define PHY_TXC_ANT_0 0x0040 /* virtual antenna 0 */
801#define PHY_TXC_SHORT_HDR 0x0010
802
803#define PHY_TXC_OLD_ANT_0 0x0000
804#define PHY_TXC_OLD_ANT_1 0x0100
805#define PHY_TXC_OLD_ANT_LAST 0x0300
806
807/* PhyTxControl_1 for Mimophy */
808#define PHY_TXC1_BW_MASK 0x0007
809#define PHY_TXC1_BW_10MHZ 0
810#define PHY_TXC1_BW_10MHZ_UP 1
811#define PHY_TXC1_BW_20MHZ 2
812#define PHY_TXC1_BW_20MHZ_UP 3
813#define PHY_TXC1_BW_40MHZ 4
814#define PHY_TXC1_BW_40MHZ_DUP 5
815#define PHY_TXC1_MODE_SHIFT 3
816#define PHY_TXC1_MODE_MASK 0x0038
817#define PHY_TXC1_MODE_SISO 0
818#define PHY_TXC1_MODE_CDD 1
819#define PHY_TXC1_MODE_STBC 2
820#define PHY_TXC1_MODE_SDM 3
821
822/* PhyTxControl for HTphy that are different from Mimophy */
823#define PHY_TXC_HTANT_MASK 0x3fC0 /* bit 6, 7, 8, 9, 10, 11, 12, 13 */
824
825/* XtraFrameTypes */
826#define XFTS_RTS_FT_SHIFT 2
827#define XFTS_FBRRTS_FT_SHIFT 4
828#define XFTS_CHANNEL_SHIFT 8
829
830/* Antenna diversity bit in ant_wr_settle */
831#define PHY_AWS_ANTDIV 0x2000
832
833/* IFS ctl */
834#define IFS_USEEDCF (1 << 2)
835
836/* IFS ctl1 */
837#define IFS_CTL1_EDCRS (1 << 3)
838#define IFS_CTL1_EDCRS_20L (1 << 4)
839#define IFS_CTL1_EDCRS_40 (1 << 5)
840
841/* ABI_MimoAntSel */
842#define ABI_MAS_ADDR_BMP_IDX_MASK 0x0f00
843#define ABI_MAS_ADDR_BMP_IDX_SHIFT 8
844#define ABI_MAS_FBR_ANT_PTN_MASK 0x00f0
845#define ABI_MAS_FBR_ANT_PTN_SHIFT 4
846#define ABI_MAS_MRT_ANT_PTN_MASK 0x000f
847
848/* tx status packet */
849typedef struct tx_status tx_status_t;
1e661086 850struct tx_status {
7d4df48e
GKH		 851 u16 framelen;
852 u16 PAD;
853 u16 frameid;
854 u16 status;
855 u16 lasttxtime;
856 u16 sequence;
857 u16 phyerr;
858 u16 ackphyrxsh;
1e661086 859} __attribute__((packed));
a9533e7e
HP		 860
861#define TXSTATUS_LEN 16
862
863/* status field bit definitions */
864#define TX_STATUS_FRM_RTX_MASK 0xF000
865#define TX_STATUS_FRM_RTX_SHIFT 12
866#define TX_STATUS_RTS_RTX_MASK 0x0F00
867#define TX_STATUS_RTS_RTX_SHIFT 8
868#define TX_STATUS_MASK 0x00FE
869#define TX_STATUS_PMINDCTD (1 << 7) /* PM mode indicated to AP */
870#define TX_STATUS_INTERMEDIATE (1 << 6) /* intermediate or 1st ampdu pkg */
871#define TX_STATUS_AMPDU (1 << 5) /* AMPDU status */
872#define TX_STATUS_SUPR_MASK 0x1C /* suppress status bits (4:2) */
873#define TX_STATUS_SUPR_SHIFT 2
874#define TX_STATUS_ACK_RCV (1 << 1) /* ACK received */
875#define TX_STATUS_VALID (1 << 0) /* Tx status valid (corerev >= 5) */
876#define TX_STATUS_NO_ACK 0
877
878/* suppress status reason codes */
879#define TX_STATUS_SUPR_PMQ (1 << 2) /* PMQ entry */
880#define TX_STATUS_SUPR_FLUSH (2 << 2) /* flush request */
881#define TX_STATUS_SUPR_FRAG (3 << 2) /* previous frag failure */
882#define TX_STATUS_SUPR_TBTT (3 << 2) /* SHARED: Probe response supr for TBTT */
883#define TX_STATUS_SUPR_BADCH (4 << 2) /* channel mismatch */
884#define TX_STATUS_SUPR_EXPTIME (5 << 2) /* lifetime expiry */
885#define TX_STATUS_SUPR_UF (6 << 2) /* underflow */
886
887/* Unexpected tx status for rate update */
888#define TX_STATUS_UNEXP(status) \
889 ((((status) & TX_STATUS_INTERMEDIATE) != 0) && \
890 TX_STATUS_UNEXP_AMPDU(status))
891
892/* Unexpected tx status for A-MPDU rate update */
893#define TX_STATUS_UNEXP_AMPDU(status) \
894 ((((status) & TX_STATUS_SUPR_MASK) != 0) && \
895 (((status) & TX_STATUS_SUPR_MASK) != TX_STATUS_SUPR_EXPTIME))
896
897#define TX_STATUS_BA_BMAP03_MASK 0xF000 /* ba bitmap 0:3 in 1st pkg */
898#define TX_STATUS_BA_BMAP03_SHIFT 12 /* ba bitmap 0:3 in 1st pkg */
899#define TX_STATUS_BA_BMAP47_MASK 0x001E /* ba bitmap 4:7 in 2nd pkg */
900#define TX_STATUS_BA_BMAP47_SHIFT 3 /* ba bitmap 4:7 in 2nd pkg */
901
902/* RXE (Receive Engine) */
903
904/* RCM_CTL */
905#define RCM_INC_MASK_H 0x0080
906#define RCM_INC_MASK_L 0x0040
907#define RCM_INC_DATA 0x0020
908#define RCM_INDEX_MASK 0x001F
909#define RCM_SIZE 15
910
911#define RCM_MAC_OFFSET 0 /* current MAC address */
912#define RCM_BSSID_OFFSET 3 /* current BSSID address */
913#define RCM_F_BSSID_0_OFFSET 6 /* foreign BSS CFP tracking */
914#define RCM_F_BSSID_1_OFFSET 9 /* foreign BSS CFP tracking */
915#define RCM_F_BSSID_2_OFFSET 12 /* foreign BSS CFP tracking */
916
917#define RCM_WEP_TA0_OFFSET 16
918#define RCM_WEP_TA1_OFFSET 19
919#define RCM_WEP_TA2_OFFSET 22
920#define RCM_WEP_TA3_OFFSET 25
921
922/* PSM Block */
923
924/* psm_phy_hdr_param bits */
925#define MAC_PHY_RESET 1
926#define MAC_PHY_CLOCK_EN 2
927#define MAC_PHY_FORCE_CLK 4
928
929/* WEP Block */
930
931/* WEP_WKEY */
932#define WKEY_START (1 << 8)
933#define WKEY_SEL_MASK 0x1F
934
935/* WEP data formats */
936
937/* the number of RCMTA entries */
938#define RCMTA_SIZE 50
939
940#define M_ADDR_BMP_BLK (0x37e * 2)
941#define M_ADDR_BMP_BLK_SZ 12
942
943#define ADDR_BMP_RA (1 << 0) /* Receiver Address (RA) */
944#define ADDR_BMP_TA (1 << 1) /* Transmitter Address (TA) */
945#define ADDR_BMP_BSSID (1 << 2) /* BSSID */
946#define ADDR_BMP_AP (1 << 3) /* Infra-BSS Access Point (AP) */
947#define ADDR_BMP_STA (1 << 4) /* Infra-BSS Station (STA) */
948#define ADDR_BMP_RESERVED1 (1 << 5)
949#define ADDR_BMP_RESERVED2 (1 << 6)
950#define ADDR_BMP_RESERVED3 (1 << 7)
951#define ADDR_BMP_BSS_IDX_MASK (3 << 8) /* BSS control block index */
952#define ADDR_BMP_BSS_IDX_SHIFT 8
953
954#define WSEC_MAX_RCMTA_KEYS 54
955
956/* max keys in M_TKMICKEYS_BLK */
957#define WSEC_MAX_TKMIC_ENGINE_KEYS 12 /* 8 + 4 default */
958
959/* max RXE match registers */
960#define WSEC_MAX_RXE_KEYS 4
961
962/* SECKINDXALGO (Security Key Index & Algorithm Block) word format */
963/* SKL (Security Key Lookup) */
964#define SKL_ALGO_MASK 0x0007
965#define SKL_ALGO_SHIFT 0
966#define SKL_KEYID_MASK 0x0008
967#define SKL_KEYID_SHIFT 3
968#define SKL_INDEX_MASK 0x03F0
969#define SKL_INDEX_SHIFT 4
970#define SKL_GRP_ALGO_MASK 0x1c00
971#define SKL_GRP_ALGO_SHIFT 10
972
973/* additional bits defined for IBSS group key support */
974#define SKL_IBSS_INDEX_MASK 0x01F0
975#define SKL_IBSS_INDEX_SHIFT 4
976#define SKL_IBSS_KEYID1_MASK 0x0600
977#define SKL_IBSS_KEYID1_SHIFT 9
978#define SKL_IBSS_KEYID2_MASK 0x1800
979#define SKL_IBSS_KEYID2_SHIFT 11
980#define SKL_IBSS_KEYALGO_MASK 0xE000
981#define SKL_IBSS_KEYALGO_SHIFT 13
982
983#define WSEC_MODE_OFF 0
984#define WSEC_MODE_HW 1
985#define WSEC_MODE_SW 2
986
987#define WSEC_ALGO_OFF 0
988#define WSEC_ALGO_WEP1 1
989#define WSEC_ALGO_TKIP 2
990#define WSEC_ALGO_AES 3
991#define WSEC_ALGO_WEP128 4
992#define WSEC_ALGO_AES_LEGACY 5
993#define WSEC_ALGO_NALG 6
994
995#define AES_MODE_NONE 0
996#define AES_MODE_CCM 1
997
998/* WEP_CTL (Rev 0) */
999#define WECR0_KEYREG_SHIFT 0
1000#define WECR0_KEYREG_MASK 0x7
1001#define WECR0_DECRYPT (1 << 3)
1002#define WECR0_IVINLINE (1 << 4)
1003#define WECR0_WEPALG_SHIFT 5
1004#define WECR0_WEPALG_MASK (0x7 << 5)
1005#define WECR0_WKEYSEL_SHIFT 8
1006#define WECR0_WKEYSEL_MASK (0x7 << 8)
1007#define WECR0_WKEYSTART (1 << 11)
1008#define WECR0_WEPINIT (1 << 14)
1009#define WECR0_ICVERR (1 << 15)
1010
1011/* Frame template map byte offsets */
1012#define T_ACTS_TPL_BASE (0)
1013#define T_NULL_TPL_BASE (0xc * 2)
1014#define T_QNULL_TPL_BASE (0x1c * 2)
1015#define T_RR_TPL_BASE (0x2c * 2)
1016#define T_BCN0_TPL_BASE (0x34 * 2)
1017#define T_PRS_TPL_BASE (0x134 * 2)
1018#define T_BCN1_TPL_BASE (0x234 * 2)
1019#define T_TX_FIFO_TXRAM_BASE (T_ACTS_TPL_BASE + (TXFIFO_START_BLK * TXFIFO_SIZE_UNIT))
1020
1021#define T_BA_TPL_BASE T_QNULL_TPL_BASE /* template area for BA */
1022
1023#define T_RAM_ACCESS_SZ 4 /* template ram is 4 byte access only */
1024
1025/* Shared Mem byte offsets */
1026
1027/* Location where the ucode expects the corerev */
1028#define M_MACHW_VER (0x00b * 2)
1029
1030/* Location where the ucode expects the MAC capabilities */
1031#define M_MACHW_CAP_L (0x060 * 2)
1032#define M_MACHW_CAP_H (0x061 * 2)
1033
1034/* WME shared memory */
1035#define M_EDCF_STATUS_OFF (0x007 * 2)
1036#define M_TXF_CUR_INDEX (0x018 * 2)
1037#define M_EDCF_QINFO (0x120 * 2)
1038
1039/* PS-mode related parameters */
1040#define M_DOT11_SLOT (0x008 * 2)
1041#define M_DOT11_DTIMPERIOD (0x009 * 2)
1042#define M_NOSLPZNATDTIM (0x026 * 2)
1043
1044/* Beacon-related parameters */
1045#define M_BCN0_FRM_BYTESZ (0x00c * 2) /* Bcn 0 template length */
1046#define M_BCN1_FRM_BYTESZ (0x00d * 2) /* Bcn 1 template length */
1047#define M_BCN_TXTSF_OFFSET (0x00e * 2)
1048#define M_TIMBPOS_INBEACON (0x00f * 2)
1049#define M_SFRMTXCNTFBRTHSD (0x022 * 2)
1050#define M_LFRMTXCNTFBRTHSD (0x023 * 2)
1051#define M_BCN_PCTLWD (0x02a * 2)
1052#define M_BCN_LI (0x05b * 2) /* beacon listen interval */
1053
1054/* MAX Rx Frame len */
1055#define M_MAXRXFRM_LEN (0x010 * 2)
1056
1057/* ACK/CTS related params */
1058#define M_RSP_PCTLWD (0x011 * 2)
1059
1060/* Hardware Power Control */
1061#define M_TXPWR_N (0x012 * 2)
1062#define M_TXPWR_TARGET (0x013 * 2)
1063#define M_TXPWR_MAX (0x014 * 2)
1064#define M_TXPWR_CUR (0x019 * 2)
1065
1066/* Rx-related parameters */
1067#define M_RX_PAD_DATA_OFFSET (0x01a * 2)
1068
1069/* WEP Shared mem data */
1070#define M_SEC_DEFIVLOC (0x01e * 2)
1071#define M_SEC_VALNUMSOFTMCHTA (0x01f * 2)
1072#define M_PHYVER (0x028 * 2)
1073#define M_PHYTYPE (0x029 * 2)
1074#define M_SECRXKEYS_PTR (0x02b * 2)
1075#define M_TKMICKEYS_PTR (0x059 * 2)
1076#define M_SECKINDXALGO_BLK (0x2ea * 2)
1077#define M_SECKINDXALGO_BLK_SZ 54
1078#define M_SECPSMRXTAMCH_BLK (0x2fa * 2)
1079#define M_TKIP_TSC_TTAK (0x18c * 2)
1080#define D11_MAX_KEY_SIZE 16
1081
1082#define M_MAX_ANTCNT (0x02e * 2) /* antenna swap threshold */
1083
1084/* Probe response related parameters */
1085#define M_SSIDLEN (0x024 * 2)
1086#define M_PRB_RESP_FRM_LEN (0x025 * 2)
1087#define M_PRS_MAXTIME (0x03a * 2)
1088#define M_SSID (0xb0 * 2)
1089#define M_CTXPRS_BLK (0xc0 * 2)
1090#define C_CTX_PCTLWD_POS (0x4 * 2)
1091
1092/* Delta between OFDM and CCK power in CCK power boost mode */
1093#define M_OFDM_OFFSET (0x027 * 2)
1094
1095/* TSSI for last 4 11b/g CCK packets transmitted */
1096#define M_B_TSSI_0 (0x02c * 2)
1097#define M_B_TSSI_1 (0x02d * 2)
1098
1099/* Host flags to turn on ucode options */
1100#define M_HOST_FLAGS1 (0x02f * 2)
1101#define M_HOST_FLAGS2 (0x030 * 2)
1102#define M_HOST_FLAGS3 (0x031 * 2)
1103#define M_HOST_FLAGS4 (0x03c * 2)
1104#define M_HOST_FLAGS5 (0x06a * 2)
1105#define M_HOST_FLAGS_SZ 16
1106
1107#define M_RADAR_REG (0x033 * 2)
1108
1109/* TSSI for last 4 11a OFDM packets transmitted */
1110#define M_A_TSSI_0 (0x034 * 2)
1111#define M_A_TSSI_1 (0x035 * 2)
1112
1113/* noise interference measurement */
1114#define M_NOISE_IF_COUNT (0x034 * 2)
1115#define M_NOISE_IF_TIMEOUT (0x035 * 2)
1116
1117#define M_RF_RX_SP_REG1 (0x036 * 2)
1118
1119/* TSSI for last 4 11g OFDM packets transmitted */
1120#define M_G_TSSI_0 (0x038 * 2)
1121#define M_G_TSSI_1 (0x039 * 2)
1122
1123/* Background noise measure */
1124#define M_JSSI_0 (0x44 * 2)
1125#define M_JSSI_1 (0x45 * 2)
1126#define M_JSSI_AUX (0x46 * 2)
1127
1128#define M_CUR_2050_RADIOCODE (0x47 * 2)
1129
1130/* TX fifo sizes */
1131#define M_FIFOSIZE0 (0x4c * 2)
1132#define M_FIFOSIZE1 (0x4d * 2)
1133#define M_FIFOSIZE2 (0x4e * 2)
1134#define M_FIFOSIZE3 (0x4f * 2)
1135#define D11_MAX_TX_FRMS 32 /* max frames allowed in tx fifo */
1136
1137/* Current channel number plus upper bits */
1138#define M_CURCHANNEL (0x50 * 2)
1139#define D11_CURCHANNEL_5G 0x0100;
1140#define D11_CURCHANNEL_40 0x0200;
1141#define D11_CURCHANNEL_MAX 0x00FF;
1142
1143/* last posted frameid on the bcmc fifo */
1144#define M_BCMC_FID (0x54 * 2)
1145#define INVALIDFID 0xffff
1146
1147/* extended beacon phyctl bytes for 11N */
1148#define M_BCN_PCTL1WD (0x058 * 2)
1149
1150/* idle busy ratio to duty_cycle requirement */
1151#define M_TX_IDLE_BUSY_RATIO_X_16_CCK (0x52 * 2)
1152#define M_TX_IDLE_BUSY_RATIO_X_16_OFDM (0x5A * 2)
1153
1154/* CW RSSI for LCNPHY */
1155#define M_LCN_RSSI_0 0x1332
1156#define M_LCN_RSSI_1 0x1338
1157#define M_LCN_RSSI_2 0x133e
1158#define M_LCN_RSSI_3 0x1344
1159
1160/* SNR for LCNPHY */
1161#define M_LCN_SNR_A_0 0x1334
1162#define M_LCN_SNR_B_0 0x1336
1163
1164#define M_LCN_SNR_A_1 0x133a
1165#define M_LCN_SNR_B_1 0x133c
1166
1167#define M_LCN_SNR_A_2 0x1340
1168#define M_LCN_SNR_B_2 0x1342
1169
1170#define M_LCN_SNR_A_3 0x1346
1171#define M_LCN_SNR_B_3 0x1348
1172
1173#define M_LCN_LAST_RESET (81*2)
1174#define M_LCN_LAST_LOC (63*2)
1175#define M_LCNPHY_RESET_STATUS (4902)
1176#define M_LCNPHY_DSC_TIME (0x98d*2)
1177#define M_LCNPHY_RESET_CNT_DSC (0x98b*2)
1178#define M_LCNPHY_RESET_CNT (0x98c*2)
1179
1180/* Rate table offsets */
1181#define M_RT_DIRMAP_A (0xe0 * 2)
1182#define M_RT_BBRSMAP_A (0xf0 * 2)
1183#define M_RT_DIRMAP_B (0x100 * 2)
1184#define M_RT_BBRSMAP_B (0x110 * 2)
1185
1186/* Rate table entry offsets */
1187#define M_RT_PRS_PLCP_POS 10
1188#define M_RT_PRS_DUR_POS 16
1189#define M_RT_OFDM_PCTL1_POS 18
1190
1191#define M_20IN40_IQ (0x380 * 2)
1192
1193/* SHM locations where ucode stores the current power index */
198bd4d6
JC		 1194#define M_CURR_IDX1 (0x384 * 2)
1195#define M_CURR_IDX2 (0x387 * 2)
a9533e7e
HP		 1196
1197#define M_BSCALE_ANT0 (0x5e * 2)
1198#define M_BSCALE_ANT1 (0x5f * 2)
1199
1200/* Antenna Diversity Testing */
1201#define M_MIMO_ANTSEL_RXDFLT (0x63 * 2)
1202#define M_ANTSEL_CLKDIV (0x61 * 2)
1203#define M_MIMO_ANTSEL_TXDFLT (0x64 * 2)
1204
1205#define M_MIMO_MAXSYM (0x5d * 2)
1206#define MIMO_MAXSYM_DEF 0x8000 /* 32k */
1207#define MIMO_MAXSYM_MAX 0xffff /* 64k */
1208
1209#define M_WATCHDOG_8TU (0x1e * 2)
1210#define WATCHDOG_8TU_DEF 5
1211#define WATCHDOG_8TU_MAX 10
1212
1213/* Manufacturing Test Variables */
1214#define M_PKTENG_CTRL (0x6c * 2) /* PER test mode */
1215#define M_PKTENG_IFS (0x6d * 2) /* IFS for TX mode */
1216#define M_PKTENG_FRMCNT_LO (0x6e * 2) /* Lower word of tx frmcnt/rx lostcnt */
1217#define M_PKTENG_FRMCNT_HI (0x6f * 2) /* Upper word of tx frmcnt/rx lostcnt */
1218
1219/* Index variation in vbat ripple */
1220#define M_LCN_PWR_IDX_MAX (0x67 * 2) /* highest index read by ucode */
1221#define M_LCN_PWR_IDX_MIN (0x66 * 2) /* lowest index read by ucode */
1222
1223/* M_PKTENG_CTRL bit definitions */
1224#define M_PKTENG_MODE_TX 0x0001
1225#define M_PKTENG_MODE_TX_RIFS 0x0004
1226#define M_PKTENG_MODE_TX_CTS 0x0008
1227#define M_PKTENG_MODE_RX 0x0002
1228#define M_PKTENG_MODE_RX_WITH_ACK 0x0402
1229#define M_PKTENG_MODE_MASK 0x0003
1230#define M_PKTENG_FRMCNT_VLD 0x0100 /* TX frames indicated in the frmcnt reg */
1231
1232/* Sample Collect parameters (bitmap and type) */
1233#define M_SMPL_COL_BMP (0x37d * 2) /* Trigger bitmap for sample collect */
1234#define M_SMPL_COL_CTL (0x3b2 * 2) /* Sample collect type */
1235
1236#define ANTSEL_CLKDIV_4MHZ 6
1237#define MIMO_ANTSEL_BUSY 0x4000 /* bit 14 (busy) */
1238#define MIMO_ANTSEL_SEL 0x8000 /* bit 15 write the value */
1239#define MIMO_ANTSEL_WAIT 50 /* 50us wait */
1240#define MIMO_ANTSEL_OVERRIDE 0x8000 /* flag */
1241
1242typedef struct shm_acparams shm_acparams_t;
1e661086 1243struct shm_acparams {
7d4df48e
GKH		 1244 u16 txop;
1245 u16 cwmin;
1246 u16 cwmax;
1247 u16 cwcur;
1248 u16 aifs;
1249 u16 bslots;
1250 u16 reggap;
1251 u16 status;
1252 u16 rsvd[8];
1e661086 1253} __attribute__((packed));
a9533e7e
HP		 1254#define M_EDCF_QLEN (16 * 2)
1255
1256#define WME_STATUS_NEWAC (1 << 8)
1257
1258/* M_HOST_FLAGS */
7d4df48e 1259#define MHFMAX 5 /* Number of valid hostflag half-word (u16) */
a9533e7e
HP		 1260#define MHF1 0 /* Hostflag 1 index */
1261#define MHF2 1 /* Hostflag 2 index */
1262#define MHF3 2 /* Hostflag 3 index */
1263#define MHF4 3 /* Hostflag 4 index */
1264#define MHF5 4 /* Hostflag 5 index */
1265
1266/* Flags in M_HOST_FLAGS */
1267#define MHF1_ANTDIV 0x0001 /* Enable ucode antenna diversity help */
1268#define MHF1_EDCF 0x0100 /* Enable EDCF access control */
1269#define MHF1_IQSWAP_WAR 0x0200
1270#define MHF1_FORCEFASTCLK 0x0400 /* Disable Slow clock request, for corerev < 11 */
1271
1272/* Flags in M_HOST_FLAGS2 */
1273#define MHF2_PCISLOWCLKWAR 0x0008 /* PR16165WAR : Enable ucode PCI slow clock WAR */
1274#define MHF2_TXBCMC_NOW 0x0040 /* Flush BCMC FIFO immediately */
1275#define MHF2_HWPWRCTL 0x0080 /* Enable ucode/hw power control */
1276#define MHF2_NPHY40MHZ_WAR 0x0800
1277
1278/* Flags in M_HOST_FLAGS3 */
1279#define MHF3_ANTSEL_EN 0x0001 /* enabled mimo antenna selection */
1280#define MHF3_ANTSEL_MODE 0x0002 /* antenna selection mode: 0: 2x3, 1: 2x4 */
1281#define MHF3_RESERVED1 0x0004
1282#define MHF3_RESERVED2 0x0008
1283#define MHF3_NPHY_MLADV_WAR 0x0010
1284
1285/* Flags in M_HOST_FLAGS4 */
1286#define MHF4_BPHY_TXCORE0 0x0080 /* force bphy Tx on core 0 (board level WAR) */
1287#define MHF4_EXTPA_ENABLE 0x4000 /* for 4313A0 FEM boards */
1288
1289/* Flags in M_HOST_FLAGS5 */
1290#define MHF5_4313_GPIOCTRL 0x0001
1291#define MHF5_RESERVED1 0x0002
1292#define MHF5_RESERVED2 0x0004
1293/* Radio power setting for ucode */
1294#define M_RADIO_PWR (0x32 * 2)
1295
1296/* phy noise recorded by ucode right after tx */
1297#define M_PHY_NOISE (0x037 * 2)
1298#define PHY_NOISE_MASK 0x00ff
1299
1300/* Receive Frame Data Header for 802.11b DCF-only frames */
1301typedef struct d11rxhdr d11rxhdr_t;
1e661086 1302struct d11rxhdr {
7d4df48e
GKH		 1303 u16 RxFrameSize; /* Actual byte length of the frame data received */
1304 u16 PAD;
1305 u16 PhyRxStatus_0; /* PhyRxStatus 15:0 */
1306 u16 PhyRxStatus_1; /* PhyRxStatus 31:16 */
1307 u16 PhyRxStatus_2; /* PhyRxStatus 47:32 */
1308 u16 PhyRxStatus_3; /* PhyRxStatus 63:48 */
1309 u16 PhyRxStatus_4; /* PhyRxStatus 79:64 */
1310 u16 PhyRxStatus_5; /* PhyRxStatus 95:80 */
1311 u16 RxStatus1; /* MAC Rx Status */
1312 u16 RxStatus2; /* extended MAC Rx status */
1313 u16 RxTSFTime; /* RxTSFTime time of first MAC symbol + M_PHY_PLCPRX_DLY */
1314 u16 RxChan; /* gain code, channel radio code, and phy type */
1e661086 1315} __attribute__((packed));
a9533e7e
HP		 1316
1317#define RXHDR_LEN 24 /* sizeof d11rxhdr_t */
1318#define FRAMELEN(h) ((h)->RxFrameSize)
1319
1320typedef struct wlc_d11rxhdr wlc_d11rxhdr_t;
1e661086 1321struct wlc_d11rxhdr {
a9533e7e 1322 d11rxhdr_t rxhdr;
66cbd3ab 1323 u32 tsf_l; /* TSF_L reading */
562c8850
GKH		 1324 s8 rssi; /* computed instanteneous rssi in BMAC */
1325 s8 rxpwr0; /* obsoleted, place holder for legacy ROM code. use rxpwr[] */
1326 s8 rxpwr1; /* obsoleted, place holder for legacy ROM code. use rxpwr[] */
1327 s8 do_rssi_ma; /* do per-pkt sampling for per-antenna ma in HIGH */
1328 s8 rxpwr[WL_RSSI_ANT_MAX]; /* rssi for supported antennas */
1e661086 1329} __attribute__((packed));
a9533e7e
HP		 1330
1331/* PhyRxStatus_0: */
1332#define PRXS0_FT_MASK 0x0003 /* NPHY only: CCK, OFDM, preN, N */
1333#define PRXS0_CLIP_MASK 0x000C /* NPHY only: clip count adjustment steps by AGC */
1334#define PRXS0_CLIP_SHIFT 2
1335#define PRXS0_UNSRATE 0x0010 /* PHY received a frame with unsupported rate */
1336#define PRXS0_RXANT_UPSUBBAND 0x0020 /* GPHY: rx ant, NPHY: upper sideband */
1337#define PRXS0_LCRS 0x0040 /* CCK frame only: lost crs during cck frame reception */
1338#define PRXS0_SHORTH 0x0080 /* Short Preamble */
1339#define PRXS0_PLCPFV 0x0100 /* PLCP violation */
1340#define PRXS0_PLCPHCF 0x0200 /* PLCP header integrity check failed */
1341#define PRXS0_GAIN_CTL 0x4000 /* legacy PHY gain control */
1342#define PRXS0_ANTSEL_MASK 0xF000 /* NPHY: Antennas used for received frame, bitmask */
1343#define PRXS0_ANTSEL_SHIFT 0x12
1344
1345/* subfield PRXS0_FT_MASK */
1346#define PRXS0_CCK 0x0000
1347#define PRXS0_OFDM 0x0001 /* valid only for G phy, use rxh->RxChan for A phy */
1348#define PRXS0_PREN 0x0002
1349#define PRXS0_STDN 0x0003
1350
1351/* subfield PRXS0_ANTSEL_MASK */
1352#define PRXS0_ANTSEL_0 0x0 /* antenna 0 is used */
1353#define PRXS0_ANTSEL_1 0x2 /* antenna 1 is used */
1354#define PRXS0_ANTSEL_2 0x4 /* antenna 2 is used */
1355#define PRXS0_ANTSEL_3 0x8 /* antenna 3 is used */
1356
1357/* PhyRxStatus_1: */
1358#define PRXS1_JSSI_MASK 0x00FF
1359#define PRXS1_JSSI_SHIFT 0
1360#define PRXS1_SQ_MASK 0xFF00
1361#define PRXS1_SQ_SHIFT 8
1362
1363/* nphy PhyRxStatus_1: */
1364#define PRXS1_nphy_PWR0_MASK 0x00FF
1365#define PRXS1_nphy_PWR1_MASK 0xFF00
1366
1367/* HTPHY Rx Status defines */
1368/* htphy PhyRxStatus_0: those bit are overlapped with PhyRxStatus_0 */
1369#define PRXS0_BAND 0x0400 /* 0 = 2.4G, 1 = 5G */
1370#define PRXS0_RSVD 0x0800 /* reserved; set to 0 */
1371#define PRXS0_UNUSED 0xF000 /* unused and not defined; set to 0 */
1372
1373/* htphy PhyRxStatus_1: */
1374#define PRXS1_HTPHY_CORE_MASK 0x000F /* core enables for {3..0}, 0=disabled, 1=enabled */
1375#define PRXS1_HTPHY_ANTCFG_MASK 0x00F0 /* antenna configation */
1376#define PRXS1_HTPHY_MMPLCPLenL_MASK 0xFF00 /* Mixmode PLCP Length low byte mask */
1377
1378/* htphy PhyRxStatus_2: */
1379#define PRXS2_HTPHY_MMPLCPLenH_MASK 0x000F /* Mixmode PLCP Length high byte maskw */
1380#define PRXS2_HTPHY_MMPLCH_RATE_MASK 0x00F0 /* Mixmode PLCP rate mask */
1381#define PRXS2_HTPHY_RXPWR_ANT0 0xFF00 /* Rx power on core 0 */
1382
1383/* htphy PhyRxStatus_3: */
1384#define PRXS3_HTPHY_RXPWR_ANT1 0x00FF /* Rx power on core 1 */
1385#define PRXS3_HTPHY_RXPWR_ANT2 0xFF00 /* Rx power on core 2 */
1386
1387/* htphy PhyRxStatus_4: */
1388#define PRXS4_HTPHY_RXPWR_ANT3 0x00FF /* Rx power on core 3 */
1389#define PRXS4_HTPHY_CFO 0xFF00 /* Coarse frequency offset */
1390
1391/* htphy PhyRxStatus_5: */
1392#define PRXS5_HTPHY_FFO 0x00FF /* Fine frequency offset */
1393#define PRXS5_HTPHY_AR 0xFF00 /* Advance Retard */
1394
1395#define HTPHY_MMPLCPLen(rxs) ((((rxs)->PhyRxStatus_1 & PRXS1_HTPHY_MMPLCPLenL_MASK) >> 8) | \
1396 (((rxs)->PhyRxStatus_2 & PRXS2_HTPHY_MMPLCPLenH_MASK) << 8))
1397/* Get Rx power on core 0 */
1398#define HTPHY_RXPWR_ANT0(rxs) ((((rxs)->PhyRxStatus_2) & PRXS2_HTPHY_RXPWR_ANT0) >> 8)
1399/* Get Rx power on core 1 */
1400#define HTPHY_RXPWR_ANT1(rxs) (((rxs)->PhyRxStatus_3) & PRXS3_HTPHY_RXPWR_ANT1)
1401/* Get Rx power on core 2 */
1402#define HTPHY_RXPWR_ANT2(rxs) ((((rxs)->PhyRxStatus_3) & PRXS3_HTPHY_RXPWR_ANT2) >> 8)
1403
1404/* ucode RxStatus1: */
1405#define RXS_BCNSENT 0x8000
1406#define RXS_SECKINDX_MASK 0x07e0
1407#define RXS_SECKINDX_SHIFT 5
1408#define RXS_DECERR (1 << 4)
1409#define RXS_DECATMPT (1 << 3)
1410#define RXS_PBPRES (1 << 2) /* PAD bytes to make IP data 4 bytes aligned */
1411#define RXS_RESPFRAMETX (1 << 1)
1412#define RXS_FCSERR (1 << 0)
1413
1414/* ucode RxStatus2: */
1415#define RXS_AMSDU_MASK 1
1416#define RXS_AGGTYPE_MASK 0x6
1417#define RXS_AGGTYPE_SHIFT 1
1418#define RXS_PHYRXST_VALID (1 << 8)
1419#define RXS_RXANT_MASK 0x3
1420#define RXS_RXANT_SHIFT 12
1421
1422/* RxChan */
1423#define RXS_CHAN_40 0x1000
1424#define RXS_CHAN_5G 0x0800
1425#define RXS_CHAN_ID_MASK 0x07f8
1426#define RXS_CHAN_ID_SHIFT 3
1427#define RXS_CHAN_PHYTYPE_MASK 0x0007
1428#define RXS_CHAN_PHYTYPE_SHIFT 0
1429
1430/* Index of attenuations used during ucode power control. */
1431#define M_PWRIND_BLKS (0x184 * 2)
1432#define M_PWRIND_MAP0 (M_PWRIND_BLKS + 0x0)
1433#define M_PWRIND_MAP1 (M_PWRIND_BLKS + 0x2)
1434#define M_PWRIND_MAP2 (M_PWRIND_BLKS + 0x4)
1435#define M_PWRIND_MAP3 (M_PWRIND_BLKS + 0x6)
1436/* M_PWRIND_MAP(core) macro */
1437#define M_PWRIND_MAP(core) (M_PWRIND_BLKS + ((core)<<1))
1438
1439/* PSM SHM variable offsets */
1440#define M_PSM_SOFT_REGS 0x0
1441#define M_BOM_REV_MAJOR (M_PSM_SOFT_REGS + 0x0)
1442#define M_BOM_REV_MINOR (M_PSM_SOFT_REGS + 0x2)
1443#define M_UCODE_DBGST (M_PSM_SOFT_REGS + 0x40) /* ucode debug status code */
1444#define M_UCODE_MACSTAT (M_PSM_SOFT_REGS + 0xE0) /* macstat counters */
1445
1446#define M_AGING_THRSH (0x3e * 2) /* max time waiting for medium before tx */
1447#define M_MBURST_SIZE (0x40 * 2) /* max frames in a frameburst */
1448#define M_MBURST_TXOP (0x41 * 2) /* max frameburst TXOP in unit of us */
1449#define M_SYNTHPU_DLY (0x4a * 2) /* pre-wakeup for synthpu, default: 500 */
1450#define M_PRETBTT (0x4b * 2)
1451
1452#define M_ALT_TXPWR_IDX (M_PSM_SOFT_REGS + (0x3b * 2)) /* offset to the target txpwr */
1453#define M_PHY_TX_FLT_PTR (M_PSM_SOFT_REGS + (0x3d * 2))
1454#define M_CTS_DURATION (M_PSM_SOFT_REGS + (0x5c * 2))
1455#define M_LP_RCCAL_OVR (M_PSM_SOFT_REGS + (0x6b * 2))
1456
1457/* PKTENG Rx Stats Block */
1458#define M_RXSTATS_BLK_PTR (M_PSM_SOFT_REGS + (0x65 * 2))
1459
1460/* ucode debug status codes */
1461#define DBGST_INACTIVE 0 /* not valid really */
1462#define DBGST_INIT 1 /* after zeroing SHM, before suspending at init */
1463#define DBGST_ACTIVE 2 /* "normal" state */
1464#define DBGST_SUSPENDED 3 /* suspended */
1465#define DBGST_ASLEEP 4 /* asleep (PS mode) */
1466
1467/* Scratch Reg defs */
1468typedef enum {
1469 S_RSV0 = 0,
1470 S_RSV1,
1471 S_RSV2,
1472
1473 /* scratch registers for Dot11-contants */
1474 S_DOT11_CWMIN, /* CW-minimum 0x03 */
1475 S_DOT11_CWMAX, /* CW-maximum 0x04 */
1476 S_DOT11_CWCUR, /* CW-current 0x05 */
1477 S_DOT11_SRC_LMT, /* short retry count limit 0x06 */
1478 S_DOT11_LRC_LMT, /* long retry count limit 0x07 */
1479 S_DOT11_DTIMCOUNT, /* DTIM-count 0x08 */
1480
1481 /* Tx-side scratch registers */
1482 S_SEQ_NUM, /* hardware sequence number reg 0x09 */
1483 S_SEQ_NUM_FRAG, /* seq-num for frags (Set at the start os MSDU 0x0A */
1484 S_FRMRETX_CNT, /* frame retx count 0x0B */
1485 S_SSRC, /* Station short retry count 0x0C */
1486 S_SLRC, /* Station long retry count 0x0D */
1487 S_EXP_RSP, /* Expected response frame 0x0E */
1488 S_OLD_BREM, /* Remaining backoff ctr 0x0F */
1489 S_OLD_CWWIN, /* saved-off CW-cur 0x10 */
1490 S_TXECTL, /* TXE-Ctl word constructed in scr-pad 0x11 */
1491 S_CTXTST, /* frm type-subtype as read from Tx-descr 0x12 */
1492
1493 /* Rx-side scratch registers */
1494 S_RXTST, /* Type and subtype in Rxframe 0x13 */
1495
1496 /* Global state register */
1497 S_STREG, /* state storage actual bit maps below 0x14 */
1498
1499 S_TXPWR_SUM, /* Tx power control: accumulator 0x15 */
1500 S_TXPWR_ITER, /* Tx power control: iteration 0x16 */
1501 S_RX_FRMTYPE, /* Rate and PHY type for frames 0x17 */
1502 S_THIS_AGG, /* Size of this AGG (A-MSDU) 0x18 */
1503
1504 S_KEYINDX, /* 0x19 */
1505 S_RXFRMLEN, /* Receive MPDU length in bytes 0x1A */
1506
1507 /* Receive TSF time stored in SCR */
1508 S_RXTSFTMRVAL_WD3, /* TSF value at the start of rx 0x1B */
1509 S_RXTSFTMRVAL_WD2, /* TSF value at the start of rx 0x1C */
1510 S_RXTSFTMRVAL_WD1, /* TSF value at the start of rx 0x1D */
1511 S_RXTSFTMRVAL_WD0, /* TSF value at the start of rx 0x1E */
1512 S_RXSSN, /* Received start seq number for A-MPDU BA 0x1F */
1513 S_RXQOSFLD, /* Rx-QoS field (if present) 0x20 */
1514
1515 /* Scratch pad regs used in microcode as temp storage */
1516 S_TMP0, /* stmp0 0x21 */
1517 S_TMP1, /* stmp1 0x22 */
1518 S_TMP2, /* stmp2 0x23 */
1519 S_TMP3, /* stmp3 0x24 */
1520 S_TMP4, /* stmp4 0x25 */
1521 S_TMP5, /* stmp5 0x26 */
1522 S_PRQPENALTY_CTR, /* Probe response queue penalty counter 0x27 */
1523 S_ANTCNT, /* unsuccessful attempts on current ant. 0x28 */
1524 S_SYMBOL, /* flag for possible symbol ctl frames 0x29 */
1525 S_RXTP, /* rx frame type 0x2A */
1526 S_STREG2, /* extra state storage 0x2B */
1527 S_STREG3, /* even more extra state storage 0x2C */
1528 S_STREG4, /* ... 0x2D */
1529 S_STREG5, /* remember to initialize it to zero 0x2E */
1530
1531 S_ADJPWR_IDX,
1532 S_CUR_PTR, /* Temp pointer for A-MPDU re-Tx SHM table 0x32 */
1533 S_REVID4, /* 0x33 */
1534 S_INDX, /* 0x34 */
1535 S_ADDR0, /* 0x35 */
1536 S_ADDR1, /* 0x36 */
1537 S_ADDR2, /* 0x37 */
1538 S_ADDR3, /* 0x38 */
1539 S_ADDR4, /* 0x39 */
1540 S_ADDR5, /* 0x3A */
1541 S_TMP6, /* 0x3B */
1542 S_KEYINDX_BU, /* Backup for Key index 0x3C */
1543 S_MFGTEST_TMP0, /* Temp register used for RX test calculations 0x3D */
1544 S_RXESN, /* Received end sequence number for A-MPDU BA 0x3E */
1545 S_STREG6, /* 0x3F */
1546} ePsmScratchPadRegDefinitions;
1547
1548#define S_BEACON_INDX S_OLD_BREM
1549#define S_PRS_INDX S_OLD_CWWIN
1550#define S_PHYTYPE S_SSRC
1551#define S_PHYVER S_SLRC
1552
1553/* IHR SLOW_CTRL values */
1554#define SLOW_CTRL_PDE (1 << 0)
1555#define SLOW_CTRL_FD (1 << 8)
1556
1557/* ucode mac statistic counters in shared memory */
1558typedef struct macstat {
7d4df48e
GKH		 1559 u16 txallfrm; /* 0x80 */
1560 u16 txrtsfrm; /* 0x82 */
1561 u16 txctsfrm; /* 0x84 */
1562 u16 txackfrm; /* 0x86 */
1563 u16 txdnlfrm; /* 0x88 */
1564 u16 txbcnfrm; /* 0x8a */
1565 u16 txfunfl[8]; /* 0x8c - 0x9b */
1566 u16 txtplunfl; /* 0x9c */
1567 u16 txphyerr; /* 0x9e */
1568 u16 pktengrxducast; /* 0xa0 */
1569 u16 pktengrxdmcast; /* 0xa2 */
1570 u16 rxfrmtoolong; /* 0xa4 */
1571 u16 rxfrmtooshrt; /* 0xa6 */
1572 u16 rxinvmachdr; /* 0xa8 */
1573 u16 rxbadfcs; /* 0xaa */
1574 u16 rxbadplcp; /* 0xac */
1575 u16 rxcrsglitch; /* 0xae */
1576 u16 rxstrt; /* 0xb0 */
1577 u16 rxdfrmucastmbss; /* 0xb2 */
1578 u16 rxmfrmucastmbss; /* 0xb4 */
1579 u16 rxcfrmucast; /* 0xb6 */
1580 u16 rxrtsucast; /* 0xb8 */
1581 u16 rxctsucast; /* 0xba */
1582 u16 rxackucast; /* 0xbc */
1583 u16 rxdfrmocast; /* 0xbe */
1584 u16 rxmfrmocast; /* 0xc0 */
1585 u16 rxcfrmocast; /* 0xc2 */
1586 u16 rxrtsocast; /* 0xc4 */
1587 u16 rxctsocast; /* 0xc6 */
1588 u16 rxdfrmmcast; /* 0xc8 */
1589 u16 rxmfrmmcast; /* 0xca */
1590 u16 rxcfrmmcast; /* 0xcc */
1591 u16 rxbeaconmbss; /* 0xce */
1592 u16 rxdfrmucastobss; /* 0xd0 */
1593 u16 rxbeaconobss; /* 0xd2 */
1594 u16 rxrsptmout; /* 0xd4 */
1595 u16 bcntxcancl; /* 0xd6 */
1596 u16 PAD;
1597 u16 rxf0ovfl; /* 0xda */
1598 u16 rxf1ovfl; /* 0xdc */
1599 u16 rxf2ovfl; /* 0xde */
1600 u16 txsfovfl; /* 0xe0 */
1601 u16 pmqovfl; /* 0xe2 */
1602 u16 rxcgprqfrm; /* 0xe4 */
1603 u16 rxcgprsqovfl; /* 0xe6 */
1604 u16 txcgprsfail; /* 0xe8 */
1605 u16 txcgprssuc; /* 0xea */
1606 u16 prs_timeout; /* 0xec */
1607 u16 rxnack;
1608 u16 frmscons;
1609 u16 txnack;
1610 u16 txglitch_nack;
1611 u16 txburst; /* 0xf6 # tx bursts */
1612 u16 bphy_rxcrsglitch; /* bphy rx crs glitch */
1613 u16 phywatchdog; /* 0xfa # of phy watchdog events */
1614 u16 PAD;
1615 u16 bphy_badplcp; /* bphy bad plcp */
a9533e7e
HP		 1616} macstat_t;
1617
1618/* dot11 core-specific control flags */
1619#define SICF_PCLKE 0x0004 /* PHY clock enable */
1620#define SICF_PRST 0x0008 /* PHY reset */
1621#define SICF_MPCLKE 0x0010 /* MAC PHY clockcontrol enable */
1622#define SICF_FREF 0x0020 /* PLL FreqRefSelect (corerev >= 5) */
1623/* NOTE: the following bw bits only apply when the core is attached
1624 * to a NPHY (and corerev >= 11 which it will always be for NPHYs).
1625 */
1626#define SICF_BWMASK 0x00c0 /* phy clock mask (b6 & b7) */
1627#define SICF_BW40 0x0080 /* 40MHz BW (160MHz phyclk) */
1628#define SICF_BW20 0x0040 /* 20MHz BW (80MHz phyclk) */
1629#define SICF_BW10 0x0000 /* 10MHz BW (40MHz phyclk) */
1630#define SICF_GMODE 0x2000 /* gmode enable */
1631
1632/* dot11 core-specific status flags */
1633#define SISF_2G_PHY 0x0001 /* 2.4G capable phy (corerev >= 5) */
1634#define SISF_5G_PHY 0x0002 /* 5G capable phy (corerev >= 5) */
1635#define SISF_FCLKA 0x0004 /* FastClkAvailable (corerev >= 5) */
1636#define SISF_DB_PHY 0x0008 /* Dualband phy (corerev >= 11) */
1637
1638/* === End of MAC reg, Beginning of PHY(b/a/g/n) reg, radio and LPPHY regs are separated === */
1639
1640#define BPHY_REG_OFT_BASE 0x0
1641/* offsets for indirect access to bphy registers */
1642#define BPHY_BB_CONFIG 0x01
1643#define BPHY_ADCBIAS 0x02
1644#define BPHY_ANACORE 0x03
1645#define BPHY_PHYCRSTH 0x06
1646#define BPHY_TEST 0x0a
1647#define BPHY_PA_TX_TO 0x10
1648#define BPHY_SYNTH_DC_TO 0x11
1649#define BPHY_PA_TX_TIME_UP 0x12
1650#define BPHY_RX_FLTR_TIME_UP 0x13
1651#define BPHY_TX_POWER_OVERRIDE 0x14
1652#define BPHY_RF_OVERRIDE 0x15
1653#define BPHY_RF_TR_LOOKUP1 0x16
1654#define BPHY_RF_TR_LOOKUP2 0x17
1655#define BPHY_COEFFS 0x18
1656#define BPHY_PLL_OUT 0x19
1657#define BPHY_REFRESH_MAIN 0x1a
1658#define BPHY_REFRESH_TO0 0x1b
1659#define BPHY_REFRESH_TO1 0x1c
1660#define BPHY_RSSI_TRESH 0x20
1661#define BPHY_IQ_TRESH_HH 0x21
1662#define BPHY_IQ_TRESH_H 0x22
1663#define BPHY_IQ_TRESH_L 0x23
1664#define BPHY_IQ_TRESH_LL 0x24
1665#define BPHY_GAIN 0x25
1666#define BPHY_LNA_GAIN_RANGE 0x26
1667#define BPHY_JSSI 0x27
1668#define BPHY_TSSI_CTL 0x28
1669#define BPHY_TSSI 0x29
1670#define BPHY_TR_LOSS_CTL 0x2a
1671#define BPHY_LO_LEAKAGE 0x2b
1672#define BPHY_LO_RSSI_ACC 0x2c
1673#define BPHY_LO_IQMAG_ACC 0x2d
1674#define BPHY_TX_DC_OFF1 0x2e
1675#define BPHY_TX_DC_OFF2 0x2f
1676#define BPHY_PEAK_CNT_THRESH 0x30
1677#define BPHY_FREQ_OFFSET 0x31
1678#define BPHY_DIVERSITY_CTL 0x32
1679#define BPHY_PEAK_ENERGY_LO 0x33
1680#define BPHY_PEAK_ENERGY_HI 0x34
1681#define BPHY_SYNC_CTL 0x35
1682#define BPHY_TX_PWR_CTRL 0x36
1683#define BPHY_TX_EST_PWR 0x37
1684#define BPHY_STEP 0x38
1685#define BPHY_WARMUP 0x39
1686#define BPHY_LMS_CFF_READ 0x3a
1687#define BPHY_LMS_COEFF_I 0x3b
1688#define BPHY_LMS_COEFF_Q 0x3c
1689#define BPHY_SIG_POW 0x3d
1690#define BPHY_RFDC_CANCEL_CTL 0x3e
1691#define BPHY_HDR_TYPE 0x40
1692#define BPHY_SFD_TO 0x41
1693#define BPHY_SFD_CTL 0x42
1694#define BPHY_DEBUG 0x43
1695#define BPHY_RX_DELAY_COMP 0x44
1696#define BPHY_CRS_DROP_TO 0x45
1697#define BPHY_SHORT_SFD_NZEROS 0x46
1698#define BPHY_DSSS_COEFF1 0x48
1699#define BPHY_DSSS_COEFF2 0x49
1700#define BPHY_CCK_COEFF1 0x4a
1701#define BPHY_CCK_COEFF2 0x4b
1702#define BPHY_TR_CORR 0x4c
1703#define BPHY_ANGLE_SCALE 0x4d
1704#define BPHY_TX_PWR_BASE_IDX 0x4e
1705#define BPHY_OPTIONAL_MODES2 0x4f
1706#define BPHY_CCK_LMS_STEP 0x50
1707#define BPHY_BYPASS 0x51
1708#define BPHY_CCK_DELAY_LONG 0x52
1709#define BPHY_CCK_DELAY_SHORT 0x53
1710#define BPHY_PPROC_CHAN_DELAY 0x54
1711#define BPHY_DDFS_ENABLE 0x58
1712#define BPHY_PHASE_SCALE 0x59
1713#define BPHY_FREQ_CONTROL 0x5a
1714#define BPHY_LNA_GAIN_RANGE_10 0x5b
1715#define BPHY_LNA_GAIN_RANGE_32 0x5c
1716#define BPHY_OPTIONAL_MODES 0x5d
1717#define BPHY_RX_STATUS2 0x5e
1718#define BPHY_RX_STATUS3 0x5f
1719#define BPHY_DAC_CONTROL 0x60
1720#define BPHY_ANA11G_FILT_CTRL 0x62
1721#define BPHY_REFRESH_CTRL 0x64
1722#define BPHY_RF_OVERRIDE2 0x65
1723#define BPHY_SPUR_CANCEL_CTRL 0x66
1724#define BPHY_FINE_DIGIGAIN_CTRL 0x67
1725#define BPHY_RSSI_LUT 0x88
1726#define BPHY_RSSI_LUT_END 0xa7
1727#define BPHY_TSSI_LUT 0xa8
1728#define BPHY_TSSI_LUT_END 0xc7
1729#define BPHY_TSSI2PWR_LUT 0x380
1730#define BPHY_TSSI2PWR_LUT_END 0x39f
1731#define BPHY_LOCOMP_LUT 0x3a0
1732#define BPHY_LOCOMP_LUT_END 0x3bf
1733#define BPHY_TXGAIN_LUT 0x3c0
1734#define BPHY_TXGAIN_LUT_END 0x3ff
1735
1736/* Bits in BB_CONFIG: */
1737#define PHY_BBC_ANT_MASK 0x0180
1738#define PHY_BBC_ANT_SHIFT 7
1739#define BB_DARWIN 0x1000
1740#define BBCFG_RESETCCA 0x4000
1741#define BBCFG_RESETRX 0x8000
1742
1743/* Bits in phytest(0x0a): */
1744#define TST_DDFS 0x2000
1745#define TST_TXFILT1 0x0800
1746#define TST_UNSCRAM 0x0400
1747#define TST_CARR_SUPP 0x0200
1748#define TST_DC_COMP_LOOP 0x0100
1749#define TST_LOOPBACK 0x0080
1750#define TST_TXFILT0 0x0040
1751#define TST_TXTEST_ENABLE 0x0020
1752#define TST_TXTEST_RATE 0x0018
1753#define TST_TXTEST_PHASE 0x0007
1754
1755/* phytest txTestRate values */
1756#define TST_TXTEST_RATE_1MBPS 0
1757#define TST_TXTEST_RATE_2MBPS 1
1758#define TST_TXTEST_RATE_5_5MBPS 2
1759#define TST_TXTEST_RATE_11MBPS 3
1760#define TST_TXTEST_RATE_SHIFT 3
1761
a9533e7e
HP		 1762#define SHM_BYT_CNT 0x2 /* IHR location */
1763#define MAX_BYT_CNT 0x600 /* Maximum frame len */
1764
1765#endif /* _D11_H */
Linux kernel - Deliverables
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