[deliverable/linux.git] / drivers / staging / brcm80211 / include / siutils.h

/*
 * Copyright (c) 2010 Broadcom Corporation
 *
 * Permission to use, copy, modify, and/or distribute this software for any
 * purpose with or without fee is hereby granted, provided that the above
 * copyright notice and this permission notice appear in all copies.
 *
 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
 * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
 * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
 * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
 */

#ifndef	_siutils_h_
#define	_siutils_h_

#include <hndsoc.h>

/*
 * Data structure to export all chip specific common variables
 *   public (read-only) portion of siutils handle returned by si_attach()
 */
struct si_pub {
	uint socitype;		/* SOCI_SB, SOCI_AI */

	uint bustype;		/* SI_BUS, PCI_BUS */
	uint buscoretype;	/* PCI_CORE_ID, PCIE_CORE_ID, PCMCIA_CORE_ID */
	uint buscorerev;	/* buscore rev */
	uint buscoreidx;	/* buscore index */
	int ccrev;		/* chip common core rev */
	u32 cccaps;		/* chip common capabilities */
	u32 cccaps_ext;	/* chip common capabilities extension */
	int pmurev;		/* pmu core rev */
	u32 pmucaps;		/* pmu capabilities */
	uint boardtype;		/* board type */
	uint boardvendor;	/* board vendor */
	uint boardflags;	/* board flags */
	uint boardflags2;	/* board flags2 */
	uint chip;		/* chip number */
	uint chiprev;		/* chip revision */
	uint chippkg;		/* chip package option */
	u32 chipst;		/* chip status */
	bool issim;		/* chip is in simulation or emulation */
	uint socirev;		/* SOC interconnect rev */
	bool pci_pr32414;

};

/* for HIGH_ONLY driver, the si_t must be writable to allow states sync from BMAC to HIGH driver
 * for monolithic driver, it is readonly to prevent accident change
 */
typedef const struct si_pub si_t;

/*
 * Many of the routines below take an 'sih' handle as their first arg.
 * Allocate this by calling si_attach().  Free it by calling si_detach().
 * At any one time, the sih is logically focused on one particular si core
 * (the "current core").
 * Use si_setcore() or si_setcoreidx() to change the association to another core.
 */

#define	BADIDX		(SI_MAXCORES + 1)

/* clkctl xtal what flags */
#define	XTAL			0x1	/* primary crystal oscillator (2050) */
#define	PLL			0x2	/* main chip pll */

/* clkctl clk mode */
#define	CLK_FAST		0	/* force fast (pll) clock */
#define	CLK_DYNAMIC		2	/* enable dynamic clock control */

/* GPIO usage priorities */
#define GPIO_DRV_PRIORITY	0	/* Driver */
#define GPIO_APP_PRIORITY	1	/* Application */
#define GPIO_HI_PRIORITY	2	/* Highest priority. Ignore GPIO reservation */

/* GPIO pull up/down */
#define GPIO_PULLUP		0
#define GPIO_PULLDN		1

/* GPIO event regtype */
#define GPIO_REGEVT		0	/* GPIO register event */
#define GPIO_REGEVT_INTMSK	1	/* GPIO register event int mask */
#define GPIO_REGEVT_INTPOL	2	/* GPIO register event int polarity */

/* device path */
#define SI_DEVPATH_BUFSZ	16	/* min buffer size in bytes */

/* SI routine enumeration: to be used by update function with multiple hooks */
#define	SI_DOATTACH	1
#define SI_PCIDOWN	2
#define SI_PCIUP	3

#define	ISSIM_ENAB(sih)	0

/* PMU clock/power control */
#if defined(BCMPMUCTL)
#define PMUCTL_ENAB(sih)	(BCMPMUCTL)
#else
#define PMUCTL_ENAB(sih)	((sih)->cccaps & CC_CAP_PMU)
#endif

/* chipcommon clock/power control (exclusive with PMU's) */
#if defined(BCMPMUCTL) && BCMPMUCTL
#define CCCTL_ENAB(sih)		(0)
#define CCPLL_ENAB(sih)		(0)
#else
#define CCCTL_ENAB(sih)		((sih)->cccaps & CC_CAP_PWR_CTL)
#define CCPLL_ENAB(sih)		((sih)->cccaps & CC_CAP_PLL_MASK)
#endif

typedef void (*gpio_handler_t) (u32 stat, void *arg);

/* External PA enable mask */
#define GPIO_CTRL_EPA_EN_MASK 0x40

/* === exported functions === */
extern si_t *si_attach(uint pcidev, void *regs, uint bustype,
		       void *sdh, char **vars, uint *varsz);

extern void si_detach(si_t *sih);
extern bool si_pci_war16165(si_t *sih);

extern uint si_coreid(si_t *sih);
extern uint si_flag(si_t *sih);
extern uint si_coreidx(si_t *sih);
extern uint si_corerev(si_t *sih);
extern uint si_corereg(si_t *sih, uint coreidx, uint regoff, uint mask,
		uint val);
extern void si_write_wrapperreg(si_t *sih, u32 offset, u32 val);
extern u32 si_core_cflags(si_t *sih, u32 mask, u32 val);
extern u32 si_core_sflags(si_t *sih, u32 mask, u32 val);
extern bool si_iscoreup(si_t *sih);
extern uint si_findcoreidx(si_t *sih, uint coreid, uint coreunit);
#ifndef BCMSDIO
extern void *si_setcoreidx(si_t *sih, uint coreidx);
#endif
extern void *si_setcore(si_t *sih, uint coreid, uint coreunit);
extern void *si_switch_core(si_t *sih, uint coreid, uint *origidx,
			    uint *intr_val);
extern void si_restore_core(si_t *sih, uint coreid, uint intr_val);
extern void si_core_reset(si_t *sih, u32 bits, u32 resetbits);
extern void si_core_disable(si_t *sih, u32 bits);
extern u32 si_alp_clock(si_t *sih);
extern u32 si_ilp_clock(si_t *sih);
extern void si_pci_setup(si_t *sih, uint coremask);
extern void si_setint(si_t *sih, int siflag);
extern bool si_backplane64(si_t *sih);
extern void si_register_intr_callback(si_t *sih, void *intrsoff_fn,
				      void *intrsrestore_fn,
				      void *intrsenabled_fn, void *intr_arg);
extern void si_deregister_intr_callback(si_t *sih);
extern void si_clkctl_init(si_t *sih);
extern u16 si_clkctl_fast_pwrup_delay(si_t *sih);
extern bool si_clkctl_cc(si_t *sih, uint mode);
extern int si_clkctl_xtal(si_t *sih, uint what, bool on);
extern bool si_deviceremoved(si_t *sih);
extern u32 si_socram_size(si_t *sih);

extern void si_watchdog(si_t *sih, uint ticks);
extern u32 si_gpiocontrol(si_t *sih, u32 mask, u32 val,
			     u8 priority);

#ifdef BCMSDIO
extern void si_sdio_init(si_t *sih);
#endif

#define si_eci(sih) 0
#define si_eci_init(sih) (0)
#define si_eci_notify_bt(sih, type, val)  (0)
#define si_seci(sih) 0

/* OTP status */
extern bool si_is_otp_disabled(si_t *sih);
extern bool si_is_otp_powered(si_t *sih);
extern void si_otp_power(si_t *sih, bool on);

/* SPROM availability */
extern bool si_is_sprom_available(si_t *sih);
#ifdef SI_SPROM_PROBE
extern void si_sprom_init(si_t *sih);
#endif				/* SI_SPROM_PROBE */

#define	SI_ERROR(args)

#ifdef BCMDBG
#define	SI_MSG(args)	printk args
#else
#define	SI_MSG(args)
#endif				/* BCMDBG */

/* Define SI_VMSG to printf for verbose debugging, but don't check it in */
#define	SI_VMSG(args)

#define	IS_SIM(chippkg)	((chippkg == HDLSIM_PKG_ID) || (chippkg == HWSIM_PKG_ID))

typedef u32(*si_intrsoff_t) (void *intr_arg);
typedef void (*si_intrsrestore_t) (void *intr_arg, u32 arg);
typedef bool(*si_intrsenabled_t) (void *intr_arg);

typedef struct gpioh_item {
	void *arg;
	bool level;
	gpio_handler_t handler;
	u32 event;
	struct gpioh_item *next;
} gpioh_item_t;

/* misc si info needed by some of the routines */
typedef struct si_info {
	struct si_pub pub;	/* back plane public state (must be first) */
	void *pbus;		/* handle to bus (pci/sdio/..) */
	uint dev_coreid;	/* the core provides driver functions */
	void *intr_arg;		/* interrupt callback function arg */
	si_intrsoff_t intrsoff_fn;	/* turns chip interrupts off */
	si_intrsrestore_t intrsrestore_fn;	/* restore chip interrupts */
	si_intrsenabled_t intrsenabled_fn;	/* check if interrupts are enabled */

	void *pch;		/* PCI/E core handle */

	gpioh_item_t *gpioh_head;	/* GPIO event handlers list */

	bool memseg;		/* flag to toggle MEM_SEG register */

	char *vars;
	uint varsz;

	void *curmap;		/* current regs va */
	void *regs[SI_MAXCORES];	/* other regs va */

	uint curidx;		/* current core index */
	uint numcores;		/* # discovered cores */
	uint coreid[SI_MAXCORES];	/* id of each core */
	u32 coresba[SI_MAXCORES];	/* backplane address of each core */
	void *regs2[SI_MAXCORES];	/* va of each core second register set (usbh20) */
	u32 coresba2[SI_MAXCORES];	/* address of each core second register set (usbh20) */
	u32 coresba_size[SI_MAXCORES];	/* backplane address space size */
	u32 coresba2_size[SI_MAXCORES];	/* second address space size */

	void *curwrap;		/* current wrapper va */
	void *wrappers[SI_MAXCORES];	/* other cores wrapper va */
	u32 wrapba[SI_MAXCORES];	/* address of controlling wrapper */

	u32 cia[SI_MAXCORES];	/* erom cia entry for each core */
	u32 cib[SI_MAXCORES];	/* erom cia entry for each core */
	u32 oob_router;	/* oob router registers for axi */
} si_info_t;

#define	SI_INFO(sih)	(si_info_t *)sih

#define	GOODCOREADDR(x, b) (((x) >= (b)) && ((x) < ((b) + SI_MAXCORES * SI_CORE_SIZE)) && \
		IS_ALIGNED((x), SI_CORE_SIZE))
#define	GOODREGS(regs)	((regs) != NULL && IS_ALIGNED((unsigned long)(regs), SI_CORE_SIZE))
#define BADCOREADDR	0
#define	GOODIDX(idx)	(((uint)idx) < SI_MAXCORES)
#define	NOREV		-1	/* Invalid rev */

/* Newer chips can access PCI/PCIE and CC core without requiring to change
 * PCI BAR0 WIN
 */
#define SI_FAST(si) (((si)->pub.buscoretype == PCIE_CORE_ID) ||	\
		     (((si)->pub.buscoretype == PCI_CORE_ID) && (si)->pub.buscorerev >= 13))

#define PCIEREGS(si) (((char *)((si)->curmap) + PCI_16KB0_PCIREGS_OFFSET))
#define CCREGS_FAST(si) (((char *)((si)->curmap) + PCI_16KB0_CCREGS_OFFSET))

/*
 * Macros to disable/restore function core(D11, ENET, ILINE20, etc) interrupts
 * before after core switching to avoid invalid register access inside ISR.
 */
#define INTR_OFF(si, intr_val) \
	if ((si)->intrsoff_fn && (si)->coreid[(si)->curidx] == (si)->dev_coreid) {	\
		intr_val = (*(si)->intrsoff_fn)((si)->intr_arg); }
#define INTR_RESTORE(si, intr_val) \
	if ((si)->intrsrestore_fn && (si)->coreid[(si)->curidx] == (si)->dev_coreid) {	\
		(*(si)->intrsrestore_fn)((si)->intr_arg, intr_val); }

/* dynamic clock control defines */
#define	LPOMINFREQ		25000	/* low power oscillator min */
#define	LPOMAXFREQ		43000	/* low power oscillator max */
#define	XTALMINFREQ		19800000	/* 20 MHz - 1% */
#define	XTALMAXFREQ		20200000	/* 20 MHz + 1% */
#define	PCIMINFREQ		25000000	/* 25 MHz */
#define	PCIMAXFREQ		34000000	/* 33 MHz + fudge */

#define	ILP_DIV_5MHZ		0	/* ILP = 5 MHz */
#define	ILP_DIV_1MHZ		4	/* ILP = 1 MHz */

#define PCI(si)		(((si)->pub.bustype == PCI_BUS) &&	\
			 ((si)->pub.buscoretype == PCI_CORE_ID))
#define PCIE(si)	(((si)->pub.bustype == PCI_BUS) &&	\
			 ((si)->pub.buscoretype == PCIE_CORE_ID))
#define PCI_FORCEHT(si)	\
	(PCIE(si) && (si->pub.chip == BCM4716_CHIP_ID))

/* GPIO Based LED powersave defines */
#define DEFAULT_GPIO_ONTIME	10	/* Default: 10% on */
#define DEFAULT_GPIO_OFFTIME	90	/* Default: 10% on */

#ifndef DEFAULT_GPIOTIMERVAL
#define DEFAULT_GPIOTIMERVAL  ((DEFAULT_GPIO_ONTIME << GPIO_ONTIME_SHIFT) | DEFAULT_GPIO_OFFTIME)
#endif

/*
 * Build device path. Path size must be >= SI_DEVPATH_BUFSZ.
 * The returned path is NULL terminated and has trailing '/'.
 * Return 0 on success, nonzero otherwise.
 */
extern int si_devpath(si_t *sih, char *path, int size);
/* Read variable with prepending the devpath to the name */
extern char *si_getdevpathvar(si_t *sih, const char *name);
extern int si_getdevpathintvar(si_t *sih, const char *name);

extern void si_war42780_clkreq(si_t *sih, bool clkreq);
extern void si_pci_sleep(si_t *sih);
extern void si_pci_down(si_t *sih);
extern void si_pci_up(si_t *sih);
extern void si_pcie_extendL1timer(si_t *sih, bool extend);
extern int si_pci_fixcfg(si_t *sih);

extern void si_chipcontrl_epa4331(si_t *sih, bool on);
/* Enable Ex-PA for 4313 */
extern void si_epa_4313war(si_t *sih);

char *si_getnvramflvar(si_t *sih, const char *name);

/* AMBA Interconnect exported externs */
extern si_t *ai_attach(uint pcidev, struct osl_info *osh, void *regs,
		       uint bustype, void *sdh, char **vars, uint *varsz);
extern si_t *ai_kattach(struct osl_info *osh);
extern void ai_scan(si_t *sih, void *regs, uint devid);

extern uint ai_flag(si_t *sih);
extern void ai_setint(si_t *sih, int siflag);
extern uint ai_coreidx(si_t *sih);
extern uint ai_corevendor(si_t *sih);
extern uint ai_corerev(si_t *sih);
extern bool ai_iscoreup(si_t *sih);
extern void *ai_setcoreidx(si_t *sih, uint coreidx);
extern u32 ai_core_cflags(si_t *sih, u32 mask, u32 val);
extern void ai_core_cflags_wo(si_t *sih, u32 mask, u32 val);
extern u32 ai_core_sflags(si_t *sih, u32 mask, u32 val);
extern uint ai_corereg(si_t *sih, uint coreidx, uint regoff, uint mask,
		       uint val);
extern void ai_core_reset(si_t *sih, u32 bits, u32 resetbits);
extern void ai_core_disable(si_t *sih, u32 bits);
extern int ai_numaddrspaces(si_t *sih);
extern u32 ai_addrspace(si_t *sih, uint asidx);
extern u32 ai_addrspacesize(si_t *sih, uint asidx);
extern void ai_write_wrap_reg(si_t *sih, u32 offset, u32 val);

#ifdef BCMSDIO
#define si_setcoreidx(sih, idx) sb_setcoreidx(sih, idx)
#define si_coreid(sih) sb_coreid(sih)
#define si_corerev(sih) sb_corerev(sih)
#endif

#endif				/* _siutils_h_ */
Commit	Line	Data
a9533e7e HP	1	/*
	2	* Copyright (c) 2010 Broadcom Corporation
	3	*
	4	* Permission to use, copy, modify, and/or distribute this software for any
	5	* purpose with or without fee is hereby granted, provided that the above
	6	* copyright notice and this permission notice appear in all copies.
	7	*
	8	* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
	9	* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
	10	* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
	11	* SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
	12	* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
	13	* OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
	14	* CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
	15	*/
	16
	17	#ifndef _siutils_h_
	18	#define _siutils_h_
	19
	20	#include <hndsoc.h>
	21
a9533e7e HP	22	/*
	23	* Data structure to export all chip specific common variables
	24	* public (read-only) portion of siutils handle returned by si_attach()
	25	*/
	26	struct si_pub {
	27	uint socitype; /* SOCI_SB, SOCI_AI */
	28
	29	uint bustype; /* SI_BUS, PCI_BUS */
	30	uint buscoretype; /* PCI_CORE_ID, PCIE_CORE_ID, PCMCIA_CORE_ID */
	31	uint buscorerev; /* buscore rev */
	32	uint buscoreidx; /* buscore index */
	33	int ccrev; /* chip common core rev */
66cbd3ab GKH	34	u32 cccaps; /* chip common capabilities */
66cbd3ab GKH	35	u32 cccaps_ext; /* chip common capabilities extension */
a9533e7e	36	int pmurev; /* pmu core rev */
66cbd3ab	37	u32 pmucaps; /* pmu capabilities */
a9533e7e HP	38	uint boardtype; /* board type */
	39	uint boardvendor; /* board vendor */
	40	uint boardflags; /* board flags */
	41	uint boardflags2; /* board flags2 */
	42	uint chip; /* chip number */
	43	uint chiprev; /* chip revision */
	44	uint chippkg; /* chip package option */
66cbd3ab	45	u32 chipst; /* chip status */
a9533e7e HP	46	bool issim; /* chip is in simulation or emulation */
	47	uint socirev; /* SOC interconnect rev */
	48	bool pci_pr32414;
	49
a9533e7e HP	50	};
	51
	52	/* for HIGH_ONLY driver, the si_t must be writable to allow states sync from BMAC to HIGH driver
	53	* for monolithic driver, it is readonly to prevent accident change
	54	*/
a9533e7e	55	typedef const struct si_pub si_t;
a9533e7e HP	56
	57	/*
	58	* Many of the routines below take an 'sih' handle as their first arg.
	59	* Allocate this by calling si_attach(). Free it by calling si_detach().
	60	* At any one time, the sih is logically focused on one particular si core
	61	* (the "current core").
	62	* Use si_setcore() or si_setcoreidx() to change the association to another core.
	63	*/
	64
	65	#define BADIDX (SI_MAXCORES + 1)
	66
	67	/* clkctl xtal what flags */
	68	#define XTAL 0x1 /* primary crystal oscillator (2050) */
	69	#define PLL 0x2 /* main chip pll */
	70
	71	/* clkctl clk mode */
	72	#define CLK_FAST 0 /* force fast (pll) clock */
	73	#define CLK_DYNAMIC 2 /* enable dynamic clock control */
	74
	75	/* GPIO usage priorities */
	76	#define GPIO_DRV_PRIORITY 0 /* Driver */
	77	#define GPIO_APP_PRIORITY 1 /* Application */
	78	#define GPIO_HI_PRIORITY 2 /* Highest priority. Ignore GPIO reservation */
	79
	80	/* GPIO pull up/down */
	81	#define GPIO_PULLUP 0
	82	#define GPIO_PULLDN 1
	83
	84	/* GPIO event regtype */
	85	#define GPIO_REGEVT 0 /* GPIO register event */
	86	#define GPIO_REGEVT_INTMSK 1 /* GPIO register event int mask */
	87	#define GPIO_REGEVT_INTPOL 2 /* GPIO register event int polarity */
	88
	89	/* device path */
	90	#define SI_DEVPATH_BUFSZ 16 /* min buffer size in bytes */
	91
	92	/* SI routine enumeration: to be used by update function with multiple hooks */
	93	#define SI_DOATTACH 1
	94	#define SI_PCIDOWN 2
	95	#define SI_PCIUP 3
	96
	97	#define ISSIM_ENAB(sih) 0
	98
	99	/* PMU clock/power control */
	100	#if defined(BCMPMUCTL)
	101	#define PMUCTL_ENAB(sih) (BCMPMUCTL)
	102	#else
	103	#define PMUCTL_ENAB(sih) ((sih)->cccaps & CC_CAP_PMU)
	104	#endif
	105
	106	/* chipcommon clock/power control (exclusive with PMU's) */
	107	#if defined(BCMPMUCTL) && BCMPMUCTL
	108	#define CCCTL_ENAB(sih) (0)
	109	#define CCPLL_ENAB(sih) (0)
	110	#else
	111	#define CCCTL_ENAB(sih) ((sih)->cccaps & CC_CAP_PWR_CTL)
	112	#define CCPLL_ENAB(sih) ((sih)->cccaps & CC_CAP_PLL_MASK)
	113	#endif
	114
66cbd3ab	115	typedef void (gpio_handler_t) (u32 stat, void arg);
a9533e7e HP	116
	117	/* External PA enable mask */
	118	#define GPIO_CTRL_EPA_EN_MASK 0x40
	119
	120	/* === exported functions === */
26bcc181 AS	121	extern si_t si_attach(uint pcidev, void regs, uint bustype,
26bcc181 AS	122	void sdh, char vars, uint varsz);
7cc4a4c0 JC	123
	124	extern void si_detach(si_t *sih);
	125	extern bool si_pci_war16165(si_t *sih);
	126
7cc4a4c0 JC	127	extern uint si_coreid(si_t *sih);
7cc4a4c0 JC	128	extern uint si_flag(si_t *sih);
7cc4a4c0	129	extern uint si_coreidx(si_t *sih);
7cc4a4c0	130	extern uint si_corerev(si_t *sih);
7cc4a4c0	131	extern uint si_corereg(si_t *sih, uint coreidx, uint regoff, uint mask,
1e3950b8	132	uint val);
66cbd3ab GKH	133	extern void si_write_wrapperreg(si_t *sih, u32 offset, u32 val);
	134	extern u32 si_core_cflags(si_t *sih, u32 mask, u32 val);
	135	extern u32 si_core_sflags(si_t *sih, u32 mask, u32 val);
7cc4a4c0 JC	136	extern bool si_iscoreup(si_t *sih);
7cc4a4c0 JC	137	extern uint si_findcoreidx(si_t *sih, uint coreid, uint coreunit);
a9533e7e	138	#ifndef BCMSDIO
7cc4a4c0	139	extern void si_setcoreidx(si_t sih, uint coreidx);
a9533e7e	140	#endif
7cc4a4c0 JC	141	extern void si_setcore(si_t sih, uint coreid, uint coreunit);
	142	extern void si_switch_core(si_t sih, uint coreid, uint *origidx,
	143	uint *intr_val);
	144	extern void si_restore_core(si_t *sih, uint coreid, uint intr_val);
66cbd3ab GKH	145	extern void si_core_reset(si_t *sih, u32 bits, u32 resetbits);
	146	extern void si_core_disable(si_t *sih, u32 bits);
	147	extern u32 si_alp_clock(si_t *sih);
	148	extern u32 si_ilp_clock(si_t *sih);
7cc4a4c0 JC	149	extern void si_pci_setup(si_t *sih, uint coremask);
	150	extern void si_setint(si_t *sih, int siflag);
	151	extern bool si_backplane64(si_t *sih);
	152	extern void si_register_intr_callback(si_t sih, void intrsoff_fn,
a9533e7e HP	153	void *intrsrestore_fn,
a9533e7e HP	154	void intrsenabled_fn, void intr_arg);
7cc4a4c0 JC	155	extern void si_deregister_intr_callback(si_t *sih);
7cc4a4c0 JC	156	extern void si_clkctl_init(si_t *sih);
7d4df48e	157	extern u16 si_clkctl_fast_pwrup_delay(si_t *sih);
7cc4a4c0 JC	158	extern bool si_clkctl_cc(si_t *sih, uint mode);
7cc4a4c0 JC	159	extern int si_clkctl_xtal(si_t *sih, uint what, bool on);
7cc4a4c0	160	extern bool si_deviceremoved(si_t *sih);
66cbd3ab	161	extern u32 si_socram_size(si_t *sih);
7cc4a4c0 JC	162
7cc4a4c0 JC	163	extern void si_watchdog(si_t *sih, uint ticks);
66cbd3ab	164	extern u32 si_gpiocontrol(si_t *sih, u32 mask, u32 val,
de9bca63	165	u8 priority);
a9533e7e HP	166
a9533e7e HP	167	#ifdef BCMSDIO
7cc4a4c0	168	extern void si_sdio_init(si_t *sih);
a9533e7e HP	169	#endif
a9533e7e HP	170
a9533e7e HP	171	#define si_eci(sih) 0
	172	#define si_eci_init(sih) (0)
	173	#define si_eci_notify_bt(sih, type, val) (0)
	174	#define si_seci(sih) 0
a9533e7e HP	175
a9533e7e HP	176	/* OTP status */
7cc4a4c0 JC	177	extern bool si_is_otp_disabled(si_t *sih);
	178	extern bool si_is_otp_powered(si_t *sih);
	179	extern void si_otp_power(si_t *sih, bool on);
a9533e7e HP	180
a9533e7e HP	181	/* SPROM availability */
7cc4a4c0	182	extern bool si_is_sprom_available(si_t *sih);
a9533e7e	183	#ifdef SI_SPROM_PROBE
7cc4a4c0	184	extern void si_sprom_init(si_t *sih);
a9533e7e HP	185	#endif /* SI_SPROM_PROBE */
a9533e7e HP	186
a9533e7e HP	187	#define SI_ERROR(args)
	188
	189	#ifdef BCMDBG
0bef7748	190	#define SI_MSG(args) printk args
a9533e7e HP	191	#else
	192	#define SI_MSG(args)
	193	#endif /* BCMDBG */
	194
	195	/* Define SI_VMSG to printf for verbose debugging, but don't check it in */
	196	#define SI_VMSG(args)
	197
	198	#define IS_SIM(chippkg) ((chippkg == HDLSIM_PKG_ID) \|\| (chippkg == HWSIM_PKG_ID))
	199
66cbd3ab GKH	200	typedef u32(si_intrsoff_t) (void intr_arg);
66cbd3ab GKH	201	typedef void (si_intrsrestore_t) (void intr_arg, u32 arg);
a9533e7e HP	202	typedef bool(si_intrsenabled_t) (void intr_arg);
	203
	204	typedef struct gpioh_item {
	205	void *arg;
	206	bool level;
	207	gpio_handler_t handler;
66cbd3ab	208	u32 event;
a9533e7e HP	209	struct gpioh_item *next;
	210	} gpioh_item_t;
	211
	212	/* misc si info needed by some of the routines */
	213	typedef struct si_info {
06d278c5	214	struct si_pub pub; /* back plane public state (must be first) */
06d278c5	215	void pbus; / handle to bus (pci/sdio/..) */
a9533e7e HP	216	uint dev_coreid; /* the core provides driver functions */
	217	void intr_arg; / interrupt callback function arg */
	218	si_intrsoff_t intrsoff_fn; /* turns chip interrupts off */
	219	si_intrsrestore_t intrsrestore_fn; /* restore chip interrupts */
	220	si_intrsenabled_t intrsenabled_fn; /* check if interrupts are enabled */
	221
	222	void pch; / PCI/E core handle */
	223
	224	gpioh_item_t gpioh_head; / GPIO event handlers list */
	225
	226	bool memseg; /* flag to toggle MEM_SEG register */
	227
	228	char *vars;
	229	uint varsz;
	230
	231	void curmap; / current regs va */
	232	void regs[SI_MAXCORES]; / other regs va */
	233
	234	uint curidx; /* current core index */
	235	uint numcores; /* # discovered cores */
	236	uint coreid[SI_MAXCORES]; /* id of each core */
66cbd3ab	237	u32 coresba[SI_MAXCORES]; /* backplane address of each core */
a9533e7e	238	void regs2[SI_MAXCORES]; / va of each core second register set (usbh20) */
66cbd3ab GKH	239	u32 coresba2[SI_MAXCORES]; /* address of each core second register set (usbh20) */
	240	u32 coresba_size[SI_MAXCORES]; /* backplane address space size */
	241	u32 coresba2_size[SI_MAXCORES]; /* second address space size */
a9533e7e HP	242
	243	void curwrap; / current wrapper va */
	244	void wrappers[SI_MAXCORES]; / other cores wrapper va */
66cbd3ab	245	u32 wrapba[SI_MAXCORES]; /* address of controlling wrapper */
a9533e7e	246
66cbd3ab GKH	247	u32 cia[SI_MAXCORES]; /* erom cia entry for each core */
	248	u32 cib[SI_MAXCORES]; /* erom cia entry for each core */
	249	u32 oob_router; /* oob router registers for axi */
a9533e7e HP	250	} si_info_t;
a9533e7e HP	251
3acf41c5	252	#define SI_INFO(sih) (si_info_t *)sih
a9533e7e HP	253
a9533e7e HP	254	#define GOODCOREADDR(x, b) (((x) >= (b)) && ((x) < ((b) + SI_MAXCORES * SI_CORE_SIZE)) && \
36c63ff6	255	IS_ALIGNED((x), SI_CORE_SIZE))
f024c48a	256	#define GOODREGS(regs) ((regs) != NULL && IS_ALIGNED((unsigned long)(regs), SI_CORE_SIZE))
a9533e7e HP	257	#define BADCOREADDR 0
	258	#define GOODIDX(idx) (((uint)idx) < SI_MAXCORES)
	259	#define NOREV -1 /* Invalid rev */
	260
	261	/* Newer chips can access PCI/PCIE and CC core without requiring to change
	262	* PCI BAR0 WIN
	263	*/
	264	#define SI_FAST(si) (((si)->pub.buscoretype == PCIE_CORE_ID) \|\| \
	265	(((si)->pub.buscoretype == PCI_CORE_ID) && (si)->pub.buscorerev >= 13))
	266
	267	#define PCIEREGS(si) (((char *)((si)->curmap) + PCI_16KB0_PCIREGS_OFFSET))
	268	#define CCREGS_FAST(si) (((char *)((si)->curmap) + PCI_16KB0_CCREGS_OFFSET))
	269
	270	/*
	271	* Macros to disable/restore function core(D11, ENET, ILINE20, etc) interrupts
5ff6a1fd	272	* before after core switching to avoid invalid register access inside ISR.
a9533e7e HP	273	*/
	274	#define INTR_OFF(si, intr_val) \
	275	if ((si)->intrsoff_fn && (si)->coreid[(si)->curidx] == (si)->dev_coreid) { \
	276	intr_val = (*(si)->intrsoff_fn)((si)->intr_arg); }
	277	#define INTR_RESTORE(si, intr_val) \
	278	if ((si)->intrsrestore_fn && (si)->coreid[(si)->curidx] == (si)->dev_coreid) { \
	279	(*(si)->intrsrestore_fn)((si)->intr_arg, intr_val); }
	280
	281	/* dynamic clock control defines */
	282	#define LPOMINFREQ 25000 /* low power oscillator min */
	283	#define LPOMAXFREQ 43000 /* low power oscillator max */
	284	#define XTALMINFREQ 19800000 /* 20 MHz - 1% */
	285	#define XTALMAXFREQ 20200000 /* 20 MHz + 1% */
	286	#define PCIMINFREQ 25000000 /* 25 MHz */
	287	#define PCIMAXFREQ 34000000 /* 33 MHz + fudge */
	288
	289	#define ILP_DIV_5MHZ 0 /* ILP = 5 MHz */
	290	#define ILP_DIV_1MHZ 4 /* ILP = 1 MHz */
	291
fa7a1db2	292	#define PCI(si) (((si)->pub.bustype == PCI_BUS) && \
a9533e7e	293	((si)->pub.buscoretype == PCI_CORE_ID))
fa7a1db2	294	#define PCIE(si) (((si)->pub.bustype == PCI_BUS) && \
a9533e7e HP	295	((si)->pub.buscoretype == PCIE_CORE_ID))
	296	#define PCI_FORCEHT(si) \
	297	(PCIE(si) && (si->pub.chip == BCM4716_CHIP_ID))
	298
	299	/* GPIO Based LED powersave defines */
	300	#define DEFAULT_GPIO_ONTIME 10 /* Default: 10% on */
	301	#define DEFAULT_GPIO_OFFTIME 90 /* Default: 10% on */
	302
	303	#ifndef DEFAULT_GPIOTIMERVAL
	304	#define DEFAULT_GPIOTIMERVAL ((DEFAULT_GPIO_ONTIME << GPIO_ONTIME_SHIFT) \| DEFAULT_GPIO_OFFTIME)
	305	#endif
	306
	307	/*
	308	* Build device path. Path size must be >= SI_DEVPATH_BUFSZ.
	309	* The returned path is NULL terminated and has trailing '/'.
	310	* Return 0 on success, nonzero otherwise.
	311	*/
7cc4a4c0	312	extern int si_devpath(si_t sih, char path, int size);
a9533e7e	313	/* Read variable with prepending the devpath to the name */
7cc4a4c0 JC	314	extern char si_getdevpathvar(si_t sih, const char *name);
	315	extern int si_getdevpathintvar(si_t sih, const char name);
	316
7cc4a4c0 JC	317	extern void si_war42780_clkreq(si_t *sih, bool clkreq);
	318	extern void si_pci_sleep(si_t *sih);
	319	extern void si_pci_down(si_t *sih);
	320	extern void si_pci_up(si_t *sih);
7cc4a4c0 JC	321	extern void si_pcie_extendL1timer(si_t *sih, bool extend);
7cc4a4c0 JC	322	extern int si_pci_fixcfg(si_t *sih);
7cc4a4c0 JC	323
7cc4a4c0 JC	324	extern void si_chipcontrl_epa4331(si_t *sih, bool on);
a9533e7e	325	/* Enable Ex-PA for 4313 */
7cc4a4c0	326	extern void si_epa_4313war(si_t *sih);
a9533e7e	327
7cc4a4c0	328	char si_getnvramflvar(si_t sih, const char *name);
a9533e7e HP	329
a9533e7e HP	330	/* AMBA Interconnect exported externs */
e69284f2 BR	331	extern si_t ai_attach(uint pcidev, struct osl_info osh, void *regs,
	332	uint bustype, void sdh, char vars, uint varsz);
	333	extern si_t ai_kattach(struct osl_info osh);
7cc4a4c0 JC	334	extern void ai_scan(si_t sih, void regs, uint devid);
	335
	336	extern uint ai_flag(si_t *sih);
	337	extern void ai_setint(si_t *sih, int siflag);
	338	extern uint ai_coreidx(si_t *sih);
	339	extern uint ai_corevendor(si_t *sih);
	340	extern uint ai_corerev(si_t *sih);
	341	extern bool ai_iscoreup(si_t *sih);
	342	extern void ai_setcoreidx(si_t sih, uint coreidx);
66cbd3ab GKH	343	extern u32 ai_core_cflags(si_t *sih, u32 mask, u32 val);
	344	extern void ai_core_cflags_wo(si_t *sih, u32 mask, u32 val);
	345	extern u32 ai_core_sflags(si_t *sih, u32 mask, u32 val);
7cc4a4c0	346	extern uint ai_corereg(si_t *sih, uint coreidx, uint regoff, uint mask,
a9533e7e	347	uint val);
66cbd3ab GKH	348	extern void ai_core_reset(si_t *sih, u32 bits, u32 resetbits);
66cbd3ab GKH	349	extern void ai_core_disable(si_t *sih, u32 bits);
7cc4a4c0	350	extern int ai_numaddrspaces(si_t *sih);
66cbd3ab GKH	351	extern u32 ai_addrspace(si_t *sih, uint asidx);
	352	extern u32 ai_addrspacesize(si_t *sih, uint asidx);
	353	extern void ai_write_wrap_reg(si_t *sih, u32 offset, u32 val);
a9533e7e	354
a9533e7e HP	355	#ifdef BCMSDIO
	356	#define si_setcoreidx(sih, idx) sb_setcoreidx(sih, idx)
	357	#define si_coreid(sih) sb_coreid(sih)
	358	#define si_corerev(sih) sb_corerev(sih)
	359	#endif
	360
	361	#endif /* _siutils_h_ */