[deliverable/linux.git] / drivers / staging / brcm80211 / include / siutils.h

/*
 * Copyright (c) 2010 Broadcom Corporation
 *
 * Permission to use, copy, modify, and/or distribute this software for any
 * purpose with or without fee is hereby granted, provided that the above
 * copyright notice and this permission notice appear in all copies.
 *
 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
 * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
 * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
 * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
 */

#ifndef	_siutils_h_
#define	_siutils_h_

#include <hndsoc.h>

#if !defined(WLC_LOW)
#include "bcm_rpc.h"
#endif
/*
 * Data structure to export all chip specific common variables
 *   public (read-only) portion of siutils handle returned by si_attach()
 */
struct si_pub {
	uint socitype;		/* SOCI_SB, SOCI_AI */

	uint bustype;		/* SI_BUS, PCI_BUS */
	uint buscoretype;	/* PCI_CORE_ID, PCIE_CORE_ID, PCMCIA_CORE_ID */
	uint buscorerev;	/* buscore rev */
	uint buscoreidx;	/* buscore index */
	int ccrev;		/* chip common core rev */
	uint32 cccaps;		/* chip common capabilities */
	uint32 cccaps_ext;	/* chip common capabilities extension */
	int pmurev;		/* pmu core rev */
	uint32 pmucaps;		/* pmu capabilities */
	uint boardtype;		/* board type */
	uint boardvendor;	/* board vendor */
	uint boardflags;	/* board flags */
	uint boardflags2;	/* board flags2 */
	uint chip;		/* chip number */
	uint chiprev;		/* chip revision */
	uint chippkg;		/* chip package option */
	uint32 chipst;		/* chip status */
	bool issim;		/* chip is in simulation or emulation */
	uint socirev;		/* SOC interconnect rev */
	bool pci_pr32414;

#if !defined(WLC_LOW)
	rpc_info_t *rpc;
#endif
};

/* for HIGH_ONLY driver, the si_t must be writable to allow states sync from BMAC to HIGH driver
 * for monolithic driver, it is readonly to prevent accident change
 */
#if !defined(WLC_LOW)
typedef struct si_pub si_t;
#else
typedef const struct si_pub si_t;
#endif

/*
 * Many of the routines below take an 'sih' handle as their first arg.
 * Allocate this by calling si_attach().  Free it by calling si_detach().
 * At any one time, the sih is logically focused on one particular si core
 * (the "current core").
 * Use si_setcore() or si_setcoreidx() to change the association to another core.
 */

#define	BADIDX		(SI_MAXCORES + 1)

/* clkctl xtal what flags */
#define	XTAL			0x1	/* primary crystal oscillator (2050) */
#define	PLL			0x2	/* main chip pll */

/* clkctl clk mode */
#define	CLK_FAST		0	/* force fast (pll) clock */
#define	CLK_DYNAMIC		2	/* enable dynamic clock control */

/* GPIO usage priorities */
#define GPIO_DRV_PRIORITY	0	/* Driver */
#define GPIO_APP_PRIORITY	1	/* Application */
#define GPIO_HI_PRIORITY	2	/* Highest priority. Ignore GPIO reservation */

/* GPIO pull up/down */
#define GPIO_PULLUP		0
#define GPIO_PULLDN		1

/* GPIO event regtype */
#define GPIO_REGEVT		0	/* GPIO register event */
#define GPIO_REGEVT_INTMSK	1	/* GPIO register event int mask */
#define GPIO_REGEVT_INTPOL	2	/* GPIO register event int polarity */

/* device path */
#define SI_DEVPATH_BUFSZ	16	/* min buffer size in bytes */

/* SI routine enumeration: to be used by update function with multiple hooks */
#define	SI_DOATTACH	1
#define SI_PCIDOWN	2
#define SI_PCIUP	3

#define	ISSIM_ENAB(sih)	0

/* PMU clock/power control */
#if defined(BCMPMUCTL)
#define PMUCTL_ENAB(sih)	(BCMPMUCTL)
#else
#define PMUCTL_ENAB(sih)	((sih)->cccaps & CC_CAP_PMU)
#endif

/* chipcommon clock/power control (exclusive with PMU's) */
#if defined(BCMPMUCTL) && BCMPMUCTL
#define CCCTL_ENAB(sih)		(0)
#define CCPLL_ENAB(sih)		(0)
#else
#define CCCTL_ENAB(sih)		((sih)->cccaps & CC_CAP_PWR_CTL)
#define CCPLL_ENAB(sih)		((sih)->cccaps & CC_CAP_PLL_MASK)
#endif

typedef void (*gpio_handler_t) (uint32 stat, void *arg);

/* External PA enable mask */
#define GPIO_CTRL_EPA_EN_MASK 0x40

/* === exported functions === */
extern si_t *si_attach(uint pcidev, osl_t *osh, void *regs, uint bustype,
		       void *sdh, char **vars, uint *varsz);

extern void si_detach(si_t *sih);
extern bool si_pci_war16165(si_t *sih);

extern uint si_corelist(si_t *sih, uint coreid[]);
extern uint si_coreid(si_t *sih);
extern uint si_flag(si_t *sih);
extern uint si_intflag(si_t *sih);
extern uint si_coreidx(si_t *sih);
extern uint si_coreunit(si_t *sih);
extern uint si_corevendor(si_t *sih);
extern uint si_corerev(si_t *sih);
extern void *si_osh(si_t *sih);
extern void si_setosh(si_t *sih, osl_t *osh);
extern uint si_corereg(si_t *sih, uint coreidx, uint regoff, uint mask,
		       uint val);
extern void *si_coreregs(si_t *sih);
extern void si_write_wrapperreg(si_t *sih, uint32 offset, uint32 val);
extern uint32 si_core_cflags(si_t *sih, uint32 mask, uint32 val);
extern void si_core_cflags_wo(si_t *sih, uint32 mask, uint32 val);
extern uint32 si_core_sflags(si_t *sih, uint32 mask, uint32 val);
extern bool si_iscoreup(si_t *sih);
extern uint si_findcoreidx(si_t *sih, uint coreid, uint coreunit);
#ifndef BCMSDIO
extern void *si_setcoreidx(si_t *sih, uint coreidx);
#endif
extern void *si_setcore(si_t *sih, uint coreid, uint coreunit);
extern void *si_switch_core(si_t *sih, uint coreid, uint *origidx,
			    uint *intr_val);
extern void si_restore_core(si_t *sih, uint coreid, uint intr_val);
extern int si_numaddrspaces(si_t *sih);
extern uint32 si_addrspace(si_t *sih, uint asidx);
extern uint32 si_addrspacesize(si_t *sih, uint asidx);
extern int si_corebist(si_t *sih);
extern void si_core_reset(si_t *sih, uint32 bits, uint32 resetbits);
extern void si_core_disable(si_t *sih, uint32 bits);
extern uint32 si_clock_rate(uint32 pll_type, uint32 n, uint32 m);
extern uint32 si_clock(si_t *sih);
extern uint32 si_alp_clock(si_t *sih);
extern uint32 si_ilp_clock(si_t *sih);
extern void si_pci_setup(si_t *sih, uint coremask);
extern void si_setint(si_t *sih, int siflag);
extern bool si_backplane64(si_t *sih);
extern void si_register_intr_callback(si_t *sih, void *intrsoff_fn,
				      void *intrsrestore_fn,
				      void *intrsenabled_fn, void *intr_arg);
extern void si_deregister_intr_callback(si_t *sih);
extern void si_clkctl_init(si_t *sih);
extern uint16 si_clkctl_fast_pwrup_delay(si_t *sih);
extern bool si_clkctl_cc(si_t *sih, uint mode);
extern int si_clkctl_xtal(si_t *sih, uint what, bool on);
extern uint32 si_gpiotimerval(si_t *sih, uint32 mask, uint32 val);
extern bool si_deviceremoved(si_t *sih);
extern uint32 si_socram_size(si_t *sih);
extern uint32 si_socdevram_size(si_t *sih);
extern void si_socdevram(si_t *sih, bool set, u8 *ennable,
			 u8 *protect);
extern bool si_socdevram_pkg(si_t *sih);

extern void si_watchdog(si_t *sih, uint ticks);
extern void si_watchdog_ms(si_t *sih, uint32 ms);
extern void *si_gpiosetcore(si_t *sih);
extern uint32 si_gpiocontrol(si_t *sih, uint32 mask, uint32 val,
			     u8 priority);
extern uint32 si_gpioouten(si_t *sih, uint32 mask, uint32 val, u8 priority);
extern uint32 si_gpioout(si_t *sih, uint32 mask, uint32 val, u8 priority);
extern uint32 si_gpioin(si_t *sih);
extern uint32 si_gpiointpolarity(si_t *sih, uint32 mask, uint32 val,
				 u8 priority);
extern uint32 si_gpiointmask(si_t *sih, uint32 mask, uint32 val,
			     u8 priority);
extern uint32 si_gpioled(si_t *sih, uint32 mask, uint32 val);
extern uint32 si_gpioreserve(si_t *sih, uint32 gpio_num, u8 priority);
extern uint32 si_gpiorelease(si_t *sih, uint32 gpio_num, u8 priority);
extern uint32 si_gpiopull(si_t *sih, bool updown, uint32 mask, uint32 val);
extern uint32 si_gpioevent(si_t *sih, uint regtype, uint32 mask, uint32 val);
extern uint32 si_gpio_int_enable(si_t *sih, bool enable);

/* GPIO event handlers */
extern void *si_gpio_handler_register(si_t *sih, uint32 e, bool lev,
				      gpio_handler_t cb, void *arg);
extern void si_gpio_handler_unregister(si_t *sih, void *gpioh);
extern void si_gpio_handler_process(si_t *sih);

/* Wake-on-wireless-LAN (WOWL) */
extern bool si_pci_pmecap(si_t *sih);
struct osl_info;
extern bool si_pci_fastpmecap(struct osl_info *osh);
extern bool si_pci_pmestat(si_t *sih);
extern void si_pci_pmeclr(si_t *sih);
extern void si_pci_pmeen(si_t *sih);
extern uint si_pcie_readreg(void *sih, uint addrtype, uint offset);

#ifdef BCMSDIO
extern void si_sdio_init(si_t *sih);
#endif

extern uint16 si_d11_devid(si_t *sih);

#define si_eci(sih) 0
#define si_eci_init(sih) (0)
#define si_eci_notify_bt(sih, type, val)  (0)
#define si_seci(sih) 0
static inline void *si_seci_init(si_t *sih, u8 use_seci)
{
	return NULL;
}

/* OTP status */
extern bool si_is_otp_disabled(si_t *sih);
extern bool si_is_otp_powered(si_t *sih);
extern void si_otp_power(si_t *sih, bool on);

/* SPROM availability */
extern bool si_is_sprom_available(si_t *sih);
extern bool si_is_sprom_enabled(si_t *sih);
extern void si_sprom_enable(si_t *sih, bool enable);
#ifdef SI_SPROM_PROBE
extern void si_sprom_init(si_t *sih);
#endif				/* SI_SPROM_PROBE */

/* OTP/SROM CIS stuff */
extern int si_cis_source(si_t *sih);
#define CIS_DEFAULT	0
#define CIS_SROM	1
#define CIS_OTP		2

/* Fab-id information */
#define	DEFAULT_FAB	0x0	/* Original/first fab used for this chip */
#define	CSM_FAB7	0x1	/* CSM Fab7 chip */
#define	TSMC_FAB12	0x2	/* TSMC Fab12/Fab14 chip */
#define	SMIC_FAB4	0x3	/* SMIC Fab4 chip */

#define	SI_ERROR(args)

#ifdef BCMDBG
#define	SI_MSG(args)	printf args
#else
#define	SI_MSG(args)
#endif				/* BCMDBG */

/* Define SI_VMSG to printf for verbose debugging, but don't check it in */
#define	SI_VMSG(args)

#define	IS_SIM(chippkg)	((chippkg == HDLSIM_PKG_ID) || (chippkg == HWSIM_PKG_ID))

typedef uint32(*si_intrsoff_t) (void *intr_arg);
typedef void (*si_intrsrestore_t) (void *intr_arg, uint32 arg);
typedef bool(*si_intrsenabled_t) (void *intr_arg);

typedef struct gpioh_item {
	void *arg;
	bool level;
	gpio_handler_t handler;
	uint32 event;
	struct gpioh_item *next;
} gpioh_item_t;

/* misc si info needed by some of the routines */
typedef struct si_info {
	struct si_pub pub;	/* back plane public state (must be first field) */
	void *osh;		/* osl os handle */
	void *sdh;		/* bcmsdh handle */
	uint dev_coreid;	/* the core provides driver functions */
	void *intr_arg;		/* interrupt callback function arg */
	si_intrsoff_t intrsoff_fn;	/* turns chip interrupts off */
	si_intrsrestore_t intrsrestore_fn;	/* restore chip interrupts */
	si_intrsenabled_t intrsenabled_fn;	/* check if interrupts are enabled */

	void *pch;		/* PCI/E core handle */

	gpioh_item_t *gpioh_head;	/* GPIO event handlers list */

	bool memseg;		/* flag to toggle MEM_SEG register */

	char *vars;
	uint varsz;

	void *curmap;		/* current regs va */
	void *regs[SI_MAXCORES];	/* other regs va */

	uint curidx;		/* current core index */
	uint numcores;		/* # discovered cores */
	uint coreid[SI_MAXCORES];	/* id of each core */
	uint32 coresba[SI_MAXCORES];	/* backplane address of each core */
	void *regs2[SI_MAXCORES];	/* va of each core second register set (usbh20) */
	uint32 coresba2[SI_MAXCORES];	/* address of each core second register set (usbh20) */
	uint32 coresba_size[SI_MAXCORES];	/* backplane address space size */
	uint32 coresba2_size[SI_MAXCORES];	/* second address space size */

	void *curwrap;		/* current wrapper va */
	void *wrappers[SI_MAXCORES];	/* other cores wrapper va */
	uint32 wrapba[SI_MAXCORES];	/* address of controlling wrapper */

	uint32 cia[SI_MAXCORES];	/* erom cia entry for each core */
	uint32 cib[SI_MAXCORES];	/* erom cia entry for each core */
	uint32 oob_router;	/* oob router registers for axi */
} si_info_t;

#define	SI_INFO(sih)	(si_info_t *)(uintptr)sih

#define	GOODCOREADDR(x, b) (((x) >= (b)) && ((x) < ((b) + SI_MAXCORES * SI_CORE_SIZE)) && \
		ISALIGNED((x), SI_CORE_SIZE))
#define	GOODREGS(regs)	((regs) != NULL && ISALIGNED((uintptr)(regs), SI_CORE_SIZE))
#define BADCOREADDR	0
#define	GOODIDX(idx)	(((uint)idx) < SI_MAXCORES)
#define	NOREV		-1	/* Invalid rev */

/* Newer chips can access PCI/PCIE and CC core without requiring to change
 * PCI BAR0 WIN
 */
#define SI_FAST(si) (((si)->pub.buscoretype == PCIE_CORE_ID) ||	\
		     (((si)->pub.buscoretype == PCI_CORE_ID) && (si)->pub.buscorerev >= 13))

#define PCIEREGS(si) (((char *)((si)->curmap) + PCI_16KB0_PCIREGS_OFFSET))
#define CCREGS_FAST(si) (((char *)((si)->curmap) + PCI_16KB0_CCREGS_OFFSET))

/*
 * Macros to disable/restore function core(D11, ENET, ILINE20, etc) interrupts
 * before after core switching to avoid invalid register accesss inside ISR.
 */
#define INTR_OFF(si, intr_val) \
	if ((si)->intrsoff_fn && (si)->coreid[(si)->curidx] == (si)->dev_coreid) {	\
		intr_val = (*(si)->intrsoff_fn)((si)->intr_arg); }
#define INTR_RESTORE(si, intr_val) \
	if ((si)->intrsrestore_fn && (si)->coreid[(si)->curidx] == (si)->dev_coreid) {	\
		(*(si)->intrsrestore_fn)((si)->intr_arg, intr_val); }

/* dynamic clock control defines */
#define	LPOMINFREQ		25000	/* low power oscillator min */
#define	LPOMAXFREQ		43000	/* low power oscillator max */
#define	XTALMINFREQ		19800000	/* 20 MHz - 1% */
#define	XTALMAXFREQ		20200000	/* 20 MHz + 1% */
#define	PCIMINFREQ		25000000	/* 25 MHz */
#define	PCIMAXFREQ		34000000	/* 33 MHz + fudge */

#define	ILP_DIV_5MHZ		0	/* ILP = 5 MHz */
#define	ILP_DIV_1MHZ		4	/* ILP = 1 MHz */

#define PCI(si)		((BUSTYPE((si)->pub.bustype) == PCI_BUS) &&	\
			 ((si)->pub.buscoretype == PCI_CORE_ID))
#define PCIE(si)	((BUSTYPE((si)->pub.bustype) == PCI_BUS) &&	\
			 ((si)->pub.buscoretype == PCIE_CORE_ID))
#define PCI_FORCEHT(si)	\
	(PCIE(si) && (si->pub.chip == BCM4716_CHIP_ID))

/* GPIO Based LED powersave defines */
#define DEFAULT_GPIO_ONTIME	10	/* Default: 10% on */
#define DEFAULT_GPIO_OFFTIME	90	/* Default: 10% on */

#ifndef DEFAULT_GPIOTIMERVAL
#define DEFAULT_GPIOTIMERVAL  ((DEFAULT_GPIO_ONTIME << GPIO_ONTIME_SHIFT) | DEFAULT_GPIO_OFFTIME)
#endif

/*
 * Build device path. Path size must be >= SI_DEVPATH_BUFSZ.
 * The returned path is NULL terminated and has trailing '/'.
 * Return 0 on success, nonzero otherwise.
 */
extern int si_devpath(si_t *sih, char *path, int size);
/* Read variable with prepending the devpath to the name */
extern char *si_getdevpathvar(si_t *sih, const char *name);
extern int si_getdevpathintvar(si_t *sih, const char *name);

extern u8 si_pcieclkreq(si_t *sih, uint32 mask, uint32 val);
extern uint32 si_pcielcreg(si_t *sih, uint32 mask, uint32 val);
extern void si_war42780_clkreq(si_t *sih, bool clkreq);
extern void si_pci_sleep(si_t *sih);
extern void si_pci_down(si_t *sih);
extern void si_pci_up(si_t *sih);
extern void si_pcie_war_ovr_update(si_t *sih, u8 aspm);
extern void si_pcie_extendL1timer(si_t *sih, bool extend);
extern int si_pci_fixcfg(si_t *sih);
extern void si_chippkg_set(si_t *sih, uint);

extern void si_chipcontrl_epa4331(si_t *sih, bool on);
/* Enable Ex-PA for 4313 */
extern void si_epa_4313war(si_t *sih);

/* === debug routines === */
extern uint32 si_pciereg(si_t *sih, uint32 offset, uint32 mask, uint32 val,
			 uint type);
extern uint32 si_pcieserdesreg(si_t *sih, uint32 mdioslave, uint32 offset,
			       uint32 mask, uint32 val);

char *si_getnvramflvar(si_t *sih, const char *name);

/* AMBA Interconnect exported externs */
extern si_t *ai_attach(uint pcidev, osl_t *osh, void *regs, uint bustype,
		       void *sdh, char **vars, uint *varsz);
extern si_t *ai_kattach(osl_t *osh);
extern void ai_scan(si_t *sih, void *regs, uint devid);

extern uint ai_flag(si_t *sih);
extern void ai_setint(si_t *sih, int siflag);
extern uint ai_coreidx(si_t *sih);
extern uint ai_corevendor(si_t *sih);
extern uint ai_corerev(si_t *sih);
extern bool ai_iscoreup(si_t *sih);
extern void *ai_setcoreidx(si_t *sih, uint coreidx);
extern uint32 ai_core_cflags(si_t *sih, uint32 mask, uint32 val);
extern void ai_core_cflags_wo(si_t *sih, uint32 mask, uint32 val);
extern uint32 ai_core_sflags(si_t *sih, uint32 mask, uint32 val);
extern uint ai_corereg(si_t *sih, uint coreidx, uint regoff, uint mask,
		       uint val);
extern void ai_core_reset(si_t *sih, uint32 bits, uint32 resetbits);
extern void ai_core_disable(si_t *sih, uint32 bits);
extern int ai_numaddrspaces(si_t *sih);
extern uint32 ai_addrspace(si_t *sih, uint asidx);
extern uint32 ai_addrspacesize(si_t *sih, uint asidx);
extern void ai_write_wrap_reg(si_t *sih, uint32 offset, uint32 val);

#ifdef BCMDBG
extern void ai_view(si_t *sih, bool verbose);
#endif

#ifdef BCMSDIO
#define si_setcoreidx(sih, idx) sb_setcoreidx(sih, idx)
#define si_coreid(sih) sb_coreid(sih)
#define si_corerev(sih) sb_corerev(sih)
#endif

#endif				/* _siutils_h_ */
Commit	Line	Data
a9533e7e HP	1	/*
	2	* Copyright (c) 2010 Broadcom Corporation
	3	*
	4	* Permission to use, copy, modify, and/or distribute this software for any
	5	* purpose with or without fee is hereby granted, provided that the above
	6	* copyright notice and this permission notice appear in all copies.
	7	*
	8	* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
	9	* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
	10	* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
	11	* SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
	12	* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
	13	* OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
	14	* CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
	15	*/
	16
	17	#ifndef _siutils_h_
	18	#define _siutils_h_
	19
	20	#include <hndsoc.h>
	21
	22	#if !defined(WLC_LOW)
	23	#include "bcm_rpc.h"
	24	#endif
	25	/*
	26	* Data structure to export all chip specific common variables
	27	* public (read-only) portion of siutils handle returned by si_attach()
	28	*/
	29	struct si_pub {
	30	uint socitype; /* SOCI_SB, SOCI_AI */
	31
	32	uint bustype; /* SI_BUS, PCI_BUS */
	33	uint buscoretype; /* PCI_CORE_ID, PCIE_CORE_ID, PCMCIA_CORE_ID */
	34	uint buscorerev; /* buscore rev */
	35	uint buscoreidx; /* buscore index */
	36	int ccrev; /* chip common core rev */
	37	uint32 cccaps; /* chip common capabilities */
	38	uint32 cccaps_ext; /* chip common capabilities extension */
	39	int pmurev; /* pmu core rev */
	40	uint32 pmucaps; /* pmu capabilities */
	41	uint boardtype; /* board type */
	42	uint boardvendor; /* board vendor */
	43	uint boardflags; /* board flags */
	44	uint boardflags2; /* board flags2 */
	45	uint chip; /* chip number */
	46	uint chiprev; /* chip revision */
	47	uint chippkg; /* chip package option */
	48	uint32 chipst; /* chip status */
	49	bool issim; /* chip is in simulation or emulation */
	50	uint socirev; /* SOC interconnect rev */
	51	bool pci_pr32414;
	52
	53	#if !defined(WLC_LOW)
	54	rpc_info_t *rpc;
	55	#endif
	56	};
	57
	58	/* for HIGH_ONLY driver, the si_t must be writable to allow states sync from BMAC to HIGH driver
	59	* for monolithic driver, it is readonly to prevent accident change
	60	*/
	61	#if !defined(WLC_LOW)
	62	typedef struct si_pub si_t;
	63	#else
	64	typedef const struct si_pub si_t;
65	#endif
66
67	/*
68	* Many of the routines below take an 'sih' handle as their first arg.
69	* Allocate this by calling si_attach(). Free it by calling si_detach().
70	* At any one time, the sih is logically focused on one particular si core
71	* (the "current core").
72	* Use si_setcore() or si_setcoreidx() to change the association to another core.
73	*/
74
75	#define BADIDX (SI_MAXCORES + 1)
76
77	/* clkctl xtal what flags */
78	#define XTAL 0x1 /* primary crystal oscillator (2050) */
79	#define PLL 0x2 /* main chip pll */
80
81	/* clkctl clk mode */
82	#define CLK_FAST 0 /* force fast (pll) clock */
83	#define CLK_DYNAMIC 2 /* enable dynamic clock control */
84
85	/* GPIO usage priorities */
86	#define GPIO_DRV_PRIORITY 0 /* Driver */
87	#define GPIO_APP_PRIORITY 1 /* Application */
88	#define GPIO_HI_PRIORITY 2 /* Highest priority. Ignore GPIO reservation */
89
90	/* GPIO pull up/down */
91	#define GPIO_PULLUP 0
92	#define GPIO_PULLDN 1
93
94	/* GPIO event regtype */
95	#define GPIO_REGEVT 0 /* GPIO register event */
96	#define GPIO_REGEVT_INTMSK 1 /* GPIO register event int mask */
97	#define GPIO_REGEVT_INTPOL 2 /* GPIO register event int polarity */
98
99	/* device path */
100	#define SI_DEVPATH_BUFSZ 16 /* min buffer size in bytes */
101
102	/* SI routine enumeration: to be used by update function with multiple hooks */
103	#define SI_DOATTACH 1
104	#define SI_PCIDOWN 2
105	#define SI_PCIUP 3
106
107	#define ISSIM_ENAB(sih) 0
108
109	/* PMU clock/power control */
110	#if defined(BCMPMUCTL)
111	#define PMUCTL_ENAB(sih) (BCMPMUCTL)
112	#else
113	#define PMUCTL_ENAB(sih) ((sih)->cccaps & CC_CAP_PMU)
114	#endif
115
116	/* chipcommon clock/power control (exclusive with PMU's) */
117	#if defined(BCMPMUCTL) && BCMPMUCTL
118	#define CCCTL_ENAB(sih) (0)
119	#define CCPLL_ENAB(sih) (0)
120	#else
121	#define CCCTL_ENAB(sih) ((sih)->cccaps & CC_CAP_PWR_CTL)
122	#define CCPLL_ENAB(sih) ((sih)->cccaps & CC_CAP_PLL_MASK)
123	#endif
124
125	typedef void (gpio_handler_t) (uint32 stat, void arg);
126
127	/* External PA enable mask */
128	#define GPIO_CTRL_EPA_EN_MASK 0x40
129
130	/* === exported functions === */
7cc4a4c0 JC	131	extern si_t si_attach(uint pcidev, osl_t osh, void *regs, uint bustype,
	132	void sdh, char vars, uint varsz);
	133
	134	extern void si_detach(si_t *sih);
	135	extern bool si_pci_war16165(si_t *sih);
	136
	137	extern uint si_corelist(si_t *sih, uint coreid[]);
	138	extern uint si_coreid(si_t *sih);
	139	extern uint si_flag(si_t *sih);
	140	extern uint si_intflag(si_t *sih);
	141	extern uint si_coreidx(si_t *sih);
	142	extern uint si_coreunit(si_t *sih);
	143	extern uint si_corevendor(si_t *sih);
	144	extern uint si_corerev(si_t *sih);
	145	extern void si_osh(si_t sih);
	146	extern void si_setosh(si_t sih, osl_t osh);
	147	extern uint si_corereg(si_t *sih, uint coreidx, uint regoff, uint mask,
a9533e7e	148	uint val);
7cc4a4c0 JC	149	extern void si_coreregs(si_t sih);
	150	extern void si_write_wrapperreg(si_t *sih, uint32 offset, uint32 val);
	151	extern uint32 si_core_cflags(si_t *sih, uint32 mask, uint32 val);
	152	extern void si_core_cflags_wo(si_t *sih, uint32 mask, uint32 val);
	153	extern uint32 si_core_sflags(si_t *sih, uint32 mask, uint32 val);
	154	extern bool si_iscoreup(si_t *sih);
	155	extern uint si_findcoreidx(si_t *sih, uint coreid, uint coreunit);
a9533e7e	156	#ifndef BCMSDIO
7cc4a4c0	157	extern void si_setcoreidx(si_t sih, uint coreidx);
a9533e7e	158	#endif
7cc4a4c0 JC	159	extern void si_setcore(si_t sih, uint coreid, uint coreunit);
	160	extern void si_switch_core(si_t sih, uint coreid, uint *origidx,
	161	uint *intr_val);
	162	extern void si_restore_core(si_t *sih, uint coreid, uint intr_val);
	163	extern int si_numaddrspaces(si_t *sih);
	164	extern uint32 si_addrspace(si_t *sih, uint asidx);
	165	extern uint32 si_addrspacesize(si_t *sih, uint asidx);
	166	extern int si_corebist(si_t *sih);
	167	extern void si_core_reset(si_t *sih, uint32 bits, uint32 resetbits);
	168	extern void si_core_disable(si_t *sih, uint32 bits);
a9533e7e	169	extern uint32 si_clock_rate(uint32 pll_type, uint32 n, uint32 m);
7cc4a4c0 JC	170	extern uint32 si_clock(si_t *sih);
	171	extern uint32 si_alp_clock(si_t *sih);
	172	extern uint32 si_ilp_clock(si_t *sih);
	173	extern void si_pci_setup(si_t *sih, uint coremask);
	174	extern void si_setint(si_t *sih, int siflag);
	175	extern bool si_backplane64(si_t *sih);
	176	extern void si_register_intr_callback(si_t sih, void intrsoff_fn,
a9533e7e HP	177	void *intrsrestore_fn,
a9533e7e HP	178	void intrsenabled_fn, void intr_arg);
7cc4a4c0 JC	179	extern void si_deregister_intr_callback(si_t *sih);
	180	extern void si_clkctl_init(si_t *sih);
	181	extern uint16 si_clkctl_fast_pwrup_delay(si_t *sih);
	182	extern bool si_clkctl_cc(si_t *sih, uint mode);
	183	extern int si_clkctl_xtal(si_t *sih, uint what, bool on);
	184	extern uint32 si_gpiotimerval(si_t *sih, uint32 mask, uint32 val);
	185	extern bool si_deviceremoved(si_t *sih);
	186	extern uint32 si_socram_size(si_t *sih);
	187	extern uint32 si_socdevram_size(si_t *sih);
de9bca63 GKH	188	extern void si_socdevram(si_t sih, bool set, u8 ennable,
de9bca63 GKH	189	u8 *protect);
7cc4a4c0 JC	190	extern bool si_socdevram_pkg(si_t *sih);
	191
	192	extern void si_watchdog(si_t *sih, uint ticks);
	193	extern void si_watchdog_ms(si_t *sih, uint32 ms);
	194	extern void si_gpiosetcore(si_t sih);
	195	extern uint32 si_gpiocontrol(si_t *sih, uint32 mask, uint32 val,
de9bca63 GKH	196	u8 priority);
	197	extern uint32 si_gpioouten(si_t *sih, uint32 mask, uint32 val, u8 priority);
	198	extern uint32 si_gpioout(si_t *sih, uint32 mask, uint32 val, u8 priority);
7cc4a4c0 JC	199	extern uint32 si_gpioin(si_t *sih);
7cc4a4c0 JC	200	extern uint32 si_gpiointpolarity(si_t *sih, uint32 mask, uint32 val,
de9bca63	201	u8 priority);
7cc4a4c0	202	extern uint32 si_gpiointmask(si_t *sih, uint32 mask, uint32 val,
de9bca63	203	u8 priority);
7cc4a4c0	204	extern uint32 si_gpioled(si_t *sih, uint32 mask, uint32 val);
de9bca63 GKH	205	extern uint32 si_gpioreserve(si_t *sih, uint32 gpio_num, u8 priority);
de9bca63 GKH	206	extern uint32 si_gpiorelease(si_t *sih, uint32 gpio_num, u8 priority);
7cc4a4c0 JC	207	extern uint32 si_gpiopull(si_t *sih, bool updown, uint32 mask, uint32 val);
	208	extern uint32 si_gpioevent(si_t *sih, uint regtype, uint32 mask, uint32 val);
	209	extern uint32 si_gpio_int_enable(si_t *sih, bool enable);
a9533e7e HP	210
a9533e7e HP	211	/* GPIO event handlers */
7cc4a4c0	212	extern void si_gpio_handler_register(si_t sih, uint32 e, bool lev,
a9533e7e	213	gpio_handler_t cb, void *arg);
7cc4a4c0 JC	214	extern void si_gpio_handler_unregister(si_t sih, void gpioh);
7cc4a4c0 JC	215	extern void si_gpio_handler_process(si_t *sih);
a9533e7e HP	216
a9533e7e HP	217	/* Wake-on-wireless-LAN (WOWL) */
7cc4a4c0	218	extern bool si_pci_pmecap(si_t *sih);
a9533e7e HP	219	struct osl_info;
a9533e7e HP	220	extern bool si_pci_fastpmecap(struct osl_info *osh);
7cc4a4c0 JC	221	extern bool si_pci_pmestat(si_t *sih);
	222	extern void si_pci_pmeclr(si_t *sih);
	223	extern void si_pci_pmeen(si_t *sih);
a9533e7e HP	224	extern uint si_pcie_readreg(void *sih, uint addrtype, uint offset);
	225
	226	#ifdef BCMSDIO
7cc4a4c0	227	extern void si_sdio_init(si_t *sih);
a9533e7e HP	228	#endif
a9533e7e HP	229
7cc4a4c0	230	extern uint16 si_d11_devid(si_t *sih);
a9533e7e HP	231
	232	#define si_eci(sih) 0
	233	#define si_eci_init(sih) (0)
	234	#define si_eci_notify_bt(sih, type, val) (0)
	235	#define si_seci(sih) 0
de9bca63	236	static inline void si_seci_init(si_t sih, u8 use_seci)
a9533e7e HP	237	{
	238	return NULL;
	239	}
	240
	241	/* OTP status */
7cc4a4c0 JC	242	extern bool si_is_otp_disabled(si_t *sih);
	243	extern bool si_is_otp_powered(si_t *sih);
	244	extern void si_otp_power(si_t *sih, bool on);
a9533e7e HP	245
a9533e7e HP	246	/* SPROM availability */
7cc4a4c0 JC	247	extern bool si_is_sprom_available(si_t *sih);
	248	extern bool si_is_sprom_enabled(si_t *sih);
	249	extern void si_sprom_enable(si_t *sih, bool enable);
a9533e7e	250	#ifdef SI_SPROM_PROBE
7cc4a4c0	251	extern void si_sprom_init(si_t *sih);
a9533e7e HP	252	#endif /* SI_SPROM_PROBE */
	253
	254	/* OTP/SROM CIS stuff */
7cc4a4c0	255	extern int si_cis_source(si_t *sih);
a9533e7e HP	256	#define CIS_DEFAULT 0
	257	#define CIS_SROM 1
	258	#define CIS_OTP 2
	259
	260	/* Fab-id information */
	261	#define DEFAULT_FAB 0x0 /* Original/first fab used for this chip */
	262	#define CSM_FAB7 0x1 /* CSM Fab7 chip */
	263	#define TSMC_FAB12 0x2 /* TSMC Fab12/Fab14 chip */
	264	#define SMIC_FAB4 0x3 /* SMIC Fab4 chip */
	265
	266	#define SI_ERROR(args)
	267
	268	#ifdef BCMDBG
	269	#define SI_MSG(args) printf args
	270	#else
	271	#define SI_MSG(args)
	272	#endif /* BCMDBG */
	273
	274	/* Define SI_VMSG to printf for verbose debugging, but don't check it in */
	275	#define SI_VMSG(args)
	276
	277	#define IS_SIM(chippkg) ((chippkg == HDLSIM_PKG_ID) \|\| (chippkg == HWSIM_PKG_ID))
	278
	279	typedef uint32(si_intrsoff_t) (void intr_arg);
	280	typedef void (si_intrsrestore_t) (void intr_arg, uint32 arg);
	281	typedef bool(si_intrsenabled_t) (void intr_arg);
	282
	283	typedef struct gpioh_item {
	284	void *arg;
	285	bool level;
	286	gpio_handler_t handler;
	287	uint32 event;
	288	struct gpioh_item *next;
	289	} gpioh_item_t;
	290
	291	/* misc si info needed by some of the routines */
	292	typedef struct si_info {
	293	struct si_pub pub; /* back plane public state (must be first field) */
	294	void osh; / osl os handle */
	295	void sdh; / bcmsdh handle */
	296	uint dev_coreid; /* the core provides driver functions */
	297	void intr_arg; / interrupt callback function arg */
	298	si_intrsoff_t intrsoff_fn; /* turns chip interrupts off */
	299	si_intrsrestore_t intrsrestore_fn; /* restore chip interrupts */
	300	si_intrsenabled_t intrsenabled_fn; /* check if interrupts are enabled */
	301
	302	void pch; / PCI/E core handle */
	303
	304	gpioh_item_t gpioh_head; / GPIO event handlers list */
	305
	306	bool memseg; /* flag to toggle MEM_SEG register */
	307
	308	char *vars;
	309	uint varsz;
	310
	311	void curmap; / current regs va */
	312	void regs[SI_MAXCORES]; / other regs va */
	313
	314	uint curidx; /* current core index */
	315	uint numcores; /* # discovered cores */
	316	uint coreid[SI_MAXCORES]; /* id of each core */
	317	uint32 coresba[SI_MAXCORES]; /* backplane address of each core */
	318	void regs2[SI_MAXCORES]; / va of each core second register set (usbh20) */
	319	uint32 coresba2[SI_MAXCORES]; /* address of each core second register set (usbh20) */
320	uint32 coresba_size[SI_MAXCORES]; /* backplane address space size */
321	uint32 coresba2_size[SI_MAXCORES]; /* second address space size */
322
323	void curwrap; / current wrapper va */
324	void wrappers[SI_MAXCORES]; / other cores wrapper va */
325	uint32 wrapba[SI_MAXCORES]; /* address of controlling wrapper */
326
327	uint32 cia[SI_MAXCORES]; /* erom cia entry for each core */
328	uint32 cib[SI_MAXCORES]; /* erom cia entry for each core */
329	uint32 oob_router; /* oob router registers for axi */
330	} si_info_t;
331
332	#define SI_INFO(sih) (si_info_t *)(uintptr)sih
333
334	#define GOODCOREADDR(x, b) (((x) >= (b)) && ((x) < ((b) + SI_MAXCORES * SI_CORE_SIZE)) && \
335	ISALIGNED((x), SI_CORE_SIZE))
336	#define GOODREGS(regs) ((regs) != NULL && ISALIGNED((uintptr)(regs), SI_CORE_SIZE))
337	#define BADCOREADDR 0
338	#define GOODIDX(idx) (((uint)idx) < SI_MAXCORES)
339	#define NOREV -1 /* Invalid rev */
340
341	/* Newer chips can access PCI/PCIE and CC core without requiring to change
342	* PCI BAR0 WIN
343	*/
344	#define SI_FAST(si) (((si)->pub.buscoretype == PCIE_CORE_ID) \|\| \
345	(((si)->pub.buscoretype == PCI_CORE_ID) && (si)->pub.buscorerev >= 13))
346
347	#define PCIEREGS(si) (((char *)((si)->curmap) + PCI_16KB0_PCIREGS_OFFSET))
348	#define CCREGS_FAST(si) (((char *)((si)->curmap) + PCI_16KB0_CCREGS_OFFSET))
349
350	/*
351	* Macros to disable/restore function core(D11, ENET, ILINE20, etc) interrupts
352	* before after core switching to avoid invalid register accesss inside ISR.
353	*/
354	#define INTR_OFF(si, intr_val) \
355	if ((si)->intrsoff_fn && (si)->coreid[(si)->curidx] == (si)->dev_coreid) { \
356	intr_val = (*(si)->intrsoff_fn)((si)->intr_arg); }
357	#define INTR_RESTORE(si, intr_val) \
358	if ((si)->intrsrestore_fn && (si)->coreid[(si)->curidx] == (si)->dev_coreid) { \
359	(*(si)->intrsrestore_fn)((si)->intr_arg, intr_val); }
360
361	/* dynamic clock control defines */
362	#define LPOMINFREQ 25000 /* low power oscillator min */
363	#define LPOMAXFREQ 43000 /* low power oscillator max */
364	#define XTALMINFREQ 19800000 /* 20 MHz - 1% */
365	#define XTALMAXFREQ 20200000 /* 20 MHz + 1% */
366	#define PCIMINFREQ 25000000 /* 25 MHz */
367	#define PCIMAXFREQ 34000000 /* 33 MHz + fudge */
368
369	#define ILP_DIV_5MHZ 0 /* ILP = 5 MHz */
370	#define ILP_DIV_1MHZ 4 /* ILP = 1 MHz */
371
372	#define PCI(si) ((BUSTYPE((si)->pub.bustype) == PCI_BUS) && \
373	((si)->pub.buscoretype == PCI_CORE_ID))
374	#define PCIE(si) ((BUSTYPE((si)->pub.bustype) == PCI_BUS) && \
375	((si)->pub.buscoretype == PCIE_CORE_ID))
376	#define PCI_FORCEHT(si) \
377	(PCIE(si) && (si->pub.chip == BCM4716_CHIP_ID))
378
379	/* GPIO Based LED powersave defines */
380	#define DEFAULT_GPIO_ONTIME 10 /* Default: 10% on */
381	#define DEFAULT_GPIO_OFFTIME 90 /* Default: 10% on */
382
383	#ifndef DEFAULT_GPIOTIMERVAL
384	#define DEFAULT_GPIOTIMERVAL ((DEFAULT_GPIO_ONTIME << GPIO_ONTIME_SHIFT) \| DEFAULT_GPIO_OFFTIME)
385	#endif
386
387	/*
388	* Build device path. Path size must be >= SI_DEVPATH_BUFSZ.
389	* The returned path is NULL terminated and has trailing '/'.
390	* Return 0 on success, nonzero otherwise.
391	*/
7cc4a4c0	392	extern int si_devpath(si_t sih, char path, int size);
a9533e7e	393	/* Read variable with prepending the devpath to the name */
7cc4a4c0 JC	394	extern char si_getdevpathvar(si_t sih, const char *name);
	395	extern int si_getdevpathintvar(si_t sih, const char name);
	396
de9bca63	397	extern u8 si_pcieclkreq(si_t *sih, uint32 mask, uint32 val);
7cc4a4c0 JC	398	extern uint32 si_pcielcreg(si_t *sih, uint32 mask, uint32 val);
	399	extern void si_war42780_clkreq(si_t *sih, bool clkreq);
	400	extern void si_pci_sleep(si_t *sih);
	401	extern void si_pci_down(si_t *sih);
	402	extern void si_pci_up(si_t *sih);
de9bca63	403	extern void si_pcie_war_ovr_update(si_t *sih, u8 aspm);
7cc4a4c0 JC	404	extern void si_pcie_extendL1timer(si_t *sih, bool extend);
	405	extern int si_pci_fixcfg(si_t *sih);
	406	extern void si_chippkg_set(si_t *sih, uint);
	407
	408	extern void si_chipcontrl_epa4331(si_t *sih, bool on);
a9533e7e	409	/* Enable Ex-PA for 4313 */
7cc4a4c0	410	extern void si_epa_4313war(si_t *sih);
a9533e7e HP	411
a9533e7e HP	412	/* === debug routines === */
7cc4a4c0	413	extern uint32 si_pciereg(si_t *sih, uint32 offset, uint32 mask, uint32 val,
a9533e7e	414	uint type);
7cc4a4c0	415	extern uint32 si_pcieserdesreg(si_t *sih, uint32 mdioslave, uint32 offset,
a9533e7e HP	416	uint32 mask, uint32 val);
a9533e7e HP	417
7cc4a4c0	418	char si_getnvramflvar(si_t sih, const char *name);
a9533e7e HP	419
a9533e7e HP	420	/* AMBA Interconnect exported externs */
7cc4a4c0 JC	421	extern si_t ai_attach(uint pcidev, osl_t osh, void *regs, uint bustype,
	422	void sdh, char vars, uint varsz);
	423	extern si_t ai_kattach(osl_t osh);
	424	extern void ai_scan(si_t sih, void regs, uint devid);
	425
	426	extern uint ai_flag(si_t *sih);
	427	extern void ai_setint(si_t *sih, int siflag);
	428	extern uint ai_coreidx(si_t *sih);
	429	extern uint ai_corevendor(si_t *sih);
	430	extern uint ai_corerev(si_t *sih);
	431	extern bool ai_iscoreup(si_t *sih);
	432	extern void ai_setcoreidx(si_t sih, uint coreidx);
	433	extern uint32 ai_core_cflags(si_t *sih, uint32 mask, uint32 val);
	434	extern void ai_core_cflags_wo(si_t *sih, uint32 mask, uint32 val);
	435	extern uint32 ai_core_sflags(si_t *sih, uint32 mask, uint32 val);
	436	extern uint ai_corereg(si_t *sih, uint coreidx, uint regoff, uint mask,
a9533e7e	437	uint val);
7cc4a4c0 JC	438	extern void ai_core_reset(si_t *sih, uint32 bits, uint32 resetbits);
	439	extern void ai_core_disable(si_t *sih, uint32 bits);
	440	extern int ai_numaddrspaces(si_t *sih);
	441	extern uint32 ai_addrspace(si_t *sih, uint asidx);
	442	extern uint32 ai_addrspacesize(si_t *sih, uint asidx);
	443	extern void ai_write_wrap_reg(si_t *sih, uint32 offset, uint32 val);
a9533e7e HP	444
a9533e7e HP	445	#ifdef BCMDBG
7cc4a4c0	446	extern void ai_view(si_t *sih, bool verbose);
a9533e7e HP	447	#endif
	448
	449	#ifdef BCMSDIO
	450	#define si_setcoreidx(sih, idx) sb_setcoreidx(sih, idx)
	451	#define si_coreid(sih) sb_coreid(sih)
	452	#define si_corerev(sih) sb_corerev(sih)
	453	#endif
	454
	455	#endif /* _siutils_h_ */