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staging: brcm80211: Move #includes out of d11.h
[deliverable/linux.git] / drivers / staging / brcm80211 / sys / wlc_bmac.c
CommitLineData
a9533e7e
HP		 1/*
2 * Copyright (c) 2010 Broadcom Corporation
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
11 * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
13 * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
14 * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17#ifndef WLC_LOW
18#error "This file needs WLC_LOW"
19#endif
20
a1c16ed2 21#include <linux/kernel.h>
a9533e7e 22#include <wlc_cfg.h>
3327989a 23#include <linuxver.h>
a9533e7e
HP		 24#include <bcmdefs.h>
25#include <osl.h>
26#include <proto/802.11.h>
27#include <bcmwifi.h>
28#include <bcmutils.h>
29#include <siutils.h>
30#include <bcmendian.h>
31#include <wlioctl.h>
32#include <sbconfig.h>
33#include <sbchipc.h>
34#include <pcicfg.h>
35#include <sbhndpio.h>
36#include <sbhnddma.h>
37#include <hnddma.h>
38#include <hndpmu.h>
39#include <d11.h>
40#include <wlc_rate.h>
41#include <wlc_pub.h>
42#include <wlc_channel.h>
43#include <bcmsrom.h>
44#include <wlc_key.h>
a52ba66c 45#include <bcmdevs.h>
a9533e7e
HP		 46/* BMAC_NOTE: a WLC_HIGH compile include of wlc.h adds in more structures and type
47 * dependencies. Need to include these to files to allow a clean include of wlc.h
48 * with WLC_HIGH defined.
49 * At some point we may be able to skip the include of wlc.h and instead just
50 * define a stub wlc_info and band struct to allow rpc calls to get the rpc handle.
51 */
52#include <wlc_mac80211.h>
53#include <wlc_bmac.h>
54#include <wlc_phy_shim.h>
55#include <wlc_phy_hal.h>
56#include <wl_export.h>
57#include "wl_ucode.h"
58#include "d11ucode_ext.h"
59#ifdef BCMSDIO
60#include <bcmsdh.h>
61#endif
62#include <bcmotp.h>
63
64/* BMAC_NOTE: With WLC_HIGH defined, some fns in this file make calls to high level
65 * functions defined in the headers below. We should be eliminating those calls and
66 * will be able to delete these include lines.
67 */
68#include <wlc_antsel.h>
69
70#include <pcie_core.h>
71
72#include <wlc_alloc.h>
73
74#define TIMER_INTERVAL_WATCHDOG_BMAC 1000 /* watchdog timer, in unit of ms */
75
76#define SYNTHPU_DLY_APHY_US 3700 /* a phy synthpu_dly time in us */
77#define SYNTHPU_DLY_BPHY_US 1050 /* b/g phy synthpu_dly time in us, default */
78#define SYNTHPU_DLY_NPHY_US 2048 /* n phy REV3 synthpu_dly time in us, default */
79#define SYNTHPU_DLY_LPPHY_US 300 /* lpphy synthpu_dly time in us */
80
81#define SYNTHPU_DLY_PHY_US_QT 100 /* QT synthpu_dly time in us */
82
83#ifndef BMAC_DUP_TO_REMOVE
84#define WLC_RM_WAIT_TX_SUSPEND 4 /* Wait Tx Suspend */
85
86#define ANTCNT 10 /* vanilla M_MAX_ANTCNT value */
87
88#endif /* BMAC_DUP_TO_REMOVE */
89
90#define DMAREG(wlc_hw, direction, fifonum) (D11REV_LT(wlc_hw->corerev, 11) ? \
91 ((direction == DMA_TX) ? \
e88cf8eb
GKH		 92 (void *)&(wlc_hw->regs->fifo.f32regs.dmaregs[fifonum].xmt) : \
93 (void *)&(wlc_hw->regs->fifo.f32regs.dmaregs[fifonum].rcv)) : \
a9533e7e 94 ((direction == DMA_TX) ? \
e88cf8eb
GKH		 95 (void *)&(wlc_hw->regs->fifo.f64regs[fifonum].dmaxmt) : \
96 (void *)&(wlc_hw->regs->fifo.f64regs[fifonum].dmarcv)))
a9533e7e
HP		 97
98/*
99 * The following table lists the buffer memory allocated to xmt fifos in HW.
100 * the size is in units of 256bytes(one block), total size is HW dependent
101 * ucode has default fifo partition, sw can overwrite if necessary
102 *
103 * This is documented in twiki under the topic UcodeTxFifo. Please ensure
104 * the twiki is updated before making changes.
105 */
106
107#define XMTFIFOTBL_STARTREV 20 /* Starting corerev for the fifo size table */
108
7d4df48e 109static u16 xmtfifo_sz[][NFIFO] = {
a9533e7e
HP		 110 {20, 192, 192, 21, 17, 5}, /* corerev 20: 5120, 49152, 49152, 5376, 4352, 1280 */
111 {9, 58, 22, 14, 14, 5}, /* corerev 21: 2304, 14848, 5632, 3584, 3584, 1280 */
112 {20, 192, 192, 21, 17, 5}, /* corerev 22: 5120, 49152, 49152, 5376, 4352, 1280 */
113 {20, 192, 192, 21, 17, 5}, /* corerev 23: 5120, 49152, 49152, 5376, 4352, 1280 */
114 {9, 58, 22, 14, 14, 5}, /* corerev 24: 2304, 14848, 5632, 3584, 3584, 1280 */
115};
116
7cc4a4c0
JC		 117static void wlc_clkctl_clk(wlc_hw_info_t *wlc, uint mode);
118static void wlc_coreinit(wlc_info_t *wlc);
a9533e7e
HP		 119
120/* used by wlc_wakeucode_init() */
7cc4a4c0 121static void wlc_write_inits(wlc_hw_info_t *wlc_hw, const d11init_t *inits);
66cbd3ab 122static void wlc_ucode_write(wlc_hw_info_t *wlc_hw, const u32 ucode[],
a9533e7e 123 const uint nbytes);
7cc4a4c0
JC		 124static void wlc_ucode_download(wlc_hw_info_t *wlc);
125static void wlc_ucode_txant_set(wlc_hw_info_t *wlc_hw);
a9533e7e
HP		 126
127/* used by wlc_dpc() */
7cc4a4c0 128static bool wlc_bmac_dotxstatus(wlc_hw_info_t *wlc, tx_status_t *txs,
66cbd3ab 129 u32 s2);
7cc4a4c0
JC		 130static bool wlc_bmac_txstatus_corerev4(wlc_hw_info_t *wlc);
131static bool wlc_bmac_txstatus(wlc_hw_info_t *wlc, bool bound, bool *fatal);
132static bool wlc_bmac_recv(wlc_hw_info_t *wlc_hw, uint fifo, bool bound);
a9533e7e
HP		 133
134/* used by wlc_down() */
7cc4a4c0 135static void wlc_flushqueues(wlc_info_t *wlc);
a9533e7e 136
7d4df48e 137static void wlc_write_mhf(wlc_hw_info_t *wlc_hw, u16 *mhfs);
7cc4a4c0
JC		 138static void wlc_mctrl_reset(wlc_hw_info_t *wlc_hw);
139static void wlc_corerev_fifofixup(wlc_hw_info_t *wlc_hw);
a9533e7e
HP		 140
141/* Low Level Prototypes */
7d4df48e 142static u16 wlc_bmac_read_objmem(wlc_hw_info_t *wlc_hw, uint offset,
66cbd3ab 143 u32 sel);
7d4df48e 144static void wlc_bmac_write_objmem(wlc_hw_info_t *wlc_hw, uint offset, u16 v,
66cbd3ab 145 u32 sel);
7cc4a4c0
JC		 146static bool wlc_bmac_attach_dmapio(wlc_info_t *wlc, uint j, bool wme);
147static void wlc_bmac_detach_dmapio(wlc_hw_info_t *wlc_hw);
148static void wlc_ucode_bsinit(wlc_hw_info_t *wlc_hw);
149static bool wlc_validboardtype(wlc_hw_info_t *wlc);
150static bool wlc_isgoodchip(wlc_hw_info_t *wlc_hw);
151static char *wlc_get_macaddr(wlc_hw_info_t *wlc_hw);
7d4df48e 152static void wlc_mhfdef(wlc_info_t *wlc, u16 *mhfs, u16 mhf2_init);
7cc4a4c0
JC		 153static void wlc_mctrl_write(wlc_hw_info_t *wlc_hw);
154static void wlc_ucode_mute_override_set(wlc_hw_info_t *wlc_hw);
155static void wlc_ucode_mute_override_clear(wlc_hw_info_t *wlc_hw);
66cbd3ab
GKH		 156static u32 wlc_wlintrsoff(wlc_info_t *wlc);
157static void wlc_wlintrsrestore(wlc_info_t *wlc, u32 macintmask);
7cc4a4c0
JC		 158static void wlc_gpio_init(wlc_info_t *wlc);
159static void wlc_write_hw_bcntemplate0(wlc_hw_info_t *wlc_hw, void *bcn,
a9533e7e 160 int len);
7cc4a4c0 161static void wlc_write_hw_bcntemplate1(wlc_hw_info_t *wlc_hw, void *bcn,
a9533e7e 162 int len);
7cc4a4c0 163static void wlc_bmac_bsinit(wlc_info_t *wlc, chanspec_t chanspec);
66cbd3ab 164static u32 wlc_setband_inact(wlc_info_t *wlc, uint bandunit);
7cc4a4c0 165static void wlc_bmac_setband(wlc_hw_info_t *wlc_hw, uint bandunit,
a9533e7e 166 chanspec_t chanspec);
7cc4a4c0
JC		 167static void wlc_bmac_update_slot_timing(wlc_hw_info_t *wlc_hw, bool shortslot);
168static void wlc_upd_ofdm_pctl1_table(wlc_hw_info_t *wlc_hw);
7d4df48e 169static u16 wlc_bmac_ofdm_ratetable_offset(wlc_hw_info_t *wlc_hw,
41feb5ed 170 u8 rate);
a9533e7e
HP		 171
172/* === Low Level functions === */
173
7cc4a4c0 174void wlc_bmac_set_shortslot(wlc_hw_info_t *wlc_hw, bool shortslot)
a9533e7e
HP		 175{
176 wlc_hw->shortslot = shortslot;
177
178 if (BAND_2G(wlc_hw->band->bandtype) && wlc_hw->up) {
179 wlc_suspend_mac_and_wait(wlc_hw->wlc);
180 wlc_bmac_update_slot_timing(wlc_hw, shortslot);
181 wlc_enable_mac(wlc_hw->wlc);
182 }
183}
184
185/*
186 * Update the slot timing for standard 11b/g (20us slots)
187 * or shortslot 11g (9us slots)
188 * The PSM needs to be suspended for this call.
189 */
7cc4a4c0 190static void wlc_bmac_update_slot_timing(wlc_hw_info_t *wlc_hw, bool shortslot)
a9533e7e
HP		 191{
192 osl_t *osh;
193 d11regs_t *regs;
194
195 osh = wlc_hw->osh;
196 regs = wlc_hw->regs;
197
198 if (shortslot) {
199 /* 11g short slot: 11a timing */
200 W_REG(osh, &regs->ifs_slot, 0x0207); /* APHY_SLOT_TIME */
201 wlc_bmac_write_shm(wlc_hw, M_DOT11_SLOT, APHY_SLOT_TIME);
202 } else {
203 /* 11g long slot: 11b timing */
204 W_REG(osh, &regs->ifs_slot, 0x0212); /* BPHY_SLOT_TIME */
205 wlc_bmac_write_shm(wlc_hw, M_DOT11_SLOT, BPHY_SLOT_TIME);
206 }
207}
208
a2627bc0
JC		 209static void WLBANDINITFN(wlc_ucode_bsinit) (wlc_hw_info_t *wlc_hw)
210{
a9533e7e
HP		 211 /* init microcode host flags */
212 wlc_write_mhf(wlc_hw, wlc_hw->band->mhfs);
213
214 /* do band-specific ucode IHR, SHM, and SCR inits */
215 if (D11REV_IS(wlc_hw->corerev, 23)) {
216 if (WLCISNPHY(wlc_hw->band)) {
217 wlc_write_inits(wlc_hw, d11n0bsinitvals16);
218 } else {
219 WL_ERROR(("%s: wl%d: unsupported phy in corerev %d\n",
220 __func__, wlc_hw->unit, wlc_hw->corerev));
221 }
222 } else {
223 if (D11REV_IS(wlc_hw->corerev, 24)) {
224 if (WLCISLCNPHY(wlc_hw->band)) {
225 wlc_write_inits(wlc_hw, d11lcn0bsinitvals24);
226 } else
227 WL_ERROR(("%s: wl%d: unsupported phy in corerev %d\n", __func__, wlc_hw->unit, wlc_hw->corerev));
228 } else {
229 WL_ERROR(("%s: wl%d: unsupported corerev %d\n",
230 __func__, wlc_hw->unit, wlc_hw->corerev));
231 }
232 }
233}
234
235/* switch to new band but leave it inactive */
66cbd3ab 236static u32 WLBANDINITFN(wlc_setband_inact) (wlc_info_t *wlc, uint bandunit)
a2627bc0 237{
a9533e7e 238 wlc_hw_info_t *wlc_hw = wlc->hw;
66cbd3ab
GKH		 239 u32 macintmask;
240 u32 tmp;
a9533e7e
HP		 241
242 WL_TRACE(("wl%d: wlc_setband_inact\n", wlc_hw->unit));
243
244 ASSERT(bandunit != wlc_hw->band->bandunit);
245 ASSERT(si_iscoreup(wlc_hw->sih));
246 ASSERT((R_REG(wlc_hw->osh, &wlc_hw->regs->maccontrol) & MCTL_EN_MAC) ==
247 0);
248
249 /* disable interrupts */
250 macintmask = wl_intrsoff(wlc->wl);
251
252 /* radio off */
253 wlc_phy_switch_radio(wlc_hw->band->pi, OFF);
254
255 ASSERT(wlc_hw->clk);
256
257 if (D11REV_LT(wlc_hw->corerev, 17))
258 tmp = R_REG(wlc_hw->osh, &wlc_hw->regs->maccontrol);
259
260 wlc_bmac_core_phy_clk(wlc_hw, OFF);
261
262 wlc_setxband(wlc_hw, bandunit);
263
90ea2296 264 return macintmask;
a9533e7e
HP		 265}
266
267/* Process received frames */
268/*
0965ae88 269 * Return true if more frames need to be processed. false otherwise.
a9533e7e
HP		 270 * Param 'bound' indicates max. # frames to process before break out.
271 */
272static bool BCMFASTPATH
7cc4a4c0 273wlc_bmac_recv(wlc_hw_info_t *wlc_hw, uint fifo, bool bound)
a9533e7e
HP		 274{
275 void *p;
276 void *head = NULL;
277 void *tail = NULL;
278 uint n = 0;
279 uint bound_limit = bound ? wlc_hw->wlc->pub->tunables->rxbnd : -1;
66cbd3ab 280 u32 tsf_h, tsf_l;
a9533e7e
HP		 281 wlc_d11rxhdr_t *wlc_rxhdr = NULL;
282
283 WL_TRACE(("wl%d: %s\n", wlc_hw->unit, __func__));
284 /* gather received frames */
285 while ((p = dma_rx(wlc_hw->di[fifo]))) {
286
287 if (!tail)
288 head = tail = p;
289 else {
290 PKTSETLINK(tail, p);
291 tail = p;
292 }
293
294 /* !give others some time to run! */
295 if (++n >= bound_limit)
296 break;
297 }
298
299 /* get the TSF REG reading */
300 wlc_bmac_read_tsf(wlc_hw, &tsf_l, &tsf_h);
301
302 /* post more rbufs */
303 dma_rxfill(wlc_hw->di[fifo]);
304
305 /* process each frame */
306 while ((p = head) != NULL) {
307 head = PKTLINK(head);
308 PKTSETLINK(p, NULL);
309
310 /* record the tsf_l in wlc_rxd11hdr */
311 wlc_rxhdr = (wlc_d11rxhdr_t *) PKTDATA(p);
312 wlc_rxhdr->tsf_l = htol32(tsf_l);
313
314 /* compute the RSSI from d11rxhdr and record it in wlc_rxd11hr */
315 wlc_phy_rssi_compute(wlc_hw->band->pi, wlc_rxhdr);
316
317 wlc_recv(wlc_hw->wlc, p);
318 }
319
90ea2296 320 return n >= bound_limit;
a9533e7e
HP		 321}
322
323/* second-level interrupt processing
0965ae88 324 * Return true if another dpc needs to be re-scheduled. false otherwise.
a9533e7e
HP		 325 * Param 'bounded' indicates if applicable loops should be bounded.
326 */
7cc4a4c0 327bool BCMFASTPATH wlc_dpc(wlc_info_t *wlc, bool bounded)
a9533e7e 328{
66cbd3ab 329 u32 macintstatus;
a9533e7e
HP		 330 wlc_hw_info_t *wlc_hw = wlc->hw;
331 d11regs_t *regs = wlc_hw->regs;
0965ae88 332 bool fatal = false;
a9533e7e
HP		 333
334 if (DEVICEREMOVED(wlc)) {
335 WL_ERROR(("wl%d: %s: dead chip\n", wlc_hw->unit, __func__));
336 wl_down(wlc->wl);
0965ae88 337 return false;
a9533e7e
HP		 338 }
339
340 /* grab and clear the saved software intstatus bits */
341 macintstatus = wlc->macintstatus;
342 wlc->macintstatus = 0;
343
344 WL_TRACE(("wl%d: wlc_dpc: macintstatus 0x%x\n", wlc_hw->unit,
345 macintstatus));
346
347 if (macintstatus & MI_PRQ) {
348 /* Process probe request FIFO */
349 ASSERT(0 && "PRQ Interrupt in non-MBSS");
350 }
351
352 /* BCN template is available */
353 /* ZZZ: Use AP_ACTIVE ? */
354 if (AP_ENAB(wlc->pub) && (!APSTA_ENAB(wlc->pub) || wlc->aps_associated)
355 && (macintstatus & MI_BCNTPL)) {
356 wlc_update_beacon(wlc);
357 }
358
359 /* PMQ entry addition */
360 if (macintstatus & MI_PMQ) {
361 }
362
363 /* tx status */
364 if (macintstatus & MI_TFS) {
365 if (wlc_bmac_txstatus(wlc->hw, bounded, &fatal))
366 wlc->macintstatus |= MI_TFS;
367 if (fatal) {
368 WL_ERROR(("MI_TFS: fatal\n"));
369 goto fatal;
370 }
371 }
372
373 if (macintstatus & (MI_TBTT | MI_DTIM_TBTT))
374 wlc_tbtt(wlc, regs);
375
376 /* ATIM window end */
377 if (macintstatus & MI_ATIMWINEND) {
378 WL_TRACE(("wlc_isr: end of ATIM window\n"));
379
380 OR_REG(wlc_hw->osh, &regs->maccommand, wlc->qvalid);
381 wlc->qvalid = 0;
382 }
383
384 /* phy tx error */
385 if (macintstatus & MI_PHYTXERR) {
386 WLCNTINCR(wlc->pub->_cnt->txphyerr);
387 }
388
389 /* received data or control frame, MI_DMAINT is indication of RX_FIFO interrupt */
390 if (macintstatus & MI_DMAINT) {
391 if (wlc_bmac_recv(wlc_hw, RX_FIFO, bounded)) {
392 wlc->macintstatus |= MI_DMAINT;
393 }
394 }
395
396 /* TX FIFO suspend/flush completion */
397 if (macintstatus & MI_TXSTOP) {
398 if (wlc_bmac_tx_fifo_suspended(wlc_hw, TX_DATA_FIFO)) {
399 /* WL_ERROR(("dpc: fifo_suspend_comlete\n")); */
400 }
401 }
402
403 /* noise sample collected */
404 if (macintstatus & MI_BG_NOISE) {
405 wlc_phy_noise_sample_intr(wlc_hw->band->pi);
406 }
407
408 if (macintstatus & MI_GP0) {
409 WL_ERROR(("wl%d: PSM microcode watchdog fired at %d (seconds). Resetting.\n", wlc_hw->unit, wlc_hw->now));
410
411 printk_once("%s : PSM Watchdog, chipid 0x%x, chiprev 0x%x\n",
412 __func__, CHIPID(wlc_hw->sih->chip),
413 CHIPREV(wlc_hw->sih->chiprev));
414
415 WLCNTINCR(wlc->pub->_cnt->psmwds);
416
417 /* big hammer */
418 wl_init(wlc->wl);
419 }
420
421 /* gptimer timeout */
422 if (macintstatus & MI_TO) {
423 W_REG(wlc_hw->osh, &regs->gptimer, 0);
424 }
425
426 if (macintstatus & MI_RFDISABLE) {
427#if defined(BCMDBG)
66cbd3ab 428 u32 rfd = R_REG(wlc_hw->osh, &regs->phydebug) & PDBG_RFD;
a9533e7e
HP		 429#endif
430
431 WL_ERROR(("wl%d: MAC Detected a change on the RF Disable Input 0x%x\n", wlc_hw->unit, rfd));
432
433 WLCNTINCR(wlc->pub->_cnt->rfdisable);
434 }
435
436 /* send any enq'd tx packets. Just makes sure to jump start tx */
437 if (!pktq_empty(&wlc->active_queue->q))
438 wlc_send_q(wlc, wlc->active_queue);
439
440 ASSERT(wlc_ps_check(wlc));
441
442 /* make sure the bound indication and the implementation are in sync */
0f0881b0 443 ASSERT(bounded == true || wlc->macintstatus == 0);
a9533e7e
HP		 444
445 /* it isn't done and needs to be resched if macintstatus is non-zero */
90ea2296 446 return wlc->macintstatus != 0;
a9533e7e
HP		 447
448 fatal:
449 wl_init(wlc->wl);
90ea2296 450 return wlc->macintstatus != 0;
a9533e7e
HP		 451}
452
453/* common low-level watchdog code */
454void wlc_bmac_watchdog(void *arg)
455{
456 wlc_info_t *wlc = (wlc_info_t *) arg;
457 wlc_hw_info_t *wlc_hw = wlc->hw;
458
459 WL_TRACE(("wl%d: wlc_bmac_watchdog\n", wlc_hw->unit));
460
461 if (!wlc_hw->up)
462 return;
463
464 /* increment second count */
465 wlc_hw->now++;
466
467 /* Check for FIFO error interrupts */
468 wlc_bmac_fifoerrors(wlc_hw);
469
470 /* make sure RX dma has buffers */
471 dma_rxfill(wlc->hw->di[RX_FIFO]);
472 if (D11REV_IS(wlc_hw->corerev, 4)) {
473 dma_rxfill(wlc->hw->di[RX_TXSTATUS_FIFO]);
474 }
475
476 wlc_phy_watchdog(wlc_hw->band->pi);
477}
478
479void
7cc4a4c0 480wlc_bmac_set_chanspec(wlc_hw_info_t *wlc_hw, chanspec_t chanspec, bool mute,
a9533e7e
HP		 481 struct txpwr_limits *txpwr)
482{
483 uint bandunit;
484
485 WL_TRACE(("wl%d: wlc_bmac_set_chanspec 0x%x\n", wlc_hw->unit,
486 chanspec));
487
488 wlc_hw->chanspec = chanspec;
489
490 /* Switch bands if necessary */
491 if (NBANDS_HW(wlc_hw) > 1) {
492 bandunit = CHSPEC_WLCBANDUNIT(chanspec);
493 if (wlc_hw->band->bandunit != bandunit) {
494 /* wlc_bmac_setband disables other bandunit,
495 * use light band switch if not up yet
496 */
497 if (wlc_hw->up) {
498 wlc_phy_chanspec_radio_set(wlc_hw->
499 bandstate[bandunit]->
500 pi, chanspec);
501 wlc_bmac_setband(wlc_hw, bandunit, chanspec);
502 } else {
503 wlc_setxband(wlc_hw, bandunit);
504 }
505 }
506 }
507
508 wlc_phy_initcal_enable(wlc_hw->band->pi, !mute);
509
510 if (!wlc_hw->up) {
511 if (wlc_hw->clk)
512 wlc_phy_txpower_limit_set(wlc_hw->band->pi, txpwr,
513 chanspec);
514 wlc_phy_chanspec_radio_set(wlc_hw->band->pi, chanspec);
515 } else {
516 wlc_phy_chanspec_set(wlc_hw->band->pi, chanspec);
517 wlc_phy_txpower_limit_set(wlc_hw->band->pi, txpwr, chanspec);
518
519 /* Update muting of the channel */
520 wlc_bmac_mute(wlc_hw, mute, 0);
521 }
522}
523
7cc4a4c0 524int wlc_bmac_revinfo_get(wlc_hw_info_t *wlc_hw, wlc_bmac_revinfo_t *revinfo)
a9533e7e
HP		 525{
526 si_t *sih = wlc_hw->sih;
527 uint idx;
528
529 revinfo->vendorid = wlc_hw->vendorid;
530 revinfo->deviceid = wlc_hw->deviceid;
531
532 revinfo->boardrev = wlc_hw->boardrev;
533 revinfo->corerev = wlc_hw->corerev;
534 revinfo->sromrev = wlc_hw->sromrev;
535 revinfo->chiprev = sih->chiprev;
536 revinfo->chip = sih->chip;
537 revinfo->chippkg = sih->chippkg;
538 revinfo->boardtype = sih->boardtype;
539 revinfo->boardvendor = sih->boardvendor;
540 revinfo->bustype = sih->bustype;
541 revinfo->buscoretype = sih->buscoretype;
542 revinfo->buscorerev = sih->buscorerev;
543 revinfo->issim = sih->issim;
544
545 revinfo->nbands = NBANDS_HW(wlc_hw);
546
547 for (idx = 0; idx < NBANDS_HW(wlc_hw); idx++) {
548 wlc_hwband_t *band = wlc_hw->bandstate[idx];
549 revinfo->band[idx].bandunit = band->bandunit;
550 revinfo->band[idx].bandtype = band->bandtype;
551 revinfo->band[idx].phytype = band->phytype;
552 revinfo->band[idx].phyrev = band->phyrev;
553 revinfo->band[idx].radioid = band->radioid;
554 revinfo->band[idx].radiorev = band->radiorev;
555 revinfo->band[idx].abgphy_encore = band->abgphy_encore;
556 revinfo->band[idx].anarev = 0;
557
558 }
559 return 0;
560}
561
7cc4a4c0 562int wlc_bmac_state_get(wlc_hw_info_t *wlc_hw, wlc_bmac_state_t *state)
a9533e7e
HP		 563{
564 state->machwcap = wlc_hw->machwcap;
565
566 return 0;
567}
568
0d2f0724 569static bool wlc_bmac_attach_dmapio(wlc_info_t *wlc, uint j, bool wme)
a2627bc0 570{
a9533e7e
HP		 571 uint i;
572 char name[8];
573 /* ucode host flag 2 needed for pio mode, independent of band and fifo */
7d4df48e 574 u16 pio_mhf2 = 0;
a9533e7e
HP		 575 wlc_hw_info_t *wlc_hw = wlc->hw;
576 uint unit = wlc_hw->unit;
577 wlc_tunables_t *tune = wlc->pub->tunables;
578
579 /* name and offsets for dma_attach */
580 snprintf(name, sizeof(name), "wl%d", unit);
581
582 if (wlc_hw->di[0] == 0) { /* Init FIFOs */
583 uint addrwidth;
584 int dma_attach_err = 0;
585 osl_t *osh = wlc_hw->osh;
586
587 /* Find out the DMA addressing capability and let OS know
588 * All the channels within one DMA core have 'common-minimum' same
589 * capability
590 */
591 addrwidth =
592 dma_addrwidth(wlc_hw->sih, DMAREG(wlc_hw, DMA_TX, 0));
593 OSL_DMADDRWIDTH(osh, addrwidth);
594
595 if (!wl_alloc_dma_resources(wlc_hw->wlc->wl, addrwidth)) {
596 WL_ERROR(("wl%d: wlc_attach: alloc_dma_resources failed\n", unit));
0965ae88 597 return false;
a9533e7e
HP		 598 }
599
600 /*
601 * FIFO 0
602 * TX: TX_AC_BK_FIFO (TX AC Background data packets)
603 * RX: RX_FIFO (RX data packets)
604 */
605 ASSERT(TX_AC_BK_FIFO == 0);
606 ASSERT(RX_FIFO == 0);
607 wlc_hw->di[0] = dma_attach(osh, name, wlc_hw->sih,
608 (wme ? DMAREG(wlc_hw, DMA_TX, 0) :
609 NULL), DMAREG(wlc_hw, DMA_RX, 0),
610 (wme ? tune->ntxd : 0), tune->nrxd,
611 tune->rxbufsz, -1, tune->nrxbufpost,
612 WL_HWRXOFF, &wl_msg_level);
613 dma_attach_err |= (NULL == wlc_hw->di[0]);
614
615 /*
616 * FIFO 1
617 * TX: TX_AC_BE_FIFO (TX AC Best-Effort data packets)
618 * (legacy) TX_DATA_FIFO (TX data packets)
619 * RX: UNUSED
620 */
621 ASSERT(TX_AC_BE_FIFO == 1);
622 ASSERT(TX_DATA_FIFO == 1);
623 wlc_hw->di[1] = dma_attach(osh, name, wlc_hw->sih,
624 DMAREG(wlc_hw, DMA_TX, 1), NULL,
625 tune->ntxd, 0, 0, -1, 0, 0,
626 &wl_msg_level);
627 dma_attach_err |= (NULL == wlc_hw->di[1]);
628
629 /*
630 * FIFO 2
631 * TX: TX_AC_VI_FIFO (TX AC Video data packets)
632 * RX: UNUSED
633 */
634 ASSERT(TX_AC_VI_FIFO == 2);
635 wlc_hw->di[2] = dma_attach(osh, name, wlc_hw->sih,
636 DMAREG(wlc_hw, DMA_TX, 2), NULL,
637 tune->ntxd, 0, 0, -1, 0, 0,
638 &wl_msg_level);
639 dma_attach_err |= (NULL == wlc_hw->di[2]);
640 /*
641 * FIFO 3
642 * TX: TX_AC_VO_FIFO (TX AC Voice data packets)
643 * (legacy) TX_CTL_FIFO (TX control & mgmt packets)
644 * RX: RX_TXSTATUS_FIFO (transmit-status packets)
645 * for corerev < 5 only
646 */
647 ASSERT(TX_AC_VO_FIFO == 3);
648 ASSERT(TX_CTL_FIFO == 3);
649 if (D11REV_IS(wlc_hw->corerev, 4)) {
650 ASSERT(RX_TXSTATUS_FIFO == 3);
651 wlc_hw->di[3] = dma_attach(osh, name, wlc_hw->sih,
652 DMAREG(wlc_hw, DMA_TX, 3),
653 DMAREG(wlc_hw, DMA_RX, 3),
654 tune->ntxd, tune->nrxd,
655 sizeof(tx_status_t), -1,
656 tune->nrxbufpost, 0,
657 &wl_msg_level);
658 dma_attach_err |= (NULL == wlc_hw->di[3]);
659 } else {
660 wlc_hw->di[3] = dma_attach(osh, name, wlc_hw->sih,
661 DMAREG(wlc_hw, DMA_TX, 3),
662 NULL, tune->ntxd, 0, 0, -1,
663 0, 0, &wl_msg_level);
664 dma_attach_err |= (NULL == wlc_hw->di[3]);
665 }
666/* Cleaner to leave this as if with AP defined */
667
668 if (dma_attach_err) {
669 WL_ERROR(("wl%d: wlc_attach: dma_attach failed\n",
670 unit));
0965ae88 671 return false;
a9533e7e
HP		 672 }
673
674 /* get pointer to dma engine tx flow control variable */
675 for (i = 0; i < NFIFO; i++)
676 if (wlc_hw->di[i])
677 wlc_hw->txavail[i] =
678 (uint *) dma_getvar(wlc_hw->di[i],
679 "&txavail");
680 }
681
682 /* initial ucode host flags */
683 wlc_mhfdef(wlc, wlc_hw->band->mhfs, pio_mhf2);
684
0f0881b0 685 return true;
a9533e7e
HP		 686}
687
0d2f0724 688static void wlc_bmac_detach_dmapio(wlc_hw_info_t *wlc_hw)
a2627bc0 689{
a9533e7e
HP		 690 uint j;
691
692 for (j = 0; j < NFIFO; j++) {
693 if (wlc_hw->di[j]) {
694 dma_detach(wlc_hw->di[j]);
695 wlc_hw->di[j] = NULL;
696 }
697 }
698}
699
700/* low level attach
701 * run backplane attach, init nvram
702 * run phy attach
703 * initialize software state for each core and band
704 * put the whole chip in reset(driver down state), no clock
705 */
0d2f0724
GKH		 706int wlc_bmac_attach(wlc_info_t *wlc, u16 vendor, u16 device, uint unit,
707 bool piomode, osl_t *osh, void *regsva, uint bustype,
708 void *btparam)
709{
a9533e7e
HP		 710 wlc_hw_info_t *wlc_hw;
711 d11regs_t *regs;
712 char *macaddr = NULL;
713 char *vars;
714 uint err = 0;
715 uint j;
0965ae88 716 bool wme = false;
a9533e7e
HP		 717 shared_phy_params_t sha_params;
718
719 WL_TRACE(("wl%d: wlc_bmac_attach: vendor 0x%x device 0x%x\n", unit,
720 vendor, device));
721
722 ASSERT(sizeof(wlc_d11rxhdr_t) <= WL_HWRXOFF);
723
0f0881b0 724 wme = true;
a9533e7e
HP		 725
726 wlc_hw = wlc->hw;
727 wlc_hw->wlc = wlc;
728 wlc_hw->unit = unit;
729 wlc_hw->osh = osh;
730 wlc_hw->band = wlc_hw->bandstate[0];
731 wlc_hw->_piomode = piomode;
732
733 /* populate wlc_hw_info_t with default values */
734 wlc_bmac_info_init(wlc_hw);
735
736 /*
737 * Do the hardware portion of the attach.
738 * Also initialize software state that depends on the particular hardware
739 * we are running.
740 */
741 wlc_hw->sih = si_attach((uint) device, osh, regsva, bustype, btparam,
742 &wlc_hw->vars, &wlc_hw->vars_size);
743 if (wlc_hw->sih == NULL) {
744 WL_ERROR(("wl%d: wlc_bmac_attach: si_attach failed\n", unit));
745 err = 11;
746 goto fail;
747 }
748 vars = wlc_hw->vars;
749
750 /*
751 * Get vendid/devid nvram overwrites, which could be different
752 * than those the BIOS recognizes for devices on PCMCIA_BUS,
753 * SDIO_BUS, and SROMless devices on PCI_BUS.
754 */
755#ifdef BCMBUSTYPE
756 bustype = BCMBUSTYPE;
757#endif
758 if (bustype != SI_BUS) {
759 char *var;
760
ca8c1e59
JC		 761 var = getvar(vars, "vendid");
762 if (var) {
7d4df48e 763 vendor = (u16) simple_strtoul(var, NULL, 0);
a9533e7e
HP		 764 WL_ERROR(("Overriding vendor id = 0x%x\n", vendor));
765 }
ca8c1e59
JC		 766 var = getvar(vars, "devid");
767 if (var) {
7d4df48e 768 u16 devid = (u16) simple_strtoul(var, NULL, 0);
a9533e7e
HP		 769 if (devid != 0xffff) {
770 device = devid;
771 WL_ERROR(("Overriding device id = 0x%x\n",
772 device));
773 }
774 }
775
776 /* verify again the device is supported */
777 if (!wlc_chipmatch(vendor, device)) {
778 WL_ERROR(("wl%d: wlc_bmac_attach: Unsupported vendor/device (0x%x/0x%x)\n", unit, vendor, device));
779 err = 12;
780 goto fail;
781 }
782 }
783
784 wlc_hw->vendorid = vendor;
785 wlc_hw->deviceid = device;
786
787 /* set bar0 window to point at D11 core */
788 wlc_hw->regs = (d11regs_t *) si_setcore(wlc_hw->sih, D11_CORE_ID, 0);
789 wlc_hw->corerev = si_corerev(wlc_hw->sih);
790
791 regs = wlc_hw->regs;
792
793 wlc->regs = wlc_hw->regs;
794
795 /* validate chip, chiprev and corerev */
796 if (!wlc_isgoodchip(wlc_hw)) {
797 err = 13;
798 goto fail;
799 }
800
801 /* initialize power control registers */
802 si_clkctl_init(wlc_hw->sih);
803
804 /* request fastclock and force fastclock for the rest of attach
805 * bring the d11 core out of reset.
0965ae88 806 * For PMU chips, the first wlc_clkctl_clk is no-op since core-clk is still false;
a9533e7e
HP		 807 * But it will be called again inside wlc_corereset, after d11 is out of reset.
808 */
809 wlc_clkctl_clk(wlc_hw, CLK_FAST);
810 wlc_bmac_corereset(wlc_hw, WLC_USE_COREFLAGS);
811
812 if (!wlc_bmac_validate_chip_access(wlc_hw)) {
813 WL_ERROR(("wl%d: wlc_bmac_attach: validate_chip_access failed\n", unit));
814 err = 14;
815 goto fail;
816 }
817
818 /* get the board rev, used just below */
819 j = getintvar(vars, "boardrev");
820 /* promote srom boardrev of 0xFF to 1 */
821 if (j == BOARDREV_PROMOTABLE)
822 j = BOARDREV_PROMOTED;
7d4df48e 823 wlc_hw->boardrev = (u16) j;
a9533e7e
HP		 824 if (!wlc_validboardtype(wlc_hw)) {
825 WL_ERROR(("wl%d: wlc_bmac_attach: Unsupported Broadcom board type (0x%x)" " or revision level (0x%x)\n", unit, wlc_hw->sih->boardtype, wlc_hw->boardrev));
826 err = 15;
827 goto fail;
828 }
41feb5ed 829 wlc_hw->sromrev = (u8) getintvar(vars, "sromrev");
66cbd3ab
GKH		 830 wlc_hw->boardflags = (u32) getintvar(vars, "boardflags");
831 wlc_hw->boardflags2 = (u32) getintvar(vars, "boardflags2");
a9533e7e
HP		 832
833 if (D11REV_LE(wlc_hw->corerev, 4)
834 || (wlc_hw->boardflags & BFL_NOPLLDOWN))
0f0881b0 835 wlc_bmac_pllreq(wlc_hw, true, WLC_PLLREQ_SHARED);
a9533e7e
HP		 836
837 if ((BUSTYPE(wlc_hw->sih->bustype) == PCI_BUS)
838 && (si_pci_war16165(wlc_hw->sih)))
0f0881b0 839 wlc->war16165 = true;
a9533e7e
HP		 840
841 /* check device id(srom, nvram etc.) to set bands */
842 if (wlc_hw->deviceid == BCM43224_D11N_ID) {
843 /* Dualband boards */
844 wlc_hw->_nbands = 2;
845 } else
846 wlc_hw->_nbands = 1;
847
848 if ((CHIPID(wlc_hw->sih->chip) == BCM43225_CHIP_ID))
849 wlc_hw->_nbands = 1;
850
851 /* BMAC_NOTE: remove init of pub values when wlc_attach() unconditionally does the
852 * init of these values
853 */
854 wlc->vendorid = wlc_hw->vendorid;
855 wlc->deviceid = wlc_hw->deviceid;
856 wlc->pub->sih = wlc_hw->sih;
857 wlc->pub->corerev = wlc_hw->corerev;
858 wlc->pub->sromrev = wlc_hw->sromrev;
859 wlc->pub->boardrev = wlc_hw->boardrev;
860 wlc->pub->boardflags = wlc_hw->boardflags;
861 wlc->pub->boardflags2 = wlc_hw->boardflags2;
862 wlc->pub->_nbands = wlc_hw->_nbands;
863
864 wlc_hw->physhim = wlc_phy_shim_attach(wlc_hw, wlc->wl, wlc);
865
866 if (wlc_hw->physhim == NULL) {
867 WL_ERROR(("wl%d: wlc_bmac_attach: wlc_phy_shim_attach failed\n",
868 unit));
869 err = 25;
870 goto fail;
871 }
872
873 /* pass all the parameters to wlc_phy_shared_attach in one struct */
874 sha_params.osh = osh;
875 sha_params.sih = wlc_hw->sih;
876 sha_params.physhim = wlc_hw->physhim;
877 sha_params.unit = unit;
878 sha_params.corerev = wlc_hw->corerev;
879 sha_params.vars = vars;
880 sha_params.vid = wlc_hw->vendorid;
881 sha_params.did = wlc_hw->deviceid;
882 sha_params.chip = wlc_hw->sih->chip;
883 sha_params.chiprev = wlc_hw->sih->chiprev;
884 sha_params.chippkg = wlc_hw->sih->chippkg;
885 sha_params.sromrev = wlc_hw->sromrev;
886 sha_params.boardtype = wlc_hw->sih->boardtype;
887 sha_params.boardrev = wlc_hw->boardrev;
888 sha_params.boardvendor = wlc_hw->sih->boardvendor;
889 sha_params.boardflags = wlc_hw->boardflags;
890 sha_params.boardflags2 = wlc_hw->boardflags2;
891 sha_params.bustype = wlc_hw->sih->bustype;
892 sha_params.buscorerev = wlc_hw->sih->buscorerev;
893
894 /* alloc and save pointer to shared phy state area */
895 wlc_hw->phy_sh = wlc_phy_shared_attach(&sha_params);
896 if (!wlc_hw->phy_sh) {
897 err = 16;
898 goto fail;
899 }
900
901 /* initialize software state for each core and band */
902 for (j = 0; j < NBANDS_HW(wlc_hw); j++) {
903 /*
904 * band0 is always 2.4Ghz
905 * band1, if present, is 5Ghz
906 */
907
908 /* So if this is a single band 11a card, use band 1 */
909 if (IS_SINGLEBAND_5G(wlc_hw->deviceid))
910 j = BAND_5G_INDEX;
911
912 wlc_setxband(wlc_hw, j);
913
914 wlc_hw->band->bandunit = j;
915 wlc_hw->band->bandtype = j ? WLC_BAND_5G : WLC_BAND_2G;
916 wlc->band->bandunit = j;
917 wlc->band->bandtype = j ? WLC_BAND_5G : WLC_BAND_2G;
918 wlc->core->coreidx = si_coreidx(wlc_hw->sih);
919
920 if (D11REV_GE(wlc_hw->corerev, 13)) {
921 wlc_hw->machwcap = R_REG(wlc_hw->osh, &regs->machwcap);
922 wlc_hw->machwcap_backup = wlc_hw->machwcap;
923 }
924
925 /* init tx fifo size */
926 ASSERT((wlc_hw->corerev - XMTFIFOTBL_STARTREV) <
8d3d6a69 927 ARRAY_SIZE(xmtfifo_sz));
a9533e7e
HP		 928 wlc_hw->xmtfifo_sz =
929 xmtfifo_sz[(wlc_hw->corerev - XMTFIFOTBL_STARTREV)];
930
931 /* Get a phy for this band */
ca8c1e59 932 wlc_hw->band->pi = wlc_phy_attach(wlc_hw->phy_sh,
e88cf8eb 933 (void *)regs, wlc_hw->band->bandtype, vars);
ca8c1e59 934 if (wlc_hw->band->pi == NULL) {
a9533e7e
HP		 935 WL_ERROR(("wl%d: wlc_bmac_attach: wlc_phy_attach failed\n", unit));
936 err = 17;
937 goto fail;
938 }
939
940 wlc_phy_machwcap_set(wlc_hw->band->pi, wlc_hw->machwcap);
941
942 wlc_phy_get_phyversion(wlc_hw->band->pi, &wlc_hw->band->phytype,
943 &wlc_hw->band->phyrev,
944 &wlc_hw->band->radioid,
945 &wlc_hw->band->radiorev);
946 wlc_hw->band->abgphy_encore =
947 wlc_phy_get_encore(wlc_hw->band->pi);
948 wlc->band->abgphy_encore = wlc_phy_get_encore(wlc_hw->band->pi);
949 wlc_hw->band->core_flags =
950 wlc_phy_get_coreflags(wlc_hw->band->pi);
951
952 /* verify good phy_type & supported phy revision */
953 if (WLCISNPHY(wlc_hw->band)) {
954 if (NCONF_HAS(wlc_hw->band->phyrev))
955 goto good_phy;
956 else
957 goto bad_phy;
958 } else if (WLCISLCNPHY(wlc_hw->band)) {
959 if (LCNCONF_HAS(wlc_hw->band->phyrev))
960 goto good_phy;
961 else
962 goto bad_phy;
963 } else {
964 bad_phy:
965 WL_ERROR(("wl%d: wlc_bmac_attach: unsupported phy type/rev (%d/%d)\n", unit, wlc_hw->band->phytype, wlc_hw->band->phyrev));
966 err = 18;
967 goto fail;
968 }
969
970 good_phy:
971 /* BMAC_NOTE: wlc->band->pi should not be set below and should be done in the
972 * high level attach. However we can not make that change until all low level access
973 * is changed to wlc_hw->band->pi. Instead do the wlc->band->pi init below, keeping
974 * wlc_hw->band->pi as well for incremental update of low level fns, and cut over
975 * low only init when all fns updated.
976 */
977 wlc->band->pi = wlc_hw->band->pi;
978 wlc->band->phytype = wlc_hw->band->phytype;
979 wlc->band->phyrev = wlc_hw->band->phyrev;
980 wlc->band->radioid = wlc_hw->band->radioid;
981 wlc->band->radiorev = wlc_hw->band->radiorev;
982
983 /* default contention windows size limits */
984 wlc_hw->band->CWmin = APHY_CWMIN;
985 wlc_hw->band->CWmax = PHY_CWMAX;
986
987 if (!wlc_bmac_attach_dmapio(wlc, j, wme)) {
988 err = 19;
989 goto fail;
990 }
991 }
992
993 /* disable core to match driver "down" state */
994 wlc_coredisable(wlc_hw);
995
996 /* Match driver "down" state */
997 if (BUSTYPE(wlc_hw->sih->bustype) == PCI_BUS)
998 si_pci_down(wlc_hw->sih);
999
1000 /* register sb interrupt callback functions */
1001 si_register_intr_callback(wlc_hw->sih, (void *)wlc_wlintrsoff,
1002 (void *)wlc_wlintrsrestore, NULL, wlc);
1003
1004 /* turn off pll and xtal to match driver "down" state */
1005 wlc_bmac_xtal(wlc_hw, OFF);
1006
1007 /* *********************************************************************
1008 * The hardware is in the DOWN state at this point. D11 core
1009 * or cores are in reset with clocks off, and the board PLLs
1010 * are off if possible.
1011 *
0965ae88 1012 * Beyond this point, wlc->sbclk == false and chip registers
a9533e7e
HP		 1013 * should not be touched.
1014 *********************************************************************
1015 */
1016
1017 /* init etheraddr state variables */
ca8c1e59
JC		 1018 macaddr = wlc_get_macaddr(wlc_hw);
1019 if (macaddr == NULL) {
a9533e7e
HP		 1020 WL_ERROR(("wl%d: wlc_bmac_attach: macaddr not found\n", unit));
1021 err = 21;
1022 goto fail;
1023 }
1024 bcm_ether_atoe(macaddr, &wlc_hw->etheraddr);
1025 if (ETHER_ISBCAST((char *)&wlc_hw->etheraddr) ||
1026 ETHER_ISNULLADDR((char *)&wlc_hw->etheraddr)) {
1027 WL_ERROR(("wl%d: wlc_bmac_attach: bad macaddr %s\n", unit,
1028 macaddr));
1029 err = 22;
1030 goto fail;
1031 }
1032
1033 WL_ERROR(("%s:: deviceid 0x%x nbands %d board 0x%x macaddr: %s\n",
1034 __func__, wlc_hw->deviceid, wlc_hw->_nbands,
1035 wlc_hw->sih->boardtype, macaddr));
1036
1037 return err;
1038
1039 fail:
1040 WL_ERROR(("wl%d: wlc_bmac_attach: failed with err %d\n", unit, err));
1041 return err;
1042}
1043
1044/*
1045 * Initialize wlc_info default values ...
1046 * may get overrides later in this function
1047 * BMAC_NOTES, move low out and resolve the dangling ones
1048 */
0d2f0724 1049void wlc_bmac_info_init(wlc_hw_info_t *wlc_hw)
a2627bc0 1050{
a9533e7e
HP		 1051 wlc_info_t *wlc = wlc_hw->wlc;
1052
1053 /* set default sw macintmask value */
1054 wlc->defmacintmask = DEF_MACINTMASK;
1055
1056 /* various 802.11g modes */
0965ae88 1057 wlc_hw->shortslot = false;
a9533e7e
HP		 1058
1059 wlc_hw->SFBL = RETRY_SHORT_FB;
1060 wlc_hw->LFBL = RETRY_LONG_FB;
1061
1062 /* default mac retry limits */
1063 wlc_hw->SRL = RETRY_SHORT_DEF;
1064 wlc_hw->LRL = RETRY_LONG_DEF;
1065 wlc_hw->chanspec = CH20MHZ_CHSPEC(1);
1066}
1067
1068/*
1069 * low level detach
1070 */
0d2f0724 1071int wlc_bmac_detach(wlc_info_t *wlc)
a2627bc0 1072{
a9533e7e
HP		 1073 uint i;
1074 wlc_hwband_t *band;
1075 wlc_hw_info_t *wlc_hw = wlc->hw;
1076 int callbacks;
1077
1078 callbacks = 0;
1079
1080 if (wlc_hw->sih) {
1081 /* detach interrupt sync mechanism since interrupt is disabled and per-port
1082 * interrupt object may has been freed. this must be done before sb core switch
1083 */
1084 si_deregister_intr_callback(wlc_hw->sih);
1085
1086 if (BUSTYPE(wlc_hw->sih->bustype) == PCI_BUS)
1087 si_pci_sleep(wlc_hw->sih);
1088 }
1089
1090 wlc_bmac_detach_dmapio(wlc_hw);
1091
1092 band = wlc_hw->band;
1093 for (i = 0; i < NBANDS_HW(wlc_hw); i++) {
1094 if (band->pi) {
1095 /* Detach this band's phy */
1096 wlc_phy_detach(band->pi);
1097 band->pi = NULL;
1098 }
1099 band = wlc_hw->bandstate[OTHERBANDUNIT(wlc)];
1100 }
1101
1102 /* Free shared phy state */
1103 wlc_phy_shared_detach(wlc_hw->phy_sh);
1104
1105 wlc_phy_shim_detach(wlc_hw->physhim);
1106
1107 /* free vars */
1108 if (wlc_hw->vars) {
182acb3c 1109 kfree(wlc_hw->vars);
a9533e7e
HP		 1110 wlc_hw->vars = NULL;
1111 }
1112
1113 if (wlc_hw->sih) {
1114 si_detach(wlc_hw->sih);
1115 wlc_hw->sih = NULL;
1116 }
1117
1118 return callbacks;
1119
1120}
1121
b4f790ee 1122void wlc_bmac_reset(wlc_hw_info_t *wlc_hw)
a2627bc0 1123{
a9533e7e
HP		 1124 WL_TRACE(("wl%d: wlc_bmac_reset\n", wlc_hw->unit));
1125
1126 WLCNTINCR(wlc_hw->wlc->pub->_cnt->reset);
1127
1128 /* reset the core */
1129 if (!DEVICEREMOVED(wlc_hw->wlc))
1130 wlc_bmac_corereset(wlc_hw, WLC_USE_COREFLAGS);
1131
1132 /* purge the dma rings */
1133 wlc_flushqueues(wlc_hw->wlc);
1134
1135 wlc_reset_bmac_done(wlc_hw->wlc);
1136}
1137
1138void
b4f790ee 1139wlc_bmac_init(wlc_hw_info_t *wlc_hw, chanspec_t chanspec,
a9533e7e 1140 bool mute) {
66cbd3ab 1141 u32 macintmask;
a9533e7e
HP		 1142 bool fastclk;
1143 wlc_info_t *wlc = wlc_hw->wlc;
1144
1145 WL_TRACE(("wl%d: wlc_bmac_init\n", wlc_hw->unit));
1146
1147 /* request FAST clock if not on */
ca8c1e59
JC		 1148 fastclk = wlc_hw->forcefastclk;
1149 if (!fastclk)
a9533e7e
HP		 1150 wlc_clkctl_clk(wlc_hw, CLK_FAST);
1151
1152 /* disable interrupts */
1153 macintmask = wl_intrsoff(wlc->wl);
1154
1155 /* set up the specified band and chanspec */
1156 wlc_setxband(wlc_hw, CHSPEC_WLCBANDUNIT(chanspec));
1157 wlc_phy_chanspec_radio_set(wlc_hw->band->pi, chanspec);
1158
1159 /* do one-time phy inits and calibration */
1160 wlc_phy_cal_init(wlc_hw->band->pi);
1161
1162 /* core-specific initialization */
1163 wlc_coreinit(wlc);
1164
1165 /* suspend the tx fifos and mute the phy for preism cac time */
1166 if (mute)
1167 wlc_bmac_mute(wlc_hw, ON, PHY_MUTE_FOR_PREISM);
1168
1169 /* band-specific inits */
1170 wlc_bmac_bsinit(wlc, chanspec);
1171
1172 /* restore macintmask */
1173 wl_intrsrestore(wlc->wl, macintmask);
1174
1175 /* seed wake_override with WLC_WAKE_OVERRIDE_MACSUSPEND since the mac is suspended
1176 * and wlc_enable_mac() will clear this override bit.
1177 */
1178 mboolset(wlc_hw->wake_override, WLC_WAKE_OVERRIDE_MACSUSPEND);
1179
1180 /*
1181 * initialize mac_suspend_depth to 1 to match ucode initial suspended state
1182 */
1183 wlc_hw->mac_suspend_depth = 1;
1184
1185 /* restore the clk */
1186 if (!fastclk)
1187 wlc_clkctl_clk(wlc_hw, CLK_DYNAMIC);
1188}
1189
b4f790ee 1190int wlc_bmac_up_prep(wlc_hw_info_t *wlc_hw)
a2627bc0 1191{
a9533e7e
HP		 1192 uint coremask;
1193
1194 WL_TRACE(("wl%d: %s:\n", wlc_hw->unit, __func__));
1195
1196 ASSERT(wlc_hw->wlc->pub->hw_up && wlc_hw->wlc->macintmask == 0);
1197
1198 /*
1199 * Enable pll and xtal, initialize the power control registers,
1200 * and force fastclock for the remainder of wlc_up().
1201 */
1202 wlc_bmac_xtal(wlc_hw, ON);
1203 si_clkctl_init(wlc_hw->sih);
1204 wlc_clkctl_clk(wlc_hw, CLK_FAST);
1205
1206 /*
1207 * Configure pci/pcmcia here instead of in wlc_attach()
1208 * to allow mfg hotswap: down, hotswap (chip power cycle), up.
1209 */
1210 coremask = (1 << wlc_hw->wlc->core->coreidx);
1211
1212 if (BUSTYPE(wlc_hw->sih->bustype) == PCI_BUS)
1213 si_pci_setup(wlc_hw->sih, coremask);
1214
1215 ASSERT(si_coreid(wlc_hw->sih) == D11_CORE_ID);
1216
1217 /*
1218 * Need to read the hwradio status here to cover the case where the system
1219 * is loaded with the hw radio disabled. We do not want to bring the driver up in this case.
1220 */
1221 if (wlc_bmac_radio_read_hwdisabled(wlc_hw)) {
1222 /* put SB PCI in down state again */
1223 if (BUSTYPE(wlc_hw->sih->bustype) == PCI_BUS)
1224 si_pci_down(wlc_hw->sih);
1225 wlc_bmac_xtal(wlc_hw, OFF);
1226 return BCME_RADIOOFF;
1227 }
1228
1229 if (BUSTYPE(wlc_hw->sih->bustype) == PCI_BUS)
1230 si_pci_up(wlc_hw->sih);
1231
1232 /* reset the d11 core */
1233 wlc_bmac_corereset(wlc_hw, WLC_USE_COREFLAGS);
1234
1235 return 0;
1236}
1237
b4f790ee 1238int wlc_bmac_up_finish(wlc_hw_info_t *wlc_hw)
a2627bc0 1239{
a9533e7e
HP		 1240 WL_TRACE(("wl%d: %s:\n", wlc_hw->unit, __func__));
1241
0f0881b0
GKH		 1242 wlc_hw->up = true;
1243 wlc_phy_hw_state_upd(wlc_hw->band->pi, true);
a9533e7e
HP		 1244
1245 /* FULLY enable dynamic power control and d11 core interrupt */
1246 wlc_clkctl_clk(wlc_hw, CLK_DYNAMIC);
1247 ASSERT(wlc_hw->wlc->macintmask == 0);
1248 wl_intrson(wlc_hw->wlc->wl);
1249 return 0;
1250}
1251
9927fc2e 1252int wlc_bmac_down_prep(wlc_hw_info_t *wlc_hw)
a2627bc0 1253{
a9533e7e
HP		 1254 bool dev_gone;
1255 uint callbacks = 0;
1256
1257 WL_TRACE(("wl%d: %s:\n", wlc_hw->unit, __func__));
1258
1259 if (!wlc_hw->up)
1260 return callbacks;
1261
1262 dev_gone = DEVICEREMOVED(wlc_hw->wlc);
1263
1264 /* disable interrupts */
1265 if (dev_gone)
1266 wlc_hw->wlc->macintmask = 0;
1267 else {
1268 /* now disable interrupts */
1269 wl_intrsoff(wlc_hw->wlc->wl);
1270
1271 /* ensure we're running on the pll clock again */
1272 wlc_clkctl_clk(wlc_hw, CLK_FAST);
1273 }
1274 /* down phy at the last of this stage */
1275 callbacks += wlc_phy_down(wlc_hw->band->pi);
1276
1277 return callbacks;
1278}
1279
9927fc2e 1280int wlc_bmac_down_finish(wlc_hw_info_t *wlc_hw)
a2627bc0 1281{
a9533e7e
HP		 1282 uint callbacks = 0;
1283 bool dev_gone;
1284
1285 WL_TRACE(("wl%d: %s:\n", wlc_hw->unit, __func__));
1286
1287 if (!wlc_hw->up)
1288 return callbacks;
1289
0965ae88
GKH		 1290 wlc_hw->up = false;
1291 wlc_phy_hw_state_upd(wlc_hw->band->pi, false);
a9533e7e
HP		 1292
1293 dev_gone = DEVICEREMOVED(wlc_hw->wlc);
1294
1295 if (dev_gone) {
0965ae88
GKH		 1296 wlc_hw->sbclk = false;
1297 wlc_hw->clk = false;
1298 wlc_phy_hw_clk_state_upd(wlc_hw->band->pi, false);
a9533e7e
HP		 1299
1300 /* reclaim any posted packets */
1301 wlc_flushqueues(wlc_hw->wlc);
1302 } else {
1303
1304 /* Reset and disable the core */
1305 if (si_iscoreup(wlc_hw->sih)) {
1306 if (R_REG(wlc_hw->osh, &wlc_hw->regs->maccontrol) &
1307 MCTL_EN_MAC)
1308 wlc_suspend_mac_and_wait(wlc_hw->wlc);
1309 callbacks += wl_reset(wlc_hw->wlc->wl);
1310 wlc_coredisable(wlc_hw);
1311 }
1312
1313 /* turn off primary xtal and pll */
1314 if (!wlc_hw->noreset) {
1315 if (BUSTYPE(wlc_hw->sih->bustype) == PCI_BUS)
1316 si_pci_down(wlc_hw->sih);
1317 wlc_bmac_xtal(wlc_hw, OFF);
1318 }
1319 }
1320
1321 return callbacks;
1322}
1323
7cc4a4c0 1324void wlc_bmac_wait_for_wake(wlc_hw_info_t *wlc_hw)
a9533e7e
HP		 1325{
1326 if (D11REV_IS(wlc_hw->corerev, 4)) /* no slowclock */
7383141b 1327 udelay(5);
a9533e7e
HP		 1328 else {
1329 /* delay before first read of ucode state */
7383141b 1330 udelay(40);
a9533e7e
HP		 1331
1332 /* wait until ucode is no longer asleep */
1333 SPINWAIT((wlc_bmac_read_shm(wlc_hw, M_UCODE_DBGST) ==
1334 DBGST_ASLEEP), wlc_hw->wlc->fastpwrup_dly);
1335 }
1336
1337 ASSERT(wlc_bmac_read_shm(wlc_hw, M_UCODE_DBGST) != DBGST_ASLEEP);
1338}
1339
7cc4a4c0 1340void wlc_bmac_hw_etheraddr(wlc_hw_info_t *wlc_hw, struct ether_addr *ea)
a9533e7e
HP		 1341{
1342 bcopy(&wlc_hw->etheraddr, ea, ETHER_ADDR_LEN);
1343}
1344
7cc4a4c0 1345void wlc_bmac_set_hw_etheraddr(wlc_hw_info_t *wlc_hw, struct ether_addr *ea)
a9533e7e
HP		 1346{
1347 bcopy(ea, &wlc_hw->etheraddr, ETHER_ADDR_LEN);
1348}
1349
7cc4a4c0 1350int wlc_bmac_bandtype(wlc_hw_info_t *wlc_hw)
a9533e7e 1351{
90ea2296 1352 return wlc_hw->band->bandtype;
a9533e7e
HP		 1353}
1354
7cc4a4c0 1355void *wlc_cur_phy(wlc_info_t *wlc)
a9533e7e
HP		 1356{
1357 wlc_hw_info_t *wlc_hw = wlc->hw;
90ea2296 1358 return (void *)wlc_hw->band->pi;
a9533e7e
HP		 1359}
1360
1361/* control chip clock to save power, enable dynamic clock or force fast clock */
7cc4a4c0 1362static void wlc_clkctl_clk(wlc_hw_info_t *wlc_hw, uint mode)
a9533e7e
HP		 1363{
1364 if (PMUCTL_ENAB(wlc_hw->sih)) {
1365 /* new chips with PMU, CCS_FORCEHT will distribute the HT clock on backplane,
1366 * but mac core will still run on ALP(not HT) when it enters powersave mode,
1367 * which means the FCA bit may not be set.
1368 * should wakeup mac if driver wants it to run on HT.
1369 */
1370
1371 if (wlc_hw->clk) {
1372 if (mode == CLK_FAST) {
1373 OR_REG(wlc_hw->osh, &wlc_hw->regs->clk_ctl_st,
1374 CCS_FORCEHT);
1375
7383141b 1376 udelay(64);
a9533e7e
HP		 1377
1378 SPINWAIT(((R_REG
1379 (wlc_hw->osh,
1380 &wlc_hw->regs->
1381 clk_ctl_st) & CCS_HTAVAIL) == 0),
1382 PMU_MAX_TRANSITION_DLY);
1383 ASSERT(R_REG
1384 (wlc_hw->osh,
1385 &wlc_hw->regs->
1386 clk_ctl_st) & CCS_HTAVAIL);
1387 } else {
1388 if ((wlc_hw->sih->pmurev == 0) &&
1389 (R_REG
1390 (wlc_hw->osh,
1391 &wlc_hw->regs->
1392 clk_ctl_st) & (CCS_FORCEHT | CCS_HTAREQ)))
1393 SPINWAIT(((R_REG
1394 (wlc_hw->osh,
1395 &wlc_hw->regs->
1396 clk_ctl_st) & CCS_HTAVAIL)
1397 == 0),
1398 PMU_MAX_TRANSITION_DLY);
1399 AND_REG(wlc_hw->osh, &wlc_hw->regs->clk_ctl_st,
1400 ~CCS_FORCEHT);
1401 }
1402 }
1403 wlc_hw->forcefastclk = (mode == CLK_FAST);
1404 } else {
1405 bool wakeup_ucode;
1406
1407 /* old chips w/o PMU, force HT through cc,
1408 * then use FCA to verify mac is running fast clock
1409 */
1410
1411 wakeup_ucode = D11REV_LT(wlc_hw->corerev, 9);
1412
1413 if (wlc_hw->up && wakeup_ucode)
1414 wlc_ucode_wake_override_set(wlc_hw,
1415 WLC_WAKE_OVERRIDE_CLKCTL);
1416
1417 wlc_hw->forcefastclk = si_clkctl_cc(wlc_hw->sih, mode);
1418
1419 if (D11REV_LT(wlc_hw->corerev, 11)) {
1420 /* ucode WAR for old chips */
1421 if (wlc_hw->forcefastclk)
1422 wlc_bmac_mhf(wlc_hw, MHF1, MHF1_FORCEFASTCLK,
1423 MHF1_FORCEFASTCLK, WLC_BAND_ALL);
1424 else
1425 wlc_bmac_mhf(wlc_hw, MHF1, MHF1_FORCEFASTCLK, 0,
1426 WLC_BAND_ALL);
1427 }
1428
1429 /* check fast clock is available (if core is not in reset) */
1430 if (D11REV_GT(wlc_hw->corerev, 4) && wlc_hw->forcefastclk
1431 && wlc_hw->clk)
1432 ASSERT(si_core_sflags(wlc_hw->sih, 0, 0) & SISF_FCLKA);
1433
1434 /* keep the ucode wake bit on if forcefastclk is on
1435 * since we do not want ucode to put us back to slow clock
1436 * when it dozes for PM mode.
1437 * Code below matches the wake override bit with current forcefastclk state
1438 * Only setting bit in wake_override instead of waking ucode immediately
1439 * since old code (wlc.c 1.4499) had this behavior. Older code set
1440 * wlc->forcefastclk but only had the wake happen if the wakup_ucode work
1441 * (protected by an up check) was executed just below.
1442 */
1443 if (wlc_hw->forcefastclk)
1444 mboolset(wlc_hw->wake_override,
1445 WLC_WAKE_OVERRIDE_FORCEFAST);
1446 else
1447 mboolclr(wlc_hw->wake_override,
1448 WLC_WAKE_OVERRIDE_FORCEFAST);
1449
1450 /* ok to clear the wakeup now */
1451 if (wlc_hw->up && wakeup_ucode)
1452 wlc_ucode_wake_override_clear(wlc_hw,
1453 WLC_WAKE_OVERRIDE_CLKCTL);
1454 }
1455}
1456
1457/* set initial host flags value */
1458static void
b4f790ee 1459wlc_mhfdef(wlc_info_t *wlc, u16 *mhfs, u16 mhf2_init)
a2627bc0 1460{
a9533e7e
HP		 1461 wlc_hw_info_t *wlc_hw = wlc->hw;
1462
7d4df48e 1463 bzero(mhfs, sizeof(u16) * MHFMAX);
a9533e7e
HP		 1464
1465 mhfs[MHF2] |= mhf2_init;
1466
1467 /* prohibit use of slowclock on multifunction boards */
1468 if (wlc_hw->boardflags & BFL_NOPLLDOWN)
1469 mhfs[MHF1] |= MHF1_FORCEFASTCLK;
1470
1471 if (WLCISNPHY(wlc_hw->band) && NREV_LT(wlc_hw->band->phyrev, 2)) {
1472 mhfs[MHF2] |= MHF2_NPHY40MHZ_WAR;
1473 mhfs[MHF1] |= MHF1_IQSWAP_WAR;
1474 }
1475}
1476
1477/* set or clear ucode host flag bits
1478 * it has an optimization for no-change write
1479 * it only writes through shared memory when the core has clock;
1480 * pre-CLK changes should use wlc_write_mhf to get around the optimization
1481 *
1482 *
1483 * bands values are: WLC_BAND_AUTO <--- Current band only
1484 * WLC_BAND_5G <--- 5G band only
1485 * WLC_BAND_2G <--- 2G band only
1486 * WLC_BAND_ALL <--- All bands
1487 */
1488void
7d4df48e 1489wlc_bmac_mhf(wlc_hw_info_t *wlc_hw, u8 idx, u16 mask, u16 val,
a9533e7e
HP		 1490 int bands)
1491{
7d4df48e
GKH		 1492 u16 save;
1493 u16 addr[MHFMAX] = {
e5c4536f 1494 M_HOST_FLAGS1, M_HOST_FLAGS2, M_HOST_FLAGS3, M_HOST_FLAGS4,
a9533e7e
HP		 1495 M_HOST_FLAGS5
1496 };
1497 wlc_hwband_t *band;
1498
1499 ASSERT((val & ~mask) == 0);
1500 ASSERT(idx < MHFMAX);
8d3d6a69 1501 ASSERT(ARRAY_SIZE(addr) == MHFMAX);
a9533e7e
HP		 1502
1503 switch (bands) {
1504 /* Current band only or all bands,
1505 * then set the band to current band
1506 */
1507 case WLC_BAND_AUTO:
1508 case WLC_BAND_ALL:
1509 band = wlc_hw->band;
1510 break;
1511 case WLC_BAND_5G:
1512 band = wlc_hw->bandstate[BAND_5G_INDEX];
1513 break;
1514 case WLC_BAND_2G:
1515 band = wlc_hw->bandstate[BAND_2G_INDEX];
1516 break;
1517 default:
1518 ASSERT(0);
1519 band = NULL;
1520 }
1521
1522 if (band) {
1523 save = band->mhfs[idx];
1524 band->mhfs[idx] = (band->mhfs[idx] & ~mask) | val;
1525
1526 /* optimization: only write through if changed, and
1527 * changed band is the current band
1528 */
1529 if (wlc_hw->clk && (band->mhfs[idx] != save)
1530 && (band == wlc_hw->band))
1531 wlc_bmac_write_shm(wlc_hw, addr[idx],
7d4df48e 1532 (u16) band->mhfs[idx]);
a9533e7e
HP		 1533 }
1534
1535 if (bands == WLC_BAND_ALL) {
1536 wlc_hw->bandstate[0]->mhfs[idx] =
1537 (wlc_hw->bandstate[0]->mhfs[idx] & ~mask) | val;
1538 wlc_hw->bandstate[1]->mhfs[idx] =
1539 (wlc_hw->bandstate[1]->mhfs[idx] & ~mask) | val;
1540 }
1541}
1542
7d4df48e 1543u16 wlc_bmac_mhf_get(wlc_hw_info_t *wlc_hw, u8 idx, int bands)
a9533e7e
HP		 1544{
1545 wlc_hwband_t *band;
1546 ASSERT(idx < MHFMAX);
1547
1548 switch (bands) {
1549 case WLC_BAND_AUTO:
1550 band = wlc_hw->band;
1551 break;
1552 case WLC_BAND_5G:
1553 band = wlc_hw->bandstate[BAND_5G_INDEX];
1554 break;
1555 case WLC_BAND_2G:
1556 band = wlc_hw->bandstate[BAND_2G_INDEX];
1557 break;
1558 default:
1559 ASSERT(0);
1560 band = NULL;
1561 }
1562
1563 if (!band)
1564 return 0;
1565
1566 return band->mhfs[idx];
1567}
1568
7d4df48e 1569static void wlc_write_mhf(wlc_hw_info_t *wlc_hw, u16 *mhfs)
a9533e7e 1570{
41feb5ed 1571 u8 idx;
7d4df48e 1572 u16 addr[] = {
e5c4536f 1573 M_HOST_FLAGS1, M_HOST_FLAGS2, M_HOST_FLAGS3, M_HOST_FLAGS4,
a9533e7e
HP		 1574 M_HOST_FLAGS5
1575 };
1576
8d3d6a69 1577 ASSERT(ARRAY_SIZE(addr) == MHFMAX);
a9533e7e
HP		 1578
1579 for (idx = 0; idx < MHFMAX; idx++) {
1580 wlc_bmac_write_shm(wlc_hw, addr[idx], mhfs[idx]);
1581 }
1582}
1583
1584/* set the maccontrol register to desired reset state and
1585 * initialize the sw cache of the register
1586 */
7cc4a4c0 1587static void wlc_mctrl_reset(wlc_hw_info_t *wlc_hw)
a9533e7e
HP		 1588{
1589 /* IHR accesses are always enabled, PSM disabled, HPS off and WAKE on */
1590 wlc_hw->maccontrol = 0;
1591 wlc_hw->suspended_fifos = 0;
1592 wlc_hw->wake_override = 0;
1593 wlc_hw->mute_override = 0;
1594 wlc_bmac_mctrl(wlc_hw, ~0, MCTL_IHR_EN | MCTL_WAKE);
1595}
1596
1597/* set or clear maccontrol bits */
66cbd3ab 1598void wlc_bmac_mctrl(wlc_hw_info_t *wlc_hw, u32 mask, u32 val)
a9533e7e 1599{
66cbd3ab
GKH		 1600 u32 maccontrol;
1601 u32 new_maccontrol;
a9533e7e
HP		 1602
1603 ASSERT((val & ~mask) == 0);
1604
1605 maccontrol = wlc_hw->maccontrol;
1606 new_maccontrol = (maccontrol & ~mask) | val;
1607
1608 /* if the new maccontrol value is the same as the old, nothing to do */
1609 if (new_maccontrol == maccontrol)
1610 return;
1611
1612 /* something changed, cache the new value */
1613 wlc_hw->maccontrol = new_maccontrol;
1614
1615 /* write the new values with overrides applied */
1616 wlc_mctrl_write(wlc_hw);
1617}
1618
1619/* write the software state of maccontrol and overrides to the maccontrol register */
7cc4a4c0 1620static void wlc_mctrl_write(wlc_hw_info_t *wlc_hw)
a9533e7e 1621{
66cbd3ab 1622 u32 maccontrol = wlc_hw->maccontrol;
a9533e7e
HP		 1623
1624 /* OR in the wake bit if overridden */
1625 if (wlc_hw->wake_override)
1626 maccontrol |= MCTL_WAKE;
1627
1628 /* set AP and INFRA bits for mute if needed */
1629 if (wlc_hw->mute_override) {
1630 maccontrol &= ~(MCTL_AP);
1631 maccontrol |= MCTL_INFRA;
1632 }
1633
1634 W_REG(wlc_hw->osh, &wlc_hw->regs->maccontrol, maccontrol);
1635}
1636
66cbd3ab 1637void wlc_ucode_wake_override_set(wlc_hw_info_t *wlc_hw, u32 override_bit)
a9533e7e
HP		 1638{
1639 ASSERT((wlc_hw->wake_override & override_bit) == 0);
1640
1641 if (wlc_hw->wake_override || (wlc_hw->maccontrol & MCTL_WAKE)) {
1642 mboolset(wlc_hw->wake_override, override_bit);
1643 return;
1644 }
1645
1646 mboolset(wlc_hw->wake_override, override_bit);
1647
1648 wlc_mctrl_write(wlc_hw);
1649 wlc_bmac_wait_for_wake(wlc_hw);
1650
1651 return;
1652}
1653
66cbd3ab 1654void wlc_ucode_wake_override_clear(wlc_hw_info_t *wlc_hw, u32 override_bit)
a9533e7e
HP		 1655{
1656 ASSERT(wlc_hw->wake_override & override_bit);
1657
1658 mboolclr(wlc_hw->wake_override, override_bit);
1659
1660 if (wlc_hw->wake_override || (wlc_hw->maccontrol & MCTL_WAKE))
1661 return;
1662
1663 wlc_mctrl_write(wlc_hw);
1664
1665 return;
1666}
1667
1668/* When driver needs ucode to stop beaconing, it has to make sure that
1669 * MCTL_AP is clear and MCTL_INFRA is set
1670 * Mode MCTL_AP MCTL_INFRA
1671 * AP 1 1
1672 * STA 0 1 <--- This will ensure no beacons
1673 * IBSS 0 0
1674 */
7cc4a4c0 1675static void wlc_ucode_mute_override_set(wlc_hw_info_t *wlc_hw)
a9533e7e
HP		 1676{
1677 wlc_hw->mute_override = 1;
1678
1679 /* if maccontrol already has AP == 0 and INFRA == 1 without this
1680 * override, then there is no change to write
1681 */
1682 if ((wlc_hw->maccontrol & (MCTL_AP | MCTL_INFRA)) == MCTL_INFRA)
1683 return;
1684
1685 wlc_mctrl_write(wlc_hw);
1686
1687 return;
1688}
1689
1690/* Clear the override on AP and INFRA bits */
7cc4a4c0 1691static void wlc_ucode_mute_override_clear(wlc_hw_info_t *wlc_hw)
a9533e7e
HP		 1692{
1693 if (wlc_hw->mute_override == 0)
1694 return;
1695
1696 wlc_hw->mute_override = 0;
1697
1698 /* if maccontrol already has AP == 0 and INFRA == 1 without this
1699 * override, then there is no change to write
1700 */
1701 if ((wlc_hw->maccontrol & (MCTL_AP | MCTL_INFRA)) == MCTL_INFRA)
1702 return;
1703
1704 wlc_mctrl_write(wlc_hw);
1705}
1706
1707/*
1708 * Write a MAC address to the rcmta structure
1709 */
1710void
7cc4a4c0 1711wlc_bmac_set_rcmta(wlc_hw_info_t *wlc_hw, int idx,
a9533e7e
HP		 1712 const struct ether_addr *addr)
1713{
1714 d11regs_t *regs = wlc_hw->regs;
e88cf8eb 1715 volatile u16 *objdata16 = (volatile u16 *)&regs->objdata;
66cbd3ab 1716 u32 mac_hm;
7d4df48e 1717 u16 mac_l;
a9533e7e
HP		 1718 osl_t *osh;
1719
1720 WL_TRACE(("wl%d: %s\n", wlc_hw->unit, __func__));
1721
1722 ASSERT(wlc_hw->corerev > 4);
1723
1724 mac_hm =
1725 (addr->octet[3] << 24) | (addr->octet[2] << 16) | (addr->
1726 octet[1] << 8) |
1727 addr->octet[0];
1728 mac_l = (addr->octet[5] << 8) | addr->octet[4];
1729
1730 osh = wlc_hw->osh;
1731
1732 W_REG(osh, &regs->objaddr, (OBJADDR_RCMTA_SEL | (idx * 2)));
1733 (void)R_REG(osh, &regs->objaddr);
1734 W_REG(osh, &regs->objdata, mac_hm);
1735 W_REG(osh, &regs->objaddr, (OBJADDR_RCMTA_SEL | ((idx * 2) + 1)));
1736 (void)R_REG(osh, &regs->objaddr);
1737 W_REG(osh, objdata16, mac_l);
1738}
1739
1740/*
1741 * Write a MAC address to the given match reg offset in the RXE match engine.
1742 */
1743void
7cc4a4c0 1744wlc_bmac_set_addrmatch(wlc_hw_info_t *wlc_hw, int match_reg_offset,
a9533e7e
HP		 1745 const struct ether_addr *addr)
1746{
1747 d11regs_t *regs;
7d4df48e
GKH		 1748 u16 mac_l;
1749 u16 mac_m;
1750 u16 mac_h;
a9533e7e
HP		 1751 osl_t *osh;
1752
1753 WL_TRACE(("wl%d: wlc_bmac_set_addrmatch\n", wlc_hw->unit));
1754
1755 ASSERT((match_reg_offset < RCM_SIZE) || (wlc_hw->corerev == 4));
1756
1757 regs = wlc_hw->regs;
1758 mac_l = addr->octet[0] | (addr->octet[1] << 8);
1759 mac_m = addr->octet[2] | (addr->octet[3] << 8);
1760 mac_h = addr->octet[4] | (addr->octet[5] << 8);
1761
1762 osh = wlc_hw->osh;
1763
1764 /* enter the MAC addr into the RXE match registers */
1765 W_REG(osh, &regs->rcm_ctl, RCM_INC_DATA | match_reg_offset);
1766 W_REG(osh, &regs->rcm_mat_data, mac_l);
1767 W_REG(osh, &regs->rcm_mat_data, mac_m);
1768 W_REG(osh, &regs->rcm_mat_data, mac_h);
1769
1770}
1771
1772void
7cc4a4c0 1773wlc_bmac_write_template_ram(wlc_hw_info_t *wlc_hw, int offset, int len,
a9533e7e
HP		 1774 void *buf)
1775{
1776 d11regs_t *regs;
66cbd3ab 1777 u32 word;
a9533e7e
HP		 1778 bool be_bit;
1779#ifdef IL_BIGENDIAN
7d4df48e 1780 volatile u16 *dptr = NULL;
a9533e7e
HP		 1781#endif /* IL_BIGENDIAN */
1782 osl_t *osh;
1783
1784 WL_TRACE(("wl%d: wlc_bmac_write_template_ram\n", wlc_hw->unit));
1785
1786 regs = wlc_hw->regs;
1787 osh = wlc_hw->osh;
1788
36c63ff6
GKH		 1789 ASSERT(IS_ALIGNED(offset, sizeof(u32)));
1790 ASSERT(IS_ALIGNED(len, sizeof(u32)));
a9533e7e
HP		 1791 ASSERT((offset & ~0xffff) == 0);
1792
1793 W_REG(osh, &regs->tplatewrptr, offset);
1794
1795 /* if MCTL_BIGEND bit set in mac control register,
1796 * the chip swaps data in fifo, as well as data in
1797 * template ram
1798 */
1799 be_bit = (R_REG(osh, &regs->maccontrol) & MCTL_BIGEND) != 0;
1800
1801 while (len > 0) {
66cbd3ab 1802 bcopy((u8 *) buf, &word, sizeof(u32));
a9533e7e
HP		 1803
1804 if (be_bit)
1805 word = hton32(word);
1806 else
1807 word = htol32(word);
1808
1809 W_REG(osh, &regs->tplatewrdata, word);
1810
66cbd3ab
GKH		 1811 buf = (u8 *) buf + sizeof(u32);
1812 len -= sizeof(u32);
a9533e7e
HP		 1813 }
1814}
1815
7d4df48e 1816void wlc_bmac_set_cwmin(wlc_hw_info_t *wlc_hw, u16 newmin)
a9533e7e
HP		 1817{
1818 osl_t *osh;
1819
1820 osh = wlc_hw->osh;
1821 wlc_hw->band->CWmin = newmin;
1822
1823 W_REG(osh, &wlc_hw->regs->objaddr, OBJADDR_SCR_SEL | S_DOT11_CWMIN);
1824 (void)R_REG(osh, &wlc_hw->regs->objaddr);
1825 W_REG(osh, &wlc_hw->regs->objdata, newmin);
1826}
1827
7d4df48e 1828void wlc_bmac_set_cwmax(wlc_hw_info_t *wlc_hw, u16 newmax)
a9533e7e
HP		 1829{
1830 osl_t *osh;
1831
1832 osh = wlc_hw->osh;
1833 wlc_hw->band->CWmax = newmax;
1834
1835 W_REG(osh, &wlc_hw->regs->objaddr, OBJADDR_SCR_SEL | S_DOT11_CWMAX);
1836 (void)R_REG(osh, &wlc_hw->regs->objaddr);
1837 W_REG(osh, &wlc_hw->regs->objdata, newmax);
1838}
1839
7d4df48e 1840void wlc_bmac_bw_set(wlc_hw_info_t *wlc_hw, u16 bw)
a9533e7e
HP		 1841{
1842 bool fastclk;
66cbd3ab 1843 u32 tmp;
a9533e7e
HP		 1844
1845 /* request FAST clock if not on */
ca8c1e59
JC		 1846 fastclk = wlc_hw->forcefastclk;
1847 if (!fastclk)
a9533e7e
HP		 1848 wlc_clkctl_clk(wlc_hw, CLK_FAST);
1849
1850 wlc_phy_bw_state_set(wlc_hw->band->pi, bw);
1851
1852 ASSERT(wlc_hw->clk);
1853 if (D11REV_LT(wlc_hw->corerev, 17))
1854 tmp = R_REG(wlc_hw->osh, &wlc_hw->regs->maccontrol);
1855
1856 wlc_bmac_phy_reset(wlc_hw);
1857 wlc_phy_init(wlc_hw->band->pi, wlc_phy_chanspec_get(wlc_hw->band->pi));
1858
1859 /* restore the clk */
1860 if (!fastclk)
1861 wlc_clkctl_clk(wlc_hw, CLK_DYNAMIC);
1862}
1863
1864static void
7cc4a4c0 1865wlc_write_hw_bcntemplate0(wlc_hw_info_t *wlc_hw, void *bcn, int len)
a9533e7e
HP		 1866{
1867 d11regs_t *regs = wlc_hw->regs;
1868
1869 wlc_bmac_write_template_ram(wlc_hw, T_BCN0_TPL_BASE, (len + 3) & ~3,
1870 bcn);
1871 /* write beacon length to SCR */
1872 ASSERT(len < 65536);
7d4df48e 1873 wlc_bmac_write_shm(wlc_hw, M_BCN0_FRM_BYTESZ, (u16) len);
a9533e7e
HP		 1874 /* mark beacon0 valid */
1875 OR_REG(wlc_hw->osh, &regs->maccommand, MCMD_BCN0VLD);
1876}
1877
1878static void
7cc4a4c0 1879wlc_write_hw_bcntemplate1(wlc_hw_info_t *wlc_hw, void *bcn, int len)
a9533e7e
HP		 1880{
1881 d11regs_t *regs = wlc_hw->regs;
1882
1883 wlc_bmac_write_template_ram(wlc_hw, T_BCN1_TPL_BASE, (len + 3) & ~3,
1884 bcn);
1885 /* write beacon length to SCR */
1886 ASSERT(len < 65536);
7d4df48e 1887 wlc_bmac_write_shm(wlc_hw, M_BCN1_FRM_BYTESZ, (u16) len);
a9533e7e
HP		 1888 /* mark beacon1 valid */
1889 OR_REG(wlc_hw->osh, &regs->maccommand, MCMD_BCN1VLD);
1890}
1891
1892/* mac is assumed to be suspended at this point */
1893void
7cc4a4c0 1894wlc_bmac_write_hw_bcntemplates(wlc_hw_info_t *wlc_hw, void *bcn, int len,
a9533e7e
HP		 1895 bool both)
1896{
1897 d11regs_t *regs = wlc_hw->regs;
1898
1899 if (both) {
1900 wlc_write_hw_bcntemplate0(wlc_hw, bcn, len);
1901 wlc_write_hw_bcntemplate1(wlc_hw, bcn, len);
1902 } else {
1903 /* bcn 0 */
1904 if (!(R_REG(wlc_hw->osh, &regs->maccommand) & MCMD_BCN0VLD))
1905 wlc_write_hw_bcntemplate0(wlc_hw, bcn, len);
1906 /* bcn 1 */
1907 else if (!
1908 (R_REG(wlc_hw->osh, &regs->maccommand) & MCMD_BCN1VLD))
1909 wlc_write_hw_bcntemplate1(wlc_hw, bcn, len);
1910 else /* one template should always have been available */
1911 ASSERT(0);
1912 }
1913}
1914
a2627bc0
JC		 1915static void WLBANDINITFN(wlc_bmac_upd_synthpu) (wlc_hw_info_t *wlc_hw)
1916{
7d4df48e 1917 u16 v;
a9533e7e
HP		 1918 wlc_info_t *wlc = wlc_hw->wlc;
1919 /* update SYNTHPU_DLY */
1920
1921 if (WLCISLCNPHY(wlc->band)) {
1922 v = SYNTHPU_DLY_LPPHY_US;
1923 } else if (WLCISNPHY(wlc->band) && (NREV_GE(wlc->band->phyrev, 3))) {
1924 v = SYNTHPU_DLY_NPHY_US;
1925 } else {
1926 v = SYNTHPU_DLY_BPHY_US;
1927 }
1928
1929 wlc_bmac_write_shm(wlc_hw, M_SYNTHPU_DLY, v);
1930}
1931
1932/* band-specific init */
1933static void
a2627bc0
JC		 1934WLBANDINITFN(wlc_bmac_bsinit) (wlc_info_t *wlc, chanspec_t chanspec)
1935{
a9533e7e
HP		 1936 wlc_hw_info_t *wlc_hw = wlc->hw;
1937
1938 WL_TRACE(("wl%d: wlc_bmac_bsinit: bandunit %d\n", wlc_hw->unit,
1939 wlc_hw->band->bandunit));
1940
1941 /* sanity check */
1942 if (PHY_TYPE(R_REG(wlc_hw->osh, &wlc_hw->regs->phyversion)) !=
1943 PHY_TYPE_LCNXN)
1944 ASSERT((uint)
1945 PHY_TYPE(R_REG(wlc_hw->osh, &wlc_hw->regs->phyversion))
1946 == wlc_hw->band->phytype);
1947
1948 wlc_ucode_bsinit(wlc_hw);
1949
1950 wlc_phy_init(wlc_hw->band->pi, chanspec);
1951
1952 wlc_ucode_txant_set(wlc_hw);
1953
1954 /* cwmin is band-specific, update hardware with value for current band */
1955 wlc_bmac_set_cwmin(wlc_hw, wlc_hw->band->CWmin);
1956 wlc_bmac_set_cwmax(wlc_hw, wlc_hw->band->CWmax);
1957
1958 wlc_bmac_update_slot_timing(wlc_hw,
1959 BAND_5G(wlc_hw->band->
0f0881b0 1960 bandtype) ? true : wlc_hw->
a9533e7e
HP		 1961 shortslot);
1962
1963 /* write phytype and phyvers */
7d4df48e
GKH		 1964 wlc_bmac_write_shm(wlc_hw, M_PHYTYPE, (u16) wlc_hw->band->phytype);
1965 wlc_bmac_write_shm(wlc_hw, M_PHYVER, (u16) wlc_hw->band->phyrev);
a9533e7e
HP		 1966
1967 /* initialize the txphyctl1 rate table since shmem is shared between bands */
1968 wlc_upd_ofdm_pctl1_table(wlc_hw);
1969
1970 wlc_bmac_upd_synthpu(wlc_hw);
1971}
1972
7cc4a4c0 1973void wlc_bmac_core_phy_clk(wlc_hw_info_t *wlc_hw, bool clk)
a9533e7e
HP		 1974{
1975 WL_TRACE(("wl%d: wlc_bmac_core_phy_clk: clk %d\n", wlc_hw->unit, clk));
1976
1977 wlc_hw->phyclk = clk;
1978
1979 if (OFF == clk) { /* clear gmode bit, put phy into reset */
1980
1981 si_core_cflags(wlc_hw->sih, (SICF_PRST | SICF_FGC | SICF_GMODE),
1982 (SICF_PRST | SICF_FGC));
7383141b 1983 udelay(1);
a9533e7e 1984 si_core_cflags(wlc_hw->sih, (SICF_PRST | SICF_FGC), SICF_PRST);
7383141b 1985 udelay(1);
a9533e7e
HP		 1986
1987 } else { /* take phy out of reset */
1988
1989 si_core_cflags(wlc_hw->sih, (SICF_PRST | SICF_FGC), SICF_FGC);
7383141b 1990 udelay(1);
a9533e7e 1991 si_core_cflags(wlc_hw->sih, (SICF_FGC), 0);
7383141b 1992 udelay(1);
a9533e7e
HP		 1993
1994 }
1995}
1996
1997/* Perform a soft reset of the PHY PLL */
7cc4a4c0 1998void wlc_bmac_core_phypll_reset(wlc_hw_info_t *wlc_hw)
a9533e7e
HP		 1999{
2000 WL_TRACE(("wl%d: wlc_bmac_core_phypll_reset\n", wlc_hw->unit));
2001
2002 si_corereg(wlc_hw->sih, SI_CC_IDX,
ce0f1b8c 2003 offsetof(chipcregs_t, chipcontrol_addr), ~0, 0);
7383141b 2004 udelay(1);
a9533e7e 2005 si_corereg(wlc_hw->sih, SI_CC_IDX,
ce0f1b8c 2006 offsetof(chipcregs_t, chipcontrol_data), 0x4, 0);
7383141b 2007 udelay(1);
a9533e7e 2008 si_corereg(wlc_hw->sih, SI_CC_IDX,
ce0f1b8c 2009 offsetof(chipcregs_t, chipcontrol_data), 0x4, 4);
7383141b 2010 udelay(1);
a9533e7e 2011 si_corereg(wlc_hw->sih, SI_CC_IDX,
ce0f1b8c 2012 offsetof(chipcregs_t, chipcontrol_data), 0x4, 0);
7383141b 2013 udelay(1);
a9533e7e
HP		 2014}
2015
2016/* light way to turn on phy clock without reset for NPHY only
2017 * refer to wlc_bmac_core_phy_clk for full version
2018 */
7cc4a4c0 2019void wlc_bmac_phyclk_fgc(wlc_hw_info_t *wlc_hw, bool clk)
a9533e7e
HP		 2020{
2021 /* support(necessary for NPHY and HYPHY) only */
2022 if (!WLCISNPHY(wlc_hw->band))
2023 return;
2024
2025 if (ON == clk)
2026 si_core_cflags(wlc_hw->sih, SICF_FGC, SICF_FGC);
2027 else
2028 si_core_cflags(wlc_hw->sih, SICF_FGC, 0);
2029
2030}
2031
7cc4a4c0 2032void wlc_bmac_macphyclk_set(wlc_hw_info_t *wlc_hw, bool clk)
a9533e7e
HP		 2033{
2034 if (ON == clk)
2035 si_core_cflags(wlc_hw->sih, SICF_MPCLKE, SICF_MPCLKE);
2036 else
2037 si_core_cflags(wlc_hw->sih, SICF_MPCLKE, 0);
2038}
2039
7cc4a4c0 2040void wlc_bmac_phy_reset(wlc_hw_info_t *wlc_hw)
a9533e7e
HP		 2041{
2042 wlc_phy_t *pih = wlc_hw->band->pi;
66cbd3ab 2043 u32 phy_bw_clkbits;
0965ae88 2044 bool phy_in_reset = false;
a9533e7e
HP		 2045
2046 WL_TRACE(("wl%d: wlc_bmac_phy_reset\n", wlc_hw->unit));
2047
2048 if (pih == NULL)
2049 return;
2050
2051 phy_bw_clkbits = wlc_phy_clk_bwbits(wlc_hw->band->pi);
2052
2053 /* Specfic reset sequence required for NPHY rev 3 and 4 */
2054 if (WLCISNPHY(wlc_hw->band) && NREV_GE(wlc_hw->band->phyrev, 3) &&
2055 NREV_LE(wlc_hw->band->phyrev, 4)) {
2056 /* Set the PHY bandwidth */
2057 si_core_cflags(wlc_hw->sih, SICF_BWMASK, phy_bw_clkbits);
2058
7383141b 2059 udelay(1);
a9533e7e
HP		 2060
2061 /* Perform a soft reset of the PHY PLL */
2062 wlc_bmac_core_phypll_reset(wlc_hw);
2063
2064 /* reset the PHY */
2065 si_core_cflags(wlc_hw->sih, (SICF_PRST | SICF_PCLKE),
2066 (SICF_PRST | SICF_PCLKE));
0f0881b0 2067 phy_in_reset = true;
a9533e7e
HP		 2068 } else {
2069
2070 si_core_cflags(wlc_hw->sih,
2071 (SICF_PRST | SICF_PCLKE | SICF_BWMASK),
2072 (SICF_PRST | SICF_PCLKE | phy_bw_clkbits));
2073 }
2074
7383141b 2075 udelay(2);
a9533e7e
HP		 2076 wlc_bmac_core_phy_clk(wlc_hw, ON);
2077
2078 if (pih)
2079 wlc_phy_anacore(pih, ON);
2080}
2081
2082/* switch to and initialize new band */
2083static void
7cc4a4c0 2084WLBANDINITFN(wlc_bmac_setband) (wlc_hw_info_t *wlc_hw, uint bandunit,
a9533e7e
HP		 2085 chanspec_t chanspec) {
2086 wlc_info_t *wlc = wlc_hw->wlc;
66cbd3ab 2087 u32 macintmask;
a9533e7e
HP		 2088
2089 ASSERT(NBANDS_HW(wlc_hw) > 1);
2090 ASSERT(bandunit != wlc_hw->band->bandunit);
2091
2092 /* Enable the d11 core before accessing it */
2093 if (!si_iscoreup(wlc_hw->sih)) {
2094 si_core_reset(wlc_hw->sih, 0, 0);
2095 ASSERT(si_iscoreup(wlc_hw->sih));
2096 wlc_mctrl_reset(wlc_hw);
2097 }
2098
2099 macintmask = wlc_setband_inact(wlc, bandunit);
2100
2101 if (!wlc_hw->up)
2102 return;
2103
2104 wlc_bmac_core_phy_clk(wlc_hw, ON);
2105
2106 /* band-specific initializations */
2107 wlc_bmac_bsinit(wlc, chanspec);
2108
2109 /*
2110 * If there are any pending software interrupt bits,
2111 * then replace these with a harmless nonzero value
2112 * so wlc_dpc() will re-enable interrupts when done.
2113 */
2114 if (wlc->macintstatus)
2115 wlc->macintstatus = MI_DMAINT;
2116
2117 /* restore macintmask */
2118 wl_intrsrestore(wlc->wl, macintmask);
2119
2120 /* ucode should still be suspended.. */
2121 ASSERT((R_REG(wlc_hw->osh, &wlc_hw->regs->maccontrol) & MCTL_EN_MAC) ==
2122 0);
2123}
2124
2125/* low-level band switch utility routine */
a2627bc0
JC		 2126void WLBANDINITFN(wlc_setxband) (wlc_hw_info_t *wlc_hw, uint bandunit)
2127{
a9533e7e
HP		 2128 WL_TRACE(("wl%d: wlc_setxband: bandunit %d\n", wlc_hw->unit, bandunit));
2129
2130 wlc_hw->band = wlc_hw->bandstate[bandunit];
2131
2132 /* BMAC_NOTE: until we eliminate need for wlc->band refs in low level code */
2133 wlc_hw->wlc->band = wlc_hw->wlc->bandstate[bandunit];
2134
2135 /* set gmode core flag */
2136 if (wlc_hw->sbclk && !wlc_hw->noreset) {
2137 si_core_cflags(wlc_hw->sih, SICF_GMODE,
2138 ((bandunit == 0) ? SICF_GMODE : 0));
2139 }
2140}
2141
0d2f0724 2142static bool wlc_isgoodchip(wlc_hw_info_t *wlc_hw)
a2627bc0 2143{
a9533e7e
HP		 2144
2145 /* reject unsupported corerev */
2146 if (!VALID_COREREV(wlc_hw->corerev)) {
2147 WL_ERROR(("unsupported core rev %d\n", wlc_hw->corerev));
0965ae88 2148 return false;
a9533e7e
HP		 2149 }
2150
0f0881b0 2151 return true;
a9533e7e
HP		 2152}
2153
0d2f0724 2154static bool wlc_validboardtype(wlc_hw_info_t *wlc_hw)
a2627bc0 2155{
0f0881b0 2156 bool goodboard = true;
a9533e7e
HP		 2157 uint boardrev = wlc_hw->boardrev;
2158
2159 if (boardrev == 0)
0965ae88 2160 goodboard = false;
a9533e7e
HP		 2161 else if (boardrev > 0xff) {
2162 uint brt = (boardrev & 0xf000) >> 12;
2163 uint b0 = (boardrev & 0xf00) >> 8;
2164 uint b1 = (boardrev & 0xf0) >> 4;
2165 uint b2 = boardrev & 0xf;
2166
2167 if ((brt > 2) || (brt == 0) || (b0 > 9) || (b0 == 0) || (b1 > 9)
2168 || (b2 > 9))
0965ae88 2169 goodboard = false;
a9533e7e
HP		 2170 }
2171
2172 if (wlc_hw->sih->boardvendor != VENDOR_BROADCOM)
2173 return goodboard;
2174
2175 return goodboard;
2176}
2177
b4f790ee 2178static char *wlc_get_macaddr(wlc_hw_info_t *wlc_hw)
a2627bc0 2179{
a9533e7e
HP		 2180 const char *varname = "macaddr";
2181 char *macaddr;
2182
2183 /* If macaddr exists, use it (Sromrev4, CIS, ...). */
ca8c1e59
JC		 2184 macaddr = getvar(wlc_hw->vars, varname);
2185 if (macaddr != NULL)
a9533e7e
HP		 2186 return macaddr;
2187
2188 if (NBANDS_HW(wlc_hw) > 1)
2189 varname = "et1macaddr";
2190 else
2191 varname = "il0macaddr";
2192
ca8c1e59
JC		 2193 macaddr = getvar(wlc_hw->vars, varname);
2194 if (macaddr == NULL) {
a9533e7e
HP		 2195 WL_ERROR(("wl%d: wlc_get_macaddr: macaddr getvar(%s) not found\n", wlc_hw->unit, varname));
2196 }
2197
2198 return macaddr;
2199}
2200
2201/*
0965ae88 2202 * Return true if radio is disabled, otherwise false.
a9533e7e
HP		 2203 * hw radio disable signal is an external pin, users activate it asynchronously
2204 * this function could be called when driver is down and w/o clock
2205 * it operates on different registers depending on corerev and boardflag.
2206 */
7cc4a4c0 2207bool wlc_bmac_radio_read_hwdisabled(wlc_hw_info_t *wlc_hw)
a9533e7e
HP		 2208{
2209 bool v, clk, xtal;
66cbd3ab 2210 u32 resetbits = 0, flags = 0;
a9533e7e
HP		 2211
2212 xtal = wlc_hw->sbclk;
2213 if (!xtal)
2214 wlc_bmac_xtal(wlc_hw, ON);
2215
2216 /* may need to take core out of reset first */
2217 clk = wlc_hw->clk;
2218 if (!clk) {
2219 if (D11REV_LE(wlc_hw->corerev, 11))
2220 resetbits |= SICF_PCLKE;
2221
2222 /*
2223 * corerev >= 18, mac no longer enables phyclk automatically when driver accesses
2224 * phyreg throughput mac. This can be skipped since only mac reg is accessed below
2225 */
2226 if (D11REV_GE(wlc_hw->corerev, 18))
2227 flags |= SICF_PCLKE;
2228
2229 /* AI chip doesn't restore bar0win2 on hibernation/resume, need sw fixup */
2230 if ((CHIPID(wlc_hw->sih->chip) == BCM43224_CHIP_ID) ||
2231 (CHIPID(wlc_hw->sih->chip) == BCM43225_CHIP_ID) ||
2232 (CHIPID(wlc_hw->sih->chip) == BCM43421_CHIP_ID))
2233 wlc_hw->regs =
2234 (d11regs_t *) si_setcore(wlc_hw->sih, D11_CORE_ID,
2235 0);
2236 si_core_reset(wlc_hw->sih, flags, resetbits);
2237 wlc_mctrl_reset(wlc_hw);
2238 }
2239
2240 v = ((R_REG(wlc_hw->osh, &wlc_hw->regs->phydebug) & PDBG_RFD) != 0);
2241
2242 /* put core back into reset */
2243 if (!clk)
2244 si_core_disable(wlc_hw->sih, 0);
2245
2246 if (!xtal)
2247 wlc_bmac_xtal(wlc_hw, OFF);
2248
90ea2296 2249 return v;
a9533e7e
HP		 2250}
2251
2252/* Initialize just the hardware when coming out of POR or S3/S5 system states */
b4f790ee 2253void wlc_bmac_hw_up(wlc_hw_info_t *wlc_hw)
a2627bc0 2254{
a9533e7e
HP		 2255 if (wlc_hw->wlc->pub->hw_up)
2256 return;
2257
2258 WL_TRACE(("wl%d: %s:\n", wlc_hw->unit, __func__));
2259
2260 /*
2261 * Enable pll and xtal, initialize the power control registers,
2262 * and force fastclock for the remainder of wlc_up().
2263 */
2264 wlc_bmac_xtal(wlc_hw, ON);
2265 si_clkctl_init(wlc_hw->sih);
2266 wlc_clkctl_clk(wlc_hw, CLK_FAST);
2267
2268 if (BUSTYPE(wlc_hw->sih->bustype) == PCI_BUS) {
2269 si_pci_fixcfg(wlc_hw->sih);
2270
2271 /* AI chip doesn't restore bar0win2 on hibernation/resume, need sw fixup */
2272 if ((CHIPID(wlc_hw->sih->chip) == BCM43224_CHIP_ID) ||
2273 (CHIPID(wlc_hw->sih->chip) == BCM43225_CHIP_ID) ||
2274 (CHIPID(wlc_hw->sih->chip) == BCM43421_CHIP_ID))
2275 wlc_hw->regs =
2276 (d11regs_t *) si_setcore(wlc_hw->sih, D11_CORE_ID,
2277 0);
2278 }
2279
2280 /* Inform phy that a POR reset has occurred so it does a complete phy init */
2281 wlc_phy_por_inform(wlc_hw->band->pi);
2282
0965ae88 2283 wlc_hw->ucode_loaded = false;
0f0881b0 2284 wlc_hw->wlc->pub->hw_up = true;
a9533e7e
HP		 2285
2286 if ((wlc_hw->boardflags & BFL_FEM)
2287 && (CHIPID(wlc_hw->sih->chip) == BCM4313_CHIP_ID)) {
2288 if (!
2289 (wlc_hw->boardrev >= 0x1250
2290 && (wlc_hw->boardflags & BFL_FEM_BT)))
2291 si_epa_4313war(wlc_hw->sih);
2292 }
2293}
2294
7cc4a4c0 2295static bool wlc_dma_rxreset(wlc_hw_info_t *wlc_hw, uint fifo)
a9533e7e
HP		 2296{
2297 hnddma_t *di = wlc_hw->di[fifo];
2298 osl_t *osh;
2299
2300 if (D11REV_LT(wlc_hw->corerev, 12)) {
0f0881b0 2301 bool rxidle = true;
7d4df48e 2302 u16 rcv_frm_cnt = 0;
a9533e7e
HP		 2303
2304 osh = wlc_hw->osh;
2305
2306 W_REG(osh, &wlc_hw->regs->rcv_fifo_ctl, fifo << 8);
2307 SPINWAIT((!(rxidle = dma_rxidle(di))) &&
2308 ((rcv_frm_cnt =
2309 R_REG(osh, &wlc_hw->regs->rcv_frm_cnt)) != 0),
2310 50000);
2311
2312 if (!rxidle && (rcv_frm_cnt != 0))
2313 WL_ERROR(("wl%d: %s: rxdma[%d] not idle && rcv_frm_cnt(%d) not zero\n", wlc_hw->unit, __func__, fifo, rcv_frm_cnt));
7383141b 2314 mdelay(2);
a9533e7e
HP		 2315 }
2316
90ea2296 2317 return dma_rxreset(di);
a9533e7e
HP		 2318}
2319
2320/* d11 core reset
2321 * ensure fask clock during reset
2322 * reset dma
2323 * reset d11(out of reset)
2324 * reset phy(out of reset)
2325 * clear software macintstatus for fresh new start
2326 * one testing hack wlc_hw->noreset will bypass the d11/phy reset
2327 */
b4f790ee 2328void wlc_bmac_corereset(wlc_hw_info_t *wlc_hw, u32 flags)
a2627bc0 2329{
a9533e7e
HP		 2330 d11regs_t *regs;
2331 uint i;
2332 bool fastclk;
66cbd3ab 2333 u32 resetbits = 0;
a9533e7e
HP		 2334
2335 if (flags == WLC_USE_COREFLAGS)
2336 flags = (wlc_hw->band->pi ? wlc_hw->band->core_flags : 0);
2337
2338 WL_TRACE(("wl%d: %s\n", wlc_hw->unit, __func__));
2339
2340 regs = wlc_hw->regs;
2341
2342 /* request FAST clock if not on */
ca8c1e59
JC		 2343 fastclk = wlc_hw->forcefastclk;
2344 if (!fastclk)
a9533e7e
HP		 2345 wlc_clkctl_clk(wlc_hw, CLK_FAST);
2346
2347 /* reset the dma engines except first time thru */
2348 if (si_iscoreup(wlc_hw->sih)) {
2349 for (i = 0; i < NFIFO; i++)
2350 if ((wlc_hw->di[i]) && (!dma_txreset(wlc_hw->di[i]))) {
2351 WL_ERROR(("wl%d: %s: dma_txreset[%d]: cannot stop dma\n", wlc_hw->unit, __func__, i));
2352 }
2353
2354 if ((wlc_hw->di[RX_FIFO])
2355 && (!wlc_dma_rxreset(wlc_hw, RX_FIFO))) {
2356 WL_ERROR(("wl%d: %s: dma_rxreset[%d]: cannot stop dma\n", wlc_hw->unit, __func__, RX_FIFO));
2357 }
2358 if (D11REV_IS(wlc_hw->corerev, 4)
2359 && wlc_hw->di[RX_TXSTATUS_FIFO]
2360 && (!wlc_dma_rxreset(wlc_hw, RX_TXSTATUS_FIFO))) {
2361 WL_ERROR(("wl%d: %s: dma_rxreset[%d]: cannot stop dma\n", wlc_hw->unit, __func__, RX_TXSTATUS_FIFO));
2362 }
2363 }
2364 /* if noreset, just stop the psm and return */
2365 if (wlc_hw->noreset) {
2366 wlc_hw->wlc->macintstatus = 0; /* skip wl_dpc after down */
2367 wlc_bmac_mctrl(wlc_hw, MCTL_PSM_RUN | MCTL_EN_MAC, 0);
2368 return;
2369 }
2370
2371 if (D11REV_LE(wlc_hw->corerev, 11))
2372 resetbits |= SICF_PCLKE;
2373
2374 /*
2375 * corerev >= 18, mac no longer enables phyclk automatically when driver accesses phyreg
2376 * throughput mac, AND phy_reset is skipped at early stage when band->pi is invalid
2377 * need to enable PHY CLK
2378 */
2379 if (D11REV_GE(wlc_hw->corerev, 18))
2380 flags |= SICF_PCLKE;
2381
2382 /* reset the core
2383 * In chips with PMU, the fastclk request goes through d11 core reg 0x1e0, which
2384 * is cleared by the core_reset. have to re-request it.
2385 * This adds some delay and we can optimize it by also requesting fastclk through
2386 * chipcommon during this period if necessary. But that has to work coordinate
2387 * with other driver like mips/arm since they may touch chipcommon as well.
2388 */
0965ae88 2389 wlc_hw->clk = false;
a9533e7e 2390 si_core_reset(wlc_hw->sih, flags, resetbits);
0f0881b0 2391 wlc_hw->clk = true;
a9533e7e 2392 if (wlc_hw->band && wlc_hw->band->pi)
0f0881b0 2393 wlc_phy_hw_clk_state_upd(wlc_hw->band->pi, true);
a9533e7e
HP		 2394
2395 wlc_mctrl_reset(wlc_hw);
2396
2397 if (PMUCTL_ENAB(wlc_hw->sih))
2398 wlc_clkctl_clk(wlc_hw, CLK_FAST);
2399
2400 wlc_bmac_phy_reset(wlc_hw);
2401
2402 /* turn on PHY_PLL */
0f0881b0 2403 wlc_bmac_core_phypll_ctl(wlc_hw, true);
a9533e7e
HP		 2404
2405 /* clear sw intstatus */
2406 wlc_hw->wlc->macintstatus = 0;
2407
2408 /* restore the clk setting */
2409 if (!fastclk)
2410 wlc_clkctl_clk(wlc_hw, CLK_DYNAMIC);
2411}
2412
2413/* If the ucode that supports corerev 5 is used for corerev 9 and above,
2414 * txfifo sizes needs to be modified(increased) since the newer cores
2415 * have more memory.
2416 */
b4f790ee 2417static void wlc_corerev_fifofixup(wlc_hw_info_t *wlc_hw)
a2627bc0 2418{
a9533e7e 2419 d11regs_t *regs = wlc_hw->regs;
7d4df48e
GKH		 2420 u16 fifo_nu;
2421 u16 txfifo_startblk = TXFIFO_START_BLK, txfifo_endblk;
2422 u16 txfifo_def, txfifo_def1;
2423 u16 txfifo_cmd;
a9533e7e
HP		 2424 osl_t *osh;
2425
2426 if (D11REV_LT(wlc_hw->corerev, 9))
2427 goto exit;
2428
2429 /* tx fifos start at TXFIFO_START_BLK from the Base address */
2430 txfifo_startblk = TXFIFO_START_BLK;
2431
2432 osh = wlc_hw->osh;
2433
2434 /* sequence of operations: reset fifo, set fifo size, reset fifo */
2435 for (fifo_nu = 0; fifo_nu < NFIFO; fifo_nu++) {
2436
2437 txfifo_endblk = txfifo_startblk + wlc_hw->xmtfifo_sz[fifo_nu];
2438 txfifo_def = (txfifo_startblk & 0xff) |
2439 (((txfifo_endblk - 1) & 0xff) << TXFIFO_FIFOTOP_SHIFT);
2440 txfifo_def1 = ((txfifo_startblk >> 8) & 0x1) |
2441 ((((txfifo_endblk -
2442 1) >> 8) & 0x1) << TXFIFO_FIFOTOP_SHIFT);
2443 txfifo_cmd =
2444 TXFIFOCMD_RESET_MASK | (fifo_nu << TXFIFOCMD_FIFOSEL_SHIFT);
2445
2446 W_REG(osh, &regs->xmtfifocmd, txfifo_cmd);
2447 W_REG(osh, &regs->xmtfifodef, txfifo_def);
2448 if (D11REV_GE(wlc_hw->corerev, 16))
2449 W_REG(osh, &regs->xmtfifodef1, txfifo_def1);
2450
2451 W_REG(osh, &regs->xmtfifocmd, txfifo_cmd);
2452
2453 txfifo_startblk += wlc_hw->xmtfifo_sz[fifo_nu];
2454 }
2455 exit:
2456 /* need to propagate to shm location to be in sync since ucode/hw won't do this */
2457 wlc_bmac_write_shm(wlc_hw, M_FIFOSIZE0,
2458 wlc_hw->xmtfifo_sz[TX_AC_BE_FIFO]);
2459 wlc_bmac_write_shm(wlc_hw, M_FIFOSIZE1,
2460 wlc_hw->xmtfifo_sz[TX_AC_VI_FIFO]);
2461 wlc_bmac_write_shm(wlc_hw, M_FIFOSIZE2,
2462 ((wlc_hw->xmtfifo_sz[TX_AC_VO_FIFO] << 8) | wlc_hw->
2463 xmtfifo_sz[TX_AC_BK_FIFO]));
2464 wlc_bmac_write_shm(wlc_hw, M_FIFOSIZE3,
2465 ((wlc_hw->xmtfifo_sz[TX_ATIM_FIFO] << 8) | wlc_hw->
2466 xmtfifo_sz[TX_BCMC_FIFO]));
2467}
2468
2469/* d11 core init
2470 * reset PSM
2471 * download ucode/PCM
2472 * let ucode run to suspended
2473 * download ucode inits
2474 * config other core registers
2475 * init dma
2476 */
b4f790ee 2477static void wlc_coreinit(wlc_info_t *wlc)
a2627bc0 2478{
a9533e7e
HP		 2479 wlc_hw_info_t *wlc_hw = wlc->hw;
2480 d11regs_t *regs;
66cbd3ab 2481 u32 sflags;
a9533e7e
HP		 2482 uint bcnint_us;
2483 uint i = 0;
0965ae88 2484 bool fifosz_fixup = false;
a9533e7e
HP		 2485 osl_t *osh;
2486 int err = 0;
7d4df48e 2487 u16 buf[NFIFO];
a9533e7e
HP		 2488
2489 regs = wlc_hw->regs;
2490 osh = wlc_hw->osh;
2491
2492 WL_TRACE(("wl%d: wlc_coreinit\n", wlc_hw->unit));
2493
2494 /* reset PSM */
2495 wlc_bmac_mctrl(wlc_hw, ~0, (MCTL_IHR_EN | MCTL_PSM_JMP_0 | MCTL_WAKE));
2496
2497 wlc_ucode_download(wlc_hw);
2498 /*
2499 * FIFOSZ fixup
2500 * 1) core5-9 use ucode 5 to save space since the PSM is the same
2501 * 2) newer chips, driver wants to controls the fifo allocation
2502 */
2503 if (D11REV_GE(wlc_hw->corerev, 4))
0f0881b0 2504 fifosz_fixup = true;
a9533e7e
HP		 2505
2506 /* let the PSM run to the suspended state, set mode to BSS STA */
2507 W_REG(osh, &regs->macintstatus, -1);
2508 wlc_bmac_mctrl(wlc_hw, ~0,
2509 (MCTL_IHR_EN | MCTL_INFRA | MCTL_PSM_RUN | MCTL_WAKE));
2510
2511 /* wait for ucode to self-suspend after auto-init */
2512 SPINWAIT(((R_REG(osh, &regs->macintstatus) & MI_MACSSPNDD) == 0),
2513 1000 * 1000);
2514 if ((R_REG(osh, &regs->macintstatus) & MI_MACSSPNDD) == 0)
2515 WL_ERROR(("wl%d: wlc_coreinit: ucode did not self-suspend!\n",
2516 wlc_hw->unit));
2517
2518 wlc_gpio_init(wlc);
2519
2520 sflags = si_core_sflags(wlc_hw->sih, 0, 0);
2521
2522 if (D11REV_IS(wlc_hw->corerev, 23)) {
2523 if (WLCISNPHY(wlc_hw->band))
2524 wlc_write_inits(wlc_hw, d11n0initvals16);
2525 else
2526 WL_ERROR(("%s: wl%d: unsupported phy in corerev %d\n",
2527 __func__, wlc_hw->unit, wlc_hw->corerev));
2528 } else if (D11REV_IS(wlc_hw->corerev, 24)) {
2529 if (WLCISLCNPHY(wlc_hw->band)) {
2530 wlc_write_inits(wlc_hw, d11lcn0initvals24);
2531 } else {
2532 WL_ERROR(("%s: wl%d: unsupported phy in corerev %d\n",
2533 __func__, wlc_hw->unit, wlc_hw->corerev));
2534 }
2535 } else {
2536 WL_ERROR(("%s: wl%d: unsupported corerev %d\n",
2537 __func__, wlc_hw->unit, wlc_hw->corerev));
2538 }
2539
2540 /* For old ucode, txfifo sizes needs to be modified(increased) for Corerev >= 9 */
0f0881b0 2541 if (fifosz_fixup == true) {
a9533e7e
HP		 2542 wlc_corerev_fifofixup(wlc_hw);
2543 }
2544
2545 /* check txfifo allocations match between ucode and driver */
2546 buf[TX_AC_BE_FIFO] = wlc_bmac_read_shm(wlc_hw, M_FIFOSIZE0);
2547 if (buf[TX_AC_BE_FIFO] != wlc_hw->xmtfifo_sz[TX_AC_BE_FIFO]) {
2548 i = TX_AC_BE_FIFO;
2549 err = -1;
2550 }
2551 buf[TX_AC_VI_FIFO] = wlc_bmac_read_shm(wlc_hw, M_FIFOSIZE1);
2552 if (buf[TX_AC_VI_FIFO] != wlc_hw->xmtfifo_sz[TX_AC_VI_FIFO]) {
2553 i = TX_AC_VI_FIFO;
2554 err = -1;
2555 }
2556 buf[TX_AC_BK_FIFO] = wlc_bmac_read_shm(wlc_hw, M_FIFOSIZE2);
2557 buf[TX_AC_VO_FIFO] = (buf[TX_AC_BK_FIFO] >> 8) & 0xff;
2558 buf[TX_AC_BK_FIFO] &= 0xff;
2559 if (buf[TX_AC_BK_FIFO] != wlc_hw->xmtfifo_sz[TX_AC_BK_FIFO]) {
2560 i = TX_AC_BK_FIFO;
2561 err = -1;
2562 }
2563 if (buf[TX_AC_VO_FIFO] != wlc_hw->xmtfifo_sz[TX_AC_VO_FIFO]) {
2564 i = TX_AC_VO_FIFO;
2565 err = -1;
2566 }
2567 buf[TX_BCMC_FIFO] = wlc_bmac_read_shm(wlc_hw, M_FIFOSIZE3);
2568 buf[TX_ATIM_FIFO] = (buf[TX_BCMC_FIFO] >> 8) & 0xff;
2569 buf[TX_BCMC_FIFO] &= 0xff;
2570 if (buf[TX_BCMC_FIFO] != wlc_hw->xmtfifo_sz[TX_BCMC_FIFO]) {
2571 i = TX_BCMC_FIFO;
2572 err = -1;
2573 }
2574 if (buf[TX_ATIM_FIFO] != wlc_hw->xmtfifo_sz[TX_ATIM_FIFO]) {
2575 i = TX_ATIM_FIFO;
2576 err = -1;
2577 }
2578 if (err != 0) {
2579 WL_ERROR(("wlc_coreinit: txfifo mismatch: ucode size %d driver size %d index %d\n", buf[i], wlc_hw->xmtfifo_sz[i], i));
2580 /* DO NOT ASSERT corerev < 4 even there is a mismatch
2581 * shmem, since driver don't overwrite those chip and
2582 * ucode initialize data will be used.
2583 */
2584 if (D11REV_GE(wlc_hw->corerev, 4))
2585 ASSERT(0);
2586 }
2587
2588 /* make sure we can still talk to the mac */
2589 ASSERT(R_REG(osh, &regs->maccontrol) != 0xffffffff);
2590
2591 /* band-specific inits done by wlc_bsinit() */
2592
2593 /* Set up frame burst size and antenna swap threshold init values */
2594 wlc_bmac_write_shm(wlc_hw, M_MBURST_SIZE, MAXTXFRAMEBURST);
2595 wlc_bmac_write_shm(wlc_hw, M_MAX_ANTCNT, ANTCNT);
2596
2597 /* enable one rx interrupt per received frame */
2598 W_REG(osh, &regs->intrcvlazy[0], (1 << IRL_FC_SHIFT));
2599 if (D11REV_IS(wlc_hw->corerev, 4))
2600 W_REG(osh, &regs->intrcvlazy[3], (1 << IRL_FC_SHIFT));
2601
2602 /* set the station mode (BSS STA) */
2603 wlc_bmac_mctrl(wlc_hw,
2604 (MCTL_INFRA | MCTL_DISCARD_PMQ | MCTL_AP),
2605 (MCTL_INFRA | MCTL_DISCARD_PMQ));
2606
2607 /* set up Beacon interval */
2608 bcnint_us = 0x8000 << 10;
2609 W_REG(osh, &regs->tsf_cfprep, (bcnint_us << CFPREP_CBI_SHIFT));
2610 W_REG(osh, &regs->tsf_cfpstart, bcnint_us);
2611 W_REG(osh, &regs->macintstatus, MI_GP1);
2612
2613 /* write interrupt mask */
2614 W_REG(osh, &regs->intctrlregs[RX_FIFO].intmask, DEF_RXINTMASK);
2615 if (D11REV_IS(wlc_hw->corerev, 4))
2616 W_REG(osh, &regs->intctrlregs[RX_TXSTATUS_FIFO].intmask,
2617 DEF_RXINTMASK);
2618
2619 /* allow the MAC to control the PHY clock (dynamic on/off) */
2620 wlc_bmac_macphyclk_set(wlc_hw, ON);
2621
2622 /* program dynamic clock control fast powerup delay register */
2623 if (D11REV_GT(wlc_hw->corerev, 4)) {
2624 wlc->fastpwrup_dly = si_clkctl_fast_pwrup_delay(wlc_hw->sih);
2625 W_REG(osh, &regs->scc_fastpwrup_dly, wlc->fastpwrup_dly);
2626 }
2627
2628 /* tell the ucode the corerev */
7d4df48e 2629 wlc_bmac_write_shm(wlc_hw, M_MACHW_VER, (u16) wlc_hw->corerev);
a9533e7e
HP		 2630
2631 /* tell the ucode MAC capabilities */
2632 if (D11REV_GE(wlc_hw->corerev, 13)) {
2633 wlc_bmac_write_shm(wlc_hw, M_MACHW_CAP_L,
7d4df48e 2634 (u16) (wlc_hw->machwcap & 0xffff));
a9533e7e 2635 wlc_bmac_write_shm(wlc_hw, M_MACHW_CAP_H,
7d4df48e 2636 (u16) ((wlc_hw->
a9533e7e
HP		 2637 machwcap >> 16) & 0xffff));
2638 }
2639
2640 /* write retry limits to SCR, this done after PSM init */
2641 W_REG(osh, &regs->objaddr, OBJADDR_SCR_SEL | S_DOT11_SRC_LMT);
2642 (void)R_REG(osh, &regs->objaddr);
2643 W_REG(osh, &regs->objdata, wlc_hw->SRL);
2644 W_REG(osh, &regs->objaddr, OBJADDR_SCR_SEL | S_DOT11_LRC_LMT);
2645 (void)R_REG(osh, &regs->objaddr);
2646 W_REG(osh, &regs->objdata, wlc_hw->LRL);
2647
2648 /* write rate fallback retry limits */
2649 wlc_bmac_write_shm(wlc_hw, M_SFRMTXCNTFBRTHSD, wlc_hw->SFBL);
2650 wlc_bmac_write_shm(wlc_hw, M_LFRMTXCNTFBRTHSD, wlc_hw->LFBL);
2651
2652 if (D11REV_GE(wlc_hw->corerev, 16)) {
2653 AND_REG(osh, &regs->ifs_ctl, 0x0FFF);
2654 W_REG(osh, &regs->ifs_aifsn, EDCF_AIFSN_MIN);
2655 }
2656
2657 /* dma initializations */
2658 wlc->txpend16165war = 0;
2659
2660 /* init the tx dma engines */
2661 for (i = 0; i < NFIFO; i++) {
2662 if (wlc_hw->di[i])
2663 dma_txinit(wlc_hw->di[i]);
2664 }
2665
2666 /* init the rx dma engine(s) and post receive buffers */
2667 dma_rxinit(wlc_hw->di[RX_FIFO]);
2668 dma_rxfill(wlc_hw->di[RX_FIFO]);
2669 if (D11REV_IS(wlc_hw->corerev, 4)) {
2670 dma_rxinit(wlc_hw->di[RX_TXSTATUS_FIFO]);
2671 dma_rxfill(wlc_hw->di[RX_TXSTATUS_FIFO]);
2672 }
2673}
2674
2675/* This function is used for changing the tsf frac register
2676 * If spur avoidance mode is off, the mac freq will be 80/120/160Mhz
2677 * If spur avoidance mode is on1, the mac freq will be 82/123/164Mhz
2678 * If spur avoidance mode is on2, the mac freq will be 84/126/168Mhz
2679 * HTPHY Formula is 2^26/freq(MHz) e.g.
2680 * For spuron2 - 126MHz -> 2^26/126 = 532610.0
2681 * - 532610 = 0x82082 => tsf_clk_frac_h = 0x8, tsf_clk_frac_l = 0x2082
2682 * For spuron: 123MHz -> 2^26/123 = 545600.5
2683 * - 545601 = 0x85341 => tsf_clk_frac_h = 0x8, tsf_clk_frac_l = 0x5341
2684 * For spur off: 120MHz -> 2^26/120 = 559240.5
2685 * - 559241 = 0x88889 => tsf_clk_frac_h = 0x8, tsf_clk_frac_l = 0x8889
2686 */
2687
41feb5ed 2688void wlc_bmac_switch_macfreq(wlc_hw_info_t *wlc_hw, u8 spurmode)
a9533e7e
HP		 2689{
2690 d11regs_t *regs;
2691 osl_t *osh;
2692 regs = wlc_hw->regs;
2693 osh = wlc_hw->osh;
2694
2695 if ((CHIPID(wlc_hw->sih->chip) == BCM43224_CHIP_ID) ||
2696 (CHIPID(wlc_hw->sih->chip) == BCM43225_CHIP_ID)) {
2697 if (spurmode == WL_SPURAVOID_ON2) { /* 126Mhz */
2698 W_REG(osh, &regs->tsf_clk_frac_l, 0x2082);
2699 W_REG(osh, &regs->tsf_clk_frac_h, 0x8);
2700 } else if (spurmode == WL_SPURAVOID_ON1) { /* 123Mhz */
2701 W_REG(osh, &regs->tsf_clk_frac_l, 0x5341);
2702 W_REG(osh, &regs->tsf_clk_frac_h, 0x8);
2703 } else { /* 120Mhz */
2704 W_REG(osh, &regs->tsf_clk_frac_l, 0x8889);
2705 W_REG(osh, &regs->tsf_clk_frac_h, 0x8);
2706 }
2707 } else if (WLCISLCNPHY(wlc_hw->band)) {
2708 if (spurmode == WL_SPURAVOID_ON1) { /* 82Mhz */
2709 W_REG(osh, &regs->tsf_clk_frac_l, 0x7CE0);
2710 W_REG(osh, &regs->tsf_clk_frac_h, 0xC);
2711 } else { /* 80Mhz */
2712 W_REG(osh, &regs->tsf_clk_frac_l, 0xCCCD);
2713 W_REG(osh, &regs->tsf_clk_frac_h, 0xC);
2714 }
2715 }
2716}
2717
2718/* Initialize GPIOs that are controlled by D11 core */
b4f790ee 2719static void wlc_gpio_init(wlc_info_t *wlc)
a2627bc0 2720{
a9533e7e
HP		 2721 wlc_hw_info_t *wlc_hw = wlc->hw;
2722 d11regs_t *regs;
66cbd3ab 2723 u32 gc, gm;
a9533e7e
HP		 2724 osl_t *osh;
2725
2726 regs = wlc_hw->regs;
2727 osh = wlc_hw->osh;
2728
2729 /* use GPIO select 0 to get all gpio signals from the gpio out reg */
2730 wlc_bmac_mctrl(wlc_hw, MCTL_GPOUT_SEL_MASK, 0);
2731
2732 /*
2733 * Common GPIO setup:
2734 * G0 = LED 0 = WLAN Activity
2735 * G1 = LED 1 = WLAN 2.4 GHz Radio State
2736 * G2 = LED 2 = WLAN 5 GHz Radio State
2737 * G4 = radio disable input (HI enabled, LO disabled)
2738 */
2739
2740 gc = gm = 0;
2741
2742 /* Allocate GPIOs for mimo antenna diversity feature */
2743 if (WLANTSEL_ENAB(wlc)) {
2744 if (wlc_hw->antsel_type == ANTSEL_2x3) {
2745 /* Enable antenna diversity, use 2x3 mode */
2746 wlc_bmac_mhf(wlc_hw, MHF3, MHF3_ANTSEL_EN,
2747 MHF3_ANTSEL_EN, WLC_BAND_ALL);
2748 wlc_bmac_mhf(wlc_hw, MHF3, MHF3_ANTSEL_MODE,
2749 MHF3_ANTSEL_MODE, WLC_BAND_ALL);
2750
2751 /* init superswitch control */
0965ae88 2752 wlc_phy_antsel_init(wlc_hw->band->pi, false);
a9533e7e
HP		 2753
2754 } else if (wlc_hw->antsel_type == ANTSEL_2x4) {
2755 ASSERT((gm & BOARD_GPIO_12) == 0);
2756 gm |= gc |= (BOARD_GPIO_12 | BOARD_GPIO_13);
2757 /* The board itself is powered by these GPIOs (when not sending pattern)
2758 * So set them high
2759 */
2760 OR_REG(osh, &regs->psm_gpio_oe,
2761 (BOARD_GPIO_12 | BOARD_GPIO_13));
2762 OR_REG(osh, &regs->psm_gpio_out,
2763 (BOARD_GPIO_12 | BOARD_GPIO_13));
2764
2765 /* Enable antenna diversity, use 2x4 mode */
2766 wlc_bmac_mhf(wlc_hw, MHF3, MHF3_ANTSEL_EN,
2767 MHF3_ANTSEL_EN, WLC_BAND_ALL);
2768 wlc_bmac_mhf(wlc_hw, MHF3, MHF3_ANTSEL_MODE, 0,
2769 WLC_BAND_ALL);
2770
2771 /* Configure the desired clock to be 4Mhz */
2772 wlc_bmac_write_shm(wlc_hw, M_ANTSEL_CLKDIV,
2773 ANTSEL_CLKDIV_4MHZ);
2774 }
2775 }
2776 /* gpio 9 controls the PA. ucode is responsible for wiggling out and oe */
2777 if (wlc_hw->boardflags & BFL_PACTRL)
2778 gm |= gc |= BOARD_GPIO_PACTRL;
2779
2780 /* apply to gpiocontrol register */
2781 si_gpiocontrol(wlc_hw->sih, gm, gc, GPIO_DRV_PRIORITY);
2782}
2783
0d2f0724 2784static void wlc_ucode_download(wlc_hw_info_t *wlc_hw)
a2627bc0 2785{
a9533e7e
HP		 2786 wlc_info_t *wlc;
2787 wlc = wlc_hw->wlc;
2788
2789 if (wlc_hw->ucode_loaded)
2790 return;
2791
2792 if (D11REV_IS(wlc_hw->corerev, 23)) {
2793 if (WLCISNPHY(wlc_hw->band)) {
2794 wlc_ucode_write(wlc_hw, bcm43xx_16_mimo,
2795 bcm43xx_16_mimosz);
0f0881b0 2796 wlc_hw->ucode_loaded = true;
a9533e7e
HP		 2797 } else
2798 WL_ERROR(("%s: wl%d: unsupported phy in corerev %d\n",
2799 __func__, wlc_hw->unit, wlc_hw->corerev));
2800 } else if (D11REV_IS(wlc_hw->corerev, 24)) {
2801 if (WLCISLCNPHY(wlc_hw->band)) {
2802 wlc_ucode_write(wlc_hw, bcm43xx_24_lcn,
2803 bcm43xx_24_lcnsz);
0f0881b0 2804 wlc_hw->ucode_loaded = true;
a9533e7e
HP		 2805 } else {
2806 WL_ERROR(("%s: wl%d: unsupported phy in corerev %d\n",
2807 __func__, wlc_hw->unit, wlc_hw->corerev));
2808 }
2809 }
2810}
2811
0d2f0724 2812static void wlc_ucode_write(wlc_hw_info_t *wlc_hw, const u32 ucode[],
a9533e7e
HP		 2813 const uint nbytes) {
2814 osl_t *osh;
2815 d11regs_t *regs = wlc_hw->regs;
2816 uint i;
2817 uint count;
2818
2819 osh = wlc_hw->osh;
2820
2821 WL_TRACE(("wl%d: wlc_ucode_write\n", wlc_hw->unit));
2822
36c63ff6 2823 ASSERT(IS_ALIGNED(nbytes, sizeof(u32)));
a9533e7e 2824
66cbd3ab 2825 count = (nbytes / sizeof(u32));
a9533e7e
HP		 2826
2827 W_REG(osh, &regs->objaddr, (OBJADDR_AUTO_INC | OBJADDR_UCM_SEL));
2828 (void)R_REG(osh, &regs->objaddr);
2829 for (i = 0; i < count; i++)
2830 W_REG(osh, &regs->objdata, ucode[i]);
2831}
2832
7cc4a4c0 2833static void wlc_write_inits(wlc_hw_info_t *wlc_hw, const d11init_t *inits)
a9533e7e
HP		 2834{
2835 int i;
2836 osl_t *osh;
41feb5ed 2837 volatile u8 *base;
a9533e7e
HP		 2838
2839 WL_TRACE(("wl%d: wlc_write_inits\n", wlc_hw->unit));
2840
2841 osh = wlc_hw->osh;
41feb5ed 2842 base = (volatile u8 *)wlc_hw->regs;
a9533e7e
HP		 2843
2844 for (i = 0; inits[i].addr != 0xffff; i++) {
2845 ASSERT((inits[i].size == 2) || (inits[i].size == 4));
2846
2847 if (inits[i].size == 2)
e88cf8eb 2848 W_REG(osh, (u16 *)(base + inits[i].addr),
a9533e7e
HP		 2849 inits[i].value);
2850 else if (inits[i].size == 4)
e88cf8eb 2851 W_REG(osh, (u32 *)(base + inits[i].addr),
a9533e7e
HP		 2852 inits[i].value);
2853 }
2854}
2855
7cc4a4c0 2856static void wlc_ucode_txant_set(wlc_hw_info_t *wlc_hw)
a9533e7e 2857{
7d4df48e
GKH		 2858 u16 phyctl;
2859 u16 phytxant = wlc_hw->bmac_phytxant;
2860 u16 mask = PHY_TXC_ANT_MASK;
a9533e7e
HP		 2861
2862 /* set the Probe Response frame phy control word */
2863 phyctl = wlc_bmac_read_shm(wlc_hw, M_CTXPRS_BLK + C_CTX_PCTLWD_POS);
2864 phyctl = (phyctl & ~mask) | phytxant;
2865 wlc_bmac_write_shm(wlc_hw, M_CTXPRS_BLK + C_CTX_PCTLWD_POS, phyctl);
2866
2867 /* set the Response (ACK/CTS) frame phy control word */
2868 phyctl = wlc_bmac_read_shm(wlc_hw, M_RSP_PCTLWD);
2869 phyctl = (phyctl & ~mask) | phytxant;
2870 wlc_bmac_write_shm(wlc_hw, M_RSP_PCTLWD, phyctl);
2871}
2872
7d4df48e 2873void wlc_bmac_txant_set(wlc_hw_info_t *wlc_hw, u16 phytxant)
a9533e7e
HP		 2874{
2875 /* update sw state */
2876 wlc_hw->bmac_phytxant = phytxant;
2877
2878 /* push to ucode if up */
2879 if (!wlc_hw->up)
2880 return;
2881 wlc_ucode_txant_set(wlc_hw);
2882
2883}
2884
7d4df48e 2885u16 wlc_bmac_get_txant(wlc_hw_info_t *wlc_hw)
a9533e7e 2886{
7d4df48e 2887 return (u16) wlc_hw->wlc->stf->txant;
a9533e7e
HP		 2888}
2889
41feb5ed 2890void wlc_bmac_antsel_type_set(wlc_hw_info_t *wlc_hw, u8 antsel_type)
a9533e7e
HP		 2891{
2892 wlc_hw->antsel_type = antsel_type;
2893
2894 /* Update the antsel type for phy module to use */
2895 wlc_phy_antsel_type_set(wlc_hw->band->pi, antsel_type);
2896}
2897
7cc4a4c0 2898void wlc_bmac_fifoerrors(wlc_hw_info_t *wlc_hw)
a9533e7e 2899{
0965ae88 2900 bool fatal = false;
a9533e7e
HP		 2901 uint unit;
2902 uint intstatus, idx;
2903 d11regs_t *regs = wlc_hw->regs;
2904
2905 unit = wlc_hw->unit;
2906
2907 for (idx = 0; idx < NFIFO; idx++) {
2908 /* read intstatus register and ignore any non-error bits */
2909 intstatus =
2910 R_REG(wlc_hw->osh,
2911 &regs->intctrlregs[idx].intstatus) & I_ERRORS;
2912 if (!intstatus)
2913 continue;
2914
2915 WL_TRACE(("wl%d: wlc_bmac_fifoerrors: intstatus%d 0x%x\n", unit,
2916 idx, intstatus));
2917
2918 if (intstatus & I_RO) {
2919 WL_ERROR(("wl%d: fifo %d: receive fifo overflow\n",
2920 unit, idx));
2921 WLCNTINCR(wlc_hw->wlc->pub->_cnt->rxoflo);
0f0881b0 2922 fatal = true;
a9533e7e
HP		 2923 }
2924
2925 if (intstatus & I_PC) {
2926 WL_ERROR(("wl%d: fifo %d: descriptor error\n", unit,
2927 idx));
2928 WLCNTINCR(wlc_hw->wlc->pub->_cnt->dmade);
0f0881b0 2929 fatal = true;
a9533e7e
HP		 2930 }
2931
2932 if (intstatus & I_PD) {
2933 WL_ERROR(("wl%d: fifo %d: data error\n", unit, idx));
2934 WLCNTINCR(wlc_hw->wlc->pub->_cnt->dmada);
0f0881b0 2935 fatal = true;
a9533e7e
HP		 2936 }
2937
2938 if (intstatus & I_DE) {
2939 WL_ERROR(("wl%d: fifo %d: descriptor protocol error\n",
2940 unit, idx));
2941 WLCNTINCR(wlc_hw->wlc->pub->_cnt->dmape);
0f0881b0 2942 fatal = true;
a9533e7e
HP		 2943 }
2944
2945 if (intstatus & I_RU) {
2946 WL_ERROR(("wl%d: fifo %d: receive descriptor underflow\n", unit, idx));
2947 WLCNTINCR(wlc_hw->wlc->pub->_cnt->rxuflo[idx]);
2948 }
2949
2950 if (intstatus & I_XU) {
2951 WL_ERROR(("wl%d: fifo %d: transmit fifo underflow\n",
2952 idx, unit));
2953 WLCNTINCR(wlc_hw->wlc->pub->_cnt->txuflo);
0f0881b0 2954 fatal = true;
a9533e7e
HP		 2955 }
2956
2957 if (fatal) {
2958 wlc_fatal_error(wlc_hw->wlc); /* big hammer */
2959 break;
2960 } else
2961 W_REG(wlc_hw->osh, &regs->intctrlregs[idx].intstatus,
2962 intstatus);
2963 }
2964}
2965
7cc4a4c0 2966void wlc_intrson(wlc_info_t *wlc)
a9533e7e
HP		 2967{
2968 wlc_hw_info_t *wlc_hw = wlc->hw;
2969 ASSERT(wlc->defmacintmask);
2970 wlc->macintmask = wlc->defmacintmask;
2971 W_REG(wlc_hw->osh, &wlc_hw->regs->macintmask, wlc->macintmask);
2972}
2973
2974/* callback for siutils.c, which has only wlc handler, no wl
2975 * they both check up, not only because there is no need to off/restore d11 interrupt
2976 * but also because per-port code may require sync with valid interrupt.
2977 */
2978
66cbd3ab 2979static u32 wlc_wlintrsoff(wlc_info_t *wlc)
a9533e7e
HP		 2980{
2981 if (!wlc->hw->up)
2982 return 0;
2983
2984 return wl_intrsoff(wlc->wl);
2985}
2986
66cbd3ab 2987static void wlc_wlintrsrestore(wlc_info_t *wlc, u32 macintmask)
a9533e7e
HP		 2988{
2989 if (!wlc->hw->up)
2990 return;
2991
2992 wl_intrsrestore(wlc->wl, macintmask);
2993}
2994
66cbd3ab 2995u32 wlc_intrsoff(wlc_info_t *wlc)
a9533e7e
HP		 2996{
2997 wlc_hw_info_t *wlc_hw = wlc->hw;
66cbd3ab 2998 u32 macintmask;
a9533e7e
HP		 2999
3000 if (!wlc_hw->clk)
3001 return 0;
3002
3003 macintmask = wlc->macintmask; /* isr can still happen */
3004
3005 W_REG(wlc_hw->osh, &wlc_hw->regs->macintmask, 0);
3006 (void)R_REG(wlc_hw->osh, &wlc_hw->regs->macintmask); /* sync readback */
7383141b 3007 udelay(1); /* ensure int line is no longer driven */
a9533e7e
HP		 3008 wlc->macintmask = 0;
3009
3010 /* return previous macintmask; resolve race between us and our isr */
90ea2296 3011 return wlc->macintstatus ? 0 : macintmask;
a9533e7e
HP		 3012}
3013
66cbd3ab 3014void wlc_intrsrestore(wlc_info_t *wlc, u32 macintmask)
a9533e7e
HP		 3015{
3016 wlc_hw_info_t *wlc_hw = wlc->hw;
3017 if (!wlc_hw->clk)
3018 return;
3019
3020 wlc->macintmask = macintmask;
3021 W_REG(wlc_hw->osh, &wlc_hw->regs->macintmask, wlc->macintmask);
3022}
3023
7cc4a4c0 3024void wlc_bmac_mute(wlc_hw_info_t *wlc_hw, bool on, mbool flags)
a9533e7e
HP		 3025{
3026 struct ether_addr null_ether_addr = { {0, 0, 0, 0, 0, 0} };
3027
3028 if (on) {
3029 /* suspend tx fifos */
3030 wlc_bmac_tx_fifo_suspend(wlc_hw, TX_DATA_FIFO);
3031 wlc_bmac_tx_fifo_suspend(wlc_hw, TX_CTL_FIFO);
3032 wlc_bmac_tx_fifo_suspend(wlc_hw, TX_AC_BK_FIFO);
3033 wlc_bmac_tx_fifo_suspend(wlc_hw, TX_AC_VI_FIFO);
3034
3035 /* zero the address match register so we do not send ACKs */
3036 wlc_bmac_set_addrmatch(wlc_hw, RCM_MAC_OFFSET,
3037 &null_ether_addr);
3038 } else {
3039 /* resume tx fifos */
3040 if (!wlc_hw->wlc->tx_suspended) {
3041 wlc_bmac_tx_fifo_resume(wlc_hw, TX_DATA_FIFO);
3042 }
3043 wlc_bmac_tx_fifo_resume(wlc_hw, TX_CTL_FIFO);
3044 wlc_bmac_tx_fifo_resume(wlc_hw, TX_AC_BK_FIFO);
3045 wlc_bmac_tx_fifo_resume(wlc_hw, TX_AC_VI_FIFO);
3046
3047 /* Restore address */
3048 wlc_bmac_set_addrmatch(wlc_hw, RCM_MAC_OFFSET,
3049 &wlc_hw->etheraddr);
3050 }
3051
3052 wlc_phy_mute_upd(wlc_hw->band->pi, on, flags);
3053
3054 if (on)
3055 wlc_ucode_mute_override_set(wlc_hw);
3056 else
3057 wlc_ucode_mute_override_clear(wlc_hw);
3058}
3059
7cc4a4c0 3060void wlc_bmac_set_deaf(wlc_hw_info_t *wlc_hw, bool user_flag)
a9533e7e
HP		 3061{
3062 wlc_phy_set_deaf(wlc_hw->band->pi, user_flag);
3063}
3064
7cc4a4c0 3065int wlc_bmac_xmtfifo_sz_get(wlc_hw_info_t *wlc_hw, uint fifo, uint *blocks)
a9533e7e
HP		 3066{
3067 if (fifo >= NFIFO)
3068 return BCME_RANGE;
3069
3070 *blocks = wlc_hw->xmtfifo_sz[fifo];
3071
3072 return 0;
3073}
3074
7cc4a4c0 3075int wlc_bmac_xmtfifo_sz_set(wlc_hw_info_t *wlc_hw, uint fifo, uint blocks)
a9533e7e
HP		 3076{
3077 if (fifo >= NFIFO || blocks > 299)
3078 return BCME_RANGE;
3079
7d4df48e
GKH		 3080 /* BMAC_NOTE, change blocks to u16 */
3081 wlc_hw->xmtfifo_sz[fifo] = (u16) blocks;
a9533e7e
HP		 3082
3083 return 0;
3084}
3085
3086/* wlc_bmac_tx_fifo_suspended:
3087 * Check the MAC's tx suspend status for a tx fifo.
3088 *
3089 * When the MAC acknowledges a tx suspend, it indicates that no more
3090 * packets will be transmitted out the radio. This is independent of
3091 * DMA channel suspension---the DMA may have finished suspending, or may still
3092 * be pulling data into a tx fifo, by the time the MAC acks the suspend
3093 * request.
3094 */
7cc4a4c0 3095bool wlc_bmac_tx_fifo_suspended(wlc_hw_info_t *wlc_hw, uint tx_fifo)
a9533e7e
HP		 3096{
3097 /* check that a suspend has been requested and is no longer pending */
3098
3099 /*
3100 * for DMA mode, the suspend request is set in xmtcontrol of the DMA engine,
3101 * and the tx fifo suspend at the lower end of the MAC is acknowledged in the
3102 * chnstatus register.
3103 * The tx fifo suspend completion is independent of the DMA suspend completion and
3104 * may be acked before or after the DMA is suspended.
3105 */
3106 if (dma_txsuspended(wlc_hw->di[tx_fifo]) &&
3107 (R_REG(wlc_hw->osh, &wlc_hw->regs->chnstatus) &
3108 (1 << tx_fifo)) == 0)
0f0881b0 3109 return true;
a9533e7e 3110
0965ae88 3111 return false;
a9533e7e
HP		 3112}
3113
7cc4a4c0 3114void wlc_bmac_tx_fifo_suspend(wlc_hw_info_t *wlc_hw, uint tx_fifo)
a9533e7e 3115{
41feb5ed 3116 u8 fifo = 1 << tx_fifo;
a9533e7e
HP		 3117
3118 /* Two clients of this code, 11h Quiet period and scanning. */
3119
3120 /* only suspend if not already suspended */
3121 if ((wlc_hw->suspended_fifos & fifo) == fifo)
3122 return;
3123
3124 /* force the core awake only if not already */
3125 if (wlc_hw->suspended_fifos == 0)
3126 wlc_ucode_wake_override_set(wlc_hw, WLC_WAKE_OVERRIDE_TXFIFO);
3127
3128 wlc_hw->suspended_fifos |= fifo;
3129
3130 if (wlc_hw->di[tx_fifo]) {
3131 /* Suspending AMPDU transmissions in the middle can cause underflow
3132 * which may result in mismatch between ucode and driver
3133 * so suspend the mac before suspending the FIFO
3134 */
3135 if (WLC_PHY_11N_CAP(wlc_hw->band))
3136 wlc_suspend_mac_and_wait(wlc_hw->wlc);
3137
3138 dma_txsuspend(wlc_hw->di[tx_fifo]);
3139
3140 if (WLC_PHY_11N_CAP(wlc_hw->band))
3141 wlc_enable_mac(wlc_hw->wlc);
3142 }
3143}
3144
7cc4a4c0 3145void wlc_bmac_tx_fifo_resume(wlc_hw_info_t *wlc_hw, uint tx_fifo)
a9533e7e
HP		 3146{
3147 /* BMAC_NOTE: WLC_TX_FIFO_ENAB is done in wlc_dpc() for DMA case but need to be done
3148 * here for PIO otherwise the watchdog will catch the inconsistency and fire
3149 */
3150 /* Two clients of this code, 11h Quiet period and scanning. */
3151 if (wlc_hw->di[tx_fifo])
3152 dma_txresume(wlc_hw->di[tx_fifo]);
3153
3154 /* allow core to sleep again */
3155 if (wlc_hw->suspended_fifos == 0)
3156 return;
3157 else {
3158 wlc_hw->suspended_fifos &= ~(1 << tx_fifo);
3159 if (wlc_hw->suspended_fifos == 0)
3160 wlc_ucode_wake_override_clear(wlc_hw,
3161 WLC_WAKE_OVERRIDE_TXFIFO);
3162 }
3163}
3164
3165/*
3166 * Read and clear macintmask and macintstatus and intstatus registers.
3167 * This routine should be called with interrupts off
3168 * Return:
0f0881b0 3169 * -1 if DEVICEREMOVED(wlc) evaluates to true;
a9533e7e
HP		 3170 * 0 if the interrupt is not for us, or we are in some special cases;
3171 * device interrupt status bits otherwise.
3172 */
66cbd3ab 3173static inline u32 wlc_intstatus(wlc_info_t *wlc, bool in_isr)
a9533e7e
HP		 3174{
3175 wlc_hw_info_t *wlc_hw = wlc->hw;
3176 d11regs_t *regs = wlc_hw->regs;
66cbd3ab
GKH		 3177 u32 macintstatus;
3178 u32 intstatus_rxfifo, intstatus_txsfifo;
a9533e7e
HP		 3179 osl_t *osh;
3180
3181 osh = wlc_hw->osh;
3182
3183 /* macintstatus includes a DMA interrupt summary bit */
3184 macintstatus = R_REG(osh, &regs->macintstatus);
3185
3186 WL_TRACE(("wl%d: macintstatus: 0x%x\n", wlc_hw->unit, macintstatus));
3187
3188 /* detect cardbus removed, in power down(suspend) and in reset */
3189 if (DEVICEREMOVED(wlc))
3190 return -1;
3191
3192 /* DEVICEREMOVED succeeds even when the core is still resetting,
3193 * handle that case here.
3194 */
3195 if (macintstatus == 0xffffffff)
3196 return 0;
3197
3198 /* defer unsolicited interrupts */
3199 macintstatus &= (in_isr ? wlc->macintmask : wlc->defmacintmask);
3200
3201 /* if not for us */
3202 if (macintstatus == 0)
3203 return 0;
3204
3205 /* interrupts are already turned off for CFE build
3206 * Caution: For CFE Turning off the interrupts again has some undesired
3207 * consequences
3208 */
3209 /* turn off the interrupts */
3210 W_REG(osh, &regs->macintmask, 0);
3211#ifndef BCMSDIO
3212 (void)R_REG(osh, &regs->macintmask); /* sync readback */
3213#endif
3214 wlc->macintmask = 0;
3215
3216 /* clear device interrupts */
3217 W_REG(osh, &regs->macintstatus, macintstatus);
3218
3219 /* MI_DMAINT is indication of non-zero intstatus */
3220 if (macintstatus & MI_DMAINT) {
3221 if (D11REV_IS(wlc_hw->corerev, 4)) {
3222 intstatus_rxfifo =
3223 R_REG(osh, &regs->intctrlregs[RX_FIFO].intstatus);
3224 intstatus_txsfifo =
3225 R_REG(osh,
3226 &regs->intctrlregs[RX_TXSTATUS_FIFO].
3227 intstatus);
3228 WL_TRACE(("wl%d: intstatus_rxfifo 0x%x, intstatus_txsfifo 0x%x\n", wlc_hw->unit, intstatus_rxfifo, intstatus_txsfifo));
3229
3230 /* defer unsolicited interrupt hints */
3231 intstatus_rxfifo &= DEF_RXINTMASK;
3232 intstatus_txsfifo &= DEF_RXINTMASK;
3233
3234 /* MI_DMAINT bit in macintstatus is indication of RX_FIFO interrupt */
3235 /* clear interrupt hints */
3236 if (intstatus_rxfifo)
3237 W_REG(osh,
3238 &regs->intctrlregs[RX_FIFO].intstatus,
3239 intstatus_rxfifo);
3240 else
3241 macintstatus &= ~MI_DMAINT;
3242
3243 /* MI_TFS bit in macintstatus is encoding of RX_TXSTATUS_FIFO interrupt */
3244 if (intstatus_txsfifo) {
3245 W_REG(osh,
3246 &regs->intctrlregs[RX_TXSTATUS_FIFO].
3247 intstatus, intstatus_txsfifo);
3248 macintstatus |= MI_TFS;
3249 }
3250 } else {
3251 /*
3252 * For corerevs >= 5, only fifo interrupt enabled is I_RI in RX_FIFO.
3253 * If MI_DMAINT is set, assume it is set and clear the interrupt.
3254 */
3255 W_REG(osh, &regs->intctrlregs[RX_FIFO].intstatus,
3256 DEF_RXINTMASK);
3257 }
3258 }
3259
3260 return macintstatus;
3261}
3262
3263/* Update wlc->macintstatus and wlc->intstatus[]. */
0965ae88 3264/* Return true if they are updated successfully. false otherwise */
7cc4a4c0 3265bool wlc_intrsupd(wlc_info_t *wlc)
a9533e7e 3266{
66cbd3ab 3267 u32 macintstatus;
a9533e7e
HP		 3268
3269 ASSERT(wlc->macintstatus != 0);
3270
3271 /* read and clear macintstatus and intstatus registers */
0965ae88 3272 macintstatus = wlc_intstatus(wlc, false);
a9533e7e
HP		 3273
3274 /* device is removed */
3275 if (macintstatus == 0xffffffff)
0965ae88 3276 return false;
a9533e7e
HP		 3277
3278 /* update interrupt status in software */
3279 wlc->macintstatus |= macintstatus;
3280
0f0881b0 3281 return true;
a9533e7e
HP		 3282}
3283
3284/*
3285 * First-level interrupt processing.
0965ae88 3286 * Return true if this was our interrupt, false otherwise.
0f0881b0 3287 * *wantdpc will be set to true if further wlc_dpc() processing is required,
0965ae88 3288 * false otherwise.
a9533e7e 3289 */
7cc4a4c0 3290bool BCMFASTPATH wlc_isr(wlc_info_t *wlc, bool *wantdpc)
a9533e7e
HP		 3291{
3292 wlc_hw_info_t *wlc_hw = wlc->hw;
66cbd3ab 3293 u32 macintstatus;
a9533e7e 3294
0965ae88 3295 *wantdpc = false;
a9533e7e
HP		 3296
3297 if (!wlc_hw->up || !wlc->macintmask)
0965ae88 3298 return false;
a9533e7e
HP		 3299
3300 /* read and clear macintstatus and intstatus registers */
0f0881b0 3301 macintstatus = wlc_intstatus(wlc, true);
a9533e7e
HP		 3302
3303 if (macintstatus == 0xffffffff)
3304 WL_ERROR(("DEVICEREMOVED detected in the ISR code path.\n"));
3305
3306 /* it is not for us */
3307 if (macintstatus == 0)
0965ae88 3308 return false;
a9533e7e 3309
0f0881b0 3310 *wantdpc = true;
a9533e7e
HP		 3311
3312 /* save interrupt status bits */
3313 ASSERT(wlc->macintstatus == 0);
3314 wlc->macintstatus = macintstatus;
3315
0f0881b0 3316 return true;
a9533e7e
HP		 3317
3318}
3319
3320/* process tx completion events for corerev < 5 */
7cc4a4c0 3321static bool wlc_bmac_txstatus_corerev4(wlc_hw_info_t *wlc_hw)
a9533e7e
HP		 3322{
3323 void *status_p;
3324 tx_status_t *txs;
3325 osl_t *osh;
0965ae88 3326 bool fatal = false;
a9533e7e
HP		 3327
3328 WL_TRACE(("wl%d: wlc_txstatusrecv\n", wlc_hw->unit));
3329
3330 osh = wlc_hw->osh;
3331
3332 while (!fatal && (status_p = dma_rx(wlc_hw->di[RX_TXSTATUS_FIFO]))) {
3333
3334 txs = (tx_status_t *) PKTDATA(status_p);
3335 /* MAC uses little endian only */
3336 ltoh16_buf((void *)txs, sizeof(tx_status_t));
3337
3338 /* shift low bits for tx_status_t status compatibility */
3339 txs->status = (txs->status & ~TXS_COMPAT_MASK)
3340 | (((txs->status & TXS_COMPAT_MASK) << TXS_COMPAT_SHIFT));
3341
3342 fatal = wlc_bmac_dotxstatus(wlc_hw, txs, 0);
3343
0965ae88 3344 PKTFREE(osh, status_p, false);
a9533e7e
HP		 3345 }
3346
3347 if (fatal)
0f0881b0 3348 return true;
a9533e7e
HP		 3349
3350 /* post more rbufs */
3351 dma_rxfill(wlc_hw->di[RX_TXSTATUS_FIFO]);
3352
0965ae88 3353 return false;
a9533e7e
HP		 3354}
3355
3356static bool BCMFASTPATH
66cbd3ab 3357wlc_bmac_dotxstatus(wlc_hw_info_t *wlc_hw, tx_status_t *txs, u32 s2)
a9533e7e
HP		 3358{
3359 /* discard intermediate indications for ucode with one legitimate case:
3360 * e.g. if "useRTS" is set. ucode did a successful rts/cts exchange, but the subsequent
3361 * tx of DATA failed. so it will start rts/cts from the beginning (resetting the rts
3362 * transmission count)
3363 */
3364 if (!(txs->status & TX_STATUS_AMPDU)
3365 && (txs->status & TX_STATUS_INTERMEDIATE)) {
0965ae88 3366 return false;
a9533e7e
HP		 3367 }
3368
3369 return wlc_dotxstatus(wlc_hw->wlc, txs, s2);
3370}
3371
3372/* process tx completion events in BMAC
0965ae88 3373 * Return true if more tx status need to be processed. false otherwise.
a9533e7e
HP		 3374 */
3375static bool BCMFASTPATH
7cc4a4c0 3376wlc_bmac_txstatus(wlc_hw_info_t *wlc_hw, bool bound, bool *fatal)
a9533e7e 3377{
0965ae88 3378 bool morepending = false;
a9533e7e
HP		 3379 wlc_info_t *wlc = wlc_hw->wlc;
3380
3381 WL_TRACE(("wl%d: wlc_bmac_txstatus\n", wlc_hw->unit));
3382
3383 if (D11REV_IS(wlc_hw->corerev, 4)) {
3384 /* to retire soon */
3385 *fatal = wlc_bmac_txstatus_corerev4(wlc->hw);
3386
3387 if (*fatal)
3388 return 0;
3389 } else {
3390 /* corerev >= 5 */
3391 d11regs_t *regs;
3392 osl_t *osh;
3393 tx_status_t txstatus, *txs;
66cbd3ab 3394 u32 s1, s2;
a9533e7e
HP		 3395 uint n = 0;
3396 /* Param 'max_tx_num' indicates max. # tx status to process before break out. */
3397 uint max_tx_num = bound ? wlc->pub->tunables->txsbnd : -1;
3398
3399 txs = &txstatus;
3400 regs = wlc_hw->regs;
3401 osh = wlc_hw->osh;
3402 while (!(*fatal)
3403 && (s1 = R_REG(osh, &regs->frmtxstatus)) & TXS_V) {
3404
3405 if (s1 == 0xffffffff) {
3406 WL_ERROR(("wl%d: %s: dead chip\n",
3407 wlc_hw->unit, __func__));
3408 ASSERT(s1 != 0xffffffff);
3409 return morepending;
3410 }
3411
3412 s2 = R_REG(osh, &regs->frmtxstatus2);
3413
3414 txs->status = s1 & TXS_STATUS_MASK;
3415 txs->frameid = (s1 & TXS_FID_MASK) >> TXS_FID_SHIFT;
3416 txs->sequence = s2 & TXS_SEQ_MASK;
3417 txs->phyerr = (s2 & TXS_PTX_MASK) >> TXS_PTX_SHIFT;
3418 txs->lasttxtime = 0;
3419
3420 *fatal = wlc_bmac_dotxstatus(wlc_hw, txs, s2);
3421
3422 /* !give others some time to run! */
3423 if (++n >= max_tx_num)
3424 break;
3425 }
3426
3427 if (*fatal)
3428 return 0;
3429
3430 if (n >= max_tx_num)
0f0881b0 3431 morepending = true;
a9533e7e
HP		 3432 }
3433
3434 if (!pktq_empty(&wlc->active_queue->q))
3435 wlc_send_q(wlc, wlc->active_queue);
3436
3437 return morepending;
3438}
3439
7cc4a4c0 3440void wlc_suspend_mac_and_wait(wlc_info_t *wlc)
a9533e7e
HP		 3441{
3442 wlc_hw_info_t *wlc_hw = wlc->hw;
3443 d11regs_t *regs = wlc_hw->regs;
66cbd3ab 3444 u32 mc, mi;
a9533e7e
HP		 3445 osl_t *osh;
3446
3447 WL_TRACE(("wl%d: wlc_suspend_mac_and_wait: bandunit %d\n", wlc_hw->unit,
3448 wlc_hw->band->bandunit));
3449
3450 /*
3451 * Track overlapping suspend requests
3452 */
3453 wlc_hw->mac_suspend_depth++;
3454 if (wlc_hw->mac_suspend_depth > 1)
3455 return;
3456
3457 osh = wlc_hw->osh;
3458
3459 /* force the core awake */
3460 wlc_ucode_wake_override_set(wlc_hw, WLC_WAKE_OVERRIDE_MACSUSPEND);
3461
3462 mc = R_REG(osh, &regs->maccontrol);
3463
3464 if (mc == 0xffffffff) {
3465 WL_ERROR(("wl%d: %s: dead chip\n", wlc_hw->unit, __func__));
3466 wl_down(wlc->wl);
3467 return;
3468 }
3469 ASSERT(!(mc & MCTL_PSM_JMP_0));
3470 ASSERT(mc & MCTL_PSM_RUN);
3471 ASSERT(mc & MCTL_EN_MAC);
3472
3473 mi = R_REG(osh, &regs->macintstatus);
3474 if (mi == 0xffffffff) {
3475 WL_ERROR(("wl%d: %s: dead chip\n", wlc_hw->unit, __func__));
3476 wl_down(wlc->wl);
3477 return;
3478 }
3479 ASSERT(!(mi & MI_MACSSPNDD));
3480
3481 wlc_bmac_mctrl(wlc_hw, MCTL_EN_MAC, 0);
3482
3483 SPINWAIT(!(R_REG(osh, &regs->macintstatus) & MI_MACSSPNDD),
3484 WLC_MAX_MAC_SUSPEND);
3485
3486 if (!(R_REG(osh, &regs->macintstatus) & MI_MACSSPNDD)) {
3487 WL_ERROR(("wl%d: wlc_suspend_mac_and_wait: waited %d uS and "
3488 "MI_MACSSPNDD is still not on.\n",
3489 wlc_hw->unit, WLC_MAX_MAC_SUSPEND));
3490 WL_ERROR(("wl%d: psmdebug 0x%08x, phydebug 0x%08x, psm_brc 0x%04x\n", wlc_hw->unit, R_REG(osh, &regs->psmdebug), R_REG(osh, &regs->phydebug), R_REG(osh, &regs->psm_brc)));
3491 }
3492
3493 mc = R_REG(osh, &regs->maccontrol);
3494 if (mc == 0xffffffff) {
3495 WL_ERROR(("wl%d: %s: dead chip\n", wlc_hw->unit, __func__));
3496 wl_down(wlc->wl);
3497 return;
3498 }
3499 ASSERT(!(mc & MCTL_PSM_JMP_0));
3500 ASSERT(mc & MCTL_PSM_RUN);
3501 ASSERT(!(mc & MCTL_EN_MAC));
3502}
3503
7cc4a4c0 3504void wlc_enable_mac(wlc_info_t *wlc)
a9533e7e
HP		 3505{
3506 wlc_hw_info_t *wlc_hw = wlc->hw;
3507 d11regs_t *regs = wlc_hw->regs;
66cbd3ab 3508 u32 mc, mi;
a9533e7e
HP		 3509 osl_t *osh;
3510
3511 WL_TRACE(("wl%d: wlc_enable_mac: bandunit %d\n", wlc_hw->unit,
3512 wlc->band->bandunit));
3513
3514 /*
3515 * Track overlapping suspend requests
3516 */
3517 ASSERT(wlc_hw->mac_suspend_depth > 0);
3518 wlc_hw->mac_suspend_depth--;
3519 if (wlc_hw->mac_suspend_depth > 0)
3520 return;
3521
3522 osh = wlc_hw->osh;
3523
3524 mc = R_REG(osh, &regs->maccontrol);
3525 ASSERT(!(mc & MCTL_PSM_JMP_0));
3526 ASSERT(!(mc & MCTL_EN_MAC));
3527 ASSERT(mc & MCTL_PSM_RUN);
3528
3529 wlc_bmac_mctrl(wlc_hw, MCTL_EN_MAC, MCTL_EN_MAC);
3530 W_REG(osh, &regs->macintstatus, MI_MACSSPNDD);
3531
3532 mc = R_REG(osh, &regs->maccontrol);
3533 ASSERT(!(mc & MCTL_PSM_JMP_0));
3534 ASSERT(mc & MCTL_EN_MAC);
3535 ASSERT(mc & MCTL_PSM_RUN);
3536
3537 mi = R_REG(osh, &regs->macintstatus);
3538 ASSERT(!(mi & MI_MACSSPNDD));
3539
3540 wlc_ucode_wake_override_clear(wlc_hw, WLC_WAKE_OVERRIDE_MACSUSPEND);
3541}
3542
7cc4a4c0 3543void wlc_bmac_ifsctl_edcrs_set(wlc_hw_info_t *wlc_hw, bool abie, bool isht)
a9533e7e
HP		 3544{
3545 if (!(WLCISNPHY(wlc_hw->band) && (D11REV_GE(wlc_hw->corerev, 16))))
3546 return;
3547
3548 if (isht) {
3549 if (WLCISNPHY(wlc_hw->band) && NREV_LT(wlc_hw->band->phyrev, 3)) {
3550 AND_REG(wlc_hw->osh, &wlc_hw->regs->ifs_ctl1,
3551 ~IFS_CTL1_EDCRS);
3552 }
3553 } else {
3554 /* enable EDCRS for non-11n association */
3555 OR_REG(wlc_hw->osh, &wlc_hw->regs->ifs_ctl1, IFS_CTL1_EDCRS);
3556 }
3557
3558 if (WLCISNPHY(wlc_hw->band) && NREV_GE(wlc_hw->band->phyrev, 3)) {
3559 if (CHSPEC_IS20(wlc_hw->chanspec)) {
3560 /* 20 mhz, use 20U ED only */
3561 OR_REG(wlc_hw->osh, &wlc_hw->regs->ifs_ctl1,
3562 IFS_CTL1_EDCRS);
3563 AND_REG(wlc_hw->osh, &wlc_hw->regs->ifs_ctl1,
3564 ~IFS_CTL1_EDCRS_20L);
3565 AND_REG(wlc_hw->osh, &wlc_hw->regs->ifs_ctl1,
3566 ~IFS_CTL1_EDCRS_40);
3567 } else {
3568 /* 40 mhz, use 20U 20L and 40 ED */
3569 OR_REG(wlc_hw->osh, &wlc_hw->regs->ifs_ctl1,
3570 IFS_CTL1_EDCRS);
3571 OR_REG(wlc_hw->osh, &wlc_hw->regs->ifs_ctl1,
3572 IFS_CTL1_EDCRS_20L);
3573 OR_REG(wlc_hw->osh, &wlc_hw->regs->ifs_ctl1,
3574 IFS_CTL1_EDCRS_40);
3575 }
3576 }
3577}
3578
7cc4a4c0 3579static void wlc_upd_ofdm_pctl1_table(wlc_hw_info_t *wlc_hw)
a9533e7e 3580{
41feb5ed
GKH		 3581 u8 rate;
3582 u8 rates[8] = {
a9533e7e
HP		 3583 WLC_RATE_6M, WLC_RATE_9M, WLC_RATE_12M, WLC_RATE_18M,
3584 WLC_RATE_24M, WLC_RATE_36M, WLC_RATE_48M, WLC_RATE_54M
3585 };
7d4df48e
GKH		 3586 u16 entry_ptr;
3587 u16 pctl1;
a9533e7e
HP		 3588 uint i;
3589
3590 if (!WLC_PHY_11N_CAP(wlc_hw->band))
3591 return;
3592
3593 /* walk the phy rate table and update the entries */
8d3d6a69 3594 for (i = 0; i < ARRAY_SIZE(rates); i++) {
a9533e7e
HP		 3595 rate = rates[i];
3596
3597 entry_ptr = wlc_bmac_ofdm_ratetable_offset(wlc_hw, rate);
3598
3599 /* read the SHM Rate Table entry OFDM PCTL1 values */
3600 pctl1 =
3601 wlc_bmac_read_shm(wlc_hw, entry_ptr + M_RT_OFDM_PCTL1_POS);
3602
3603 /* modify the value */
3604 pctl1 &= ~PHY_TXC1_MODE_MASK;
3605 pctl1 |= (wlc_hw->hw_stf_ss_opmode << PHY_TXC1_MODE_SHIFT);
3606
3607 /* Update the SHM Rate Table entry OFDM PCTL1 values */
3608 wlc_bmac_write_shm(wlc_hw, entry_ptr + M_RT_OFDM_PCTL1_POS,
3609 pctl1);
3610 }
3611}
3612
7d4df48e 3613static u16 wlc_bmac_ofdm_ratetable_offset(wlc_hw_info_t *wlc_hw, u8 rate)
a9533e7e
HP		 3614{
3615 uint i;
41feb5ed 3616 u8 plcp_rate = 0;
a9533e7e 3617 struct plcp_signal_rate_lookup {
41feb5ed
GKH		 3618 u8 rate;
3619 u8 signal_rate;
a9533e7e
HP		 3620 };
3621 /* OFDM RATE sub-field of PLCP SIGNAL field, per 802.11 sec 17.3.4.1 */
3622 const struct plcp_signal_rate_lookup rate_lookup[] = {
3623 {WLC_RATE_6M, 0xB},
3624 {WLC_RATE_9M, 0xF},
3625 {WLC_RATE_12M, 0xA},
3626 {WLC_RATE_18M, 0xE},
3627 {WLC_RATE_24M, 0x9},
3628 {WLC_RATE_36M, 0xD},
3629 {WLC_RATE_48M, 0x8},
3630 {WLC_RATE_54M, 0xC}
3631 };
3632
8d3d6a69 3633 for (i = 0; i < ARRAY_SIZE(rate_lookup); i++) {
a9533e7e
HP		 3634 if (rate == rate_lookup[i].rate) {
3635 plcp_rate = rate_lookup[i].signal_rate;
3636 break;
3637 }
3638 }
3639
3640 /* Find the SHM pointer to the rate table entry by looking in the
3641 * Direct-map Table
3642 */
90ea2296 3643 return 2 * wlc_bmac_read_shm(wlc_hw, M_RT_DIRMAP_A + (plcp_rate * 2));
a9533e7e
HP		 3644}
3645
41feb5ed 3646void wlc_bmac_band_stf_ss_set(wlc_hw_info_t *wlc_hw, u8 stf_mode)
a9533e7e
HP		 3647{
3648 wlc_hw->hw_stf_ss_opmode = stf_mode;
3649
3650 if (wlc_hw->clk)
3651 wlc_upd_ofdm_pctl1_table(wlc_hw);
3652}
3653
3654void BCMFASTPATH
66cbd3ab
GKH		 3655wlc_bmac_read_tsf(wlc_hw_info_t *wlc_hw, u32 *tsf_l_ptr,
3656 u32 *tsf_h_ptr)
a9533e7e
HP		 3657{
3658 d11regs_t *regs = wlc_hw->regs;
3659
3660 /* read the tsf timer low, then high to get an atomic read */
3661 *tsf_l_ptr = R_REG(wlc_hw->osh, &regs->tsf_timerlow);
3662 *tsf_h_ptr = R_REG(wlc_hw->osh, &regs->tsf_timerhigh);
3663
3664 return;
3665}
3666
0d2f0724 3667bool wlc_bmac_validate_chip_access(wlc_hw_info_t *wlc_hw)
a2627bc0 3668{
a9533e7e 3669 d11regs_t *regs;
66cbd3ab 3670 u32 w, val;
7d4df48e 3671 volatile u16 *reg16;
a9533e7e
HP		 3672 osl_t *osh;
3673
3674 WL_TRACE(("wl%d: validate_chip_access\n", wlc_hw->unit));
3675
3676 regs = wlc_hw->regs;
3677 osh = wlc_hw->osh;
3678
3679 /* Validate dchip register access */
3680
3681 W_REG(osh, &regs->objaddr, OBJADDR_SHM_SEL | 0);
3682 (void)R_REG(osh, &regs->objaddr);
3683 w = R_REG(osh, &regs->objdata);
3684
3685 /* Can we write and read back a 32bit register? */
3686 W_REG(osh, &regs->objaddr, OBJADDR_SHM_SEL | 0);
3687 (void)R_REG(osh, &regs->objaddr);
66cbd3ab 3688 W_REG(osh, &regs->objdata, (u32) 0xaa5555aa);
a9533e7e
HP		 3689
3690 W_REG(osh, &regs->objaddr, OBJADDR_SHM_SEL | 0);
3691 (void)R_REG(osh, &regs->objaddr);
3692 val = R_REG(osh, &regs->objdata);
66cbd3ab 3693 if (val != (u32) 0xaa5555aa) {
a9533e7e 3694 WL_ERROR(("wl%d: validate_chip_access: SHM = 0x%x, expected 0xaa5555aa\n", wlc_hw->unit, val));
0965ae88 3695 return false;
a9533e7e
HP		 3696 }
3697
3698 W_REG(osh, &regs->objaddr, OBJADDR_SHM_SEL | 0);
3699 (void)R_REG(osh, &regs->objaddr);
66cbd3ab 3700 W_REG(osh, &regs->objdata, (u32) 0x55aaaa55);
a9533e7e
HP		 3701
3702 W_REG(osh, &regs->objaddr, OBJADDR_SHM_SEL | 0);
3703 (void)R_REG(osh, &regs->objaddr);
3704 val = R_REG(osh, &regs->objdata);
66cbd3ab 3705 if (val != (u32) 0x55aaaa55) {
a9533e7e 3706 WL_ERROR(("wl%d: validate_chip_access: SHM = 0x%x, expected 0x55aaaa55\n", wlc_hw->unit, val));
0965ae88 3707 return false;
a9533e7e
HP		 3708 }
3709
3710 W_REG(osh, &regs->objaddr, OBJADDR_SHM_SEL | 0);
3711 (void)R_REG(osh, &regs->objaddr);
3712 W_REG(osh, &regs->objdata, w);
3713
3714 if (D11REV_LT(wlc_hw->corerev, 11)) {
3715 /* if 32 bit writes are split into 16 bit writes, are they in the correct order
3716 * for our interface, low to high
3717 */
e88cf8eb 3718 reg16 = (volatile u16 *)&regs->tsf_cfpstart;
a9533e7e
HP		 3719
3720 /* write the CFPStart register low half explicitly, starting a buffered write */
3721 W_REG(osh, reg16, 0xAAAA);
3722
3723 /* Write a 32 bit value to CFPStart to test the 16 bit split order.
3724 * If the low 16 bits are written first, followed by the high 16 bits then the
3725 * 32 bit value 0xCCCCBBBB should end up in the register.
3726 * If the order is reversed, then the write to the high half will trigger a buffered
3727 * write of 0xCCCCAAAA.
3728 * If the bus is 32 bits, then this is not much of a test, and the reg should
3729 * have the correct value 0xCCCCBBBB.
3730 */
3731 W_REG(osh, &regs->tsf_cfpstart, 0xCCCCBBBB);
3732
3733 /* verify with the 16 bit registers that have no side effects */
3734 val = R_REG(osh, &regs->tsf_cfpstrt_l);
3735 if (val != (uint) 0xBBBB) {
3736 WL_ERROR(("wl%d: validate_chip_access: tsf_cfpstrt_l = 0x%x, expected" " 0x%x\n", wlc_hw->unit, val, 0xBBBB));
0965ae88 3737 return false;
a9533e7e
HP		 3738 }
3739 val = R_REG(osh, &regs->tsf_cfpstrt_h);
3740 if (val != (uint) 0xCCCC) {
3741 WL_ERROR(("wl%d: validate_chip_access: tsf_cfpstrt_h = 0x%x, expected" " 0x%x\n", wlc_hw->unit, val, 0xCCCC));
0965ae88 3742 return false;
a9533e7e
HP		 3743 }
3744
3745 }
3746
3747 /* clear CFPStart */
3748 W_REG(osh, &regs->tsf_cfpstart, 0);
3749
3750 w = R_REG(osh, &regs->maccontrol);
3751 if ((w != (MCTL_IHR_EN | MCTL_WAKE)) &&
3752 (w != (MCTL_IHR_EN | MCTL_GMODE | MCTL_WAKE))) {
3753 WL_ERROR(("wl%d: validate_chip_access: maccontrol = 0x%x, expected 0x%x or 0x%x\n", wlc_hw->unit, w, (MCTL_IHR_EN | MCTL_WAKE), (MCTL_IHR_EN | MCTL_GMODE | MCTL_WAKE)));
0965ae88 3754 return false;
a9533e7e
HP		 3755 }
3756
0f0881b0 3757 return true;
a9533e7e
HP		 3758}
3759
3760#define PHYPLL_WAIT_US 100000
3761
7cc4a4c0 3762void wlc_bmac_core_phypll_ctl(wlc_hw_info_t *wlc_hw, bool on)
a9533e7e
HP		 3763{
3764 d11regs_t *regs;
3765 osl_t *osh;
66cbd3ab 3766 u32 tmp;
a9533e7e
HP		 3767
3768 WL_TRACE(("wl%d: wlc_bmac_core_phypll_ctl\n", wlc_hw->unit));
3769
3770 tmp = 0;
3771 regs = wlc_hw->regs;
3772 osh = wlc_hw->osh;
3773
3774 if (D11REV_LE(wlc_hw->corerev, 16) || D11REV_IS(wlc_hw->corerev, 20))
3775 return;
3776
3777 if (on) {
3778 if ((wlc_hw->sih->chip == BCM4313_CHIP_ID)) {
3779 OR_REG(osh, &regs->clk_ctl_st,
3780 (CCS_ERSRC_REQ_HT | CCS_ERSRC_REQ_D11PLL |
3781 CCS_ERSRC_REQ_PHYPLL));
3782 SPINWAIT((R_REG(osh, &regs->clk_ctl_st) &
3783 (CCS_ERSRC_AVAIL_HT)) != (CCS_ERSRC_AVAIL_HT),
3784 PHYPLL_WAIT_US);
3785
3786 tmp = R_REG(osh, &regs->clk_ctl_st);
3787 if ((tmp & (CCS_ERSRC_AVAIL_HT)) !=
3788 (CCS_ERSRC_AVAIL_HT)) {
3789 WL_ERROR(("%s: turn on PHY PLL failed\n",
3790 __func__));
3791 ASSERT(0);
3792 }
3793 } else {
3794 OR_REG(osh, &regs->clk_ctl_st,
3795 (CCS_ERSRC_REQ_D11PLL | CCS_ERSRC_REQ_PHYPLL));
3796 SPINWAIT((R_REG(osh, &regs->clk_ctl_st) &
3797 (CCS_ERSRC_AVAIL_D11PLL |
3798 CCS_ERSRC_AVAIL_PHYPLL)) !=
3799 (CCS_ERSRC_AVAIL_D11PLL |
3800 CCS_ERSRC_AVAIL_PHYPLL), PHYPLL_WAIT_US);
3801
3802 tmp = R_REG(osh, &regs->clk_ctl_st);
3803 if ((tmp &
3804 (CCS_ERSRC_AVAIL_D11PLL | CCS_ERSRC_AVAIL_PHYPLL))
3805 !=
3806 (CCS_ERSRC_AVAIL_D11PLL | CCS_ERSRC_AVAIL_PHYPLL)) {
3807 WL_ERROR(("%s: turn on PHY PLL failed\n",
3808 __func__));
3809 ASSERT(0);
3810 }
3811 }
3812 } else {
3813 /* Since the PLL may be shared, other cores can still be requesting it;
3814 * so we'll deassert the request but not wait for status to comply.
3815 */
3816 AND_REG(osh, &regs->clk_ctl_st, ~CCS_ERSRC_REQ_PHYPLL);
3817 tmp = R_REG(osh, &regs->clk_ctl_st);
3818 }
3819}
3820
7cc4a4c0 3821void wlc_coredisable(wlc_hw_info_t *wlc_hw)
a9533e7e
HP		 3822{
3823 bool dev_gone;
3824
3825 WL_TRACE(("wl%d: %s\n", wlc_hw->unit, __func__));
3826
3827 ASSERT(!wlc_hw->up);
3828
3829 dev_gone = DEVICEREMOVED(wlc_hw->wlc);
3830
3831 if (dev_gone)
3832 return;
3833
3834 if (wlc_hw->noreset)
3835 return;
3836
3837 /* radio off */
3838 wlc_phy_switch_radio(wlc_hw->band->pi, OFF);
3839
3840 /* turn off analog core */
3841 wlc_phy_anacore(wlc_hw->band->pi, OFF);
3842
3843 /* turn off PHYPLL to save power */
0965ae88 3844 wlc_bmac_core_phypll_ctl(wlc_hw, false);
a9533e7e
HP		 3845
3846 /* No need to set wlc->pub->radio_active = OFF
3847 * because this function needs down capability and
3848 * radio_active is designed for BCMNODOWN.
3849 */
3850
3851 /* remove gpio controls */
3852 if (wlc_hw->ucode_dbgsel)
3853 si_gpiocontrol(wlc_hw->sih, ~0, 0, GPIO_DRV_PRIORITY);
3854
0965ae88 3855 wlc_hw->clk = false;
a9533e7e 3856 si_core_disable(wlc_hw->sih, 0);
0965ae88 3857 wlc_phy_hw_clk_state_upd(wlc_hw->band->pi, false);
a9533e7e
HP		 3858}
3859
3860/* power both the pll and external oscillator on/off */
7cc4a4c0 3861void wlc_bmac_xtal(wlc_hw_info_t *wlc_hw, bool want)
a9533e7e
HP		 3862{
3863 WL_TRACE(("wl%d: wlc_bmac_xtal: want %d\n", wlc_hw->unit, want));
3864
3865 /* dont power down if plldown is false or we must poll hw radio disable */
3866 if (!want && wlc_hw->pllreq)
3867 return;
3868
3869 if (wlc_hw->sih)
3870 si_clkctl_xtal(wlc_hw->sih, XTAL | PLL, want);
3871
3872 wlc_hw->sbclk = want;
3873 if (!wlc_hw->sbclk) {
0965ae88 3874 wlc_hw->clk = false;
a9533e7e 3875 if (wlc_hw->band && wlc_hw->band->pi)
0965ae88 3876 wlc_phy_hw_clk_state_upd(wlc_hw->band->pi, false);
a9533e7e
HP		 3877 }
3878}
3879
7cc4a4c0 3880static void wlc_flushqueues(wlc_info_t *wlc)
a9533e7e
HP		 3881{
3882 wlc_hw_info_t *wlc_hw = wlc->hw;
3883 uint i;
3884
3885 wlc->txpend16165war = 0;
3886
3887 /* free any posted tx packets */
3888 for (i = 0; i < NFIFO; i++)
3889 if (wlc_hw->di[i]) {
3890 dma_txreclaim(wlc_hw->di[i], HNDDMA_RANGE_ALL);
3891 TXPKTPENDCLR(wlc, i);
3892 WL_TRACE(("wlc_flushqueues: pktpend fifo %d cleared\n",
3893 i));
3894 }
3895
3896 /* free any posted rx packets */
3897 dma_rxreclaim(wlc_hw->di[RX_FIFO]);
3898 if (D11REV_IS(wlc_hw->corerev, 4))
3899 dma_rxreclaim(wlc_hw->di[RX_TXSTATUS_FIFO]);
3900}
3901
7d4df48e 3902u16 wlc_bmac_read_shm(wlc_hw_info_t *wlc_hw, uint offset)
a9533e7e
HP		 3903{
3904 return wlc_bmac_read_objmem(wlc_hw, offset, OBJADDR_SHM_SEL);
3905}
3906
7d4df48e 3907void wlc_bmac_write_shm(wlc_hw_info_t *wlc_hw, uint offset, u16 v)
a9533e7e
HP		 3908{
3909 wlc_bmac_write_objmem(wlc_hw, offset, v, OBJADDR_SHM_SEL);
3910}
3911
3912/* Set a range of shared memory to a value.
3913 * SHM 'offset' needs to be an even address and
3914 * Buffer length 'len' must be an even number of bytes
3915 */
7d4df48e 3916void wlc_bmac_set_shm(wlc_hw_info_t *wlc_hw, uint offset, u16 v, int len)
a9533e7e
HP		 3917{
3918 int i;
3919
3920 /* offset and len need to be even */
3921 ASSERT((offset & 1) == 0);
3922 ASSERT((len & 1) == 0);
3923
3924 if (len <= 0)
3925 return;
3926
3927 for (i = 0; i < len; i += 2) {
3928 wlc_bmac_write_objmem(wlc_hw, offset + i, v, OBJADDR_SHM_SEL);
3929 }
3930}
3931
7d4df48e 3932static u16
66cbd3ab 3933wlc_bmac_read_objmem(wlc_hw_info_t *wlc_hw, uint offset, u32 sel)
a9533e7e
HP		 3934{
3935 d11regs_t *regs = wlc_hw->regs;
e88cf8eb 3936 volatile u16 *objdata_lo = (volatile u16 *)&regs->objdata;
7d4df48e
GKH		 3937 volatile u16 *objdata_hi = objdata_lo + 1;
3938 u16 v;
a9533e7e
HP		 3939
3940 ASSERT((offset & 1) == 0);
3941
3942 W_REG(wlc_hw->osh, &regs->objaddr, sel | (offset >> 2));
3943 (void)R_REG(wlc_hw->osh, &regs->objaddr);
3944 if (offset & 2) {
3945 v = R_REG(wlc_hw->osh, objdata_hi);
3946 } else {
3947 v = R_REG(wlc_hw->osh, objdata_lo);
3948 }
3949
3950 return v;
3951}
3952
3953static void
66cbd3ab 3954wlc_bmac_write_objmem(wlc_hw_info_t *wlc_hw, uint offset, u16 v, u32 sel)
a9533e7e
HP		 3955{
3956 d11regs_t *regs = wlc_hw->regs;
e88cf8eb 3957 volatile u16 *objdata_lo = (volatile u16 *)&regs->objdata;
7d4df48e 3958 volatile u16 *objdata_hi = objdata_lo + 1;
a9533e7e
HP		 3959
3960 ASSERT((offset & 1) == 0);
3961
3962 W_REG(wlc_hw->osh, &regs->objaddr, sel | (offset >> 2));
3963 (void)R_REG(wlc_hw->osh, &regs->objaddr);
3964 if (offset & 2) {
3965 W_REG(wlc_hw->osh, objdata_hi, v);
3966 } else {
3967 W_REG(wlc_hw->osh, objdata_lo, v);
3968 }
3969}
3970
3971/* Copy a buffer to shared memory of specified type .
3972 * SHM 'offset' needs to be an even address and
3973 * Buffer length 'len' must be an even number of bytes
3974 * 'sel' selects the type of memory
3975 */
3976void
7cc4a4c0 3977wlc_bmac_copyto_objmem(wlc_hw_info_t *wlc_hw, uint offset, const void *buf,
66cbd3ab 3978 int len, u32 sel)
a9533e7e 3979{
7d4df48e 3980 u16 v;
41feb5ed 3981 const u8 *p = (const u8 *)buf;
a9533e7e
HP		 3982 int i;
3983
3984 /* offset and len need to be even */
3985 ASSERT((offset & 1) == 0);
3986 ASSERT((len & 1) == 0);
3987
3988 if (len <= 0)
3989 return;
3990
3991 for (i = 0; i < len; i += 2) {
3992 v = p[i] | (p[i + 1] << 8);
3993 wlc_bmac_write_objmem(wlc_hw, offset + i, v, sel);
3994 }
3995}
3996
3997/* Copy a piece of shared memory of specified type to a buffer .
3998 * SHM 'offset' needs to be an even address and
3999 * Buffer length 'len' must be an even number of bytes
4000 * 'sel' selects the type of memory
4001 */
4002void
7cc4a4c0 4003wlc_bmac_copyfrom_objmem(wlc_hw_info_t *wlc_hw, uint offset, void *buf,
66cbd3ab 4004 int len, u32 sel)
a9533e7e 4005{
7d4df48e 4006 u16 v;
41feb5ed 4007 u8 *p = (u8 *) buf;
a9533e7e
HP		 4008 int i;
4009
4010 /* offset and len need to be even */
4011 ASSERT((offset & 1) == 0);
4012 ASSERT((len & 1) == 0);
4013
4014 if (len <= 0)
4015 return;
4016
4017 for (i = 0; i < len; i += 2) {
4018 v = wlc_bmac_read_objmem(wlc_hw, offset + i, sel);
4019 p[i] = v & 0xFF;
4020 p[i + 1] = (v >> 8) & 0xFF;
4021 }
4022}
4023
7cc4a4c0 4024void wlc_bmac_copyfrom_vars(wlc_hw_info_t *wlc_hw, char **buf, uint *len)
a9533e7e
HP		 4025{
4026 WL_TRACE(("wlc_bmac_copyfrom_vars, nvram vars totlen=%d\n",
4027 wlc_hw->vars_size));
4028
4029 *buf = wlc_hw->vars;
4030 *len = wlc_hw->vars_size;
4031}
4032
7d4df48e 4033void wlc_bmac_retrylimit_upd(wlc_hw_info_t *wlc_hw, u16 SRL, u16 LRL)
a9533e7e
HP		 4034{
4035 wlc_hw->SRL = SRL;
4036 wlc_hw->LRL = LRL;
4037
4038 /* write retry limit to SCR, shouldn't need to suspend */
4039 if (wlc_hw->up) {
4040 W_REG(wlc_hw->osh, &wlc_hw->regs->objaddr,
4041 OBJADDR_SCR_SEL | S_DOT11_SRC_LMT);
4042 (void)R_REG(wlc_hw->osh, &wlc_hw->regs->objaddr);
4043 W_REG(wlc_hw->osh, &wlc_hw->regs->objdata, wlc_hw->SRL);
4044 W_REG(wlc_hw->osh, &wlc_hw->regs->objaddr,
4045 OBJADDR_SCR_SEL | S_DOT11_LRC_LMT);
4046 (void)R_REG(wlc_hw->osh, &wlc_hw->regs->objaddr);
4047 W_REG(wlc_hw->osh, &wlc_hw->regs->objdata, wlc_hw->LRL);
4048 }
4049}
4050
7cc4a4c0 4051void wlc_bmac_set_noreset(wlc_hw_info_t *wlc_hw, bool noreset_flag)
a9533e7e
HP		 4052{
4053 wlc_hw->noreset = noreset_flag;
4054}
4055
7cc4a4c0 4056void wlc_bmac_set_ucode_loaded(wlc_hw_info_t *wlc_hw, bool ucode_loaded)
a9533e7e
HP		 4057{
4058 wlc_hw->ucode_loaded = ucode_loaded;
4059}
4060
7cc4a4c0 4061void wlc_bmac_pllreq(wlc_hw_info_t *wlc_hw, bool set, mbool req_bit)
a9533e7e
HP		 4062{
4063 ASSERT(req_bit);
4064
4065 if (set) {
4066 if (mboolisset(wlc_hw->pllreq, req_bit))
4067 return;
4068
4069 mboolset(wlc_hw->pllreq, req_bit);
4070
4071 if (mboolisset(wlc_hw->pllreq, WLC_PLLREQ_FLIP)) {
4072 if (!wlc_hw->sbclk) {
4073 wlc_bmac_xtal(wlc_hw, ON);
4074 }
4075 }
4076 } else {
4077 if (!mboolisset(wlc_hw->pllreq, req_bit))
4078 return;
4079
4080 mboolclr(wlc_hw->pllreq, req_bit);
4081
4082 if (mboolisset(wlc_hw->pllreq, WLC_PLLREQ_FLIP)) {
4083 if (wlc_hw->sbclk) {
4084 wlc_bmac_xtal(wlc_hw, OFF);
4085 }
4086 }
4087 }
4088
4089 return;
4090}
4091
7cc4a4c0 4092void wlc_bmac_set_clk(wlc_hw_info_t *wlc_hw, bool on)
a9533e7e
HP		 4093{
4094 if (on) {
4095 /* power up pll and oscillator */
4096 wlc_bmac_xtal(wlc_hw, ON);
4097
4098 /* enable core(s), ignore bandlocked
4099 * Leave with the same band selected as we entered
4100 */
4101 wlc_bmac_corereset(wlc_hw, WLC_USE_COREFLAGS);
4102 } else {
4103 /* if already down, must skip the core disable */
4104 if (wlc_hw->clk) {
4105 /* disable core(s), ignore bandlocked */
4106 wlc_coredisable(wlc_hw);
4107 }
4108 /* power down pll and oscillator */
4109 wlc_bmac_xtal(wlc_hw, OFF);
4110 }
4111}
4112
4113/* this will be true for all ai chips */
7cc4a4c0 4114bool wlc_bmac_taclear(wlc_hw_info_t *wlc_hw, bool ta_ok)
a9533e7e 4115{
0f0881b0 4116 return true;
a9533e7e
HP		 4117}
4118
4119/* Lower down relevant GPIOs like LED when going down w/o
4120 * doing PCI config cycles or touching interrupts
4121 */
7cc4a4c0 4122void wlc_gpio_fast_deinit(wlc_hw_info_t *wlc_hw)
a9533e7e
HP		 4123{
4124 if ((wlc_hw == NULL) || (wlc_hw->sih == NULL))
4125 return;
4126
4127 /* Only chips with internal bus or PCIE cores or certain PCI cores
4128 * are able to switch cores w/o disabling interrupts
4129 */
4130 if (!((BUSTYPE(wlc_hw->sih->bustype) == SI_BUS) ||
4131 ((BUSTYPE(wlc_hw->sih->bustype) == PCI_BUS) &&
4132 ((wlc_hw->sih->buscoretype == PCIE_CORE_ID) ||
4133 (wlc_hw->sih->buscorerev >= 13)))))
4134 return;
4135
4136 WL_TRACE(("wl%d: %s\n", wlc_hw->unit, __func__));
4137 return;
4138}
4139
7cc4a4c0 4140bool wlc_bmac_radio_hw(wlc_hw_info_t *wlc_hw, bool enable)
a9533e7e
HP		 4141{
4142 /* Do not access Phy registers if core is not up */
0965ae88
GKH		 4143 if (si_iscoreup(wlc_hw->sih) == false)
4144 return false;
a9533e7e
HP		 4145
4146 if (enable) {
4147 if (PMUCTL_ENAB(wlc_hw->sih)) {
4148 AND_REG(wlc_hw->osh, &wlc_hw->regs->clk_ctl_st,
4149 ~CCS_FORCEHWREQOFF);
0f0881b0 4150 si_pmu_radio_enable(wlc_hw->sih, true);
a9533e7e
HP		 4151 }
4152
4153 wlc_phy_anacore(wlc_hw->band->pi, ON);
4154 wlc_phy_switch_radio(wlc_hw->band->pi, ON);
4155
4156 /* resume d11 core */
4157 wlc_enable_mac(wlc_hw->wlc);
4158 } else {
4159 /* suspend d11 core */
4160 wlc_suspend_mac_and_wait(wlc_hw->wlc);
4161
4162 wlc_phy_switch_radio(wlc_hw->band->pi, OFF);
4163 wlc_phy_anacore(wlc_hw->band->pi, OFF);
4164
4165 if (PMUCTL_ENAB(wlc_hw->sih)) {
0965ae88 4166 si_pmu_radio_enable(wlc_hw->sih, false);
a9533e7e
HP		 4167 OR_REG(wlc_hw->osh, &wlc_hw->regs->clk_ctl_st,
4168 CCS_FORCEHWREQOFF);
4169 }
4170 }
4171
0f0881b0 4172 return true;
a9533e7e
HP		 4173}
4174
7d4df48e 4175u16 wlc_bmac_rate_shm_offset(wlc_hw_info_t *wlc_hw, u8 rate)
a9533e7e 4176{
7d4df48e 4177 u16 table_ptr;
41feb5ed 4178 u8 phy_rate, index;
a9533e7e
HP		 4179
4180 /* get the phy specific rate encoding for the PLCP SIGNAL field */
4181 /* XXX4321 fixup needed ? */
4182 if (IS_OFDM(rate))
4183 table_ptr = M_RT_DIRMAP_A;
4184 else
4185 table_ptr = M_RT_DIRMAP_B;
4186
4187 /* for a given rate, the LS-nibble of the PLCP SIGNAL field is
4188 * the index into the rate table.
4189 */
4190 phy_rate = rate_info[rate] & RATE_MASK;
4191 index = phy_rate & 0xf;
4192
4193 /* Find the SHM pointer to the rate table entry by looking in the
4194 * Direct-map Table
4195 */
90ea2296 4196 return 2 * wlc_bmac_read_shm(wlc_hw, table_ptr + (index * 2));
a9533e7e
HP		 4197}
4198
41feb5ed 4199void wlc_bmac_set_txpwr_percent(wlc_hw_info_t *wlc_hw, u8 val)
a9533e7e
HP		 4200{
4201 wlc_phy_txpwr_percent_set(wlc_hw->band->pi, val);
4202}
4203
66cbd3ab 4204void wlc_bmac_antsel_set(wlc_hw_info_t *wlc_hw, u32 antsel_avail)
a9533e7e
HP		 4205{
4206 wlc_hw->antsel_avail = antsel_avail;
4207}
Linux kernel - Deliverables
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