Commit | Line | Data |
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a9533e7e HP |
1 | /* |
2 | * Copyright (c) 2010 Broadcom Corporation | |
3 | * | |
4 | * Permission to use, copy, modify, and/or distribute this software for any | |
5 | * purpose with or without fee is hereby granted, provided that the above | |
6 | * copyright notice and this permission notice appear in all copies. | |
7 | * | |
8 | * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | |
9 | * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | |
10 | * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY | |
11 | * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | |
12 | * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION | |
13 | * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN | |
14 | * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | |
15 | */ | |
16 | ||
01d11441 | 17 | #include <linux/delay.h> |
3327989a BR |
18 | #include <linux/kernel.h> |
19 | #include <linux/string.h> | |
a1c16ed2 GKH |
20 | #include <bcmdefs.h> |
21 | #include <osl.h> | |
c6ac24e9 BR |
22 | #include <linux/module.h> |
23 | #include <linux/pci.h> | |
a9533e7e HP |
24 | #include <bcmutils.h> |
25 | #include <siutils.h> | |
26 | #include <bcmdevs.h> | |
27 | #include <hndsoc.h> | |
28 | #include <sbchipc.h> | |
29 | #include <pci_core.h> | |
30 | #include <pcie_core.h> | |
31 | #include <nicpci.h> | |
32 | #include <bcmnvram.h> | |
33 | #include <bcmsrom.h> | |
a9533e7e HP |
34 | #include <pcicfg.h> |
35 | #include <sbsocram.h> | |
36 | #ifdef BCMSDIO | |
37 | #include <bcmsdh.h> | |
38 | #include <sdio.h> | |
39 | #include <sbsdio.h> | |
40 | #include <sbhnddma.h> | |
41 | #include <sbsdpcmdev.h> | |
42 | #include <bcmsdpcm.h> | |
43 | #endif /* BCMSDIO */ | |
44 | #include <hndpmu.h> | |
45 | ||
46 | /* this file now contains only definitions for sb functions, only necessary | |
47 | *for devices using Sonics backplanes (bcm4329) | |
48 | */ | |
49 | ||
50 | /* if an amba SDIO device is supported, please further restrict the inclusion | |
51 | * of this file | |
52 | */ | |
53 | #ifdef BCMSDIO | |
54 | #include "siutils_priv.h" | |
55 | #endif | |
56 | ||
57 | /* local prototypes */ | |
26bcc181 AS |
58 | static si_info_t *si_doattach(si_info_t *sii, uint devid, void *regs, |
59 | uint bustype, void *sdh, char **vars, | |
7cc4a4c0 JC |
60 | uint *varsz); |
61 | static bool si_buscore_prep(si_info_t *sii, uint bustype, uint devid, | |
a9533e7e | 62 | void *sdh); |
7cc4a4c0 | 63 | static bool si_buscore_setup(si_info_t *sii, chipcregs_t *cc, uint bustype, |
66cbd3ab | 64 | u32 savewin, uint *origidx, void *regs); |
7cc4a4c0 | 65 | static void si_nvram_process(si_info_t *sii, char *pvars); |
a9533e7e HP |
66 | |
67 | /* dev path concatenation util */ | |
7cc4a4c0 JC |
68 | static char *si_devpathvar(si_t *sih, char *var, int len, const char *name); |
69 | static bool _si_clkctl_cc(si_info_t *sii, uint mode); | |
70 | static bool si_ispcie(si_info_t *sii); | |
b4f790ee | 71 | static uint socram_banksize(si_info_t *sii, sbsocramregs_t *r, |
36ef9a1e | 72 | u8 idx, u8 mtype); |
a9533e7e HP |
73 | |
74 | /* global variable to indicate reservation/release of gpio's */ | |
66cbd3ab | 75 | static u32 si_gpioreservation; |
a9533e7e | 76 | |
a9533e7e HP |
77 | /* |
78 | * Allocate a si handle. | |
79 | * devid - pci device id (used to determine chip#) | |
80 | * osh - opaque OS handle | |
81 | * regs - virtual address of initial core registers | |
82 | * bustype - pci/sb/sdio/etc | |
83 | * vars - pointer to a pointer area for "environment" variables | |
84 | * varsz - pointer to int to return the size of the vars | |
85 | */ | |
26bcc181 | 86 | si_t *si_attach(uint devid, void *regs, uint bustype, |
e69284f2 | 87 | void *sdh, char **vars, uint *varsz) |
0d2f0724 | 88 | { |
a9533e7e HP |
89 | si_info_t *sii; |
90 | ||
91 | /* alloc si_info_t */ | |
5fcc1fcb | 92 | sii = kmalloc(sizeof(si_info_t), GFP_ATOMIC); |
ca8c1e59 | 93 | if (sii == NULL) { |
97e17d0e | 94 | SI_ERROR(("si_attach: malloc failed!\n")); |
90ea2296 | 95 | return NULL; |
a9533e7e HP |
96 | } |
97 | ||
26bcc181 | 98 | if (si_doattach(sii, devid, regs, bustype, sdh, vars, varsz) == |
a9533e7e | 99 | NULL) { |
182acb3c | 100 | kfree(sii); |
90ea2296 | 101 | return NULL; |
a9533e7e HP |
102 | } |
103 | sii->vars = vars ? *vars : NULL; | |
104 | sii->varsz = varsz ? *varsz : 0; | |
105 | ||
106 | return (si_t *) sii; | |
107 | } | |
108 | ||
109 | /* global kernel resource */ | |
110 | static si_info_t ksii; | |
111 | ||
0d2f0724 GKH |
112 | static bool si_buscore_prep(si_info_t *sii, uint bustype, uint devid, |
113 | void *sdh) | |
114 | { | |
a9533e7e | 115 | |
cf2b4488 | 116 | #ifndef BRCM_FULLMAC |
a9533e7e | 117 | /* kludge to enable the clock on the 4306 which lacks a slowclock */ |
fa7a1db2 | 118 | if (bustype == PCI_BUS && !si_ispcie(sii)) |
a9533e7e | 119 | si_clkctl_xtal(&sii->pub, XTAL | PLL, ON); |
cf2b4488 | 120 | #endif |
a9533e7e HP |
121 | |
122 | #if defined(BCMSDIO) | |
fa7a1db2 | 123 | if (bustype == SDIO_BUS) { |
a9533e7e | 124 | int err; |
36ef9a1e | 125 | u8 clkset; |
a9533e7e HP |
126 | |
127 | /* Try forcing SDIO core to do ALPAvail request only */ | |
128 | clkset = SBSDIO_FORCE_HW_CLKREQ_OFF | SBSDIO_ALP_AVAIL_REQ; | |
129 | bcmsdh_cfg_write(sdh, SDIO_FUNC_1, SBSDIO_FUNC1_CHIPCLKCSR, | |
130 | clkset, &err); | |
131 | if (!err) { | |
36ef9a1e | 132 | u8 clkval; |
a9533e7e HP |
133 | |
134 | /* If register supported, wait for ALPAvail and then force ALP */ | |
135 | clkval = | |
136 | bcmsdh_cfg_read(sdh, SDIO_FUNC_1, | |
137 | SBSDIO_FUNC1_CHIPCLKCSR, NULL); | |
138 | if ((clkval & ~SBSDIO_AVBITS) == clkset) { | |
139 | SPINWAIT(((clkval = | |
140 | bcmsdh_cfg_read(sdh, SDIO_FUNC_1, | |
141 | SBSDIO_FUNC1_CHIPCLKCSR, | |
142 | NULL)), | |
143 | !SBSDIO_ALPAV(clkval)), | |
144 | PMU_MAX_TRANSITION_DLY); | |
145 | if (!SBSDIO_ALPAV(clkval)) { | |
146 | SI_ERROR(("timeout on ALPAV wait, clkval 0x%02x\n", clkval)); | |
0965ae88 | 147 | return false; |
a9533e7e HP |
148 | } |
149 | clkset = | |
150 | SBSDIO_FORCE_HW_CLKREQ_OFF | | |
151 | SBSDIO_FORCE_ALP; | |
152 | bcmsdh_cfg_write(sdh, SDIO_FUNC_1, | |
153 | SBSDIO_FUNC1_CHIPCLKCSR, | |
154 | clkset, &err); | |
7383141b | 155 | udelay(65); |
a9533e7e HP |
156 | } |
157 | } | |
158 | ||
159 | /* Also, disable the extra SDIO pull-ups */ | |
160 | bcmsdh_cfg_write(sdh, SDIO_FUNC_1, SBSDIO_FUNC1_SDIOPULLUP, 0, | |
161 | NULL); | |
162 | } | |
163 | #endif /* defined(BCMSDIO) */ | |
164 | ||
0f0881b0 | 165 | return true; |
a9533e7e HP |
166 | } |
167 | ||
0d2f0724 GKH |
168 | static bool si_buscore_setup(si_info_t *sii, chipcregs_t *cc, uint bustype, |
169 | u32 savewin, uint *origidx, void *regs) | |
170 | { | |
a9533e7e HP |
171 | bool pci, pcie; |
172 | uint i; | |
173 | uint pciidx, pcieidx, pcirev, pcierev; | |
174 | ||
175 | cc = si_setcoreidx(&sii->pub, SI_CC_IDX); | |
c03b63c1 | 176 | ASSERT(cc); |
a9533e7e HP |
177 | |
178 | /* get chipcommon rev */ | |
179 | sii->pub.ccrev = (int)si_corerev(&sii->pub); | |
180 | ||
181 | /* get chipcommon chipstatus */ | |
182 | if (sii->pub.ccrev >= 11) | |
ff31c54c | 183 | sii->pub.chipst = R_REG(&cc->chipstatus); |
a9533e7e HP |
184 | |
185 | /* get chipcommon capabilites */ | |
ff31c54c | 186 | sii->pub.cccaps = R_REG(&cc->capabilities); |
a9533e7e HP |
187 | /* get chipcommon extended capabilities */ |
188 | ||
cf2b4488 | 189 | #ifndef BRCM_FULLMAC |
a9533e7e | 190 | if (sii->pub.ccrev >= 35) |
ff31c54c | 191 | sii->pub.cccaps_ext = R_REG(&cc->capabilities_ext); |
cf2b4488 | 192 | #endif |
a9533e7e HP |
193 | /* get pmu rev and caps */ |
194 | if (sii->pub.cccaps & CC_CAP_PMU) { | |
ff31c54c | 195 | sii->pub.pmucaps = R_REG(&cc->pmucapabilities); |
a9533e7e HP |
196 | sii->pub.pmurev = sii->pub.pmucaps & PCAP_REV_MASK; |
197 | } | |
198 | ||
199 | /* | |
200 | SI_MSG(("Chipc: rev %d, caps 0x%x, chipst 0x%x pmurev %d, pmucaps 0x%x\n", | |
201 | sii->pub.ccrev, sii->pub.cccaps, sii->pub.chipst, sii->pub.pmurev, | |
202 | sii->pub.pmucaps)); | |
203 | */ | |
204 | ||
205 | /* figure out bus/orignal core idx */ | |
206 | sii->pub.buscoretype = NODEV_CORE_ID; | |
207 | sii->pub.buscorerev = NOREV; | |
208 | sii->pub.buscoreidx = BADIDX; | |
209 | ||
0965ae88 | 210 | pci = pcie = false; |
a9533e7e HP |
211 | pcirev = pcierev = NOREV; |
212 | pciidx = pcieidx = BADIDX; | |
213 | ||
214 | for (i = 0; i < sii->numcores; i++) { | |
215 | uint cid, crev; | |
216 | ||
217 | si_setcoreidx(&sii->pub, i); | |
218 | cid = si_coreid(&sii->pub); | |
219 | crev = si_corerev(&sii->pub); | |
220 | ||
221 | /* Display cores found */ | |
222 | SI_VMSG(("CORE[%d]: id 0x%x rev %d base 0x%x regs 0x%p\n", | |
223 | i, cid, crev, sii->coresba[i], sii->regs[i])); | |
224 | ||
fa7a1db2 | 225 | if (bustype == PCI_BUS) { |
a9533e7e HP |
226 | if (cid == PCI_CORE_ID) { |
227 | pciidx = i; | |
228 | pcirev = crev; | |
0f0881b0 | 229 | pci = true; |
a9533e7e HP |
230 | } else if (cid == PCIE_CORE_ID) { |
231 | pcieidx = i; | |
232 | pcierev = crev; | |
0f0881b0 | 233 | pcie = true; |
a9533e7e HP |
234 | } |
235 | } | |
236 | #ifdef BCMSDIO | |
fa7a1db2 BR |
237 | else if (((bustype == SDIO_BUS) || |
238 | (bustype == SPI_BUS)) && | |
a9533e7e HP |
239 | ((cid == PCMCIA_CORE_ID) || (cid == SDIOD_CORE_ID))) { |
240 | sii->pub.buscorerev = crev; | |
241 | sii->pub.buscoretype = cid; | |
242 | sii->pub.buscoreidx = i; | |
243 | } | |
244 | #endif /* BCMSDIO */ | |
245 | ||
246 | /* find the core idx before entering this func. */ | |
247 | if ((savewin && (savewin == sii->coresba[i])) || | |
248 | (regs == sii->regs[i])) | |
249 | *origidx = i; | |
250 | } | |
251 | ||
cf2b4488 HP |
252 | #ifdef BRCM_FULLMAC |
253 | SI_MSG(("Buscore id/type/rev %d/0x%x/%d\n", sii->pub.buscoreidx, | |
254 | sii->pub.buscoretype, sii->pub.buscorerev)); | |
255 | ||
256 | /* Make sure any on-chip ARM is off (in case strapping is wrong), | |
257 | * or downloaded code was | |
258 | * already running. | |
259 | */ | |
fa7a1db2 | 260 | if ((bustype == SDIO_BUS) || (bustype == SPI_BUS)) { |
cf2b4488 HP |
261 | if (si_setcore(&sii->pub, ARM7S_CORE_ID, 0) || |
262 | si_setcore(&sii->pub, ARMCM3_CORE_ID, 0)) | |
263 | si_core_disable(&sii->pub, 0); | |
264 | } | |
265 | #else | |
a9533e7e HP |
266 | if (pci && pcie) { |
267 | if (si_ispcie(sii)) | |
0965ae88 | 268 | pci = false; |
a9533e7e | 269 | else |
0965ae88 | 270 | pcie = false; |
a9533e7e HP |
271 | } |
272 | if (pci) { | |
273 | sii->pub.buscoretype = PCI_CORE_ID; | |
274 | sii->pub.buscorerev = pcirev; | |
275 | sii->pub.buscoreidx = pciidx; | |
276 | } else if (pcie) { | |
277 | sii->pub.buscoretype = PCIE_CORE_ID; | |
278 | sii->pub.buscorerev = pcierev; | |
279 | sii->pub.buscoreidx = pcieidx; | |
280 | } | |
281 | ||
282 | SI_VMSG(("Buscore id/type/rev %d/0x%x/%d\n", sii->pub.buscoreidx, | |
283 | sii->pub.buscoretype, sii->pub.buscorerev)); | |
284 | ||
285 | /* fixup necessary chip/core configurations */ | |
fa7a1db2 | 286 | if (sii->pub.bustype == PCI_BUS) { |
a9533e7e | 287 | if (SI_FAST(sii)) { |
ca8c1e59 | 288 | if (!sii->pch) { |
c03b63c1 | 289 | sii->pch = (void *)pcicore_init( |
26bcc181 | 290 | &sii->pub, sii->pbus, |
ca8c1e59 JC |
291 | (void *)PCIEREGS(sii)); |
292 | if (sii->pch == NULL) | |
0965ae88 | 293 | return false; |
ca8c1e59 | 294 | } |
a9533e7e HP |
295 | } |
296 | if (si_pci_fixcfg(&sii->pub)) { | |
297 | SI_ERROR(("si_doattach: sb_pci_fixcfg failed\n")); | |
0965ae88 | 298 | return false; |
a9533e7e HP |
299 | } |
300 | } | |
cf2b4488 | 301 | #endif |
a9533e7e HP |
302 | /* return to the original core */ |
303 | si_setcoreidx(&sii->pub, *origidx); | |
304 | ||
0f0881b0 | 305 | return true; |
a9533e7e HP |
306 | } |
307 | ||
0d2f0724 | 308 | static __used void si_nvram_process(si_info_t *sii, char *pvars) |
a2627bc0 | 309 | { |
a9533e7e HP |
310 | uint w = 0; |
311 | ||
312 | /* get boardtype and boardrev */ | |
fa7a1db2 | 313 | switch (sii->pub.bustype) { |
a9533e7e HP |
314 | case PCI_BUS: |
315 | /* do a pci config read to get subsystem id and subvendor id */ | |
06d278c5 | 316 | pci_read_config_dword(sii->pbus, PCI_CFG_SVID, &w); |
a9533e7e | 317 | /* Let nvram variables override subsystem Vend/ID */ |
7d4df48e | 318 | sii->pub.boardvendor = (u16)si_getdevpathintvar(&sii->pub, |
ca8c1e59 JC |
319 | "boardvendor"); |
320 | if (sii->pub.boardvendor == 0) | |
a9533e7e HP |
321 | sii->pub.boardvendor = w & 0xffff; |
322 | else | |
323 | SI_ERROR(("Overriding boardvendor: 0x%x instead of 0x%x\n", sii->pub.boardvendor, w & 0xffff)); | |
7d4df48e | 324 | sii->pub.boardtype = (u16)si_getdevpathintvar(&sii->pub, |
ca8c1e59 JC |
325 | "boardtype"); |
326 | if (sii->pub.boardtype == 0) | |
a9533e7e HP |
327 | sii->pub.boardtype = (w >> 16) & 0xffff; |
328 | else | |
329 | SI_ERROR(("Overriding boardtype: 0x%x instead of 0x%x\n", sii->pub.boardtype, (w >> 16) & 0xffff)); | |
330 | break; | |
331 | ||
332 | #ifdef BCMSDIO | |
333 | case SDIO_BUS: | |
334 | #endif | |
335 | sii->pub.boardvendor = getintvar(pvars, "manfid"); | |
336 | sii->pub.boardtype = getintvar(pvars, "prodid"); | |
337 | break; | |
338 | ||
339 | #ifdef BCMSDIO | |
340 | case SPI_BUS: | |
341 | sii->pub.boardvendor = VENDOR_BROADCOM; | |
342 | sii->pub.boardtype = SPI_BOARD; | |
343 | break; | |
344 | #endif | |
345 | ||
346 | case SI_BUS: | |
347 | case JTAG_BUS: | |
348 | sii->pub.boardvendor = VENDOR_BROADCOM; | |
ca8c1e59 JC |
349 | sii->pub.boardtype = getintvar(pvars, "prodid"); |
350 | if (pvars == NULL || (sii->pub.boardtype == 0)) { | |
351 | sii->pub.boardtype = getintvar(NULL, "boardtype"); | |
352 | if (sii->pub.boardtype == 0) | |
a9533e7e | 353 | sii->pub.boardtype = 0xffff; |
ca8c1e59 | 354 | } |
a9533e7e HP |
355 | break; |
356 | } | |
357 | ||
358 | if (sii->pub.boardtype == 0) { | |
359 | SI_ERROR(("si_doattach: unknown board type\n")); | |
360 | ASSERT(sii->pub.boardtype); | |
361 | } | |
362 | ||
363 | sii->pub.boardflags = getintvar(pvars, "boardflags"); | |
364 | } | |
365 | ||
366 | /* this is will make Sonics calls directly, since Sonics is no longer supported in the Si abstraction */ | |
367 | /* this has been customized for the bcm 4329 ONLY */ | |
368 | #ifdef BCMSDIO | |
26bcc181 | 369 | static si_info_t *si_doattach(si_info_t *sii, uint devid, |
06d278c5 | 370 | void *regs, uint bustype, void *pbus, |
0d2f0724 GKH |
371 | char **vars, uint *varsz) |
372 | { | |
a9533e7e | 373 | struct si_pub *sih = &sii->pub; |
66cbd3ab | 374 | u32 w, savewin; |
a9533e7e HP |
375 | chipcregs_t *cc; |
376 | char *pvars = NULL; | |
377 | uint origidx; | |
378 | ||
379 | ASSERT(GOODREGS(regs)); | |
380 | ||
9249ede9 | 381 | memset((unsigned char *) sii, 0, sizeof(si_info_t)); |
a9533e7e HP |
382 | |
383 | savewin = 0; | |
384 | ||
385 | sih->buscoreidx = BADIDX; | |
386 | ||
387 | sii->curmap = regs; | |
06d278c5 | 388 | sii->pbus = pbus; |
a9533e7e HP |
389 | |
390 | /* find Chipcommon address */ | |
391 | cc = (chipcregs_t *) sii->curmap; | |
392 | sih->bustype = bustype; | |
393 | ||
a9533e7e | 394 | /* bus/core/clk setup for register access */ |
06d278c5 | 395 | if (!si_buscore_prep(sii, bustype, devid, pbus)) { |
a9533e7e HP |
396 | SI_ERROR(("si_doattach: si_core_clk_prep failed %d\n", |
397 | bustype)); | |
398 | return NULL; | |
399 | } | |
400 | ||
401 | /* ChipID recognition. | |
402 | * We assume we can read chipid at offset 0 from the regs arg. | |
403 | * If we add other chiptypes (or if we need to support old sdio hosts w/o chipcommon), | |
404 | * some way of recognizing them needs to be added here. | |
405 | */ | |
ff31c54c | 406 | w = R_REG(&cc->chipid); |
a9533e7e HP |
407 | sih->socitype = (w & CID_TYPE_MASK) >> CID_TYPE_SHIFT; |
408 | /* Might as wll fill in chip id rev & pkg */ | |
409 | sih->chip = w & CID_ID_MASK; | |
410 | sih->chiprev = (w & CID_REV_MASK) >> CID_REV_SHIFT; | |
411 | sih->chippkg = (w & CID_PKG_MASK) >> CID_PKG_SHIFT; | |
412 | ||
dfa26436 | 413 | if ((sih->chip == BCM4329_CHIP_ID) && |
cf2b4488 HP |
414 | (sih->chippkg != BCM4329_289PIN_PKG_ID)) |
415 | sih->chippkg = BCM4329_182PIN_PKG_ID; | |
416 | ||
a9533e7e HP |
417 | sih->issim = IS_SIM(sih->chippkg); |
418 | ||
419 | /* scan for cores */ | |
420 | /* SI_MSG(("Found chip type SB (0x%08x)\n", w)); */ | |
421 | sb_scan(&sii->pub, regs, devid); | |
422 | ||
423 | /* no cores found, bail out */ | |
424 | if (sii->numcores == 0) { | |
425 | SI_ERROR(("si_doattach: could not find any cores\n")); | |
426 | return NULL; | |
427 | } | |
428 | /* bus/core/clk setup */ | |
429 | origidx = SI_CC_IDX; | |
430 | if (!si_buscore_setup(sii, cc, bustype, savewin, &origidx, regs)) { | |
431 | SI_ERROR(("si_doattach: si_buscore_setup failed\n")); | |
432 | goto exit; | |
433 | } | |
434 | ||
cf2b4488 HP |
435 | #ifdef BRCM_FULLMAC |
436 | pvars = NULL; | |
437 | #else | |
a9533e7e HP |
438 | /* Init nvram from flash if it exists */ |
439 | nvram_init((void *)&(sii->pub)); | |
440 | ||
441 | /* Init nvram from sprom/otp if they exist */ | |
442 | if (srom_var_init | |
fa7a1db2 | 443 | (&sii->pub, bustype, regs, sii->osh, vars, varsz)) { |
a9533e7e HP |
444 | SI_ERROR(("si_doattach: srom_var_init failed: bad srom\n")); |
445 | goto exit; | |
446 | } | |
447 | pvars = vars ? *vars : NULL; | |
448 | si_nvram_process(sii, pvars); | |
cf2b4488 | 449 | #endif |
a9533e7e HP |
450 | |
451 | /* === NVRAM, clock is ready === */ | |
452 | ||
cf2b4488 HP |
453 | #ifdef BRCM_FULLMAC |
454 | if (sii->pub.ccrev >= 20) { | |
455 | #endif | |
a9533e7e | 456 | cc = (chipcregs_t *) si_setcore(sih, CC_CORE_ID, 0); |
ff31c54c AS |
457 | W_REG(&cc->gpiopullup, 0); |
458 | W_REG(&cc->gpiopulldown, 0); | |
a9533e7e | 459 | sb_setcoreidx(sih, origidx); |
cf2b4488 HP |
460 | #ifdef BRCM_FULLMAC |
461 | } | |
462 | #endif | |
a9533e7e | 463 | |
cf2b4488 | 464 | #ifndef BRCM_FULLMAC |
a9533e7e HP |
465 | /* PMU specific initializations */ |
466 | if (PMUCTL_ENAB(sih)) { | |
66cbd3ab | 467 | u32 xtalfreq; |
26bcc181 AS |
468 | si_pmu_init(sih); |
469 | si_pmu_chip_init(sih); | |
a9533e7e HP |
470 | xtalfreq = getintvar(pvars, "xtalfreq"); |
471 | /* If xtalfreq var not available, try to measure it */ | |
472 | if (xtalfreq == 0) | |
26bcc181 AS |
473 | xtalfreq = si_pmu_measure_alpclk(sih); |
474 | si_pmu_pll_init(sih, xtalfreq); | |
475 | si_pmu_res_init(sih); | |
476 | si_pmu_swreg_init(sih); | |
a9533e7e HP |
477 | } |
478 | ||
479 | /* setup the GPIO based LED powersave register */ | |
ca8c1e59 JC |
480 | w = getintvar(pvars, "leddc"); |
481 | if (w == 0) | |
a9533e7e | 482 | w = DEFAULT_GPIOTIMERVAL; |
ce0f1b8c | 483 | sb_corereg(sih, SI_CC_IDX, offsetof(chipcregs_t, gpiotimerval), ~0, w); |
a9533e7e HP |
484 | |
485 | #ifdef BCMDBG | |
486 | /* clear any previous epidiag-induced target abort */ | |
0965ae88 | 487 | sb_taclear(sih, false); |
a9533e7e | 488 | #endif /* BCMDBG */ |
cf2b4488 | 489 | #endif |
a9533e7e | 490 | |
90ea2296 | 491 | return sii; |
a9533e7e HP |
492 | |
493 | exit: | |
494 | return NULL; | |
495 | } | |
496 | ||
497 | #else /* BCMSDIO */ | |
26bcc181 | 498 | static si_info_t *si_doattach(si_info_t *sii, uint devid, |
06d278c5 | 499 | void *regs, uint bustype, void *pbus, |
0d2f0724 GKH |
500 | char **vars, uint *varsz) |
501 | { | |
a9533e7e | 502 | struct si_pub *sih = &sii->pub; |
66cbd3ab | 503 | u32 w, savewin; |
a9533e7e HP |
504 | chipcregs_t *cc; |
505 | char *pvars = NULL; | |
506 | uint origidx; | |
507 | ||
508 | ASSERT(GOODREGS(regs)); | |
509 | ||
9249ede9 | 510 | memset((unsigned char *) sii, 0, sizeof(si_info_t)); |
a9533e7e HP |
511 | |
512 | savewin = 0; | |
513 | ||
514 | sih->buscoreidx = BADIDX; | |
515 | ||
516 | sii->curmap = regs; | |
06d278c5 | 517 | sii->pbus = pbus; |
a9533e7e HP |
518 | |
519 | /* check to see if we are a si core mimic'ing a pci core */ | |
57d8cd23 | 520 | if (bustype == PCI_BUS) { |
06d278c5 | 521 | pci_read_config_dword(sii->pbus, PCI_SPROM_CONTROL, &w); |
57d8cd23 BR |
522 | if (w == 0xffffffff) { |
523 | SI_ERROR(("%s: incoming bus is PCI but it's a lie, " | |
524 | " switching to SI devid:0x%x\n", | |
525 | __func__, devid)); | |
526 | bustype = SI_BUS; | |
527 | } | |
a9533e7e HP |
528 | } |
529 | ||
530 | /* find Chipcommon address */ | |
531 | if (bustype == PCI_BUS) { | |
06d278c5 | 532 | pci_read_config_dword(sii->pbus, PCI_BAR0_WIN, &savewin); |
a9533e7e HP |
533 | if (!GOODCOREADDR(savewin, SI_ENUM_BASE)) |
534 | savewin = SI_ENUM_BASE; | |
06d278c5 | 535 | pci_write_config_dword(sii->pbus, PCI_BAR0_WIN, |
57d8cd23 | 536 | SI_ENUM_BASE); |
a9533e7e HP |
537 | cc = (chipcregs_t *) regs; |
538 | } else { | |
539 | cc = (chipcregs_t *) REG_MAP(SI_ENUM_BASE, SI_CORE_SIZE); | |
540 | } | |
541 | ||
542 | sih->bustype = bustype; | |
a9533e7e HP |
543 | |
544 | /* bus/core/clk setup for register access */ | |
06d278c5 | 545 | if (!si_buscore_prep(sii, bustype, devid, pbus)) { |
a9533e7e HP |
546 | SI_ERROR(("si_doattach: si_core_clk_prep failed %d\n", |
547 | bustype)); | |
548 | return NULL; | |
549 | } | |
550 | ||
551 | /* ChipID recognition. | |
552 | * We assume we can read chipid at offset 0 from the regs arg. | |
553 | * If we add other chiptypes (or if we need to support old sdio hosts w/o chipcommon), | |
554 | * some way of recognizing them needs to be added here. | |
555 | */ | |
ff31c54c | 556 | w = R_REG(&cc->chipid); |
a9533e7e HP |
557 | sih->socitype = (w & CID_TYPE_MASK) >> CID_TYPE_SHIFT; |
558 | /* Might as wll fill in chip id rev & pkg */ | |
559 | sih->chip = w & CID_ID_MASK; | |
560 | sih->chiprev = (w & CID_REV_MASK) >> CID_REV_SHIFT; | |
561 | sih->chippkg = (w & CID_PKG_MASK) >> CID_PKG_SHIFT; | |
562 | ||
563 | sih->issim = IS_SIM(sih->chippkg); | |
564 | ||
565 | /* scan for cores */ | |
92246bcb | 566 | if (sii->pub.socitype == SOCI_AI) { |
a9533e7e HP |
567 | SI_MSG(("Found chip type AI (0x%08x)\n", w)); |
568 | /* pass chipc address instead of original core base */ | |
c03b63c1 | 569 | ai_scan(&sii->pub, (void *)cc, devid); |
a9533e7e HP |
570 | } else { |
571 | SI_ERROR(("Found chip of unknown type (0x%08x)\n", w)); | |
572 | return NULL; | |
573 | } | |
574 | /* no cores found, bail out */ | |
575 | if (sii->numcores == 0) { | |
576 | SI_ERROR(("si_doattach: could not find any cores\n")); | |
577 | return NULL; | |
578 | } | |
579 | /* bus/core/clk setup */ | |
580 | origidx = SI_CC_IDX; | |
581 | if (!si_buscore_setup(sii, cc, bustype, savewin, &origidx, regs)) { | |
582 | SI_ERROR(("si_doattach: si_buscore_setup failed\n")); | |
583 | goto exit; | |
584 | } | |
585 | ||
586 | /* assume current core is CC */ | |
587 | if ((sii->pub.ccrev == 0x25) | |
588 | && | |
dfa26436 AS |
589 | ((sih->chip == BCM43236_CHIP_ID |
590 | || sih->chip == BCM43235_CHIP_ID | |
591 | || sih->chip == BCM43238_CHIP_ID) | |
ff29ee8f | 592 | && (sii->pub.chiprev <= 2))) { |
a9533e7e HP |
593 | |
594 | if ((cc->chipstatus & CST43236_BP_CLK) != 0) { | |
595 | uint clkdiv; | |
ff31c54c | 596 | clkdiv = R_REG(&cc->clkdiv); |
a9533e7e HP |
597 | /* otp_clk_div is even number, 120/14 < 9mhz */ |
598 | clkdiv = (clkdiv & ~CLKD_OTP) | (14 << CLKD_OTP_SHIFT); | |
ff31c54c | 599 | W_REG(&cc->clkdiv, clkdiv); |
a9533e7e HP |
600 | SI_ERROR(("%s: set clkdiv to %x\n", __func__, clkdiv)); |
601 | } | |
7383141b | 602 | udelay(10); |
a9533e7e HP |
603 | } |
604 | ||
605 | /* Init nvram from flash if it exists */ | |
606 | nvram_init((void *)&(sii->pub)); | |
607 | ||
608 | /* Init nvram from sprom/otp if they exist */ | |
609 | if (srom_var_init | |
26bcc181 | 610 | (&sii->pub, bustype, regs, vars, varsz)) { |
a9533e7e HP |
611 | SI_ERROR(("si_doattach: srom_var_init failed: bad srom\n")); |
612 | goto exit; | |
613 | } | |
614 | pvars = vars ? *vars : NULL; | |
615 | si_nvram_process(sii, pvars); | |
616 | ||
617 | /* === NVRAM, clock is ready === */ | |
618 | cc = (chipcregs_t *) si_setcore(sih, CC_CORE_ID, 0); | |
ff31c54c AS |
619 | W_REG(&cc->gpiopullup, 0); |
620 | W_REG(&cc->gpiopulldown, 0); | |
a9533e7e HP |
621 | si_setcoreidx(sih, origidx); |
622 | ||
623 | /* PMU specific initializations */ | |
624 | if (PMUCTL_ENAB(sih)) { | |
66cbd3ab | 625 | u32 xtalfreq; |
26bcc181 AS |
626 | si_pmu_init(sih); |
627 | si_pmu_chip_init(sih); | |
a9533e7e HP |
628 | xtalfreq = getintvar(pvars, "xtalfreq"); |
629 | /* If xtalfreq var not available, try to measure it */ | |
630 | if (xtalfreq == 0) | |
26bcc181 AS |
631 | xtalfreq = si_pmu_measure_alpclk(sih); |
632 | si_pmu_pll_init(sih, xtalfreq); | |
633 | si_pmu_res_init(sih); | |
634 | si_pmu_swreg_init(sih); | |
a9533e7e HP |
635 | } |
636 | ||
637 | /* setup the GPIO based LED powersave register */ | |
ca8c1e59 JC |
638 | w = getintvar(pvars, "leddc"); |
639 | if (w == 0) | |
a9533e7e | 640 | w = DEFAULT_GPIOTIMERVAL; |
ce0f1b8c | 641 | si_corereg(sih, SI_CC_IDX, offsetof(chipcregs_t, gpiotimerval), ~0, w); |
a9533e7e HP |
642 | |
643 | if (PCIE(sii)) { | |
644 | ASSERT(sii->pch != NULL); | |
645 | pcicore_attach(sii->pch, pvars, SI_DOATTACH); | |
646 | } | |
647 | ||
dfa26436 AS |
648 | if ((sih->chip == BCM43224_CHIP_ID) || |
649 | (sih->chip == BCM43421_CHIP_ID)) { | |
a9533e7e | 650 | /* enable 12 mA drive strenth for 43224 and set chipControl register bit 15 */ |
ff29ee8f | 651 | if (sih->chiprev == 0) { |
a9533e7e HP |
652 | SI_MSG(("Applying 43224A0 WARs\n")); |
653 | si_corereg(sih, SI_CC_IDX, | |
ce0f1b8c | 654 | offsetof(chipcregs_t, chipcontrol), |
a9533e7e HP |
655 | CCTRL43224_GPIO_TOGGLE, |
656 | CCTRL43224_GPIO_TOGGLE); | |
657 | si_pmu_chipcontrol(sih, 0, CCTRL_43224A0_12MA_LED_DRIVE, | |
658 | CCTRL_43224A0_12MA_LED_DRIVE); | |
659 | } | |
ff29ee8f | 660 | if (sih->chiprev >= 1) { |
a9533e7e HP |
661 | SI_MSG(("Applying 43224B0+ WARs\n")); |
662 | si_pmu_chipcontrol(sih, 0, CCTRL_43224B0_12MA_LED_DRIVE, | |
663 | CCTRL_43224B0_12MA_LED_DRIVE); | |
664 | } | |
665 | } | |
666 | ||
dfa26436 | 667 | if (sih->chip == BCM4313_CHIP_ID) { |
a9533e7e HP |
668 | /* enable 12 mA drive strenth for 4313 and set chipControl register bit 1 */ |
669 | SI_MSG(("Applying 4313 WARs\n")); | |
670 | si_pmu_chipcontrol(sih, 0, CCTRL_4313_12MA_LED_DRIVE, | |
671 | CCTRL_4313_12MA_LED_DRIVE); | |
672 | } | |
673 | ||
dfa26436 | 674 | if (sih->chip == BCM4331_CHIP_ID) { |
a9533e7e | 675 | /* Enable Ext PA lines depending on chip package option */ |
0f0881b0 | 676 | si_chipcontrl_epa4331(sih, true); |
a9533e7e HP |
677 | } |
678 | ||
90ea2296 | 679 | return sii; |
a9533e7e | 680 | exit: |
fa7a1db2 | 681 | if (sih->bustype == PCI_BUS) { |
a9533e7e HP |
682 | if (sii->pch) |
683 | pcicore_deinit(sii->pch); | |
684 | sii->pch = NULL; | |
685 | } | |
686 | ||
687 | return NULL; | |
688 | } | |
689 | #endif /* BCMSDIO */ | |
690 | ||
691 | /* may be called with core in reset */ | |
0d2f0724 | 692 | void si_detach(si_t *sih) |
a2627bc0 | 693 | { |
a9533e7e HP |
694 | si_info_t *sii; |
695 | uint idx; | |
696 | ||
697 | struct si_pub *si_local = NULL; | |
02160695 | 698 | memcpy(&si_local, &sih, sizeof(si_t **)); |
a9533e7e HP |
699 | |
700 | sii = SI_INFO(sih); | |
701 | ||
702 | if (sii == NULL) | |
703 | return; | |
704 | ||
fa7a1db2 | 705 | if (sih->bustype == SI_BUS) |
a9533e7e HP |
706 | for (idx = 0; idx < SI_MAXCORES; idx++) |
707 | if (sii->regs[idx]) { | |
8968af14 | 708 | iounmap(sii->regs[idx]); |
a9533e7e HP |
709 | sii->regs[idx] = NULL; |
710 | } | |
711 | ||
cf2b4488 | 712 | #ifndef BRCM_FULLMAC |
a9533e7e HP |
713 | nvram_exit((void *)si_local); /* free up nvram buffers */ |
714 | ||
fa7a1db2 | 715 | if (sih->bustype == PCI_BUS) { |
a9533e7e HP |
716 | if (sii->pch) |
717 | pcicore_deinit(sii->pch); | |
718 | sii->pch = NULL; | |
719 | } | |
cf2b4488 | 720 | #endif |
a9533e7e HP |
721 | #if !defined(BCMBUSTYPE) || (BCMBUSTYPE == SI_BUS) |
722 | if (sii != &ksii) | |
723 | #endif /* !BCMBUSTYPE || (BCMBUSTYPE == SI_BUS) */ | |
182acb3c | 724 | kfree(sii); |
a9533e7e HP |
725 | } |
726 | ||
a9533e7e HP |
727 | /* register driver interrupt disabling and restoring callback functions */ |
728 | void | |
7cc4a4c0 | 729 | si_register_intr_callback(si_t *sih, void *intrsoff_fn, void *intrsrestore_fn, |
a9533e7e HP |
730 | void *intrsenabled_fn, void *intr_arg) |
731 | { | |
732 | si_info_t *sii; | |
733 | ||
734 | sii = SI_INFO(sih); | |
735 | sii->intr_arg = intr_arg; | |
736 | sii->intrsoff_fn = (si_intrsoff_t) intrsoff_fn; | |
737 | sii->intrsrestore_fn = (si_intrsrestore_t) intrsrestore_fn; | |
738 | sii->intrsenabled_fn = (si_intrsenabled_t) intrsenabled_fn; | |
739 | /* save current core id. when this function called, the current core | |
740 | * must be the core which provides driver functions(il, et, wl, etc.) | |
741 | */ | |
742 | sii->dev_coreid = sii->coreid[sii->curidx]; | |
743 | } | |
744 | ||
7cc4a4c0 | 745 | void si_deregister_intr_callback(si_t *sih) |
a9533e7e HP |
746 | { |
747 | si_info_t *sii; | |
748 | ||
749 | sii = SI_INFO(sih); | |
750 | sii->intrsoff_fn = NULL; | |
751 | } | |
752 | ||
7cc4a4c0 | 753 | uint si_flag(si_t *sih) |
a9533e7e | 754 | { |
92246bcb | 755 | if (sih->socitype == SOCI_AI) |
a9533e7e HP |
756 | return ai_flag(sih); |
757 | else { | |
758 | ASSERT(0); | |
759 | return 0; | |
760 | } | |
761 | } | |
762 | ||
7cc4a4c0 | 763 | void si_setint(si_t *sih, int siflag) |
a9533e7e | 764 | { |
92246bcb | 765 | if (sih->socitype == SOCI_AI) |
a9533e7e HP |
766 | ai_setint(sih, siflag); |
767 | else | |
768 | ASSERT(0); | |
769 | } | |
770 | ||
771 | #ifndef BCMSDIO | |
7cc4a4c0 | 772 | uint si_coreid(si_t *sih) |
a9533e7e HP |
773 | { |
774 | si_info_t *sii; | |
775 | ||
776 | sii = SI_INFO(sih); | |
777 | return sii->coreid[sii->curidx]; | |
778 | } | |
779 | #endif | |
780 | ||
7cc4a4c0 | 781 | uint si_coreidx(si_t *sih) |
a9533e7e HP |
782 | { |
783 | si_info_t *sii; | |
784 | ||
785 | sii = SI_INFO(sih); | |
786 | return sii->curidx; | |
787 | } | |
788 | ||
7cc4a4c0 | 789 | bool si_backplane64(si_t *sih) |
a9533e7e | 790 | { |
90ea2296 | 791 | return (sih->cccaps & CC_CAP_BKPLN64) != 0; |
a9533e7e HP |
792 | } |
793 | ||
794 | #ifndef BCMSDIO | |
7cc4a4c0 | 795 | uint si_corerev(si_t *sih) |
a9533e7e | 796 | { |
92246bcb | 797 | if (sih->socitype == SOCI_AI) |
a9533e7e HP |
798 | return ai_corerev(sih); |
799 | else { | |
800 | ASSERT(0); | |
801 | return 0; | |
802 | } | |
803 | } | |
804 | #endif | |
805 | ||
806 | /* return index of coreid or BADIDX if not found */ | |
7cc4a4c0 | 807 | uint si_findcoreidx(si_t *sih, uint coreid, uint coreunit) |
a9533e7e HP |
808 | { |
809 | si_info_t *sii; | |
810 | uint found; | |
811 | uint i; | |
812 | ||
813 | sii = SI_INFO(sih); | |
814 | ||
815 | found = 0; | |
816 | ||
817 | for (i = 0; i < sii->numcores; i++) | |
818 | if (sii->coreid[i] == coreid) { | |
819 | if (found == coreunit) | |
90ea2296 | 820 | return i; |
a9533e7e HP |
821 | found++; |
822 | } | |
823 | ||
90ea2296 | 824 | return BADIDX; |
a9533e7e HP |
825 | } |
826 | ||
a9533e7e HP |
827 | /* |
828 | * This function changes logical "focus" to the indicated core; | |
829 | * must be called with interrupts off. | |
830 | * Moreover, callers should keep interrupts off during switching out of and back to d11 core | |
831 | */ | |
7cc4a4c0 | 832 | void *si_setcore(si_t *sih, uint coreid, uint coreunit) |
a9533e7e HP |
833 | { |
834 | uint idx; | |
835 | ||
836 | idx = si_findcoreidx(sih, coreid, coreunit); | |
837 | if (!GOODIDX(idx)) | |
90ea2296 | 838 | return NULL; |
a9533e7e | 839 | |
92246bcb | 840 | if (sih->socitype == SOCI_AI) |
a9533e7e HP |
841 | return ai_setcoreidx(sih, idx); |
842 | else { | |
843 | #ifdef BCMSDIO | |
844 | return sb_setcoreidx(sih, idx); | |
845 | #else | |
846 | ASSERT(0); | |
847 | return NULL; | |
848 | #endif | |
849 | } | |
850 | } | |
851 | ||
852 | #ifndef BCMSDIO | |
7cc4a4c0 | 853 | void *si_setcoreidx(si_t *sih, uint coreidx) |
a9533e7e | 854 | { |
92246bcb | 855 | if (sih->socitype == SOCI_AI) |
a9533e7e HP |
856 | return ai_setcoreidx(sih, coreidx); |
857 | else { | |
858 | ASSERT(0); | |
859 | return NULL; | |
860 | } | |
861 | } | |
862 | #endif | |
863 | ||
864 | /* Turn off interrupt as required by sb_setcore, before switch core */ | |
7cc4a4c0 | 865 | void *si_switch_core(si_t *sih, uint coreid, uint *origidx, uint *intr_val) |
a9533e7e HP |
866 | { |
867 | void *cc; | |
868 | si_info_t *sii; | |
869 | ||
870 | sii = SI_INFO(sih); | |
871 | ||
872 | if (SI_FAST(sii)) { | |
873 | /* Overloading the origidx variable to remember the coreid, | |
874 | * this works because the core ids cannot be confused with | |
875 | * core indices. | |
876 | */ | |
877 | *origidx = coreid; | |
878 | if (coreid == CC_CORE_ID) | |
879 | return (void *)CCREGS_FAST(sii); | |
880 | else if (coreid == sih->buscoretype) | |
881 | return (void *)PCIEREGS(sii); | |
882 | } | |
883 | INTR_OFF(sii, *intr_val); | |
884 | *origidx = sii->curidx; | |
885 | cc = si_setcore(sih, coreid, 0); | |
886 | ASSERT(cc != NULL); | |
887 | ||
888 | return cc; | |
889 | } | |
890 | ||
891 | /* restore coreidx and restore interrupt */ | |
7cc4a4c0 | 892 | void si_restore_core(si_t *sih, uint coreid, uint intr_val) |
a9533e7e HP |
893 | { |
894 | si_info_t *sii; | |
895 | ||
896 | sii = SI_INFO(sih); | |
897 | if (SI_FAST(sii) | |
898 | && ((coreid == CC_CORE_ID) || (coreid == sih->buscoretype))) | |
899 | return; | |
900 | ||
901 | si_setcoreidx(sih, coreid); | |
902 | INTR_RESTORE(sii, intr_val); | |
903 | } | |
904 | ||
66cbd3ab | 905 | u32 si_core_cflags(si_t *sih, u32 mask, u32 val) |
a9533e7e | 906 | { |
92246bcb | 907 | if (sih->socitype == SOCI_AI) |
a9533e7e HP |
908 | return ai_core_cflags(sih, mask, val); |
909 | else { | |
910 | ASSERT(0); | |
911 | return 0; | |
912 | } | |
913 | } | |
914 | ||
66cbd3ab | 915 | u32 si_core_sflags(si_t *sih, u32 mask, u32 val) |
a9533e7e | 916 | { |
92246bcb | 917 | if (sih->socitype == SOCI_AI) |
a9533e7e HP |
918 | return ai_core_sflags(sih, mask, val); |
919 | else { | |
920 | ASSERT(0); | |
921 | return 0; | |
922 | } | |
923 | } | |
924 | ||
7cc4a4c0 | 925 | bool si_iscoreup(si_t *sih) |
a9533e7e | 926 | { |
92246bcb | 927 | if (sih->socitype == SOCI_AI) |
a9533e7e HP |
928 | return ai_iscoreup(sih); |
929 | else { | |
930 | #ifdef BCMSDIO | |
931 | return sb_iscoreup(sih); | |
932 | #else | |
933 | ASSERT(0); | |
0965ae88 | 934 | return false; |
a9533e7e HP |
935 | #endif |
936 | } | |
937 | } | |
938 | ||
66cbd3ab | 939 | void si_write_wrapperreg(si_t *sih, u32 offset, u32 val) |
a9533e7e HP |
940 | { |
941 | /* only for 4319, no requirement for SOCI_SB */ | |
92246bcb | 942 | if (sih->socitype == SOCI_AI) { |
a9533e7e HP |
943 | ai_write_wrap_reg(sih, offset, val); |
944 | } | |
945 | } | |
946 | ||
7cc4a4c0 | 947 | uint si_corereg(si_t *sih, uint coreidx, uint regoff, uint mask, uint val) |
a9533e7e HP |
948 | { |
949 | ||
92246bcb | 950 | if (sih->socitype == SOCI_AI) |
a9533e7e HP |
951 | return ai_corereg(sih, coreidx, regoff, mask, val); |
952 | else { | |
953 | #ifdef BCMSDIO | |
954 | return sb_corereg(sih, coreidx, regoff, mask, val); | |
955 | #else | |
956 | ASSERT(0); | |
957 | return 0; | |
958 | #endif | |
959 | } | |
960 | } | |
961 | ||
66cbd3ab | 962 | void si_core_disable(si_t *sih, u32 bits) |
a9533e7e HP |
963 | { |
964 | ||
92246bcb | 965 | if (sih->socitype == SOCI_AI) |
a9533e7e HP |
966 | ai_core_disable(sih, bits); |
967 | #ifdef BCMSDIO | |
968 | else | |
969 | sb_core_disable(sih, bits); | |
970 | #endif | |
971 | } | |
972 | ||
66cbd3ab | 973 | void si_core_reset(si_t *sih, u32 bits, u32 resetbits) |
a9533e7e | 974 | { |
92246bcb | 975 | if (sih->socitype == SOCI_AI) |
a9533e7e HP |
976 | ai_core_reset(sih, bits, resetbits); |
977 | #ifdef BCMSDIO | |
978 | else | |
979 | sb_core_reset(sih, bits, resetbits); | |
980 | #endif | |
981 | } | |
982 | ||
b4f790ee | 983 | u32 si_alp_clock(si_t *sih) |
a2627bc0 | 984 | { |
a9533e7e | 985 | if (PMUCTL_ENAB(sih)) |
26bcc181 | 986 | return si_pmu_alp_clock(sih); |
a9533e7e HP |
987 | |
988 | return ALP_CLOCK; | |
989 | } | |
990 | ||
b4f790ee | 991 | u32 si_ilp_clock(si_t *sih) |
a2627bc0 | 992 | { |
a9533e7e | 993 | if (PMUCTL_ENAB(sih)) |
26bcc181 | 994 | return si_pmu_ilp_clock(sih); |
a9533e7e HP |
995 | |
996 | return ILP_CLOCK; | |
997 | } | |
998 | ||
999 | /* set chip watchdog reset timer to fire in 'ticks' */ | |
cf2b4488 HP |
1000 | #ifdef BRCM_FULLMAC |
1001 | void | |
1002 | si_watchdog(si_t *sih, uint ticks) | |
1003 | { | |
1004 | if (PMUCTL_ENAB(sih)) { | |
1005 | ||
1006 | if ((sih->chip == BCM4319_CHIP_ID) && (sih->chiprev == 0) && | |
1007 | (ticks != 0)) { | |
ce0f1b8c | 1008 | si_corereg(sih, SI_CC_IDX, offsetof(chipcregs_t, |
cf2b4488 HP |
1009 | clk_ctl_st), ~0, 0x2); |
1010 | si_setcore(sih, USB20D_CORE_ID, 0); | |
1011 | si_core_disable(sih, 1); | |
1012 | si_setcore(sih, CC_CORE_ID, 0); | |
1013 | } | |
1014 | ||
1015 | if (ticks == 1) | |
1016 | ticks = 2; | |
ce0f1b8c | 1017 | si_corereg(sih, SI_CC_IDX, offsetof(chipcregs_t, pmuwatchdog), |
cf2b4488 HP |
1018 | ~0, ticks); |
1019 | } else { | |
1020 | /* instant NMI */ | |
ce0f1b8c | 1021 | si_corereg(sih, SI_CC_IDX, offsetof(chipcregs_t, watchdog), |
cf2b4488 HP |
1022 | ~0, ticks); |
1023 | } | |
1024 | } | |
1025 | #else | |
7cc4a4c0 | 1026 | void si_watchdog(si_t *sih, uint ticks) |
a9533e7e HP |
1027 | { |
1028 | uint nb, maxt; | |
1029 | ||
1030 | if (PMUCTL_ENAB(sih)) { | |
1031 | ||
dfa26436 | 1032 | if ((sih->chip == BCM4319_CHIP_ID) && |
ff29ee8f | 1033 | (sih->chiprev == 0) && (ticks != 0)) { |
a9533e7e | 1034 | si_corereg(sih, SI_CC_IDX, |
ce0f1b8c | 1035 | offsetof(chipcregs_t, clk_ctl_st), ~0, 0x2); |
a9533e7e HP |
1036 | si_setcore(sih, USB20D_CORE_ID, 0); |
1037 | si_core_disable(sih, 1); | |
1038 | si_setcore(sih, CC_CORE_ID, 0); | |
1039 | } | |
1040 | ||
1041 | nb = (sih->ccrev < 26) ? 16 : ((sih->ccrev >= 37) ? 32 : 24); | |
1042 | /* The mips compiler uses the sllv instruction, | |
1043 | * so we specially handle the 32-bit case. | |
1044 | */ | |
1045 | if (nb == 32) | |
1046 | maxt = 0xffffffff; | |
1047 | else | |
1048 | maxt = ((1 << nb) - 1); | |
1049 | ||
1050 | if (ticks == 1) | |
1051 | ticks = 2; | |
1052 | else if (ticks > maxt) | |
1053 | ticks = maxt; | |
1054 | ||
ce0f1b8c | 1055 | si_corereg(sih, SI_CC_IDX, offsetof(chipcregs_t, pmuwatchdog), |
a9533e7e HP |
1056 | ~0, ticks); |
1057 | } else { | |
1058 | /* make sure we come up in fast clock mode; or if clearing, clear clock */ | |
1059 | si_clkctl_cc(sih, ticks ? CLK_FAST : CLK_DYNAMIC); | |
1060 | maxt = (1 << 28) - 1; | |
1061 | if (ticks > maxt) | |
1062 | ticks = maxt; | |
1063 | ||
ce0f1b8c | 1064 | si_corereg(sih, SI_CC_IDX, offsetof(chipcregs_t, watchdog), ~0, |
a9533e7e HP |
1065 | ticks); |
1066 | } | |
1067 | } | |
cf2b4488 | 1068 | #endif |
a9533e7e | 1069 | |
a9533e7e | 1070 | /* return the slow clock source - LPO, XTAL, or PCI */ |
7cc4a4c0 | 1071 | static uint si_slowclk_src(si_info_t *sii) |
a9533e7e HP |
1072 | { |
1073 | chipcregs_t *cc; | |
57d8cd23 | 1074 | u32 val; |
a9533e7e HP |
1075 | |
1076 | ASSERT(SI_FAST(sii) || si_coreid(&sii->pub) == CC_CORE_ID); | |
1077 | ||
1078 | if (sii->pub.ccrev < 6) { | |
fa7a1db2 | 1079 | if (sii->pub.bustype == PCI_BUS) { |
06d278c5 | 1080 | pci_read_config_dword(sii->pbus, PCI_GPIO_OUT, |
57d8cd23 BR |
1081 | &val); |
1082 | if (val & PCI_CFG_GPIO_SCS) | |
1083 | return SCC_SS_PCI; | |
1084 | } | |
1085 | return SCC_SS_XTAL; | |
a9533e7e HP |
1086 | } else if (sii->pub.ccrev < 10) { |
1087 | cc = (chipcregs_t *) si_setcoreidx(&sii->pub, sii->curidx); | |
ff31c54c | 1088 | return R_REG(&cc->slow_clk_ctl) & SCC_SS_MASK; |
a9533e7e | 1089 | } else /* Insta-clock */ |
90ea2296 | 1090 | return SCC_SS_XTAL; |
a9533e7e HP |
1091 | } |
1092 | ||
1093 | /* return the ILP (slowclock) min or max frequency */ | |
7cc4a4c0 | 1094 | static uint si_slowclk_freq(si_info_t *sii, bool max_freq, chipcregs_t *cc) |
a9533e7e | 1095 | { |
66cbd3ab | 1096 | u32 slowclk; |
a9533e7e HP |
1097 | uint div; |
1098 | ||
1099 | ASSERT(SI_FAST(sii) || si_coreid(&sii->pub) == CC_CORE_ID); | |
1100 | ||
1101 | /* shouldn't be here unless we've established the chip has dynamic clk control */ | |
ff31c54c | 1102 | ASSERT(R_REG(&cc->capabilities) & CC_CAP_PWR_CTL); |
a9533e7e HP |
1103 | |
1104 | slowclk = si_slowclk_src(sii); | |
1105 | if (sii->pub.ccrev < 6) { | |
1106 | if (slowclk == SCC_SS_PCI) | |
90ea2296 JC |
1107 | return max_freq ? (PCIMAXFREQ / 64) |
1108 | : (PCIMINFREQ / 64); | |
a9533e7e | 1109 | else |
90ea2296 JC |
1110 | return max_freq ? (XTALMAXFREQ / 32) |
1111 | : (XTALMINFREQ / 32); | |
a9533e7e HP |
1112 | } else if (sii->pub.ccrev < 10) { |
1113 | div = 4 * | |
ff31c54c | 1114 | (((R_REG(&cc->slow_clk_ctl) & SCC_CD_MASK) >> |
a9533e7e HP |
1115 | SCC_CD_SHIFT) + 1); |
1116 | if (slowclk == SCC_SS_LPO) | |
90ea2296 | 1117 | return max_freq ? LPOMAXFREQ : LPOMINFREQ; |
a9533e7e | 1118 | else if (slowclk == SCC_SS_XTAL) |
90ea2296 JC |
1119 | return max_freq ? (XTALMAXFREQ / div) |
1120 | : (XTALMINFREQ / div); | |
a9533e7e | 1121 | else if (slowclk == SCC_SS_PCI) |
90ea2296 JC |
1122 | return max_freq ? (PCIMAXFREQ / div) |
1123 | : (PCIMINFREQ / div); | |
a9533e7e HP |
1124 | else |
1125 | ASSERT(0); | |
1126 | } else { | |
1127 | /* Chipc rev 10 is InstaClock */ | |
ff31c54c | 1128 | div = R_REG(&cc->system_clk_ctl) >> SYCC_CD_SHIFT; |
a9533e7e | 1129 | div = 4 * (div + 1); |
90ea2296 | 1130 | return max_freq ? XTALMAXFREQ : (XTALMINFREQ / div); |
a9533e7e | 1131 | } |
90ea2296 | 1132 | return 0; |
a9533e7e HP |
1133 | } |
1134 | ||
b4f790ee | 1135 | static void si_clkctl_setdelay(si_info_t *sii, void *chipcregs) |
a2627bc0 | 1136 | { |
a9533e7e HP |
1137 | chipcregs_t *cc = (chipcregs_t *) chipcregs; |
1138 | uint slowmaxfreq, pll_delay, slowclk; | |
1139 | uint pll_on_delay, fref_sel_delay; | |
1140 | ||
1141 | pll_delay = PLL_DELAY; | |
1142 | ||
1143 | /* If the slow clock is not sourced by the xtal then add the xtal_on_delay | |
1144 | * since the xtal will also be powered down by dynamic clk control logic. | |
1145 | */ | |
1146 | ||
1147 | slowclk = si_slowclk_src(sii); | |
1148 | if (slowclk != SCC_SS_XTAL) | |
1149 | pll_delay += XTAL_ON_DELAY; | |
1150 | ||
1151 | /* Starting with 4318 it is ILP that is used for the delays */ | |
1152 | slowmaxfreq = | |
0965ae88 | 1153 | si_slowclk_freq(sii, (sii->pub.ccrev >= 10) ? false : true, cc); |
a9533e7e HP |
1154 | |
1155 | pll_on_delay = ((slowmaxfreq * pll_delay) + 999999) / 1000000; | |
1156 | fref_sel_delay = ((slowmaxfreq * FREF_DELAY) + 999999) / 1000000; | |
1157 | ||
ff31c54c AS |
1158 | W_REG(&cc->pll_on_delay, pll_on_delay); |
1159 | W_REG(&cc->fref_sel_delay, fref_sel_delay); | |
a9533e7e HP |
1160 | } |
1161 | ||
1162 | /* initialize power control delay registers */ | |
b4f790ee | 1163 | void si_clkctl_init(si_t *sih) |
a2627bc0 | 1164 | { |
a9533e7e HP |
1165 | si_info_t *sii; |
1166 | uint origidx = 0; | |
1167 | chipcregs_t *cc; | |
1168 | bool fast; | |
1169 | ||
1170 | if (!CCCTL_ENAB(sih)) | |
1171 | return; | |
1172 | ||
1173 | sii = SI_INFO(sih); | |
1174 | fast = SI_FAST(sii); | |
1175 | if (!fast) { | |
1176 | origidx = sii->curidx; | |
ca8c1e59 JC |
1177 | cc = (chipcregs_t *) si_setcore(sih, CC_CORE_ID, 0); |
1178 | if (cc == NULL) | |
a9533e7e | 1179 | return; |
ca8c1e59 JC |
1180 | } else { |
1181 | cc = (chipcregs_t *) CCREGS_FAST(sii); | |
1182 | if (cc == NULL) | |
1183 | return; | |
1184 | } | |
a9533e7e HP |
1185 | ASSERT(cc != NULL); |
1186 | ||
1187 | /* set all Instaclk chip ILP to 1 MHz */ | |
1188 | if (sih->ccrev >= 10) | |
ff31c54c | 1189 | SET_REG(&cc->system_clk_ctl, SYCC_CD_MASK, |
a9533e7e HP |
1190 | (ILP_DIV_1MHZ << SYCC_CD_SHIFT)); |
1191 | ||
c03b63c1 | 1192 | si_clkctl_setdelay(sii, (void *)cc); |
a9533e7e HP |
1193 | |
1194 | if (!fast) | |
1195 | si_setcoreidx(sih, origidx); | |
1196 | } | |
1197 | ||
1198 | /* return the value suitable for writing to the dot11 core FAST_PWRUP_DELAY register */ | |
b4f790ee | 1199 | u16 si_clkctl_fast_pwrup_delay(si_t *sih) |
a2627bc0 | 1200 | { |
a9533e7e HP |
1201 | si_info_t *sii; |
1202 | uint origidx = 0; | |
1203 | chipcregs_t *cc; | |
1204 | uint slowminfreq; | |
7d4df48e | 1205 | u16 fpdelay; |
a9533e7e HP |
1206 | uint intr_val = 0; |
1207 | bool fast; | |
1208 | ||
1209 | sii = SI_INFO(sih); | |
1210 | if (PMUCTL_ENAB(sih)) { | |
1211 | INTR_OFF(sii, intr_val); | |
26bcc181 | 1212 | fpdelay = si_pmu_fast_pwrup_delay(sih); |
a9533e7e HP |
1213 | INTR_RESTORE(sii, intr_val); |
1214 | return fpdelay; | |
1215 | } | |
1216 | ||
1217 | if (!CCCTL_ENAB(sih)) | |
1218 | return 0; | |
1219 | ||
1220 | fast = SI_FAST(sii); | |
1221 | fpdelay = 0; | |
1222 | if (!fast) { | |
1223 | origidx = sii->curidx; | |
1224 | INTR_OFF(sii, intr_val); | |
ca8c1e59 JC |
1225 | cc = (chipcregs_t *) si_setcore(sih, CC_CORE_ID, 0); |
1226 | if (cc == NULL) | |
a9533e7e | 1227 | goto done; |
ca8c1e59 JC |
1228 | } else { |
1229 | cc = (chipcregs_t *) CCREGS_FAST(sii); | |
1230 | if (cc == NULL) | |
1231 | goto done; | |
1232 | } | |
a9533e7e HP |
1233 | ASSERT(cc != NULL); |
1234 | ||
0965ae88 | 1235 | slowminfreq = si_slowclk_freq(sii, false, cc); |
ff31c54c | 1236 | fpdelay = (((R_REG(&cc->pll_on_delay) + 2) * 1000000) + |
a9533e7e HP |
1237 | (slowminfreq - 1)) / slowminfreq; |
1238 | ||
1239 | done: | |
1240 | if (!fast) { | |
1241 | si_setcoreidx(sih, origidx); | |
1242 | INTR_RESTORE(sii, intr_val); | |
1243 | } | |
1244 | return fpdelay; | |
1245 | } | |
1246 | ||
1247 | /* turn primary xtal and/or pll off/on */ | |
7cc4a4c0 | 1248 | int si_clkctl_xtal(si_t *sih, uint what, bool on) |
a9533e7e HP |
1249 | { |
1250 | si_info_t *sii; | |
66cbd3ab | 1251 | u32 in, out, outen; |
a9533e7e HP |
1252 | |
1253 | sii = SI_INFO(sih); | |
1254 | ||
fa7a1db2 | 1255 | switch (sih->bustype) { |
a9533e7e HP |
1256 | |
1257 | #ifdef BCMSDIO | |
1258 | case SDIO_BUS: | |
90ea2296 | 1259 | return -1; |
a9533e7e HP |
1260 | #endif /* BCMSDIO */ |
1261 | ||
1262 | case PCI_BUS: | |
1263 | /* pcie core doesn't have any mapping to control the xtal pu */ | |
1264 | if (PCIE(sii)) | |
1265 | return -1; | |
1266 | ||
06d278c5 AS |
1267 | pci_read_config_dword(sii->pbus, PCI_GPIO_IN, &in); |
1268 | pci_read_config_dword(sii->pbus, PCI_GPIO_OUT, &out); | |
1269 | pci_read_config_dword(sii->pbus, PCI_GPIO_OUTEN, &outen); | |
a9533e7e HP |
1270 | |
1271 | /* | |
1272 | * Avoid glitching the clock if GPRS is already using it. | |
1273 | * We can't actually read the state of the PLLPD so we infer it | |
1274 | * by the value of XTAL_PU which *is* readable via gpioin. | |
1275 | */ | |
1276 | if (on && (in & PCI_CFG_GPIO_XTAL)) | |
90ea2296 | 1277 | return 0; |
a9533e7e HP |
1278 | |
1279 | if (what & XTAL) | |
1280 | outen |= PCI_CFG_GPIO_XTAL; | |
1281 | if (what & PLL) | |
1282 | outen |= PCI_CFG_GPIO_PLL; | |
1283 | ||
1284 | if (on) { | |
1285 | /* turn primary xtal on */ | |
1286 | if (what & XTAL) { | |
1287 | out |= PCI_CFG_GPIO_XTAL; | |
1288 | if (what & PLL) | |
1289 | out |= PCI_CFG_GPIO_PLL; | |
06d278c5 | 1290 | pci_write_config_dword(sii->pbus, |
57d8cd23 | 1291 | PCI_GPIO_OUT, out); |
06d278c5 | 1292 | pci_write_config_dword(sii->pbus, |
57d8cd23 | 1293 | PCI_GPIO_OUTEN, outen); |
7383141b | 1294 | udelay(XTAL_ON_DELAY); |
a9533e7e HP |
1295 | } |
1296 | ||
1297 | /* turn pll on */ | |
1298 | if (what & PLL) { | |
1299 | out &= ~PCI_CFG_GPIO_PLL; | |
06d278c5 | 1300 | pci_write_config_dword(sii->pbus, |
57d8cd23 | 1301 | PCI_GPIO_OUT, out); |
7383141b | 1302 | mdelay(2); |
a9533e7e HP |
1303 | } |
1304 | } else { | |
1305 | if (what & XTAL) | |
1306 | out &= ~PCI_CFG_GPIO_XTAL; | |
1307 | if (what & PLL) | |
1308 | out |= PCI_CFG_GPIO_PLL; | |
06d278c5 | 1309 | pci_write_config_dword(sii->pbus, |
57d8cd23 | 1310 | PCI_GPIO_OUT, out); |
06d278c5 | 1311 | pci_write_config_dword(sii->pbus, |
57d8cd23 | 1312 | PCI_GPIO_OUTEN, outen); |
a9533e7e HP |
1313 | } |
1314 | ||
1315 | default: | |
90ea2296 | 1316 | return -1; |
a9533e7e HP |
1317 | } |
1318 | ||
90ea2296 | 1319 | return 0; |
a9533e7e HP |
1320 | } |
1321 | ||
1322 | /* | |
1323 | * clock control policy function throught chipcommon | |
1324 | * | |
1325 | * set dynamic clk control mode (forceslow, forcefast, dynamic) | |
1326 | * returns true if we are forcing fast clock | |
1327 | * this is a wrapper over the next internal function | |
1328 | * to allow flexible policy settings for outside caller | |
1329 | */ | |
7cc4a4c0 | 1330 | bool si_clkctl_cc(si_t *sih, uint mode) |
a9533e7e HP |
1331 | { |
1332 | si_info_t *sii; | |
1333 | ||
1334 | sii = SI_INFO(sih); | |
1335 | ||
1336 | /* chipcommon cores prior to rev6 don't support dynamic clock control */ | |
1337 | if (sih->ccrev < 6) | |
0965ae88 | 1338 | return false; |
a9533e7e HP |
1339 | |
1340 | if (PCI_FORCEHT(sii)) | |
90ea2296 | 1341 | return mode == CLK_FAST; |
a9533e7e HP |
1342 | |
1343 | return _si_clkctl_cc(sii, mode); | |
1344 | } | |
1345 | ||
1346 | /* clk control mechanism through chipcommon, no policy checking */ | |
7cc4a4c0 | 1347 | static bool _si_clkctl_cc(si_info_t *sii, uint mode) |
a9533e7e HP |
1348 | { |
1349 | uint origidx = 0; | |
1350 | chipcregs_t *cc; | |
66cbd3ab | 1351 | u32 scc; |
a9533e7e HP |
1352 | uint intr_val = 0; |
1353 | bool fast = SI_FAST(sii); | |
1354 | ||
1355 | /* chipcommon cores prior to rev6 don't support dynamic clock control */ | |
1356 | if (sii->pub.ccrev < 6) | |
0965ae88 | 1357 | return false; |
a9533e7e HP |
1358 | |
1359 | /* Chips with ccrev 10 are EOL and they don't have SYCC_HR which we use below */ | |
1360 | ASSERT(sii->pub.ccrev != 10); | |
1361 | ||
1362 | if (!fast) { | |
1363 | INTR_OFF(sii, intr_val); | |
1364 | origidx = sii->curidx; | |
1365 | ||
fa7a1db2 | 1366 | if ((sii->pub.bustype == SI_BUS) && |
a9533e7e HP |
1367 | si_setcore(&sii->pub, MIPS33_CORE_ID, 0) && |
1368 | (si_corerev(&sii->pub) <= 7) && (sii->pub.ccrev >= 10)) | |
1369 | goto done; | |
1370 | ||
1371 | cc = (chipcregs_t *) si_setcore(&sii->pub, CC_CORE_ID, 0); | |
ca8c1e59 JC |
1372 | } else { |
1373 | cc = (chipcregs_t *) CCREGS_FAST(sii); | |
1374 | if (cc == NULL) | |
1375 | goto done; | |
1376 | } | |
a9533e7e HP |
1377 | ASSERT(cc != NULL); |
1378 | ||
1379 | if (!CCCTL_ENAB(&sii->pub) && (sii->pub.ccrev < 20)) | |
1380 | goto done; | |
1381 | ||
1382 | switch (mode) { | |
1383 | case CLK_FAST: /* FORCEHT, fast (pll) clock */ | |
1384 | if (sii->pub.ccrev < 10) { | |
1385 | /* don't forget to force xtal back on before we clear SCC_DYN_XTAL.. */ | |
1386 | si_clkctl_xtal(&sii->pub, XTAL, ON); | |
ff31c54c | 1387 | SET_REG(&cc->slow_clk_ctl, |
a9533e7e HP |
1388 | (SCC_XC | SCC_FS | SCC_IP), SCC_IP); |
1389 | } else if (sii->pub.ccrev < 20) { | |
ff31c54c | 1390 | OR_REG(&cc->system_clk_ctl, SYCC_HR); |
a9533e7e | 1391 | } else { |
ff31c54c | 1392 | OR_REG(&cc->clk_ctl_st, CCS_FORCEHT); |
a9533e7e HP |
1393 | } |
1394 | ||
1395 | /* wait for the PLL */ | |
1396 | if (PMUCTL_ENAB(&sii->pub)) { | |
66cbd3ab | 1397 | u32 htavail = CCS_HTAVAIL; |
ff31c54c | 1398 | SPINWAIT(((R_REG(&cc->clk_ctl_st) & htavail) |
a9533e7e | 1399 | == 0), PMU_MAX_TRANSITION_DLY); |
ff31c54c | 1400 | ASSERT(R_REG(&cc->clk_ctl_st) & htavail); |
a9533e7e | 1401 | } else { |
7383141b | 1402 | udelay(PLL_DELAY); |
a9533e7e HP |
1403 | } |
1404 | break; | |
1405 | ||
1406 | case CLK_DYNAMIC: /* enable dynamic clock control */ | |
1407 | if (sii->pub.ccrev < 10) { | |
ff31c54c | 1408 | scc = R_REG(&cc->slow_clk_ctl); |
a9533e7e HP |
1409 | scc &= ~(SCC_FS | SCC_IP | SCC_XC); |
1410 | if ((scc & SCC_SS_MASK) != SCC_SS_XTAL) | |
1411 | scc |= SCC_XC; | |
ff31c54c | 1412 | W_REG(&cc->slow_clk_ctl, scc); |
a9533e7e HP |
1413 | |
1414 | /* for dynamic control, we have to release our xtal_pu "force on" */ | |
1415 | if (scc & SCC_XC) | |
1416 | si_clkctl_xtal(&sii->pub, XTAL, OFF); | |
1417 | } else if (sii->pub.ccrev < 20) { | |
1418 | /* Instaclock */ | |
ff31c54c | 1419 | AND_REG(&cc->system_clk_ctl, ~SYCC_HR); |
a9533e7e | 1420 | } else { |
ff31c54c | 1421 | AND_REG(&cc->clk_ctl_st, ~CCS_FORCEHT); |
a9533e7e HP |
1422 | } |
1423 | break; | |
1424 | ||
1425 | default: | |
1426 | ASSERT(0); | |
1427 | } | |
1428 | ||
1429 | done: | |
1430 | if (!fast) { | |
1431 | si_setcoreidx(&sii->pub, origidx); | |
1432 | INTR_RESTORE(sii, intr_val); | |
1433 | } | |
90ea2296 | 1434 | return mode == CLK_FAST; |
a9533e7e HP |
1435 | } |
1436 | ||
1437 | /* Build device path. Support SI, PCI, and JTAG for now. */ | |
0d2f0724 | 1438 | int si_devpath(si_t *sih, char *path, int size) |
a2627bc0 | 1439 | { |
a9533e7e HP |
1440 | int slen; |
1441 | ||
1442 | ASSERT(path != NULL); | |
1443 | ASSERT(size >= SI_DEVPATH_BUFSZ); | |
1444 | ||
1445 | if (!path || size <= 0) | |
1446 | return -1; | |
1447 | ||
fa7a1db2 | 1448 | switch (sih->bustype) { |
a9533e7e HP |
1449 | case SI_BUS: |
1450 | case JTAG_BUS: | |
1451 | slen = snprintf(path, (size_t) size, "sb/%u/", si_coreidx(sih)); | |
1452 | break; | |
1453 | case PCI_BUS: | |
26bcc181 | 1454 | ASSERT((SI_INFO(sih))->pbus != NULL); |
a9533e7e | 1455 | slen = snprintf(path, (size_t) size, "pci/%u/%u/", |
06d278c5 AS |
1456 | ((struct pci_dev *)((SI_INFO(sih))->pbus))->bus->number, |
1457 | PCI_SLOT( | |
1458 | ((struct pci_dev *)((SI_INFO(sih))->pbus))->devfn)); | |
a9533e7e HP |
1459 | break; |
1460 | ||
1461 | #ifdef BCMSDIO | |
1462 | case SDIO_BUS: | |
1463 | SI_ERROR(("si_devpath: device 0 assumed\n")); | |
1464 | slen = snprintf(path, (size_t) size, "sd/%u/", si_coreidx(sih)); | |
1465 | break; | |
1466 | #endif | |
1467 | default: | |
1468 | slen = -1; | |
1469 | ASSERT(0); | |
1470 | break; | |
1471 | } | |
1472 | ||
1473 | if (slen < 0 || slen >= size) { | |
1474 | path[0] = '\0'; | |
1475 | return -1; | |
1476 | } | |
1477 | ||
1478 | return 0; | |
1479 | } | |
1480 | ||
1481 | /* Get a variable, but only if it has a devpath prefix */ | |
0d2f0724 | 1482 | char *si_getdevpathvar(si_t *sih, const char *name) |
a2627bc0 | 1483 | { |
a9533e7e HP |
1484 | char varname[SI_DEVPATH_BUFSZ + 32]; |
1485 | ||
1486 | si_devpathvar(sih, varname, sizeof(varname), name); | |
1487 | ||
90ea2296 | 1488 | return getvar(NULL, varname); |
a9533e7e HP |
1489 | } |
1490 | ||
1491 | /* Get a variable, but only if it has a devpath prefix */ | |
0d2f0724 | 1492 | int si_getdevpathintvar(si_t *sih, const char *name) |
a2627bc0 | 1493 | { |
a9533e7e | 1494 | #if defined(BCMBUSTYPE) && (BCMBUSTYPE == SI_BUS) |
90ea2296 | 1495 | return getintvar(NULL, name); |
a9533e7e HP |
1496 | #else |
1497 | char varname[SI_DEVPATH_BUFSZ + 32]; | |
1498 | ||
1499 | si_devpathvar(sih, varname, sizeof(varname), name); | |
1500 | ||
90ea2296 | 1501 | return getintvar(NULL, varname); |
a9533e7e HP |
1502 | #endif |
1503 | } | |
1504 | ||
7cc4a4c0 | 1505 | char *si_getnvramflvar(si_t *sih, const char *name) |
a9533e7e | 1506 | { |
90ea2296 | 1507 | return getvar(NULL, name); |
a9533e7e HP |
1508 | } |
1509 | ||
1510 | /* Concatenate the dev path with a varname into the given 'var' buffer | |
1511 | * and return the 'var' pointer. | |
1512 | * Nothing is done to the arguments if len == 0 or var is NULL, var is still returned. | |
1513 | * On overflow, the first char will be set to '\0'. | |
1514 | */ | |
0d2f0724 GKH |
1515 | static char *si_devpathvar(si_t *sih, char *var, int len, const char *name) |
1516 | { | |
a9533e7e HP |
1517 | uint path_len; |
1518 | ||
1519 | if (!var || len <= 0) | |
1520 | return var; | |
1521 | ||
1522 | if (si_devpath(sih, var, len) == 0) { | |
1523 | path_len = strlen(var); | |
1524 | ||
1525 | if (strlen(name) + 1 > (uint) (len - path_len)) | |
1526 | var[0] = '\0'; | |
1527 | else | |
1528 | strncpy(var + path_len, name, len - path_len - 1); | |
1529 | } | |
1530 | ||
1531 | return var; | |
1532 | } | |
1533 | ||
0f0881b0 | 1534 | /* return true if PCIE capability exists in the pci config space */ |
84b9fac2 | 1535 | static __used bool si_ispcie(si_info_t *sii) |
a9533e7e | 1536 | { |
36ef9a1e | 1537 | u8 cap_ptr; |
a9533e7e | 1538 | |
fa7a1db2 | 1539 | if (sii->pub.bustype != PCI_BUS) |
0965ae88 | 1540 | return false; |
a9533e7e HP |
1541 | |
1542 | cap_ptr = | |
06d278c5 | 1543 | pcicore_find_pci_capability(sii->pbus, PCI_CAP_PCIECAP_ID, NULL, |
a9533e7e HP |
1544 | NULL); |
1545 | if (!cap_ptr) | |
0965ae88 | 1546 | return false; |
a9533e7e | 1547 | |
0f0881b0 | 1548 | return true; |
a9533e7e HP |
1549 | } |
1550 | ||
a9533e7e HP |
1551 | #ifdef BCMSDIO |
1552 | /* initialize the sdio core */ | |
7cc4a4c0 | 1553 | void si_sdio_init(si_t *sih) |
a9533e7e HP |
1554 | { |
1555 | si_info_t *sii = SI_INFO(sih); | |
1556 | ||
1557 | if (((sih->buscoretype == PCMCIA_CORE_ID) && (sih->buscorerev >= 8)) || | |
1558 | (sih->buscoretype == SDIOD_CORE_ID)) { | |
1559 | uint idx; | |
1560 | sdpcmd_regs_t *sdpregs; | |
1561 | ||
1562 | /* get the current core index */ | |
1563 | idx = sii->curidx; | |
1564 | ASSERT(idx == si_findcoreidx(sih, D11_CORE_ID, 0)); | |
1565 | ||
1566 | /* switch to sdio core */ | |
ca8c1e59 JC |
1567 | sdpregs = (sdpcmd_regs_t *) si_setcore(sih, PCMCIA_CORE_ID, 0); |
1568 | if (!sdpregs) | |
a9533e7e HP |
1569 | sdpregs = |
1570 | (sdpcmd_regs_t *) si_setcore(sih, SDIOD_CORE_ID, 0); | |
1571 | ASSERT(sdpregs); | |
1572 | ||
1573 | SI_MSG(("si_sdio_init: For PCMCIA/SDIO Corerev %d, enable ints from core %d " "through SD core %d (%p)\n", sih->buscorerev, idx, sii->curidx, sdpregs)); | |
1574 | ||
1575 | /* enable backplane error and core interrupts */ | |
ff31c54c AS |
1576 | W_REG(&sdpregs->hostintmask, I_SBINT); |
1577 | W_REG(&sdpregs->sbintmask, | |
a9533e7e HP |
1578 | (I_SB_SERR | I_SB_RESPERR | (1 << idx))); |
1579 | ||
1580 | /* switch back to previous core */ | |
1581 | si_setcoreidx(sih, idx); | |
1582 | } | |
1583 | ||
1584 | /* enable interrupts */ | |
06d278c5 | 1585 | bcmsdh_intr_enable(sii->pbus); |
a9533e7e HP |
1586 | |
1587 | } | |
1588 | #endif /* BCMSDIO */ | |
1589 | ||
0d2f0724 | 1590 | bool si_pci_war16165(si_t *sih) |
a2627bc0 | 1591 | { |
a9533e7e HP |
1592 | si_info_t *sii; |
1593 | ||
1594 | sii = SI_INFO(sih); | |
1595 | ||
90ea2296 | 1596 | return PCI(sii) && (sih->buscorerev <= 10); |
a9533e7e HP |
1597 | } |
1598 | ||
b4f790ee | 1599 | void si_pci_up(si_t *sih) |
a2627bc0 | 1600 | { |
a9533e7e HP |
1601 | si_info_t *sii; |
1602 | ||
1603 | sii = SI_INFO(sih); | |
1604 | ||
1605 | /* if not pci bus, we're done */ | |
fa7a1db2 | 1606 | if (sih->bustype != PCI_BUS) |
a9533e7e HP |
1607 | return; |
1608 | ||
1609 | if (PCI_FORCEHT(sii)) | |
1610 | _si_clkctl_cc(sii, CLK_FAST); | |
1611 | ||
1612 | if (PCIE(sii)) | |
1613 | pcicore_up(sii->pch, SI_PCIUP); | |
1614 | ||
1615 | } | |
1616 | ||
1617 | /* Unconfigure and/or apply various WARs when system is going to sleep mode */ | |
9927fc2e | 1618 | void si_pci_sleep(si_t *sih) |
a2627bc0 | 1619 | { |
a9533e7e HP |
1620 | si_info_t *sii; |
1621 | ||
1622 | sii = SI_INFO(sih); | |
1623 | ||
1624 | pcicore_sleep(sii->pch); | |
1625 | } | |
1626 | ||
1627 | /* Unconfigure and/or apply various WARs when going down */ | |
b4f790ee | 1628 | void si_pci_down(si_t *sih) |
a2627bc0 | 1629 | { |
a9533e7e HP |
1630 | si_info_t *sii; |
1631 | ||
1632 | sii = SI_INFO(sih); | |
1633 | ||
1634 | /* if not pci bus, we're done */ | |
fa7a1db2 | 1635 | if (sih->bustype != PCI_BUS) |
a9533e7e HP |
1636 | return; |
1637 | ||
1638 | /* release FORCEHT since chip is going to "down" state */ | |
1639 | if (PCI_FORCEHT(sii)) | |
1640 | _si_clkctl_cc(sii, CLK_DYNAMIC); | |
1641 | ||
1642 | pcicore_down(sii->pch, SI_PCIDOWN); | |
1643 | } | |
1644 | ||
1645 | /* | |
1646 | * Configure the pci core for pci client (NIC) action | |
1647 | * coremask is the bitvec of cores by index to be enabled. | |
1648 | */ | |
0d2f0724 | 1649 | void si_pci_setup(si_t *sih, uint coremask) |
a2627bc0 | 1650 | { |
a9533e7e | 1651 | si_info_t *sii; |
c11b0ef8 | 1652 | struct sbpciregs *pciregs = NULL; |
66cbd3ab | 1653 | u32 siflag = 0, w; |
a9533e7e HP |
1654 | uint idx = 0; |
1655 | ||
1656 | sii = SI_INFO(sih); | |
1657 | ||
fa7a1db2 | 1658 | if (sii->pub.bustype != PCI_BUS) |
a9533e7e HP |
1659 | return; |
1660 | ||
1661 | ASSERT(PCI(sii) || PCIE(sii)); | |
1662 | ASSERT(sii->pub.buscoreidx != BADIDX); | |
1663 | ||
1664 | if (PCI(sii)) { | |
1665 | /* get current core index */ | |
1666 | idx = sii->curidx; | |
1667 | ||
1668 | /* we interrupt on this backplane flag number */ | |
1669 | siflag = si_flag(sih); | |
1670 | ||
1671 | /* switch over to pci core */ | |
c11b0ef8 | 1672 | pciregs = (struct sbpciregs *)si_setcoreidx(sih, sii->pub.buscoreidx); |
a9533e7e HP |
1673 | } |
1674 | ||
1675 | /* | |
1676 | * Enable sb->pci interrupts. Assume | |
1677 | * PCI rev 2.3 support was added in pci core rev 6 and things changed.. | |
1678 | */ | |
1679 | if (PCIE(sii) || (PCI(sii) && ((sii->pub.buscorerev) >= 6))) { | |
1680 | /* pci config write to set this core bit in PCIIntMask */ | |
06d278c5 | 1681 | pci_read_config_dword(sii->pbus, PCI_INT_MASK, &w); |
a9533e7e | 1682 | w |= (coremask << PCI_SBIM_SHIFT); |
06d278c5 | 1683 | pci_write_config_dword(sii->pbus, PCI_INT_MASK, w); |
a9533e7e HP |
1684 | } else { |
1685 | /* set sbintvec bit for our flag number */ | |
1686 | si_setint(sih, siflag); | |
1687 | } | |
1688 | ||
1689 | if (PCI(sii)) { | |
ff31c54c | 1690 | OR_REG(&pciregs->sbtopci2, |
a9533e7e HP |
1691 | (SBTOPCI_PREF | SBTOPCI_BURST)); |
1692 | if (sii->pub.buscorerev >= 11) { | |
ff31c54c | 1693 | OR_REG(&pciregs->sbtopci2, |
a9533e7e | 1694 | SBTOPCI_RC_READMULTI); |
ff31c54c AS |
1695 | w = R_REG(&pciregs->clkrun); |
1696 | W_REG(&pciregs->clkrun, | |
a9533e7e | 1697 | (w | PCI_CLKRUN_DSBL)); |
ff31c54c | 1698 | w = R_REG(&pciregs->clkrun); |
a9533e7e HP |
1699 | } |
1700 | ||
1701 | /* switch back to previous core */ | |
1702 | si_setcoreidx(sih, idx); | |
1703 | } | |
1704 | } | |
1705 | ||
a9533e7e HP |
1706 | /* |
1707 | * Fixup SROMless PCI device's configuration. | |
1708 | * The current core may be changed upon return. | |
1709 | */ | |
7cc4a4c0 | 1710 | int si_pci_fixcfg(si_t *sih) |
a9533e7e HP |
1711 | { |
1712 | uint origidx, pciidx; | |
c11b0ef8 | 1713 | struct sbpciregs *pciregs = NULL; |
a9533e7e HP |
1714 | sbpcieregs_t *pcieregs = NULL; |
1715 | void *regs = NULL; | |
7d4df48e | 1716 | u16 val16, *reg16 = NULL; |
a9533e7e HP |
1717 | |
1718 | si_info_t *sii = SI_INFO(sih); | |
1719 | ||
fa7a1db2 | 1720 | ASSERT(sii->pub.bustype == PCI_BUS); |
a9533e7e HP |
1721 | |
1722 | /* Fixup PI in SROM shadow area to enable the correct PCI core access */ | |
1723 | /* save the current index */ | |
1724 | origidx = si_coreidx(&sii->pub); | |
1725 | ||
1726 | /* check 'pi' is correct and fix it if not */ | |
1727 | if (sii->pub.buscoretype == PCIE_CORE_ID) { | |
1728 | pcieregs = | |
1729 | (sbpcieregs_t *) si_setcore(&sii->pub, PCIE_CORE_ID, 0); | |
1730 | regs = pcieregs; | |
1731 | ASSERT(pcieregs != NULL); | |
1732 | reg16 = &pcieregs->sprom[SRSH_PI_OFFSET]; | |
1733 | } else if (sii->pub.buscoretype == PCI_CORE_ID) { | |
c11b0ef8 | 1734 | pciregs = (struct sbpciregs *)si_setcore(&sii->pub, PCI_CORE_ID, 0); |
a9533e7e HP |
1735 | regs = pciregs; |
1736 | ASSERT(pciregs != NULL); | |
1737 | reg16 = &pciregs->sprom[SRSH_PI_OFFSET]; | |
1738 | } | |
1739 | pciidx = si_coreidx(&sii->pub); | |
ff31c54c | 1740 | val16 = R_REG(reg16); |
7d4df48e | 1741 | if (((val16 & SRSH_PI_MASK) >> SRSH_PI_SHIFT) != (u16) pciidx) { |
a9533e7e | 1742 | val16 = |
7d4df48e | 1743 | (u16) (pciidx << SRSH_PI_SHIFT) | (val16 & |
a9533e7e | 1744 | ~SRSH_PI_MASK); |
ff31c54c | 1745 | W_REG(reg16, val16); |
a9533e7e HP |
1746 | } |
1747 | ||
1748 | /* restore the original index */ | |
1749 | si_setcoreidx(&sii->pub, origidx); | |
1750 | ||
1751 | pcicore_hwup(sii->pch); | |
1752 | return 0; | |
1753 | } | |
1754 | ||
a9533e7e | 1755 | /* mask&set gpiocontrol bits */ |
66cbd3ab | 1756 | u32 si_gpiocontrol(si_t *sih, u32 mask, u32 val, u8 priority) |
a9533e7e HP |
1757 | { |
1758 | uint regoff; | |
1759 | ||
1760 | regoff = 0; | |
1761 | ||
1762 | /* gpios could be shared on router platforms | |
1763 | * ignore reservation if it's high priority (e.g., test apps) | |
1764 | */ | |
1765 | if ((priority != GPIO_HI_PRIORITY) && | |
fa7a1db2 | 1766 | (sih->bustype == SI_BUS) && (val || mask)) { |
a9533e7e HP |
1767 | mask = priority ? (si_gpioreservation & mask) : |
1768 | ((si_gpioreservation | mask) & ~(si_gpioreservation)); | |
1769 | val &= mask; | |
1770 | } | |
1771 | ||
ce0f1b8c | 1772 | regoff = offsetof(chipcregs_t, gpiocontrol); |
90ea2296 | 1773 | return si_corereg(sih, SI_CC_IDX, regoff, mask, val); |
a9533e7e HP |
1774 | } |
1775 | ||
1e3950b8 HP |
1776 | /* Return the size of the specified SOCRAM bank */ |
1777 | static uint | |
1778 | socram_banksize(si_info_t *sii, sbsocramregs_t *regs, u8 index, | |
1779 | u8 mem_type) | |
a9533e7e | 1780 | { |
1e3950b8 HP |
1781 | uint banksize, bankinfo; |
1782 | uint bankidx = index | (mem_type << SOCRAM_BANKIDX_MEMTYPE_SHIFT); | |
a9533e7e | 1783 | |
1e3950b8 | 1784 | ASSERT(mem_type <= SOCRAM_MEMTYPE_DEVRAM); |
a9533e7e | 1785 | |
ff31c54c AS |
1786 | W_REG(®s->bankidx, bankidx); |
1787 | bankinfo = R_REG(®s->bankinfo); | |
a9533e7e HP |
1788 | banksize = |
1789 | SOCRAM_BANKINFO_SZBASE * ((bankinfo & SOCRAM_BANKINFO_SZMASK) + 1); | |
1790 | return banksize; | |
1791 | } | |
1792 | ||
a9533e7e | 1793 | /* Return the RAM size of the SOCRAM core */ |
66cbd3ab | 1794 | u32 si_socram_size(si_t *sih) |
a9533e7e HP |
1795 | { |
1796 | si_info_t *sii; | |
1797 | uint origidx; | |
1798 | uint intr_val = 0; | |
1799 | ||
1800 | sbsocramregs_t *regs; | |
1801 | bool wasup; | |
1802 | uint corerev; | |
66cbd3ab | 1803 | u32 coreinfo; |
a9533e7e HP |
1804 | uint memsize = 0; |
1805 | ||
1806 | sii = SI_INFO(sih); | |
1807 | ||
1808 | /* Block ints and save current core */ | |
1809 | INTR_OFF(sii, intr_val); | |
1810 | origidx = si_coreidx(sih); | |
1811 | ||
1812 | /* Switch to SOCRAM core */ | |
ca8c1e59 JC |
1813 | regs = si_setcore(sih, SOCRAM_CORE_ID, 0); |
1814 | if (!regs) | |
a9533e7e HP |
1815 | goto done; |
1816 | ||
1817 | /* Get info for determining size */ | |
ca8c1e59 JC |
1818 | wasup = si_iscoreup(sih); |
1819 | if (!wasup) | |
a9533e7e HP |
1820 | si_core_reset(sih, 0, 0); |
1821 | corerev = si_corerev(sih); | |
ff31c54c | 1822 | coreinfo = R_REG(®s->coreinfo); |
a9533e7e HP |
1823 | |
1824 | /* Calculate size from coreinfo based on rev */ | |
1825 | if (corerev == 0) | |
1826 | memsize = 1 << (16 + (coreinfo & SRCI_MS0_MASK)); | |
1827 | else if (corerev < 3) { | |
1828 | memsize = 1 << (SR_BSZ_BASE + (coreinfo & SRCI_SRBSZ_MASK)); | |
1829 | memsize *= (coreinfo & SRCI_SRNB_MASK) >> SRCI_SRNB_SHIFT; | |
1830 | } else if ((corerev <= 7) || (corerev == 12)) { | |
1831 | uint nb = (coreinfo & SRCI_SRNB_MASK) >> SRCI_SRNB_SHIFT; | |
1832 | uint bsz = (coreinfo & SRCI_SRBSZ_MASK); | |
1833 | uint lss = (coreinfo & SRCI_LSS_MASK) >> SRCI_LSS_SHIFT; | |
1834 | if (lss != 0) | |
1835 | nb--; | |
1836 | memsize = nb * (1 << (bsz + SR_BSZ_BASE)); | |
1837 | if (lss != 0) | |
1838 | memsize += (1 << ((lss - 1) + SR_BSZ_BASE)); | |
1839 | } else { | |
36ef9a1e | 1840 | u8 i; |
a9533e7e HP |
1841 | uint nb = (coreinfo & SRCI_SRNB_MASK) >> SRCI_SRNB_SHIFT; |
1842 | for (i = 0; i < nb; i++) | |
1843 | memsize += | |
1844 | socram_banksize(sii, regs, i, SOCRAM_MEMTYPE_RAM); | |
1845 | } | |
1846 | ||
1847 | /* Return to previous state and core */ | |
1848 | if (!wasup) | |
1849 | si_core_disable(sih, 0); | |
1850 | si_setcoreidx(sih, origidx); | |
1851 | ||
1852 | done: | |
1853 | INTR_RESTORE(sii, intr_val); | |
1854 | ||
1855 | return memsize; | |
1856 | } | |
1857 | ||
7cc4a4c0 | 1858 | void si_chipcontrl_epa4331(si_t *sih, bool on) |
a9533e7e HP |
1859 | { |
1860 | si_info_t *sii; | |
1861 | chipcregs_t *cc; | |
1862 | uint origidx; | |
66cbd3ab | 1863 | u32 val; |
a9533e7e HP |
1864 | |
1865 | sii = SI_INFO(sih); | |
1866 | origidx = si_coreidx(sih); | |
1867 | ||
1868 | cc = (chipcregs_t *) si_setcore(sih, CC_CORE_ID, 0); | |
1869 | ||
ff31c54c | 1870 | val = R_REG(&cc->chipcontrol); |
a9533e7e HP |
1871 | |
1872 | if (on) { | |
1873 | if (sih->chippkg == 9 || sih->chippkg == 0xb) { | |
1874 | /* Ext PA Controls for 4331 12x9 Package */ | |
ff31c54c | 1875 | W_REG(&cc->chipcontrol, val | |
a9533e7e HP |
1876 | (CCTRL4331_EXTPA_EN | |
1877 | CCTRL4331_EXTPA_ON_GPIO2_5)); | |
1878 | } else { | |
1879 | /* Ext PA Controls for 4331 12x12 Package */ | |
ff31c54c | 1880 | W_REG(&cc->chipcontrol, |
a9533e7e HP |
1881 | val | (CCTRL4331_EXTPA_EN)); |
1882 | } | |
1883 | } else { | |
1884 | val &= ~(CCTRL4331_EXTPA_EN | CCTRL4331_EXTPA_ON_GPIO2_5); | |
ff31c54c | 1885 | W_REG(&cc->chipcontrol, val); |
a9533e7e HP |
1886 | } |
1887 | ||
1888 | si_setcoreidx(sih, origidx); | |
1889 | } | |
1890 | ||
1891 | /* Enable BT-COEX & Ex-PA for 4313 */ | |
7cc4a4c0 | 1892 | void si_epa_4313war(si_t *sih) |
a9533e7e HP |
1893 | { |
1894 | si_info_t *sii; | |
1895 | chipcregs_t *cc; | |
1896 | uint origidx; | |
1897 | ||
1898 | sii = SI_INFO(sih); | |
1899 | origidx = si_coreidx(sih); | |
1900 | ||
1901 | cc = (chipcregs_t *) si_setcore(sih, CC_CORE_ID, 0); | |
1902 | ||
1903 | /* EPA Fix */ | |
ff31c54c AS |
1904 | W_REG(&cc->gpiocontrol, |
1905 | R_REG(&cc->gpiocontrol) | GPIO_CTRL_EPA_EN_MASK); | |
a9533e7e HP |
1906 | |
1907 | si_setcoreidx(sih, origidx); | |
1908 | } | |
1909 | ||
1910 | /* check if the device is removed */ | |
7cc4a4c0 | 1911 | bool si_deviceremoved(si_t *sih) |
a9533e7e | 1912 | { |
66cbd3ab | 1913 | u32 w; |
a9533e7e HP |
1914 | si_info_t *sii; |
1915 | ||
1916 | sii = SI_INFO(sih); | |
1917 | ||
fa7a1db2 | 1918 | switch (sih->bustype) { |
a9533e7e | 1919 | case PCI_BUS: |
26bcc181 | 1920 | ASSERT(sii->pbus != NULL); |
06d278c5 | 1921 | pci_read_config_dword(sii->pbus, PCI_CFG_VID, &w); |
a9533e7e | 1922 | if ((w & 0xFFFF) != VENDOR_BROADCOM) |
0f0881b0 | 1923 | return true; |
a9533e7e HP |
1924 | break; |
1925 | } | |
0965ae88 | 1926 | return false; |
a9533e7e HP |
1927 | } |
1928 | ||
7cc4a4c0 | 1929 | bool si_is_sprom_available(si_t *sih) |
a9533e7e HP |
1930 | { |
1931 | if (sih->ccrev >= 31) { | |
1932 | si_info_t *sii; | |
1933 | uint origidx; | |
1934 | chipcregs_t *cc; | |
66cbd3ab | 1935 | u32 sromctrl; |
a9533e7e HP |
1936 | |
1937 | if ((sih->cccaps & CC_CAP_SROM) == 0) | |
0965ae88 | 1938 | return false; |
a9533e7e HP |
1939 | |
1940 | sii = SI_INFO(sih); | |
1941 | origidx = sii->curidx; | |
1942 | cc = si_setcoreidx(sih, SI_CC_IDX); | |
ff31c54c | 1943 | sromctrl = R_REG(&cc->sromcontrol); |
a9533e7e | 1944 | si_setcoreidx(sih, origidx); |
90ea2296 | 1945 | return sromctrl & SRC_PRESENT; |
a9533e7e HP |
1946 | } |
1947 | ||
dfa26436 | 1948 | switch (sih->chip) { |
a9533e7e HP |
1949 | case BCM4329_CHIP_ID: |
1950 | return (sih->chipst & CST4329_SPROM_SEL) != 0; | |
1951 | case BCM4319_CHIP_ID: | |
1952 | return (sih->chipst & CST4319_SPROM_SEL) != 0; | |
1953 | case BCM4336_CHIP_ID: | |
1954 | return (sih->chipst & CST4336_SPROM_PRESENT) != 0; | |
1955 | case BCM4330_CHIP_ID: | |
1956 | return (sih->chipst & CST4330_SPROM_PRESENT) != 0; | |
1957 | case BCM4313_CHIP_ID: | |
1958 | return (sih->chipst & CST4313_SPROM_PRESENT) != 0; | |
1959 | case BCM4331_CHIP_ID: | |
1960 | return (sih->chipst & CST4331_SPROM_PRESENT) != 0; | |
1961 | default: | |
0f0881b0 | 1962 | return true; |
a9533e7e HP |
1963 | } |
1964 | } | |
1965 | ||
7cc4a4c0 | 1966 | bool si_is_otp_disabled(si_t *sih) |
a9533e7e | 1967 | { |
dfa26436 | 1968 | switch (sih->chip) { |
a9533e7e HP |
1969 | case BCM4329_CHIP_ID: |
1970 | return (sih->chipst & CST4329_SPROM_OTP_SEL_MASK) == | |
1971 | CST4329_OTP_PWRDN; | |
1972 | case BCM4319_CHIP_ID: | |
1973 | return (sih->chipst & CST4319_SPROM_OTP_SEL_MASK) == | |
1974 | CST4319_OTP_PWRDN; | |
1975 | case BCM4336_CHIP_ID: | |
90ea2296 | 1976 | return (sih->chipst & CST4336_OTP_PRESENT) == 0; |
a9533e7e | 1977 | case BCM4330_CHIP_ID: |
90ea2296 | 1978 | return (sih->chipst & CST4330_OTP_PRESENT) == 0; |
a9533e7e HP |
1979 | case BCM4313_CHIP_ID: |
1980 | return (sih->chipst & CST4313_OTP_PRESENT) == 0; | |
1981 | /* These chips always have their OTP on */ | |
1982 | case BCM43224_CHIP_ID: | |
1983 | case BCM43225_CHIP_ID: | |
1984 | case BCM43421_CHIP_ID: | |
1985 | case BCM43235_CHIP_ID: | |
1986 | case BCM43236_CHIP_ID: | |
1987 | case BCM43238_CHIP_ID: | |
1988 | case BCM4331_CHIP_ID: | |
1989 | default: | |
0965ae88 | 1990 | return false; |
a9533e7e HP |
1991 | } |
1992 | } | |
1993 | ||
7cc4a4c0 | 1994 | bool si_is_otp_powered(si_t *sih) |
a9533e7e HP |
1995 | { |
1996 | if (PMUCTL_ENAB(sih)) | |
26bcc181 | 1997 | return si_pmu_is_otp_powered(sih); |
0f0881b0 | 1998 | return true; |
a9533e7e HP |
1999 | } |
2000 | ||
7cc4a4c0 | 2001 | void si_otp_power(si_t *sih, bool on) |
a9533e7e HP |
2002 | { |
2003 | if (PMUCTL_ENAB(sih)) | |
26bcc181 | 2004 | si_pmu_otp_power(sih, on); |
7383141b | 2005 | udelay(1000); |
a9533e7e HP |
2006 | } |
2007 |