Merge remote-tracking branch 'staging/staging-next'
[deliverable/linux.git] / drivers / staging / comedi / drivers / dt9812.c
CommitLineData
63274cd7
AB
1/*
2 * comedi/drivers/dt9812.c
3 * COMEDI driver for DataTranslation DT9812 USB module
4 *
5 * Copyright (C) 2005 Anders Blomdell <anders.blomdell@control.lth.se>
6 *
7 * COMEDI - Linux Control and Measurement Device Interface
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
63274cd7
AB
18 */
19
20/*
6c6e8b1a
HS
21 * Driver: dt9812
22 * Description: Data Translation DT9812 USB module
23 * Devices: [Data Translation] DT9812 (dt9812)
24 * Author: anders.blomdell@control.lth.se (Anders Blomdell)
25 * Status: in development
26 * Updated: Sun Nov 20 20:18:34 EST 2005
27 *
28 * This driver works, but bulk transfers not implemented. Might be a
29 * starting point for someone else. I found out too late that USB has
30 * too high latencies (>1 ms) for my needs.
31 */
63274cd7
AB
32
33/*
34 * Nota Bene:
35 * 1. All writes to command pipe has to be 32 bytes (ISP1181B SHRTP=0 ?)
36 * 2. The DDK source (as of sep 2005) is in error regarding the
37 * input MUX bits (example code says P4, but firmware schematics
38 * says P1).
39 */
40
63274cd7 41#include <linux/kernel.h>
ce157f80 42#include <linux/module.h>
63274cd7 43#include <linux/errno.h>
f52a8af7 44#include <linux/uaccess.h>
f52a8af7 45
2079377a 46#include "../comedi_usb.h"
c73190fa
GKH
47
48#define DT9812_DIAGS_BOARD_INFO_ADDR 0xFBFF
49#define DT9812_MAX_WRITE_CMD_PIPE_SIZE 32
50#define DT9812_MAX_READ_CMD_PIPE_SIZE 32
51
548c278c
HS
52/* usb_bulk_msg() timout in milliseconds */
53#define DT9812_USB_TIMEOUT 1000
54
c73190fa
GKH
55/*
56 * See Silican Laboratories C8051F020/1/2/3 manual
57 */
58#define F020_SFR_P4 0x84
59#define F020_SFR_P1 0x90
60#define F020_SFR_P2 0xa0
61#define F020_SFR_P3 0xb0
62#define F020_SFR_AMX0CF 0xba
63#define F020_SFR_AMX0SL 0xbb
64#define F020_SFR_ADC0CF 0xbc
65#define F020_SFR_ADC0L 0xbe
66#define F020_SFR_ADC0H 0xbf
67#define F020_SFR_DAC0L 0xd2
68#define F020_SFR_DAC0H 0xd3
69#define F020_SFR_DAC0CN 0xd4
70#define F020_SFR_DAC1L 0xd5
71#define F020_SFR_DAC1H 0xd6
72#define F020_SFR_DAC1CN 0xd7
73#define F020_SFR_ADC0CN 0xe8
74
75#define F020_MASK_ADC0CF_AMP0GN0 0x01
76#define F020_MASK_ADC0CF_AMP0GN1 0x02
77#define F020_MASK_ADC0CF_AMP0GN2 0x04
78
79#define F020_MASK_ADC0CN_AD0EN 0x80
80#define F020_MASK_ADC0CN_AD0INT 0x20
81#define F020_MASK_ADC0CN_AD0BUSY 0x10
82
00761a9c 83#define F020_MASK_DACXCN_DACXEN 0x80
c73190fa 84
98f3c672 85enum {
3ceba4ba
IA
86 /* A/D D/A DI DO CT */
87 DT9812_DEVID_DT9812_10, /* 8 2 8 8 1 +/- 10V */
88 DT9812_DEVID_DT9812_2PT5, /* 8 2 8 8 1 0-2.44V */
98f3c672 89};
c73190fa 90
98f3c672 91enum dt9812_gain {
c73190fa
GKH
92 DT9812_GAIN_0PT25 = 1,
93 DT9812_GAIN_0PT5 = 2,
94 DT9812_GAIN_1 = 4,
95 DT9812_GAIN_2 = 8,
96 DT9812_GAIN_4 = 16,
97 DT9812_GAIN_8 = 32,
98 DT9812_GAIN_16 = 64,
98f3c672 99};
c73190fa 100
98f3c672 101enum {
c73190fa
GKH
102 DT9812_LEAST_USB_FIRMWARE_CMD_CODE = 0,
103 /* Write Flash memory */
104 DT9812_W_FLASH_DATA = 0,
105 /* Read Flash memory misc config info */
106 DT9812_R_FLASH_DATA = 1,
107
108 /*
109 * Register read/write commands for processor
110 */
111
112 /* Read a single byte of USB memory */
113 DT9812_R_SINGLE_BYTE_REG = 2,
114 /* Write a single byte of USB memory */
115 DT9812_W_SINGLE_BYTE_REG = 3,
116 /* Multiple Reads of USB memory */
117 DT9812_R_MULTI_BYTE_REG = 4,
118 /* Multiple Writes of USB memory */
119 DT9812_W_MULTI_BYTE_REG = 5,
120 /* Read, (AND) with mask, OR value, then write (single) */
121 DT9812_RMW_SINGLE_BYTE_REG = 6,
122 /* Read, (AND) with mask, OR value, then write (multiple) */
123 DT9812_RMW_MULTI_BYTE_REG = 7,
124
125 /*
126 * Register read/write commands for SMBus
127 */
128
129 /* Read a single byte of SMBus */
130 DT9812_R_SINGLE_BYTE_SMBUS = 8,
131 /* Write a single byte of SMBus */
132 DT9812_W_SINGLE_BYTE_SMBUS = 9,
133 /* Multiple Reads of SMBus */
134 DT9812_R_MULTI_BYTE_SMBUS = 10,
135 /* Multiple Writes of SMBus */
136 DT9812_W_MULTI_BYTE_SMBUS = 11,
137
138 /*
139 * Register read/write commands for a device
140 */
141
142 /* Read a single byte of a device */
143 DT9812_R_SINGLE_BYTE_DEV = 12,
144 /* Write a single byte of a device */
145 DT9812_W_SINGLE_BYTE_DEV = 13,
146 /* Multiple Reads of a device */
147 DT9812_R_MULTI_BYTE_DEV = 14,
148 /* Multiple Writes of a device */
149 DT9812_W_MULTI_BYTE_DEV = 15,
150
151 /* Not sure if we'll need this */
152 DT9812_W_DAC_THRESHOLD = 16,
153
154 /* Set interrupt on change mask */
155 DT9812_W_INT_ON_CHANGE_MASK = 17,
156
157 /* Write (or Clear) the CGL for the ADC */
158 DT9812_W_CGL = 18,
159 /* Multiple Reads of USB memory */
160 DT9812_R_MULTI_BYTE_USBMEM = 19,
161 /* Multiple Writes to USB memory */
162 DT9812_W_MULTI_BYTE_USBMEM = 20,
163
164 /* Issue a start command to a given subsystem */
165 DT9812_START_SUBSYSTEM = 21,
166 /* Issue a stop command to a given subsystem */
167 DT9812_STOP_SUBSYSTEM = 22,
168
169 /* calibrate the board using CAL_POT_CMD */
170 DT9812_CALIBRATE_POT = 23,
171 /* set the DAC FIFO size */
172 DT9812_W_DAC_FIFO_SIZE = 24,
173 /* Write or Clear the CGL for the DAC */
174 DT9812_W_CGL_DAC = 25,
175 /* Read a single value from a subsystem */
176 DT9812_R_SINGLE_VALUE_CMD = 26,
177 /* Write a single value to a subsystem */
178 DT9812_W_SINGLE_VALUE_CMD = 27,
179 /* Valid DT9812_USB_FIRMWARE_CMD_CODE's will be less than this number */
180 DT9812_MAX_USB_FIRMWARE_CMD_CODE,
98f3c672 181};
c73190fa 182
98f3c672 183struct dt9812_flash_data {
70bcbc06
SL
184 __le16 numbytes;
185 __le16 address;
98f3c672 186};
c73190fa
GKH
187
188#define DT9812_MAX_NUM_MULTI_BYTE_RDS \
65c5cfa6 189 ((DT9812_MAX_WRITE_CMD_PIPE_SIZE - 4 - 1) / sizeof(u8))
c73190fa 190
98f3c672 191struct dt9812_read_multi {
c73190fa
GKH
192 u8 count;
193 u8 address[DT9812_MAX_NUM_MULTI_BYTE_RDS];
98f3c672 194};
c73190fa 195
98f3c672 196struct dt9812_write_byte {
c73190fa
GKH
197 u8 address;
198 u8 value;
98f3c672 199};
c73190fa
GKH
200
201#define DT9812_MAX_NUM_MULTI_BYTE_WRTS \
65c5cfa6
RKM
202 ((DT9812_MAX_WRITE_CMD_PIPE_SIZE - 4 - 1) / \
203 sizeof(struct dt9812_write_byte))
c73190fa 204
98f3c672 205struct dt9812_write_multi {
c73190fa 206 u8 count;
98f3c672
GKH
207 struct dt9812_write_byte write[DT9812_MAX_NUM_MULTI_BYTE_WRTS];
208};
c73190fa 209
98f3c672 210struct dt9812_rmw_byte {
c73190fa
GKH
211 u8 address;
212 u8 and_mask;
213 u8 or_value;
98f3c672 214};
c73190fa
GKH
215
216#define DT9812_MAX_NUM_MULTI_BYTE_RMWS \
65c5cfa6
RKM
217 ((DT9812_MAX_WRITE_CMD_PIPE_SIZE - 4 - 1) / \
218 sizeof(struct dt9812_rmw_byte))
c73190fa 219
98f3c672 220struct dt9812_rmw_multi {
c73190fa 221 u8 count;
98f3c672
GKH
222 struct dt9812_rmw_byte rmw[DT9812_MAX_NUM_MULTI_BYTE_RMWS];
223};
c73190fa 224
98f3c672 225struct dt9812_usb_cmd {
70bcbc06 226 __le32 cmd;
c73190fa 227 union {
98f3c672
GKH
228 struct dt9812_flash_data flash_data_info;
229 struct dt9812_read_multi read_multi_info;
230 struct dt9812_write_multi write_multi_info;
231 struct dt9812_rmw_multi rmw_multi_info;
c73190fa 232 } u;
98f3c672 233};
63274cd7 234
b78750c1 235struct dt9812_private {
9faa310f 236 struct mutex mut;
63274cd7
AB
237 struct {
238 __u8 addr;
239 size_t size;
387d4879 240 } cmd_wr, cmd_rd;
b78750c1 241 u16 device;
98f3c672 242};
63274cd7 243
b78750c1
HS
244static int dt9812_read_info(struct comedi_device *dev,
245 int offset, void *buf, size_t buf_size)
63274cd7 246{
87d87adc 247 struct usb_device *usb = comedi_to_usb_dev(dev);
b78750c1 248 struct dt9812_private *devpriv = dev->private;
98f3c672 249 struct dt9812_usb_cmd cmd;
0ec77d34 250 int count, ret;
63274cd7
AB
251
252 cmd.cmd = cpu_to_le32(DT9812_R_FLASH_DATA);
253 cmd.u.flash_data_info.address =
0a85b6f0 254 cpu_to_le16(DT9812_DIAGS_BOARD_INFO_ADDR + offset);
63274cd7
AB
255 cmd.u.flash_data_info.numbytes = cpu_to_le16(buf_size);
256
f52a8af7 257 /* DT9812 only responds to 32 byte writes!! */
b78750c1 258 ret = usb_bulk_msg(usb, usb_sndbulkpipe(usb, devpriv->cmd_wr.addr),
548c278c 259 &cmd, 32, &count, DT9812_USB_TIMEOUT);
0ec77d34
HS
260 if (ret)
261 return ret;
262
b78750c1 263 return usb_bulk_msg(usb, usb_rcvbulkpipe(usb, devpriv->cmd_rd.addr),
548c278c 264 buf, buf_size, &count, DT9812_USB_TIMEOUT);
63274cd7
AB
265}
266
b78750c1
HS
267static int dt9812_read_multiple_registers(struct comedi_device *dev,
268 int reg_count, u8 *address,
269 u8 *value)
63274cd7 270{
87d87adc 271 struct usb_device *usb = comedi_to_usb_dev(dev);
b78750c1 272 struct dt9812_private *devpriv = dev->private;
98f3c672 273 struct dt9812_usb_cmd cmd;
0ec77d34 274 int i, count, ret;
63274cd7
AB
275
276 cmd.cmd = cpu_to_le32(DT9812_R_MULTI_BYTE_REG);
277 cmd.u.read_multi_info.count = reg_count;
f52a8af7 278 for (i = 0; i < reg_count; i++)
63274cd7 279 cmd.u.read_multi_info.address[i] = address[i];
f52a8af7
GKH
280
281 /* DT9812 only responds to 32 byte writes!! */
b78750c1 282 ret = usb_bulk_msg(usb, usb_sndbulkpipe(usb, devpriv->cmd_wr.addr),
548c278c 283 &cmd, 32, &count, DT9812_USB_TIMEOUT);
0ec77d34
HS
284 if (ret)
285 return ret;
286
b78750c1 287 return usb_bulk_msg(usb, usb_rcvbulkpipe(usb, devpriv->cmd_rd.addr),
548c278c 288 value, reg_count, &count, DT9812_USB_TIMEOUT);
63274cd7
AB
289}
290
b78750c1 291static int dt9812_write_multiple_registers(struct comedi_device *dev,
a7a55d4a
RKM
292 int reg_count, u8 *address,
293 u8 *value)
63274cd7 294{
87d87adc 295 struct usb_device *usb = comedi_to_usb_dev(dev);
b78750c1 296 struct dt9812_private *devpriv = dev->private;
98f3c672 297 struct dt9812_usb_cmd cmd;
0ec77d34 298 int i, count;
63274cd7
AB
299
300 cmd.cmd = cpu_to_le32(DT9812_W_MULTI_BYTE_REG);
301 cmd.u.read_multi_info.count = reg_count;
302 for (i = 0; i < reg_count; i++) {
303 cmd.u.write_multi_info.write[i].address = address[i];
304 cmd.u.write_multi_info.write[i].value = value[i];
305 }
0ec77d34 306
f52a8af7 307 /* DT9812 only responds to 32 byte writes!! */
b78750c1 308 return usb_bulk_msg(usb, usb_sndbulkpipe(usb, devpriv->cmd_wr.addr),
548c278c 309 &cmd, 32, &count, DT9812_USB_TIMEOUT);
63274cd7
AB
310}
311
b78750c1
HS
312static int dt9812_rmw_multiple_registers(struct comedi_device *dev,
313 int reg_count,
98f3c672 314 struct dt9812_rmw_byte *rmw)
63274cd7 315{
87d87adc 316 struct usb_device *usb = comedi_to_usb_dev(dev);
b78750c1 317 struct dt9812_private *devpriv = dev->private;
98f3c672 318 struct dt9812_usb_cmd cmd;
0ec77d34 319 int i, count;
63274cd7
AB
320
321 cmd.cmd = cpu_to_le32(DT9812_RMW_MULTI_BYTE_REG);
322 cmd.u.rmw_multi_info.count = reg_count;
f52a8af7 323 for (i = 0; i < reg_count; i++)
63274cd7 324 cmd.u.rmw_multi_info.rmw[i] = rmw[i];
f52a8af7
GKH
325
326 /* DT9812 only responds to 32 byte writes!! */
b78750c1 327 return usb_bulk_msg(usb, usb_sndbulkpipe(usb, devpriv->cmd_wr.addr),
548c278c 328 &cmd, 32, &count, DT9812_USB_TIMEOUT);
63274cd7
AB
329}
330
4bc839f2 331static int dt9812_digital_in(struct comedi_device *dev, u8 *bits)
63274cd7 332{
4bc839f2 333 struct dt9812_private *devpriv = dev->private;
b78750c1
HS
334 u8 reg[2] = { F020_SFR_P3, F020_SFR_P1 };
335 u8 value[2];
336 int ret;
63274cd7 337
9faa310f 338 mutex_lock(&devpriv->mut);
b78750c1
HS
339 ret = dt9812_read_multiple_registers(dev, 2, reg, value);
340 if (ret == 0) {
341 /*
342 * bits 0-6 in F020_SFR_P3 are bits 0-6 in the digital
343 * input port bit 3 in F020_SFR_P1 is bit 7 in the
344 * digital input port
345 */
346 *bits = (value[0] & 0x7f) | ((value[1] & 0x08) << 4);
63274cd7 347 }
9faa310f 348 mutex_unlock(&devpriv->mut);
63274cd7 349
4bc839f2 350 return ret;
63274cd7
AB
351}
352
51af6fa1 353static int dt9812_digital_out(struct comedi_device *dev, u8 bits)
63274cd7 354{
51af6fa1 355 struct dt9812_private *devpriv = dev->private;
b78750c1
HS
356 u8 reg[1] = { F020_SFR_P2 };
357 u8 value[1] = { bits };
358 int ret;
63274cd7 359
9faa310f 360 mutex_lock(&devpriv->mut);
b78750c1 361 ret = dt9812_write_multiple_registers(dev, 1, reg, value);
9faa310f 362 mutex_unlock(&devpriv->mut);
51af6fa1
HS
363
364 return ret;
63274cd7
AB
365}
366
687d8479 367static void dt9812_configure_mux(struct comedi_device *dev,
98f3c672 368 struct dt9812_rmw_byte *rmw, int channel)
63274cd7 369{
687d8479 370 struct dt9812_private *devpriv = dev->private;
687d8479 371
b78750c1 372 if (devpriv->device == DT9812_DEVID_DT9812_10) {
f52a8af7 373 /* In the DT9812/10V MUX is selected by P1.5-7 */
63274cd7
AB
374 rmw->address = F020_SFR_P1;
375 rmw->and_mask = 0xe0;
376 rmw->or_value = channel << 5;
377 } else {
f52a8af7 378 /* In the DT9812/2.5V, internal mux is selected by bits 0:2 */
63274cd7
AB
379 rmw->address = F020_SFR_AMX0SL;
380 rmw->and_mask = 0xff;
381 rmw->or_value = channel & 0x07;
382 }
383}
384
be8f16de 385static void dt9812_configure_gain(struct comedi_device *dev,
98f3c672
GKH
386 struct dt9812_rmw_byte *rmw,
387 enum dt9812_gain gain)
63274cd7 388{
be8f16de 389 struct dt9812_private *devpriv = dev->private;
be8f16de
HS
390
391 /* In the DT9812/10V, there is an external gain of 0.5 */
b78750c1 392 if (devpriv->device == DT9812_DEVID_DT9812_10)
63274cd7 393 gain <<= 1;
63274cd7
AB
394
395 rmw->address = F020_SFR_ADC0CF;
f52a8af7 396 rmw->and_mask = F020_MASK_ADC0CF_AMP0GN2 |
be8f16de
HS
397 F020_MASK_ADC0CF_AMP0GN1 |
398 F020_MASK_ADC0CF_AMP0GN0;
399
63274cd7 400 switch (gain) {
f52a8af7
GKH
401 /*
402 * 000 -> Gain = 1
403 * 001 -> Gain = 2
404 * 010 -> Gain = 4
405 * 011 -> Gain = 8
406 * 10x -> Gain = 16
407 * 11x -> Gain = 0.5
408 */
409 case DT9812_GAIN_0PT5:
cba2c993 410 rmw->or_value = F020_MASK_ADC0CF_AMP0GN2 |
be8f16de 411 F020_MASK_ADC0CF_AMP0GN1;
63274cd7 412 break;
d6caedf0
HS
413 default:
414 /* this should never happen, just use a gain of 1 */
f52a8af7
GKH
415 case DT9812_GAIN_1:
416 rmw->or_value = 0x00;
63274cd7 417 break;
f52a8af7
GKH
418 case DT9812_GAIN_2:
419 rmw->or_value = F020_MASK_ADC0CF_AMP0GN0;
63274cd7 420 break;
f52a8af7
GKH
421 case DT9812_GAIN_4:
422 rmw->or_value = F020_MASK_ADC0CF_AMP0GN1;
63274cd7 423 break;
f52a8af7 424 case DT9812_GAIN_8:
cba2c993 425 rmw->or_value = F020_MASK_ADC0CF_AMP0GN1 |
be8f16de 426 F020_MASK_ADC0CF_AMP0GN0;
63274cd7 427 break;
f52a8af7
GKH
428 case DT9812_GAIN_16:
429 rmw->or_value = F020_MASK_ADC0CF_AMP0GN2;
63274cd7 430 break;
63274cd7
AB
431 }
432}
433
c13626a2
HS
434static int dt9812_analog_in(struct comedi_device *dev,
435 int channel, u16 *value, enum dt9812_gain gain)
63274cd7 436{
c13626a2 437 struct dt9812_private *devpriv = dev->private;
98f3c672 438 struct dt9812_rmw_byte rmw[3];
f52a8af7
GKH
439 u8 reg[3] = {
440 F020_SFR_ADC0CN,
441 F020_SFR_ADC0H,
442 F020_SFR_ADC0L
443 };
444 u8 val[3];
b78750c1 445 int ret;
63274cd7 446
9faa310f 447 mutex_lock(&devpriv->mut);
f52a8af7
GKH
448
449 /* 1 select the gain */
be8f16de 450 dt9812_configure_gain(dev, &rmw[0], gain);
f52a8af7
GKH
451
452 /* 2 set the MUX to select the channel */
687d8479 453 dt9812_configure_mux(dev, &rmw[1], channel);
f52a8af7
GKH
454
455 /* 3 start conversion */
456 rmw[2].address = F020_SFR_ADC0CN;
457 rmw[2].and_mask = 0xff;
458 rmw[2].or_value = F020_MASK_ADC0CN_AD0EN | F020_MASK_ADC0CN_AD0BUSY;
459
b78750c1 460 ret = dt9812_rmw_multiple_registers(dev, 3, rmw);
c13626a2 461 if (ret)
f52a8af7
GKH
462 goto exit;
463
464 /* read the status and ADC */
b78750c1 465 ret = dt9812_read_multiple_registers(dev, 3, reg, val);
c13626a2 466 if (ret)
f52a8af7 467 goto exit;
c13626a2 468
f52a8af7
GKH
469 /*
470 * An ADC conversion takes 16 SAR clocks cycles, i.e. about 9us.
471 * Therefore, between the instant that AD0BUSY was set via
472 * dt9812_rmw_multiple_registers and the read of AD0BUSY via
473 * dt9812_read_multiple_registers, the conversion should be complete
474 * since these two operations require two USB transactions each taking
475 * at least a millisecond to complete. However, lets make sure that
476 * conversion is finished.
477 */
478 if ((val[0] & (F020_MASK_ADC0CN_AD0INT | F020_MASK_ADC0CN_AD0BUSY)) ==
479 F020_MASK_ADC0CN_AD0INT) {
b78750c1 480 switch (devpriv->device) {
f52a8af7
GKH
481 case DT9812_DEVID_DT9812_10:
482 /*
483 * For DT9812-10V the personality module set the
484 * encoding to 2's complement. Hence, convert it before
485 * returning it
486 */
487 *value = ((val[1] << 8) | val[2]) + 0x800;
488 break;
489 case DT9812_DEVID_DT9812_2PT5:
490 *value = (val[1] << 8) | val[2];
491 break;
63274cd7
AB
492 }
493 }
f52a8af7
GKH
494
495exit:
9faa310f 496 mutex_unlock(&devpriv->mut);
c13626a2
HS
497
498 return ret;
63274cd7
AB
499}
500
9d231df8 501static int dt9812_analog_out(struct comedi_device *dev, int channel, u16 value)
63274cd7 502{
9d231df8 503 struct dt9812_private *devpriv = dev->private;
b78750c1
HS
504 struct dt9812_rmw_byte rmw[3];
505 int ret;
63274cd7 506
9faa310f 507 mutex_lock(&devpriv->mut);
63274cd7 508
b78750c1
HS
509 switch (channel) {
510 case 0:
511 /* 1. Set DAC mode */
512 rmw[0].address = F020_SFR_DAC0CN;
513 rmw[0].and_mask = 0xff;
00761a9c 514 rmw[0].or_value = F020_MASK_DACXCN_DACXEN;
b78750c1 515
5050b135 516 /* 2. load lsb of DAC value first */
b78750c1
HS
517 rmw[1].address = F020_SFR_DAC0L;
518 rmw[1].and_mask = 0xff;
519 rmw[1].or_value = value & 0xff;
520
5050b135 521 /* 3. load msb of DAC value next to latch the 12-bit value */
b78750c1
HS
522 rmw[2].address = F020_SFR_DAC0H;
523 rmw[2].and_mask = 0xff;
524 rmw[2].or_value = (value >> 8) & 0xf;
525 break;
f52a8af7 526
b78750c1
HS
527 case 1:
528 /* 1. Set DAC mode */
529 rmw[0].address = F020_SFR_DAC1CN;
530 rmw[0].and_mask = 0xff;
00761a9c 531 rmw[0].or_value = F020_MASK_DACXCN_DACXEN;
b78750c1 532
5050b135 533 /* 2. load lsb of DAC value first */
b78750c1
HS
534 rmw[1].address = F020_SFR_DAC1L;
535 rmw[1].and_mask = 0xff;
536 rmw[1].or_value = value & 0xff;
537
5050b135 538 /* 3. load msb of DAC value next to latch the 12-bit value */
b78750c1
HS
539 rmw[2].address = F020_SFR_DAC1H;
540 rmw[2].and_mask = 0xff;
541 rmw[2].or_value = (value >> 8) & 0xf;
542 break;
63274cd7 543 }
b78750c1 544 ret = dt9812_rmw_multiple_registers(dev, 3, rmw);
b78750c1 545
9faa310f 546 mutex_unlock(&devpriv->mut);
63274cd7 547
9d231df8 548 return ret;
63274cd7
AB
549}
550
e81eaba6
HS
551static int dt9812_di_insn_bits(struct comedi_device *dev,
552 struct comedi_subdevice *s,
553 struct comedi_insn *insn,
554 unsigned int *data)
63274cd7 555{
63274cd7 556 u8 bits = 0;
e81eaba6 557 int ret;
63274cd7 558
e81eaba6
HS
559 ret = dt9812_digital_in(dev, &bits);
560 if (ret)
561 return ret;
562
563 data[1] = bits;
564
565 return insn->n;
63274cd7
AB
566}
567
36c973d0
HS
568static int dt9812_do_insn_bits(struct comedi_device *dev,
569 struct comedi_subdevice *s,
570 struct comedi_insn *insn,
571 unsigned int *data)
63274cd7 572{
97f4289a 573 if (comedi_dio_update_state(s, data))
36c973d0 574 dt9812_digital_out(dev, s->state);
36c973d0
HS
575
576 data[1] = s->state;
577
578 return insn->n;
63274cd7
AB
579}
580
83a69f5a
HS
581static int dt9812_ai_insn_read(struct comedi_device *dev,
582 struct comedi_subdevice *s,
583 struct comedi_insn *insn,
584 unsigned int *data)
63274cd7 585{
83a69f5a
HS
586 unsigned int chan = CR_CHAN(insn->chanspec);
587 u16 val = 0;
588 int ret;
589 int i;
63274cd7 590
83a69f5a
HS
591 for (i = 0; i < insn->n; i++) {
592 ret = dt9812_analog_in(dev, chan, &val, DT9812_GAIN_1);
593 if (ret)
594 return ret;
595 data[i] = val;
63274cd7 596 }
83a69f5a
HS
597
598 return insn->n;
63274cd7
AB
599}
600
e79f18e6
HS
601static int dt9812_ao_insn_read(struct comedi_device *dev,
602 struct comedi_subdevice *s,
603 struct comedi_insn *insn,
604 unsigned int *data)
63274cd7 605{
e79f18e6 606 struct dt9812_private *devpriv = dev->private;
acc5fe2c 607 int ret;
63274cd7 608
9faa310f 609 mutex_lock(&devpriv->mut);
acc5fe2c 610 ret = comedi_readback_insn_read(dev, s, insn, data);
9faa310f 611 mutex_unlock(&devpriv->mut);
e79f18e6 612
acc5fe2c 613 return ret;
63274cd7
AB
614}
615
99928e65
HS
616static int dt9812_ao_insn_write(struct comedi_device *dev,
617 struct comedi_subdevice *s,
618 struct comedi_insn *insn,
619 unsigned int *data)
63274cd7 620{
99928e65 621 unsigned int chan = CR_CHAN(insn->chanspec);
99928e65 622 int i;
63274cd7 623
99928e65 624 for (i = 0; i < insn->n; i++) {
acc5fe2c
HS
625 unsigned int val = data[i];
626 int ret;
627
628 ret = dt9812_analog_out(dev, chan, val);
99928e65
HS
629 if (ret)
630 return ret;
acc5fe2c
HS
631
632 s->readback[chan] = val;
99928e65
HS
633 }
634
635 return insn->n;
63274cd7
AB
636}
637
b78750c1 638static int dt9812_find_endpoints(struct comedi_device *dev)
8ee26468 639{
b78750c1 640 struct usb_interface *intf = comedi_to_usb_interface(dev);
8ee26468 641 struct usb_host_interface *host = intf->cur_altsetting;
b78750c1 642 struct dt9812_private *devpriv = dev->private;
8ee26468
HS
643 struct usb_endpoint_descriptor *ep;
644 int i;
645
646 if (host->desc.bNumEndpoints != 5) {
056254fa 647 dev_err(dev->class_dev, "Wrong number of endpoints\n");
8ee26468
HS
648 return -ENODEV;
649 }
650
651 for (i = 0; i < host->desc.bNumEndpoints; ++i) {
652 int dir = -1;
98039f8a 653
8ee26468
HS
654 ep = &host->endpoint[i].desc;
655 switch (i) {
656 case 0:
657 /* unused message pipe */
658 dir = USB_DIR_IN;
659 break;
660 case 1:
661 dir = USB_DIR_OUT;
662 devpriv->cmd_wr.addr = ep->bEndpointAddress;
62190d49 663 devpriv->cmd_wr.size = usb_endpoint_maxp(ep);
8ee26468
HS
664 break;
665 case 2:
666 dir = USB_DIR_IN;
667 devpriv->cmd_rd.addr = ep->bEndpointAddress;
62190d49 668 devpriv->cmd_rd.size = usb_endpoint_maxp(ep);
8ee26468
HS
669 break;
670 case 3:
671 /* unused write stream */
672 dir = USB_DIR_OUT;
673 break;
674 case 4:
675 /* unused read stream */
676 dir = USB_DIR_IN;
677 break;
678 }
679 if ((ep->bEndpointAddress & USB_DIR_IN) != dir) {
056254fa
HS
680 dev_err(dev->class_dev,
681 "Endpoint has wrong direction\n");
8ee26468
HS
682 return -ENODEV;
683 }
684 }
685 return 0;
686}
687
b78750c1 688static int dt9812_reset_device(struct comedi_device *dev)
8db1eba1 689{
87d87adc 690 struct usb_device *usb = comedi_to_usb_dev(dev);
b78750c1 691 struct dt9812_private *devpriv = dev->private;
421b42ab
HS
692 u32 serial;
693 u16 vendor;
694 u16 product;
8db1eba1 695 u8 tmp8;
e4ea910a
SL
696 __le16 tmp16;
697 __le32 tmp32;
421b42ab
HS
698 int ret;
699 int i;
8db1eba1 700
b78750c1 701 ret = dt9812_read_info(dev, 0, &tmp8, sizeof(tmp8));
8db1eba1
HS
702 if (ret) {
703 /*
704 * Seems like a configuration reset is necessary if driver is
705 * reloaded while device is attached
706 */
b78750c1 707 usb_reset_configuration(usb);
8db1eba1 708 for (i = 0; i < 10; i++) {
b78750c1 709 ret = dt9812_read_info(dev, 1, &tmp8, sizeof(tmp8));
8db1eba1
HS
710 if (ret == 0)
711 break;
712 }
713 if (ret) {
056254fa
HS
714 dev_err(dev->class_dev,
715 "unable to reset configuration\n");
8db1eba1
HS
716 return ret;
717 }
718 }
719
e4ea910a 720 ret = dt9812_read_info(dev, 1, &tmp16, sizeof(tmp16));
8db1eba1 721 if (ret) {
056254fa 722 dev_err(dev->class_dev, "failed to read vendor id\n");
8db1eba1
HS
723 return ret;
724 }
e4ea910a 725 vendor = le16_to_cpu(tmp16);
8db1eba1 726
e4ea910a 727 ret = dt9812_read_info(dev, 3, &tmp16, sizeof(tmp16));
8db1eba1 728 if (ret) {
056254fa 729 dev_err(dev->class_dev, "failed to read product id\n");
8db1eba1
HS
730 return ret;
731 }
e4ea910a 732 product = le16_to_cpu(tmp16);
8db1eba1 733
b78750c1 734 ret = dt9812_read_info(dev, 5, &tmp16, sizeof(tmp16));
8db1eba1 735 if (ret) {
056254fa 736 dev_err(dev->class_dev, "failed to read device id\n");
8db1eba1
HS
737 return ret;
738 }
739 devpriv->device = le16_to_cpu(tmp16);
740
e4ea910a 741 ret = dt9812_read_info(dev, 7, &tmp32, sizeof(tmp32));
8db1eba1 742 if (ret) {
056254fa 743 dev_err(dev->class_dev, "failed to read serial number\n");
8db1eba1
HS
744 return ret;
745 }
e4ea910a 746 serial = le32_to_cpu(tmp32);
8db1eba1
HS
747
748 /* let the user know what node this device is now attached to */
056254fa 749 dev_info(dev->class_dev, "USB DT9812 (%4.4x.%4.4x.%4.4x) #0x%8.8x\n",
421b42ab 750 vendor, product, devpriv->device, serial);
8db1eba1 751
9a054c27
HS
752 if (devpriv->device != DT9812_DEVID_DT9812_10 &&
753 devpriv->device != DT9812_DEVID_DT9812_2PT5) {
754 dev_err(dev->class_dev, "Unsupported device!\n");
755 return -EINVAL;
756 }
757
8db1eba1
HS
758 return 0;
759}
760
b78750c1
HS
761static int dt9812_auto_attach(struct comedi_device *dev,
762 unsigned long context)
63274cd7 763{
b78750c1 764 struct usb_interface *intf = comedi_to_usb_interface(dev);
415227c1 765 struct dt9812_private *devpriv;
34c43922 766 struct comedi_subdevice *s;
135a0009 767 bool is_unipolar;
8b6c5694 768 int ret;
acc5fe2c 769 int i;
63274cd7 770
0bdab509 771 devpriv = comedi_alloc_devpriv(dev, sizeof(*devpriv));
c34fa261
HS
772 if (!devpriv)
773 return -ENOMEM;
f52a8af7 774
9faa310f 775 mutex_init(&devpriv->mut);
b78750c1 776 usb_set_intfdata(intf, devpriv);
1415003f 777
b78750c1
HS
778 ret = dt9812_find_endpoints(dev);
779 if (ret)
780 return ret;
63274cd7 781
b78750c1
HS
782 ret = dt9812_reset_device(dev);
783 if (ret)
784 return ret;
1415003f 785
b78750c1 786 is_unipolar = (devpriv->device == DT9812_DEVID_DT9812_2PT5);
63274cd7 787
8b6c5694
HS
788 ret = comedi_alloc_subdevices(dev, 4);
789 if (ret)
790 return ret;
63274cd7 791
b78750c1 792 /* Digital Input subdevice */
3a207891 793 s = &dev->subdevices[0];
b78750c1
HS
794 s->type = COMEDI_SUBD_DI;
795 s->subdev_flags = SDF_READABLE;
796 s->n_chan = 8;
797 s->maxdata = 1;
798 s->range_table = &range_digital;
e81eaba6 799 s->insn_bits = dt9812_di_insn_bits;
b78750c1
HS
800
801 /* Digital Output subdevice */
3a207891 802 s = &dev->subdevices[1];
b78750c1 803 s->type = COMEDI_SUBD_DO;
ef49d832 804 s->subdev_flags = SDF_WRITABLE;
b78750c1
HS
805 s->n_chan = 8;
806 s->maxdata = 1;
807 s->range_table = &range_digital;
36c973d0 808 s->insn_bits = dt9812_do_insn_bits;
135a0009 809
b78750c1 810 /* Analog Input subdevice */
3a207891 811 s = &dev->subdevices[2];
b78750c1
HS
812 s->type = COMEDI_SUBD_AI;
813 s->subdev_flags = SDF_READABLE | SDF_GROUND;
814 s->n_chan = 8;
815 s->maxdata = 0x0fff;
816 s->range_table = is_unipolar ? &range_unipolar2_5 : &range_bipolar10;
83a69f5a 817 s->insn_read = dt9812_ai_insn_read;
b78750c1
HS
818
819 /* Analog Output subdevice */
3a207891 820 s = &dev->subdevices[3];
b78750c1 821 s->type = COMEDI_SUBD_AO;
ef49d832 822 s->subdev_flags = SDF_WRITABLE;
b78750c1
HS
823 s->n_chan = 2;
824 s->maxdata = 0x0fff;
825 s->range_table = is_unipolar ? &range_unipolar2_5 : &range_bipolar10;
99928e65 826 s->insn_write = dt9812_ao_insn_write;
e79f18e6 827 s->insn_read = dt9812_ao_insn_read;
63274cd7 828
acc5fe2c
HS
829 ret = comedi_alloc_subdev_readback(s);
830 if (ret)
831 return ret;
832
833 for (i = 0; i < s->n_chan; i++)
834 s->readback[i] = is_unipolar ? 0x0000 : 0x0800;
135a0009 835
63274cd7
AB
836 return 0;
837}
838
484ecc95 839static void dt9812_detach(struct comedi_device *dev)
63274cd7 840{
b78750c1 841 struct usb_interface *intf = comedi_to_usb_interface(dev);
1415003f
HS
842 struct dt9812_private *devpriv = dev->private;
843
b78750c1
HS
844 if (!devpriv)
845 return;
df785c7a 846
9faa310f 847 mutex_lock(&devpriv->mut);
df785c7a 848
b78750c1 849 usb_set_intfdata(intf, NULL);
df785c7a 850
9faa310f 851 mutex_unlock(&devpriv->mut);
df785c7a
HS
852}
853
b78750c1
HS
854static struct comedi_driver dt9812_driver = {
855 .driver_name = "dt9812",
856 .module = THIS_MODULE,
857 .auto_attach = dt9812_auto_attach,
858 .detach = dt9812_detach,
859};
df785c7a 860
b78750c1
HS
861static int dt9812_usb_probe(struct usb_interface *intf,
862 const struct usb_device_id *id)
863{
864 return comedi_usb_auto_config(intf, &dt9812_driver, id->driver_info);
df785c7a
HS
865}
866
b78750c1 867static const struct usb_device_id dt9812_usb_table[] = {
df785c7a
HS
868 { USB_DEVICE(0x0867, 0x9812) },
869 { }
870};
b78750c1 871MODULE_DEVICE_TABLE(usb, dt9812_usb_table);
df785c7a
HS
872
873static struct usb_driver dt9812_usb_driver = {
874 .name = "dt9812",
b78750c1
HS
875 .id_table = dt9812_usb_table,
876 .probe = dt9812_usb_probe,
877 .disconnect = comedi_usb_auto_unconfig,
df785c7a 878};
b78750c1 879module_comedi_usb_driver(dt9812_driver, dt9812_usb_driver);
63274cd7
AB
880
881MODULE_AUTHOR("Anders Blomdell <anders.blomdell@control.lth.se>");
882MODULE_DESCRIPTION("Comedi DT9812 driver");
883MODULE_LICENSE("GPL");
This page took 0.965493 seconds and 5 git commands to generate.