Commit | Line | Data |
---|---|---|
01b0a258 | 1 | /* |
27fa082b HS |
2 | * Comedi driver for National Instruments AT-A2150 boards |
3 | * Copyright (C) 2001, 2002 Frank Mori Hess <fmhess@users.sourceforge.net> | |
4 | * | |
5 | * COMEDI - Linux Control and Measurement Device Interface | |
6 | * Copyright (C) 2000 David A. Schleef <ds@schleef.org> | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License as published by | |
10 | * the Free Software Foundation; either version 2 of the License, or | |
11 | * (at your option) any later version. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, | |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
17 | */ | |
01b0a258 | 18 | |
01b0a258 | 19 | /* |
27fa082b HS |
20 | * Driver: ni_at_a2150 |
21 | * Description: National Instruments AT-A2150 | |
22 | * Author: Frank Mori Hess | |
23 | * Status: works | |
24 | * Devices: [National Instruments] AT-A2150C (at_a2150c), AT-2150S (at_a2150s) | |
25 | * | |
26 | * Configuration options: | |
27 | * [0] - I/O port base address | |
28 | * [1] - IRQ (optional, required for timed conversions) | |
29 | * [2] - DMA (optional, required for timed conversions) | |
30 | * | |
31 | * Yet another driver for obsolete hardware brought to you by Frank Hess. | |
32 | * Testing and debugging help provided by Dave Andruczyk. | |
33 | * | |
34 | * If you want to ac couple the board's inputs, use AREF_OTHER. | |
35 | * | |
36 | * The only difference in the boards is their master clock frequencies. | |
37 | * | |
38 | * References (from ftp://ftp.natinst.com/support/manuals): | |
39 | * 320360.pdf AT-A2150 User Manual | |
40 | * | |
41 | * TODO: | |
42 | * - analog level triggering | |
43 | * - TRIG_WAKE_EOS | |
44 | */ | |
01b0a258 | 45 | |
ce157f80 HS |
46 | #include <linux/module.h> |
47 | #include <linux/delay.h> | |
25436dc9 | 48 | #include <linux/interrupt.h> |
5a0e3ad6 | 49 | #include <linux/slab.h> |
845d131e | 50 | #include <linux/io.h> |
ce157f80 | 51 | |
1a97f144 | 52 | #include "../comedidev.h" |
01b0a258 | 53 | |
1a97f144 | 54 | #include "comedi_isadma.h" |
e875132a | 55 | #include "comedi_8254.h" |
01b0a258 | 56 | |
30c687c1 | 57 | #define A2150_DMA_BUFFER_SIZE 0xff00 /* size in bytes of dma buffer */ |
01b0a258 | 58 | |
01b0a258 FMH |
59 | /* Registers and bits */ |
60 | #define CONFIG_REG 0x0 | |
4281c748 | 61 | #define CHANNEL_BITS(x) ((x) & 0x7) |
01b0a258 | 62 | #define CHANNEL_MASK 0x7 |
4281c748 AJ |
63 | #define CLOCK_SELECT_BITS(x) (((x) & 0x3) << 3) |
64 | #define CLOCK_DIVISOR_BITS(x) (((x) & 0x3) << 5) | |
01b0a258 | 65 | #define CLOCK_MASK (0xf << 3) |
4281c748 AJ |
66 | /* enable (don't internally ground) channels 0 and 1 */ |
67 | #define ENABLE0_BIT 0x80 | |
68 | /* enable (don't internally ground) channels 2 and 3 */ | |
69 | #define ENABLE1_BIT 0x100 | |
70 | #define AC0_BIT 0x200 /* ac couple channels 0,1 */ | |
71 | #define AC1_BIT 0x400 /* ac couple channels 2,3 */ | |
72 | #define APD_BIT 0x800 /* analog power down */ | |
73 | #define DPD_BIT 0x1000 /* digital power down */ | |
74 | #define TRIGGER_REG 0x2 /* trigger config register */ | |
75 | #define POST_TRIGGER_BITS 0x2 | |
76 | #define DELAY_TRIGGER_BITS 0x3 | |
77 | #define HW_TRIG_EN 0x10 /* enable hardware trigger */ | |
78 | #define FIFO_START_REG 0x6 /* software start aquistion trigger */ | |
79 | #define FIFO_RESET_REG 0x8 /* clears fifo + fifo flags */ | |
80 | #define FIFO_DATA_REG 0xa /* read data */ | |
81 | #define DMA_TC_CLEAR_REG 0xe /* clear dma terminal count interrupt */ | |
82 | #define STATUS_REG 0x12 /* read only */ | |
83 | #define FNE_BIT 0x1 /* fifo not empty */ | |
84 | #define OVFL_BIT 0x8 /* fifo overflow */ | |
85 | #define EDAQ_BIT 0x10 /* end of acquisition interrupt */ | |
86 | #define DCAL_BIT 0x20 /* offset calibration in progress */ | |
87 | #define INTR_BIT 0x40 /* interrupt has occurred */ | |
88 | /* dma terminal count interrupt has occurred */ | |
89 | #define DMA_TC_BIT 0x80 | |
90 | #define ID_BITS(x) (((x) >> 8) & 0x3) | |
91 | #define IRQ_DMA_CNTRL_REG 0x12 /* write only */ | |
92 | #define DMA_CHAN_BITS(x) ((x) & 0x7) /* sets dma channel */ | |
93 | #define DMA_EN_BIT 0x8 /* enables dma */ | |
94 | #define IRQ_LVL_BITS(x) (((x) & 0xf) << 4) /* sets irq level */ | |
95 | #define FIFO_INTR_EN_BIT 0x100 /* enable fifo interrupts */ | |
96 | #define FIFO_INTR_FHF_BIT 0x200 /* interrupt fifo half full */ | |
97 | /* enable interrupt on dma terminal count */ | |
98 | #define DMA_INTR_EN_BIT 0x800 | |
99 | #define DMA_DEM_EN_BIT 0x1000 /* enables demand mode dma */ | |
01b0a258 | 100 | #define I8253_BASE_REG 0x14 |
01b0a258 | 101 | |
92b635c5 | 102 | struct a2150_board { |
01b0a258 | 103 | const char *name; |
4281c748 AJ |
104 | int clock[4]; /* master clock periods, in nanoseconds */ |
105 | int num_clocks; /* number of available master clock speeds */ | |
106 | int ai_speed; /* maximum conversion rate in nanoseconds */ | |
92b635c5 | 107 | }; |
01b0a258 | 108 | |
30c687c1 | 109 | /* analog input range */ |
9ced1de6 | 110 | static const struct comedi_lrange range_a2150 = { |
168a2103 HS |
111 | 1, { |
112 | BIP_RANGE(2.828) | |
113 | } | |
01b0a258 FMH |
114 | }; |
115 | ||
30c687c1 | 116 | /* enum must match board indices */ |
01b0a258 | 117 | enum { a2150_c, a2150_s }; |
92b635c5 | 118 | static const struct a2150_board a2150_boards[] = { |
01b0a258 | 119 | { |
0a85b6f0 MT |
120 | .name = "at-a2150c", |
121 | .clock = {31250, 22676, 20833, 19531}, | |
122 | .num_clocks = 4, | |
123 | .ai_speed = 19531, | |
124 | }, | |
01b0a258 | 125 | { |
0a85b6f0 MT |
126 | .name = "at-a2150s", |
127 | .clock = {62500, 50000, 41667, 0}, | |
128 | .num_clocks = 3, | |
129 | .ai_speed = 41667, | |
130 | }, | |
01b0a258 FMH |
131 | }; |
132 | ||
3cc3872b | 133 | struct a2150_private { |
1a97f144 | 134 | struct comedi_isadma *dma; |
45478548 | 135 | unsigned int count; /* number of data points left to be taken */ |
4281c748 AJ |
136 | int irq_dma_bits; /* irq/dma register bits */ |
137 | int config_bits; /* config register bits */ | |
3cc3872b BP |
138 | }; |
139 | ||
01b0a258 | 140 | /* interrupt service routine */ |
70265d24 | 141 | static irqreturn_t a2150_interrupt(int irq, void *d) |
01b0a258 | 142 | { |
71b5f4f1 | 143 | struct comedi_device *dev = d; |
9a1a6cf8 | 144 | struct a2150_private *devpriv = dev->private; |
1a97f144 HS |
145 | struct comedi_isadma *dma = devpriv->dma; |
146 | struct comedi_isadma_desc *desc = &dma->desc[0]; | |
34c43922 | 147 | struct comedi_subdevice *s = dev->read_subdev; |
1a97f144 HS |
148 | struct comedi_async *async = s->async; |
149 | struct comedi_cmd *cmd = &async->cmd; | |
150 | unsigned short *buf = desc->virt_addr; | |
01b0a258 | 151 | unsigned int max_points, num_points, residue, leftover; |
2fb5cd38 | 152 | unsigned short dpnt; |
1a97f144 HS |
153 | int status; |
154 | int i; | |
01b0a258 | 155 | |
1a97f144 | 156 | if (!dev->attached) |
01b0a258 | 157 | return IRQ_HANDLED; |
01b0a258 FMH |
158 | |
159 | status = inw(dev->iobase + STATUS_REG); | |
1a97f144 | 160 | if ((status & INTR_BIT) == 0) |
01b0a258 | 161 | return IRQ_NONE; |
01b0a258 FMH |
162 | |
163 | if (status & OVFL_BIT) { | |
3e6cb74f | 164 | async->events |= COMEDI_CB_ERROR; |
4a706e2e | 165 | comedi_handle_events(dev, s); |
01b0a258 FMH |
166 | } |
167 | ||
168 | if ((status & DMA_TC_BIT) == 0) { | |
3e6cb74f | 169 | async->events |= COMEDI_CB_ERROR; |
4a706e2e | 170 | comedi_handle_events(dev, s); |
01b0a258 FMH |
171 | return IRQ_HANDLED; |
172 | } | |
173 | ||
10f3a2dc HS |
174 | /* |
175 | * residue is the number of bytes left to be done on the dma | |
01b0a258 FMH |
176 | * transfer. It should always be zero at this point unless |
177 | * the stop_src is set to external triggering. | |
178 | */ | |
1a97f144 | 179 | residue = comedi_isadma_disable(desc->chan); |
10f3a2dc | 180 | |
4281c748 | 181 | /* figure out how many points to read */ |
1a97f144 | 182 | max_points = comedi_bytes_to_samples(s, desc->size); |
10f3a2dc | 183 | num_points = max_points - comedi_bytes_to_samples(s, residue); |
01b0a258 FMH |
184 | if (devpriv->count < num_points && cmd->stop_src == TRIG_COUNT) |
185 | num_points = devpriv->count; | |
186 | ||
4281c748 | 187 | /* figure out how many points will be stored next time */ |
01b0a258 FMH |
188 | leftover = 0; |
189 | if (cmd->stop_src == TRIG_NONE) { | |
1a97f144 | 190 | leftover = comedi_bytes_to_samples(s, desc->size); |
01b0a258 FMH |
191 | } else if (devpriv->count > max_points) { |
192 | leftover = devpriv->count - max_points; | |
193 | if (leftover > max_points) | |
194 | leftover = max_points; | |
195 | } | |
4281c748 AJ |
196 | /* |
197 | * There should only be a residue if collection was stopped by having | |
01b0a258 FMH |
198 | * the stop_src set to an external trigger, in which case there |
199 | * will be no more data | |
200 | */ | |
201 | if (residue) | |
202 | leftover = 0; | |
203 | ||
204 | for (i = 0; i < num_points; i++) { | |
205 | /* write data point to comedi buffer */ | |
6d262751 | 206 | dpnt = buf[i]; |
4281c748 | 207 | /* convert from 2's complement to unsigned coding */ |
01b0a258 | 208 | dpnt ^= 0x8000; |
7138e892 | 209 | comedi_buf_write_samples(s, &dpnt, 1); |
01b0a258 FMH |
210 | if (cmd->stop_src == TRIG_COUNT) { |
211 | if (--devpriv->count == 0) { /* end of acquisition */ | |
01b0a258 FMH |
212 | async->events |= COMEDI_CB_EOA; |
213 | break; | |
214 | } | |
215 | } | |
216 | } | |
c92b0b29 | 217 | /* re-enable dma */ |
01b0a258 | 218 | if (leftover) { |
1a97f144 HS |
219 | desc->size = comedi_samples_to_bytes(s, leftover); |
220 | comedi_isadma_program(desc); | |
01b0a258 | 221 | } |
01b0a258 | 222 | |
4a706e2e | 223 | comedi_handle_events(dev, s); |
01b0a258 FMH |
224 | |
225 | /* clear interrupt */ | |
226 | outw(0x00, dev->iobase + DMA_TC_CLEAR_REG); | |
227 | ||
228 | return IRQ_HANDLED; | |
229 | } | |
230 | ||
da91b269 | 231 | static int a2150_cancel(struct comedi_device *dev, struct comedi_subdevice *s) |
01b0a258 | 232 | { |
9a1a6cf8 | 233 | struct a2150_private *devpriv = dev->private; |
1a97f144 HS |
234 | struct comedi_isadma *dma = devpriv->dma; |
235 | struct comedi_isadma_desc *desc = &dma->desc[0]; | |
9a1a6cf8 | 236 | |
4281c748 | 237 | /* disable dma on card */ |
01b0a258 FMH |
238 | devpriv->irq_dma_bits &= ~DMA_INTR_EN_BIT & ~DMA_EN_BIT; |
239 | outw(devpriv->irq_dma_bits, dev->iobase + IRQ_DMA_CNTRL_REG); | |
240 | ||
4281c748 | 241 | /* disable computer's dma */ |
1a97f144 | 242 | comedi_isadma_disable(desc->chan); |
01b0a258 | 243 | |
4281c748 | 244 | /* clear fifo and reset triggering circuitry */ |
01b0a258 FMH |
245 | outw(0, dev->iobase + FIFO_RESET_REG); |
246 | ||
247 | return 0; | |
248 | } | |
249 | ||
c9bef032 HS |
250 | /* |
251 | * sets bits in devpriv->clock_bits to nearest approximation of requested | |
252 | * period, adjusts requested period to actual timing. | |
253 | */ | |
254 | static int a2150_get_timing(struct comedi_device *dev, unsigned int *period, | |
255 | unsigned int flags) | |
256 | { | |
94be3ef2 | 257 | const struct a2150_board *board = dev->board_ptr; |
c9bef032 HS |
258 | struct a2150_private *devpriv = dev->private; |
259 | int lub, glb, temp; | |
260 | int lub_divisor_shift, lub_index, glb_divisor_shift, glb_index; | |
261 | int i, j; | |
262 | ||
4281c748 | 263 | /* initialize greatest lower and least upper bounds */ |
c9bef032 HS |
264 | lub_divisor_shift = 3; |
265 | lub_index = 0; | |
94be3ef2 | 266 | lub = board->clock[lub_index] * (1 << lub_divisor_shift); |
c9bef032 | 267 | glb_divisor_shift = 0; |
94be3ef2 HS |
268 | glb_index = board->num_clocks - 1; |
269 | glb = board->clock[glb_index] * (1 << glb_divisor_shift); | |
c9bef032 | 270 | |
4281c748 | 271 | /* make sure period is in available range */ |
c9bef032 HS |
272 | if (*period < glb) |
273 | *period = glb; | |
274 | if (*period > lub) | |
275 | *period = lub; | |
276 | ||
4281c748 | 277 | /* we can multiply period by 1, 2, 4, or 8, using (1 << i) */ |
c9bef032 | 278 | for (i = 0; i < 4; i++) { |
4281c748 | 279 | /* there are a maximum of 4 master clocks */ |
94be3ef2 | 280 | for (j = 0; j < board->num_clocks; j++) { |
4281c748 | 281 | /* temp is the period in nanosec we are evaluating */ |
94be3ef2 | 282 | temp = board->clock[j] * (1 << i); |
4281c748 | 283 | /* if it is the best match yet */ |
c9bef032 HS |
284 | if (temp < lub && temp >= *period) { |
285 | lub_divisor_shift = i; | |
286 | lub_index = j; | |
287 | lub = temp; | |
288 | } | |
289 | if (temp > glb && temp <= *period) { | |
290 | glb_divisor_shift = i; | |
291 | glb_index = j; | |
292 | glb = temp; | |
293 | } | |
294 | } | |
295 | } | |
b544bd69 IA |
296 | switch (flags & CMDF_ROUND_MASK) { |
297 | case CMDF_ROUND_NEAREST: | |
c9bef032 | 298 | default: |
4281c748 | 299 | /* if least upper bound is better approximation */ |
c9bef032 HS |
300 | if (lub - *period < *period - glb) |
301 | *period = lub; | |
302 | else | |
303 | *period = glb; | |
304 | break; | |
b544bd69 | 305 | case CMDF_ROUND_UP: |
c9bef032 HS |
306 | *period = lub; |
307 | break; | |
b544bd69 | 308 | case CMDF_ROUND_DOWN: |
c9bef032 HS |
309 | *period = glb; |
310 | break; | |
311 | } | |
312 | ||
4281c748 | 313 | /* set clock bits for config register appropriately */ |
c9bef032 HS |
314 | devpriv->config_bits &= ~CLOCK_MASK; |
315 | if (*period == lub) { | |
316 | devpriv->config_bits |= | |
317 | CLOCK_SELECT_BITS(lub_index) | | |
318 | CLOCK_DIVISOR_BITS(lub_divisor_shift); | |
319 | } else { | |
320 | devpriv->config_bits |= | |
321 | CLOCK_SELECT_BITS(glb_index) | | |
322 | CLOCK_DIVISOR_BITS(glb_divisor_shift); | |
323 | } | |
324 | ||
325 | return 0; | |
326 | } | |
327 | ||
328 | static int a2150_set_chanlist(struct comedi_device *dev, | |
329 | unsigned int start_channel, | |
330 | unsigned int num_channels) | |
331 | { | |
332 | struct a2150_private *devpriv = dev->private; | |
333 | ||
334 | if (start_channel + num_channels > 4) | |
335 | return -1; | |
336 | ||
337 | devpriv->config_bits &= ~CHANNEL_MASK; | |
338 | ||
339 | switch (num_channels) { | |
340 | case 1: | |
341 | devpriv->config_bits |= CHANNEL_BITS(0x4 | start_channel); | |
342 | break; | |
343 | case 2: | |
344 | if (start_channel == 0) | |
345 | devpriv->config_bits |= CHANNEL_BITS(0x2); | |
346 | else if (start_channel == 2) | |
347 | devpriv->config_bits |= CHANNEL_BITS(0x3); | |
348 | else | |
349 | return -1; | |
350 | break; | |
351 | case 4: | |
352 | devpriv->config_bits |= CHANNEL_BITS(0x1); | |
353 | break; | |
354 | default: | |
355 | return -1; | |
356 | } | |
357 | ||
358 | return 0; | |
359 | } | |
360 | ||
8f61419f HS |
361 | static int a2150_ai_check_chanlist(struct comedi_device *dev, |
362 | struct comedi_subdevice *s, | |
363 | struct comedi_cmd *cmd) | |
364 | { | |
365 | unsigned int chan0 = CR_CHAN(cmd->chanlist[0]); | |
366 | unsigned int aref0 = CR_AREF(cmd->chanlist[0]); | |
367 | int i; | |
368 | ||
369 | if (cmd->chanlist_len == 2 && (chan0 == 1 || chan0 == 3)) { | |
370 | dev_dbg(dev->class_dev, | |
371 | "length 2 chanlist must be channels 0,1 or channels 2,3\n"); | |
372 | return -EINVAL; | |
373 | } | |
374 | ||
375 | if (cmd->chanlist_len == 3) { | |
376 | dev_dbg(dev->class_dev, | |
377 | "chanlist must have 1,2 or 4 channels\n"); | |
378 | return -EINVAL; | |
379 | } | |
380 | ||
381 | for (i = 1; i < cmd->chanlist_len; i++) { | |
382 | unsigned int chan = CR_CHAN(cmd->chanlist[i]); | |
383 | unsigned int aref = CR_AREF(cmd->chanlist[i]); | |
384 | ||
385 | if (chan != (chan0 + i)) { | |
386 | dev_dbg(dev->class_dev, | |
387 | "entries in chanlist must be consecutive channels, counting upwards\n"); | |
388 | return -EINVAL; | |
389 | } | |
390 | ||
391 | if (chan == 2) | |
392 | aref0 = aref; | |
393 | if (aref != aref0) { | |
394 | dev_dbg(dev->class_dev, | |
395 | "channels 0/1 and 2/3 must have the same analog reference\n"); | |
396 | return -EINVAL; | |
397 | } | |
398 | } | |
399 | ||
400 | return 0; | |
401 | } | |
402 | ||
0a85b6f0 MT |
403 | static int a2150_ai_cmdtest(struct comedi_device *dev, |
404 | struct comedi_subdevice *s, struct comedi_cmd *cmd) | |
01b0a258 | 405 | { |
94be3ef2 | 406 | const struct a2150_board *board = dev->board_ptr; |
01b0a258 | 407 | int err = 0; |
75cff543 | 408 | unsigned int arg; |
01b0a258 | 409 | |
27020ffe | 410 | /* Step 1 : check if triggers are trivially valid */ |
01b0a258 | 411 | |
ded24683 IA |
412 | err |= comedi_check_trigger_src(&cmd->start_src, TRIG_NOW | TRIG_EXT); |
413 | err |= comedi_check_trigger_src(&cmd->scan_begin_src, TRIG_TIMER); | |
414 | err |= comedi_check_trigger_src(&cmd->convert_src, TRIG_NOW); | |
415 | err |= comedi_check_trigger_src(&cmd->scan_end_src, TRIG_COUNT); | |
416 | err |= comedi_check_trigger_src(&cmd->stop_src, TRIG_COUNT | TRIG_NONE); | |
01b0a258 FMH |
417 | |
418 | if (err) | |
419 | return 1; | |
420 | ||
27020ffe | 421 | /* Step 2a : make sure trigger sources are unique */ |
01b0a258 | 422 | |
ded24683 IA |
423 | err |= comedi_check_trigger_is_unique(cmd->start_src); |
424 | err |= comedi_check_trigger_is_unique(cmd->stop_src); | |
27020ffe HS |
425 | |
426 | /* Step 2b : and mutually compatible */ | |
01b0a258 FMH |
427 | |
428 | if (err) | |
429 | return 2; | |
430 | ||
dd254844 | 431 | /* Step 3: check if arguments are trivially valid */ |
01b0a258 | 432 | |
ded24683 | 433 | err |= comedi_check_trigger_arg_is(&cmd->start_arg, 0); |
dd254844 | 434 | |
ded24683 IA |
435 | if (cmd->convert_src == TRIG_TIMER) { |
436 | err |= comedi_check_trigger_arg_min(&cmd->convert_arg, | |
94be3ef2 | 437 | board->ai_speed); |
ded24683 | 438 | } |
dd254844 | 439 | |
ded24683 IA |
440 | err |= comedi_check_trigger_arg_min(&cmd->chanlist_len, 1); |
441 | err |= comedi_check_trigger_arg_is(&cmd->scan_end_arg, | |
442 | cmd->chanlist_len); | |
dd254844 HS |
443 | |
444 | if (cmd->stop_src == TRIG_COUNT) | |
ded24683 | 445 | err |= comedi_check_trigger_arg_min(&cmd->stop_arg, 1); |
dd254844 | 446 | else /* TRIG_NONE */ |
ded24683 | 447 | err |= comedi_check_trigger_arg_is(&cmd->stop_arg, 0); |
01b0a258 FMH |
448 | |
449 | if (err) | |
450 | return 3; | |
451 | ||
452 | /* step 4: fix up any arguments */ | |
453 | ||
454 | if (cmd->scan_begin_src == TRIG_TIMER) { | |
75cff543 HS |
455 | arg = cmd->scan_begin_arg; |
456 | a2150_get_timing(dev, &arg, cmd->flags); | |
ded24683 | 457 | err |= comedi_check_trigger_arg_is(&cmd->scan_begin_arg, arg); |
01b0a258 FMH |
458 | } |
459 | ||
460 | if (err) | |
461 | return 4; | |
462 | ||
8f61419f HS |
463 | /* Step 5: check channel list if it exists */ |
464 | if (cmd->chanlist && cmd->chanlist_len > 0) | |
465 | err |= a2150_ai_check_chanlist(dev, s, cmd); | |
01b0a258 FMH |
466 | |
467 | if (err) | |
468 | return 5; | |
469 | ||
470 | return 0; | |
471 | } | |
472 | ||
da91b269 | 473 | static int a2150_ai_cmd(struct comedi_device *dev, struct comedi_subdevice *s) |
01b0a258 | 474 | { |
9a1a6cf8 | 475 | struct a2150_private *devpriv = dev->private; |
1a97f144 HS |
476 | struct comedi_isadma *dma = devpriv->dma; |
477 | struct comedi_isadma_desc *desc = &dma->desc[0]; | |
d163679c | 478 | struct comedi_async *async = s->async; |
ea6d0d4c | 479 | struct comedi_cmd *cmd = &async->cmd; |
01b0a258 FMH |
480 | unsigned int old_config_bits = devpriv->config_bits; |
481 | unsigned int trigger_bits; | |
482 | ||
34ae4160 | 483 | if (cmd->flags & CMDF_PRIORITY) { |
770bc73d | 484 | dev_err(dev->class_dev, |
34ae4160 | 485 | "dma incompatible with hard real-time interrupt (CMDF_PRIORITY), aborting\n"); |
01b0a258 FMH |
486 | return -1; |
487 | } | |
4281c748 | 488 | /* clear fifo and reset triggering circuitry */ |
01b0a258 FMH |
489 | outw(0, dev->iobase + FIFO_RESET_REG); |
490 | ||
491 | /* setup chanlist */ | |
492 | if (a2150_set_chanlist(dev, CR_CHAN(cmd->chanlist[0]), | |
0a85b6f0 | 493 | cmd->chanlist_len) < 0) |
01b0a258 FMH |
494 | return -1; |
495 | ||
4281c748 | 496 | /* setup ac/dc coupling */ |
01b0a258 FMH |
497 | if (CR_AREF(cmd->chanlist[0]) == AREF_OTHER) |
498 | devpriv->config_bits |= AC0_BIT; | |
499 | else | |
500 | devpriv->config_bits &= ~AC0_BIT; | |
501 | if (CR_AREF(cmd->chanlist[2]) == AREF_OTHER) | |
502 | devpriv->config_bits |= AC1_BIT; | |
503 | else | |
504 | devpriv->config_bits &= ~AC1_BIT; | |
505 | ||
4281c748 | 506 | /* setup timing */ |
01b0a258 FMH |
507 | a2150_get_timing(dev, &cmd->scan_begin_arg, cmd->flags); |
508 | ||
4281c748 | 509 | /* send timing, channel, config bits */ |
01b0a258 FMH |
510 | outw(devpriv->config_bits, dev->iobase + CONFIG_REG); |
511 | ||
4281c748 | 512 | /* initialize number of samples remaining */ |
01b0a258 FMH |
513 | devpriv->count = cmd->stop_arg * cmd->chanlist_len; |
514 | ||
1a97f144 | 515 | comedi_isadma_disable(desc->chan); |
c92b0b29 | 516 | |
4281c748 | 517 | /* set size of transfer to fill in 1/3 second */ |
01b0a258 | 518 | #define ONE_THIRD_SECOND 333333333 |
1a97f144 | 519 | desc->size = comedi_bytes_per_sample(s) * cmd->chanlist_len * |
5bf7d295 | 520 | ONE_THIRD_SECOND / cmd->scan_begin_arg; |
1a97f144 HS |
521 | if (desc->size > desc->maxsize) |
522 | desc->size = desc->maxsize; | |
523 | if (desc->size < comedi_bytes_per_sample(s)) | |
524 | desc->size = comedi_bytes_per_sample(s); | |
525 | desc->size -= desc->size % comedi_bytes_per_sample(s); | |
c92b0b29 | 526 | |
1a97f144 | 527 | comedi_isadma_program(desc); |
01b0a258 | 528 | |
27fa082b HS |
529 | /* |
530 | * Clear dma interrupt before enabling it, to try and get rid of | |
531 | * that one spurious interrupt that has been happening. | |
532 | */ | |
01b0a258 FMH |
533 | outw(0x00, dev->iobase + DMA_TC_CLEAR_REG); |
534 | ||
4281c748 | 535 | /* enable dma on card */ |
01b0a258 FMH |
536 | devpriv->irq_dma_bits |= DMA_INTR_EN_BIT | DMA_EN_BIT; |
537 | outw(devpriv->irq_dma_bits, dev->iobase + IRQ_DMA_CNTRL_REG); | |
538 | ||
4281c748 | 539 | /* may need to wait 72 sampling periods if timing was changed */ |
e875132a | 540 | comedi_8254_load(dev->pacer, 2, 72, I8254_MODE0 | I8254_BINARY); |
01b0a258 | 541 | |
4281c748 | 542 | /* setup start triggering */ |
01b0a258 | 543 | trigger_bits = 0; |
4281c748 | 544 | /* decide if we need to wait 72 periods for valid data */ |
01b0a258 | 545 | if (cmd->start_src == TRIG_NOW && |
0a85b6f0 MT |
546 | (old_config_bits & CLOCK_MASK) != |
547 | (devpriv->config_bits & CLOCK_MASK)) { | |
4281c748 | 548 | /* set trigger source to delay trigger */ |
01b0a258 FMH |
549 | trigger_bits |= DELAY_TRIGGER_BITS; |
550 | } else { | |
4281c748 | 551 | /* otherwise no delay */ |
01b0a258 FMH |
552 | trigger_bits |= POST_TRIGGER_BITS; |
553 | } | |
4281c748 | 554 | /* enable external hardware trigger */ |
01b0a258 FMH |
555 | if (cmd->start_src == TRIG_EXT) { |
556 | trigger_bits |= HW_TRIG_EN; | |
557 | } else if (cmd->start_src == TRIG_OTHER) { | |
4281c748 AJ |
558 | /* |
559 | * XXX add support for level/slope start trigger | |
560 | * using TRIG_OTHER | |
561 | */ | |
770bc73d | 562 | dev_err(dev->class_dev, "you shouldn't see this?\n"); |
01b0a258 | 563 | } |
4281c748 | 564 | /* send trigger config bits */ |
01b0a258 FMH |
565 | outw(trigger_bits, dev->iobase + TRIGGER_REG); |
566 | ||
4281c748 | 567 | /* start acquisition for soft trigger */ |
a96b98f2 | 568 | if (cmd->start_src == TRIG_NOW) |
01b0a258 | 569 | outw(0, dev->iobase + FIFO_START_REG); |
01b0a258 FMH |
570 | |
571 | return 0; | |
572 | } | |
573 | ||
33a6d44b HS |
574 | static int a2150_ai_eoc(struct comedi_device *dev, |
575 | struct comedi_subdevice *s, | |
576 | struct comedi_insn *insn, | |
577 | unsigned long context) | |
578 | { | |
579 | unsigned int status; | |
580 | ||
581 | status = inw(dev->iobase + STATUS_REG); | |
582 | if (status & FNE_BIT) | |
583 | return 0; | |
584 | return -EBUSY; | |
585 | } | |
586 | ||
da91b269 | 587 | static int a2150_ai_rinsn(struct comedi_device *dev, struct comedi_subdevice *s, |
0a85b6f0 | 588 | struct comedi_insn *insn, unsigned int *data) |
01b0a258 | 589 | { |
9a1a6cf8 | 590 | struct a2150_private *devpriv = dev->private; |
33a6d44b HS |
591 | unsigned int n; |
592 | int ret; | |
01b0a258 | 593 | |
4281c748 | 594 | /* clear fifo and reset triggering circuitry */ |
01b0a258 FMH |
595 | outw(0, dev->iobase + FIFO_RESET_REG); |
596 | ||
597 | /* setup chanlist */ | |
598 | if (a2150_set_chanlist(dev, CR_CHAN(insn->chanspec), 1) < 0) | |
599 | return -1; | |
600 | ||
4281c748 | 601 | /* set dc coupling */ |
01b0a258 FMH |
602 | devpriv->config_bits &= ~AC0_BIT; |
603 | devpriv->config_bits &= ~AC1_BIT; | |
604 | ||
4281c748 | 605 | /* send timing, channel, config bits */ |
01b0a258 FMH |
606 | outw(devpriv->config_bits, dev->iobase + CONFIG_REG); |
607 | ||
4281c748 | 608 | /* disable dma on card */ |
01b0a258 FMH |
609 | devpriv->irq_dma_bits &= ~DMA_INTR_EN_BIT & ~DMA_EN_BIT; |
610 | outw(devpriv->irq_dma_bits, dev->iobase + IRQ_DMA_CNTRL_REG); | |
611 | ||
4281c748 | 612 | /* setup start triggering */ |
01b0a258 FMH |
613 | outw(0, dev->iobase + TRIGGER_REG); |
614 | ||
4281c748 | 615 | /* start acquisition for soft trigger */ |
01b0a258 FMH |
616 | outw(0, dev->iobase + FIFO_START_REG); |
617 | ||
949fd38c RKM |
618 | /* |
619 | * there is a 35.6 sample delay for data to get through the | |
620 | * antialias filter | |
621 | */ | |
33a6d44b HS |
622 | for (n = 0; n < 36; n++) { |
623 | ret = comedi_timeout(dev, s, insn, a2150_ai_eoc, 0); | |
22ca19d9 | 624 | if (ret) |
33a6d44b | 625 | return ret; |
33a6d44b | 626 | |
01b0a258 FMH |
627 | inw(dev->iobase + FIFO_DATA_REG); |
628 | } | |
629 | ||
4281c748 | 630 | /* read data */ |
01b0a258 | 631 | for (n = 0; n < insn->n; n++) { |
33a6d44b | 632 | ret = comedi_timeout(dev, s, insn, a2150_ai_eoc, 0); |
22ca19d9 | 633 | if (ret) |
33a6d44b | 634 | return ret; |
33a6d44b | 635 | |
01b0a258 | 636 | data[n] = inw(dev->iobase + FIFO_DATA_REG); |
01b0a258 FMH |
637 | data[n] ^= 0x8000; |
638 | } | |
639 | ||
4281c748 | 640 | /* clear fifo and reset triggering circuitry */ |
01b0a258 FMH |
641 | outw(0, dev->iobase + FIFO_RESET_REG); |
642 | ||
643 | return n; | |
644 | } | |
645 | ||
1a97f144 HS |
646 | static void a2150_alloc_irq_and_dma(struct comedi_device *dev, |
647 | struct comedi_devconfig *it) | |
7cbb0ef9 HS |
648 | { |
649 | struct a2150_private *devpriv = dev->private; | |
650 | unsigned int irq_num = it->options[1]; | |
651 | unsigned int dma_chan = it->options[2]; | |
652 | ||
653 | /* | |
654 | * Only IRQs 15, 14, 12-9, and 7-3 are valid. | |
655 | * Only DMA channels 7-5 and 3-0 are valid. | |
7cbb0ef9 HS |
656 | */ |
657 | if (irq_num > 15 || dma_chan > 7 || | |
658 | !((1 << irq_num) & 0xdef8) || !((1 << dma_chan) & 0xef)) | |
659 | return; | |
660 | ||
7cbb0ef9 HS |
661 | if (request_irq(irq_num, a2150_interrupt, 0, dev->board_name, dev)) |
662 | return; | |
1a97f144 HS |
663 | |
664 | /* DMA uses 1 buffer */ | |
665 | devpriv->dma = comedi_isadma_alloc(dev, 1, dma_chan, dma_chan, | |
666 | A2150_DMA_BUFFER_SIZE, | |
667 | COMEDI_ISADMA_READ); | |
668 | if (!devpriv->dma) { | |
7cbb0ef9 | 669 | free_irq(irq_num, dev); |
1a97f144 HS |
670 | } else { |
671 | dev->irq = irq_num; | |
672 | devpriv->irq_dma_bits = IRQ_LVL_BITS(irq_num) | | |
673 | DMA_CHAN_BITS(dma_chan); | |
7cbb0ef9 | 674 | } |
7cbb0ef9 HS |
675 | } |
676 | ||
b1478901 HS |
677 | static void a2150_free_dma(struct comedi_device *dev) |
678 | { | |
679 | struct a2150_private *devpriv = dev->private; | |
b1478901 | 680 | |
1a97f144 HS |
681 | if (devpriv) |
682 | comedi_isadma_free(devpriv->dma); | |
b1478901 HS |
683 | } |
684 | ||
30f23066 | 685 | static const struct a2150_board *a2150_probe(struct comedi_device *dev) |
fe14fa2b | 686 | { |
30f23066 | 687 | int id = ID_BITS(inw(dev->iobase + STATUS_REG)); |
a95b7ccf | 688 | |
30f23066 HS |
689 | if (id >= ARRAY_SIZE(a2150_boards)) |
690 | return NULL; | |
691 | ||
692 | return &a2150_boards[id]; | |
fe14fa2b HS |
693 | } |
694 | ||
695 | static int a2150_attach(struct comedi_device *dev, struct comedi_devconfig *it) | |
696 | { | |
94be3ef2 | 697 | const struct a2150_board *board; |
9a1a6cf8 | 698 | struct a2150_private *devpriv; |
fe14fa2b | 699 | struct comedi_subdevice *s; |
fe14fa2b HS |
700 | static const int timeout = 2000; |
701 | int i; | |
8b6c5694 | 702 | int ret; |
fe14fa2b | 703 | |
0bdab509 | 704 | devpriv = comedi_alloc_devpriv(dev, sizeof(*devpriv)); |
c34fa261 HS |
705 | if (!devpriv) |
706 | return -ENOMEM; | |
fe14fa2b | 707 | |
862755ec | 708 | ret = comedi_request_region(dev, it->options[0], 0x1c); |
3671cae1 HS |
709 | if (ret) |
710 | return ret; | |
fe14fa2b | 711 | |
94be3ef2 HS |
712 | board = a2150_probe(dev); |
713 | if (!board) | |
e988e1f3 | 714 | return -ENODEV; |
94be3ef2 HS |
715 | dev->board_ptr = board; |
716 | dev->board_name = board->name; | |
6cb8e1a2 | 717 | |
1a97f144 HS |
718 | /* an IRQ and DMA are required to support async commands */ |
719 | a2150_alloc_irq_and_dma(dev, it); | |
fe14fa2b | 720 | |
e875132a HS |
721 | dev->pacer = comedi_8254_init(dev->iobase + I8253_BASE_REG, |
722 | 0, I8254_IO8, 0); | |
723 | if (!dev->pacer) | |
724 | return -ENOMEM; | |
725 | ||
8b6c5694 HS |
726 | ret = comedi_alloc_subdevices(dev, 1); |
727 | if (ret) | |
728 | return ret; | |
fe14fa2b HS |
729 | |
730 | /* analog input subdevice */ | |
ca3caabb | 731 | s = &dev->subdevices[0]; |
fe14fa2b | 732 | s->type = COMEDI_SUBD_AI; |
6cb8e1a2 | 733 | s->subdev_flags = SDF_READABLE | SDF_GROUND | SDF_OTHER; |
fe14fa2b | 734 | s->n_chan = 4; |
fe14fa2b HS |
735 | s->maxdata = 0xffff; |
736 | s->range_table = &range_a2150; | |
fe14fa2b | 737 | s->insn_read = a2150_ai_rinsn; |
7cbb0ef9 | 738 | if (dev->irq) { |
6cb8e1a2 HS |
739 | dev->read_subdev = s; |
740 | s->subdev_flags |= SDF_CMD_READ; | |
741 | s->len_chanlist = s->n_chan; | |
742 | s->do_cmd = a2150_ai_cmd; | |
743 | s->do_cmdtest = a2150_ai_cmdtest; | |
744 | s->cancel = a2150_cancel; | |
745 | } | |
fe14fa2b | 746 | |
4281c748 | 747 | /* set card's irq and dma levels */ |
fe14fa2b HS |
748 | outw(devpriv->irq_dma_bits, dev->iobase + IRQ_DMA_CNTRL_REG); |
749 | ||
4281c748 | 750 | /* reset and sync adc clock circuitry */ |
fe14fa2b HS |
751 | outw_p(DPD_BIT | APD_BIT, dev->iobase + CONFIG_REG); |
752 | outw_p(DPD_BIT, dev->iobase + CONFIG_REG); | |
4281c748 | 753 | /* initialize configuration register */ |
fe14fa2b HS |
754 | devpriv->config_bits = 0; |
755 | outw(devpriv->config_bits, dev->iobase + CONFIG_REG); | |
4281c748 | 756 | /* wait until offset calibration is done, then enable analog inputs */ |
fe14fa2b HS |
757 | for (i = 0; i < timeout; i++) { |
758 | if ((DCAL_BIT & inw(dev->iobase + STATUS_REG)) == 0) | |
759 | break; | |
760 | udelay(1000); | |
761 | } | |
762 | if (i == timeout) { | |
bc0640a7 HS |
763 | dev_err(dev->class_dev, |
764 | "timed out waiting for offset calibration to complete\n"); | |
fe14fa2b HS |
765 | return -ETIME; |
766 | } | |
767 | devpriv->config_bits |= ENABLE0_BIT | ENABLE1_BIT; | |
768 | outw(devpriv->config_bits, dev->iobase + CONFIG_REG); | |
769 | ||
770 | return 0; | |
771 | }; | |
772 | ||
484ecc95 | 773 | static void a2150_detach(struct comedi_device *dev) |
fe14fa2b | 774 | { |
a32c6d00 | 775 | if (dev->iobase) |
fe14fa2b | 776 | outw(APD_BIT | DPD_BIT, dev->iobase + CONFIG_REG); |
b1478901 | 777 | a2150_free_dma(dev); |
a32c6d00 | 778 | comedi_legacy_detach(dev); |
fe14fa2b HS |
779 | }; |
780 | ||
781 | static struct comedi_driver ni_at_a2150_driver = { | |
782 | .driver_name = "ni_at_a2150", | |
783 | .module = THIS_MODULE, | |
784 | .attach = a2150_attach, | |
785 | .detach = a2150_detach, | |
786 | }; | |
787 | module_comedi_driver(ni_at_a2150_driver); | |
788 | ||
90f703d3 AT |
789 | MODULE_AUTHOR("Comedi http://www.comedi.org"); |
790 | MODULE_DESCRIPTION("Comedi low-level driver"); | |
791 | MODULE_LICENSE("GPL"); |