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staging: comedi: ni_mio_common: remove forward declaration 8
[deliverable/linux.git] / drivers / staging / comedi / drivers / ni_mio_common.c
CommitLineData
03aef4b6
DS		 1/*
2 comedi/drivers/ni_mio_common.c
3 Hardware driver for DAQ-STC based boards
4
5 COMEDI - Linux Control and Measurement Device Interface
6 Copyright (C) 1997-2001 David A. Schleef <ds@schleef.org>
7 Copyright (C) 2002-2006 Frank Mori Hess <fmhess@users.sourceforge.net>
8
9 This program is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 2 of the License, or
12 (at your option) any later version.
13
14 This program is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
03aef4b6
DS		 18*/
19
20/*
21 This file is meant to be included by another file, e.g.,
22 ni_atmio.c or ni_pcimio.c.
23
24 Interrupt support originally added by Truxton Fulton
25 <trux@truxton.com>
26
27 References (from ftp://ftp.natinst.com/support/manuals):
28
29 340747b.pdf AT-MIO E series Register Level Programmer Manual
30 341079b.pdf PCI E Series RLPM
31 340934b.pdf DAQ-STC reference manual
631dd1a8 32 67xx and 611x registers (from ftp://ftp.ni.com/support/daq/mhddk/documentation/)
03aef4b6
DS		 33 release_ni611x.pdf
34 release_ni67xx.pdf
35 Other possibly relevant info:
36
37 320517c.pdf User manual (obsolete)
38 320517f.pdf User manual (new)
39 320889a.pdf delete
40 320906c.pdf maximum signal ratings
41 321066a.pdf about 16x
42 321791a.pdf discontinuation of at-mio-16e-10 rev. c
43 321808a.pdf about at-mio-16e-10 rev P
44 321837a.pdf discontinuation of at-mio-16de-10 rev d
45 321838a.pdf about at-mio-16de-10 rev N
46
47 ISSUES:
48
49 - the interrupt routine needs to be cleaned up
50
51 2006-02-07: S-Series PCI-6143: Support has been added but is not
52 fully tested as yet. Terry Barnaby, BEAM Ltd.
53*/
54
25436dc9 55#include <linux/interrupt.h>
4377a026 56#include <linux/sched.h>
305591a5 57#include <linux/delay.h>
03aef4b6
DS		 58#include "8255.h"
59#include "mite.h"
60#include "comedi_fc.h"
61
03aef4b6
DS		 62/* A timeout count */
63#define NI_TIMEOUT 1000
64static const unsigned old_RTSI_clock_channel = 7;
65
66/* Note: this table must match the ai_gain_* definitions */
67static const short ni_gainlkup[][16] = {
68 [ai_gain_16] = {0, 1, 2, 3, 4, 5, 6, 7,
0a85b6f0 69 0x100, 0x101, 0x102, 0x103, 0x104, 0x105, 0x106, 0x107},
03aef4b6
DS		 70 [ai_gain_8] = {1, 2, 4, 7, 0x101, 0x102, 0x104, 0x107},
71 [ai_gain_14] = {1, 2, 3, 4, 5, 6, 7,
0a85b6f0 72 0x101, 0x102, 0x103, 0x104, 0x105, 0x106, 0x107},
03aef4b6
DS		 73 [ai_gain_4] = {0, 1, 4, 7},
74 [ai_gain_611x] = {0x00a, 0x00b, 0x001, 0x002,
0a85b6f0 75 0x003, 0x004, 0x005, 0x006},
03aef4b6
DS		 76 [ai_gain_622x] = {0, 1, 4, 5},
77 [ai_gain_628x] = {1, 2, 3, 4, 5, 6, 7},
78 [ai_gain_6143] = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
79};
80
daed6c72
HS		 81static const struct comedi_lrange range_ni_E_ai = {
82 16, {
83 BIP_RANGE(10),
84 BIP_RANGE(5),
85 BIP_RANGE(2.5),
86 BIP_RANGE(1),
87 BIP_RANGE(0.5),
88 BIP_RANGE(0.25),
89 BIP_RANGE(0.1),
90 BIP_RANGE(0.05),
91 UNI_RANGE(20),
92 UNI_RANGE(10),
93 UNI_RANGE(5),
94 UNI_RANGE(2),
95 UNI_RANGE(1),
96 UNI_RANGE(0.5),
97 UNI_RANGE(0.2),
98 UNI_RANGE(0.1)
99 }
03aef4b6 100};
0a85b6f0 101
daed6c72
HS		 102static const struct comedi_lrange range_ni_E_ai_limited = {
103 8, {
104 BIP_RANGE(10),
105 BIP_RANGE(5),
106 BIP_RANGE(1),
107 BIP_RANGE(0.1),
108 UNI_RANGE(10),
109 UNI_RANGE(5),
110 UNI_RANGE(1),
111 UNI_RANGE(0.1)
112 }
03aef4b6 113};
0a85b6f0 114
daed6c72
HS		 115static const struct comedi_lrange range_ni_E_ai_limited14 = {
116 14, {
117 BIP_RANGE(10),
118 BIP_RANGE(5),
119 BIP_RANGE(2),
120 BIP_RANGE(1),
121 BIP_RANGE(0.5),
122 BIP_RANGE(0.2),
123 BIP_RANGE(0.1),
124 UNI_RANGE(10),
125 UNI_RANGE(5),
126 UNI_RANGE(2),
127 UNI_RANGE(1),
128 UNI_RANGE(0.5),
129 UNI_RANGE(0.2),
130 UNI_RANGE(0.1)
131 }
03aef4b6 132};
0a85b6f0 133
daed6c72
HS		 134static const struct comedi_lrange range_ni_E_ai_bipolar4 = {
135 4, {
136 BIP_RANGE(10),
137 BIP_RANGE(5),
138 BIP_RANGE(0.5),
139 BIP_RANGE(0.05)
140 }
03aef4b6 141};
0a85b6f0 142
daed6c72
HS		 143static const struct comedi_lrange range_ni_E_ai_611x = {
144 8, {
145 BIP_RANGE(50),
146 BIP_RANGE(20),
147 BIP_RANGE(10),
148 BIP_RANGE(5),
149 BIP_RANGE(2),
150 BIP_RANGE(1),
151 BIP_RANGE(0.5),
152 BIP_RANGE(0.2)
153 }
03aef4b6 154};
0a85b6f0 155
daed6c72
HS		 156static const struct comedi_lrange range_ni_M_ai_622x = {
157 4, {
158 BIP_RANGE(10),
159 BIP_RANGE(5),
160 BIP_RANGE(1),
161 BIP_RANGE(0.2)
162 }
03aef4b6 163};
0a85b6f0 164
daed6c72
HS		 165static const struct comedi_lrange range_ni_M_ai_628x = {
166 7, {
167 BIP_RANGE(10),
168 BIP_RANGE(5),
169 BIP_RANGE(2),
170 BIP_RANGE(1),
171 BIP_RANGE(0.5),
172 BIP_RANGE(0.2),
173 BIP_RANGE(0.1)
174 }
03aef4b6 175};
0a85b6f0 176
daed6c72
HS		 177static const struct comedi_lrange range_ni_E_ao_ext = {
178 4, {
179 BIP_RANGE(10),
180 UNI_RANGE(10),
181 RANGE_ext(-1, 1),
182 RANGE_ext(0, 1)
183 }
03aef4b6
DS		 184};
185
9ced1de6 186static const struct comedi_lrange *const ni_range_lkup[] = {
03aef4b6
DS		 187 [ai_gain_16] = &range_ni_E_ai,
188 [ai_gain_8] = &range_ni_E_ai_limited,
189 [ai_gain_14] = &range_ni_E_ai_limited14,
190 [ai_gain_4] = &range_ni_E_ai_bipolar4,
191 [ai_gain_611x] = &range_ni_E_ai_611x,
192 [ai_gain_622x] = &range_ni_M_ai_622x,
193 [ai_gain_628x] = &range_ni_M_ai_628x,
50708d98 194 [ai_gain_6143] = &range_bipolar5
03aef4b6
DS		 195};
196
0a85b6f0
MT		 197static int ni_dio_insn_config(struct comedi_device *dev,
198 struct comedi_subdevice *s,
199 struct comedi_insn *insn, unsigned int *data);
200static int ni_dio_insn_bits(struct comedi_device *dev,
201 struct comedi_subdevice *s,
202 struct comedi_insn *insn, unsigned int *data);
203static int ni_cdio_cmdtest(struct comedi_device *dev,
204 struct comedi_subdevice *s, struct comedi_cmd *cmd);
da91b269 205static int ni_cdio_cmd(struct comedi_device *dev, struct comedi_subdevice *s);
0a85b6f0
MT		 206static int ni_cdio_cancel(struct comedi_device *dev,
207 struct comedi_subdevice *s);
da91b269
BP		 208static void handle_cdio_interrupt(struct comedi_device *dev);
209static int ni_cdo_inttrig(struct comedi_device *dev, struct comedi_subdevice *s,
0a85b6f0
MT		 210 unsigned int trignum);
211
212static int ni_serial_insn_config(struct comedi_device *dev,
213 struct comedi_subdevice *s,
214 struct comedi_insn *insn, unsigned int *data);
215static int ni_serial_hw_readwrite8(struct comedi_device *dev,
216 struct comedi_subdevice *s,
217 unsigned char data_out,
218 unsigned char *data_in);
219static int ni_serial_sw_readwrite8(struct comedi_device *dev,
220 struct comedi_subdevice *s,
221 unsigned char data_out,
222 unsigned char *data_in);
223
da91b269 224static void ni_rtsi_init(struct comedi_device *dev);
0a85b6f0
MT		 225static int ni_rtsi_insn_bits(struct comedi_device *dev,
226 struct comedi_subdevice *s,
227 struct comedi_insn *insn, unsigned int *data);
228static int ni_rtsi_insn_config(struct comedi_device *dev,
229 struct comedi_subdevice *s,
230 struct comedi_insn *insn, unsigned int *data);
03aef4b6 231
03aef4b6 232#ifndef PCIDMA
da91b269 233static void ni_handle_fifo_half_full(struct comedi_device *dev);
0a85b6f0
MT		 234static int ni_ao_fifo_half_empty(struct comedi_device *dev,
235 struct comedi_subdevice *s);
03aef4b6 236#endif
da91b269
BP		 237static void ni_handle_fifo_dregs(struct comedi_device *dev);
238static int ni_ai_inttrig(struct comedi_device *dev, struct comedi_subdevice *s,
0a85b6f0
MT		 239 unsigned int trignum);
240static void ni_load_channelgain_list(struct comedi_device *dev,
241 unsigned int n_chan, unsigned int *list);
da91b269 242static void shutdown_ai_command(struct comedi_device *dev);
03aef4b6 243
da91b269 244static int ni_ao_inttrig(struct comedi_device *dev, struct comedi_subdevice *s,
0a85b6f0 245 unsigned int trignum);
03aef4b6 246
da91b269 247static void handle_gpct_interrupt(struct comedi_device *dev,
0a85b6f0 248 unsigned short counter_index);
03aef4b6 249
da91b269 250static int ni_set_master_clock(struct comedi_device *dev, unsigned source,
0a85b6f0 251 unsigned period_ns);
da91b269
BP		 252static void ack_a_interrupt(struct comedi_device *dev, unsigned short a_status);
253static void ack_b_interrupt(struct comedi_device *dev, unsigned short b_status);
03aef4b6
DS		 254
255enum aimodes {
256 AIMODE_NONE = 0,
257 AIMODE_HALF_FULL = 1,
258 AIMODE_SCAN = 2,
259 AIMODE_SAMPLE = 3,
260};
261
262enum ni_common_subdevices {
263 NI_AI_SUBDEV,
264 NI_AO_SUBDEV,
265 NI_DIO_SUBDEV,
266 NI_8255_DIO_SUBDEV,
267 NI_UNUSED_SUBDEV,
268 NI_CALIBRATION_SUBDEV,
269 NI_EEPROM_SUBDEV,
270 NI_PFI_DIO_SUBDEV,
271 NI_CS5529_CALIBRATION_SUBDEV,
272 NI_SERIAL_SUBDEV,
273 NI_RTSI_SUBDEV,
274 NI_GPCT0_SUBDEV,
275 NI_GPCT1_SUBDEV,
276 NI_FREQ_OUT_SUBDEV,
277 NI_NUM_SUBDEVICES
278};
279static inline unsigned NI_GPCT_SUBDEV(unsigned counter_index)
280{
281 switch (counter_index) {
282 case 0:
283 return NI_GPCT0_SUBDEV;
284 break;
285 case 1:
286 return NI_GPCT1_SUBDEV;
287 break;
288 default:
289 break;
290 }
291 BUG();
292 return NI_GPCT0_SUBDEV;
293}
294
295enum timebase_nanoseconds {
296 TIMEBASE_1_NS = 50,
297 TIMEBASE_2_NS = 10000
298};
299
300#define SERIAL_DISABLED 0
301#define SERIAL_600NS 600
302#define SERIAL_1_2US 1200
303#define SERIAL_10US 10000
304
305static const int num_adc_stages_611x = 3;
306
da91b269 307static void handle_a_interrupt(struct comedi_device *dev, unsigned short status,
0a85b6f0 308 unsigned ai_mite_status);
da91b269 309static void handle_b_interrupt(struct comedi_device *dev, unsigned short status,
0a85b6f0 310 unsigned ao_mite_status);
da91b269
BP		 311static void get_last_sample_611x(struct comedi_device *dev);
312static void get_last_sample_6143(struct comedi_device *dev);
03aef4b6 313
da91b269 314static inline void ni_set_bitfield(struct comedi_device *dev, int reg,
0a85b6f0 315 unsigned bit_mask, unsigned bit_values)
03aef4b6 316{
0e05c552 317 struct ni_private *devpriv = dev->private;
03aef4b6
DS		 318 unsigned long flags;
319
5f74ea14 320 spin_lock_irqsave(&devpriv->soft_reg_copy_lock, flags);
03aef4b6
DS		 321 switch (reg) {
322 case Interrupt_A_Enable_Register:
323 devpriv->int_a_enable_reg &= ~bit_mask;
324 devpriv->int_a_enable_reg |= bit_values & bit_mask;
325 devpriv->stc_writew(dev, devpriv->int_a_enable_reg,
0a85b6f0 326 Interrupt_A_Enable_Register);
03aef4b6
DS		 327 break;
328 case Interrupt_B_Enable_Register:
329 devpriv->int_b_enable_reg &= ~bit_mask;
330 devpriv->int_b_enable_reg |= bit_values & bit_mask;
331 devpriv->stc_writew(dev, devpriv->int_b_enable_reg,
0a85b6f0 332 Interrupt_B_Enable_Register);
03aef4b6
DS		 333 break;
334 case IO_Bidirection_Pin_Register:
335 devpriv->io_bidirection_pin_reg &= ~bit_mask;
336 devpriv->io_bidirection_pin_reg |= bit_values & bit_mask;
337 devpriv->stc_writew(dev, devpriv->io_bidirection_pin_reg,
0a85b6f0 338 IO_Bidirection_Pin_Register);
03aef4b6
DS		 339 break;
340 case AI_AO_Select:
341 devpriv->ai_ao_select_reg &= ~bit_mask;
342 devpriv->ai_ao_select_reg |= bit_values & bit_mask;
343 ni_writeb(devpriv->ai_ao_select_reg, AI_AO_Select);
344 break;
345 case G0_G1_Select:
346 devpriv->g0_g1_select_reg &= ~bit_mask;
347 devpriv->g0_g1_select_reg |= bit_values & bit_mask;
348 ni_writeb(devpriv->g0_g1_select_reg, G0_G1_Select);
349 break;
350 default:
0a85b6f0 351 printk("Warning %s() called with invalid register\n", __func__);
5f74ea14 352 printk("reg is %d\n", reg);
03aef4b6
DS		 353 break;
354 }
355 mmiowb();
5f74ea14 356 spin_unlock_irqrestore(&devpriv->soft_reg_copy_lock, flags);
03aef4b6
DS		 357}
358
359#ifdef PCIDMA
da91b269 360static int ni_ai_drain_dma(struct comedi_device *dev);
03aef4b6
DS		 361
362/* DMA channel setup */
363
2696fb57 364/* negative channel means no channel */
da91b269 365static inline void ni_set_ai_dma_channel(struct comedi_device *dev, int channel)
03aef4b6
DS		 366{
367 unsigned bitfield;
368
369 if (channel >= 0) {
370 bitfield =
0a85b6f0
MT		 371 (ni_stc_dma_channel_select_bitfield(channel) <<
372 AI_DMA_Select_Shift) & AI_DMA_Select_Mask;
03aef4b6
DS		 373 } else {
374 bitfield = 0;
375 }
376 ni_set_bitfield(dev, AI_AO_Select, AI_DMA_Select_Mask, bitfield);
377}
378
2696fb57 379/* negative channel means no channel */
da91b269 380static inline void ni_set_ao_dma_channel(struct comedi_device *dev, int channel)
03aef4b6
DS		 381{
382 unsigned bitfield;
383
384 if (channel >= 0) {
385 bitfield =
0a85b6f0
MT		 386 (ni_stc_dma_channel_select_bitfield(channel) <<
387 AO_DMA_Select_Shift) & AO_DMA_Select_Mask;
03aef4b6
DS		 388 } else {
389 bitfield = 0;
390 }
391 ni_set_bitfield(dev, AI_AO_Select, AO_DMA_Select_Mask, bitfield);
392}
393
2696fb57 394/* negative mite_channel means no channel */
da91b269 395static inline void ni_set_gpct_dma_channel(struct comedi_device *dev,
0a85b6f0
MT		 396 unsigned gpct_index,
397 int mite_channel)
03aef4b6
DS		 398{
399 unsigned bitfield;
400
bc461556 401 if (mite_channel >= 0)
03aef4b6 402 bitfield = GPCT_DMA_Select_Bits(gpct_index, mite_channel);
bc461556 403 else
03aef4b6 404 bitfield = 0;
03aef4b6 405 ni_set_bitfield(dev, G0_G1_Select, GPCT_DMA_Select_Mask(gpct_index),
0a85b6f0 406 bitfield);
03aef4b6
DS		 407}
408
2696fb57 409/* negative mite_channel means no channel */
0a85b6f0
MT		 410static inline void ni_set_cdo_dma_channel(struct comedi_device *dev,
411 int mite_channel)
03aef4b6 412{
0e05c552 413 struct ni_private *devpriv = dev->private;
03aef4b6
DS		 414 unsigned long flags;
415
5f74ea14 416 spin_lock_irqsave(&devpriv->soft_reg_copy_lock, flags);
03aef4b6
DS		 417 devpriv->cdio_dma_select_reg &= ~CDO_DMA_Select_Mask;
418 if (mite_channel >= 0) {
419 /*XXX just guessing ni_stc_dma_channel_select_bitfield() returns the right bits,
420 under the assumption the cdio dma selection works just like ai/ao/gpct.
421 Definitely works for dma channels 0 and 1. */
422 devpriv->cdio_dma_select_reg |=
0a85b6f0
MT		 423 (ni_stc_dma_channel_select_bitfield(mite_channel) <<
424 CDO_DMA_Select_Shift) & CDO_DMA_Select_Mask;
03aef4b6
DS		 425 }
426 ni_writeb(devpriv->cdio_dma_select_reg, M_Offset_CDIO_DMA_Select);
427 mmiowb();
5f74ea14 428 spin_unlock_irqrestore(&devpriv->soft_reg_copy_lock, flags);
03aef4b6
DS		 429}
430
da91b269 431static int ni_request_ai_mite_channel(struct comedi_device *dev)
03aef4b6 432{
0e05c552 433 struct ni_private *devpriv = dev->private;
03aef4b6
DS		 434 unsigned long flags;
435
5f74ea14 436 spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
03aef4b6
DS		 437 BUG_ON(devpriv->ai_mite_chan);
438 devpriv->ai_mite_chan =
0a85b6f0 439 mite_request_channel(devpriv->mite, devpriv->ai_mite_ring);
03aef4b6 440 if (devpriv->ai_mite_chan == NULL) {
0a85b6f0 441 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
03aef4b6 442 comedi_error(dev,
0a85b6f0 443 "failed to reserve mite dma channel for analog input.");
03aef4b6
DS		 444 return -EBUSY;
445 }
446 devpriv->ai_mite_chan->dir = COMEDI_INPUT;
447 ni_set_ai_dma_channel(dev, devpriv->ai_mite_chan->channel);
5f74ea14 448 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
03aef4b6
DS		 449 return 0;
450}
451
da91b269 452static int ni_request_ao_mite_channel(struct comedi_device *dev)
03aef4b6 453{
0e05c552 454 struct ni_private *devpriv = dev->private;
03aef4b6
DS		 455 unsigned long flags;
456
5f74ea14 457 spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
03aef4b6
DS		 458 BUG_ON(devpriv->ao_mite_chan);
459 devpriv->ao_mite_chan =
0a85b6f0 460 mite_request_channel(devpriv->mite, devpriv->ao_mite_ring);
03aef4b6 461 if (devpriv->ao_mite_chan == NULL) {
0a85b6f0 462 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
03aef4b6 463 comedi_error(dev,
0a85b6f0 464 "failed to reserve mite dma channel for analog outut.");
03aef4b6
DS		 465 return -EBUSY;
466 }
467 devpriv->ao_mite_chan->dir = COMEDI_OUTPUT;
468 ni_set_ao_dma_channel(dev, devpriv->ao_mite_chan->channel);
5f74ea14 469 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
03aef4b6
DS		 470 return 0;
471}
472
da91b269 473static int ni_request_gpct_mite_channel(struct comedi_device *dev,
0a85b6f0
MT		 474 unsigned gpct_index,
475 enum comedi_io_direction direction)
03aef4b6 476{
0e05c552 477 struct ni_private *devpriv = dev->private;
03aef4b6
DS		 478 unsigned long flags;
479 struct mite_channel *mite_chan;
480
481 BUG_ON(gpct_index >= NUM_GPCT);
5f74ea14 482 spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
03aef4b6
DS		 483 BUG_ON(devpriv->counter_dev->counters[gpct_index].mite_chan);
484 mite_chan =
0a85b6f0
MT		 485 mite_request_channel(devpriv->mite,
486 devpriv->gpct_mite_ring[gpct_index]);
03aef4b6 487 if (mite_chan == NULL) {
0a85b6f0 488 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
03aef4b6 489 comedi_error(dev,
0a85b6f0 490 "failed to reserve mite dma channel for counter.");
03aef4b6
DS		 491 return -EBUSY;
492 }
493 mite_chan->dir = direction;
494 ni_tio_set_mite_channel(&devpriv->counter_dev->counters[gpct_index],
0a85b6f0 495 mite_chan);
03aef4b6 496 ni_set_gpct_dma_channel(dev, gpct_index, mite_chan->channel);
5f74ea14 497 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
03aef4b6
DS		 498 return 0;
499}
500
2696fb57 501#endif /* PCIDMA */
03aef4b6 502
da91b269 503static int ni_request_cdo_mite_channel(struct comedi_device *dev)
03aef4b6
DS		 504{
505#ifdef PCIDMA
0e05c552 506 struct ni_private *devpriv = dev->private;
03aef4b6
DS		 507 unsigned long flags;
508
5f74ea14 509 spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
03aef4b6
DS		 510 BUG_ON(devpriv->cdo_mite_chan);
511 devpriv->cdo_mite_chan =
0a85b6f0 512 mite_request_channel(devpriv->mite, devpriv->cdo_mite_ring);
03aef4b6 513 if (devpriv->cdo_mite_chan == NULL) {
0a85b6f0 514 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
03aef4b6 515 comedi_error(dev,
0a85b6f0 516 "failed to reserve mite dma channel for correlated digital outut.");
03aef4b6
DS		 517 return -EBUSY;
518 }
519 devpriv->cdo_mite_chan->dir = COMEDI_OUTPUT;
520 ni_set_cdo_dma_channel(dev, devpriv->cdo_mite_chan->channel);
5f74ea14 521 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
2696fb57 522#endif /* PCIDMA */
03aef4b6
DS		 523 return 0;
524}
525
da91b269 526static void ni_release_ai_mite_channel(struct comedi_device *dev)
03aef4b6
DS		 527{
528#ifdef PCIDMA
0e05c552 529 struct ni_private *devpriv = dev->private;
03aef4b6
DS		 530 unsigned long flags;
531
5f74ea14 532 spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
03aef4b6
DS		 533 if (devpriv->ai_mite_chan) {
534 ni_set_ai_dma_channel(dev, -1);
535 mite_release_channel(devpriv->ai_mite_chan);
536 devpriv->ai_mite_chan = NULL;
537 }
5f74ea14 538 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
2696fb57 539#endif /* PCIDMA */
03aef4b6
DS		 540}
541
da91b269 542static void ni_release_ao_mite_channel(struct comedi_device *dev)
03aef4b6
DS		 543{
544#ifdef PCIDMA
0e05c552 545 struct ni_private *devpriv = dev->private;
03aef4b6
DS		 546 unsigned long flags;
547
5f74ea14 548 spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
03aef4b6
DS		 549 if (devpriv->ao_mite_chan) {
550 ni_set_ao_dma_channel(dev, -1);
551 mite_release_channel(devpriv->ao_mite_chan);
552 devpriv->ao_mite_chan = NULL;
553 }
5f74ea14 554 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
2696fb57 555#endif /* PCIDMA */
03aef4b6
DS		 556}
557
03aef4b6 558#ifdef PCIDMA
29aba763
HS		 559static void ni_release_gpct_mite_channel(struct comedi_device *dev,
560 unsigned gpct_index)
561{
0e05c552 562 struct ni_private *devpriv = dev->private;
03aef4b6
DS		 563 unsigned long flags;
564
565 BUG_ON(gpct_index >= NUM_GPCT);
5f74ea14 566 spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
03aef4b6
DS		 567 if (devpriv->counter_dev->counters[gpct_index].mite_chan) {
568 struct mite_channel *mite_chan =
0a85b6f0 569 devpriv->counter_dev->counters[gpct_index].mite_chan;
03aef4b6
DS		 570
571 ni_set_gpct_dma_channel(dev, gpct_index, -1);
0a85b6f0
MT		 572 ni_tio_set_mite_channel(&devpriv->
573 counter_dev->counters[gpct_index],
574 NULL);
03aef4b6
DS		 575 mite_release_channel(mite_chan);
576 }
5f74ea14 577 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
03aef4b6 578}
29aba763 579#endif /* PCIDMA */
03aef4b6 580
da91b269 581static void ni_release_cdo_mite_channel(struct comedi_device *dev)
03aef4b6
DS		 582{
583#ifdef PCIDMA
0e05c552 584 struct ni_private *devpriv = dev->private;
03aef4b6
DS		 585 unsigned long flags;
586
5f74ea14 587 spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
03aef4b6
DS		 588 if (devpriv->cdo_mite_chan) {
589 ni_set_cdo_dma_channel(dev, -1);
590 mite_release_channel(devpriv->cdo_mite_chan);
591 devpriv->cdo_mite_chan = NULL;
592 }
5f74ea14 593 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
2696fb57 594#endif /* PCIDMA */
03aef4b6
DS		 595}
596
2696fb57 597/* e-series boards use the second irq signals to generate dma requests for their counters */
03aef4b6 598#ifdef PCIDMA
da91b269 599static void ni_e_series_enable_second_irq(struct comedi_device *dev,
0a85b6f0 600 unsigned gpct_index, short enable)
03aef4b6 601{
6293e357 602 const struct ni_board_struct *board = comedi_board(dev);
0e05c552
HS		 603 struct ni_private *devpriv = dev->private;
604
6293e357 605 if (board->reg_type & ni_reg_m_series_mask)
03aef4b6
DS		 606 return;
607 switch (gpct_index) {
608 case 0:
609 if (enable) {
610 devpriv->stc_writew(dev, G0_Gate_Second_Irq_Enable,
0a85b6f0 611 Second_IRQ_A_Enable_Register);
03aef4b6
DS		 612 } else {
613 devpriv->stc_writew(dev, 0,
0a85b6f0 614 Second_IRQ_A_Enable_Register);
03aef4b6
DS		 615 }
616 break;
617 case 1:
618 if (enable) {
619 devpriv->stc_writew(dev, G1_Gate_Second_Irq_Enable,
0a85b6f0 620 Second_IRQ_B_Enable_Register);
03aef4b6
DS		 621 } else {
622 devpriv->stc_writew(dev, 0,
0a85b6f0 623 Second_IRQ_B_Enable_Register);
03aef4b6
DS		 624 }
625 break;
626 default:
627 BUG();
628 break;
629 }
630}
2696fb57 631#endif /* PCIDMA */
03aef4b6 632
da91b269 633static void ni_clear_ai_fifo(struct comedi_device *dev)
03aef4b6 634{
6293e357 635 const struct ni_board_struct *board = comedi_board(dev);
0e05c552 636 struct ni_private *devpriv = dev->private;
60738f60
CS		 637 static const int timeout = 10000;
638 int i;
0e05c552 639
6293e357 640 if (board->reg_type == ni_reg_6143) {
2696fb57
BP		 641 /* Flush the 6143 data FIFO */
642 ni_writel(0x10, AIFIFO_Control_6143); /* Flush fifo */
643 ni_writel(0x00, AIFIFO_Control_6143); /* Flush fifo */
60738f60
CS		 644 /* Wait for complete */
645 for (i = 0; i < timeout; i++) {
646 if (!(ni_readl(AIFIFO_Status_6143) & 0x10))
647 break;
648 udelay(1);
649 }
650 if (i == timeout) {
651 comedi_error(dev, "FIFO flush timeout.");
652 }
03aef4b6
DS		 653 } else {
654 devpriv->stc_writew(dev, 1, ADC_FIFO_Clear);
6293e357 655 if (board->reg_type == ni_reg_625x) {
03aef4b6
DS		 656 ni_writeb(0, M_Offset_Static_AI_Control(0));
657 ni_writeb(1, M_Offset_Static_AI_Control(0));
658#if 0
659 /* the NI example code does 3 convert pulses for 625x boards,
660 but that appears to be wrong in practice. */
661 devpriv->stc_writew(dev, AI_CONVERT_Pulse,
0a85b6f0 662 AI_Command_1_Register);
03aef4b6 663 devpriv->stc_writew(dev, AI_CONVERT_Pulse,
0a85b6f0 664 AI_Command_1_Register);
03aef4b6 665 devpriv->stc_writew(dev, AI_CONVERT_Pulse,
0a85b6f0 666 AI_Command_1_Register);
03aef4b6
DS		 667#endif
668 }
669 }
670}
671
da91b269 672static void win_out2(struct comedi_device *dev, uint32_t data, int reg)
03aef4b6 673{
0e05c552
HS		 674 struct ni_private *devpriv = dev->private;
675
03aef4b6
DS		 676 devpriv->stc_writew(dev, data >> 16, reg);
677 devpriv->stc_writew(dev, data & 0xffff, reg + 1);
678}
679
da91b269 680static uint32_t win_in2(struct comedi_device *dev, int reg)
03aef4b6 681{
0e05c552 682 struct ni_private *devpriv = dev->private;
03aef4b6 683 uint32_t bits;
0e05c552 684
03aef4b6
DS		 685 bits = devpriv->stc_readw(dev, reg) << 16;
686 bits |= devpriv->stc_readw(dev, reg + 1);
687 return bits;
688}
689
f7cbd7aa 690#define ao_win_out(data, addr) ni_ao_win_outw(dev, data, addr)
0a85b6f0
MT		 691static inline void ni_ao_win_outw(struct comedi_device *dev, uint16_t data,
692 int addr)
03aef4b6 693{
0e05c552 694 struct ni_private *devpriv = dev->private;
03aef4b6
DS		 695 unsigned long flags;
696
5f74ea14 697 spin_lock_irqsave(&devpriv->window_lock, flags);
03aef4b6
DS		 698 ni_writew(addr, AO_Window_Address_611x);
699 ni_writew(data, AO_Window_Data_611x);
5f74ea14 700 spin_unlock_irqrestore(&devpriv->window_lock, flags);
03aef4b6
DS		 701}
702
0a85b6f0
MT		 703static inline void ni_ao_win_outl(struct comedi_device *dev, uint32_t data,
704 int addr)
03aef4b6 705{
0e05c552 706 struct ni_private *devpriv = dev->private;
03aef4b6
DS		 707 unsigned long flags;
708
5f74ea14 709 spin_lock_irqsave(&devpriv->window_lock, flags);
03aef4b6
DS		 710 ni_writew(addr, AO_Window_Address_611x);
711 ni_writel(data, AO_Window_Data_611x);
5f74ea14 712 spin_unlock_irqrestore(&devpriv->window_lock, flags);
03aef4b6
DS		 713}
714
da91b269 715static inline unsigned short ni_ao_win_inw(struct comedi_device *dev, int addr)
03aef4b6 716{
0e05c552 717 struct ni_private *devpriv = dev->private;
03aef4b6
DS		 718 unsigned long flags;
719 unsigned short data;
720
5f74ea14 721 spin_lock_irqsave(&devpriv->window_lock, flags);
03aef4b6
DS		 722 ni_writew(addr, AO_Window_Address_611x);
723 data = ni_readw(AO_Window_Data_611x);
5f74ea14 724 spin_unlock_irqrestore(&devpriv->window_lock, flags);
03aef4b6
DS		 725 return data;
726}
727
728/* ni_set_bits( ) allows different parts of the ni_mio_common driver to
729* share registers (such as Interrupt_A_Register) without interfering with
730* each other.
731*
732* NOTE: the switch/case statements are optimized out for a constant argument
733* so this is actually quite fast--- If you must wrap another function around this
734* make it inline to avoid a large speed penalty.
735*
736* value should only be 1 or 0.
737*/
0a85b6f0
MT		 738static inline void ni_set_bits(struct comedi_device *dev, int reg,
739 unsigned bits, unsigned value)
03aef4b6
DS		 740{
741 unsigned bit_values;
742
743 if (value)
744 bit_values = bits;
745 else
746 bit_values = 0;
747 ni_set_bitfield(dev, reg, bits, bit_values);
748}
749
70265d24 750static irqreturn_t ni_E_interrupt(int irq, void *d)
03aef4b6 751{
71b5f4f1 752 struct comedi_device *dev = d;
0e05c552 753 struct ni_private *devpriv = dev->private;
03aef4b6
DS		 754 unsigned short a_status;
755 unsigned short b_status;
756 unsigned int ai_mite_status = 0;
757 unsigned int ao_mite_status = 0;
758 unsigned long flags;
759#ifdef PCIDMA
760 struct mite_struct *mite = devpriv->mite;
761#endif
762
a7401cdd 763 if (!dev->attached)
03aef4b6 764 return IRQ_NONE;
2696fb57 765 smp_mb(); /* make sure dev->attached is checked before handler does anything else. */
03aef4b6 766
2696fb57 767 /* lock to avoid race with comedi_poll */
5f74ea14 768 spin_lock_irqsave(&dev->spinlock, flags);
03aef4b6
DS		 769 a_status = devpriv->stc_readw(dev, AI_Status_1_Register);
770 b_status = devpriv->stc_readw(dev, AO_Status_1_Register);
771#ifdef PCIDMA
772 if (mite) {
773 unsigned long flags_too;
774
5f74ea14 775 spin_lock_irqsave(&devpriv->mite_channel_lock, flags_too);
03aef4b6
DS		 776 if (devpriv->ai_mite_chan) {
777 ai_mite_status = mite_get_status(devpriv->ai_mite_chan);
778 if (ai_mite_status & CHSR_LINKC)
779 writel(CHOR_CLRLC,
0a85b6f0
MT		 780 devpriv->mite->mite_io_addr +
781 MITE_CHOR(devpriv->
782 ai_mite_chan->channel));
03aef4b6
DS		 783 }
784 if (devpriv->ao_mite_chan) {
785 ao_mite_status = mite_get_status(devpriv->ao_mite_chan);
786 if (ao_mite_status & CHSR_LINKC)
787 writel(CHOR_CLRLC,
0a85b6f0
MT		 788 mite->mite_io_addr +
789 MITE_CHOR(devpriv->
790 ao_mite_chan->channel));
03aef4b6 791 }
5f74ea14 792 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags_too);
03aef4b6
DS		 793 }
794#endif
795 ack_a_interrupt(dev, a_status);
796 ack_b_interrupt(dev, b_status);
797 if ((a_status & Interrupt_A_St) || (ai_mite_status & CHSR_INT))
798 handle_a_interrupt(dev, a_status, ai_mite_status);
799 if ((b_status & Interrupt_B_St) || (ao_mite_status & CHSR_INT))
800 handle_b_interrupt(dev, b_status, ao_mite_status);
801 handle_gpct_interrupt(dev, 0);
802 handle_gpct_interrupt(dev, 1);
803 handle_cdio_interrupt(dev);
804
5f74ea14 805 spin_unlock_irqrestore(&dev->spinlock, flags);
03aef4b6
DS		 806 return IRQ_HANDLED;
807}
808
809#ifdef PCIDMA
da91b269 810static void ni_sync_ai_dma(struct comedi_device *dev)
03aef4b6 811{
0e05c552 812 struct ni_private *devpriv = dev->private;
f9cd92eb 813 struct comedi_subdevice *s = &dev->subdevices[NI_AI_SUBDEV];
03aef4b6
DS		 814 unsigned long flags;
815
5f74ea14 816 spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
03aef4b6 817 if (devpriv->ai_mite_chan)
74f63db7 818 mite_sync_input_dma(devpriv->ai_mite_chan, s);
5f74ea14 819 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
03aef4b6
DS		 820}
821
0a85b6f0
MT		 822static void mite_handle_b_linkc(struct mite_struct *mite,
823 struct comedi_device *dev)
03aef4b6 824{
0e05c552 825 struct ni_private *devpriv = dev->private;
f9cd92eb 826 struct comedi_subdevice *s = &dev->subdevices[NI_AO_SUBDEV];
03aef4b6
DS		 827 unsigned long flags;
828
5f74ea14 829 spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
bc461556 830 if (devpriv->ao_mite_chan)
1e575a9c 831 mite_sync_output_dma(devpriv->ao_mite_chan, s);
5f74ea14 832 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
03aef4b6
DS		 833}
834
da91b269 835static int ni_ao_wait_for_dma_load(struct comedi_device *dev)
03aef4b6 836{
0e05c552 837 struct ni_private *devpriv = dev->private;
03aef4b6
DS		 838 static const int timeout = 10000;
839 int i;
840 for (i = 0; i < timeout; i++) {
841 unsigned short b_status;
842
843 b_status = devpriv->stc_readw(dev, AO_Status_1_Register);
844 if (b_status & AO_FIFO_Half_Full_St)
845 break;
846 /* if we poll too often, the pci bus activity seems
847 to slow the dma transfer down */
5f74ea14 848 udelay(10);
03aef4b6
DS		 849 }
850 if (i == timeout) {
851 comedi_error(dev, "timed out waiting for dma load");
852 return -EPIPE;
853 }
854 return 0;
855}
856
2696fb57 857#endif /* PCIDMA */
da91b269 858static void ni_handle_eos(struct comedi_device *dev, struct comedi_subdevice *s)
03aef4b6 859{
0e05c552
HS		 860 struct ni_private *devpriv = dev->private;
861
03aef4b6
DS		 862 if (devpriv->aimode == AIMODE_SCAN) {
863#ifdef PCIDMA
864 static const int timeout = 10;
865 int i;
866
867 for (i = 0; i < timeout; i++) {
868 ni_sync_ai_dma(dev);
869 if ((s->async->events & COMEDI_CB_EOS))
870 break;
5f74ea14 871 udelay(1);
03aef4b6
DS		 872 }
873#else
874 ni_handle_fifo_dregs(dev);
875 s->async->events |= COMEDI_CB_EOS;
876#endif
877 }
878 /* handle special case of single scan using AI_End_On_End_Of_Scan */
bc461556 879 if ((devpriv->ai_cmd2 & AI_End_On_End_Of_Scan))
03aef4b6 880 shutdown_ai_command(dev);
03aef4b6
DS		 881}
882
da91b269 883static void shutdown_ai_command(struct comedi_device *dev)
03aef4b6 884{
f9cd92eb 885 struct comedi_subdevice *s = &dev->subdevices[NI_AI_SUBDEV];
03aef4b6
DS		 886
887#ifdef PCIDMA
888 ni_ai_drain_dma(dev);
889#endif
890 ni_handle_fifo_dregs(dev);
891 get_last_sample_611x(dev);
892 get_last_sample_6143(dev);
893
894 s->async->events |= COMEDI_CB_EOA;
895}
896
da91b269 897static void handle_gpct_interrupt(struct comedi_device *dev,
0a85b6f0 898 unsigned short counter_index)
03aef4b6
DS		 899{
900#ifdef PCIDMA
0e05c552 901 struct ni_private *devpriv = dev->private;
f9cd92eb
HS		 902 struct comedi_subdevice *s;
903
904 s = &dev->subdevices[NI_GPCT_SUBDEV(counter_index)];
03aef4b6
DS		 905
906 ni_tio_handle_interrupt(&devpriv->counter_dev->counters[counter_index],
0a85b6f0 907 s);
a21eacfe 908 cfc_handle_events(dev, s);
03aef4b6
DS		 909#endif
910}
911
da91b269 912static void ack_a_interrupt(struct comedi_device *dev, unsigned short a_status)
03aef4b6 913{
0e05c552 914 struct ni_private *devpriv = dev->private;
03aef4b6
DS		 915 unsigned short ack = 0;
916
bc461556 917 if (a_status & AI_SC_TC_St)
03aef4b6 918 ack |= AI_SC_TC_Interrupt_Ack;
bc461556 919 if (a_status & AI_START1_St)
03aef4b6 920 ack |= AI_START1_Interrupt_Ack;
bc461556 921 if (a_status & AI_START_St)
03aef4b6 922 ack |= AI_START_Interrupt_Ack;
bc461556 923 if (a_status & AI_STOP_St)
03aef4b6 924 /* not sure why we used to ack the START here also, instead of doing it independently. Frank Hess 2007-07-06 */
69ba8358 925 ack |= AI_STOP_Interrupt_Ack /*| AI_START_Interrupt_Ack */;
03aef4b6
DS		 926 if (ack)
927 devpriv->stc_writew(dev, ack, Interrupt_A_Ack_Register);
928}
929
da91b269 930static void handle_a_interrupt(struct comedi_device *dev, unsigned short status,
0a85b6f0 931 unsigned ai_mite_status)
03aef4b6 932{
0e05c552 933 struct ni_private *devpriv = dev->private;
f9cd92eb 934 struct comedi_subdevice *s = &dev->subdevices[NI_AI_SUBDEV];
03aef4b6 935
2696fb57 936 /* 67xx boards don't have ai subdevice, but their gpct0 might generate an a interrupt */
03aef4b6
DS		 937 if (s->type == COMEDI_SUBD_UNUSED)
938 return;
939
03aef4b6 940#ifdef PCIDMA
bc461556 941 if (ai_mite_status & CHSR_LINKC)
03aef4b6 942 ni_sync_ai_dma(dev);
03aef4b6
DS		 943
944 if (ai_mite_status & ~(CHSR_INT | CHSR_LINKC | CHSR_DONE | CHSR_MRDY |
0a85b6f0
MT		 945 CHSR_DRDY | CHSR_DRQ1 | CHSR_DRQ0 | CHSR_ERROR |
946 CHSR_SABORT | CHSR_XFERR | CHSR_LxERR_mask)) {
5f74ea14 947 printk
0a85b6f0
MT		 948 ("unknown mite interrupt, ack! (ai_mite_status=%08x)\n",
949 ai_mite_status);
03aef4b6 950 s->async->events |= COMEDI_CB_ERROR | COMEDI_CB_EOA;
2696fb57 951 /* disable_irq(dev->irq); */
03aef4b6
DS		 952 }
953#endif
954
955 /* test for all uncommon interrupt events at the same time */
956 if (status & (AI_Overrun_St | AI_Overflow_St | AI_SC_TC_Error_St |
0a85b6f0 957 AI_SC_TC_St | AI_START1_St)) {
03aef4b6 958 if (status == 0xffff) {
5f74ea14 959 printk
0a85b6f0 960 ("ni_mio_common: a_status=0xffff. Card removed?\n");
03aef4b6
DS		 961 /* we probably aren't even running a command now,
962 * so it's a good idea to be careful. */
f0124630 963 if (comedi_is_subdevice_running(s)) {
03aef4b6 964 s->async->events |=
0a85b6f0 965 COMEDI_CB_ERROR | COMEDI_CB_EOA;
a21eacfe 966 cfc_handle_events(dev, s);
03aef4b6
DS		 967 }
968 return;
969 }
970 if (status & (AI_Overrun_St | AI_Overflow_St |
0a85b6f0 971 AI_SC_TC_Error_St)) {
5f74ea14 972 printk("ni_mio_common: ai error a_status=%04x\n",
0a85b6f0 973 status);
03aef4b6
DS		 974
975 shutdown_ai_command(dev);
976
977 s->async->events |= COMEDI_CB_ERROR;
978 if (status & (AI_Overrun_St | AI_Overflow_St))
979 s->async->events |= COMEDI_CB_OVERFLOW;
980
a21eacfe 981 cfc_handle_events(dev, s);
03aef4b6
DS		 982 return;
983 }
984 if (status & AI_SC_TC_St) {
bc461556 985 if (!devpriv->ai_continuous)
03aef4b6 986 shutdown_ai_command(dev);
03aef4b6
DS		 987 }
988 }
989#ifndef PCIDMA
990 if (status & AI_FIFO_Half_Full_St) {
991 int i;
992 static const int timeout = 10;
993 /* pcmcia cards (at least 6036) seem to stop producing interrupts if we
994 *fail to get the fifo less than half full, so loop to be sure.*/
995 for (i = 0; i < timeout; ++i) {
996 ni_handle_fifo_half_full(dev);
997 if ((devpriv->stc_readw(dev,
998 AI_Status_1_Register) &
0a85b6f0 999 AI_FIFO_Half_Full_St) == 0)
03aef4b6
DS		 1000 break;
1001 }
1002 }
2696fb57 1003#endif /* !PCIDMA */
03aef4b6 1004
bc461556 1005 if ((status & AI_STOP_St))
03aef4b6 1006 ni_handle_eos(dev, s);
03aef4b6 1007
a21eacfe 1008 cfc_handle_events(dev, s);
03aef4b6
DS		 1009}
1010
da91b269 1011static void ack_b_interrupt(struct comedi_device *dev, unsigned short b_status)
03aef4b6 1012{
0e05c552 1013 struct ni_private *devpriv = dev->private;
03aef4b6 1014 unsigned short ack = 0;
0e05c552 1015
bc461556 1016 if (b_status & AO_BC_TC_St)
03aef4b6 1017 ack |= AO_BC_TC_Interrupt_Ack;
bc461556 1018 if (b_status & AO_Overrun_St)
03aef4b6 1019 ack |= AO_Error_Interrupt_Ack;
bc461556 1020 if (b_status & AO_START_St)
03aef4b6 1021 ack |= AO_START_Interrupt_Ack;
bc461556 1022 if (b_status & AO_START1_St)
03aef4b6 1023 ack |= AO_START1_Interrupt_Ack;
bc461556 1024 if (b_status & AO_UC_TC_St)
03aef4b6 1025 ack |= AO_UC_TC_Interrupt_Ack;
bc461556 1026 if (b_status & AO_UI2_TC_St)
03aef4b6 1027 ack |= AO_UI2_TC_Interrupt_Ack;
bc461556 1028 if (b_status & AO_UPDATE_St)
03aef4b6 1029 ack |= AO_UPDATE_Interrupt_Ack;
03aef4b6
DS		 1030 if (ack)
1031 devpriv->stc_writew(dev, ack, Interrupt_B_Ack_Register);
1032}
1033
0a85b6f0
MT		 1034static void handle_b_interrupt(struct comedi_device *dev,
1035 unsigned short b_status, unsigned ao_mite_status)
03aef4b6 1036{
0e05c552 1037 struct ni_private *devpriv = dev->private;
f9cd92eb 1038 struct comedi_subdevice *s = &dev->subdevices[NI_AO_SUBDEV];
2696fb57 1039 /* unsigned short ack=0; */
0e05c552 1040
03aef4b6
DS		 1041#ifdef PCIDMA
1042 /* Currently, mite.c requires us to handle LINKC */
bc461556 1043 if (ao_mite_status & CHSR_LINKC)
03aef4b6 1044 mite_handle_b_linkc(devpriv->mite, dev);
03aef4b6
DS		 1045
1046 if (ao_mite_status & ~(CHSR_INT | CHSR_LINKC | CHSR_DONE | CHSR_MRDY |
0a85b6f0
MT		 1047 CHSR_DRDY | CHSR_DRQ1 | CHSR_DRQ0 | CHSR_ERROR |
1048 CHSR_SABORT | CHSR_XFERR | CHSR_LxERR_mask)) {
5f74ea14 1049 printk
0a85b6f0
MT		 1050 ("unknown mite interrupt, ack! (ao_mite_status=%08x)\n",
1051 ao_mite_status);
03aef4b6
DS		 1052 s->async->events |= COMEDI_CB_EOA | COMEDI_CB_ERROR;
1053 }
1054#endif
1055
1056 if (b_status == 0xffff)
1057 return;
1058 if (b_status & AO_Overrun_St) {
5f74ea14 1059 printk
0a85b6f0
MT		 1060 ("ni_mio_common: AO FIFO underrun status=0x%04x status2=0x%04x\n",
1061 b_status, devpriv->stc_readw(dev, AO_Status_2_Register));
03aef4b6
DS		 1062 s->async->events |= COMEDI_CB_OVERFLOW;
1063 }
1064
a7866a6e 1065 if (b_status & AO_BC_TC_St)
03aef4b6 1066 s->async->events |= COMEDI_CB_EOA;
a7866a6e 1067
03aef4b6
DS		 1068#ifndef PCIDMA
1069 if (b_status & AO_FIFO_Request_St) {
1070 int ret;
1071
1072 ret = ni_ao_fifo_half_empty(dev, s);
1073 if (!ret) {
5f74ea14 1074 printk("ni_mio_common: AO buffer underrun\n");
03aef4b6 1075 ni_set_bits(dev, Interrupt_B_Enable_Register,
0a85b6f0
MT		 1076 AO_FIFO_Interrupt_Enable |
1077 AO_Error_Interrupt_Enable, 0);
03aef4b6
DS		 1078 s->async->events |= COMEDI_CB_OVERFLOW;
1079 }
1080 }
1081#endif
1082
a21eacfe 1083 cfc_handle_events(dev, s);
03aef4b6
DS		 1084}
1085
03aef4b6
DS		 1086#ifndef PCIDMA
1087
0a85b6f0
MT		 1088static void ni_ao_fifo_load(struct comedi_device *dev,
1089 struct comedi_subdevice *s, int n)
03aef4b6 1090{
6293e357 1091 const struct ni_board_struct *board = comedi_board(dev);
d163679c 1092 struct comedi_async *async = s->async;
ea6d0d4c 1093 struct comedi_cmd *cmd = &async->cmd;
03aef4b6
DS		 1094 int chan;
1095 int i;
3a2b101c 1096 unsigned short d;
03aef4b6
DS		 1097 u32 packed_data;
1098 int range;
1099 int err = 1;
1100
1101 chan = async->cur_chan;
1102 for (i = 0; i < n; i++) {
458c13e9 1103 err &= comedi_buf_get(s, &d);
03aef4b6
DS		 1104 if (err == 0)
1105 break;
1106
1107 range = CR_RANGE(cmd->chanlist[chan]);
1108
6293e357 1109 if (board->reg_type & ni_reg_6xxx_mask) {
03aef4b6
DS		 1110 packed_data = d & 0xffff;
1111 /* 6711 only has 16 bit wide ao fifo */
6293e357 1112 if (board->reg_type != ni_reg_6711) {
458c13e9 1113 err &= comedi_buf_get(s, &d);
03aef4b6
DS		 1114 if (err == 0)
1115 break;
1116 chan++;
1117 i++;
1118 packed_data |= (d << 16) & 0xffff0000;
1119 }
1120 ni_writel(packed_data, DAC_FIFO_Data_611x);
1121 } else {
1122 ni_writew(d, DAC_FIFO_Data);
1123 }
1124 chan++;
1125 chan %= cmd->chanlist_len;
1126 }
1127 async->cur_chan = chan;
bc461556 1128 if (err == 0)
03aef4b6 1129 async->events |= COMEDI_CB_OVERFLOW;
03aef4b6
DS		 1130}
1131
1132/*
1133 * There's a small problem if the FIFO gets really low and we
1134 * don't have the data to fill it. Basically, if after we fill
1135 * the FIFO with all the data available, the FIFO is _still_
1136 * less than half full, we never clear the interrupt. If the
1137 * IRQ is in edge mode, we never get another interrupt, because
1138 * this one wasn't cleared. If in level mode, we get flooded
1139 * with interrupts that we can't fulfill, because nothing ever
1140 * gets put into the buffer.
1141 *
1142 * This kind of situation is recoverable, but it is easier to
1143 * just pretend we had a FIFO underrun, since there is a good
1144 * chance it will happen anyway. This is _not_ the case for
1145 * RT code, as RT code might purposely be running close to the
1146 * metal. Needs to be fixed eventually.
1147 */
0a85b6f0
MT		 1148static int ni_ao_fifo_half_empty(struct comedi_device *dev,
1149 struct comedi_subdevice *s)
03aef4b6 1150{
6293e357 1151 const struct ni_board_struct *board = comedi_board(dev);
03aef4b6
DS		 1152 int n;
1153
e9edef3a 1154 n = comedi_buf_read_n_available(s);
03aef4b6
DS		 1155 if (n == 0) {
1156 s->async->events |= COMEDI_CB_OVERFLOW;
1157 return 0;
1158 }
1159
790c5541 1160 n /= sizeof(short);
6293e357
HS		 1161 if (n > board->ao_fifo_depth / 2)
1162 n = board->ao_fifo_depth / 2;
03aef4b6
DS		 1163
1164 ni_ao_fifo_load(dev, s, n);
1165
1166 s->async->events |= COMEDI_CB_BLOCK;
1167
1168 return 1;
1169}
1170
0a85b6f0
MT		 1171static int ni_ao_prep_fifo(struct comedi_device *dev,
1172 struct comedi_subdevice *s)
03aef4b6 1173{
6293e357 1174 const struct ni_board_struct *board = comedi_board(dev);
0e05c552 1175 struct ni_private *devpriv = dev->private;
03aef4b6
DS		 1176 int n;
1177
1178 /* reset fifo */
1179 devpriv->stc_writew(dev, 1, DAC_FIFO_Clear);
6293e357 1180 if (board->reg_type & ni_reg_6xxx_mask)
03aef4b6
DS		 1181 ni_ao_win_outl(dev, 0x6, AO_FIFO_Offset_Load_611x);
1182
1183 /* load some data */
e9edef3a 1184 n = comedi_buf_read_n_available(s);
03aef4b6
DS		 1185 if (n == 0)
1186 return 0;
1187
790c5541 1188 n /= sizeof(short);
6293e357
HS		 1189 if (n > board->ao_fifo_depth)
1190 n = board->ao_fifo_depth;
03aef4b6
DS		 1191
1192 ni_ao_fifo_load(dev, s, n);
1193
1194 return n;
1195}
1196
0a85b6f0
MT		 1197static void ni_ai_fifo_read(struct comedi_device *dev,
1198 struct comedi_subdevice *s, int n)
03aef4b6 1199{
6293e357 1200 const struct ni_board_struct *board = comedi_board(dev);
0e05c552 1201 struct ni_private *devpriv = dev->private;
d163679c 1202 struct comedi_async *async = s->async;
03aef4b6
DS		 1203 int i;
1204
6293e357 1205 if (board->reg_type == ni_reg_611x) {
3a2b101c 1206 unsigned short data[2];
03aef4b6
DS		 1207 u32 dl;
1208
1209 for (i = 0; i < n / 2; i++) {
1210 dl = ni_readl(ADC_FIFO_Data_611x);
1211 /* This may get the hi/lo data in the wrong order */
1212 data[0] = (dl >> 16) & 0xffff;
1213 data[1] = dl & 0xffff;
1214 cfc_write_array_to_buffer(s, data, sizeof(data));
1215 }
1216 /* Check if there's a single sample stuck in the FIFO */
1217 if (n % 2) {
1218 dl = ni_readl(ADC_FIFO_Data_611x);
1219 data[0] = dl & 0xffff;
1220 cfc_write_to_buffer(s, data[0]);
1221 }
6293e357 1222 } else if (board->reg_type == ni_reg_6143) {
3a2b101c 1223 unsigned short data[2];
03aef4b6
DS		 1224 u32 dl;
1225
2696fb57 1226 /* This just reads the FIFO assuming the data is present, no checks on the FIFO status are performed */
03aef4b6
DS		 1227 for (i = 0; i < n / 2; i++) {
1228 dl = ni_readl(AIFIFO_Data_6143);
1229
1230 data[0] = (dl >> 16) & 0xffff;
1231 data[1] = dl & 0xffff;
1232 cfc_write_array_to_buffer(s, data, sizeof(data));
1233 }
1234 if (n % 2) {
1235 /* Assume there is a single sample stuck in the FIFO */
2696fb57 1236 ni_writel(0x01, AIFIFO_Control_6143); /* Get stranded sample into FIFO */
03aef4b6
DS		 1237 dl = ni_readl(AIFIFO_Data_6143);
1238 data[0] = (dl >> 16) & 0xffff;
1239 cfc_write_to_buffer(s, data[0]);
1240 }
1241 } else {
1242 if (n > sizeof(devpriv->ai_fifo_buffer) /
0a85b6f0 1243 sizeof(devpriv->ai_fifo_buffer[0])) {
03aef4b6
DS		 1244 comedi_error(dev, "bug! ai_fifo_buffer too small");
1245 async->events |= COMEDI_CB_ERROR;
1246 return;
1247 }
1248 for (i = 0; i < n; i++) {
1249 devpriv->ai_fifo_buffer[i] =
0a85b6f0 1250 ni_readw(ADC_FIFO_Data_Register);
03aef4b6
DS		 1251 }
1252 cfc_write_array_to_buffer(s, devpriv->ai_fifo_buffer,
0a85b6f0
MT		 1253 n *
1254 sizeof(devpriv->ai_fifo_buffer[0]));
03aef4b6
DS		 1255 }
1256}
1257
da91b269 1258static void ni_handle_fifo_half_full(struct comedi_device *dev)
03aef4b6 1259{
6293e357 1260 const struct ni_board_struct *board = comedi_board(dev);
f9cd92eb 1261 struct comedi_subdevice *s = &dev->subdevices[NI_AI_SUBDEV];
6293e357 1262 int n;
03aef4b6 1263
6293e357 1264 n = board->ai_fifo_depth / 2;
03aef4b6
DS		 1265
1266 ni_ai_fifo_read(dev, s, n);
1267}
1268#endif
1269
1270#ifdef PCIDMA
da91b269 1271static int ni_ai_drain_dma(struct comedi_device *dev)
03aef4b6 1272{
0e05c552 1273 struct ni_private *devpriv = dev->private;
03aef4b6
DS		 1274 int i;
1275 static const int timeout = 10000;
1276 unsigned long flags;
1277 int retval = 0;
1278
5f74ea14 1279 spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
03aef4b6
DS		 1280 if (devpriv->ai_mite_chan) {
1281 for (i = 0; i < timeout; i++) {
1282 if ((devpriv->stc_readw(dev,
1283 AI_Status_1_Register) &
0a85b6f0
MT		 1284 AI_FIFO_Empty_St)
1285 && mite_bytes_in_transit(devpriv->ai_mite_chan) ==
1286 0)
03aef4b6 1287 break;
5f74ea14 1288 udelay(5);
03aef4b6
DS		 1289 }
1290 if (i == timeout) {
0a85b6f0 1291 printk("ni_mio_common: wait for dma drain timed out\n");
5f74ea14 1292 printk
0a85b6f0
MT		 1293 ("mite_bytes_in_transit=%i, AI_Status1_Register=0x%x\n",
1294 mite_bytes_in_transit(devpriv->ai_mite_chan),
1295 devpriv->stc_readw(dev, AI_Status_1_Register));
03aef4b6
DS		 1296 retval = -1;
1297 }
1298 }
5f74ea14 1299 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
03aef4b6
DS		 1300
1301 ni_sync_ai_dma(dev);
1302
1303 return retval;
1304}
1305#endif
1306/*
1307 Empties the AI fifo
1308*/
da91b269 1309static void ni_handle_fifo_dregs(struct comedi_device *dev)
03aef4b6 1310{
6293e357 1311 const struct ni_board_struct *board = comedi_board(dev);
0e05c552 1312 struct ni_private *devpriv = dev->private;
f9cd92eb 1313 struct comedi_subdevice *s = &dev->subdevices[NI_AI_SUBDEV];
3a2b101c 1314 unsigned short data[2];
03aef4b6 1315 u32 dl;
3a2b101c 1316 unsigned short fifo_empty;
03aef4b6
DS		 1317 int i;
1318
6293e357 1319 if (board->reg_type == ni_reg_611x) {
03aef4b6 1320 while ((devpriv->stc_readw(dev,
0a85b6f0
MT		 1321 AI_Status_1_Register) &
1322 AI_FIFO_Empty_St) == 0) {
03aef4b6
DS		 1323 dl = ni_readl(ADC_FIFO_Data_611x);
1324
1325 /* This may get the hi/lo data in the wrong order */
1326 data[0] = (dl >> 16);
1327 data[1] = (dl & 0xffff);
1328 cfc_write_array_to_buffer(s, data, sizeof(data));
1329 }
6293e357 1330 } else if (board->reg_type == ni_reg_6143) {
03aef4b6
DS		 1331 i = 0;
1332 while (ni_readl(AIFIFO_Status_6143) & 0x04) {
1333 dl = ni_readl(AIFIFO_Data_6143);
1334
1335 /* This may get the hi/lo data in the wrong order */
1336 data[0] = (dl >> 16);
1337 data[1] = (dl & 0xffff);
1338 cfc_write_array_to_buffer(s, data, sizeof(data));
1339 i += 2;
1340 }
2696fb57 1341 /* Check if stranded sample is present */
03aef4b6 1342 if (ni_readl(AIFIFO_Status_6143) & 0x01) {
2696fb57 1343 ni_writel(0x01, AIFIFO_Control_6143); /* Get stranded sample into FIFO */
03aef4b6
DS		 1344 dl = ni_readl(AIFIFO_Data_6143);
1345 data[0] = (dl >> 16) & 0xffff;
1346 cfc_write_to_buffer(s, data[0]);
1347 }
1348
1349 } else {
1350 fifo_empty =
0a85b6f0
MT		 1351 devpriv->stc_readw(dev,
1352 AI_Status_1_Register) & AI_FIFO_Empty_St;
03aef4b6
DS		 1353 while (fifo_empty == 0) {
1354 for (i = 0;
0a85b6f0
MT		 1355 i <
1356 sizeof(devpriv->ai_fifo_buffer) /
1357 sizeof(devpriv->ai_fifo_buffer[0]); i++) {
03aef4b6 1358 fifo_empty =
0a85b6f0
MT		 1359 devpriv->stc_readw(dev,
1360 AI_Status_1_Register) &
1361 AI_FIFO_Empty_St;
03aef4b6
DS		 1362 if (fifo_empty)
1363 break;
1364 devpriv->ai_fifo_buffer[i] =
0a85b6f0 1365 ni_readw(ADC_FIFO_Data_Register);
03aef4b6
DS		 1366 }
1367 cfc_write_array_to_buffer(s, devpriv->ai_fifo_buffer,
0a85b6f0
MT		 1368 i *
1369 sizeof(devpriv->
1370 ai_fifo_buffer[0]));
03aef4b6
DS		 1371 }
1372 }
1373}
1374
da91b269 1375static void get_last_sample_611x(struct comedi_device *dev)
03aef4b6 1376{
6293e357 1377 const struct ni_board_struct *board = comedi_board(dev);
0e05c552 1378 struct ni_private *devpriv __maybe_unused = dev->private;
f9cd92eb 1379 struct comedi_subdevice *s = &dev->subdevices[NI_AI_SUBDEV];
3a2b101c 1380 unsigned short data;
03aef4b6
DS		 1381 u32 dl;
1382
6293e357 1383 if (board->reg_type != ni_reg_611x)
03aef4b6
DS		 1384 return;
1385
1386 /* Check if there's a single sample stuck in the FIFO */
1387 if (ni_readb(XXX_Status) & 0x80) {
1388 dl = ni_readl(ADC_FIFO_Data_611x);
1389 data = (dl & 0xffff);
1390 cfc_write_to_buffer(s, data);
1391 }
1392}
1393
da91b269 1394static void get_last_sample_6143(struct comedi_device *dev)
03aef4b6 1395{
6293e357 1396 const struct ni_board_struct *board = comedi_board(dev);
0e05c552 1397 struct ni_private *devpriv __maybe_unused = dev->private;
f9cd92eb 1398 struct comedi_subdevice *s = &dev->subdevices[NI_AI_SUBDEV];
3a2b101c 1399 unsigned short data;
03aef4b6
DS		 1400 u32 dl;
1401
6293e357 1402 if (board->reg_type != ni_reg_6143)
03aef4b6
DS		 1403 return;
1404
1405 /* Check if there's a single sample stuck in the FIFO */
1406 if (ni_readl(AIFIFO_Status_6143) & 0x01) {
2696fb57 1407 ni_writel(0x01, AIFIFO_Control_6143); /* Get stranded sample into FIFO */
03aef4b6
DS		 1408 dl = ni_readl(AIFIFO_Data_6143);
1409
1410 /* This may get the hi/lo data in the wrong order */
1411 data = (dl >> 16) & 0xffff;
1412 cfc_write_to_buffer(s, data);
1413 }
1414}
1415
da91b269 1416static void ni_ai_munge(struct comedi_device *dev, struct comedi_subdevice *s,
0a85b6f0
MT		 1417 void *data, unsigned int num_bytes,
1418 unsigned int chan_index)
03aef4b6 1419{
0e05c552 1420 struct ni_private *devpriv = dev->private;
d163679c 1421 struct comedi_async *async = s->async;
9663ab1f 1422 struct comedi_cmd *cmd = &async->cmd;
03aef4b6 1423 unsigned int length = num_bytes / bytes_per_sample(s);
3a2b101c 1424 unsigned short *array = data;
790c5541 1425 unsigned int *larray = data;
9663ab1f 1426 unsigned int i;
0e05c552 1427
03aef4b6
DS		 1428 for (i = 0; i < length; i++) {
1429#ifdef PCIDMA
1430 if (s->subdev_flags & SDF_LSAMPL)
1431 larray[i] = le32_to_cpu(larray[i]);
1432 else
1433 array[i] = le16_to_cpu(array[i]);
1434#endif
1435 if (s->subdev_flags & SDF_LSAMPL)
1436 larray[i] += devpriv->ai_offset[chan_index];
1437 else
1438 array[i] += devpriv->ai_offset[chan_index];
1439 chan_index++;
9663ab1f 1440 chan_index %= cmd->chanlist_len;
03aef4b6
DS		 1441 }
1442}
1443
1444#ifdef PCIDMA
1445
da91b269 1446static int ni_ai_setup_MITE_dma(struct comedi_device *dev)
03aef4b6 1447{
6293e357 1448 const struct ni_board_struct *board = comedi_board(dev);
0e05c552 1449 struct ni_private *devpriv = dev->private;
f9cd92eb 1450 struct comedi_subdevice *s = &dev->subdevices[NI_AI_SUBDEV];
03aef4b6
DS		 1451 int retval;
1452 unsigned long flags;
1453
1454 retval = ni_request_ai_mite_channel(dev);
1455 if (retval)
1456 return retval;
5f74ea14 1457/* printk("comedi_debug: using mite channel %i for ai.\n", devpriv->ai_mite_chan->channel); */
03aef4b6
DS		 1458
1459 /* write alloc the entire buffer */
24e894bb 1460 comedi_buf_write_alloc(s, s->async->prealloc_bufsz);
03aef4b6 1461
5f74ea14
GKH		 1462 spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
1463 if (devpriv->ai_mite_chan == NULL) {
1464 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
03aef4b6
DS		 1465 return -EIO;
1466 }
1467
6293e357 1468 switch (board->reg_type) {
03aef4b6
DS		 1469 case ni_reg_611x:
1470 case ni_reg_6143:
1471 mite_prep_dma(devpriv->ai_mite_chan, 32, 16);
1472 break;
1473 case ni_reg_628x:
1474 mite_prep_dma(devpriv->ai_mite_chan, 32, 32);
1475 break;
1476 default:
1477 mite_prep_dma(devpriv->ai_mite_chan, 16, 16);
1478 break;
95cd17c9 1479 }
03aef4b6
DS		 1480 /*start the MITE */
1481 mite_dma_arm(devpriv->ai_mite_chan);
5f74ea14 1482 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
03aef4b6
DS		 1483
1484 return 0;
1485}
1486
da91b269 1487static int ni_ao_setup_MITE_dma(struct comedi_device *dev)
03aef4b6 1488{
6293e357 1489 const struct ni_board_struct *board = comedi_board(dev);
0e05c552 1490 struct ni_private *devpriv = dev->private;
f9cd92eb 1491 struct comedi_subdevice *s = &dev->subdevices[NI_AO_SUBDEV];
03aef4b6
DS		 1492 int retval;
1493 unsigned long flags;
1494
1495 retval = ni_request_ao_mite_channel(dev);
1496 if (retval)
1497 return retval;
1498
1499 /* read alloc the entire buffer */
d13be55a 1500 comedi_buf_read_alloc(s, s->async->prealloc_bufsz);
03aef4b6 1501
5f74ea14 1502 spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
03aef4b6 1503 if (devpriv->ao_mite_chan) {
6293e357 1504 if (board->reg_type & (ni_reg_611x | ni_reg_6713)) {
03aef4b6
DS		 1505 mite_prep_dma(devpriv->ao_mite_chan, 32, 32);
1506 } else {
1507 /* doing 32 instead of 16 bit wide transfers from memory
1508 makes the mite do 32 bit pci transfers, doubling pci bandwidth. */
1509 mite_prep_dma(devpriv->ao_mite_chan, 16, 32);
1510 }
1511 mite_dma_arm(devpriv->ao_mite_chan);
1512 } else
1513 retval = -EIO;
5f74ea14 1514 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
03aef4b6
DS		 1515
1516 return retval;
1517}
1518
2696fb57 1519#endif /* PCIDMA */
03aef4b6
DS		 1520
1521/*
1522 used for both cancel ioctl and board initialization
1523
1524 this is pretty harsh for a cancel, but it works...
1525 */
1526
da91b269 1527static int ni_ai_reset(struct comedi_device *dev, struct comedi_subdevice *s)
03aef4b6 1528{
6293e357 1529 const struct ni_board_struct *board = comedi_board(dev);
0e05c552
HS		 1530 struct ni_private *devpriv = dev->private;
1531
03aef4b6
DS		 1532 ni_release_ai_mite_channel(dev);
1533 /* ai configuration */
1534 devpriv->stc_writew(dev, AI_Configuration_Start | AI_Reset,
0a85b6f0 1535 Joint_Reset_Register);
03aef4b6
DS		 1536
1537 ni_set_bits(dev, Interrupt_A_Enable_Register,
0a85b6f0
MT		 1538 AI_SC_TC_Interrupt_Enable | AI_START1_Interrupt_Enable |
1539 AI_START2_Interrupt_Enable | AI_START_Interrupt_Enable |
1540 AI_STOP_Interrupt_Enable | AI_Error_Interrupt_Enable |
1541 AI_FIFO_Interrupt_Enable, 0);
03aef4b6
DS		 1542
1543 ni_clear_ai_fifo(dev);
1544
6293e357 1545 if (board->reg_type != ni_reg_6143)
03aef4b6
DS		 1546 ni_writeb(0, Misc_Command);
1547
1548 devpriv->stc_writew(dev, AI_Disarm, AI_Command_1_Register); /* reset pulses */
1549 devpriv->stc_writew(dev,
0a85b6f0
MT		 1550 AI_Start_Stop | AI_Mode_1_Reserved
1551 /*| AI_Trigger_Once */ ,
1552 AI_Mode_1_Register);
03aef4b6
DS		 1553 devpriv->stc_writew(dev, 0x0000, AI_Mode_2_Register);
1554 /* generate FIFO interrupts on non-empty */
1555 devpriv->stc_writew(dev, (0 << 6) | 0x0000, AI_Mode_3_Register);
6293e357 1556 if (board->reg_type == ni_reg_611x) {
03aef4b6 1557 devpriv->stc_writew(dev, AI_SHIFTIN_Pulse_Width |
0a85b6f0
MT		 1558 AI_SOC_Polarity |
1559 AI_LOCALMUX_CLK_Pulse_Width,
1560 AI_Personal_Register);
1561 devpriv->stc_writew(dev,
1562 AI_SCAN_IN_PROG_Output_Select(3) |
1563 AI_EXTMUX_CLK_Output_Select(0) |
1564 AI_LOCALMUX_CLK_Output_Select(2) |
1565 AI_SC_TC_Output_Select(3) |
1566 AI_CONVERT_Output_Select
1567 (AI_CONVERT_Output_Enable_High),
1568 AI_Output_Control_Register);
6293e357 1569 } else if (board->reg_type == ni_reg_6143) {
03aef4b6 1570 devpriv->stc_writew(dev, AI_SHIFTIN_Pulse_Width |
0a85b6f0
MT		 1571 AI_SOC_Polarity |
1572 AI_LOCALMUX_CLK_Pulse_Width,
1573 AI_Personal_Register);
1574 devpriv->stc_writew(dev,
1575 AI_SCAN_IN_PROG_Output_Select(3) |
1576 AI_EXTMUX_CLK_Output_Select(0) |
1577 AI_LOCALMUX_CLK_Output_Select(2) |
1578 AI_SC_TC_Output_Select(3) |
1579 AI_CONVERT_Output_Select
1580 (AI_CONVERT_Output_Enable_Low),
1581 AI_Output_Control_Register);
03aef4b6
DS		 1582 } else {
1583 unsigned ai_output_control_bits;
1584 devpriv->stc_writew(dev, AI_SHIFTIN_Pulse_Width |
0a85b6f0
MT		 1585 AI_SOC_Polarity |
1586 AI_CONVERT_Pulse_Width |
1587 AI_LOCALMUX_CLK_Pulse_Width,
1588 AI_Personal_Register);
1589 ai_output_control_bits =
1590 AI_SCAN_IN_PROG_Output_Select(3) |
1591 AI_EXTMUX_CLK_Output_Select(0) |
1592 AI_LOCALMUX_CLK_Output_Select(2) |
1593 AI_SC_TC_Output_Select(3);
6293e357 1594 if (board->reg_type == ni_reg_622x)
03aef4b6 1595 ai_output_control_bits |=
0a85b6f0
MT		 1596 AI_CONVERT_Output_Select
1597 (AI_CONVERT_Output_Enable_High);
03aef4b6
DS		 1598 else
1599 ai_output_control_bits |=
0a85b6f0
MT		 1600 AI_CONVERT_Output_Select
1601 (AI_CONVERT_Output_Enable_Low);
03aef4b6 1602 devpriv->stc_writew(dev, ai_output_control_bits,
0a85b6f0 1603 AI_Output_Control_Register);
03aef4b6
DS		 1604 }
1605 /* the following registers should not be changed, because there
1606 * are no backup registers in devpriv. If you want to change
1607 * any of these, add a backup register and other appropriate code:
1608 * AI_Mode_1_Register
1609 * AI_Mode_3_Register
1610 * AI_Personal_Register
1611 * AI_Output_Control_Register
1612 */
1613 devpriv->stc_writew(dev, AI_SC_TC_Error_Confirm | AI_START_Interrupt_Ack | AI_START2_Interrupt_Ack | AI_START1_Interrupt_Ack | AI_SC_TC_Interrupt_Ack | AI_Error_Interrupt_Ack | AI_STOP_Interrupt_Ack, Interrupt_A_Ack_Register); /* clear interrupts */
1614
1615 devpriv->stc_writew(dev, AI_Configuration_End, Joint_Reset_Register);
1616
1617 return 0;
1618}
1619
da91b269 1620static int ni_ai_poll(struct comedi_device *dev, struct comedi_subdevice *s)
03aef4b6 1621{
3cd73bc1 1622 unsigned long flags;
03aef4b6
DS		 1623 int count;
1624
2696fb57 1625 /* lock to avoid race with interrupt handler */
3cd73bc1 1626 spin_lock_irqsave(&dev->spinlock, flags);
03aef4b6
DS		 1627#ifndef PCIDMA
1628 ni_handle_fifo_dregs(dev);
1629#else
1630 ni_sync_ai_dma(dev);
1631#endif
1632 count = s->async->buf_write_count - s->async->buf_read_count;
3cd73bc1 1633 spin_unlock_irqrestore(&dev->spinlock, flags);
03aef4b6
DS		 1634
1635 return count;
1636}
1637
0a85b6f0
MT		 1638static int ni_ai_insn_read(struct comedi_device *dev,
1639 struct comedi_subdevice *s, struct comedi_insn *insn,
1640 unsigned int *data)
03aef4b6 1641{
6293e357 1642 const struct ni_board_struct *board = comedi_board(dev);
0e05c552 1643 struct ni_private *devpriv = dev->private;
03aef4b6 1644 int i, n;
6293e357 1645 const unsigned int mask = (1 << board->adbits) - 1;
03aef4b6
DS		 1646 unsigned signbits;
1647 unsigned short d;
1648 unsigned long dl;
1649
1650 ni_load_channelgain_list(dev, 1, &insn->chanspec);
1651
1652 ni_clear_ai_fifo(dev);
1653
1654 signbits = devpriv->ai_offset[0];
6293e357 1655 if (board->reg_type == ni_reg_611x) {
03aef4b6
DS		 1656 for (n = 0; n < num_adc_stages_611x; n++) {
1657 devpriv->stc_writew(dev, AI_CONVERT_Pulse,
0a85b6f0 1658 AI_Command_1_Register);
5f74ea14 1659 udelay(1);
03aef4b6
DS		 1660 }
1661 for (n = 0; n < insn->n; n++) {
1662 devpriv->stc_writew(dev, AI_CONVERT_Pulse,
0a85b6f0 1663 AI_Command_1_Register);
03aef4b6
DS		 1664 /* The 611x has screwy 32-bit FIFOs. */
1665 d = 0;
1666 for (i = 0; i < NI_TIMEOUT; i++) {
1667 if (ni_readb(XXX_Status) & 0x80) {
1668 d = (ni_readl(ADC_FIFO_Data_611x) >> 16)
0a85b6f0 1669 & 0xffff;
03aef4b6
DS		 1670 break;
1671 }
1672 if (!(devpriv->stc_readw(dev,
0a85b6f0
MT		 1673 AI_Status_1_Register) &
1674 AI_FIFO_Empty_St)) {
03aef4b6 1675 d = ni_readl(ADC_FIFO_Data_611x) &
0a85b6f0 1676 0xffff;
03aef4b6
DS		 1677 break;
1678 }
1679 }
1680 if (i == NI_TIMEOUT) {
5f74ea14 1681 printk
0a85b6f0 1682 ("ni_mio_common: timeout in 611x ni_ai_insn_read\n");
03aef4b6
DS		 1683 return -ETIME;
1684 }
1685 d += signbits;
1686 data[n] = d;
1687 }
6293e357 1688 } else if (board->reg_type == ni_reg_6143) {
03aef4b6
DS		 1689 for (n = 0; n < insn->n; n++) {
1690 devpriv->stc_writew(dev, AI_CONVERT_Pulse,
0a85b6f0 1691 AI_Command_1_Register);
03aef4b6
DS		 1692
1693 /* The 6143 has 32-bit FIFOs. You need to strobe a bit to move a single 16bit stranded sample into the FIFO */
1694 dl = 0;
1695 for (i = 0; i < NI_TIMEOUT; i++) {
1696 if (ni_readl(AIFIFO_Status_6143) & 0x01) {
2696fb57 1697 ni_writel(0x01, AIFIFO_Control_6143); /* Get stranded sample into FIFO */
03aef4b6
DS		 1698 dl = ni_readl(AIFIFO_Data_6143);
1699 break;
1700 }
1701 }
1702 if (i == NI_TIMEOUT) {
5f74ea14 1703 printk
0a85b6f0 1704 ("ni_mio_common: timeout in 6143 ni_ai_insn_read\n");
03aef4b6
DS		 1705 return -ETIME;
1706 }
1707 data[n] = (((dl >> 16) & 0xFFFF) + signbits) & 0xFFFF;
1708 }
1709 } else {
1710 for (n = 0; n < insn->n; n++) {
1711 devpriv->stc_writew(dev, AI_CONVERT_Pulse,
0a85b6f0 1712 AI_Command_1_Register);
03aef4b6
DS		 1713 for (i = 0; i < NI_TIMEOUT; i++) {
1714 if (!(devpriv->stc_readw(dev,
0a85b6f0
MT		 1715 AI_Status_1_Register) &
1716 AI_FIFO_Empty_St))
03aef4b6
DS		 1717 break;
1718 }
1719 if (i == NI_TIMEOUT) {
5f74ea14 1720 printk
0a85b6f0 1721 ("ni_mio_common: timeout in ni_ai_insn_read\n");
03aef4b6
DS		 1722 return -ETIME;
1723 }
6293e357 1724 if (board->reg_type & ni_reg_m_series_mask) {
03aef4b6 1725 data[n] =
0a85b6f0 1726 ni_readl(M_Offset_AI_FIFO_Data) & mask;
03aef4b6
DS		 1727 } else {
1728 d = ni_readw(ADC_FIFO_Data_Register);
1729 d += signbits; /* subtle: needs to be short addition */
1730 data[n] = d;
1731 }
1732 }
1733 }
1734 return insn->n;
1735}
1736
29aba763 1737static void ni_prime_channelgain_list(struct comedi_device *dev)
03aef4b6 1738{
0e05c552 1739 struct ni_private *devpriv = dev->private;
03aef4b6 1740 int i;
0e05c552 1741
03aef4b6
DS		 1742 devpriv->stc_writew(dev, AI_CONVERT_Pulse, AI_Command_1_Register);
1743 for (i = 0; i < NI_TIMEOUT; ++i) {
1744 if (!(devpriv->stc_readw(dev,
0a85b6f0
MT		 1745 AI_Status_1_Register) &
1746 AI_FIFO_Empty_St)) {
03aef4b6
DS		 1747 devpriv->stc_writew(dev, 1, ADC_FIFO_Clear);
1748 return;
1749 }
5f74ea14 1750 udelay(1);
03aef4b6 1751 }
5f74ea14 1752 printk("ni_mio_common: timeout loading channel/gain list\n");
03aef4b6
DS		 1753}
1754
da91b269 1755static void ni_m_series_load_channelgain_list(struct comedi_device *dev,
0a85b6f0
MT		 1756 unsigned int n_chan,
1757 unsigned int *list)
03aef4b6 1758{
6293e357 1759 const struct ni_board_struct *board = comedi_board(dev);
0e05c552 1760 struct ni_private *devpriv = dev->private;
03aef4b6
DS		 1761 unsigned int chan, range, aref;
1762 unsigned int i;
1763 unsigned offset;
1764 unsigned int dither;
1765 unsigned range_code;
1766
1767 devpriv->stc_writew(dev, 1, Configuration_Memory_Clear);
1768
6293e357 1769/* offset = 1 << (board->adbits - 1); */
03aef4b6
DS		 1770 if ((list[0] & CR_ALT_SOURCE)) {
1771 unsigned bypass_bits;
1772 chan = CR_CHAN(list[0]);
1773 range = CR_RANGE(list[0]);
6293e357 1774 range_code = ni_gainlkup[board->gainlkup][range];
03aef4b6
DS		 1775 dither = ((list[0] & CR_ALT_FILTER) != 0);
1776 bypass_bits = MSeries_AI_Bypass_Config_FIFO_Bit;
1777 bypass_bits |= chan;
1778 bypass_bits |=
0a85b6f0
MT		 1779 (devpriv->ai_calib_source) &
1780 (MSeries_AI_Bypass_Cal_Sel_Pos_Mask |
1781 MSeries_AI_Bypass_Cal_Sel_Neg_Mask |
1782 MSeries_AI_Bypass_Mode_Mux_Mask |
1783 MSeries_AO_Bypass_AO_Cal_Sel_Mask);
03aef4b6
DS		 1784 bypass_bits |= MSeries_AI_Bypass_Gain_Bits(range_code);
1785 if (dither)
1786 bypass_bits |= MSeries_AI_Bypass_Dither_Bit;
2696fb57 1787 /* don't use 2's complement encoding */
03aef4b6
DS		 1788 bypass_bits |= MSeries_AI_Bypass_Polarity_Bit;
1789 ni_writel(bypass_bits, M_Offset_AI_Config_FIFO_Bypass);
1790 } else {
1791 ni_writel(0, M_Offset_AI_Config_FIFO_Bypass);
1792 }
1793 offset = 0;
1794 for (i = 0; i < n_chan; i++) {
1795 unsigned config_bits = 0;
1796 chan = CR_CHAN(list[i]);
1797 aref = CR_AREF(list[i]);
1798 range = CR_RANGE(list[i]);
1799 dither = ((list[i] & CR_ALT_FILTER) != 0);
1800
6293e357 1801 range_code = ni_gainlkup[board->gainlkup][range];
03aef4b6
DS		 1802 devpriv->ai_offset[i] = offset;
1803 switch (aref) {
1804 case AREF_DIFF:
1805 config_bits |=
0a85b6f0 1806 MSeries_AI_Config_Channel_Type_Differential_Bits;
03aef4b6
DS		 1807 break;
1808 case AREF_COMMON:
1809 config_bits |=
0a85b6f0 1810 MSeries_AI_Config_Channel_Type_Common_Ref_Bits;
03aef4b6
DS		 1811 break;
1812 case AREF_GROUND:
1813 config_bits |=
0a85b6f0 1814 MSeries_AI_Config_Channel_Type_Ground_Ref_Bits;
03aef4b6
DS		 1815 break;
1816 case AREF_OTHER:
1817 break;
1818 }
1819 config_bits |= MSeries_AI_Config_Channel_Bits(chan);
1820 config_bits |=
6293e357 1821 MSeries_AI_Config_Bank_Bits(board->reg_type, chan);
03aef4b6
DS		 1822 config_bits |= MSeries_AI_Config_Gain_Bits(range_code);
1823 if (i == n_chan - 1)
1824 config_bits |= MSeries_AI_Config_Last_Channel_Bit;
1825 if (dither)
1826 config_bits |= MSeries_AI_Config_Dither_Bit;
2696fb57 1827 /* don't use 2's complement encoding */
03aef4b6
DS		 1828 config_bits |= MSeries_AI_Config_Polarity_Bit;
1829 ni_writew(config_bits, M_Offset_AI_Config_FIFO_Data);
1830 }
1831 ni_prime_channelgain_list(dev);
1832}
1833
1834/*
1835 * Notes on the 6110 and 6111:
1836 * These boards a slightly different than the rest of the series, since
1837 * they have multiple A/D converters.
1838 * From the driver side, the configuration memory is a
1839 * little different.
1840 * Configuration Memory Low:
1841 * bits 15-9: same
1842 * bit 8: unipolar/bipolar (should be 0 for bipolar)
1843 * bits 0-3: gain. This is 4 bits instead of 3 for the other boards
1844 * 1001 gain=0.1 (+/- 50)
1845 * 1010 0.2
1846 * 1011 0.1
1847 * 0001 1
1848 * 0010 2
1849 * 0011 5
1850 * 0100 10
1851 * 0101 20
1852 * 0110 50
1853 * Configuration Memory High:
1854 * bits 12-14: Channel Type
1855 * 001 for differential
1856 * 000 for calibration
1857 * bit 11: coupling (this is not currently handled)
1858 * 1 AC coupling
1859 * 0 DC coupling
1860 * bits 0-2: channel
1861 * valid channels are 0-3
1862 */
0a85b6f0
MT		 1863static void ni_load_channelgain_list(struct comedi_device *dev,
1864 unsigned int n_chan, unsigned int *list)
03aef4b6 1865{
6293e357 1866 const struct ni_board_struct *board = comedi_board(dev);
0e05c552 1867 struct ni_private *devpriv = dev->private;
03aef4b6
DS		 1868 unsigned int chan, range, aref;
1869 unsigned int i;
1870 unsigned int hi, lo;
1871 unsigned offset;
1872 unsigned int dither;
1873
6293e357 1874 if (board->reg_type & ni_reg_m_series_mask) {
03aef4b6
DS		 1875 ni_m_series_load_channelgain_list(dev, n_chan, list);
1876 return;
1877 }
6293e357
HS		 1878 if (n_chan == 1 && (board->reg_type != ni_reg_611x)
1879 && (board->reg_type != ni_reg_6143)) {
03aef4b6 1880 if (devpriv->changain_state
0a85b6f0 1881 && devpriv->changain_spec == list[0]) {
2696fb57 1882 /* ready to go. */
03aef4b6
DS		 1883 return;
1884 }
1885 devpriv->changain_state = 1;
1886 devpriv->changain_spec = list[0];
1887 } else {
1888 devpriv->changain_state = 0;
1889 }
1890
1891 devpriv->stc_writew(dev, 1, Configuration_Memory_Clear);
1892
2696fb57 1893 /* Set up Calibration mode if required */
6293e357 1894 if (board->reg_type == ni_reg_6143) {
03aef4b6 1895 if ((list[0] & CR_ALT_SOURCE)
0a85b6f0 1896 && !devpriv->ai_calib_source_enabled) {
2696fb57 1897 /* Strobe Relay enable bit */
0a85b6f0
MT		 1898 ni_writew(devpriv->ai_calib_source |
1899 Calibration_Channel_6143_RelayOn,
1900 Calibration_Channel_6143);
03aef4b6 1901 ni_writew(devpriv->ai_calib_source,
0a85b6f0 1902 Calibration_Channel_6143);
03aef4b6 1903 devpriv->ai_calib_source_enabled = 1;
2696fb57 1904 msleep_interruptible(100); /* Allow relays to change */
03aef4b6 1905 } else if (!(list[0] & CR_ALT_SOURCE)
0a85b6f0 1906 && devpriv->ai_calib_source_enabled) {
2696fb57 1907 /* Strobe Relay disable bit */
0a85b6f0
MT		 1908 ni_writew(devpriv->ai_calib_source |
1909 Calibration_Channel_6143_RelayOff,
1910 Calibration_Channel_6143);
03aef4b6 1911 ni_writew(devpriv->ai_calib_source,
0a85b6f0 1912 Calibration_Channel_6143);
03aef4b6 1913 devpriv->ai_calib_source_enabled = 0;
2696fb57 1914 msleep_interruptible(100); /* Allow relays to change */
03aef4b6
DS		 1915 }
1916 }
1917
6293e357 1918 offset = 1 << (board->adbits - 1);
03aef4b6 1919 for (i = 0; i < n_chan; i++) {
6293e357 1920 if ((board->reg_type != ni_reg_6143)
0a85b6f0 1921 && (list[i] & CR_ALT_SOURCE)) {
03aef4b6
DS		 1922 chan = devpriv->ai_calib_source;
1923 } else {
1924 chan = CR_CHAN(list[i]);
1925 }
1926 aref = CR_AREF(list[i]);
1927 range = CR_RANGE(list[i]);
1928 dither = ((list[i] & CR_ALT_FILTER) != 0);
1929
1930 /* fix the external/internal range differences */
6293e357
HS		 1931 range = ni_gainlkup[board->gainlkup][range];
1932 if (board->reg_type == ni_reg_611x)
03aef4b6
DS		 1933 devpriv->ai_offset[i] = offset;
1934 else
1935 devpriv->ai_offset[i] = (range & 0x100) ? 0 : offset;
1936
1937 hi = 0;
1938 if ((list[i] & CR_ALT_SOURCE)) {
6293e357 1939 if (board->reg_type == ni_reg_611x)
03aef4b6 1940 ni_writew(CR_CHAN(list[i]) & 0x0003,
0a85b6f0 1941 Calibration_Channel_Select_611x);
03aef4b6 1942 } else {
6293e357 1943 if (board->reg_type == ni_reg_611x)
03aef4b6 1944 aref = AREF_DIFF;
6293e357 1945 else if (board->reg_type == ni_reg_6143)
03aef4b6
DS		 1946 aref = AREF_OTHER;
1947 switch (aref) {
1948 case AREF_DIFF:
1949 hi |= AI_DIFFERENTIAL;
1950 break;
1951 case AREF_COMMON:
1952 hi |= AI_COMMON;
1953 break;
1954 case AREF_GROUND:
1955 hi |= AI_GROUND;
1956 break;
1957 case AREF_OTHER:
1958 break;
1959 }
1960 }
1961 hi |= AI_CONFIG_CHANNEL(chan);
1962
1963 ni_writew(hi, Configuration_Memory_High);
1964
6293e357 1965 if (board->reg_type != ni_reg_6143) {
03aef4b6
DS		 1966 lo = range;
1967 if (i == n_chan - 1)
1968 lo |= AI_LAST_CHANNEL;
1969 if (dither)
1970 lo |= AI_DITHER;
1971
1972 ni_writew(lo, Configuration_Memory_Low);
1973 }
1974 }
1975
1976 /* prime the channel/gain list */
6293e357
HS		 1977 if ((board->reg_type != ni_reg_611x)
1978 && (board->reg_type != ni_reg_6143)) {
03aef4b6
DS		 1979 ni_prime_channelgain_list(dev);
1980 }
1981}
1982
da91b269 1983static int ni_ns_to_timer(const struct comedi_device *dev, unsigned nanosec,
0a85b6f0 1984 int round_mode)
03aef4b6 1985{
0e05c552 1986 struct ni_private *devpriv = dev->private;
03aef4b6 1987 int divider;
0e05c552 1988
03aef4b6
DS		 1989 switch (round_mode) {
1990 case TRIG_ROUND_NEAREST:
1991 default:
1992 divider = (nanosec + devpriv->clock_ns / 2) / devpriv->clock_ns;
1993 break;
1994 case TRIG_ROUND_DOWN:
1995 divider = (nanosec) / devpriv->clock_ns;
1996 break;
1997 case TRIG_ROUND_UP:
1998 divider = (nanosec + devpriv->clock_ns - 1) / devpriv->clock_ns;
1999 break;
2000 }
2001 return divider - 1;
2002}
2003
da91b269 2004static unsigned ni_timer_to_ns(const struct comedi_device *dev, int timer)
03aef4b6 2005{
0e05c552
HS		 2006 struct ni_private *devpriv = dev->private;
2007
03aef4b6
DS		 2008 return devpriv->clock_ns * (timer + 1);
2009}
2010
da91b269 2011static unsigned ni_min_ai_scan_period_ns(struct comedi_device *dev,
0a85b6f0 2012 unsigned num_channels)
03aef4b6 2013{
6293e357
HS		 2014 const struct ni_board_struct *board = comedi_board(dev);
2015
2016 switch (board->reg_type) {
03aef4b6
DS		 2017 case ni_reg_611x:
2018 case ni_reg_6143:
2696fb57 2019 /* simultaneously-sampled inputs */
6293e357 2020 return board->ai_speed;
03aef4b6
DS		 2021 break;
2022 default:
2696fb57 2023 /* multiplexed inputs */
03aef4b6 2024 break;
95cd17c9 2025 }
6293e357 2026 return board->ai_speed * num_channels;
03aef4b6
DS		 2027}
2028
da91b269 2029static int ni_ai_cmdtest(struct comedi_device *dev, struct comedi_subdevice *s,
0a85b6f0 2030 struct comedi_cmd *cmd)
03aef4b6 2031{
6293e357 2032 const struct ni_board_struct *board = comedi_board(dev);
0e05c552 2033 struct ni_private *devpriv = dev->private;
03aef4b6 2034 int err = 0;
ebb657ba 2035 unsigned int tmp;
27020ffe 2036 unsigned int sources;
03aef4b6 2037
27020ffe 2038 /* Step 1 : check if triggers are trivially valid */
03aef4b6 2039
27020ffe 2040 if ((cmd->flags & CMDF_WRITE))
03aef4b6 2041 cmd->flags &= ~CMDF_WRITE;
03aef4b6 2042
27020ffe
HS		 2043 err |= cfc_check_trigger_src(&cmd->start_src,
2044 TRIG_NOW | TRIG_INT | TRIG_EXT);
2045 err |= cfc_check_trigger_src(&cmd->scan_begin_src,
2046 TRIG_TIMER | TRIG_EXT);
03aef4b6 2047
03aef4b6 2048 sources = TRIG_TIMER | TRIG_EXT;
6293e357
HS		 2049 if (board->reg_type == ni_reg_611x ||
2050 board->reg_type == ni_reg_6143)
03aef4b6 2051 sources |= TRIG_NOW;
27020ffe 2052 err |= cfc_check_trigger_src(&cmd->convert_src, sources);
03aef4b6 2053
27020ffe
HS		 2054 err |= cfc_check_trigger_src(&cmd->scan_end_src, TRIG_COUNT);
2055 err |= cfc_check_trigger_src(&cmd->stop_src, TRIG_COUNT | TRIG_NONE);
03aef4b6
DS		 2056
2057 if (err)
2058 return 1;
2059
27020ffe 2060 /* Step 2a : make sure trigger sources are unique */
03aef4b6 2061
27020ffe
HS		 2062 err |= cfc_check_trigger_is_unique(cmd->start_src);
2063 err |= cfc_check_trigger_is_unique(cmd->scan_begin_src);
2064 err |= cfc_check_trigger_is_unique(cmd->convert_src);
2065 err |= cfc_check_trigger_is_unique(cmd->stop_src);
2066
2067 /* Step 2b : and mutually compatible */
03aef4b6
DS		 2068
2069 if (err)
2070 return 2;
2071
c3be5c7f 2072 /* Step 3: check if arguments are trivially valid */
03aef4b6 2073
ebb657ba
HS		 2074 switch (cmd->start_src) {
2075 case TRIG_NOW:
2076 case TRIG_INT:
2077 err |= cfc_check_trigger_arg_is(&cmd->start_arg, 0);
2078 break;
2079 case TRIG_EXT:
2080 tmp = CR_CHAN(cmd->start_arg);
03aef4b6
DS		 2081
2082 if (tmp > 16)
2083 tmp = 16;
2084 tmp |= (cmd->start_arg & (CR_INVERT | CR_EDGE));
c3be5c7f 2085 err |= cfc_check_trigger_arg_is(&cmd->start_arg, tmp);
ebb657ba 2086 break;
03aef4b6 2087 }
c3be5c7f 2088
03aef4b6 2089 if (cmd->scan_begin_src == TRIG_TIMER) {
c3be5c7f
HS		 2090 err |= cfc_check_trigger_arg_min(&cmd->scan_begin_arg,
2091 ni_min_ai_scan_period_ns(dev, cmd->chanlist_len));
2092 err |= cfc_check_trigger_arg_max(&cmd->scan_begin_arg,
2093 devpriv->clock_ns * 0xffffff);
03aef4b6
DS		 2094 } else if (cmd->scan_begin_src == TRIG_EXT) {
2095 /* external trigger */
2096 unsigned int tmp = CR_CHAN(cmd->scan_begin_arg);
2097
2098 if (tmp > 16)
2099 tmp = 16;
2100 tmp |= (cmd->scan_begin_arg & (CR_INVERT | CR_EDGE));
c3be5c7f 2101 err |= cfc_check_trigger_arg_is(&cmd->scan_begin_arg, tmp);
03aef4b6 2102 } else { /* TRIG_OTHER */
c3be5c7f 2103 err |= cfc_check_trigger_arg_is(&cmd->scan_begin_arg, 0);
03aef4b6 2104 }
c3be5c7f 2105
03aef4b6 2106 if (cmd->convert_src == TRIG_TIMER) {
6293e357
HS		 2107 if ((board->reg_type == ni_reg_611x)
2108 || (board->reg_type == ni_reg_6143)) {
c3be5c7f 2109 err |= cfc_check_trigger_arg_is(&cmd->convert_arg, 0);
03aef4b6 2110 } else {
c3be5c7f 2111 err |= cfc_check_trigger_arg_min(&cmd->convert_arg,
6293e357 2112 board->ai_speed);
c3be5c7f
HS		 2113 err |= cfc_check_trigger_arg_max(&cmd->convert_arg,
2114 devpriv->clock_ns * 0xffff);
03aef4b6
DS		 2115 }
2116 } else if (cmd->convert_src == TRIG_EXT) {
2117 /* external trigger */
2118 unsigned int tmp = CR_CHAN(cmd->convert_arg);
2119
2120 if (tmp > 16)
2121 tmp = 16;
2122 tmp |= (cmd->convert_arg & (CR_ALT_FILTER | CR_INVERT));
c3be5c7f 2123 err |= cfc_check_trigger_arg_is(&cmd->convert_arg, tmp);
03aef4b6 2124 } else if (cmd->convert_src == TRIG_NOW) {
c3be5c7f 2125 err |= cfc_check_trigger_arg_is(&cmd->convert_arg, 0);
03aef4b6
DS		 2126 }
2127
c3be5c7f
HS		 2128 err |= cfc_check_trigger_arg_is(&cmd->scan_end_arg, cmd->chanlist_len);
2129
03aef4b6
DS		 2130 if (cmd->stop_src == TRIG_COUNT) {
2131 unsigned int max_count = 0x01000000;
2132
6293e357 2133 if (board->reg_type == ni_reg_611x)
03aef4b6 2134 max_count -= num_adc_stages_611x;
c3be5c7f
HS		 2135 err |= cfc_check_trigger_arg_max(&cmd->stop_arg, max_count);
2136 err |= cfc_check_trigger_arg_min(&cmd->stop_arg, 1);
03aef4b6
DS		 2137 } else {
2138 /* TRIG_NONE */
c3be5c7f 2139 err |= cfc_check_trigger_arg_is(&cmd->stop_arg, 0);
03aef4b6
DS		 2140 }
2141
2142 if (err)
2143 return 3;
2144
2145 /* step 4: fix up any arguments */
2146
2147 if (cmd->scan_begin_src == TRIG_TIMER) {
2148 tmp = cmd->scan_begin_arg;
2149 cmd->scan_begin_arg =
0a85b6f0
MT		 2150 ni_timer_to_ns(dev, ni_ns_to_timer(dev,
2151 cmd->scan_begin_arg,
2152 cmd->
2153 flags &
2154 TRIG_ROUND_MASK));
03aef4b6
DS		 2155 if (tmp != cmd->scan_begin_arg)
2156 err++;
2157 }
2158 if (cmd->convert_src == TRIG_TIMER) {
6293e357
HS		 2159 if ((board->reg_type != ni_reg_611x)
2160 && (board->reg_type != ni_reg_6143)) {
03aef4b6
DS		 2161 tmp = cmd->convert_arg;
2162 cmd->convert_arg =
0a85b6f0
MT		 2163 ni_timer_to_ns(dev, ni_ns_to_timer(dev,
2164 cmd->convert_arg,
2165 cmd->
2166 flags &
2167 TRIG_ROUND_MASK));
03aef4b6
DS		 2168 if (tmp != cmd->convert_arg)
2169 err++;
2170 if (cmd->scan_begin_src == TRIG_TIMER &&
0a85b6f0
MT		 2171 cmd->scan_begin_arg <
2172 cmd->convert_arg * cmd->scan_end_arg) {
03aef4b6 2173 cmd->scan_begin_arg =
0a85b6f0 2174 cmd->convert_arg * cmd->scan_end_arg;
03aef4b6
DS		 2175 err++;
2176 }
2177 }
2178 }
2179
2180 if (err)
2181 return 4;
2182
2183 return 0;
2184}
2185
da91b269 2186static int ni_ai_cmd(struct comedi_device *dev, struct comedi_subdevice *s)
03aef4b6 2187{
6293e357 2188 const struct ni_board_struct *board = comedi_board(dev);
0e05c552 2189 struct ni_private *devpriv = dev->private;
ea6d0d4c 2190 const struct comedi_cmd *cmd = &s->async->cmd;
03aef4b6
DS		 2191 int timer;
2192 int mode1 = 0; /* mode1 is needed for both stop and convert */
2193 int mode2 = 0;
2194 int start_stop_select = 0;
2195 unsigned int stop_count;
2196 int interrupt_a_enable = 0;
2197
03aef4b6
DS		 2198 if (dev->irq == 0) {
2199 comedi_error(dev, "cannot run command without an irq");
2200 return -EIO;
2201 }
2202 ni_clear_ai_fifo(dev);
2203
2204 ni_load_channelgain_list(dev, cmd->chanlist_len, cmd->chanlist);
2205
2206 /* start configuration */
2207 devpriv->stc_writew(dev, AI_Configuration_Start, Joint_Reset_Register);
2208
2209 /* disable analog triggering for now, since it
2210 * interferes with the use of pfi0 */
2211 devpriv->an_trig_etc_reg &= ~Analog_Trigger_Enable;
2212 devpriv->stc_writew(dev, devpriv->an_trig_etc_reg,
0a85b6f0 2213 Analog_Trigger_Etc_Register);
03aef4b6
DS		 2214
2215 switch (cmd->start_src) {
2216 case TRIG_INT:
2217 case TRIG_NOW:
2218 devpriv->stc_writew(dev, AI_START2_Select(0) |
0a85b6f0
MT		 2219 AI_START1_Sync | AI_START1_Edge |
2220 AI_START1_Select(0),
2221 AI_Trigger_Select_Register);
03aef4b6
DS		 2222 break;
2223 case TRIG_EXT:
2224 {
2225 int chan = CR_CHAN(cmd->start_arg);
2226 unsigned int bits = AI_START2_Select(0) |
0a85b6f0 2227 AI_START1_Sync | AI_START1_Select(chan + 1);
03aef4b6
DS		 2228
2229 if (cmd->start_arg & CR_INVERT)
2230 bits |= AI_START1_Polarity;
2231 if (cmd->start_arg & CR_EDGE)
2232 bits |= AI_START1_Edge;
2233 devpriv->stc_writew(dev, bits,
0a85b6f0 2234 AI_Trigger_Select_Register);
03aef4b6
DS		 2235 break;
2236 }
2237 }
2238
2239 mode2 &= ~AI_Pre_Trigger;
2240 mode2 &= ~AI_SC_Initial_Load_Source;
2241 mode2 &= ~AI_SC_Reload_Mode;
2242 devpriv->stc_writew(dev, mode2, AI_Mode_2_Register);
2243
6293e357
HS		 2244 if (cmd->chanlist_len == 1 || (board->reg_type == ni_reg_611x)
2245 || (board->reg_type == ni_reg_6143)) {
03aef4b6 2246 start_stop_select |= AI_STOP_Polarity;
2696fb57 2247 start_stop_select |= AI_STOP_Select(31); /* logic low */
03aef4b6
DS		 2248 start_stop_select |= AI_STOP_Sync;
2249 } else {
2696fb57 2250 start_stop_select |= AI_STOP_Select(19); /* ai configuration memory */
03aef4b6
DS		 2251 }
2252 devpriv->stc_writew(dev, start_stop_select,
0a85b6f0 2253 AI_START_STOP_Select_Register);
03aef4b6
DS		 2254
2255 devpriv->ai_cmd2 = 0;
2256 switch (cmd->stop_src) {
2257 case TRIG_COUNT:
2258 stop_count = cmd->stop_arg - 1;
2259
6293e357 2260 if (board->reg_type == ni_reg_611x) {
2696fb57 2261 /* have to take 3 stage adc pipeline into account */
03aef4b6
DS		 2262 stop_count += num_adc_stages_611x;
2263 }
2264 /* stage number of scans */
2265 devpriv->stc_writel(dev, stop_count, AI_SC_Load_A_Registers);
2266
2267 mode1 |= AI_Start_Stop | AI_Mode_1_Reserved | AI_Trigger_Once;
2268 devpriv->stc_writew(dev, mode1, AI_Mode_1_Register);
2269 /* load SC (Scan Count) */
2270 devpriv->stc_writew(dev, AI_SC_Load, AI_Command_1_Register);
2271
2272 devpriv->ai_continuous = 0;
2273 if (stop_count == 0) {
2274 devpriv->ai_cmd2 |= AI_End_On_End_Of_Scan;
2275 interrupt_a_enable |= AI_STOP_Interrupt_Enable;
2696fb57 2276 /* this is required to get the last sample for chanlist_len > 1, not sure why */
03aef4b6
DS		 2277 if (cmd->chanlist_len > 1)
2278 start_stop_select |=
0a85b6f0 2279 AI_STOP_Polarity | AI_STOP_Edge;
03aef4b6
DS		 2280 }
2281 break;
2282 case TRIG_NONE:
2283 /* stage number of scans */
2284 devpriv->stc_writel(dev, 0, AI_SC_Load_A_Registers);
2285
2286 mode1 |= AI_Start_Stop | AI_Mode_1_Reserved | AI_Continuous;
2287 devpriv->stc_writew(dev, mode1, AI_Mode_1_Register);
2288
2289 /* load SC (Scan Count) */
2290 devpriv->stc_writew(dev, AI_SC_Load, AI_Command_1_Register);
2291
2292 devpriv->ai_continuous = 1;
2293
2294 break;
2295 }
2296
2297 switch (cmd->scan_begin_src) {
2298 case TRIG_TIMER:
2299 /*
2300 stop bits for non 611x boards
2301 AI_SI_Special_Trigger_Delay=0
2302 AI_Pre_Trigger=0
2303 AI_START_STOP_Select_Register:
2304 AI_START_Polarity=0 (?) rising edge
2305 AI_START_Edge=1 edge triggered
2306 AI_START_Sync=1 (?)
2307 AI_START_Select=0 SI_TC
2308 AI_STOP_Polarity=0 rising edge
2309 AI_STOP_Edge=0 level
2310 AI_STOP_Sync=1
2311 AI_STOP_Select=19 external pin (configuration mem)
2312 */
2313 start_stop_select |= AI_START_Edge | AI_START_Sync;
2314 devpriv->stc_writew(dev, start_stop_select,
0a85b6f0 2315 AI_START_STOP_Select_Register);
03aef4b6
DS		 2316
2317 mode2 |= AI_SI_Reload_Mode(0);
2318 /* AI_SI_Initial_Load_Source=A */
2319 mode2 &= ~AI_SI_Initial_Load_Source;
2696fb57 2320 /* mode2 |= AI_SC_Reload_Mode; */
03aef4b6
DS		 2321 devpriv->stc_writew(dev, mode2, AI_Mode_2_Register);
2322
2323 /* load SI */
2324 timer = ni_ns_to_timer(dev, cmd->scan_begin_arg,
0a85b6f0 2325 TRIG_ROUND_NEAREST);
03aef4b6
DS		 2326 devpriv->stc_writel(dev, timer, AI_SI_Load_A_Registers);
2327 devpriv->stc_writew(dev, AI_SI_Load, AI_Command_1_Register);
2328 break;
2329 case TRIG_EXT:
2330 if (cmd->scan_begin_arg & CR_EDGE)
2331 start_stop_select |= AI_START_Edge;
2332 /* AI_START_Polarity==1 is falling edge */
2333 if (cmd->scan_begin_arg & CR_INVERT)
2334 start_stop_select |= AI_START_Polarity;
2335 if (cmd->scan_begin_src != cmd->convert_src ||
0a85b6f0
MT		 2336 (cmd->scan_begin_arg & ~CR_EDGE) !=
2337 (cmd->convert_arg & ~CR_EDGE))
03aef4b6
DS		 2338 start_stop_select |= AI_START_Sync;
2339 start_stop_select |=
0a85b6f0 2340 AI_START_Select(1 + CR_CHAN(cmd->scan_begin_arg));
03aef4b6 2341 devpriv->stc_writew(dev, start_stop_select,
0a85b6f0 2342 AI_START_STOP_Select_Register);
03aef4b6
DS		 2343 break;
2344 }
2345
2346 switch (cmd->convert_src) {
2347 case TRIG_TIMER:
2348 case TRIG_NOW:
2349 if (cmd->convert_arg == 0 || cmd->convert_src == TRIG_NOW)
2350 timer = 1;
2351 else
2352 timer = ni_ns_to_timer(dev, cmd->convert_arg,
0a85b6f0 2353 TRIG_ROUND_NEAREST);
03aef4b6
DS		 2354 devpriv->stc_writew(dev, 1, AI_SI2_Load_A_Register); /* 0,0 does not work. */
2355 devpriv->stc_writew(dev, timer, AI_SI2_Load_B_Register);
2356
2357 /* AI_SI2_Reload_Mode = alternate */
2358 /* AI_SI2_Initial_Load_Source = A */
2359 mode2 &= ~AI_SI2_Initial_Load_Source;
2360 mode2 |= AI_SI2_Reload_Mode;
2361 devpriv->stc_writew(dev, mode2, AI_Mode_2_Register);
2362
2363 /* AI_SI2_Load */
2364 devpriv->stc_writew(dev, AI_SI2_Load, AI_Command_1_Register);
2365
2696fb57
BP		 2366 mode2 |= AI_SI2_Reload_Mode; /* alternate */
2367 mode2 |= AI_SI2_Initial_Load_Source; /* B */
03aef4b6
DS		 2368
2369 devpriv->stc_writew(dev, mode2, AI_Mode_2_Register);
2370 break;
2371 case TRIG_EXT:
2372 mode1 |= AI_CONVERT_Source_Select(1 + cmd->convert_arg);
2373 if ((cmd->convert_arg & CR_INVERT) == 0)
2374 mode1 |= AI_CONVERT_Source_Polarity;
2375 devpriv->stc_writew(dev, mode1, AI_Mode_1_Register);
2376
2377 mode2 |= AI_Start_Stop_Gate_Enable | AI_SC_Gate_Enable;
2378 devpriv->stc_writew(dev, mode2, AI_Mode_2_Register);
2379
2380 break;
2381 }
2382
2383 if (dev->irq) {
2384
2385 /* interrupt on FIFO, errors, SC_TC */
2386 interrupt_a_enable |= AI_Error_Interrupt_Enable |
0a85b6f0 2387 AI_SC_TC_Interrupt_Enable;
03aef4b6
DS		 2388
2389#ifndef PCIDMA
2390 interrupt_a_enable |= AI_FIFO_Interrupt_Enable;
2391#endif
2392
2393 if (cmd->flags & TRIG_WAKE_EOS
0a85b6f0 2394 || (devpriv->ai_cmd2 & AI_End_On_End_Of_Scan)) {
03aef4b6
DS		 2395 /* wake on end-of-scan */
2396 devpriv->aimode = AIMODE_SCAN;
2397 } else {
2398 devpriv->aimode = AIMODE_HALF_FULL;
2399 }
2400
2401 switch (devpriv->aimode) {
2402 case AIMODE_HALF_FULL:
2403 /*generate FIFO interrupts and DMA requests on half-full */
2404#ifdef PCIDMA
2405 devpriv->stc_writew(dev, AI_FIFO_Mode_HF_to_E,
0a85b6f0 2406 AI_Mode_3_Register);
03aef4b6
DS		 2407#else
2408 devpriv->stc_writew(dev, AI_FIFO_Mode_HF,
0a85b6f0 2409 AI_Mode_3_Register);
03aef4b6
DS		 2410#endif
2411 break;
2412 case AIMODE_SAMPLE:
2413 /*generate FIFO interrupts on non-empty */
2414 devpriv->stc_writew(dev, AI_FIFO_Mode_NE,
0a85b6f0 2415 AI_Mode_3_Register);
03aef4b6
DS		 2416 break;
2417 case AIMODE_SCAN:
2418#ifdef PCIDMA
2419 devpriv->stc_writew(dev, AI_FIFO_Mode_NE,
0a85b6f0 2420 AI_Mode_3_Register);
03aef4b6
DS		 2421#else
2422 devpriv->stc_writew(dev, AI_FIFO_Mode_HF,
0a85b6f0 2423 AI_Mode_3_Register);
03aef4b6
DS		 2424#endif
2425 interrupt_a_enable |= AI_STOP_Interrupt_Enable;
2426 break;
2427 default:
2428 break;
2429 }
2430
2431 devpriv->stc_writew(dev, AI_Error_Interrupt_Ack | AI_STOP_Interrupt_Ack | AI_START_Interrupt_Ack | AI_START2_Interrupt_Ack | AI_START1_Interrupt_Ack | AI_SC_TC_Interrupt_Ack | AI_SC_TC_Error_Confirm, Interrupt_A_Ack_Register); /* clear interrupts */
2432
2433 ni_set_bits(dev, Interrupt_A_Enable_Register,
0a85b6f0 2434 interrupt_a_enable, 1);
03aef4b6
DS		 2435 } else {
2436 /* interrupt on nothing */
2437 ni_set_bits(dev, Interrupt_A_Enable_Register, ~0, 0);
2438
2439 /* XXX start polling if necessary */
03aef4b6
DS		 2440 }
2441
2442 /* end configuration */
2443 devpriv->stc_writew(dev, AI_Configuration_End, Joint_Reset_Register);
2444
2445 switch (cmd->scan_begin_src) {
2446 case TRIG_TIMER:
2447 devpriv->stc_writew(dev,
0a85b6f0
MT		 2448 AI_SI2_Arm | AI_SI_Arm | AI_DIV_Arm |
2449 AI_SC_Arm, AI_Command_1_Register);
03aef4b6
DS		 2450 break;
2451 case TRIG_EXT:
2452 /* XXX AI_SI_Arm? */
2453 devpriv->stc_writew(dev,
0a85b6f0
MT		 2454 AI_SI2_Arm | AI_SI_Arm | AI_DIV_Arm |
2455 AI_SC_Arm, AI_Command_1_Register);
03aef4b6
DS		 2456 break;
2457 }
2458
2459#ifdef PCIDMA
2460 {
2461 int retval = ni_ai_setup_MITE_dma(dev);
2462 if (retval)
2463 return retval;
2464 }
03aef4b6
DS		 2465#endif
2466
ebb657ba 2467 if (cmd->start_src == TRIG_NOW) {
03aef4b6
DS		 2468 /* AI_START1_Pulse */
2469 devpriv->stc_writew(dev, AI_START1_Pulse | devpriv->ai_cmd2,
0a85b6f0 2470 AI_Command_2_Register);
03aef4b6 2471 s->async->inttrig = NULL;
ebb657ba 2472 } else if (cmd->start_src == TRIG_EXT) {
03aef4b6 2473 s->async->inttrig = NULL;
ebb657ba
HS		 2474 } else { /* TRIG_INT */
2475 s->async->inttrig = ni_ai_inttrig;
03aef4b6
DS		 2476 }
2477
03aef4b6
DS		 2478 return 0;
2479}
2480
ebb657ba
HS		 2481static int ni_ai_inttrig(struct comedi_device *dev,
2482 struct comedi_subdevice *s,
2483 unsigned int trig_num)
03aef4b6 2484{
0e05c552 2485 struct ni_private *devpriv = dev->private;
ebb657ba 2486 struct comedi_cmd *cmd = &s->async->cmd;
0e05c552 2487
ebb657ba 2488 if (trig_num != cmd->start_arg)
03aef4b6
DS		 2489 return -EINVAL;
2490
2491 devpriv->stc_writew(dev, AI_START1_Pulse | devpriv->ai_cmd2,
0a85b6f0 2492 AI_Command_2_Register);
03aef4b6
DS		 2493 s->async->inttrig = NULL;
2494
2495 return 1;
2496}
2497
0a85b6f0
MT		 2498static int ni_ai_config_analog_trig(struct comedi_device *dev,
2499 struct comedi_subdevice *s,
2500 struct comedi_insn *insn,
2501 unsigned int *data);
03aef4b6 2502
0a85b6f0
MT		 2503static int ni_ai_insn_config(struct comedi_device *dev,
2504 struct comedi_subdevice *s,
2505 struct comedi_insn *insn, unsigned int *data)
03aef4b6 2506{
6293e357 2507 const struct ni_board_struct *board = comedi_board(dev);
0e05c552
HS		 2508 struct ni_private *devpriv = dev->private;
2509
03aef4b6
DS		 2510 if (insn->n < 1)
2511 return -EINVAL;
2512
2513 switch (data[0]) {
2514 case INSN_CONFIG_ANALOG_TRIG:
2515 return ni_ai_config_analog_trig(dev, s, insn, data);
2516 case INSN_CONFIG_ALT_SOURCE:
6293e357 2517 if (board->reg_type & ni_reg_m_series_mask) {
03aef4b6
DS		 2518 if (data[1] & ~(MSeries_AI_Bypass_Cal_Sel_Pos_Mask |
2519 MSeries_AI_Bypass_Cal_Sel_Neg_Mask |
2520 MSeries_AI_Bypass_Mode_Mux_Mask |
2521 MSeries_AO_Bypass_AO_Cal_Sel_Mask)) {
2522 return -EINVAL;
2523 }
2524 devpriv->ai_calib_source = data[1];
6293e357 2525 } else if (board->reg_type == ni_reg_6143) {
03aef4b6
DS		 2526 unsigned int calib_source;
2527
2528 calib_source = data[1] & 0xf;
2529
2530 if (calib_source > 0xF)
2531 return -EINVAL;
2532
2533 devpriv->ai_calib_source = calib_source;
2534 ni_writew(calib_source, Calibration_Channel_6143);
2535 } else {
2536 unsigned int calib_source;
2537 unsigned int calib_source_adjust;
2538
2539 calib_source = data[1] & 0xf;
2540 calib_source_adjust = (data[1] >> 4) & 0xff;
2541
2542 if (calib_source >= 8)
2543 return -EINVAL;
2544 devpriv->ai_calib_source = calib_source;
6293e357 2545 if (board->reg_type == ni_reg_611x) {
03aef4b6 2546 ni_writeb(calib_source_adjust,
0a85b6f0 2547 Cal_Gain_Select_611x);
03aef4b6
DS		 2548 }
2549 }
2550 return 2;
2551 default:
2552 break;
2553 }
2554
2555 return -EINVAL;
2556}
2557
0a85b6f0
MT		 2558static int ni_ai_config_analog_trig(struct comedi_device *dev,
2559 struct comedi_subdevice *s,
2560 struct comedi_insn *insn,
2561 unsigned int *data)
03aef4b6 2562{
6293e357 2563 const struct ni_board_struct *board = comedi_board(dev);
0e05c552 2564 struct ni_private *devpriv = dev->private;
03aef4b6
DS		 2565 unsigned int a, b, modebits;
2566 int err = 0;
2567
2568 /* data[1] is flags
2569 * data[2] is analog line
2570 * data[3] is set level
2571 * data[4] is reset level */
6293e357 2572 if (!board->has_analog_trig)
03aef4b6
DS		 2573 return -EINVAL;
2574 if ((data[1] & 0xffff0000) != COMEDI_EV_SCAN_BEGIN) {
2575 data[1] &= (COMEDI_EV_SCAN_BEGIN | 0xffff);
2576 err++;
2577 }
6293e357
HS		 2578 if (data[2] >= board->n_adchan) {
2579 data[2] = board->n_adchan - 1;
03aef4b6
DS		 2580 err++;
2581 }
2582 if (data[3] > 255) { /* a */
2583 data[3] = 255;
2584 err++;
2585 }
2586 if (data[4] > 255) { /* b */
2587 data[4] = 255;
2588 err++;
2589 }
2590 /*
2591 * 00 ignore
2592 * 01 set
2593 * 10 reset
2594 *
2595 * modes:
2596 * 1 level: +b- +a-
2597 * high mode 00 00 01 10
2598 * low mode 00 00 10 01
2599 * 2 level: (a<b)
2600 * hysteresis low mode 10 00 00 01
2601 * hysteresis high mode 01 00 00 10
2602 * middle mode 10 01 01 10
2603 */
2604
2605 a = data[3];
2606 b = data[4];
2607 modebits = data[1] & 0xff;
2608 if (modebits & 0xf0) {
2609 /* two level mode */
2610 if (b < a) {
2611 /* swap order */
2612 a = data[4];
2613 b = data[3];
2614 modebits =
0a85b6f0 2615 ((data[1] & 0xf) << 4) | ((data[1] & 0xf0) >> 4);
03aef4b6
DS		 2616 }
2617 devpriv->atrig_low = a;
2618 devpriv->atrig_high = b;
2619 switch (modebits) {
2620 case 0x81: /* low hysteresis mode */
2621 devpriv->atrig_mode = 6;
2622 break;
2623 case 0x42: /* high hysteresis mode */
2624 devpriv->atrig_mode = 3;
2625 break;
2626 case 0x96: /* middle window mode */
2627 devpriv->atrig_mode = 2;
2628 break;
2629 default:
2630 data[1] &= ~0xff;
2631 err++;
2632 }
2633 } else {
2634 /* one level mode */
2635 if (b != 0) {
2636 data[4] = 0;
2637 err++;
2638 }
2639 switch (modebits) {
2640 case 0x06: /* high window mode */
2641 devpriv->atrig_high = a;
2642 devpriv->atrig_mode = 0;
2643 break;
2644 case 0x09: /* low window mode */
2645 devpriv->atrig_low = a;
2646 devpriv->atrig_mode = 1;
2647 break;
2648 default:
2649 data[1] &= ~0xff;
2650 err++;
2651 }
2652 }
2653 if (err)
2654 return -EAGAIN;
2655 return 5;
2656}
2657
2658/* munge data from unsigned to 2's complement for analog output bipolar modes */
da91b269 2659static void ni_ao_munge(struct comedi_device *dev, struct comedi_subdevice *s,
0a85b6f0
MT		 2660 void *data, unsigned int num_bytes,
2661 unsigned int chan_index)
03aef4b6 2662{
6293e357 2663 const struct ni_board_struct *board = comedi_board(dev);
d163679c 2664 struct comedi_async *async = s->async;
9663ab1f 2665 struct comedi_cmd *cmd = &async->cmd;
790c5541 2666 unsigned int length = num_bytes / sizeof(short);
9663ab1f 2667 unsigned int offset = 1 << (board->aobits - 1);
3a2b101c 2668 unsigned short *array = data;
9663ab1f
HS		 2669 unsigned int range;
2670 unsigned int i;
03aef4b6 2671
03aef4b6 2672 for (i = 0; i < length; i++) {
9663ab1f 2673 range = CR_RANGE(cmd->chanlist[chan_index]);
6293e357 2674 if (board->ao_unipolar == 0 || (range & 1) == 0)
03aef4b6
DS		 2675 array[i] -= offset;
2676#ifdef PCIDMA
2677 array[i] = cpu_to_le16(array[i]);
2678#endif
2679 chan_index++;
9663ab1f 2680 chan_index %= cmd->chanlist_len;
03aef4b6
DS		 2681 }
2682}
2683
da91b269 2684static int ni_m_series_ao_config_chanlist(struct comedi_device *dev,
0a85b6f0
MT		 2685 struct comedi_subdevice *s,
2686 unsigned int chanspec[],
2687 unsigned int n_chans, int timed)
03aef4b6 2688{
6293e357 2689 const struct ni_board_struct *board = comedi_board(dev);
0e05c552 2690 struct ni_private *devpriv = dev->private;
03aef4b6
DS		 2691 unsigned int range;
2692 unsigned int chan;
2693 unsigned int conf;
2694 int i;
2695 int invert = 0;
2696
53106ae6 2697 if (timed) {
6293e357 2698 for (i = 0; i < board->n_aochan; ++i) {
03aef4b6 2699 devpriv->ao_conf[i] &= ~MSeries_AO_Update_Timed_Bit;
0a85b6f0
MT		 2700 ni_writeb(devpriv->ao_conf[i],
2701 M_Offset_AO_Config_Bank(i));
03aef4b6
DS		 2702 ni_writeb(0xf, M_Offset_AO_Waveform_Order(i));
2703 }
2704 }
2705 for (i = 0; i < n_chans; i++) {
1f6325d6 2706 const struct comedi_krange *krange;
03aef4b6
DS		 2707 chan = CR_CHAN(chanspec[i]);
2708 range = CR_RANGE(chanspec[i]);
2709 krange = s->range_table->range + range;
2710 invert = 0;
2711 conf = 0;
2712 switch (krange->max - krange->min) {
2713 case 20000000:
2714 conf |= MSeries_AO_DAC_Reference_10V_Internal_Bits;
2715 ni_writeb(0, M_Offset_AO_Reference_Attenuation(chan));
2716 break;
2717 case 10000000:
2718 conf |= MSeries_AO_DAC_Reference_5V_Internal_Bits;
2719 ni_writeb(0, M_Offset_AO_Reference_Attenuation(chan));
2720 break;
2721 case 4000000:
2722 conf |= MSeries_AO_DAC_Reference_10V_Internal_Bits;
2723 ni_writeb(MSeries_Attenuate_x5_Bit,
0a85b6f0 2724 M_Offset_AO_Reference_Attenuation(chan));
03aef4b6
DS		 2725 break;
2726 case 2000000:
2727 conf |= MSeries_AO_DAC_Reference_5V_Internal_Bits;
2728 ni_writeb(MSeries_Attenuate_x5_Bit,
0a85b6f0 2729 M_Offset_AO_Reference_Attenuation(chan));
03aef4b6
DS		 2730 break;
2731 default:
5f74ea14 2732 printk("%s: bug! unhandled ao reference voltage\n",
0a85b6f0 2733 __func__);
03aef4b6
DS		 2734 break;
2735 }
2736 switch (krange->max + krange->min) {
2737 case 0:
2738 conf |= MSeries_AO_DAC_Offset_0V_Bits;
2739 break;
2740 case 10000000:
2741 conf |= MSeries_AO_DAC_Offset_5V_Bits;
2742 break;
2743 default:
5f74ea14 2744 printk("%s: bug! unhandled ao offset voltage\n",
0a85b6f0 2745 __func__);
03aef4b6
DS		 2746 break;
2747 }
2748 if (timed)
2749 conf |= MSeries_AO_Update_Timed_Bit;
2750 ni_writeb(conf, M_Offset_AO_Config_Bank(chan));
2751 devpriv->ao_conf[chan] = conf;
2752 ni_writeb(i, M_Offset_AO_Waveform_Order(chan));
2753 }
2754 return invert;
2755}
2756
0a85b6f0
MT		 2757static int ni_old_ao_config_chanlist(struct comedi_device *dev,
2758 struct comedi_subdevice *s,
2759 unsigned int chanspec[],
2760 unsigned int n_chans)
03aef4b6 2761{
6293e357 2762 const struct ni_board_struct *board = comedi_board(dev);
0e05c552 2763 struct ni_private *devpriv = dev->private;
03aef4b6
DS		 2764 unsigned int range;
2765 unsigned int chan;
2766 unsigned int conf;
2767 int i;
2768 int invert = 0;
2769
2770 for (i = 0; i < n_chans; i++) {
2771 chan = CR_CHAN(chanspec[i]);
2772 range = CR_RANGE(chanspec[i]);
2773 conf = AO_Channel(chan);
2774
6293e357 2775 if (board->ao_unipolar) {
03aef4b6
DS		 2776 if ((range & 1) == 0) {
2777 conf |= AO_Bipolar;
6293e357 2778 invert = (1 << (board->aobits - 1));
03aef4b6
DS		 2779 } else {
2780 invert = 0;
2781 }
2782 if (range & 2)
2783 conf |= AO_Ext_Ref;
2784 } else {
2785 conf |= AO_Bipolar;
6293e357 2786 invert = (1 << (board->aobits - 1));
03aef4b6
DS		 2787 }
2788
2789 /* not all boards can deglitch, but this shouldn't hurt */
2790 if (chanspec[i] & CR_DEGLITCH)
2791 conf |= AO_Deglitch;
2792
2793 /* analog reference */
2794 /* AREF_OTHER connects AO ground to AI ground, i think */
2795 conf |= (CR_AREF(chanspec[i]) ==
0a85b6f0 2796 AREF_OTHER) ? AO_Ground_Ref : 0;
03aef4b6
DS		 2797
2798 ni_writew(conf, AO_Configuration);
2799 devpriv->ao_conf[chan] = conf;
2800 }
2801 return invert;
2802}
2803
0a85b6f0
MT		 2804static int ni_ao_config_chanlist(struct comedi_device *dev,
2805 struct comedi_subdevice *s,
2806 unsigned int chanspec[], unsigned int n_chans,
2807 int timed)
03aef4b6 2808{
6293e357
HS		 2809 const struct ni_board_struct *board = comedi_board(dev);
2810
2811 if (board->reg_type & ni_reg_m_series_mask)
03aef4b6 2812 return ni_m_series_ao_config_chanlist(dev, s, chanspec, n_chans,
0a85b6f0 2813 timed);
03aef4b6
DS		 2814 else
2815 return ni_old_ao_config_chanlist(dev, s, chanspec, n_chans);
2816}
0a85b6f0
MT		 2817
2818static int ni_ao_insn_read(struct comedi_device *dev,
2819 struct comedi_subdevice *s, struct comedi_insn *insn,
2820 unsigned int *data)
03aef4b6 2821{
0e05c552
HS		 2822 struct ni_private *devpriv = dev->private;
2823
03aef4b6
DS		 2824 data[0] = devpriv->ao[CR_CHAN(insn->chanspec)];
2825
2826 return 1;
2827}
2828
0a85b6f0
MT		 2829static int ni_ao_insn_write(struct comedi_device *dev,
2830 struct comedi_subdevice *s,
2831 struct comedi_insn *insn, unsigned int *data)
03aef4b6 2832{
6293e357 2833 const struct ni_board_struct *board = comedi_board(dev);
0e05c552 2834 struct ni_private *devpriv = dev->private;
03aef4b6
DS		 2835 unsigned int chan = CR_CHAN(insn->chanspec);
2836 unsigned int invert;
2837
2838 invert = ni_ao_config_chanlist(dev, s, &insn->chanspec, 1, 0);
2839
2840 devpriv->ao[chan] = data[0];
2841
6293e357 2842 if (board->reg_type & ni_reg_m_series_mask) {
03aef4b6
DS		 2843 ni_writew(data[0], M_Offset_DAC_Direct_Data(chan));
2844 } else
2845 ni_writew(data[0] ^ invert,
0a85b6f0 2846 (chan) ? DAC1_Direct_Data : DAC0_Direct_Data);
03aef4b6
DS		 2847
2848 return 1;
2849}
2850
0a85b6f0
MT		 2851static int ni_ao_insn_write_671x(struct comedi_device *dev,
2852 struct comedi_subdevice *s,
2853 struct comedi_insn *insn, unsigned int *data)
03aef4b6 2854{
6293e357 2855 const struct ni_board_struct *board = comedi_board(dev);
0e05c552 2856 struct ni_private *devpriv = dev->private;
03aef4b6
DS		 2857 unsigned int chan = CR_CHAN(insn->chanspec);
2858 unsigned int invert;
2859
2860 ao_win_out(1 << chan, AO_Immediate_671x);
6293e357 2861 invert = 1 << (board->aobits - 1);
03aef4b6
DS		 2862
2863 ni_ao_config_chanlist(dev, s, &insn->chanspec, 1, 0);
2864
2865 devpriv->ao[chan] = data[0];
2866 ao_win_out(data[0] ^ invert, DACx_Direct_Data_671x(chan));
2867
2868 return 1;
2869}
2870
0a85b6f0
MT		 2871static int ni_ao_insn_config(struct comedi_device *dev,
2872 struct comedi_subdevice *s,
2873 struct comedi_insn *insn, unsigned int *data)
03aef4b6 2874{
6293e357 2875 const struct ni_board_struct *board = comedi_board(dev);
0e05c552
HS		 2876 struct ni_private *devpriv = dev->private;
2877
03aef4b6
DS		 2878 switch (data[0]) {
2879 case INSN_CONFIG_GET_HARDWARE_BUFFER_SIZE:
0a85b6f0 2880 switch (data[1]) {
03aef4b6 2881 case COMEDI_OUTPUT:
6293e357 2882 data[2] = 1 + board->ao_fifo_depth * sizeof(short);
0a85b6f0
MT		 2883 if (devpriv->mite)
2884 data[2] += devpriv->mite->fifo_size;
03aef4b6
DS		 2885 break;
2886 case COMEDI_INPUT:
2887 data[2] = 0;
2888 break;
2889 default:
2890 return -EINVAL;
2891 break;
2892 }
2893 return 0;
2894 default:
2895 break;
2896 }
2897
2898 return -EINVAL;
2899}
2900
ebb657ba
HS		 2901static int ni_ao_inttrig(struct comedi_device *dev,
2902 struct comedi_subdevice *s,
2903 unsigned int trig_num)
03aef4b6 2904{
6293e357 2905 const struct ni_board_struct *board __maybe_unused = comedi_board(dev);
0e05c552 2906 struct ni_private *devpriv = dev->private;
ebb657ba 2907 struct comedi_cmd *cmd = &s->async->cmd;
03aef4b6
DS		 2908 int ret;
2909 int interrupt_b_bits;
2910 int i;
2911 static const int timeout = 1000;
2912
ebb657ba 2913 if (trig_num != cmd->start_arg)
03aef4b6
DS		 2914 return -EINVAL;
2915
2916 /* Null trig at beginning prevent ao start trigger from executing more than
2917 once per command (and doing things like trying to allocate the ao dma channel
2918 multiple times) */
2919 s->async->inttrig = NULL;
2920
2921 ni_set_bits(dev, Interrupt_B_Enable_Register,
0a85b6f0 2922 AO_FIFO_Interrupt_Enable | AO_Error_Interrupt_Enable, 0);
03aef4b6
DS		 2923 interrupt_b_bits = AO_Error_Interrupt_Enable;
2924#ifdef PCIDMA
2925 devpriv->stc_writew(dev, 1, DAC_FIFO_Clear);
6293e357 2926 if (board->reg_type & ni_reg_6xxx_mask)
03aef4b6
DS		 2927 ni_ao_win_outl(dev, 0x6, AO_FIFO_Offset_Load_611x);
2928 ret = ni_ao_setup_MITE_dma(dev);
2929 if (ret)
2930 return ret;
2931 ret = ni_ao_wait_for_dma_load(dev);
2932 if (ret < 0)
2933 return ret;
2934#else
2935 ret = ni_ao_prep_fifo(dev, s);
2936 if (ret == 0)
2937 return -EPIPE;
2938
2939 interrupt_b_bits |= AO_FIFO_Interrupt_Enable;
2940#endif
2941
2942 devpriv->stc_writew(dev, devpriv->ao_mode3 | AO_Not_An_UPDATE,
0a85b6f0 2943 AO_Mode_3_Register);
03aef4b6
DS		 2944 devpriv->stc_writew(dev, devpriv->ao_mode3, AO_Mode_3_Register);
2945 /* wait for DACs to be loaded */
2946 for (i = 0; i < timeout; i++) {
5f74ea14 2947 udelay(1);
03aef4b6
DS		 2948 if ((devpriv->stc_readw(dev,
2949 Joint_Status_2_Register) &
0a85b6f0 2950 AO_TMRDACWRs_In_Progress_St) == 0)
03aef4b6
DS		 2951 break;
2952 }
2953 if (i == timeout) {
2954 comedi_error(dev,
0a85b6f0 2955 "timed out waiting for AO_TMRDACWRs_In_Progress_St to clear");
03aef4b6
DS		 2956 return -EIO;
2957 }
2696fb57 2958 /* stc manual says we are need to clear error interrupt after AO_TMRDACWRs_In_Progress_St clears */
03aef4b6 2959 devpriv->stc_writew(dev, AO_Error_Interrupt_Ack,
0a85b6f0 2960 Interrupt_B_Ack_Register);
03aef4b6
DS		 2961
2962 ni_set_bits(dev, Interrupt_B_Enable_Register, interrupt_b_bits, 1);
2963
2964 devpriv->stc_writew(dev,
0a85b6f0
MT		 2965 devpriv->ao_cmd1 | AO_UI_Arm | AO_UC_Arm | AO_BC_Arm
2966 | AO_DAC1_Update_Mode | AO_DAC0_Update_Mode,
2967 AO_Command_1_Register);
03aef4b6
DS		 2968
2969 devpriv->stc_writew(dev, devpriv->ao_cmd2 | AO_START1_Pulse,
0a85b6f0 2970 AO_Command_2_Register);
03aef4b6
DS		 2971
2972 return 0;
2973}
2974
da91b269 2975static int ni_ao_cmd(struct comedi_device *dev, struct comedi_subdevice *s)
03aef4b6 2976{
6293e357 2977 const struct ni_board_struct *board = comedi_board(dev);
0e05c552 2978 struct ni_private *devpriv = dev->private;
ea6d0d4c 2979 const struct comedi_cmd *cmd = &s->async->cmd;
03aef4b6
DS		 2980 int bits;
2981 int i;
2982 unsigned trigvar;
2983
2984 if (dev->irq == 0) {
2985 comedi_error(dev, "cannot run command without an irq");
2986 return -EIO;
2987 }
2988
2989 devpriv->stc_writew(dev, AO_Configuration_Start, Joint_Reset_Register);
2990
2991 devpriv->stc_writew(dev, AO_Disarm, AO_Command_1_Register);
2992
6293e357 2993 if (board->reg_type & ni_reg_6xxx_mask) {
03aef4b6
DS		 2994 ao_win_out(CLEAR_WG, AO_Misc_611x);
2995
2996 bits = 0;
2997 for (i = 0; i < cmd->chanlist_len; i++) {
2998 int chan;
2999
3000 chan = CR_CHAN(cmd->chanlist[i]);
3001 bits |= 1 << chan;
3002 ao_win_out(chan, AO_Waveform_Generation_611x);
3003 }
3004 ao_win_out(bits, AO_Timed_611x);
3005 }
3006
3007 ni_ao_config_chanlist(dev, s, cmd->chanlist, cmd->chanlist_len, 1);
3008
3009 if (cmd->stop_src == TRIG_NONE) {
3010 devpriv->ao_mode1 |= AO_Continuous;
3011 devpriv->ao_mode1 &= ~AO_Trigger_Once;
3012 } else {
3013 devpriv->ao_mode1 &= ~AO_Continuous;
3014 devpriv->ao_mode1 |= AO_Trigger_Once;
3015 }
3016 devpriv->stc_writew(dev, devpriv->ao_mode1, AO_Mode_1_Register);
3017 switch (cmd->start_src) {
3018 case TRIG_INT:
3019 case TRIG_NOW:
3020 devpriv->ao_trigger_select &=
0a85b6f0 3021 ~(AO_START1_Polarity | AO_START1_Select(-1));
03aef4b6
DS		 3022 devpriv->ao_trigger_select |= AO_START1_Edge | AO_START1_Sync;
3023 devpriv->stc_writew(dev, devpriv->ao_trigger_select,
0a85b6f0 3024 AO_Trigger_Select_Register);
03aef4b6
DS		 3025 break;
3026 case TRIG_EXT:
0a85b6f0
MT		 3027 devpriv->ao_trigger_select =
3028 AO_START1_Select(CR_CHAN(cmd->start_arg) + 1);
03aef4b6 3029 if (cmd->start_arg & CR_INVERT)
0a85b6f0 3030 devpriv->ao_trigger_select |= AO_START1_Polarity; /* 0=active high, 1=active low. see daq-stc 3-24 (p186) */
03aef4b6 3031 if (cmd->start_arg & CR_EDGE)
0a85b6f0
MT		 3032 devpriv->ao_trigger_select |= AO_START1_Edge; /* 0=edge detection disabled, 1=enabled */
3033 devpriv->stc_writew(dev, devpriv->ao_trigger_select,
3034 AO_Trigger_Select_Register);
03aef4b6
DS		 3035 break;
3036 default:
3037 BUG();
3038 break;
3039 }
3040 devpriv->ao_mode3 &= ~AO_Trigger_Length;
3041 devpriv->stc_writew(dev, devpriv->ao_mode3, AO_Mode_3_Register);
3042
3043 devpriv->stc_writew(dev, devpriv->ao_mode1, AO_Mode_1_Register);
3044 devpriv->ao_mode2 &= ~AO_BC_Initial_Load_Source;
3045 devpriv->stc_writew(dev, devpriv->ao_mode2, AO_Mode_2_Register);
bc461556 3046 if (cmd->stop_src == TRIG_NONE)
03aef4b6 3047 devpriv->stc_writel(dev, 0xffffff, AO_BC_Load_A_Register);
bc461556 3048 else
03aef4b6 3049 devpriv->stc_writel(dev, 0, AO_BC_Load_A_Register);
03aef4b6
DS		 3050 devpriv->stc_writew(dev, AO_BC_Load, AO_Command_1_Register);
3051 devpriv->ao_mode2 &= ~AO_UC_Initial_Load_Source;
3052 devpriv->stc_writew(dev, devpriv->ao_mode2, AO_Mode_2_Register);
3053 switch (cmd->stop_src) {
3054 case TRIG_COUNT:
6293e357 3055 if (board->reg_type & ni_reg_m_series_mask) {
2696fb57 3056 /* this is how the NI example code does it for m-series boards, verified correct with 6259 */
03aef4b6 3057 devpriv->stc_writel(dev, cmd->stop_arg - 1,
0a85b6f0
MT		 3058 AO_UC_Load_A_Register);
3059 devpriv->stc_writew(dev, AO_UC_Load,
3060 AO_Command_1_Register);
3061 } else {
3062 devpriv->stc_writel(dev, cmd->stop_arg,
3063 AO_UC_Load_A_Register);
3064 devpriv->stc_writew(dev, AO_UC_Load,
3065 AO_Command_1_Register);
3066 devpriv->stc_writel(dev, cmd->stop_arg - 1,
3067 AO_UC_Load_A_Register);
03aef4b6
DS		 3068 }
3069 break;
3070 case TRIG_NONE:
3071 devpriv->stc_writel(dev, 0xffffff, AO_UC_Load_A_Register);
3072 devpriv->stc_writew(dev, AO_UC_Load, AO_Command_1_Register);
3073 devpriv->stc_writel(dev, 0xffffff, AO_UC_Load_A_Register);
3074 break;
3075 default:
3076 devpriv->stc_writel(dev, 0, AO_UC_Load_A_Register);
3077 devpriv->stc_writew(dev, AO_UC_Load, AO_Command_1_Register);
3078 devpriv->stc_writel(dev, cmd->stop_arg, AO_UC_Load_A_Register);
3079 }
3080
3081 devpriv->ao_mode1 &=
0a85b6f0
MT		 3082 ~(AO_UI_Source_Select(0x1f) | AO_UI_Source_Polarity |
3083 AO_UPDATE_Source_Select(0x1f) | AO_UPDATE_Source_Polarity);
03aef4b6
DS		 3084 switch (cmd->scan_begin_src) {
3085 case TRIG_TIMER:
3086 devpriv->ao_cmd2 &= ~AO_BC_Gate_Enable;
3087 trigvar =
0a85b6f0
MT		 3088 ni_ns_to_timer(dev, cmd->scan_begin_arg,
3089 TRIG_ROUND_NEAREST);
03aef4b6
DS		 3090 devpriv->stc_writel(dev, 1, AO_UI_Load_A_Register);
3091 devpriv->stc_writew(dev, AO_UI_Load, AO_Command_1_Register);
3092 devpriv->stc_writel(dev, trigvar, AO_UI_Load_A_Register);
3093 break;
3094 case TRIG_EXT:
3095 devpriv->ao_mode1 |=
0a85b6f0 3096 AO_UPDATE_Source_Select(cmd->scan_begin_arg);
03aef4b6
DS		 3097 if (cmd->scan_begin_arg & CR_INVERT)
3098 devpriv->ao_mode1 |= AO_UPDATE_Source_Polarity;
3099 devpriv->ao_cmd2 |= AO_BC_Gate_Enable;
3100 break;
3101 default:
3102 BUG();
3103 break;
3104 }
3105 devpriv->stc_writew(dev, devpriv->ao_cmd2, AO_Command_2_Register);
3106 devpriv->stc_writew(dev, devpriv->ao_mode1, AO_Mode_1_Register);
3107 devpriv->ao_mode2 &=
0a85b6f0 3108 ~(AO_UI_Reload_Mode(3) | AO_UI_Initial_Load_Source);
03aef4b6
DS		 3109 devpriv->stc_writew(dev, devpriv->ao_mode2, AO_Mode_2_Register);
3110
3111 if (cmd->scan_end_arg > 1) {
3112 devpriv->ao_mode1 |= AO_Multiple_Channels;
3113 devpriv->stc_writew(dev,
0a85b6f0
MT		 3114 AO_Number_Of_Channels(cmd->scan_end_arg -
3115 1) |
3116 AO_UPDATE_Output_Select
3117 (AO_Update_Output_High_Z),
3118 AO_Output_Control_Register);
03aef4b6
DS		 3119 } else {
3120 unsigned bits;
3121 devpriv->ao_mode1 &= ~AO_Multiple_Channels;
3122 bits = AO_UPDATE_Output_Select(AO_Update_Output_High_Z);
6293e357
HS		 3123 if (board->reg_type &
3124 (ni_reg_m_series_mask | ni_reg_6xxx_mask)) {
03aef4b6
DS		 3125 bits |= AO_Number_Of_Channels(0);
3126 } else {
0a85b6f0
MT		 3127 bits |=
3128 AO_Number_Of_Channels(CR_CHAN(cmd->chanlist[0]));
03aef4b6 3129 }
0a85b6f0 3130 devpriv->stc_writew(dev, bits, AO_Output_Control_Register);
03aef4b6
DS		 3131 }
3132 devpriv->stc_writew(dev, devpriv->ao_mode1, AO_Mode_1_Register);
3133
3134 devpriv->stc_writew(dev, AO_DAC0_Update_Mode | AO_DAC1_Update_Mode,
0a85b6f0 3135 AO_Command_1_Register);
03aef4b6
DS		 3136
3137 devpriv->ao_mode3 |= AO_Stop_On_Overrun_Error;
3138 devpriv->stc_writew(dev, devpriv->ao_mode3, AO_Mode_3_Register);
3139
3140 devpriv->ao_mode2 &= ~AO_FIFO_Mode_Mask;
3141#ifdef PCIDMA
3142 devpriv->ao_mode2 |= AO_FIFO_Mode_HF_to_F;
3143#else
3144 devpriv->ao_mode2 |= AO_FIFO_Mode_HF;
3145#endif
3146 devpriv->ao_mode2 &= ~AO_FIFO_Retransmit_Enable;
3147 devpriv->stc_writew(dev, devpriv->ao_mode2, AO_Mode_2_Register);
3148
3149 bits = AO_BC_Source_Select | AO_UPDATE_Pulse_Width |
0a85b6f0 3150 AO_TMRDACWR_Pulse_Width;
6293e357 3151 if (board->ao_fifo_depth)
03aef4b6
DS		 3152 bits |= AO_FIFO_Enable;
3153 else
3154 bits |= AO_DMA_PIO_Control;
3155#if 0
3156 /* F Hess: windows driver does not set AO_Number_Of_DAC_Packages bit for 6281,
3157 verified with bus analyzer. */
6293e357 3158 if (board->reg_type & ni_reg_m_series_mask)
03aef4b6
DS		 3159 bits |= AO_Number_Of_DAC_Packages;
3160#endif
3161 devpriv->stc_writew(dev, bits, AO_Personal_Register);
2696fb57 3162 /* enable sending of ao dma requests */
03aef4b6
DS		 3163 devpriv->stc_writew(dev, AO_AOFREQ_Enable, AO_Start_Select_Register);
3164
3165 devpriv->stc_writew(dev, AO_Configuration_End, Joint_Reset_Register);
3166
3167 if (cmd->stop_src == TRIG_COUNT) {
3168 devpriv->stc_writew(dev, AO_BC_TC_Interrupt_Ack,
0a85b6f0 3169 Interrupt_B_Ack_Register);
03aef4b6 3170 ni_set_bits(dev, Interrupt_B_Enable_Register,
0a85b6f0 3171 AO_BC_TC_Interrupt_Enable, 1);
03aef4b6
DS		 3172 }
3173
ebb657ba 3174 s->async->inttrig = ni_ao_inttrig;
03aef4b6
DS		 3175
3176 return 0;
3177}
3178
da91b269 3179static int ni_ao_cmdtest(struct comedi_device *dev, struct comedi_subdevice *s,
0a85b6f0 3180 struct comedi_cmd *cmd)
03aef4b6 3181{
6293e357 3182 const struct ni_board_struct *board = comedi_board(dev);
0e05c552 3183 struct ni_private *devpriv = dev->private;
03aef4b6 3184 int err = 0;
ebb657ba 3185 unsigned int tmp;
03aef4b6 3186
27020ffe 3187 /* Step 1 : check if triggers are trivially valid */
03aef4b6 3188
27020ffe 3189 if ((cmd->flags & CMDF_WRITE) == 0)
03aef4b6 3190 cmd->flags |= CMDF_WRITE;
03aef4b6 3191
27020ffe
HS		 3192 err |= cfc_check_trigger_src(&cmd->start_src, TRIG_INT | TRIG_EXT);
3193 err |= cfc_check_trigger_src(&cmd->scan_begin_src,
3194 TRIG_TIMER | TRIG_EXT);
3195 err |= cfc_check_trigger_src(&cmd->convert_src, TRIG_NOW);
3196 err |= cfc_check_trigger_src(&cmd->scan_end_src, TRIG_COUNT);
3197 err |= cfc_check_trigger_src(&cmd->stop_src, TRIG_COUNT | TRIG_NONE);
03aef4b6
DS		 3198
3199 if (err)
3200 return 1;
3201
27020ffe 3202 /* Step 2a : make sure trigger sources are unique */
03aef4b6 3203
27020ffe
HS		 3204 err |= cfc_check_trigger_is_unique(cmd->start_src);
3205 err |= cfc_check_trigger_is_unique(cmd->scan_begin_src);
3206 err |= cfc_check_trigger_is_unique(cmd->stop_src);
3207
3208 /* Step 2b : and mutually compatible */
03aef4b6
DS		 3209
3210 if (err)
3211 return 2;
3212
c3be5c7f 3213 /* Step 3: check if arguments are trivially valid */
03aef4b6 3214
ebb657ba
HS		 3215 switch (cmd->start_src) {
3216 case TRIG_INT:
3217 err |= cfc_check_trigger_arg_is(&cmd->start_arg, 0);
3218 break;
3219 case TRIG_EXT:
3220 tmp = CR_CHAN(cmd->start_arg);
03aef4b6
DS		 3221
3222 if (tmp > 18)
3223 tmp = 18;
3224 tmp |= (cmd->start_arg & (CR_INVERT | CR_EDGE));
c3be5c7f 3225 err |= cfc_check_trigger_arg_is(&cmd->start_arg, tmp);
ebb657ba 3226 break;
03aef4b6 3227 }
c3be5c7f 3228
03aef4b6 3229 if (cmd->scan_begin_src == TRIG_TIMER) {
c3be5c7f 3230 err |= cfc_check_trigger_arg_min(&cmd->scan_begin_arg,
6293e357 3231 board->ao_speed);
c3be5c7f
HS		 3232 err |= cfc_check_trigger_arg_max(&cmd->scan_begin_arg,
3233 devpriv->clock_ns * 0xffffff);
03aef4b6
DS		 3234 }
3235
c3be5c7f
HS		 3236 err |= cfc_check_trigger_arg_is(&cmd->convert_arg, 0);
3237 err |= cfc_check_trigger_arg_is(&cmd->scan_end_arg, cmd->chanlist_len);
3238
3239 if (cmd->stop_src == TRIG_COUNT)
3240 err |= cfc_check_trigger_arg_max(&cmd->stop_arg, 0x00ffffff);
3241 else /* TRIG_NONE */
3242 err |= cfc_check_trigger_arg_is(&cmd->stop_arg, 0);
3243
03aef4b6
DS		 3244 if (err)
3245 return 3;
3246
3247 /* step 4: fix up any arguments */
3248 if (cmd->scan_begin_src == TRIG_TIMER) {
3249 tmp = cmd->scan_begin_arg;
3250 cmd->scan_begin_arg =
0a85b6f0
MT		 3251 ni_timer_to_ns(dev, ni_ns_to_timer(dev,
3252 cmd->scan_begin_arg,
3253 cmd->
3254 flags &
3255 TRIG_ROUND_MASK));
03aef4b6
DS		 3256 if (tmp != cmd->scan_begin_arg)
3257 err++;
3258 }
3259 if (err)
3260 return 4;
3261
03aef4b6
DS		 3262 return 0;
3263}
3264
da91b269 3265static int ni_ao_reset(struct comedi_device *dev, struct comedi_subdevice *s)
03aef4b6 3266{
6293e357 3267 const struct ni_board_struct *board = comedi_board(dev);
0e05c552
HS		 3268 struct ni_private *devpriv = dev->private;
3269
2696fb57
BP		 3270 /* devpriv->ao0p=0x0000; */
3271 /* ni_writew(devpriv->ao0p,AO_Configuration); */
03aef4b6 3272
2696fb57
BP		 3273 /* devpriv->ao1p=AO_Channel(1); */
3274 /* ni_writew(devpriv->ao1p,AO_Configuration); */
03aef4b6
DS		 3275
3276 ni_release_ao_mite_channel(dev);
3277
3278 devpriv->stc_writew(dev, AO_Configuration_Start, Joint_Reset_Register);
3279 devpriv->stc_writew(dev, AO_Disarm, AO_Command_1_Register);
3280 ni_set_bits(dev, Interrupt_B_Enable_Register, ~0, 0);
3281 devpriv->stc_writew(dev, AO_BC_Source_Select, AO_Personal_Register);
3282 devpriv->stc_writew(dev, 0x3f98, Interrupt_B_Ack_Register);
3283 devpriv->stc_writew(dev, AO_BC_Source_Select | AO_UPDATE_Pulse_Width |
0a85b6f0 3284 AO_TMRDACWR_Pulse_Width, AO_Personal_Register);
03aef4b6
DS		 3285 devpriv->stc_writew(dev, 0, AO_Output_Control_Register);
3286 devpriv->stc_writew(dev, 0, AO_Start_Select_Register);
3287 devpriv->ao_cmd1 = 0;
3288 devpriv->stc_writew(dev, devpriv->ao_cmd1, AO_Command_1_Register);
3289 devpriv->ao_cmd2 = 0;
3290 devpriv->stc_writew(dev, devpriv->ao_cmd2, AO_Command_2_Register);
3291 devpriv->ao_mode1 = 0;
3292 devpriv->stc_writew(dev, devpriv->ao_mode1, AO_Mode_1_Register);
3293 devpriv->ao_mode2 = 0;
3294 devpriv->stc_writew(dev, devpriv->ao_mode2, AO_Mode_2_Register);
6293e357 3295 if (board->reg_type & ni_reg_m_series_mask)
03aef4b6
DS		 3296 devpriv->ao_mode3 = AO_Last_Gate_Disable;
3297 else
3298 devpriv->ao_mode3 = 0;
3299 devpriv->stc_writew(dev, devpriv->ao_mode3, AO_Mode_3_Register);
3300 devpriv->ao_trigger_select = 0;
3301 devpriv->stc_writew(dev, devpriv->ao_trigger_select,
0a85b6f0 3302 AO_Trigger_Select_Register);
6293e357 3303 if (board->reg_type & ni_reg_6xxx_mask) {
03aef4b6
DS		 3304 unsigned immediate_bits = 0;
3305 unsigned i;
bc461556 3306 for (i = 0; i < s->n_chan; ++i)
03aef4b6 3307 immediate_bits |= 1 << i;
03aef4b6
DS		 3308 ao_win_out(immediate_bits, AO_Immediate_671x);
3309 ao_win_out(CLEAR_WG, AO_Misc_611x);
3310 }
3311 devpriv->stc_writew(dev, AO_Configuration_End, Joint_Reset_Register);
3312
3313 return 0;
3314}
3315
2696fb57 3316/* digital io */
03aef4b6 3317
0a85b6f0
MT		 3318static int ni_dio_insn_config(struct comedi_device *dev,
3319 struct comedi_subdevice *s,
ddf62f2c
HS		 3320 struct comedi_insn *insn,
3321 unsigned int *data)
03aef4b6 3322{
0e05c552 3323 struct ni_private *devpriv = dev->private;
ddf62f2c 3324 int ret;
0e05c552 3325
ddf62f2c
HS		 3326 ret = comedi_dio_insn_config(dev, s, insn, data, 0);
3327 if (ret)
3328 return ret;
03aef4b6
DS		 3329
3330 devpriv->dio_control &= ~DIO_Pins_Dir_Mask;
3331 devpriv->dio_control |= DIO_Pins_Dir(s->io_bits);
3332 devpriv->stc_writew(dev, devpriv->dio_control, DIO_Control_Register);
3333
ddf62f2c 3334 return insn->n;
03aef4b6
DS		 3335}
3336
0a85b6f0
MT		 3337static int ni_dio_insn_bits(struct comedi_device *dev,
3338 struct comedi_subdevice *s,
6171667a
HS		 3339 struct comedi_insn *insn,
3340 unsigned int *data)
03aef4b6 3341{
0e05c552
HS		 3342 struct ni_private *devpriv = dev->private;
3343
6171667a
HS		 3344 /* Make sure we're not using the serial part of the dio */
3345 if ((data[0] & (DIO_SDIN | DIO_SDOUT)) && devpriv->serial_interval_ns)
3346 return -EBUSY;
03aef4b6 3347
6171667a 3348 if (comedi_dio_update_state(s, data)) {
03aef4b6
DS		 3349 devpriv->dio_output &= ~DIO_Parallel_Data_Mask;
3350 devpriv->dio_output |= DIO_Parallel_Data_Out(s->state);
3351 devpriv->stc_writew(dev, devpriv->dio_output,
0a85b6f0 3352 DIO_Output_Register);
03aef4b6 3353 }
6171667a 3354
03aef4b6
DS		 3355 data[1] = devpriv->stc_readw(dev, DIO_Parallel_Input_Register);
3356
a2714e3e 3357 return insn->n;
03aef4b6
DS		 3358}
3359
da91b269 3360static int ni_m_series_dio_insn_config(struct comedi_device *dev,
0a85b6f0
MT		 3361 struct comedi_subdevice *s,
3362 struct comedi_insn *insn,
3363 unsigned int *data)
03aef4b6 3364{
0e05c552 3365 struct ni_private *devpriv __maybe_unused = dev->private;
ddf62f2c 3366 int ret;
0e05c552 3367
ddf62f2c
HS		 3368 ret = comedi_dio_insn_config(dev, s, insn, data, 0);
3369 if (ret)
3370 return ret;
03aef4b6
DS		 3371
3372 ni_writel(s->io_bits, M_Offset_DIO_Direction);
3373
ddf62f2c 3374 return insn->n;
03aef4b6
DS		 3375}
3376
0a85b6f0
MT		 3377static int ni_m_series_dio_insn_bits(struct comedi_device *dev,
3378 struct comedi_subdevice *s,
3379 struct comedi_insn *insn,
3380 unsigned int *data)
03aef4b6 3381{
0e05c552
HS		 3382 struct ni_private *devpriv __maybe_unused = dev->private;
3383
6171667a 3384 if (comedi_dio_update_state(s, data))
03aef4b6 3385 ni_writel(s->state, M_Offset_Static_Digital_Output);
6171667a 3386
03aef4b6
DS		 3387 data[1] = ni_readl(M_Offset_Static_Digital_Input);
3388
a2714e3e 3389 return insn->n;
03aef4b6
DS		 3390}
3391
368c2dcd
HS		 3392static int ni_cdio_check_chanlist(struct comedi_device *dev,
3393 struct comedi_subdevice *s,
3394 struct comedi_cmd *cmd)
3395{
3396 int i;
3397
3398 for (i = 0; i < cmd->chanlist_len; ++i) {
3399 unsigned int chan = CR_CHAN(cmd->chanlist[i]);
3400
3401 if (chan != i)
3402 return -EINVAL;
3403 }
3404
3405 return 0;
3406}
3407
0a85b6f0
MT		 3408static int ni_cdio_cmdtest(struct comedi_device *dev,
3409 struct comedi_subdevice *s, struct comedi_cmd *cmd)
03aef4b6
DS		 3410{
3411 int err = 0;
3412 int tmp;
03aef4b6 3413
27020ffe 3414 /* Step 1 : check if triggers are trivially valid */
03aef4b6 3415
27020ffe
HS		 3416 err |= cfc_check_trigger_src(&cmd->start_src, TRIG_INT);
3417 err |= cfc_check_trigger_src(&cmd->scan_begin_src, TRIG_EXT);
3418 err |= cfc_check_trigger_src(&cmd->convert_src, TRIG_NOW);
3419 err |= cfc_check_trigger_src(&cmd->scan_end_src, TRIG_COUNT);
3420 err |= cfc_check_trigger_src(&cmd->stop_src, TRIG_NONE);
03aef4b6
DS		 3421
3422 if (err)
3423 return 1;
3424
27020ffe
HS		 3425 /* Step 2a : make sure trigger sources are unique */
3426 /* Step 2b : and mutually compatible */
03aef4b6
DS		 3427
3428 if (err)
3429 return 2;
3430
c3be5c7f 3431 /* Step 3: check if arguments are trivially valid */
03aef4b6 3432
c3be5c7f 3433 err |= cfc_check_trigger_arg_is(&cmd->start_arg, 0);
03aef4b6 3434
c3be5c7f
HS		 3435 tmp = cmd->scan_begin_arg;
3436 tmp &= CR_PACK_FLAGS(CDO_Sample_Source_Select_Mask, 0, 0, CR_INVERT);
3437 if (tmp != cmd->scan_begin_arg)
3438 err |= -EINVAL;
3439
3440 err |= cfc_check_trigger_arg_is(&cmd->convert_arg, 0);
3441 err |= cfc_check_trigger_arg_is(&cmd->scan_end_arg, cmd->chanlist_len);
3442 err |= cfc_check_trigger_arg_is(&cmd->stop_arg, 0);
03aef4b6
DS		 3443
3444 if (err)
3445 return 3;
3446
3447 /* step 4: fix up any arguments */
3448
3449 if (err)
3450 return 4;
3451
368c2dcd
HS		 3452 /* Step 5: check channel list if it exists */
3453 if (cmd->chanlist && cmd->chanlist_len > 0)
3454 err |= ni_cdio_check_chanlist(dev, s, cmd);
03aef4b6
DS		 3455
3456 if (err)
3457 return 5;
3458
3459 return 0;
3460}
3461
da91b269 3462static int ni_cdio_cmd(struct comedi_device *dev, struct comedi_subdevice *s)
03aef4b6 3463{
0e05c552 3464 struct ni_private *devpriv __maybe_unused = dev->private;
ea6d0d4c 3465 const struct comedi_cmd *cmd = &s->async->cmd;
03aef4b6
DS		 3466 unsigned cdo_mode_bits = CDO_FIFO_Mode_Bit | CDO_Halt_On_Error_Bit;
3467 int retval;
3468
3469 ni_writel(CDO_Reset_Bit, M_Offset_CDIO_Command);
3470 switch (cmd->scan_begin_src) {
3471 case TRIG_EXT:
3472 cdo_mode_bits |=
0a85b6f0
MT		 3473 CR_CHAN(cmd->scan_begin_arg) &
3474 CDO_Sample_Source_Select_Mask;
03aef4b6
DS		 3475 break;
3476 default:
3477 BUG();
3478 break;
3479 }
3480 if (cmd->scan_begin_arg & CR_INVERT)
3481 cdo_mode_bits |= CDO_Polarity_Bit;
3482 ni_writel(cdo_mode_bits, M_Offset_CDO_Mode);
3483 if (s->io_bits) {
3484 ni_writel(s->state, M_Offset_CDO_FIFO_Data);
3485 ni_writel(CDO_SW_Update_Bit, M_Offset_CDIO_Command);
3486 ni_writel(s->io_bits, M_Offset_CDO_Mask_Enable);
3487 } else {
3488 comedi_error(dev,
0a85b6f0 3489 "attempted to run digital output command with no lines configured as outputs");
03aef4b6
DS		 3490 return -EIO;
3491 }
3492 retval = ni_request_cdo_mite_channel(dev);
bc461556 3493 if (retval < 0)
03aef4b6 3494 return retval;
ebb657ba
HS		 3495
3496 s->async->inttrig = ni_cdo_inttrig;
3497
03aef4b6
DS		 3498 return 0;
3499}
3500
ebb657ba
HS		 3501static int ni_cdo_inttrig(struct comedi_device *dev,
3502 struct comedi_subdevice *s,
3503 unsigned int trig_num)
03aef4b6
DS		 3504{
3505#ifdef PCIDMA
0e05c552 3506 struct ni_private *devpriv = dev->private;
03aef4b6
DS		 3507 unsigned long flags;
3508#endif
ebb657ba 3509 struct comedi_cmd *cmd = &s->async->cmd;
03aef4b6
DS		 3510 int retval = 0;
3511 unsigned i;
ea12ac4f 3512 const unsigned timeout = 1000;
03aef4b6 3513
ebb657ba
HS		 3514 if (trig_num != cmd->start_arg)
3515 return -EINVAL;
3516
03aef4b6
DS		 3517 s->async->inttrig = NULL;
3518
3519 /* read alloc the entire buffer */
d13be55a 3520 comedi_buf_read_alloc(s, s->async->prealloc_bufsz);
03aef4b6
DS		 3521
3522#ifdef PCIDMA
5f74ea14 3523 spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
03aef4b6
DS		 3524 if (devpriv->cdo_mite_chan) {
3525 mite_prep_dma(devpriv->cdo_mite_chan, 32, 32);
3526 mite_dma_arm(devpriv->cdo_mite_chan);
3527 } else {
3528 comedi_error(dev, "BUG: no cdo mite channel?");
3529 retval = -EIO;
3530 }
5f74ea14 3531 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
03aef4b6
DS		 3532 if (retval < 0)
3533 return retval;
3534#endif
2696fb57
BP		 3535/*
3536* XXX not sure what interrupt C group does
3537* ni_writeb(Interrupt_Group_C_Enable_Bit,
3538* M_Offset_Interrupt_C_Enable); wait for dma to fill output fifo
3539*/
03aef4b6
DS		 3540 for (i = 0; i < timeout; ++i) {
3541 if (ni_readl(M_Offset_CDIO_Status) & CDO_FIFO_Full_Bit)
3542 break;
5f74ea14 3543 udelay(10);
03aef4b6
DS		 3544 }
3545 if (i == timeout) {
3546 comedi_error(dev, "dma failed to fill cdo fifo!");
3547 ni_cdio_cancel(dev, s);
3548 return -EIO;
3549 }
3550 ni_writel(CDO_Arm_Bit | CDO_Error_Interrupt_Enable_Set_Bit |
0a85b6f0
MT		 3551 CDO_Empty_FIFO_Interrupt_Enable_Set_Bit,
3552 M_Offset_CDIO_Command);
03aef4b6
DS		 3553 return retval;
3554}
3555
da91b269 3556static int ni_cdio_cancel(struct comedi_device *dev, struct comedi_subdevice *s)
03aef4b6 3557{
0e05c552
HS		 3558 struct ni_private *devpriv __maybe_unused = dev->private;
3559
03aef4b6 3560 ni_writel(CDO_Disarm_Bit | CDO_Error_Interrupt_Enable_Clear_Bit |
0a85b6f0
MT		 3561 CDO_Empty_FIFO_Interrupt_Enable_Clear_Bit |
3562 CDO_FIFO_Request_Interrupt_Enable_Clear_Bit,
3563 M_Offset_CDIO_Command);
2696fb57
BP		 3564/*
3565* XXX not sure what interrupt C group does ni_writeb(0,
3566* M_Offset_Interrupt_C_Enable);
3567*/
03aef4b6
DS		 3568 ni_writel(0, M_Offset_CDO_Mask_Enable);
3569 ni_release_cdo_mite_channel(dev);
3570 return 0;
3571}
3572
da91b269 3573static void handle_cdio_interrupt(struct comedi_device *dev)
03aef4b6 3574{
6293e357 3575 const struct ni_board_struct *board = comedi_board(dev);
0e05c552 3576 struct ni_private *devpriv __maybe_unused = dev->private;
03aef4b6 3577 unsigned cdio_status;
f9cd92eb 3578 struct comedi_subdevice *s = &dev->subdevices[NI_DIO_SUBDEV];
03aef4b6
DS		 3579#ifdef PCIDMA
3580 unsigned long flags;
3581#endif
3582
bc461556 3583 if ((board->reg_type & ni_reg_m_series_mask) == 0)
03aef4b6 3584 return;
03aef4b6 3585#ifdef PCIDMA
5f74ea14 3586 spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
03aef4b6
DS		 3587 if (devpriv->cdo_mite_chan) {
3588 unsigned cdo_mite_status =
0a85b6f0 3589 mite_get_status(devpriv->cdo_mite_chan);
03aef4b6
DS		 3590 if (cdo_mite_status & CHSR_LINKC) {
3591 writel(CHOR_CLRLC,
0a85b6f0
MT		 3592 devpriv->mite->mite_io_addr +
3593 MITE_CHOR(devpriv->cdo_mite_chan->channel));
03aef4b6 3594 }
1e575a9c 3595 mite_sync_output_dma(devpriv->cdo_mite_chan, s);
03aef4b6 3596 }
5f74ea14 3597 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
03aef4b6
DS		 3598#endif
3599
3600 cdio_status = ni_readl(M_Offset_CDIO_Status);
3601 if (cdio_status & (CDO_Overrun_Bit | CDO_Underflow_Bit)) {
b9ede315 3602 /* printk("cdio error: statux=0x%x\n", cdio_status); */
2696fb57 3603 ni_writel(CDO_Error_Interrupt_Confirm_Bit, M_Offset_CDIO_Command); /* XXX just guessing this is needed and does something useful */
03aef4b6
DS		 3604 s->async->events |= COMEDI_CB_OVERFLOW;
3605 }
3606 if (cdio_status & CDO_FIFO_Empty_Bit) {
b9ede315 3607 /* printk("cdio fifo empty\n"); */
03aef4b6 3608 ni_writel(CDO_Empty_FIFO_Interrupt_Enable_Clear_Bit,
0a85b6f0 3609 M_Offset_CDIO_Command);
b9ede315 3610 /* s->async->events |= COMEDI_CB_EOA; */
03aef4b6 3611 }
a21eacfe 3612 cfc_handle_events(dev, s);
03aef4b6
DS		 3613}
3614
0a85b6f0
MT		 3615static int ni_serial_insn_config(struct comedi_device *dev,
3616 struct comedi_subdevice *s,
3617 struct comedi_insn *insn, unsigned int *data)
03aef4b6 3618{
0e05c552 3619 struct ni_private *devpriv = dev->private;
03aef4b6
DS		 3620 int err = insn->n;
3621 unsigned char byte_out, byte_in = 0;
3622
3623 if (insn->n != 2)
3624 return -EINVAL;
3625
3626 switch (data[0]) {
3627 case INSN_CONFIG_SERIAL_CLOCK:
03aef4b6
DS		 3628 devpriv->serial_hw_mode = 1;
3629 devpriv->dio_control |= DIO_HW_Serial_Enable;
3630
3631 if (data[1] == SERIAL_DISABLED) {
3632 devpriv->serial_hw_mode = 0;
3633 devpriv->dio_control &= ~(DIO_HW_Serial_Enable |
0a85b6f0 3634 DIO_Software_Serial_Control);
03aef4b6
DS		 3635 data[1] = SERIAL_DISABLED;
3636 devpriv->serial_interval_ns = data[1];
3637 } else if (data[1] <= SERIAL_600NS) {
3638 /* Warning: this clock speed is too fast to reliably
3639 control SCXI. */
3640 devpriv->dio_control &= ~DIO_HW_Serial_Timebase;
3641 devpriv->clock_and_fout |= Slow_Internal_Timebase;
3642 devpriv->clock_and_fout &= ~DIO_Serial_Out_Divide_By_2;
3643 data[1] = SERIAL_600NS;
3644 devpriv->serial_interval_ns = data[1];
3645 } else if (data[1] <= SERIAL_1_2US) {
3646 devpriv->dio_control &= ~DIO_HW_Serial_Timebase;
3647 devpriv->clock_and_fout |= Slow_Internal_Timebase |
0a85b6f0 3648 DIO_Serial_Out_Divide_By_2;
03aef4b6
DS		 3649 data[1] = SERIAL_1_2US;
3650 devpriv->serial_interval_ns = data[1];
3651 } else if (data[1] <= SERIAL_10US) {
3652 devpriv->dio_control |= DIO_HW_Serial_Timebase;
3653 devpriv->clock_and_fout |= Slow_Internal_Timebase |
0a85b6f0 3654 DIO_Serial_Out_Divide_By_2;
03aef4b6
DS		 3655 /* Note: DIO_Serial_Out_Divide_By_2 only affects
3656 600ns/1.2us. If you turn divide_by_2 off with the
3657 slow clock, you will still get 10us, except then
3658 all your delays are wrong. */
3659 data[1] = SERIAL_10US;
3660 devpriv->serial_interval_ns = data[1];
3661 } else {
3662 devpriv->dio_control &= ~(DIO_HW_Serial_Enable |
0a85b6f0 3663 DIO_Software_Serial_Control);
03aef4b6
DS		 3664 devpriv->serial_hw_mode = 0;
3665 data[1] = (data[1] / 1000) * 1000;
3666 devpriv->serial_interval_ns = data[1];
3667 }
3668
3669 devpriv->stc_writew(dev, devpriv->dio_control,
0a85b6f0 3670 DIO_Control_Register);
03aef4b6 3671 devpriv->stc_writew(dev, devpriv->clock_and_fout,
0a85b6f0 3672 Clock_and_FOUT_Register);
03aef4b6
DS		 3673 return 1;
3674
3675 break;
3676
3677 case INSN_CONFIG_BIDIRECTIONAL_DATA:
3678
bc461556 3679 if (devpriv->serial_interval_ns == 0)
03aef4b6 3680 return -EINVAL;
03aef4b6
DS		 3681
3682 byte_out = data[1] & 0xFF;
3683
3684 if (devpriv->serial_hw_mode) {
3685 err = ni_serial_hw_readwrite8(dev, s, byte_out,
0a85b6f0 3686 &byte_in);
03aef4b6
DS		 3687 } else if (devpriv->serial_interval_ns > 0) {
3688 err = ni_serial_sw_readwrite8(dev, s, byte_out,
0a85b6f0 3689 &byte_in);
03aef4b6 3690 } else {
5f74ea14 3691 printk("ni_serial_insn_config: serial disabled!\n");
03aef4b6
DS		 3692 return -EINVAL;
3693 }
3694 if (err < 0)
3695 return err;
3696 data[1] = byte_in & 0xFF;
3697 return insn->n;
3698
3699 break;
3700 default:
3701 return -EINVAL;
3702 }
3703
3704}
3705
0a85b6f0
MT		 3706static int ni_serial_hw_readwrite8(struct comedi_device *dev,
3707 struct comedi_subdevice *s,
3708 unsigned char data_out,
3709 unsigned char *data_in)
03aef4b6 3710{
0e05c552 3711 struct ni_private *devpriv = dev->private;
03aef4b6
DS		 3712 unsigned int status1;
3713 int err = 0, count = 20;
3714
03aef4b6
DS		 3715 devpriv->dio_output &= ~DIO_Serial_Data_Mask;
3716 devpriv->dio_output |= DIO_Serial_Data_Out(data_out);
3717 devpriv->stc_writew(dev, devpriv->dio_output, DIO_Output_Register);
3718
3719 status1 = devpriv->stc_readw(dev, Joint_Status_1_Register);
3720 if (status1 & DIO_Serial_IO_In_Progress_St) {
3721 err = -EBUSY;
3722 goto Error;
3723 }
3724
3725 devpriv->dio_control |= DIO_HW_Serial_Start;
3726 devpriv->stc_writew(dev, devpriv->dio_control, DIO_Control_Register);
3727 devpriv->dio_control &= ~DIO_HW_Serial_Start;
3728
3729 /* Wait until STC says we're done, but don't loop infinitely. */
3730 while ((status1 =
0a85b6f0
MT		 3731 devpriv->stc_readw(dev,
3732 Joint_Status_1_Register)) &
3733 DIO_Serial_IO_In_Progress_St) {
03aef4b6 3734 /* Delay one bit per loop */
5f74ea14 3735 udelay((devpriv->serial_interval_ns + 999) / 1000);
03aef4b6 3736 if (--count < 0) {
5f74ea14 3737 printk
0a85b6f0 3738 ("ni_serial_hw_readwrite8: SPI serial I/O didn't finish in time!\n");
03aef4b6
DS		 3739 err = -ETIME;
3740 goto Error;
3741 }
3742 }
3743
3744 /* Delay for last bit. This delay is absolutely necessary, because
3745 DIO_Serial_IO_In_Progress_St goes high one bit too early. */
5f74ea14 3746 udelay((devpriv->serial_interval_ns + 999) / 1000);
03aef4b6 3747
9d6a0f6a 3748 if (data_in != NULL)
03aef4b6 3749 *data_in = devpriv->stc_readw(dev, DIO_Serial_Input_Register);
03aef4b6 3750
0a85b6f0 3751Error:
03aef4b6
DS		 3752 devpriv->stc_writew(dev, devpriv->dio_control, DIO_Control_Register);
3753
3754 return err;
3755}
3756
0a85b6f0
MT		 3757static int ni_serial_sw_readwrite8(struct comedi_device *dev,
3758 struct comedi_subdevice *s,
3759 unsigned char data_out,
3760 unsigned char *data_in)
03aef4b6 3761{
0e05c552 3762 struct ni_private *devpriv = dev->private;
03aef4b6
DS		 3763 unsigned char mask, input = 0;
3764
03aef4b6 3765 /* Wait for one bit before transfer */
5f74ea14 3766 udelay((devpriv->serial_interval_ns + 999) / 1000);
03aef4b6
DS		 3767
3768 for (mask = 0x80; mask; mask >>= 1) {
3769 /* Output current bit; note that we cannot touch s->state
3770 because it is a per-subdevice field, and serial is
3771 a separate subdevice from DIO. */
3772 devpriv->dio_output &= ~DIO_SDOUT;
bc461556 3773 if (data_out & mask)
03aef4b6 3774 devpriv->dio_output |= DIO_SDOUT;
03aef4b6 3775 devpriv->stc_writew(dev, devpriv->dio_output,
0a85b6f0 3776 DIO_Output_Register);
03aef4b6
DS		 3777
3778 /* Assert SDCLK (active low, inverted), wait for half of
3779 the delay, deassert SDCLK, and wait for the other half. */
3780 devpriv->dio_control |= DIO_Software_Serial_Control;
3781 devpriv->stc_writew(dev, devpriv->dio_control,
0a85b6f0 3782 DIO_Control_Register);
03aef4b6 3783
5f74ea14 3784 udelay((devpriv->serial_interval_ns + 999) / 2000);
03aef4b6
DS		 3785
3786 devpriv->dio_control &= ~DIO_Software_Serial_Control;
3787 devpriv->stc_writew(dev, devpriv->dio_control,
0a85b6f0 3788 DIO_Control_Register);
03aef4b6 3789
5f74ea14 3790 udelay((devpriv->serial_interval_ns + 999) / 2000);
03aef4b6
DS		 3791
3792 /* Input current bit */
3793 if (devpriv->stc_readw(dev,
bc461556 3794 DIO_Parallel_Input_Register) & DIO_SDIN) {
b9ede315 3795 /* printk("DIO_P_I_R: 0x%x\n", devpriv->stc_readw(dev, DIO_Parallel_Input_Register)); */
03aef4b6
DS		 3796 input |= mask;
3797 }
3798 }
9d6a0f6a 3799
03aef4b6
DS		 3800 if (data_in)
3801 *data_in = input;
3802
3803 return 0;
3804}
3805
da91b269 3806static void mio_common_detach(struct comedi_device *dev)
03aef4b6 3807{
0e05c552 3808 struct ni_private *devpriv = dev->private;
f9cd92eb 3809
0e05c552 3810 if (devpriv) {
bc461556 3811 if (devpriv->counter_dev)
03aef4b6 3812 ni_gpct_device_destroy(devpriv->counter_dev);
03aef4b6 3813 }
03aef4b6
DS		 3814}
3815
da91b269 3816static void init_ao_67xx(struct comedi_device *dev, struct comedi_subdevice *s)
03aef4b6
DS		 3817{
3818 int i;
3819
0a85b6f0 3820 for (i = 0; i < s->n_chan; i++) {
03aef4b6 3821 ni_ao_win_outw(dev, AO_Channel(i) | 0x0,
0a85b6f0 3822 AO_Configuration_2_67xx);
03aef4b6
DS		 3823 }
3824 ao_win_out(0x0, AO_Later_Single_Point_Updates);
3825}
3826
3827static unsigned ni_gpct_to_stc_register(enum ni_gpct_register reg)
3828{
3829 unsigned stc_register;
3830 switch (reg) {
12375292 3831 case NITIO_G0_AUTO_INC:
03aef4b6
DS		 3832 stc_register = G_Autoincrement_Register(0);
3833 break;
12375292 3834 case NITIO_G1_AUTO_INC:
03aef4b6
DS		 3835 stc_register = G_Autoincrement_Register(1);
3836 break;
12375292 3837 case NITIO_G0_CMD:
03aef4b6
DS		 3838 stc_register = G_Command_Register(0);
3839 break;
12375292 3840 case NITIO_G1_CMD:
03aef4b6
DS		 3841 stc_register = G_Command_Register(1);
3842 break;
12375292 3843 case NITIO_G0_HW_SAVE:
03aef4b6
DS		 3844 stc_register = G_HW_Save_Register(0);
3845 break;
12375292 3846 case NITIO_G1_HW_SAVE:
03aef4b6
DS		 3847 stc_register = G_HW_Save_Register(1);
3848 break;
12375292 3849 case NITIO_G0_SW_SAVE:
03aef4b6
DS		 3850 stc_register = G_Save_Register(0);
3851 break;
12375292 3852 case NITIO_G1_SW_SAVE:
03aef4b6
DS		 3853 stc_register = G_Save_Register(1);
3854 break;
12375292 3855 case NITIO_G0_MODE:
03aef4b6
DS		 3856 stc_register = G_Mode_Register(0);
3857 break;
12375292 3858 case NITIO_G1_MODE:
03aef4b6
DS		 3859 stc_register = G_Mode_Register(1);
3860 break;
12375292 3861 case NITIO_G0_LOADA:
03aef4b6
DS		 3862 stc_register = G_Load_A_Register(0);
3863 break;
12375292 3864 case NITIO_G1_LOADA:
03aef4b6
DS		 3865 stc_register = G_Load_A_Register(1);
3866 break;
12375292 3867 case NITIO_G0_LOADB:
03aef4b6
DS		 3868 stc_register = G_Load_B_Register(0);
3869 break;
12375292 3870 case NITIO_G1_LOADB:
03aef4b6
DS		 3871 stc_register = G_Load_B_Register(1);
3872 break;
12375292 3873 case NITIO_G0_INPUT_SEL:
03aef4b6
DS		 3874 stc_register = G_Input_Select_Register(0);
3875 break;
12375292 3876 case NITIO_G1_INPUT_SEL:
03aef4b6
DS		 3877 stc_register = G_Input_Select_Register(1);
3878 break;
12375292 3879 case NITIO_G01_STATUS:
03aef4b6
DS		 3880 stc_register = G_Status_Register;
3881 break;
12375292 3882 case NITIO_G01_RESET:
03aef4b6
DS		 3883 stc_register = Joint_Reset_Register;
3884 break;
12375292 3885 case NITIO_G01_STATUS1:
03aef4b6
DS		 3886 stc_register = Joint_Status_1_Register;
3887 break;
12375292 3888 case NITIO_G01_STATUS2:
03aef4b6
DS		 3889 stc_register = Joint_Status_2_Register;
3890 break;
12375292 3891 case NITIO_G0_INT_ACK:
03aef4b6
DS		 3892 stc_register = Interrupt_A_Ack_Register;
3893 break;
12375292 3894 case NITIO_G1_INT_ACK:
03aef4b6
DS		 3895 stc_register = Interrupt_B_Ack_Register;
3896 break;
12375292 3897 case NITIO_G0_STATUS:
03aef4b6
DS		 3898 stc_register = AI_Status_1_Register;
3899 break;
12375292 3900 case NITIO_G1_STATUS:
03aef4b6
DS		 3901 stc_register = AO_Status_1_Register;
3902 break;
12375292 3903 case NITIO_G0_INT_ENA:
03aef4b6
DS		 3904 stc_register = Interrupt_A_Enable_Register;
3905 break;
12375292 3906 case NITIO_G1_INT_ENA:
03aef4b6
DS		 3907 stc_register = Interrupt_B_Enable_Register;
3908 break;
3909 default:
5f74ea14 3910 printk("%s: unhandled register 0x%x in switch.\n",
0a85b6f0 3911 __func__, reg);
03aef4b6
DS		 3912 BUG();
3913 return 0;
3914 break;
3915 }
3916 return stc_register;
3917}
3918
3919static void ni_gpct_write_register(struct ni_gpct *counter, unsigned bits,
0a85b6f0 3920 enum ni_gpct_register reg)
03aef4b6 3921{
71b5f4f1 3922 struct comedi_device *dev = counter->counter_dev->dev;
0e05c552 3923 struct ni_private *devpriv = dev->private;
03aef4b6
DS		 3924 unsigned stc_register;
3925 /* bits in the join reset register which are relevant to counters */
3926 static const unsigned gpct_joint_reset_mask = G0_Reset | G1_Reset;
3927 static const unsigned gpct_interrupt_a_enable_mask =
0a85b6f0 3928 G0_Gate_Interrupt_Enable | G0_TC_Interrupt_Enable;
03aef4b6 3929 static const unsigned gpct_interrupt_b_enable_mask =
0a85b6f0 3930 G1_Gate_Interrupt_Enable | G1_TC_Interrupt_Enable;
03aef4b6
DS		 3931
3932 switch (reg) {
3933 /* m-series-only registers */
12375292 3934 case NITIO_G0_CNT_MODE:
03aef4b6
DS		 3935 ni_writew(bits, M_Offset_G0_Counting_Mode);
3936 break;
12375292 3937 case NITIO_G1_CNT_MODE:
03aef4b6
DS		 3938 ni_writew(bits, M_Offset_G1_Counting_Mode);
3939 break;
12375292 3940 case NITIO_G0_GATE2:
03aef4b6
DS		 3941 ni_writew(bits, M_Offset_G0_Second_Gate);
3942 break;
12375292 3943 case NITIO_G1_GATE2:
03aef4b6
DS		 3944 ni_writew(bits, M_Offset_G1_Second_Gate);
3945 break;
12375292 3946 case NITIO_G0_DMA_CFG:
03aef4b6
DS		 3947 ni_writew(bits, M_Offset_G0_DMA_Config);
3948 break;
12375292 3949 case NITIO_G1_DMA_CFG:
03aef4b6
DS		 3950 ni_writew(bits, M_Offset_G1_DMA_Config);
3951 break;
12375292 3952 case NITIO_G0_ABZ:
03aef4b6
DS		 3953 ni_writew(bits, M_Offset_G0_MSeries_ABZ);
3954 break;
12375292 3955 case NITIO_G1_ABZ:
03aef4b6
DS		 3956 ni_writew(bits, M_Offset_G1_MSeries_ABZ);
3957 break;
3958
3959 /* 32 bit registers */
12375292
HS		 3960 case NITIO_G0_LOADA:
3961 case NITIO_G1_LOADA:
3962 case NITIO_G0_LOADB:
3963 case NITIO_G1_LOADB:
03aef4b6
DS		 3964 stc_register = ni_gpct_to_stc_register(reg);
3965 devpriv->stc_writel(dev, bits, stc_register);
3966 break;
3967
3968 /* 16 bit registers */
12375292 3969 case NITIO_G0_INT_ENA:
03aef4b6
DS		 3970 BUG_ON(bits & ~gpct_interrupt_a_enable_mask);
3971 ni_set_bitfield(dev, Interrupt_A_Enable_Register,
0a85b6f0 3972 gpct_interrupt_a_enable_mask, bits);
03aef4b6 3973 break;
12375292 3974 case NITIO_G1_INT_ENA:
03aef4b6
DS		 3975 BUG_ON(bits & ~gpct_interrupt_b_enable_mask);
3976 ni_set_bitfield(dev, Interrupt_B_Enable_Register,
0a85b6f0 3977 gpct_interrupt_b_enable_mask, bits);
03aef4b6 3978 break;
12375292 3979 case NITIO_G01_RESET:
03aef4b6
DS		 3980 BUG_ON(bits & ~gpct_joint_reset_mask);
3981 /* fall-through */
3982 default:
3983 stc_register = ni_gpct_to_stc_register(reg);
3984 devpriv->stc_writew(dev, bits, stc_register);
3985 }
3986}
3987
3988static unsigned ni_gpct_read_register(struct ni_gpct *counter,
0a85b6f0 3989 enum ni_gpct_register reg)
03aef4b6 3990{
71b5f4f1 3991 struct comedi_device *dev = counter->counter_dev->dev;
0e05c552 3992 struct ni_private *devpriv = dev->private;
03aef4b6 3993 unsigned stc_register;
0e05c552 3994
03aef4b6
DS		 3995 switch (reg) {
3996 /* m-series only registers */
12375292 3997 case NITIO_G0_DMA_STATUS:
03aef4b6 3998 return ni_readw(M_Offset_G0_DMA_Status);
12375292 3999 case NITIO_G1_DMA_STATUS:
03aef4b6 4000 return ni_readw(M_Offset_G1_DMA_Status);
03aef4b6
DS		 4001
4002 /* 32 bit registers */
12375292
HS		 4003 case NITIO_G0_HW_SAVE:
4004 case NITIO_G1_HW_SAVE:
4005 case NITIO_G0_SW_SAVE:
4006 case NITIO_G1_SW_SAVE:
03aef4b6
DS		 4007 stc_register = ni_gpct_to_stc_register(reg);
4008 return devpriv->stc_readl(dev, stc_register);
03aef4b6
DS		 4009
4010 /* 16 bit registers */
4011 default:
4012 stc_register = ni_gpct_to_stc_register(reg);
4013 return devpriv->stc_readw(dev, stc_register);
4014 break;
4015 }
4016 return 0;
4017}
4018
da91b269 4019static int ni_freq_out_insn_read(struct comedi_device *dev,
0a85b6f0
MT		 4020 struct comedi_subdevice *s,
4021 struct comedi_insn *insn, unsigned int *data)
03aef4b6 4022{
0e05c552
HS		 4023 struct ni_private *devpriv = dev->private;
4024
03aef4b6
DS		 4025 data[0] = devpriv->clock_and_fout & FOUT_Divider_mask;
4026 return 1;
4027}
4028
da91b269 4029static int ni_freq_out_insn_write(struct comedi_device *dev,
0a85b6f0
MT		 4030 struct comedi_subdevice *s,
4031 struct comedi_insn *insn, unsigned int *data)
03aef4b6 4032{
0e05c552
HS		 4033 struct ni_private *devpriv = dev->private;
4034
03aef4b6
DS		 4035 devpriv->clock_and_fout &= ~FOUT_Enable;
4036 devpriv->stc_writew(dev, devpriv->clock_and_fout,
0a85b6f0 4037 Clock_and_FOUT_Register);
03aef4b6
DS		 4038 devpriv->clock_and_fout &= ~FOUT_Divider_mask;
4039 devpriv->clock_and_fout |= FOUT_Divider(data[0]);
4040 devpriv->clock_and_fout |= FOUT_Enable;
4041 devpriv->stc_writew(dev, devpriv->clock_and_fout,
0a85b6f0 4042 Clock_and_FOUT_Register);
03aef4b6
DS		 4043 return insn->n;
4044}
4045
0a85b6f0
MT		 4046static int ni_set_freq_out_clock(struct comedi_device *dev,
4047 unsigned int clock_source)
03aef4b6 4048{
0e05c552
HS		 4049 struct ni_private *devpriv = dev->private;
4050
03aef4b6
DS		 4051 switch (clock_source) {
4052 case NI_FREQ_OUT_TIMEBASE_1_DIV_2_CLOCK_SRC:
4053 devpriv->clock_and_fout &= ~FOUT_Timebase_Select;
4054 break;
4055 case NI_FREQ_OUT_TIMEBASE_2_CLOCK_SRC:
4056 devpriv->clock_and_fout |= FOUT_Timebase_Select;
4057 break;
4058 default:
4059 return -EINVAL;
4060 }
4061 devpriv->stc_writew(dev, devpriv->clock_and_fout,
0a85b6f0 4062 Clock_and_FOUT_Register);
03aef4b6
DS		 4063 return 3;
4064}
4065
0a85b6f0
MT		 4066static void ni_get_freq_out_clock(struct comedi_device *dev,
4067 unsigned int *clock_source,
4068 unsigned int *clock_period_ns)
03aef4b6 4069{
0e05c552
HS		 4070 struct ni_private *devpriv = dev->private;
4071
03aef4b6
DS		 4072 if (devpriv->clock_and_fout & FOUT_Timebase_Select) {
4073 *clock_source = NI_FREQ_OUT_TIMEBASE_2_CLOCK_SRC;
4074 *clock_period_ns = TIMEBASE_2_NS;
4075 } else {
4076 *clock_source = NI_FREQ_OUT_TIMEBASE_1_DIV_2_CLOCK_SRC;
4077 *clock_period_ns = TIMEBASE_1_NS * 2;
4078 }
4079}
4080
0a85b6f0
MT		 4081static int ni_freq_out_insn_config(struct comedi_device *dev,
4082 struct comedi_subdevice *s,
4083 struct comedi_insn *insn, unsigned int *data)
03aef4b6
DS		 4084{
4085 switch (data[0]) {
4086 case INSN_CONFIG_SET_CLOCK_SRC:
4087 return ni_set_freq_out_clock(dev, data[1]);
4088 break;
4089 case INSN_CONFIG_GET_CLOCK_SRC:
4090 ni_get_freq_out_clock(dev, &data[1], &data[2]);
4091 return 3;
4092 default:
4093 break;
4094 }
4095 return -EINVAL;
4096}
4097
da91b269 4098static int ni_alloc_private(struct comedi_device *dev)
03aef4b6 4099{
0e05c552 4100 struct ni_private *devpriv;
03aef4b6 4101
0bdab509 4102 devpriv = comedi_alloc_devpriv(dev, sizeof(*devpriv));
c34fa261
HS		 4103 if (!devpriv)
4104 return -ENOMEM;
03aef4b6
DS		 4105
4106 spin_lock_init(&devpriv->window_lock);
4107 spin_lock_init(&devpriv->soft_reg_copy_lock);
4108 spin_lock_init(&devpriv->mite_channel_lock);
4109
4110 return 0;
4111};
4112
f5985867
HS		 4113static int ni_8255_callback(int dir, int port, int data, unsigned long arg)
4114{
4115 struct comedi_device *dev = (struct comedi_device *)arg;
4116 struct ni_private *devpriv __maybe_unused = dev->private;
4117
4118 if (dir) {
4119 ni_writeb(data, Port_A + 2 * port);
4120 return 0;
4121 } else {
4122 return ni_readb(Port_A + 2 * port);
4123 }
4124}
4125
1e49c5da
HS		 4126static int ni_get_pwm_config(struct comedi_device *dev, unsigned int *data)
4127{
4128 struct ni_private *devpriv = dev->private;
4129
4130 data[1] = devpriv->pwm_up_count * devpriv->clock_ns;
4131 data[2] = devpriv->pwm_down_count * devpriv->clock_ns;
4132 return 3;
4133}
4134
4135static int ni_m_series_pwm_config(struct comedi_device *dev,
4136 struct comedi_subdevice *s,
4137 struct comedi_insn *insn,
4138 unsigned int *data)
4139{
4140 struct ni_private *devpriv = dev->private;
4141 unsigned up_count, down_count;
4142
4143 switch (data[0]) {
4144 case INSN_CONFIG_PWM_OUTPUT:
4145 switch (data[1]) {
4146 case TRIG_ROUND_NEAREST:
4147 up_count =
4148 (data[2] +
4149 devpriv->clock_ns / 2) / devpriv->clock_ns;
4150 break;
4151 case TRIG_ROUND_DOWN:
4152 up_count = data[2] / devpriv->clock_ns;
4153 break;
4154 case TRIG_ROUND_UP:
4155 up_count =
4156 (data[2] + devpriv->clock_ns -
4157 1) / devpriv->clock_ns;
4158 break;
4159 default:
4160 return -EINVAL;
4161 break;
4162 }
4163 switch (data[3]) {
4164 case TRIG_ROUND_NEAREST:
4165 down_count =
4166 (data[4] +
4167 devpriv->clock_ns / 2) / devpriv->clock_ns;
4168 break;
4169 case TRIG_ROUND_DOWN:
4170 down_count = data[4] / devpriv->clock_ns;
4171 break;
4172 case TRIG_ROUND_UP:
4173 down_count =
4174 (data[4] + devpriv->clock_ns -
4175 1) / devpriv->clock_ns;
4176 break;
4177 default:
4178 return -EINVAL;
4179 break;
4180 }
4181 if (up_count * devpriv->clock_ns != data[2] ||
4182 down_count * devpriv->clock_ns != data[4]) {
4183 data[2] = up_count * devpriv->clock_ns;
4184 data[4] = down_count * devpriv->clock_ns;
4185 return -EAGAIN;
4186 }
4187 ni_writel(MSeries_Cal_PWM_High_Time_Bits(up_count) |
4188 MSeries_Cal_PWM_Low_Time_Bits(down_count),
4189 M_Offset_Cal_PWM);
4190 devpriv->pwm_up_count = up_count;
4191 devpriv->pwm_down_count = down_count;
4192 return 5;
4193 break;
4194 case INSN_CONFIG_GET_PWM_OUTPUT:
4195 return ni_get_pwm_config(dev, data);
4196 break;
4197 default:
4198 return -EINVAL;
4199 break;
4200 }
4201 return 0;
4202}
4203
4204static int ni_6143_pwm_config(struct comedi_device *dev,
4205 struct comedi_subdevice *s,
4206 struct comedi_insn *insn,
4207 unsigned int *data)
4208{
4209 struct ni_private *devpriv = dev->private;
4210 unsigned up_count, down_count;
4211
4212 switch (data[0]) {
4213 case INSN_CONFIG_PWM_OUTPUT:
4214 switch (data[1]) {
4215 case TRIG_ROUND_NEAREST:
4216 up_count =
4217 (data[2] +
4218 devpriv->clock_ns / 2) / devpriv->clock_ns;
4219 break;
4220 case TRIG_ROUND_DOWN:
4221 up_count = data[2] / devpriv->clock_ns;
4222 break;
4223 case TRIG_ROUND_UP:
4224 up_count =
4225 (data[2] + devpriv->clock_ns -
4226 1) / devpriv->clock_ns;
4227 break;
4228 default:
4229 return -EINVAL;
4230 break;
4231 }
4232 switch (data[3]) {
4233 case TRIG_ROUND_NEAREST:
4234 down_count =
4235 (data[4] +
4236 devpriv->clock_ns / 2) / devpriv->clock_ns;
4237 break;
4238 case TRIG_ROUND_DOWN:
4239 down_count = data[4] / devpriv->clock_ns;
4240 break;
4241 case TRIG_ROUND_UP:
4242 down_count =
4243 (data[4] + devpriv->clock_ns -
4244 1) / devpriv->clock_ns;
4245 break;
4246 default:
4247 return -EINVAL;
4248 break;
4249 }
4250 if (up_count * devpriv->clock_ns != data[2] ||
4251 down_count * devpriv->clock_ns != data[4]) {
4252 data[2] = up_count * devpriv->clock_ns;
4253 data[4] = down_count * devpriv->clock_ns;
4254 return -EAGAIN;
4255 }
4256 ni_writel(up_count, Calibration_HighTime_6143);
4257 devpriv->pwm_up_count = up_count;
4258 ni_writel(down_count, Calibration_LowTime_6143);
4259 devpriv->pwm_down_count = down_count;
4260 return 5;
4261 break;
4262 case INSN_CONFIG_GET_PWM_OUTPUT:
4263 return ni_get_pwm_config(dev, data);
4264 default:
4265 return -EINVAL;
4266 break;
4267 }
4268 return 0;
4269}
4270
62c2bce0
HS		 4271static int pack_mb88341(int addr, int val, int *bitstring)
4272{
4273 /*
4274 Fujitsu MB 88341
4275 Note that address bits are reversed. Thanks to
4276 Ingo Keen for noticing this.
4277
4278 Note also that the 88341 expects address values from
4279 1-12, whereas we use channel numbers 0-11. The NI
4280 docs use 1-12, also, so be careful here.
4281 */
4282 addr++;
4283 *bitstring = ((addr & 0x1) << 11) |
4284 ((addr & 0x2) << 9) |
4285 ((addr & 0x4) << 7) | ((addr & 0x8) << 5) | (val & 0xff);
4286 return 12;
4287}
4288
4289static int pack_dac8800(int addr, int val, int *bitstring)
4290{
4291 *bitstring = ((addr & 0x7) << 8) | (val & 0xff);
4292 return 11;
4293}
4294
4295static int pack_dac8043(int addr, int val, int *bitstring)
4296{
4297 *bitstring = val & 0xfff;
4298 return 12;
4299}
4300
4301static int pack_ad8522(int addr, int val, int *bitstring)
4302{
4303 *bitstring = (val & 0xfff) | (addr ? 0xc000 : 0xa000);
4304 return 16;
4305}
4306
4307static int pack_ad8804(int addr, int val, int *bitstring)
4308{
4309 *bitstring = ((addr & 0xf) << 8) | (val & 0xff);
4310 return 12;
4311}
4312
4313static int pack_ad8842(int addr, int val, int *bitstring)
4314{
4315 *bitstring = ((addr + 1) << 8) | (val & 0xff);
4316 return 12;
4317}
4318
4319struct caldac_struct {
4320 int n_chans;
4321 int n_bits;
4322 int (*packbits)(int, int, int *);
4323};
4324
4325static struct caldac_struct caldacs[] = {
4326 [mb88341] = {12, 8, pack_mb88341},
4327 [dac8800] = {8, 8, pack_dac8800},
4328 [dac8043] = {1, 12, pack_dac8043},
4329 [ad8522] = {2, 12, pack_ad8522},
4330 [ad8804] = {12, 8, pack_ad8804},
4331 [ad8842] = {8, 8, pack_ad8842},
4332 [ad8804_debug] = {16, 8, pack_ad8804},
4333};
4334
4335static void ni_write_caldac(struct comedi_device *dev, int addr, int val)
4336{
4337 const struct ni_board_struct *board = comedi_board(dev);
4338 struct ni_private *devpriv = dev->private;
4339 unsigned int loadbit = 0, bits = 0, bit, bitstring = 0;
4340 int i;
4341 int type;
4342
4343 /* printk("ni_write_caldac: chan=%d val=%d\n",addr,val); */
4344 if (devpriv->caldacs[addr] == val)
4345 return;
4346 devpriv->caldacs[addr] = val;
4347
4348 for (i = 0; i < 3; i++) {
4349 type = board->caldac[i];
4350 if (type == caldac_none)
4351 break;
4352 if (addr < caldacs[type].n_chans) {
4353 bits = caldacs[type].packbits(addr, val, &bitstring);
4354 loadbit = SerDacLd(i);
4355 /* printk("caldac: using i=%d addr=%d %x\n",i,addr,bitstring); */
4356 break;
4357 }
4358 addr -= caldacs[type].n_chans;
4359 }
4360
4361 for (bit = 1 << (bits - 1); bit; bit >>= 1) {
4362 ni_writeb(((bit & bitstring) ? 0x02 : 0), Serial_Command);
4363 udelay(1);
4364 ni_writeb(1 | ((bit & bitstring) ? 0x02 : 0), Serial_Command);
4365 udelay(1);
4366 }
4367 ni_writeb(loadbit, Serial_Command);
4368 udelay(1);
4369 ni_writeb(0, Serial_Command);
4370}
4371
4372static int ni_calib_insn_write(struct comedi_device *dev,
4373 struct comedi_subdevice *s,
4374 struct comedi_insn *insn,
4375 unsigned int *data)
4376{
4377 ni_write_caldac(dev, CR_CHAN(insn->chanspec), data[0]);
4378
4379 return 1;
4380}
4381
4382static int ni_calib_insn_read(struct comedi_device *dev,
4383 struct comedi_subdevice *s,
4384 struct comedi_insn *insn,
4385 unsigned int *data)
4386{
4387 struct ni_private *devpriv = dev->private;
4388
4389 data[0] = devpriv->caldacs[CR_CHAN(insn->chanspec)];
4390
4391 return 1;
4392}
4393
4394static void caldac_setup(struct comedi_device *dev, struct comedi_subdevice *s)
4395{
4396 const struct ni_board_struct *board = comedi_board(dev);
4397 struct ni_private *devpriv = dev->private;
4398 int i, j;
4399 int n_dacs;
4400 int n_chans = 0;
4401 int n_bits;
4402 int diffbits = 0;
4403 int type;
4404 int chan;
4405
4406 type = board->caldac[0];
4407 if (type == caldac_none)
4408 return;
4409 n_bits = caldacs[type].n_bits;
4410 for (i = 0; i < 3; i++) {
4411 type = board->caldac[i];
4412 if (type == caldac_none)
4413 break;
4414 if (caldacs[type].n_bits != n_bits)
4415 diffbits = 1;
4416 n_chans += caldacs[type].n_chans;
4417 }
4418 n_dacs = i;
4419 s->n_chan = n_chans;
4420
4421 if (diffbits) {
4422 unsigned int *maxdata_list;
4423
4424 if (n_chans > MAX_N_CALDACS)
4425 printk("BUG! MAX_N_CALDACS too small\n");
4426 s->maxdata_list = maxdata_list = devpriv->caldac_maxdata_list;
4427 chan = 0;
4428 for (i = 0; i < n_dacs; i++) {
4429 type = board->caldac[i];
4430 for (j = 0; j < caldacs[type].n_chans; j++) {
4431 maxdata_list[chan] =
4432 (1 << caldacs[type].n_bits) - 1;
4433 chan++;
4434 }
4435 }
4436
4437 for (chan = 0; chan < s->n_chan; chan++)
4438 ni_write_caldac(dev, i, s->maxdata_list[i] / 2);
4439 } else {
4440 type = board->caldac[0];
4441 s->maxdata = (1 << caldacs[type].n_bits) - 1;
4442
4443 for (chan = 0; chan < s->n_chan; chan++)
4444 ni_write_caldac(dev, i, s->maxdata / 2);
4445 }
4446}
4447
36adeee1
HS		 4448static int ni_read_eeprom(struct comedi_device *dev, int addr)
4449{
4450 struct ni_private *devpriv __maybe_unused = dev->private;
4451 int bit;
4452 int bitstring;
4453
4454 bitstring = 0x0300 | ((addr & 0x100) << 3) | (addr & 0xff);
4455 ni_writeb(0x04, Serial_Command);
4456 for (bit = 0x8000; bit; bit >>= 1) {
4457 ni_writeb(0x04 | ((bit & bitstring) ? 0x02 : 0),
4458 Serial_Command);
4459 ni_writeb(0x05 | ((bit & bitstring) ? 0x02 : 0),
4460 Serial_Command);
4461 }
4462 bitstring = 0;
4463 for (bit = 0x80; bit; bit >>= 1) {
4464 ni_writeb(0x04, Serial_Command);
4465 ni_writeb(0x05, Serial_Command);
4466 bitstring |= ((ni_readb(XXX_Status) & PROMOUT) ? bit : 0);
4467 }
4468 ni_writeb(0x00, Serial_Command);
4469
4470 return bitstring;
4471}
4472
4473static int ni_eeprom_insn_read(struct comedi_device *dev,
4474 struct comedi_subdevice *s,
4475 struct comedi_insn *insn,
4476 unsigned int *data)
4477{
4478 data[0] = ni_read_eeprom(dev, CR_CHAN(insn->chanspec));
4479
4480 return 1;
4481}
4482
4483static int ni_m_series_eeprom_insn_read(struct comedi_device *dev,
4484 struct comedi_subdevice *s,
4485 struct comedi_insn *insn,
4486 unsigned int *data)
4487{
4488 struct ni_private *devpriv = dev->private;
4489
4490 data[0] = devpriv->eeprom_buffer[CR_CHAN(insn->chanspec)];
4491
4492 return 1;
4493}
4494
4187a79a
HS		 4495static unsigned ni_old_get_pfi_routing(struct comedi_device *dev,
4496 unsigned chan)
4497{
4498 /* pre-m-series boards have fixed signals on pfi pins */
4499 switch (chan) {
4500 case 0:
4501 return NI_PFI_OUTPUT_AI_START1;
4502 break;
4503 case 1:
4504 return NI_PFI_OUTPUT_AI_START2;
4505 break;
4506 case 2:
4507 return NI_PFI_OUTPUT_AI_CONVERT;
4508 break;
4509 case 3:
4510 return NI_PFI_OUTPUT_G_SRC1;
4511 break;
4512 case 4:
4513 return NI_PFI_OUTPUT_G_GATE1;
4514 break;
4515 case 5:
4516 return NI_PFI_OUTPUT_AO_UPDATE_N;
4517 break;
4518 case 6:
4519 return NI_PFI_OUTPUT_AO_START1;
4520 break;
4521 case 7:
4522 return NI_PFI_OUTPUT_AI_START_PULSE;
4523 break;
4524 case 8:
4525 return NI_PFI_OUTPUT_G_SRC0;
4526 break;
4527 case 9:
4528 return NI_PFI_OUTPUT_G_GATE0;
4529 break;
4530 default:
4531 printk("%s: bug, unhandled case in switch.\n", __func__);
4532 break;
4533 }
4534 return 0;
4535}
4536
4537static int ni_old_set_pfi_routing(struct comedi_device *dev,
4538 unsigned chan, unsigned source)
4539{
4540 /* pre-m-series boards have fixed signals on pfi pins */
4541 if (source != ni_old_get_pfi_routing(dev, chan))
4542 return -EINVAL;
4543 return 2;
4544}
4545
4546static unsigned ni_m_series_get_pfi_routing(struct comedi_device *dev,
4547 unsigned chan)
4548{
4549 struct ni_private *devpriv = dev->private;
4550 const unsigned array_offset = chan / 3;
4551
4552 return MSeries_PFI_Output_Select_Source(chan,
4553 devpriv->pfi_output_select_reg[array_offset]);
4554}
4555
4556static int ni_m_series_set_pfi_routing(struct comedi_device *dev,
4557 unsigned chan, unsigned source)
4558{
4559 struct ni_private *devpriv = dev->private;
4560 unsigned pfi_reg_index;
4561 unsigned array_offset;
4562
4563 if ((source & 0x1f) != source)
4564 return -EINVAL;
4565 pfi_reg_index = 1 + chan / 3;
4566 array_offset = pfi_reg_index - 1;
4567 devpriv->pfi_output_select_reg[array_offset] &=
4568 ~MSeries_PFI_Output_Select_Mask(chan);
4569 devpriv->pfi_output_select_reg[array_offset] |=
4570 MSeries_PFI_Output_Select_Bits(chan, source);
4571 ni_writew(devpriv->pfi_output_select_reg[array_offset],
4572 M_Offset_PFI_Output_Select(pfi_reg_index));
4573 return 2;
4574}
4575
4576static unsigned ni_get_pfi_routing(struct comedi_device *dev, unsigned chan)
4577{
4578 const struct ni_board_struct *board = comedi_board(dev);
4579
4580 if (board->reg_type & ni_reg_m_series_mask)
4581 return ni_m_series_get_pfi_routing(dev, chan);
4582 else
4583 return ni_old_get_pfi_routing(dev, chan);
4584}
4585
4586static int ni_set_pfi_routing(struct comedi_device *dev, unsigned chan,
4587 unsigned source)
4588{
4589 const struct ni_board_struct *board = comedi_board(dev);
4590
4591 if (board->reg_type & ni_reg_m_series_mask)
4592 return ni_m_series_set_pfi_routing(dev, chan, source);
4593 else
4594 return ni_old_set_pfi_routing(dev, chan, source);
4595}
4596
4597static int ni_config_filter(struct comedi_device *dev,
4598 unsigned pfi_channel,
4599 enum ni_pfi_filter_select filter)
4600{
4601 const struct ni_board_struct *board = comedi_board(dev);
4602 struct ni_private *devpriv __maybe_unused = dev->private;
4603 unsigned bits;
4604
4605 if ((board->reg_type & ni_reg_m_series_mask) == 0)
4606 return -ENOTSUPP;
4607 bits = ni_readl(M_Offset_PFI_Filter);
4608 bits &= ~MSeries_PFI_Filter_Select_Mask(pfi_channel);
4609 bits |= MSeries_PFI_Filter_Select_Bits(pfi_channel, filter);
4610 ni_writel(bits, M_Offset_PFI_Filter);
4611 return 0;
4612}
4613
4614static int ni_pfi_insn_config(struct comedi_device *dev,
4615 struct comedi_subdevice *s,
4616 struct comedi_insn *insn,
4617 unsigned int *data)
4618{
4619 struct ni_private *devpriv = dev->private;
4620 unsigned int chan;
4621
4622 if (insn->n < 1)
4623 return -EINVAL;
4624
4625 chan = CR_CHAN(insn->chanspec);
4626
4627 switch (data[0]) {
4628 case COMEDI_OUTPUT:
4629 ni_set_bits(dev, IO_Bidirection_Pin_Register, 1 << chan, 1);
4630 break;
4631 case COMEDI_INPUT:
4632 ni_set_bits(dev, IO_Bidirection_Pin_Register, 1 << chan, 0);
4633 break;
4634 case INSN_CONFIG_DIO_QUERY:
4635 data[1] =
4636 (devpriv->io_bidirection_pin_reg & (1 << chan)) ?
4637 COMEDI_OUTPUT : COMEDI_INPUT;
4638 return 0;
4639 break;
4640 case INSN_CONFIG_SET_ROUTING:
4641 return ni_set_pfi_routing(dev, chan, data[1]);
4642 break;
4643 case INSN_CONFIG_GET_ROUTING:
4644 data[1] = ni_get_pfi_routing(dev, chan);
4645 break;
4646 case INSN_CONFIG_FILTER:
4647 return ni_config_filter(dev, chan, data[1]);
4648 break;
4649 default:
4650 return -EINVAL;
4651 }
4652 return 0;
4653}
4654
4655static int ni_pfi_insn_bits(struct comedi_device *dev,
4656 struct comedi_subdevice *s,
4657 struct comedi_insn *insn,
4658 unsigned int *data)
4659{
4660 const struct ni_board_struct *board = comedi_board(dev);
4661 struct ni_private *devpriv __maybe_unused = dev->private;
4662
4663 if (!(board->reg_type & ni_reg_m_series_mask))
4664 return -ENOTSUPP;
4665
4666 if (comedi_dio_update_state(s, data))
4667 ni_writew(s->state, M_Offset_PFI_DO);
4668
4669 data[1] = ni_readw(M_Offset_PFI_DI);
4670
4671 return insn->n;
4672}
4673
24e7c352
HS		 4674static int cs5529_wait_for_idle(struct comedi_device *dev)
4675{
4676 unsigned short status;
4677 const int timeout = HZ;
4678 int i;
4679
4680 for (i = 0; i < timeout; i++) {
4681 status = ni_ao_win_inw(dev, CAL_ADC_Status_67xx);
4682 if ((status & CSS_ADC_BUSY) == 0)
4683 break;
4684 set_current_state(TASK_INTERRUPTIBLE);
4685 if (schedule_timeout(1))
4686 return -EIO;
4687 }
4688/* printk("looped %i times waiting for idle\n", i); */
4689 if (i == timeout) {
4690 printk("%s: %s: timeout\n", __FILE__, __func__);
4691 return -ETIME;
4692 }
4693 return 0;
4694}
4695
4696static void cs5529_command(struct comedi_device *dev, unsigned short value)
4697{
4698 static const int timeout = 100;
4699 int i;
4700
4701 ni_ao_win_outw(dev, value, CAL_ADC_Command_67xx);
4702 /* give time for command to start being serially clocked into cs5529.
4703 * this insures that the CSS_ADC_BUSY bit will get properly
4704 * set before we exit this function.
4705 */
4706 for (i = 0; i < timeout; i++) {
4707 if ((ni_ao_win_inw(dev, CAL_ADC_Status_67xx) & CSS_ADC_BUSY))
4708 break;
4709 udelay(1);
4710 }
4711/* printk("looped %i times writing command to cs5529\n", i); */
4712 if (i == timeout)
4713 comedi_error(dev, "possible problem - never saw adc go busy?");
4714}
4715
4716static int cs5529_do_conversion(struct comedi_device *dev,
4717 unsigned short *data)
4718{
4719 int retval;
4720 unsigned short status;
4721
4722 cs5529_command(dev, CSCMD_COMMAND | CSCMD_SINGLE_CONVERSION);
4723 retval = cs5529_wait_for_idle(dev);
4724 if (retval) {
4725 comedi_error(dev,
4726 "timeout or signal in cs5529_do_conversion()");
4727 return -ETIME;
4728 }
4729 status = ni_ao_win_inw(dev, CAL_ADC_Status_67xx);
4730 if (status & CSS_OSC_DETECT) {
4731 printk
4732 ("ni_mio_common: cs5529 conversion error, status CSS_OSC_DETECT\n");
4733 return -EIO;
4734 }
4735 if (status & CSS_OVERRANGE) {
4736 printk
4737 ("ni_mio_common: cs5529 conversion error, overrange (ignoring)\n");
4738 }
4739 if (data) {
4740 *data = ni_ao_win_inw(dev, CAL_ADC_Data_67xx);
4741 /* cs5529 returns 16 bit signed data in bipolar mode */
4742 *data ^= (1 << 15);
4743 }
4744 return 0;
4745}
4746
4747static int cs5529_ai_insn_read(struct comedi_device *dev,
4748 struct comedi_subdevice *s,
4749 struct comedi_insn *insn,
4750 unsigned int *data)
4751{
4752 int n, retval;
4753 unsigned short sample;
4754 unsigned int channel_select;
4755 const unsigned int INTERNAL_REF = 0x1000;
4756
4757 /* Set calibration adc source. Docs lie, reference select bits 8 to 11
4758 * do nothing. bit 12 seems to chooses internal reference voltage, bit
4759 * 13 causes the adc input to go overrange (maybe reads external reference?) */
4760 if (insn->chanspec & CR_ALT_SOURCE)
4761 channel_select = INTERNAL_REF;
4762 else
4763 channel_select = CR_CHAN(insn->chanspec);
4764 ni_ao_win_outw(dev, channel_select, AO_Calibration_Channel_Select_67xx);
4765
4766 for (n = 0; n < insn->n; n++) {
4767 retval = cs5529_do_conversion(dev, &sample);
4768 if (retval < 0)
4769 return retval;
4770 data[n] = sample;
4771 }
4772 return insn->n;
4773}
4774
4775static void cs5529_config_write(struct comedi_device *dev, unsigned int value,
4776 unsigned int reg_select_bits)
4777{
4778 ni_ao_win_outw(dev, ((value >> 16) & 0xff),
4779 CAL_ADC_Config_Data_High_Word_67xx);
4780 ni_ao_win_outw(dev, (value & 0xffff),
4781 CAL_ADC_Config_Data_Low_Word_67xx);
4782 reg_select_bits &= CSCMD_REGISTER_SELECT_MASK;
4783 cs5529_command(dev, CSCMD_COMMAND | reg_select_bits);
4784 if (cs5529_wait_for_idle(dev))
4785 comedi_error(dev, "time or signal in cs5529_config_write()");
4786}
4787
4788static int init_cs5529(struct comedi_device *dev)
4789{
4790 unsigned int config_bits =
4791 CSCFG_PORT_MODE | CSCFG_WORD_RATE_2180_CYCLES;
4792
4793#if 1
4794 /* do self-calibration */
4795 cs5529_config_write(dev, config_bits | CSCFG_SELF_CAL_OFFSET_GAIN,
4796 CSCMD_CONFIG_REGISTER);
4797 /* need to force a conversion for calibration to run */
4798 cs5529_do_conversion(dev, NULL);
4799#else
4800 /* force gain calibration to 1 */
4801 cs5529_config_write(dev, 0x400000, CSCMD_GAIN_REGISTER);
4802 cs5529_config_write(dev, config_bits | CSCFG_SELF_CAL_OFFSET,
4803 CSCMD_CONFIG_REGISTER);
4804 if (cs5529_wait_for_idle(dev))
4805 comedi_error(dev, "timeout or signal in init_cs5529()\n");
4806#endif
4807 return 0;
4808}
4809
c8508a1d
HS		 4810#ifdef PCIDMA
4811static int ni_gpct_cmd(struct comedi_device *dev, struct comedi_subdevice *s)
4812{
4813 struct ni_gpct *counter = s->private;
4814 int retval;
4815
4816 retval = ni_request_gpct_mite_channel(dev, counter->counter_index,
4817 COMEDI_INPUT);
4818 if (retval) {
4819 comedi_error(dev,
4820 "no dma channel available for use by counter");
4821 return retval;
4822 }
4823 ni_tio_acknowledge_and_confirm(counter, NULL, NULL, NULL, NULL);
4824 ni_e_series_enable_second_irq(dev, counter->counter_index, 1);
4825
4826 return ni_tio_cmd(dev, s);
4827}
4828
4829static int ni_gpct_cancel(struct comedi_device *dev, struct comedi_subdevice *s)
4830{
4831 struct ni_gpct *counter = s->private;
4832 int retval;
4833
4834 retval = ni_tio_cancel(counter);
4835 ni_e_series_enable_second_irq(dev, counter->counter_index, 0);
4836 ni_release_gpct_mite_channel(dev, counter->counter_index);
4837 return retval;
4838}
4839#endif
4840
5b6137d8 4841static int ni_E_init(struct comedi_device *dev)
03aef4b6 4842{
6293e357 4843 const struct ni_board_struct *board = comedi_board(dev);
0e05c552 4844 struct ni_private *devpriv = dev->private;
34c43922 4845 struct comedi_subdevice *s;
03aef4b6
DS		 4846 unsigned j;
4847 enum ni_gpct_variant counter_variant;
8b6c5694 4848 int ret;
03aef4b6 4849
6293e357
HS		 4850 if (board->n_aochan > MAX_N_AO_CHAN) {
4851 printk("bug! n_aochan > MAX_N_AO_CHAN\n");
03aef4b6
DS		 4852 return -EINVAL;
4853 }
4854
8b6c5694
HS		 4855 ret = comedi_alloc_subdevices(dev, NI_NUM_SUBDEVICES);
4856 if (ret)
4857 return ret;
03aef4b6
DS		 4858
4859 /* analog input subdevice */
4860
f9cd92eb 4861 s = &dev->subdevices[NI_AI_SUBDEV];
03aef4b6 4862 dev->read_subdev = s;
6293e357 4863 if (board->n_adchan) {
03aef4b6
DS		 4864 s->type = COMEDI_SUBD_AI;
4865 s->subdev_flags =
0a85b6f0 4866 SDF_READABLE | SDF_DIFF | SDF_DITHER | SDF_CMD_READ;
6293e357 4867 if (board->reg_type != ni_reg_611x)
03aef4b6 4868 s->subdev_flags |= SDF_GROUND | SDF_COMMON | SDF_OTHER;
6293e357 4869 if (board->adbits > 16)
03aef4b6 4870 s->subdev_flags |= SDF_LSAMPL;
6293e357 4871 if (board->reg_type & ni_reg_m_series_mask)
03aef4b6 4872 s->subdev_flags |= SDF_SOFT_CALIBRATED;
6293e357 4873 s->n_chan = board->n_adchan;
03aef4b6 4874 s->len_chanlist = 512;
6293e357
HS		 4875 s->maxdata = (1 << board->adbits) - 1;
4876 s->range_table = ni_range_lkup[board->gainlkup];
03aef4b6
DS		 4877 s->insn_read = &ni_ai_insn_read;
4878 s->insn_config = &ni_ai_insn_config;
4879 s->do_cmdtest = &ni_ai_cmdtest;
4880 s->do_cmd = &ni_ai_cmd;
4881 s->cancel = &ni_ai_reset;
4882 s->poll = &ni_ai_poll;
4883 s->munge = &ni_ai_munge;
4884#ifdef PCIDMA
4885 s->async_dma_dir = DMA_FROM_DEVICE;
4886#endif
4887 } else {
4888 s->type = COMEDI_SUBD_UNUSED;
4889 }
4890
4891 /* analog output subdevice */
4892
f9cd92eb 4893 s = &dev->subdevices[NI_AO_SUBDEV];
6293e357 4894 if (board->n_aochan) {
03aef4b6
DS		 4895 s->type = COMEDI_SUBD_AO;
4896 s->subdev_flags = SDF_WRITABLE | SDF_DEGLITCH | SDF_GROUND;
6293e357 4897 if (board->reg_type & ni_reg_m_series_mask)
03aef4b6 4898 s->subdev_flags |= SDF_SOFT_CALIBRATED;
6293e357
HS		 4899 s->n_chan = board->n_aochan;
4900 s->maxdata = (1 << board->aobits) - 1;
4901 s->range_table = board->ao_range_table;
03aef4b6 4902 s->insn_read = &ni_ao_insn_read;
bc461556 4903 if (board->reg_type & ni_reg_6xxx_mask)
03aef4b6 4904 s->insn_write = &ni_ao_insn_write_671x;
bc461556 4905 else
03aef4b6 4906 s->insn_write = &ni_ao_insn_write;
03aef4b6
DS		 4907 s->insn_config = &ni_ao_insn_config;
4908#ifdef PCIDMA
6293e357 4909 if (board->n_aochan) {
03aef4b6
DS		 4910 s->async_dma_dir = DMA_TO_DEVICE;
4911#else
6293e357 4912 if (board->ao_fifo_depth) {
03aef4b6
DS		 4913#endif
4914 dev->write_subdev = s;
4915 s->subdev_flags |= SDF_CMD_WRITE;
4916 s->do_cmd = &ni_ao_cmd;
4917 s->do_cmdtest = &ni_ao_cmdtest;
6293e357
HS		 4918 s->len_chanlist = board->n_aochan;
4919 if ((board->reg_type & ni_reg_m_series_mask) == 0)
03aef4b6
DS		 4920 s->munge = ni_ao_munge;
4921 }
4922 s->cancel = &ni_ao_reset;
4923 } else {
4924 s->type = COMEDI_SUBD_UNUSED;
4925 }
6293e357 4926 if ((board->reg_type & ni_reg_67xx_mask))
03aef4b6
DS		 4927 init_ao_67xx(dev, s);
4928
4929 /* digital i/o subdevice */
4930
f9cd92eb 4931 s = &dev->subdevices[NI_DIO_SUBDEV];
03aef4b6
DS		 4932 s->type = COMEDI_SUBD_DIO;
4933 s->subdev_flags = SDF_WRITABLE | SDF_READABLE;
4934 s->maxdata = 1;
4935 s->io_bits = 0; /* all bits input */
4936 s->range_table = &range_digital;
6293e357
HS		 4937 s->n_chan = board->num_p0_dio_channels;
4938 if (board->reg_type & ni_reg_m_series_mask) {
03aef4b6 4939 s->subdev_flags |=
69ba8358 4940 SDF_LSAMPL | SDF_CMD_WRITE /* | SDF_CMD_READ */;
03aef4b6
DS		 4941 s->insn_bits = &ni_m_series_dio_insn_bits;
4942 s->insn_config = &ni_m_series_dio_insn_config;
4943 s->do_cmd = &ni_cdio_cmd;
4944 s->do_cmdtest = &ni_cdio_cmdtest;
4945 s->cancel = &ni_cdio_cancel;
4946 s->async_dma_dir = DMA_BIDIRECTIONAL;
4947 s->len_chanlist = s->n_chan;
4948
4949 ni_writel(CDO_Reset_Bit | CDI_Reset_Bit, M_Offset_CDIO_Command);
4950 ni_writel(s->io_bits, M_Offset_DIO_Direction);
4951 } else {
4952 s->insn_bits = &ni_dio_insn_bits;
4953 s->insn_config = &ni_dio_insn_config;
4954 devpriv->dio_control = DIO_Pins_Dir(s->io_bits);
4955 ni_writew(devpriv->dio_control, DIO_Control_Register);
4956 }
4957
4958 /* 8255 device */
f9cd92eb 4959 s = &dev->subdevices[NI_8255_DIO_SUBDEV];
e6439a45
HS		 4960 if (board->has_8255) {
4961 ret = subdev_8255_init(dev, s, ni_8255_callback,
4962 (unsigned long)dev);
4963 if (ret)
4964 return ret;
4965 } else {
03aef4b6 4966 s->type = COMEDI_SUBD_UNUSED;
e6439a45 4967 }
03aef4b6
DS		 4968
4969 /* formerly general purpose counter/timer device, but no longer used */
f9cd92eb 4970 s = &dev->subdevices[NI_UNUSED_SUBDEV];
03aef4b6
DS		 4971 s->type = COMEDI_SUBD_UNUSED;
4972
4973 /* calibration subdevice -- ai and ao */
f9cd92eb 4974 s = &dev->subdevices[NI_CALIBRATION_SUBDEV];
03aef4b6 4975 s->type = COMEDI_SUBD_CALIB;
6293e357 4976 if (board->reg_type & ni_reg_m_series_mask) {
2696fb57 4977 /* internal PWM analog output used for AI nonlinearity calibration */
03aef4b6
DS		 4978 s->subdev_flags = SDF_INTERNAL;
4979 s->insn_config = &ni_m_series_pwm_config;
4980 s->n_chan = 1;
4981 s->maxdata = 0;
4982 ni_writel(0x0, M_Offset_Cal_PWM);
6293e357 4983 } else if (board->reg_type == ni_reg_6143) {
2696fb57 4984 /* internal PWM analog output used for AI nonlinearity calibration */
03aef4b6
DS		 4985 s->subdev_flags = SDF_INTERNAL;
4986 s->insn_config = &ni_6143_pwm_config;
4987 s->n_chan = 1;
4988 s->maxdata = 0;
4989 } else {
4990 s->subdev_flags = SDF_WRITABLE | SDF_INTERNAL;
4991 s->insn_read = &ni_calib_insn_read;
4992 s->insn_write = &ni_calib_insn_write;
4993 caldac_setup(dev, s);
4994 }
4995
4996 /* EEPROM */
f9cd92eb 4997 s = &dev->subdevices[NI_EEPROM_SUBDEV];
03aef4b6
DS		 4998 s->type = COMEDI_SUBD_MEMORY;
4999 s->subdev_flags = SDF_READABLE | SDF_INTERNAL;
5000 s->maxdata = 0xff;
6293e357 5001 if (board->reg_type & ni_reg_m_series_mask) {
03aef4b6
DS		 5002 s->n_chan = M_SERIES_EEPROM_SIZE;
5003 s->insn_read = &ni_m_series_eeprom_insn_read;
5004 } else {
5005 s->n_chan = 512;
5006 s->insn_read = &ni_eeprom_insn_read;
5007 }
5008
5009 /* PFI */
f9cd92eb 5010 s = &dev->subdevices[NI_PFI_DIO_SUBDEV];
03aef4b6
DS		 5011 s->type = COMEDI_SUBD_DIO;
5012 s->subdev_flags = SDF_READABLE | SDF_WRITABLE | SDF_INTERNAL;
6293e357 5013 if (board->reg_type & ni_reg_m_series_mask) {
03aef4b6
DS		 5014 unsigned i;
5015 s->n_chan = 16;
5016 ni_writew(s->state, M_Offset_PFI_DO);
5017 for (i = 0; i < NUM_PFI_OUTPUT_SELECT_REGS; ++i) {
5018 ni_writew(devpriv->pfi_output_select_reg[i],
0a85b6f0 5019 M_Offset_PFI_Output_Select(i + 1));
03aef4b6
DS		 5020 }
5021 } else {
5022 s->n_chan = 10;
5023 }
5024 s->maxdata = 1;
bc461556 5025 if (board->reg_type & ni_reg_m_series_mask)
03aef4b6 5026 s->insn_bits = &ni_pfi_insn_bits;
03aef4b6
DS		 5027 s->insn_config = &ni_pfi_insn_config;
5028 ni_set_bits(dev, IO_Bidirection_Pin_Register, ~0, 0);
5029
5030 /* cs5529 calibration adc */
f9cd92eb 5031 s = &dev->subdevices[NI_CS5529_CALIBRATION_SUBDEV];
6293e357 5032 if (board->reg_type & ni_reg_67xx_mask) {
03aef4b6
DS		 5033 s->type = COMEDI_SUBD_AI;
5034 s->subdev_flags = SDF_READABLE | SDF_DIFF | SDF_INTERNAL;
2696fb57 5035 /* one channel for each analog output channel */
6293e357 5036 s->n_chan = board->n_aochan;
03aef4b6
DS		 5037 s->maxdata = (1 << 16) - 1;
5038 s->range_table = &range_unknown; /* XXX */
5039 s->insn_read = cs5529_ai_insn_read;
5040 s->insn_config = NULL;
5041 init_cs5529(dev);
5042 } else {
5043 s->type = COMEDI_SUBD_UNUSED;
5044 }
5045
5046 /* Serial */
f9cd92eb 5047 s = &dev->subdevices[NI_SERIAL_SUBDEV];
03aef4b6
DS		 5048 s->type = COMEDI_SUBD_SERIAL;
5049 s->subdev_flags = SDF_READABLE | SDF_WRITABLE | SDF_INTERNAL;
5050 s->n_chan = 1;
5051 s->maxdata = 0xff;
5052 s->insn_config = ni_serial_insn_config;
5053 devpriv->serial_interval_ns = 0;
5054 devpriv->serial_hw_mode = 0;
5055
5056 /* RTSI */
f9cd92eb 5057 s = &dev->subdevices[NI_RTSI_SUBDEV];
03aef4b6
DS		 5058 s->type = COMEDI_SUBD_DIO;
5059 s->subdev_flags = SDF_READABLE | SDF_WRITABLE | SDF_INTERNAL;
5060 s->n_chan = 8;
5061 s->maxdata = 1;
5062 s->insn_bits = ni_rtsi_insn_bits;
5063 s->insn_config = ni_rtsi_insn_config;
5064 ni_rtsi_init(dev);
5065
bc461556 5066 if (board->reg_type & ni_reg_m_series_mask)
03aef4b6 5067 counter_variant = ni_gpct_variant_m_series;
bc461556 5068 else
03aef4b6 5069 counter_variant = ni_gpct_variant_e_series;
03aef4b6 5070 devpriv->counter_dev = ni_gpct_device_construct(dev,
0a85b6f0
MT		 5071 &ni_gpct_write_register,
5072 &ni_gpct_read_register,
5073 counter_variant,
5074 NUM_GPCT);
c095fad3
KAM		 5075 if (!devpriv->counter_dev)
5076 return -ENOMEM;
5077
03aef4b6
DS		 5078 /* General purpose counters */
5079 for (j = 0; j < NUM_GPCT; ++j) {
f9cd92eb 5080 s = &dev->subdevices[NI_GPCT_SUBDEV(j)];
03aef4b6 5081 s->type = COMEDI_SUBD_COUNTER;
bd304a73 5082 s->subdev_flags = SDF_READABLE | SDF_WRITABLE | SDF_LSAMPL;
03aef4b6 5083 s->n_chan = 3;
6293e357 5084 if (board->reg_type & ni_reg_m_series_mask)
03aef4b6
DS		 5085 s->maxdata = 0xffffffff;
5086 else
5087 s->maxdata = 0xffffff;
9014d816 5088 s->insn_read = ni_tio_insn_read;
10f74377 5089 s->insn_write = ni_tio_insn_read;
cac04c0f 5090 s->insn_config = ni_tio_insn_config;
bd304a73
IA		 5091#ifdef PCIDMA
5092 s->subdev_flags |= SDF_CMD_READ /* | SDF_CMD_WRITE */;
03aef4b6
DS		 5093 s->do_cmd = &ni_gpct_cmd;
5094 s->len_chanlist = 1;
c3f3b431 5095 s->do_cmdtest = ni_tio_cmdtest;
03aef4b6
DS		 5096 s->cancel = &ni_gpct_cancel;
5097 s->async_dma_dir = DMA_BIDIRECTIONAL;
bd304a73 5098#endif
03aef4b6
DS		 5099 s->private = &devpriv->counter_dev->counters[j];
5100
5101 devpriv->counter_dev->counters[j].chip_index = 0;
5102 devpriv->counter_dev->counters[j].counter_index = j;
5103 ni_tio_init_counter(&devpriv->counter_dev->counters[j]);
5104 }
5105
5106 /* Frequency output */
f9cd92eb 5107 s = &dev->subdevices[NI_FREQ_OUT_SUBDEV];
03aef4b6
DS		 5108 s->type = COMEDI_SUBD_COUNTER;
5109 s->subdev_flags = SDF_READABLE | SDF_WRITABLE;
5110 s->n_chan = 1;
5111 s->maxdata = 0xf;
5112 s->insn_read = &ni_freq_out_insn_read;
5113 s->insn_write = &ni_freq_out_insn_write;
5114 s->insn_config = &ni_freq_out_insn_config;
5115
5116 /* ai configuration */
f9cd92eb
HS		 5117 s = &dev->subdevices[NI_AI_SUBDEV];
5118 ni_ai_reset(dev, s);
6293e357 5119 if ((board->reg_type & ni_reg_6xxx_mask) == 0) {
2696fb57 5120 /* BEAM is this needed for PCI-6143 ?? */
03aef4b6 5121 devpriv->clock_and_fout =
0a85b6f0
MT		 5122 Slow_Internal_Time_Divide_By_2 |
5123 Slow_Internal_Timebase |
5124 Clock_To_Board_Divide_By_2 |
5125 Clock_To_Board |
5126 AI_Output_Divide_By_2 | AO_Output_Divide_By_2;
03aef4b6
DS		 5127 } else {
5128 devpriv->clock_and_fout =
0a85b6f0
MT		 5129 Slow_Internal_Time_Divide_By_2 |
5130 Slow_Internal_Timebase |
5131 Clock_To_Board_Divide_By_2 | Clock_To_Board;
03aef4b6
DS		 5132 }
5133 devpriv->stc_writew(dev, devpriv->clock_and_fout,
0a85b6f0 5134 Clock_and_FOUT_Register);
03aef4b6
DS		 5135
5136 /* analog output configuration */
f9cd92eb
HS		 5137 s = &dev->subdevices[NI_AO_SUBDEV];
5138 ni_ao_reset(dev, s);
03aef4b6
DS		 5139
5140 if (dev->irq) {
5141 devpriv->stc_writew(dev,
0a85b6f0
MT		 5142 (IRQ_POLARITY ? Interrupt_Output_Polarity :
5143 0) | (Interrupt_Output_On_3_Pins & 0) |
5144 Interrupt_A_Enable | Interrupt_B_Enable |
5145 Interrupt_A_Output_Select(interrupt_pin
5146 (dev->irq)) |
5147 Interrupt_B_Output_Select(interrupt_pin
5148 (dev->irq)),
5149 Interrupt_Control_Register);
03aef4b6
DS		 5150 }
5151
5152 /* DMA setup */
5153 ni_writeb(devpriv->ai_ao_select_reg, AI_AO_Select);
5154 ni_writeb(devpriv->g0_g1_select_reg, G0_G1_Select);
5155
6293e357 5156 if (board->reg_type & ni_reg_6xxx_mask) {
03aef4b6 5157 ni_writeb(0, Magic_611x);
6293e357 5158 } else if (board->reg_type & ni_reg_m_series_mask) {
03aef4b6 5159 int channel;
6293e357 5160 for (channel = 0; channel < board->n_aochan; ++channel) {
03aef4b6
DS		 5161 ni_writeb(0xf, M_Offset_AO_Waveform_Order(channel));
5162 ni_writeb(0x0,
0a85b6f0 5163 M_Offset_AO_Reference_Attenuation(channel));
03aef4b6
DS		 5164 }
5165 ni_writeb(0x0, M_Offset_AO_Calibration);
5166 }
5167
03aef4b6
DS		 5168 return 0;
5169}
5170
03aef4b6
DS		 5171#if 0
5172/*
5173 * Read the GPCTs current value.
5174 */
da91b269 5175static int GPCT_G_Watch(struct comedi_device *dev, int chan)
03aef4b6
DS		 5176{
5177 unsigned int hi1, hi2, lo;
5178
5179 devpriv->gpct_command[chan] &= ~G_Save_Trace;
5180 devpriv->stc_writew(dev, devpriv->gpct_command[chan],
0a85b6f0 5181 G_Command_Register(chan));
03aef4b6
DS		 5182
5183 devpriv->gpct_command[chan] |= G_Save_Trace;
5184 devpriv->stc_writew(dev, devpriv->gpct_command[chan],
0a85b6f0 5185 G_Command_Register(chan));
03aef4b6
DS		 5186
5187 /* This procedure is used because the two registers cannot
5188 * be read atomically. */
5189 do {
5190 hi1 = devpriv->stc_readw(dev, G_Save_Register_High(chan));
5191 lo = devpriv->stc_readw(dev, G_Save_Register_Low(chan));
5192 hi2 = devpriv->stc_readw(dev, G_Save_Register_High(chan));
5193 } while (hi1 != hi2);
5194
5195 return (hi1 << 16) | lo;
5196}
5197
da91b269 5198static void GPCT_Reset(struct comedi_device *dev, int chan)
03aef4b6
DS		 5199{
5200 int temp_ack_reg = 0;
5201
2696fb57 5202 /* printk("GPCT_Reset..."); */
03aef4b6
DS		 5203 devpriv->gpct_cur_operation[chan] = GPCT_RESET;
5204
5205 switch (chan) {
5206 case 0:
5207 devpriv->stc_writew(dev, G0_Reset, Joint_Reset_Register);
5208 ni_set_bits(dev, Interrupt_A_Enable_Register,
0a85b6f0 5209 G0_TC_Interrupt_Enable, 0);
03aef4b6 5210 ni_set_bits(dev, Interrupt_A_Enable_Register,
0a85b6f0 5211 G0_Gate_Interrupt_Enable, 0);
03aef4b6
DS		 5212 temp_ack_reg |= G0_Gate_Error_Confirm;
5213 temp_ack_reg |= G0_TC_Error_Confirm;
5214 temp_ack_reg |= G0_TC_Interrupt_Ack;
5215 temp_ack_reg |= G0_Gate_Interrupt_Ack;
5216 devpriv->stc_writew(dev, temp_ack_reg,
0a85b6f0 5217 Interrupt_A_Ack_Register);
03aef4b6 5218
2696fb57 5219 /* problem...this interferes with the other ctr... */
03aef4b6
DS		 5220 devpriv->an_trig_etc_reg |= GPFO_0_Output_Enable;
5221 devpriv->stc_writew(dev, devpriv->an_trig_etc_reg,
0a85b6f0 5222 Analog_Trigger_Etc_Register);
03aef4b6
DS		 5223 break;
5224 case 1:
5225 devpriv->stc_writew(dev, G1_Reset, Joint_Reset_Register);
5226 ni_set_bits(dev, Interrupt_B_Enable_Register,
0a85b6f0 5227 G1_TC_Interrupt_Enable, 0);
03aef4b6 5228 ni_set_bits(dev, Interrupt_B_Enable_Register,
0a85b6f0 5229 G0_Gate_Interrupt_Enable, 0);
03aef4b6
DS		 5230 temp_ack_reg |= G1_Gate_Error_Confirm;
5231 temp_ack_reg |= G1_TC_Error_Confirm;
5232 temp_ack_reg |= G1_TC_Interrupt_Ack;
5233 temp_ack_reg |= G1_Gate_Interrupt_Ack;
5234 devpriv->stc_writew(dev, temp_ack_reg,
0a85b6f0 5235 Interrupt_B_Ack_Register);
03aef4b6
DS		 5236
5237 devpriv->an_trig_etc_reg |= GPFO_1_Output_Enable;
5238 devpriv->stc_writew(dev, devpriv->an_trig_etc_reg,
0a85b6f0 5239 Analog_Trigger_Etc_Register);
03aef4b6 5240 break;
95cd17c9 5241 }
03aef4b6
DS		 5242
5243 devpriv->gpct_mode[chan] = 0;
5244 devpriv->gpct_input_select[chan] = 0;
5245 devpriv->gpct_command[chan] = 0;
5246
5247 devpriv->gpct_command[chan] |= G_Synchronized_Gate;
5248
5249 devpriv->stc_writew(dev, devpriv->gpct_mode[chan],
0a85b6f0 5250 G_Mode_Register(chan));
03aef4b6 5251 devpriv->stc_writew(dev, devpriv->gpct_input_select[chan],
0a85b6f0 5252 G_Input_Select_Register(chan));
03aef4b6
DS		 5253 devpriv->stc_writew(dev, 0, G_Autoincrement_Register(chan));
5254
2696fb57 5255 /* printk("exit GPCT_Reset\n"); */
03aef4b6
DS		 5256}
5257
5258#endif
5259
03aef4b6
DS		 5260/*
5261 *
5262 * NI RTSI Bus Functions
5263 *
5264 */
da91b269 5265static void ni_rtsi_init(struct comedi_device *dev)
03aef4b6 5266{
6293e357 5267 const struct ni_board_struct *board = comedi_board(dev);
0e05c552
HS		 5268 struct ni_private *devpriv = dev->private;
5269
2696fb57 5270 /* Initialises the RTSI bus signal switch to a default state */
03aef4b6 5271
2696fb57 5272 /* Set clock mode to internal */
03aef4b6 5273 devpriv->clock_and_fout2 = MSeries_RTSI_10MHz_Bit;
bc461556 5274 if (ni_set_master_clock(dev, NI_MIO_INTERNAL_CLOCK, 0) < 0)
5f74ea14 5275 printk("ni_set_master_clock failed, bug?");
2696fb57 5276 /* default internal lines routing to RTSI bus lines */
03aef4b6 5277 devpriv->rtsi_trig_a_output_reg =
0a85b6f0
MT		 5278 RTSI_Trig_Output_Bits(0,
5279 NI_RTSI_OUTPUT_ADR_START1) |
5280 RTSI_Trig_Output_Bits(1,
5281 NI_RTSI_OUTPUT_ADR_START2) |
5282 RTSI_Trig_Output_Bits(2,
5283 NI_RTSI_OUTPUT_SCLKG) |
5284 RTSI_Trig_Output_Bits(3, NI_RTSI_OUTPUT_DACUPDN);
03aef4b6 5285 devpriv->stc_writew(dev, devpriv->rtsi_trig_a_output_reg,
0a85b6f0 5286 RTSI_Trig_A_Output_Register);
03aef4b6 5287 devpriv->rtsi_trig_b_output_reg =
0a85b6f0
MT		 5288 RTSI_Trig_Output_Bits(4,
5289 NI_RTSI_OUTPUT_DA_START1) |
5290 RTSI_Trig_Output_Bits(5,
5291 NI_RTSI_OUTPUT_G_SRC0) |
5292 RTSI_Trig_Output_Bits(6, NI_RTSI_OUTPUT_G_GATE0);
6293e357 5293 if (board->reg_type & ni_reg_m_series_mask)
03aef4b6 5294 devpriv->rtsi_trig_b_output_reg |=
0a85b6f0 5295 RTSI_Trig_Output_Bits(7, NI_RTSI_OUTPUT_RTSI_OSC);
03aef4b6 5296 devpriv->stc_writew(dev, devpriv->rtsi_trig_b_output_reg,
0a85b6f0 5297 RTSI_Trig_B_Output_Register);
03aef4b6 5298
2696fb57
BP		 5299/*
5300* Sets the source and direction of the 4 on board lines
5301* devpriv->stc_writew(dev, 0x0000, RTSI_Board_Register);
5302*/
03aef4b6
DS		 5303}
5304
0a85b6f0
MT		 5305static int ni_rtsi_insn_bits(struct comedi_device *dev,
5306 struct comedi_subdevice *s,
5307 struct comedi_insn *insn, unsigned int *data)
03aef4b6 5308{
03aef4b6
DS		 5309 data[1] = 0;
5310
a2714e3e 5311 return insn->n;
03aef4b6
DS		 5312}
5313
5314/* Find best multiplier/divider to try and get the PLL running at 80 MHz
5315 * given an arbitrary frequency input clock */
5316static int ni_mseries_get_pll_parameters(unsigned reference_period_ns,
0a85b6f0
MT		 5317 unsigned *freq_divider,
5318 unsigned *freq_multiplier,
5319 unsigned *actual_period_ns)
03aef4b6
DS		 5320{
5321 unsigned div;
5322 unsigned best_div = 1;
5323 static const unsigned max_div = 0x10;
5324 unsigned mult;
5325 unsigned best_mult = 1;
5326 static const unsigned max_mult = 0x100;
5327 static const unsigned pico_per_nano = 1000;
5328
5329 const unsigned reference_picosec = reference_period_ns * pico_per_nano;
5330 /* m-series wants the phased-locked loop to output 80MHz, which is divided by 4 to
5331 * 20 MHz for most timing clocks */
5332 static const unsigned target_picosec = 12500;
5333 static const unsigned fudge_factor_80_to_20Mhz = 4;
5334 int best_period_picosec = 0;
5335 for (div = 1; div <= max_div; ++div) {
5336 for (mult = 1; mult <= max_mult; ++mult) {
5337 unsigned new_period_ps =
0a85b6f0 5338 (reference_picosec * div) / mult;
03aef4b6 5339 if (abs(new_period_ps - target_picosec) <
0a85b6f0 5340 abs(best_period_picosec - target_picosec)) {
03aef4b6
DS		 5341 best_period_picosec = new_period_ps;
5342 best_div = div;
5343 best_mult = mult;
5344 }
5345 }
5346 }
5347 if (best_period_picosec == 0) {
0a85b6f0 5348 printk("%s: bug, failed to find pll parameters\n", __func__);
03aef4b6
DS		 5349 return -EIO;
5350 }
5351 *freq_divider = best_div;
5352 *freq_multiplier = best_mult;
5353 *actual_period_ns =
0a85b6f0
MT		 5354 (best_period_picosec * fudge_factor_80_to_20Mhz +
5355 (pico_per_nano / 2)) / pico_per_nano;
03aef4b6
DS		 5356 return 0;
5357}
5358
da91b269 5359static inline unsigned num_configurable_rtsi_channels(struct comedi_device *dev)
03aef4b6 5360{
6293e357
HS		 5361 const struct ni_board_struct *board = comedi_board(dev);
5362
5363 if (board->reg_type & ni_reg_m_series_mask)
03aef4b6
DS		 5364 return 8;
5365 else
5366 return 7;
5367}
5368
0a85b6f0
MT		 5369static int ni_mseries_set_pll_master_clock(struct comedi_device *dev,
5370 unsigned source, unsigned period_ns)
03aef4b6 5371{
0e05c552 5372 struct ni_private *devpriv = dev->private;
03aef4b6
DS		 5373 static const unsigned min_period_ns = 50;
5374 static const unsigned max_period_ns = 1000;
5375 static const unsigned timeout = 1000;
5376 unsigned pll_control_bits;
5377 unsigned freq_divider;
5378 unsigned freq_multiplier;
5379 unsigned i;
5380 int retval;
0e05c552 5381
03aef4b6
DS		 5382 if (source == NI_MIO_PLL_PXI10_CLOCK)
5383 period_ns = 100;
2696fb57 5384 /* these limits are somewhat arbitrary, but NI advertises 1 to 20MHz range so we'll use that */
03aef4b6 5385 if (period_ns < min_period_ns || period_ns > max_period_ns) {
5f74ea14 5386 printk
0a85b6f0
MT		 5387 ("%s: you must specify an input clock frequency between %i and %i nanosec "
5388 "for the phased-lock loop.\n", __func__,
5389 min_period_ns, max_period_ns);
03aef4b6
DS		 5390 return -EINVAL;
5391 }
5392 devpriv->rtsi_trig_direction_reg &= ~Use_RTSI_Clock_Bit;
5393 devpriv->stc_writew(dev, devpriv->rtsi_trig_direction_reg,
0a85b6f0 5394 RTSI_Trig_Direction_Register);
03aef4b6 5395 pll_control_bits =
0a85b6f0 5396 MSeries_PLL_Enable_Bit | MSeries_PLL_VCO_Mode_75_150MHz_Bits;
03aef4b6 5397 devpriv->clock_and_fout2 |=
0a85b6f0 5398 MSeries_Timebase1_Select_Bit | MSeries_Timebase3_Select_Bit;
03aef4b6
DS		 5399 devpriv->clock_and_fout2 &= ~MSeries_PLL_In_Source_Select_Mask;
5400 switch (source) {
5401 case NI_MIO_PLL_PXI_STAR_TRIGGER_CLOCK:
5402 devpriv->clock_and_fout2 |=
0a85b6f0 5403 MSeries_PLL_In_Source_Select_Star_Trigger_Bits;
03aef4b6 5404 retval = ni_mseries_get_pll_parameters(period_ns, &freq_divider,
0a85b6f0
MT		 5405 &freq_multiplier,
5406 &devpriv->clock_ns);
03aef4b6
DS		 5407 if (retval < 0)
5408 return retval;
5409 break;
5410 case NI_MIO_PLL_PXI10_CLOCK:
5411 /* pxi clock is 10MHz */
5412 devpriv->clock_and_fout2 |=
0a85b6f0 5413 MSeries_PLL_In_Source_Select_PXI_Clock10;
03aef4b6 5414 retval = ni_mseries_get_pll_parameters(period_ns, &freq_divider,
0a85b6f0
MT		 5415 &freq_multiplier,
5416 &devpriv->clock_ns);
03aef4b6
DS		 5417 if (retval < 0)
5418 return retval;
5419 break;
5420 default:
5421 {
5422 unsigned rtsi_channel;
5423 static const unsigned max_rtsi_channel = 7;
5424 for (rtsi_channel = 0; rtsi_channel <= max_rtsi_channel;
0a85b6f0 5425 ++rtsi_channel) {
03aef4b6 5426 if (source ==
0a85b6f0 5427 NI_MIO_PLL_RTSI_CLOCK(rtsi_channel)) {
03aef4b6 5428 devpriv->clock_and_fout2 |=
0a85b6f0
MT		 5429 MSeries_PLL_In_Source_Select_RTSI_Bits
5430 (rtsi_channel);
03aef4b6
DS		 5431 break;
5432 }
5433 }
5434 if (rtsi_channel > max_rtsi_channel)
5435 return -EINVAL;
5436 retval = ni_mseries_get_pll_parameters(period_ns,
0a85b6f0
MT		 5437 &freq_divider,
5438 &freq_multiplier,
5439 &devpriv->
5440 clock_ns);
03aef4b6
DS		 5441 if (retval < 0)
5442 return retval;
5443 }
5444 break;
5445 }
5446 ni_writew(devpriv->clock_and_fout2, M_Offset_Clock_and_Fout2);
5447 pll_control_bits |=
0a85b6f0
MT		 5448 MSeries_PLL_Divisor_Bits(freq_divider) |
5449 MSeries_PLL_Multiplier_Bits(freq_multiplier);
2696fb57 5450
5f74ea14 5451 /* printk("using divider=%i, multiplier=%i for PLL. pll_control_bits = 0x%x\n",
2696fb57 5452 * freq_divider, freq_multiplier, pll_control_bits); */
5f74ea14 5453 /* printk("clock_ns=%d\n", devpriv->clock_ns); */
03aef4b6
DS		 5454 ni_writew(pll_control_bits, M_Offset_PLL_Control);
5455 devpriv->clock_source = source;
5456 /* it seems to typically take a few hundred microseconds for PLL to lock */
5457 for (i = 0; i < timeout; ++i) {
bc461556 5458 if (ni_readw(M_Offset_PLL_Status) & MSeries_PLL_Locked_Bit)
03aef4b6 5459 break;
03aef4b6
DS		 5460 udelay(1);
5461 }
5462 if (i == timeout) {
5f74ea14 5463 printk
0a85b6f0
MT		 5464 ("%s: timed out waiting for PLL to lock to reference clock source %i with period %i ns.\n",
5465 __func__, source, period_ns);
03aef4b6
DS		 5466 return -ETIMEDOUT;
5467 }
5468 return 3;
5469}
5470
da91b269 5471static int ni_set_master_clock(struct comedi_device *dev, unsigned source,
0a85b6f0 5472 unsigned period_ns)
03aef4b6 5473{
6293e357 5474 const struct ni_board_struct *board = comedi_board(dev);
0e05c552
HS		 5475 struct ni_private *devpriv = dev->private;
5476
03aef4b6
DS		 5477 if (source == NI_MIO_INTERNAL_CLOCK) {
5478 devpriv->rtsi_trig_direction_reg &= ~Use_RTSI_Clock_Bit;
5479 devpriv->stc_writew(dev, devpriv->rtsi_trig_direction_reg,
0a85b6f0 5480 RTSI_Trig_Direction_Register);
03aef4b6 5481 devpriv->clock_ns = TIMEBASE_1_NS;
6293e357 5482 if (board->reg_type & ni_reg_m_series_mask) {
03aef4b6 5483 devpriv->clock_and_fout2 &=
0a85b6f0
MT		 5484 ~(MSeries_Timebase1_Select_Bit |
5485 MSeries_Timebase3_Select_Bit);
03aef4b6 5486 ni_writew(devpriv->clock_and_fout2,
0a85b6f0 5487 M_Offset_Clock_and_Fout2);
03aef4b6
DS		 5488 ni_writew(0, M_Offset_PLL_Control);
5489 }
5490 devpriv->clock_source = source;
5491 } else {
6293e357 5492 if (board->reg_type & ni_reg_m_series_mask) {
03aef4b6 5493 return ni_mseries_set_pll_master_clock(dev, source,
0a85b6f0 5494 period_ns);
03aef4b6
DS		 5495 } else {
5496 if (source == NI_MIO_RTSI_CLOCK) {
5497 devpriv->rtsi_trig_direction_reg |=
0a85b6f0 5498 Use_RTSI_Clock_Bit;
03aef4b6 5499 devpriv->stc_writew(dev,
0a85b6f0
MT		 5500 devpriv->
5501 rtsi_trig_direction_reg,
5502 RTSI_Trig_Direction_Register);
03aef4b6 5503 if (period_ns == 0) {
5f74ea14 5504 printk
0a85b6f0
MT		 5505 ("%s: we don't handle an unspecified clock period correctly yet, returning error.\n",
5506 __func__);
03aef4b6
DS		 5507 return -EINVAL;
5508 } else {
5509 devpriv->clock_ns = period_ns;
5510 }
5511 devpriv->clock_source = source;
5512 } else
5513 return -EINVAL;
5514 }
5515 }
5516 return 3;
5517}
5518
da91b269 5519static int ni_valid_rtsi_output_source(struct comedi_device *dev, unsigned chan,
0a85b6f0 5520 unsigned source)
03aef4b6 5521{
6293e357
HS		 5522 const struct ni_board_struct *board = comedi_board(dev);
5523
03aef4b6
DS		 5524 if (chan >= num_configurable_rtsi_channels(dev)) {
5525 if (chan == old_RTSI_clock_channel) {
5526 if (source == NI_RTSI_OUTPUT_RTSI_OSC)
5527 return 1;
5528 else {
5f74ea14 5529 printk
0a85b6f0
MT		 5530 ("%s: invalid source for channel=%i, channel %i is always the RTSI clock for pre-m-series boards.\n",
5531 __func__, chan, old_RTSI_clock_channel);
03aef4b6
DS		 5532 return 0;
5533 }
5534 }
5535 return 0;
5536 }
5537 switch (source) {
5538 case NI_RTSI_OUTPUT_ADR_START1:
5539 case NI_RTSI_OUTPUT_ADR_START2:
5540 case NI_RTSI_OUTPUT_SCLKG:
5541 case NI_RTSI_OUTPUT_DACUPDN:
5542 case NI_RTSI_OUTPUT_DA_START1:
5543 case NI_RTSI_OUTPUT_G_SRC0:
5544 case NI_RTSI_OUTPUT_G_GATE0:
5545 case NI_RTSI_OUTPUT_RGOUT0:
5546 case NI_RTSI_OUTPUT_RTSI_BRD_0:
5547 return 1;
5548 break;
5549 case NI_RTSI_OUTPUT_RTSI_OSC:
6293e357 5550 if (board->reg_type & ni_reg_m_series_mask)
03aef4b6
DS		 5551 return 1;
5552 else
5553 return 0;
5554 break;
5555 default:
5556 return 0;
5557 break;
5558 }
5559}
5560
da91b269 5561static int ni_set_rtsi_routing(struct comedi_device *dev, unsigned chan,
0a85b6f0 5562 unsigned source)
03aef4b6 5563{
0e05c552
HS		 5564 struct ni_private *devpriv = dev->private;
5565
03aef4b6
DS		 5566 if (ni_valid_rtsi_output_source(dev, chan, source) == 0)
5567 return -EINVAL;
5568 if (chan < 4) {
5569 devpriv->rtsi_trig_a_output_reg &= ~RTSI_Trig_Output_Mask(chan);
5570 devpriv->rtsi_trig_a_output_reg |=
0a85b6f0 5571 RTSI_Trig_Output_Bits(chan, source);
03aef4b6 5572 devpriv->stc_writew(dev, devpriv->rtsi_trig_a_output_reg,
0a85b6f0 5573 RTSI_Trig_A_Output_Register);
03aef4b6
DS		 5574 } else if (chan < 8) {
5575 devpriv->rtsi_trig_b_output_reg &= ~RTSI_Trig_Output_Mask(chan);
5576 devpriv->rtsi_trig_b_output_reg |=
0a85b6f0 5577 RTSI_Trig_Output_Bits(chan, source);
03aef4b6 5578 devpriv->stc_writew(dev, devpriv->rtsi_trig_b_output_reg,
0a85b6f0 5579 RTSI_Trig_B_Output_Register);
03aef4b6
DS		 5580 }
5581 return 2;
5582}
5583
da91b269 5584static unsigned ni_get_rtsi_routing(struct comedi_device *dev, unsigned chan)
03aef4b6 5585{
0e05c552
HS		 5586 struct ni_private *devpriv = dev->private;
5587
03aef4b6
DS		 5588 if (chan < 4) {
5589 return RTSI_Trig_Output_Source(chan,
0a85b6f0 5590 devpriv->rtsi_trig_a_output_reg);
03aef4b6
DS		 5591 } else if (chan < num_configurable_rtsi_channels(dev)) {
5592 return RTSI_Trig_Output_Source(chan,
0a85b6f0 5593 devpriv->rtsi_trig_b_output_reg);
03aef4b6
DS		 5594 } else {
5595 if (chan == old_RTSI_clock_channel)
5596 return NI_RTSI_OUTPUT_RTSI_OSC;
5f74ea14 5597 printk("%s: bug! should never get here?\n", __func__);
03aef4b6
DS		 5598 return 0;
5599 }
5600}
5601
0a85b6f0
MT		 5602static int ni_rtsi_insn_config(struct comedi_device *dev,
5603 struct comedi_subdevice *s,
5604 struct comedi_insn *insn, unsigned int *data)
03aef4b6 5605{
6293e357 5606 const struct ni_board_struct *board = comedi_board(dev);
0e05c552 5607 struct ni_private *devpriv = dev->private;
03aef4b6 5608 unsigned int chan = CR_CHAN(insn->chanspec);
0e05c552 5609
03aef4b6
DS		 5610 switch (data[0]) {
5611 case INSN_CONFIG_DIO_OUTPUT:
5612 if (chan < num_configurable_rtsi_channels(dev)) {
5613 devpriv->rtsi_trig_direction_reg |=
0a85b6f0 5614 RTSI_Output_Bit(chan,
6293e357 5615 (board->reg_type & ni_reg_m_series_mask) != 0);
03aef4b6
DS		 5616 } else if (chan == old_RTSI_clock_channel) {
5617 devpriv->rtsi_trig_direction_reg |=
0a85b6f0 5618 Drive_RTSI_Clock_Bit;
03aef4b6
DS		 5619 }
5620 devpriv->stc_writew(dev, devpriv->rtsi_trig_direction_reg,
0a85b6f0 5621 RTSI_Trig_Direction_Register);
03aef4b6
DS		 5622 break;
5623 case INSN_CONFIG_DIO_INPUT:
5624 if (chan < num_configurable_rtsi_channels(dev)) {
5625 devpriv->rtsi_trig_direction_reg &=
0a85b6f0 5626 ~RTSI_Output_Bit(chan,
6293e357 5627 (board->reg_type & ni_reg_m_series_mask) != 0);
03aef4b6
DS		 5628 } else if (chan == old_RTSI_clock_channel) {
5629 devpriv->rtsi_trig_direction_reg &=
0a85b6f0 5630 ~Drive_RTSI_Clock_Bit;
03aef4b6
DS		 5631 }
5632 devpriv->stc_writew(dev, devpriv->rtsi_trig_direction_reg,
0a85b6f0 5633 RTSI_Trig_Direction_Register);
03aef4b6
DS		 5634 break;
5635 case INSN_CONFIG_DIO_QUERY:
5636 if (chan < num_configurable_rtsi_channels(dev)) {
5637 data[1] =
0a85b6f0
MT		 5638 (devpriv->rtsi_trig_direction_reg &
5639 RTSI_Output_Bit(chan,
6293e357
HS		 5640 (board->reg_type & ni_reg_m_series_mask) != 0))
5641 ? INSN_CONFIG_DIO_OUTPUT
5642 : INSN_CONFIG_DIO_INPUT;
03aef4b6
DS		 5643 } else if (chan == old_RTSI_clock_channel) {
5644 data[1] =
0a85b6f0
MT		 5645 (devpriv->rtsi_trig_direction_reg &
5646 Drive_RTSI_Clock_Bit)
5647 ? INSN_CONFIG_DIO_OUTPUT : INSN_CONFIG_DIO_INPUT;
03aef4b6
DS		 5648 }
5649 return 2;
5650 break;
5651 case INSN_CONFIG_SET_CLOCK_SRC:
5652 return ni_set_master_clock(dev, data[1], data[2]);
5653 break;
5654 case INSN_CONFIG_GET_CLOCK_SRC:
5655 data[1] = devpriv->clock_source;
5656 data[2] = devpriv->clock_ns;
5657 return 3;
5658 break;
5659 case INSN_CONFIG_SET_ROUTING:
5660 return ni_set_rtsi_routing(dev, chan, data[1]);
5661 break;
5662 case INSN_CONFIG_GET_ROUTING:
5663 data[1] = ni_get_rtsi_routing(dev, chan);
5664 return 2;
5665 break;
5666 default:
5667 return -EINVAL;
5668 break;
5669 }
5670 return 1;
5671}
Linux kernel - Deliverables
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