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staging: comedi: ni_stc.h: tidy up AO_Configuration register and bits
[deliverable/linux.git] / drivers / staging / comedi / drivers / ni_mio_common.c
CommitLineData
03aef4b6
DS		 1/*
2 comedi/drivers/ni_mio_common.c
3 Hardware driver for DAQ-STC based boards
4
5 COMEDI - Linux Control and Measurement Device Interface
6 Copyright (C) 1997-2001 David A. Schleef <ds@schleef.org>
7 Copyright (C) 2002-2006 Frank Mori Hess <fmhess@users.sourceforge.net>
8
9 This program is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 2 of the License, or
12 (at your option) any later version.
13
14 This program is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
03aef4b6
DS		 18*/
19
20/*
21 This file is meant to be included by another file, e.g.,
22 ni_atmio.c or ni_pcimio.c.
23
24 Interrupt support originally added by Truxton Fulton
25 <trux@truxton.com>
26
27 References (from ftp://ftp.natinst.com/support/manuals):
28
29 340747b.pdf AT-MIO E series Register Level Programmer Manual
30 341079b.pdf PCI E Series RLPM
31 340934b.pdf DAQ-STC reference manual
631dd1a8 32 67xx and 611x registers (from ftp://ftp.ni.com/support/daq/mhddk/documentation/)
03aef4b6
DS		 33 release_ni611x.pdf
34 release_ni67xx.pdf
35 Other possibly relevant info:
36
37 320517c.pdf User manual (obsolete)
38 320517f.pdf User manual (new)
39 320889a.pdf delete
40 320906c.pdf maximum signal ratings
41 321066a.pdf about 16x
42 321791a.pdf discontinuation of at-mio-16e-10 rev. c
43 321808a.pdf about at-mio-16e-10 rev P
44 321837a.pdf discontinuation of at-mio-16de-10 rev d
45 321838a.pdf about at-mio-16de-10 rev N
46
47 ISSUES:
48
49 - the interrupt routine needs to be cleaned up
50
51 2006-02-07: S-Series PCI-6143: Support has been added but is not
52 fully tested as yet. Terry Barnaby, BEAM Ltd.
53*/
54
25436dc9 55#include <linux/interrupt.h>
4377a026 56#include <linux/sched.h>
305591a5 57#include <linux/delay.h>
03aef4b6
DS		 58#include "8255.h"
59#include "mite.h"
03aef4b6 60
03aef4b6
DS		 61/* A timeout count */
62#define NI_TIMEOUT 1000
03aef4b6
DS		 63
64/* Note: this table must match the ai_gain_* definitions */
65static const short ni_gainlkup[][16] = {
66 [ai_gain_16] = {0, 1, 2, 3, 4, 5, 6, 7,
0a85b6f0 67 0x100, 0x101, 0x102, 0x103, 0x104, 0x105, 0x106, 0x107},
03aef4b6
DS		 68 [ai_gain_8] = {1, 2, 4, 7, 0x101, 0x102, 0x104, 0x107},
69 [ai_gain_14] = {1, 2, 3, 4, 5, 6, 7,
0a85b6f0 70 0x101, 0x102, 0x103, 0x104, 0x105, 0x106, 0x107},
03aef4b6
DS		 71 [ai_gain_4] = {0, 1, 4, 7},
72 [ai_gain_611x] = {0x00a, 0x00b, 0x001, 0x002,
0a85b6f0 73 0x003, 0x004, 0x005, 0x006},
03aef4b6
DS		 74 [ai_gain_622x] = {0, 1, 4, 5},
75 [ai_gain_628x] = {1, 2, 3, 4, 5, 6, 7},
76 [ai_gain_6143] = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
77};
78
daed6c72
HS		 79static const struct comedi_lrange range_ni_E_ai = {
80 16, {
81 BIP_RANGE(10),
82 BIP_RANGE(5),
83 BIP_RANGE(2.5),
84 BIP_RANGE(1),
85 BIP_RANGE(0.5),
86 BIP_RANGE(0.25),
87 BIP_RANGE(0.1),
88 BIP_RANGE(0.05),
89 UNI_RANGE(20),
90 UNI_RANGE(10),
91 UNI_RANGE(5),
92 UNI_RANGE(2),
93 UNI_RANGE(1),
94 UNI_RANGE(0.5),
95 UNI_RANGE(0.2),
96 UNI_RANGE(0.1)
97 }
03aef4b6 98};
0a85b6f0 99
daed6c72
HS		 100static const struct comedi_lrange range_ni_E_ai_limited = {
101 8, {
102 BIP_RANGE(10),
103 BIP_RANGE(5),
104 BIP_RANGE(1),
105 BIP_RANGE(0.1),
106 UNI_RANGE(10),
107 UNI_RANGE(5),
108 UNI_RANGE(1),
109 UNI_RANGE(0.1)
110 }
03aef4b6 111};
0a85b6f0 112
daed6c72
HS		 113static const struct comedi_lrange range_ni_E_ai_limited14 = {
114 14, {
115 BIP_RANGE(10),
116 BIP_RANGE(5),
117 BIP_RANGE(2),
118 BIP_RANGE(1),
119 BIP_RANGE(0.5),
120 BIP_RANGE(0.2),
121 BIP_RANGE(0.1),
122 UNI_RANGE(10),
123 UNI_RANGE(5),
124 UNI_RANGE(2),
125 UNI_RANGE(1),
126 UNI_RANGE(0.5),
127 UNI_RANGE(0.2),
128 UNI_RANGE(0.1)
129 }
03aef4b6 130};
0a85b6f0 131
daed6c72
HS		 132static const struct comedi_lrange range_ni_E_ai_bipolar4 = {
133 4, {
134 BIP_RANGE(10),
135 BIP_RANGE(5),
136 BIP_RANGE(0.5),
137 BIP_RANGE(0.05)
138 }
03aef4b6 139};
0a85b6f0 140
daed6c72
HS		 141static const struct comedi_lrange range_ni_E_ai_611x = {
142 8, {
143 BIP_RANGE(50),
144 BIP_RANGE(20),
145 BIP_RANGE(10),
146 BIP_RANGE(5),
147 BIP_RANGE(2),
148 BIP_RANGE(1),
149 BIP_RANGE(0.5),
150 BIP_RANGE(0.2)
151 }
03aef4b6 152};
0a85b6f0 153
daed6c72
HS		 154static const struct comedi_lrange range_ni_M_ai_622x = {
155 4, {
156 BIP_RANGE(10),
157 BIP_RANGE(5),
158 BIP_RANGE(1),
159 BIP_RANGE(0.2)
160 }
03aef4b6 161};
0a85b6f0 162
daed6c72
HS		 163static const struct comedi_lrange range_ni_M_ai_628x = {
164 7, {
165 BIP_RANGE(10),
166 BIP_RANGE(5),
167 BIP_RANGE(2),
168 BIP_RANGE(1),
169 BIP_RANGE(0.5),
170 BIP_RANGE(0.2),
171 BIP_RANGE(0.1)
172 }
03aef4b6 173};
0a85b6f0 174
daed6c72
HS		 175static const struct comedi_lrange range_ni_E_ao_ext = {
176 4, {
177 BIP_RANGE(10),
178 UNI_RANGE(10),
179 RANGE_ext(-1, 1),
180 RANGE_ext(0, 1)
181 }
03aef4b6
DS		 182};
183
9ced1de6 184static const struct comedi_lrange *const ni_range_lkup[] = {
03aef4b6
DS		 185 [ai_gain_16] = &range_ni_E_ai,
186 [ai_gain_8] = &range_ni_E_ai_limited,
187 [ai_gain_14] = &range_ni_E_ai_limited14,
188 [ai_gain_4] = &range_ni_E_ai_bipolar4,
189 [ai_gain_611x] = &range_ni_E_ai_611x,
190 [ai_gain_622x] = &range_ni_M_ai_622x,
191 [ai_gain_628x] = &range_ni_M_ai_628x,
50708d98 192 [ai_gain_6143] = &range_bipolar5
03aef4b6
DS		 193};
194
03aef4b6
DS		 195enum aimodes {
196 AIMODE_NONE = 0,
197 AIMODE_HALF_FULL = 1,
198 AIMODE_SCAN = 2,
199 AIMODE_SAMPLE = 3,
200};
201
202enum ni_common_subdevices {
203 NI_AI_SUBDEV,
204 NI_AO_SUBDEV,
205 NI_DIO_SUBDEV,
206 NI_8255_DIO_SUBDEV,
207 NI_UNUSED_SUBDEV,
208 NI_CALIBRATION_SUBDEV,
209 NI_EEPROM_SUBDEV,
210 NI_PFI_DIO_SUBDEV,
211 NI_CS5529_CALIBRATION_SUBDEV,
212 NI_SERIAL_SUBDEV,
213 NI_RTSI_SUBDEV,
214 NI_GPCT0_SUBDEV,
215 NI_GPCT1_SUBDEV,
216 NI_FREQ_OUT_SUBDEV,
217 NI_NUM_SUBDEVICES
218};
219static inline unsigned NI_GPCT_SUBDEV(unsigned counter_index)
220{
221 switch (counter_index) {
222 case 0:
223 return NI_GPCT0_SUBDEV;
03aef4b6
DS		 224 case 1:
225 return NI_GPCT1_SUBDEV;
03aef4b6
DS		 226 default:
227 break;
228 }
229 BUG();
230 return NI_GPCT0_SUBDEV;
231}
232
233enum timebase_nanoseconds {
234 TIMEBASE_1_NS = 50,
235 TIMEBASE_2_NS = 10000
236};
237
238#define SERIAL_DISABLED 0
239#define SERIAL_600NS 600
240#define SERIAL_1_2US 1200
241#define SERIAL_10US 10000
242
243static const int num_adc_stages_611x = 3;
244
5a92cac5
HS		 245static void ni_writel(struct comedi_device *dev, uint32_t data, int reg)
246{
5f8a5f4f
HS		 247 if (dev->mmio)
248 writel(data, dev->mmio + reg);
0953ee4a
HS		 249
250 outl(data, dev->iobase + reg);
5a92cac5
HS		 251}
252
253static void ni_writew(struct comedi_device *dev, uint16_t data, int reg)
254{
5f8a5f4f
HS		 255 if (dev->mmio)
256 writew(data, dev->mmio + reg);
0953ee4a
HS		 257
258 outw(data, dev->iobase + reg);
5a92cac5
HS		 259}
260
261static void ni_writeb(struct comedi_device *dev, uint8_t data, int reg)
262{
5f8a5f4f
HS		 263 if (dev->mmio)
264 writeb(data, dev->mmio + reg);
0953ee4a
HS		 265
266 outb(data, dev->iobase + reg);
5a92cac5
HS		 267}
268
269static uint32_t ni_readl(struct comedi_device *dev, int reg)
270{
5f8a5f4f
HS		 271 if (dev->mmio)
272 return readl(dev->mmio + reg);
0953ee4a
HS		 273
274 return inl(dev->iobase + reg);
5a92cac5
HS		 275}
276
277static uint16_t ni_readw(struct comedi_device *dev, int reg)
278{
5f8a5f4f
HS		 279 if (dev->mmio)
280 return readw(dev->mmio + reg);
0953ee4a
HS		 281
282 return inw(dev->iobase + reg);
5a92cac5
HS		 283}
284
285static uint8_t ni_readb(struct comedi_device *dev, int reg)
286{
5f8a5f4f
HS		 287 if (dev->mmio)
288 return readb(dev->mmio + reg);
0953ee4a
HS		 289
290 return inb(dev->iobase + reg);
5a92cac5
HS		 291}
292
b30f0d0c
HS		 293/*
294 * We automatically take advantage of STC registers that can be
295 * read/written directly in the I/O space of the board.
296 *
297 * The AT-MIO and DAQCard devices map the low 8 STC registers to
298 * iobase+reg*2.
299 *
300 * Most PCIMIO devices also map the low 8 STC registers but the
301 * 611x devices map the read registers to iobase+(addr-1)*2.
302 * For now non-windowed STC access is disabled if a PCIMIO device
303 * is detected (devpriv->mite has been initialized).
304 *
305 * The M series devices do not used windowed registers for the
306 * STC registers. The functions below handle the mapping of the
307 * windowed STC registers to the m series register offsets.
308 */
309
05dd0c9f
HS		 310struct mio_regmap {
311 unsigned int mio_reg;
312 int size;
313};
314
315static const struct mio_regmap m_series_stc_write_regmap[] = {
480456d3 316 [NISTC_INTA_ACK_REG] = { 0x104, 2 },
4a6de832 317 [NISTC_INTB_ACK_REG] = { 0x106, 2 },
a1da35a5 318 [NISTC_AI_CMD2_REG] = { 0x108, 2 },
382b3c4f 319 [NISTC_AO_CMD2_REG] = { 0x10a, 2 },
5fa2fa44
HS		 320 [NISTC_G0_CMD_REG] = { 0x10c, 2 },
321 [NISTC_G1_CMD_REG] = { 0x10e, 2 },
4c4d715a 322 [NISTC_AI_CMD1_REG] = { 0x110, 2 },
7bfcc2d4 323 [NISTC_AO_CMD1_REG] = { 0x112, 2 },
975b6d25 324 /*
05aafeea 325 * NISTC_DIO_OUT_REG maps to:
975b6d25
HS		 326 * { NI_M_DIO_REG, 4 } and { NI_M_SCXI_SER_DO_REG, 1 }
327 */
05aafeea 328 [NISTC_DIO_OUT_REG] = { 0, 0 }, /* DOES NOT MAP CLEANLY */
59a97c3c 329 [NISTC_DIO_CTRL_REG] = { 0, 0 }, /* DOES NOT MAP CLEANLY */
bd358f5e 330 [NISTC_AI_MODE1_REG] = { 0x118, 2 },
b134cc58 331 [NISTC_AI_MODE2_REG] = { 0x11a, 2 },
a2c53736
HS		 332 [NISTC_AI_SI_LOADA_REG] = { 0x11c, 4 },
333 [NISTC_AI_SI_LOADB_REG] = { 0x120, 4 },
334 [NISTC_AI_SC_LOADA_REG] = { 0x124, 4 },
335 [NISTC_AI_SC_LOADB_REG] = { 0x128, 4 },
336 [NISTC_AI_SI2_LOADA_REG] = { 0x12c, 4 },
337 [NISTC_AI_SI2_LOADB_REG] = { 0x130, 4 },
aff27008
HS		 338 [NISTC_G0_MODE_REG] = { 0x134, 2 },
339 [NISTC_G1_MODE_REG] = { 0x136, 2 },
340 [NISTC_G0_LOADA_REG] = { 0x138, 4 },
341 [NISTC_G0_LOADB_REG] = { 0x13c, 4 },
342 [NISTC_G1_LOADA_REG] = { 0x140, 4 },
343 [NISTC_G1_LOADB_REG] = { 0x144, 4 },
344 [NISTC_G0_INPUT_SEL_REG] = { 0x148, 2 },
345 [NISTC_G1_INPUT_SEL_REG] = { 0x14a, 2 },
4e5ce0a8 346 [NISTC_AO_MODE1_REG] = { 0x14c, 2 },
ec8bf725 347 [NISTC_AO_MODE2_REG] = { 0x14e, 2 },
37e0ecee
HS		 348 [NISTC_AO_UI_LOADA_REG] = { 0x150, 4 },
349 [NISTC_AO_UI_LOADB_REG] = { 0x154, 4 },
350 [NISTC_AO_BC_LOADA_REG] = { 0x158, 4 },
351 [NISTC_AO_BC_LOADB_REG] = { 0x15c, 4 },
352 [NISTC_AO_UC_LOADA_REG] = { 0x160, 4 },
353 [NISTC_AO_UC_LOADB_REG] = { 0x164, 4 },
a47fc02b 354 [NISTC_CLK_FOUT_REG] = { 0x170, 2 },
5ecadf8c 355 [NISTC_IO_BIDIR_PIN_REG] = { 0x172, 2 },
a4f18b1c 356 [NISTC_RTSI_TRIG_DIR_REG] = { 0x174, 2 },
d8f62c46 357 [NISTC_INT_CTRL_REG] = { 0x176, 2 },
aa9d73ba 358 [NISTC_AI_OUT_CTRL_REG] = { 0x178, 2 },
27cf6c02 359 [NISTC_ATRIG_ETC_REG] = { 0x17a, 2 },
3e908892 360 [NISTC_AI_START_STOP_REG] = { 0x17c, 2 },
f878071a 361 [NISTC_AI_TRIG_SEL_REG] = { 0x17e, 2 },
af5102a7 362 [NISTC_AI_DIV_LOADA_REG] = { 0x180, 4 },
2b6285da 363 [NISTC_AO_START_SEL_REG] = { 0x184, 2 },
f21844d3 364 [NISTC_AO_TRIG_SEL_REG] = { 0x186, 2 },
38aba4c9
HS		 365 [NISTC_G0_AUTOINC_REG] = { 0x188, 2 },
366 [NISTC_G1_AUTOINC_REG] = { 0x18a, 2 },
72bca4f5 367 [NISTC_AO_MODE3_REG] = { 0x18c, 2 },
707502f3 368 [NISTC_RESET_REG] = { 0x190, 2 },
5cca26aa 369 [NISTC_INTA_ENA_REG] = { 0x192, 2 },
d84e9c34 370 [NISTC_INTA2_ENA_REG] = { 0, 0 }, /* E-Series only */
4c9c1d2c 371 [NISTC_INTB_ENA_REG] = { 0x196, 2 },
04b68467 372 [NISTC_INTB2_ENA_REG] = { 0, 0 }, /* E-Series only */
c1b74035 373 [NISTC_AI_PERSONAL_REG] = { 0x19a, 2 },
63ff3f2c 374 [NISTC_AO_PERSONAL_REG] = { 0x19c, 2 },
390bc6ff
HS		 375 [NISTC_RTSI_TRIGA_OUT_REG] = { 0x19e, 2 },
376 [NISTC_RTSI_TRIGB_OUT_REG] = { 0x1a0, 2 },
24a11ba6 377 [NISTC_RTSI_BOARD_REG] = { 0, 0 }, /* Unknown */
8102f3d0
HS		 378 [NISTC_CFG_MEM_CLR_REG] = { 0x1a4, 2 },
379 [NISTC_ADC_FIFO_CLR_REG] = { 0x1a6, 2 },
380 [NISTC_DAC_FIFO_CLR_REG] = { 0x1a8, 2 },
5bd1c728 381 [NISTC_AO_OUT_CTRL_REG] = { 0x1ac, 2 },
c7edadc1 382 [NISTC_AI_MODE3_REG] = { 0x1ae, 2 },
05dd0c9f
HS		 383};
384
385static void m_series_stc_write(struct comedi_device *dev,
386 unsigned int data, unsigned int reg)
00b14b1d 387{
05dd0c9f 388 const struct mio_regmap *regmap;
b30f0d0c 389
05dd0c9f
HS		 390 if (reg < ARRAY_SIZE(m_series_stc_write_regmap)) {
391 regmap = &m_series_stc_write_regmap[reg];
392 } else {
393 dev_warn(dev->class_dev, "%s: unhandled register=0x%x\n",
b30f0d0c
HS		 394 __func__, reg);
395 return;
396 }
b30f0d0c 397
05dd0c9f
HS		 398 switch (regmap->size) {
399 case 4:
400 ni_writel(dev, data, regmap->mio_reg);
b30f0d0c 401 break;
05dd0c9f
HS		 402 case 2:
403 ni_writew(dev, data, regmap->mio_reg);
b30f0d0c 404 break;
b30f0d0c 405 default:
05dd0c9f 406 dev_warn(dev->class_dev, "%s: unmapped register=0x%x\n",
b30f0d0c 407 __func__, reg);
05dd0c9f 408 break;
b30f0d0c 409 }
b30f0d0c
HS		 410}
411
05dd0c9f 412static const struct mio_regmap m_series_stc_read_regmap[] = {
7b14fffd 413 [NISTC_AI_STATUS1_REG] = { 0x104, 2 },
d123ee3c 414 [NISTC_AO_STATUS1_REG] = { 0x106, 2 },
7f0e1bac 415 [NISTC_G01_STATUS_REG] = { 0x108, 2 },
3ca18fef 416 [NISTC_AI_STATUS2_REG] = { 0, 0 }, /* Unknown */
63b2bb05 417 [NISTC_AO_STATUS2_REG] = { 0x10c, 2 },
6f764a47 418 [NISTC_DIO_IN_REG] = { 0, 0 }, /* Unknown */
27650d99
HS		 419 [NISTC_G0_HW_SAVE_REG] = { 0x110, 4 },
420 [NISTC_G1_HW_SAVE_REG] = { 0x114, 4 },
d9c4115f
HS		 421 [NISTC_G0_SAVE_REG] = { 0x118, 4 },
422 [NISTC_G1_SAVE_REG] = { 0x11c, 4 },
2c090acd
HS		 423 [NISTC_AO_UI_SAVE_REG] = { 0x120, 4 },
424 [NISTC_AO_BC_SAVE_REG] = { 0x124, 4 },
425 [NISTC_AO_UC_SAVE_REG] = { 0x128, 4 },
d3fed081 426 [NISTC_STATUS1_REG] = { 0x136, 2 },
8fbb0154 427 [NISTC_DIO_SERIAL_IN_REG] = { 0x009, 1 },
bab382ef 428 [NISTC_STATUS2_REG] = { 0x13a, 2 },
549835c7
HS		 429 [NISTC_AI_SI_SAVE_REG] = { 0x180, 4 },
430 [NISTC_AI_SC_SAVE_REG] = { 0x184, 4 },
05dd0c9f
HS		 431};
432
433static unsigned int m_series_stc_read(struct comedi_device *dev,
434 unsigned int reg)
b30f0d0c 435{
05dd0c9f 436 const struct mio_regmap *regmap;
00b14b1d 437
05dd0c9f
HS		 438 if (reg < ARRAY_SIZE(m_series_stc_read_regmap)) {
439 regmap = &m_series_stc_read_regmap[reg];
440 } else {
441 dev_warn(dev->class_dev, "%s: unhandled register=0x%x\n",
b30f0d0c
HS		 442 __func__, reg);
443 return 0;
444 }
b30f0d0c 445
05dd0c9f
HS		 446 switch (regmap->size) {
447 case 4:
448 return ni_readl(dev, regmap->mio_reg);
449 case 2:
450 return ni_readw(dev, regmap->mio_reg);
451 case 1:
452 return ni_readb(dev, regmap->mio_reg);
b30f0d0c 453 default:
05dd0c9f 454 dev_warn(dev->class_dev, "%s: unmapped register=0x%x\n",
b30f0d0c
HS		 455 __func__, reg);
456 return 0;
457 }
00b14b1d
HS		 458}
459
460static void ni_stc_writew(struct comedi_device *dev, uint16_t data, int reg)
461{
462 struct ni_private *devpriv = dev->private;
b30f0d0c 463 unsigned long flags;
00b14b1d 464
b30f0d0c 465 if (devpriv->is_m_series) {
05dd0c9f 466 m_series_stc_write(dev, data, reg);
b30f0d0c
HS		 467 } else {
468 spin_lock_irqsave(&devpriv->window_lock, flags);
469 if (!devpriv->mite && reg < 8) {
470 ni_writew(dev, data, reg * 2);
471 } else {
4f809ff5
HS		 472 ni_writew(dev, reg, NI_E_STC_WINDOW_ADDR_REG);
473 ni_writew(dev, data, NI_E_STC_WINDOW_DATA_REG);
b30f0d0c
HS		 474 }
475 spin_unlock_irqrestore(&devpriv->window_lock, flags);
476 }
00b14b1d
HS		 477}
478
b30f0d0c 479static void ni_stc_writel(struct comedi_device *dev, uint32_t data, int reg)
00b14b1d
HS		 480{
481 struct ni_private *devpriv = dev->private;
482
b30f0d0c 483 if (devpriv->is_m_series) {
05dd0c9f 484 m_series_stc_write(dev, data, reg);
b30f0d0c
HS		 485 } else {
486 ni_stc_writew(dev, data >> 16, reg);
487 ni_stc_writew(dev, data & 0xffff, reg + 1);
488 }
00b14b1d
HS		 489}
490
491static uint16_t ni_stc_readw(struct comedi_device *dev, int reg)
492{
493 struct ni_private *devpriv = dev->private;
b30f0d0c
HS		 494 unsigned long flags;
495 uint16_t val;
00b14b1d 496
b30f0d0c 497 if (devpriv->is_m_series) {
05dd0c9f 498 val = m_series_stc_read(dev, reg);
b30f0d0c
HS		 499 } else {
500 spin_lock_irqsave(&devpriv->window_lock, flags);
501 if (!devpriv->mite && reg < 8) {
502 val = ni_readw(dev, reg * 2);
503 } else {
4f809ff5
HS		 504 ni_writew(dev, reg, NI_E_STC_WINDOW_ADDR_REG);
505 val = ni_readw(dev, NI_E_STC_WINDOW_DATA_REG);
b30f0d0c
HS		 506 }
507 spin_unlock_irqrestore(&devpriv->window_lock, flags);
508 }
509 return val;
510}
511
512static uint32_t ni_stc_readl(struct comedi_device *dev, int reg)
513{
514 struct ni_private *devpriv = dev->private;
515 uint32_t val;
516
517 if (devpriv->is_m_series) {
05dd0c9f 518 val = m_series_stc_read(dev, reg);
b30f0d0c
HS		 519 } else {
520 val = ni_stc_readw(dev, reg) << 16;
521 val |= ni_stc_readw(dev, reg + 1);
522 }
523 return val;
00b14b1d
HS		 524}
525
da91b269 526static inline void ni_set_bitfield(struct comedi_device *dev, int reg,
0a85b6f0 527 unsigned bit_mask, unsigned bit_values)
03aef4b6 528{
0e05c552 529 struct ni_private *devpriv = dev->private;
03aef4b6
DS		 530 unsigned long flags;
531
5f74ea14 532 spin_lock_irqsave(&devpriv->soft_reg_copy_lock, flags);
03aef4b6 533 switch (reg) {
5cca26aa 534 case NISTC_INTA_ENA_REG:
03aef4b6
DS		 535 devpriv->int_a_enable_reg &= ~bit_mask;
536 devpriv->int_a_enable_reg |= bit_values & bit_mask;
f1618db1 537 ni_stc_writew(dev, devpriv->int_a_enable_reg, reg);
03aef4b6 538 break;
4c9c1d2c 539 case NISTC_INTB_ENA_REG:
03aef4b6
DS		 540 devpriv->int_b_enable_reg &= ~bit_mask;
541 devpriv->int_b_enable_reg |= bit_values & bit_mask;
f1618db1 542 ni_stc_writew(dev, devpriv->int_b_enable_reg, reg);
03aef4b6 543 break;
5ecadf8c 544 case NISTC_IO_BIDIR_PIN_REG:
03aef4b6
DS		 545 devpriv->io_bidirection_pin_reg &= ~bit_mask;
546 devpriv->io_bidirection_pin_reg |= bit_values & bit_mask;
f1618db1 547 ni_stc_writew(dev, devpriv->io_bidirection_pin_reg, reg);
03aef4b6
DS		 548 break;
549 case AI_AO_Select:
550 devpriv->ai_ao_select_reg &= ~bit_mask;
551 devpriv->ai_ao_select_reg |= bit_values & bit_mask;
f1618db1 552 ni_writeb(dev, devpriv->ai_ao_select_reg, reg);
03aef4b6
DS		 553 break;
554 case G0_G1_Select:
555 devpriv->g0_g1_select_reg &= ~bit_mask;
556 devpriv->g0_g1_select_reg |= bit_values & bit_mask;
f1618db1 557 ni_writeb(dev, devpriv->g0_g1_select_reg, reg);
03aef4b6
DS		 558 break;
559 default:
ce82410c
HM		 560 dev_err(dev->class_dev, "called with invalid register %d\n",
561 reg);
03aef4b6
DS		 562 break;
563 }
564 mmiowb();
5f74ea14 565 spin_unlock_irqrestore(&devpriv->soft_reg_copy_lock, flags);
03aef4b6
DS		 566}
567
568#ifdef PCIDMA
03aef4b6
DS		 569/* DMA channel setup */
570
2696fb57 571/* negative channel means no channel */
da91b269 572static inline void ni_set_ai_dma_channel(struct comedi_device *dev, int channel)
03aef4b6
DS		 573{
574 unsigned bitfield;
575
4475cf2e 576 if (channel >= 0)
03aef4b6 577 bitfield =
0a85b6f0
MT		 578 (ni_stc_dma_channel_select_bitfield(channel) <<
579 AI_DMA_Select_Shift) & AI_DMA_Select_Mask;
4475cf2e 580 else
03aef4b6 581 bitfield = 0;
03aef4b6
DS		 582 ni_set_bitfield(dev, AI_AO_Select, AI_DMA_Select_Mask, bitfield);
583}
584
2696fb57 585/* negative channel means no channel */
da91b269 586static inline void ni_set_ao_dma_channel(struct comedi_device *dev, int channel)
03aef4b6
DS		 587{
588 unsigned bitfield;
589
4475cf2e 590 if (channel >= 0)
03aef4b6 591 bitfield =
0a85b6f0
MT		 592 (ni_stc_dma_channel_select_bitfield(channel) <<
593 AO_DMA_Select_Shift) & AO_DMA_Select_Mask;
4475cf2e 594 else
03aef4b6 595 bitfield = 0;
03aef4b6
DS		 596 ni_set_bitfield(dev, AI_AO_Select, AO_DMA_Select_Mask, bitfield);
597}
598
2696fb57 599/* negative mite_channel means no channel */
da91b269 600static inline void ni_set_gpct_dma_channel(struct comedi_device *dev,
0a85b6f0
MT		 601 unsigned gpct_index,
602 int mite_channel)
03aef4b6
DS		 603{
604 unsigned bitfield;
605
bc461556 606 if (mite_channel >= 0)
03aef4b6 607 bitfield = GPCT_DMA_Select_Bits(gpct_index, mite_channel);
bc461556 608 else
03aef4b6 609 bitfield = 0;
03aef4b6 610 ni_set_bitfield(dev, G0_G1_Select, GPCT_DMA_Select_Mask(gpct_index),
0a85b6f0 611 bitfield);
03aef4b6
DS		 612}
613
2696fb57 614/* negative mite_channel means no channel */
0a85b6f0
MT		 615static inline void ni_set_cdo_dma_channel(struct comedi_device *dev,
616 int mite_channel)
03aef4b6 617{
0e05c552 618 struct ni_private *devpriv = dev->private;
03aef4b6 619 unsigned long flags;
2dd0825f 620 unsigned bits;
03aef4b6 621
5f74ea14 622 spin_lock_irqsave(&devpriv->soft_reg_copy_lock, flags);
2dd0825f 623 devpriv->cdio_dma_select_reg &= ~NI_M_CDIO_DMA_SEL_CDO_MASK;
03aef4b6 624 if (mite_channel >= 0) {
2dd0825f
HS		 625 /*
626 * XXX just guessing ni_stc_dma_channel_select_bitfield()
627 * returns the right bits, under the assumption the cdio dma
628 * selection works just like ai/ao/gpct.
629 * Definitely works for dma channels 0 and 1.
630 */
631 bits = ni_stc_dma_channel_select_bitfield(mite_channel);
632 devpriv->cdio_dma_select_reg |= NI_M_CDIO_DMA_SEL_CDO(bits);
03aef4b6 633 }
975b6d25 634 ni_writeb(dev, devpriv->cdio_dma_select_reg, NI_M_CDIO_DMA_SEL_REG);
03aef4b6 635 mmiowb();
5f74ea14 636 spin_unlock_irqrestore(&devpriv->soft_reg_copy_lock, flags);
03aef4b6
DS		 637}
638
da91b269 639static int ni_request_ai_mite_channel(struct comedi_device *dev)
03aef4b6 640{
0e05c552 641 struct ni_private *devpriv = dev->private;
03aef4b6
DS		 642 unsigned long flags;
643
5f74ea14 644 spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
03aef4b6
DS		 645 BUG_ON(devpriv->ai_mite_chan);
646 devpriv->ai_mite_chan =
0a85b6f0 647 mite_request_channel(devpriv->mite, devpriv->ai_mite_ring);
c6be1548 648 if (!devpriv->ai_mite_chan) {
0a85b6f0 649 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
5ac1d82b
HS		 650 dev_err(dev->class_dev,
651 "failed to reserve mite dma channel for analog input\n");
03aef4b6
DS		 652 return -EBUSY;
653 }
654 devpriv->ai_mite_chan->dir = COMEDI_INPUT;
655 ni_set_ai_dma_channel(dev, devpriv->ai_mite_chan->channel);
5f74ea14 656 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
03aef4b6
DS		 657 return 0;
658}
659
da91b269 660static int ni_request_ao_mite_channel(struct comedi_device *dev)
03aef4b6 661{
0e05c552 662 struct ni_private *devpriv = dev->private;
03aef4b6
DS		 663 unsigned long flags;
664
5f74ea14 665 spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
03aef4b6
DS		 666 BUG_ON(devpriv->ao_mite_chan);
667 devpriv->ao_mite_chan =
0a85b6f0 668 mite_request_channel(devpriv->mite, devpriv->ao_mite_ring);
c6be1548 669 if (!devpriv->ao_mite_chan) {
0a85b6f0 670 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
5ac1d82b
HS		 671 dev_err(dev->class_dev,
672 "failed to reserve mite dma channel for analog outut\n");
03aef4b6
DS		 673 return -EBUSY;
674 }
675 devpriv->ao_mite_chan->dir = COMEDI_OUTPUT;
676 ni_set_ao_dma_channel(dev, devpriv->ao_mite_chan->channel);
5f74ea14 677 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
03aef4b6
DS		 678 return 0;
679}
680
da91b269 681static int ni_request_gpct_mite_channel(struct comedi_device *dev,
0a85b6f0
MT		 682 unsigned gpct_index,
683 enum comedi_io_direction direction)
03aef4b6 684{
0e05c552 685 struct ni_private *devpriv = dev->private;
03aef4b6
DS		 686 unsigned long flags;
687 struct mite_channel *mite_chan;
688
689 BUG_ON(gpct_index >= NUM_GPCT);
5f74ea14 690 spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
03aef4b6
DS		 691 BUG_ON(devpriv->counter_dev->counters[gpct_index].mite_chan);
692 mite_chan =
0a85b6f0
MT		 693 mite_request_channel(devpriv->mite,
694 devpriv->gpct_mite_ring[gpct_index]);
c6be1548 695 if (!mite_chan) {
0a85b6f0 696 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
5ac1d82b
HS		 697 dev_err(dev->class_dev,
698 "failed to reserve mite dma channel for counter\n");
03aef4b6
DS		 699 return -EBUSY;
700 }
701 mite_chan->dir = direction;
702 ni_tio_set_mite_channel(&devpriv->counter_dev->counters[gpct_index],
0a85b6f0 703 mite_chan);
03aef4b6 704 ni_set_gpct_dma_channel(dev, gpct_index, mite_chan->channel);
5f74ea14 705 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
03aef4b6
DS		 706 return 0;
707}
708
2696fb57 709#endif /* PCIDMA */
03aef4b6 710
da91b269 711static int ni_request_cdo_mite_channel(struct comedi_device *dev)
03aef4b6
DS		 712{
713#ifdef PCIDMA
0e05c552 714 struct ni_private *devpriv = dev->private;
03aef4b6
DS		 715 unsigned long flags;
716
5f74ea14 717 spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
03aef4b6
DS		 718 BUG_ON(devpriv->cdo_mite_chan);
719 devpriv->cdo_mite_chan =
0a85b6f0 720 mite_request_channel(devpriv->mite, devpriv->cdo_mite_ring);
c6be1548 721 if (!devpriv->cdo_mite_chan) {
0a85b6f0 722 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
5ac1d82b
HS		 723 dev_err(dev->class_dev,
724 "failed to reserve mite dma channel for correlated digital output\n");
03aef4b6
DS		 725 return -EBUSY;
726 }
727 devpriv->cdo_mite_chan->dir = COMEDI_OUTPUT;
728 ni_set_cdo_dma_channel(dev, devpriv->cdo_mite_chan->channel);
5f74ea14 729 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
2696fb57 730#endif /* PCIDMA */
03aef4b6
DS		 731 return 0;
732}
733
da91b269 734static void ni_release_ai_mite_channel(struct comedi_device *dev)
03aef4b6
DS		 735{
736#ifdef PCIDMA
0e05c552 737 struct ni_private *devpriv = dev->private;
03aef4b6
DS		 738 unsigned long flags;
739
5f74ea14 740 spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
03aef4b6
DS		 741 if (devpriv->ai_mite_chan) {
742 ni_set_ai_dma_channel(dev, -1);
743 mite_release_channel(devpriv->ai_mite_chan);
744 devpriv->ai_mite_chan = NULL;
745 }
5f74ea14 746 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
2696fb57 747#endif /* PCIDMA */
03aef4b6
DS		 748}
749
da91b269 750static void ni_release_ao_mite_channel(struct comedi_device *dev)
03aef4b6
DS		 751{
752#ifdef PCIDMA
0e05c552 753 struct ni_private *devpriv = dev->private;
03aef4b6
DS		 754 unsigned long flags;
755
5f74ea14 756 spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
03aef4b6
DS		 757 if (devpriv->ao_mite_chan) {
758 ni_set_ao_dma_channel(dev, -1);
759 mite_release_channel(devpriv->ao_mite_chan);
760 devpriv->ao_mite_chan = NULL;
761 }
5f74ea14 762 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
2696fb57 763#endif /* PCIDMA */
03aef4b6
DS		 764}
765
03aef4b6 766#ifdef PCIDMA
29aba763
HS		 767static void ni_release_gpct_mite_channel(struct comedi_device *dev,
768 unsigned gpct_index)
769{
0e05c552 770 struct ni_private *devpriv = dev->private;
03aef4b6
DS		 771 unsigned long flags;
772
773 BUG_ON(gpct_index >= NUM_GPCT);
5f74ea14 774 spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
03aef4b6
DS		 775 if (devpriv->counter_dev->counters[gpct_index].mite_chan) {
776 struct mite_channel *mite_chan =
0a85b6f0 777 devpriv->counter_dev->counters[gpct_index].mite_chan;
03aef4b6
DS		 778
779 ni_set_gpct_dma_channel(dev, gpct_index, -1);
0a85b6f0
MT		 780 ni_tio_set_mite_channel(&devpriv->
781 counter_dev->counters[gpct_index],
782 NULL);
03aef4b6
DS		 783 mite_release_channel(mite_chan);
784 }
5f74ea14 785 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
03aef4b6 786}
29aba763 787#endif /* PCIDMA */
03aef4b6 788
da91b269 789static void ni_release_cdo_mite_channel(struct comedi_device *dev)
03aef4b6
DS		 790{
791#ifdef PCIDMA
0e05c552 792 struct ni_private *devpriv = dev->private;
03aef4b6
DS		 793 unsigned long flags;
794
5f74ea14 795 spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
03aef4b6
DS		 796 if (devpriv->cdo_mite_chan) {
797 ni_set_cdo_dma_channel(dev, -1);
798 mite_release_channel(devpriv->cdo_mite_chan);
799 devpriv->cdo_mite_chan = NULL;
800 }
5f74ea14 801 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
2696fb57 802#endif /* PCIDMA */
03aef4b6
DS		 803}
804
03aef4b6 805#ifdef PCIDMA
da91b269 806static void ni_e_series_enable_second_irq(struct comedi_device *dev,
0a85b6f0 807 unsigned gpct_index, short enable)
03aef4b6 808{
0e05c552 809 struct ni_private *devpriv = dev->private;
5f315520
HS		 810 uint16_t val = 0;
811 int reg;
0e05c552 812
5f315520 813 if (devpriv->is_m_series || gpct_index > 1)
03aef4b6 814 return;
5f315520
HS		 815
816 /*
817 * e-series boards use the second irq signals to generate
818 * dma requests for their counters
819 */
820 if (gpct_index == 0) {
d84e9c34 821 reg = NISTC_INTA2_ENA_REG;
5f315520 822 if (enable)
d84e9c34 823 val = NISTC_INTA_ENA_G0_GATE;
5f315520 824 } else {
04b68467 825 reg = NISTC_INTB2_ENA_REG;
5f315520 826 if (enable)
04b68467 827 val = NISTC_INTB_ENA_G1_GATE;
03aef4b6 828 }
00b14b1d 829 ni_stc_writew(dev, val, reg);
03aef4b6 830}
2696fb57 831#endif /* PCIDMA */
03aef4b6 832
da91b269 833static void ni_clear_ai_fifo(struct comedi_device *dev)
03aef4b6 834{
a52b53e4 835 struct ni_private *devpriv = dev->private;
60738f60
CS		 836 static const int timeout = 10000;
837 int i;
0e05c552 838
a52b53e4 839 if (devpriv->is_6143) {
2696fb57 840 /* Flush the 6143 data FIFO */
5a92cac5
HS		 841 ni_writel(dev, 0x10, AIFIFO_Control_6143);
842 ni_writel(dev, 0x00, AIFIFO_Control_6143);
60738f60
CS		 843 /* Wait for complete */
844 for (i = 0; i < timeout; i++) {
5a92cac5 845 if (!(ni_readl(dev, AIFIFO_Status_6143) & 0x10))
60738f60
CS		 846 break;
847 udelay(1);
848 }
a6266977 849 if (i == timeout)
5ac1d82b 850 dev_err(dev->class_dev, "FIFO flush timeout\n");
03aef4b6 851 } else {
8102f3d0 852 ni_stc_writew(dev, 1, NISTC_ADC_FIFO_CLR_REG);
a52b53e4 853 if (devpriv->is_625x) {
975b6d25
HS		 854 ni_writeb(dev, 0, NI_M_STATIC_AI_CTRL_REG(0));
855 ni_writeb(dev, 1, NI_M_STATIC_AI_CTRL_REG(0));
03aef4b6
DS		 856#if 0
857 /* the NI example code does 3 convert pulses for 625x boards,
858 but that appears to be wrong in practice. */
4c4d715a
HS		 859 ni_stc_writew(dev, NISTC_AI_CMD1_CONVERT_PULSE,
860 NISTC_AI_CMD1_REG);
861 ni_stc_writew(dev, NISTC_AI_CMD1_CONVERT_PULSE,
862 NISTC_AI_CMD1_REG);
863 ni_stc_writew(dev, NISTC_AI_CMD1_CONVERT_PULSE,
864 NISTC_AI_CMD1_REG);
03aef4b6
DS		 865#endif
866 }
867 }
868}
869
0a85b6f0
MT		 870static inline void ni_ao_win_outw(struct comedi_device *dev, uint16_t data,
871 int addr)
03aef4b6 872{
0e05c552 873 struct ni_private *devpriv = dev->private;
03aef4b6
DS		 874 unsigned long flags;
875
5f74ea14 876 spin_lock_irqsave(&devpriv->window_lock, flags);
5a92cac5
HS		 877 ni_writew(dev, addr, AO_Window_Address_611x);
878 ni_writew(dev, data, AO_Window_Data_611x);
5f74ea14 879 spin_unlock_irqrestore(&devpriv->window_lock, flags);
03aef4b6
DS		 880}
881
0a85b6f0
MT		 882static inline void ni_ao_win_outl(struct comedi_device *dev, uint32_t data,
883 int addr)
03aef4b6 884{
0e05c552 885 struct ni_private *devpriv = dev->private;
03aef4b6
DS		 886 unsigned long flags;
887
5f74ea14 888 spin_lock_irqsave(&devpriv->window_lock, flags);
5a92cac5
HS		 889 ni_writew(dev, addr, AO_Window_Address_611x);
890 ni_writel(dev, data, AO_Window_Data_611x);
5f74ea14 891 spin_unlock_irqrestore(&devpriv->window_lock, flags);
03aef4b6
DS		 892}
893
da91b269 894static inline unsigned short ni_ao_win_inw(struct comedi_device *dev, int addr)
03aef4b6 895{
0e05c552 896 struct ni_private *devpriv = dev->private;
03aef4b6
DS		 897 unsigned long flags;
898 unsigned short data;
899
5f74ea14 900 spin_lock_irqsave(&devpriv->window_lock, flags);
5a92cac5
HS		 901 ni_writew(dev, addr, AO_Window_Address_611x);
902 data = ni_readw(dev, AO_Window_Data_611x);
5f74ea14 903 spin_unlock_irqrestore(&devpriv->window_lock, flags);
03aef4b6
DS		 904 return data;
905}
906
907/* ni_set_bits( ) allows different parts of the ni_mio_common driver to
908* share registers (such as Interrupt_A_Register) without interfering with
909* each other.
910*
911* NOTE: the switch/case statements are optimized out for a constant argument
912* so this is actually quite fast--- If you must wrap another function around this
913* make it inline to avoid a large speed penalty.
914*
915* value should only be 1 or 0.
916*/
0a85b6f0
MT		 917static inline void ni_set_bits(struct comedi_device *dev, int reg,
918 unsigned bits, unsigned value)
03aef4b6
DS		 919{
920 unsigned bit_values;
921
922 if (value)
923 bit_values = bits;
924 else
925 bit_values = 0;
926 ni_set_bitfield(dev, reg, bits, bit_values);
927}
928
03aef4b6 929#ifdef PCIDMA
da91b269 930static void ni_sync_ai_dma(struct comedi_device *dev)
03aef4b6 931{
0e05c552 932 struct ni_private *devpriv = dev->private;
5dce16e5 933 struct comedi_subdevice *s = dev->read_subdev;
03aef4b6
DS		 934 unsigned long flags;
935
5f74ea14 936 spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
03aef4b6 937 if (devpriv->ai_mite_chan)
74f63db7 938 mite_sync_input_dma(devpriv->ai_mite_chan, s);
5f74ea14 939 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
03aef4b6
DS		 940}
941
2655c8a1
HS		 942static int ni_ai_drain_dma(struct comedi_device *dev)
943{
944 struct ni_private *devpriv = dev->private;
945 int i;
946 static const int timeout = 10000;
947 unsigned long flags;
948 int retval = 0;
949
950 spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
951 if (devpriv->ai_mite_chan) {
952 for (i = 0; i < timeout; i++) {
7b14fffd
HS		 953 if ((ni_stc_readw(dev, NISTC_AI_STATUS1_REG) &
954 NISTC_AI_STATUS1_FIFO_E)
2655c8a1
HS		 955 && mite_bytes_in_transit(devpriv->ai_mite_chan) ==
956 0)
957 break;
958 udelay(5);
959 }
960 if (i == timeout) {
cd25503f 961 dev_err(dev->class_dev, "timed out\n");
89c4695e
HS		 962 dev_err(dev->class_dev,
963 "mite_bytes_in_transit=%i, AI_Status1_Register=0x%x\n",
964 mite_bytes_in_transit(devpriv->ai_mite_chan),
7b14fffd 965 ni_stc_readw(dev, NISTC_AI_STATUS1_REG));
2655c8a1
HS		 966 retval = -1;
967 }
968 }
969 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
970
971 ni_sync_ai_dma(dev);
972
973 return retval;
974}
975
0a85b6f0
MT		 976static void mite_handle_b_linkc(struct mite_struct *mite,
977 struct comedi_device *dev)
03aef4b6 978{
0e05c552 979 struct ni_private *devpriv = dev->private;
e879c315 980 struct comedi_subdevice *s = dev->write_subdev;
03aef4b6
DS		 981 unsigned long flags;
982
5f74ea14 983 spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
bc461556 984 if (devpriv->ao_mite_chan)
1e575a9c 985 mite_sync_output_dma(devpriv->ao_mite_chan, s);
5f74ea14 986 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
03aef4b6
DS		 987}
988
da91b269 989static int ni_ao_wait_for_dma_load(struct comedi_device *dev)
03aef4b6
DS		 990{
991 static const int timeout = 10000;
992 int i;
f7401979 993
03aef4b6
DS		 994 for (i = 0; i < timeout; i++) {
995 unsigned short b_status;
996
d123ee3c
HS		 997 b_status = ni_stc_readw(dev, NISTC_AO_STATUS1_REG);
998 if (b_status & NISTC_AO_STATUS1_FIFO_HF)
03aef4b6
DS		 999 break;
1000 /* if we poll too often, the pci bus activity seems
1001 to slow the dma transfer down */
5f74ea14 1002 udelay(10);
03aef4b6
DS		 1003 }
1004 if (i == timeout) {
5ac1d82b 1005 dev_err(dev->class_dev, "timed out waiting for dma load\n");
03aef4b6
DS		 1006 return -EPIPE;
1007 }
1008 return 0;
1009}
2696fb57 1010#endif /* PCIDMA */
f8246dfa 1011
2ffb2476
HS		 1012#ifndef PCIDMA
1013
1014static void ni_ao_fifo_load(struct comedi_device *dev,
1015 struct comedi_subdevice *s, int n)
1016{
a52b53e4 1017 struct ni_private *devpriv = dev->private;
2ffb2476
HS		 1018 int i;
1019 unsigned short d;
1020 u32 packed_data;
2ffb2476 1021
2ffb2476 1022 for (i = 0; i < n; i++) {
e14c6a60 1023 comedi_buf_read_samples(s, &d, 1);
2ffb2476 1024
a52b53e4 1025 if (devpriv->is_6xxx) {
2ffb2476
HS		 1026 packed_data = d & 0xffff;
1027 /* 6711 only has 16 bit wide ao fifo */
a52b53e4 1028 if (!devpriv->is_6711) {
e14c6a60 1029 comedi_buf_read_samples(s, &d, 1);
2ffb2476
HS		 1030 i++;
1031 packed_data |= (d << 16) & 0xffff0000;
1032 }
5a92cac5 1033 ni_writel(dev, packed_data, DAC_FIFO_Data_611x);
2ffb2476 1034 } else {
5a92cac5 1035 ni_writew(dev, d, DAC_FIFO_Data);
2ffb2476 1036 }
2ffb2476 1037 }
2ffb2476
HS		 1038}
1039
1040/*
1041 * There's a small problem if the FIFO gets really low and we
1042 * don't have the data to fill it. Basically, if after we fill
1043 * the FIFO with all the data available, the FIFO is _still_
1044 * less than half full, we never clear the interrupt. If the
1045 * IRQ is in edge mode, we never get another interrupt, because
1046 * this one wasn't cleared. If in level mode, we get flooded
1047 * with interrupts that we can't fulfill, because nothing ever
1048 * gets put into the buffer.
1049 *
1050 * This kind of situation is recoverable, but it is easier to
1051 * just pretend we had a FIFO underrun, since there is a good
1052 * chance it will happen anyway. This is _not_ the case for
1053 * RT code, as RT code might purposely be running close to the
1054 * metal. Needs to be fixed eventually.
1055 */
1056static int ni_ao_fifo_half_empty(struct comedi_device *dev,
1057 struct comedi_subdevice *s)
1058{
7cf94adc 1059 const struct ni_board_struct *board = dev->board_ptr;
836b571d
HS		 1060 unsigned int nbytes;
1061 unsigned int nsamples;
2ffb2476 1062
836b571d
HS		 1063 nbytes = comedi_buf_read_n_available(s);
1064 if (nbytes == 0) {
2ffb2476
HS		 1065 s->async->events |= COMEDI_CB_OVERFLOW;
1066 return 0;
1067 }
1068
836b571d
HS		 1069 nsamples = comedi_bytes_to_samples(s, nbytes);
1070 if (nsamples > board->ao_fifo_depth / 2)
1071 nsamples = board->ao_fifo_depth / 2;
2ffb2476 1072
836b571d 1073 ni_ao_fifo_load(dev, s, nsamples);
2ffb2476 1074
2ffb2476
HS		 1075 return 1;
1076}
1077
1078static int ni_ao_prep_fifo(struct comedi_device *dev,
1079 struct comedi_subdevice *s)
1080{
7cf94adc 1081 const struct ni_board_struct *board = dev->board_ptr;
a52b53e4 1082 struct ni_private *devpriv = dev->private;
836b571d
HS		 1083 unsigned int nbytes;
1084 unsigned int nsamples;
2ffb2476
HS		 1085
1086 /* reset fifo */
8102f3d0 1087 ni_stc_writew(dev, 1, NISTC_DAC_FIFO_CLR_REG);
a52b53e4 1088 if (devpriv->is_6xxx)
2ffb2476
HS		 1089 ni_ao_win_outl(dev, 0x6, AO_FIFO_Offset_Load_611x);
1090
1091 /* load some data */
836b571d
HS		 1092 nbytes = comedi_buf_read_n_available(s);
1093 if (nbytes == 0)
2ffb2476
HS		 1094 return 0;
1095
836b571d
HS		 1096 nsamples = comedi_bytes_to_samples(s, nbytes);
1097 if (nsamples > board->ao_fifo_depth)
1098 nsamples = board->ao_fifo_depth;
2ffb2476 1099
836b571d 1100 ni_ao_fifo_load(dev, s, nsamples);
2ffb2476 1101
836b571d 1102 return nsamples;
2ffb2476
HS		 1103}
1104
1105static void ni_ai_fifo_read(struct comedi_device *dev,
1106 struct comedi_subdevice *s, int n)
1107{
2ffb2476
HS		 1108 struct ni_private *devpriv = dev->private;
1109 struct comedi_async *async = s->async;
9caba329
HS		 1110 u32 dl;
1111 unsigned short data;
2ffb2476
HS		 1112 int i;
1113
a52b53e4 1114 if (devpriv->is_611x) {
2ffb2476 1115 for (i = 0; i < n / 2; i++) {
5a92cac5 1116 dl = ni_readl(dev, ADC_FIFO_Data_611x);
2ffb2476 1117 /* This may get the hi/lo data in the wrong order */
9caba329
HS		 1118 data = (dl >> 16) & 0xffff;
1119 comedi_buf_write_samples(s, &data, 1);
1120 data = dl & 0xffff;
1121 comedi_buf_write_samples(s, &data, 1);
2ffb2476
HS		 1122 }
1123 /* Check if there's a single sample stuck in the FIFO */
1124 if (n % 2) {
5a92cac5 1125 dl = ni_readl(dev, ADC_FIFO_Data_611x);
9caba329
HS		 1126 data = dl & 0xffff;
1127 comedi_buf_write_samples(s, &data, 1);
2ffb2476 1128 }
a52b53e4 1129 } else if (devpriv->is_6143) {
2ffb2476
HS		 1130 /* This just reads the FIFO assuming the data is present, no checks on the FIFO status are performed */
1131 for (i = 0; i < n / 2; i++) {
5a92cac5 1132 dl = ni_readl(dev, AIFIFO_Data_6143);
2ffb2476 1133
9caba329
HS		 1134 data = (dl >> 16) & 0xffff;
1135 comedi_buf_write_samples(s, &data, 1);
1136 data = dl & 0xffff;
1137 comedi_buf_write_samples(s, &data, 1);
2ffb2476
HS		 1138 }
1139 if (n % 2) {
1140 /* Assume there is a single sample stuck in the FIFO */
9c340ac9 1141 /* Get stranded sample into FIFO */
5a92cac5
HS		 1142 ni_writel(dev, 0x01, AIFIFO_Control_6143);
1143 dl = ni_readl(dev, AIFIFO_Data_6143);
9caba329
HS		 1144 data = (dl >> 16) & 0xffff;
1145 comedi_buf_write_samples(s, &data, 1);
2ffb2476
HS		 1146 }
1147 } else {
1148 if (n > sizeof(devpriv->ai_fifo_buffer) /
1149 sizeof(devpriv->ai_fifo_buffer[0])) {
5ac1d82b
HS		 1150 dev_err(dev->class_dev,
1151 "bug! ai_fifo_buffer too small\n");
2ffb2476
HS		 1152 async->events |= COMEDI_CB_ERROR;
1153 return;
1154 }
1155 for (i = 0; i < n; i++) {
1156 devpriv->ai_fifo_buffer[i] =
363f570e 1157 ni_readw(dev, NI_E_AI_FIFO_DATA_REG);
2ffb2476 1158 }
9caba329 1159 comedi_buf_write_samples(s, devpriv->ai_fifo_buffer, n);
2ffb2476
HS		 1160 }
1161}
1162
1163static void ni_handle_fifo_half_full(struct comedi_device *dev)
1164{
7cf94adc 1165 const struct ni_board_struct *board = dev->board_ptr;
5dce16e5 1166 struct comedi_subdevice *s = dev->read_subdev;
2ffb2476
HS		 1167 int n;
1168
1169 n = board->ai_fifo_depth / 2;
1170
1171 ni_ai_fifo_read(dev, s, n);
1172}
1173#endif
1174
1175/*
1176 Empties the AI fifo
1177*/
1178static void ni_handle_fifo_dregs(struct comedi_device *dev)
1179{
2ffb2476 1180 struct ni_private *devpriv = dev->private;
5dce16e5 1181 struct comedi_subdevice *s = dev->read_subdev;
2ffb2476 1182 u32 dl;
9caba329 1183 unsigned short data;
2ffb2476
HS		 1184 unsigned short fifo_empty;
1185 int i;
1186
a52b53e4 1187 if (devpriv->is_611x) {
7b14fffd
HS		 1188 while ((ni_stc_readw(dev, NISTC_AI_STATUS1_REG) &
1189 NISTC_AI_STATUS1_FIFO_E) == 0) {
5a92cac5 1190 dl = ni_readl(dev, ADC_FIFO_Data_611x);
2ffb2476
HS		 1191
1192 /* This may get the hi/lo data in the wrong order */
9caba329
HS		 1193 data = dl >> 16;
1194 comedi_buf_write_samples(s, &data, 1);
1195 data = dl & 0xffff;
1196 comedi_buf_write_samples(s, &data, 1);
2ffb2476 1197 }
a52b53e4 1198 } else if (devpriv->is_6143) {
2ffb2476 1199 i = 0;
5a92cac5
HS		 1200 while (ni_readl(dev, AIFIFO_Status_6143) & 0x04) {
1201 dl = ni_readl(dev, AIFIFO_Data_6143);
2ffb2476
HS		 1202
1203 /* This may get the hi/lo data in the wrong order */
9caba329
HS		 1204 data = dl >> 16;
1205 comedi_buf_write_samples(s, &data, 1);
1206 data = dl & 0xffff;
1207 comedi_buf_write_samples(s, &data, 1);
2ffb2476
HS		 1208 i += 2;
1209 }
1210 /* Check if stranded sample is present */
5a92cac5 1211 if (ni_readl(dev, AIFIFO_Status_6143) & 0x01) {
9c340ac9 1212 /* Get stranded sample into FIFO */
5a92cac5
HS		 1213 ni_writel(dev, 0x01, AIFIFO_Control_6143);
1214 dl = ni_readl(dev, AIFIFO_Data_6143);
9caba329
HS		 1215 data = (dl >> 16) & 0xffff;
1216 comedi_buf_write_samples(s, &data, 1);
2ffb2476
HS		 1217 }
1218
1219 } else {
7b14fffd
HS		 1220 fifo_empty = ni_stc_readw(dev, NISTC_AI_STATUS1_REG) &
1221 NISTC_AI_STATUS1_FIFO_E;
2ffb2476
HS		 1222 while (fifo_empty == 0) {
1223 for (i = 0;
1224 i <
1225 sizeof(devpriv->ai_fifo_buffer) /
1226 sizeof(devpriv->ai_fifo_buffer[0]); i++) {
00b14b1d 1227 fifo_empty = ni_stc_readw(dev,
7b14fffd
HS		 1228 NISTC_AI_STATUS1_REG) &
1229 NISTC_AI_STATUS1_FIFO_E;
2ffb2476
HS		 1230 if (fifo_empty)
1231 break;
1232 devpriv->ai_fifo_buffer[i] =
363f570e 1233 ni_readw(dev, NI_E_AI_FIFO_DATA_REG);
2ffb2476 1234 }
9caba329 1235 comedi_buf_write_samples(s, devpriv->ai_fifo_buffer, i);
2ffb2476
HS		 1236 }
1237 }
1238}
1239
f8f6d91d
HS		 1240static void get_last_sample_611x(struct comedi_device *dev)
1241{
a52b53e4 1242 struct ni_private *devpriv = dev->private;
5dce16e5 1243 struct comedi_subdevice *s = dev->read_subdev;
f8f6d91d
HS		 1244 unsigned short data;
1245 u32 dl;
1246
a52b53e4 1247 if (!devpriv->is_611x)
f8f6d91d
HS		 1248 return;
1249
1250 /* Check if there's a single sample stuck in the FIFO */
906170b8 1251 if (ni_readb(dev, NI_E_STATUS_REG) & 0x80) {
5a92cac5 1252 dl = ni_readl(dev, ADC_FIFO_Data_611x);
f0dff421 1253 data = dl & 0xffff;
9caba329 1254 comedi_buf_write_samples(s, &data, 1);
f8f6d91d
HS		 1255 }
1256}
1257
1258static void get_last_sample_6143(struct comedi_device *dev)
1259{
a52b53e4 1260 struct ni_private *devpriv = dev->private;
5dce16e5 1261 struct comedi_subdevice *s = dev->read_subdev;
f8f6d91d
HS		 1262 unsigned short data;
1263 u32 dl;
1264
a52b53e4 1265 if (!devpriv->is_6143)
f8f6d91d
HS		 1266 return;
1267
1268 /* Check if there's a single sample stuck in the FIFO */
5a92cac5 1269 if (ni_readl(dev, AIFIFO_Status_6143) & 0x01) {
9c340ac9 1270 /* Get stranded sample into FIFO */
5a92cac5
HS		 1271 ni_writel(dev, 0x01, AIFIFO_Control_6143);
1272 dl = ni_readl(dev, AIFIFO_Data_6143);
f8f6d91d
HS		 1273
1274 /* This may get the hi/lo data in the wrong order */
1275 data = (dl >> 16) & 0xffff;
9caba329 1276 comedi_buf_write_samples(s, &data, 1);
f8f6d91d
HS		 1277 }
1278}
1279
f8246dfa
HS		 1280static void shutdown_ai_command(struct comedi_device *dev)
1281{
5dce16e5 1282 struct comedi_subdevice *s = dev->read_subdev;
f8246dfa
HS		 1283
1284#ifdef PCIDMA
1285 ni_ai_drain_dma(dev);
1286#endif
1287 ni_handle_fifo_dregs(dev);
1288 get_last_sample_611x(dev);
1289 get_last_sample_6143(dev);
1290
1291 s->async->events |= COMEDI_CB_EOA;
1292}
1293
da91b269 1294static void ni_handle_eos(struct comedi_device *dev, struct comedi_subdevice *s)
03aef4b6 1295{
0e05c552
HS		 1296 struct ni_private *devpriv = dev->private;
1297
03aef4b6
DS		 1298 if (devpriv->aimode == AIMODE_SCAN) {
1299#ifdef PCIDMA
1300 static const int timeout = 10;
1301 int i;
1302
1303 for (i = 0; i < timeout; i++) {
1304 ni_sync_ai_dma(dev);
1305 if ((s->async->events & COMEDI_CB_EOS))
1306 break;
5f74ea14 1307 udelay(1);
03aef4b6
DS		 1308 }
1309#else
1310 ni_handle_fifo_dregs(dev);
1311 s->async->events |= COMEDI_CB_EOS;
1312#endif
1313 }
a1da35a5
HS		 1314 /* handle special case of single scan */
1315 if (devpriv->ai_cmd2 & NISTC_AI_CMD2_END_ON_EOS)
03aef4b6 1316 shutdown_ai_command(dev);
03aef4b6
DS		 1317}
1318
da91b269 1319static void handle_gpct_interrupt(struct comedi_device *dev,
0a85b6f0 1320 unsigned short counter_index)
03aef4b6
DS		 1321{
1322#ifdef PCIDMA
0e05c552 1323 struct ni_private *devpriv = dev->private;
f9cd92eb
HS		 1324 struct comedi_subdevice *s;
1325
1326 s = &dev->subdevices[NI_GPCT_SUBDEV(counter_index)];
03aef4b6
DS		 1327
1328 ni_tio_handle_interrupt(&devpriv->counter_dev->counters[counter_index],
0a85b6f0 1329 s);
b9a69a19 1330 comedi_handle_events(dev, s);
03aef4b6
DS		 1331#endif
1332}
1333
da91b269 1334static void ack_a_interrupt(struct comedi_device *dev, unsigned short a_status)
03aef4b6
DS		 1335{
1336 unsigned short ack = 0;
1337
7b14fffd 1338 if (a_status & NISTC_AI_STATUS1_SC_TC)
480456d3 1339 ack |= NISTC_INTA_ACK_AI_SC_TC;
7b14fffd 1340 if (a_status & NISTC_AI_STATUS1_START1)
480456d3 1341 ack |= NISTC_INTA_ACK_AI_START1;
7b14fffd 1342 if (a_status & NISTC_AI_STATUS1_START)
480456d3 1343 ack |= NISTC_INTA_ACK_AI_START;
7b14fffd 1344 if (a_status & NISTC_AI_STATUS1_STOP)
480456d3 1345 ack |= NISTC_INTA_ACK_AI_STOP;
03aef4b6 1346 if (ack)
480456d3 1347 ni_stc_writew(dev, ack, NISTC_INTA_ACK_REG);
03aef4b6
DS		 1348}
1349
da91b269 1350static void handle_a_interrupt(struct comedi_device *dev, unsigned short status,
0a85b6f0 1351 unsigned ai_mite_status)
03aef4b6 1352{
5dce16e5 1353 struct comedi_subdevice *s = dev->read_subdev;
93fac790 1354 struct comedi_cmd *cmd = &s->async->cmd;
03aef4b6 1355
2696fb57 1356 /* 67xx boards don't have ai subdevice, but their gpct0 might generate an a interrupt */
03aef4b6
DS		 1357 if (s->type == COMEDI_SUBD_UNUSED)
1358 return;
1359
03aef4b6 1360#ifdef PCIDMA
bc461556 1361 if (ai_mite_status & CHSR_LINKC)
03aef4b6 1362 ni_sync_ai_dma(dev);
03aef4b6
DS		 1363
1364 if (ai_mite_status & ~(CHSR_INT | CHSR_LINKC | CHSR_DONE | CHSR_MRDY |
0a85b6f0
MT		 1365 CHSR_DRDY | CHSR_DRQ1 | CHSR_DRQ0 | CHSR_ERROR |
1366 CHSR_SABORT | CHSR_XFERR | CHSR_LxERR_mask)) {
89c4695e
HS		 1367 dev_err(dev->class_dev,
1368 "unknown mite interrupt (ai_mite_status=%08x)\n",
1369 ai_mite_status);
3e6cb74f 1370 s->async->events |= COMEDI_CB_ERROR;
2696fb57 1371 /* disable_irq(dev->irq); */
03aef4b6
DS		 1372 }
1373#endif
1374
1375 /* test for all uncommon interrupt events at the same time */
7b14fffd
HS		 1376 if (status & (NISTC_AI_STATUS1_ERR |
1377 NISTC_AI_STATUS1_SC_TC | NISTC_AI_STATUS1_START1)) {
03aef4b6 1378 if (status == 0xffff) {
89c4695e 1379 dev_err(dev->class_dev, "Card removed?\n");
03aef4b6
DS		 1380 /* we probably aren't even running a command now,
1381 * so it's a good idea to be careful. */
f0124630 1382 if (comedi_is_subdevice_running(s)) {
3e6cb74f 1383 s->async->events |= COMEDI_CB_ERROR;
b9a69a19 1384 comedi_handle_events(dev, s);
03aef4b6
DS		 1385 }
1386 return;
1387 }
7b14fffd 1388 if (status & NISTC_AI_STATUS1_ERR) {
89c4695e
HS		 1389 dev_err(dev->class_dev, "ai error a_status=%04x\n",
1390 status);
03aef4b6
DS		 1391
1392 shutdown_ai_command(dev);
1393
1394 s->async->events |= COMEDI_CB_ERROR;
7b14fffd 1395 if (status & NISTC_AI_STATUS1_OVER)
03aef4b6
DS		 1396 s->async->events |= COMEDI_CB_OVERFLOW;
1397
b9a69a19 1398 comedi_handle_events(dev, s);
03aef4b6
DS		 1399 return;
1400 }
7b14fffd 1401 if (status & NISTC_AI_STATUS1_SC_TC) {
93fac790 1402 if (cmd->stop_src == TRIG_COUNT)
03aef4b6 1403 shutdown_ai_command(dev);
03aef4b6
DS		 1404 }
1405 }
1406#ifndef PCIDMA
7b14fffd 1407 if (status & NISTC_AI_STATUS1_FIFO_HF) {
03aef4b6
DS		 1408 int i;
1409 static const int timeout = 10;
1410 /* pcmcia cards (at least 6036) seem to stop producing interrupts if we
1411 *fail to get the fifo less than half full, so loop to be sure.*/
1412 for (i = 0; i < timeout; ++i) {
1413 ni_handle_fifo_half_full(dev);
7b14fffd
HS		 1414 if ((ni_stc_readw(dev, NISTC_AI_STATUS1_REG) &
1415 NISTC_AI_STATUS1_FIFO_HF) == 0)
03aef4b6
DS		 1416 break;
1417 }
1418 }
2696fb57 1419#endif /* !PCIDMA */
03aef4b6 1420
7b14fffd 1421 if (status & NISTC_AI_STATUS1_STOP)
03aef4b6 1422 ni_handle_eos(dev, s);
03aef4b6 1423
b9a69a19 1424 comedi_handle_events(dev, s);
03aef4b6
DS		 1425}
1426
da91b269 1427static void ack_b_interrupt(struct comedi_device *dev, unsigned short b_status)
03aef4b6
DS		 1428{
1429 unsigned short ack = 0;
0e05c552 1430
d123ee3c 1431 if (b_status & NISTC_AO_STATUS1_BC_TC)
4a6de832 1432 ack |= NISTC_INTB_ACK_AO_BC_TC;
d123ee3c 1433 if (b_status & NISTC_AO_STATUS1_OVERRUN)
4a6de832 1434 ack |= NISTC_INTB_ACK_AO_ERR;
d123ee3c 1435 if (b_status & NISTC_AO_STATUS1_START)
4a6de832 1436 ack |= NISTC_INTB_ACK_AO_START;
d123ee3c 1437 if (b_status & NISTC_AO_STATUS1_START1)
4a6de832 1438 ack |= NISTC_INTB_ACK_AO_START1;
d123ee3c 1439 if (b_status & NISTC_AO_STATUS1_UC_TC)
4a6de832 1440 ack |= NISTC_INTB_ACK_AO_UC_TC;
d123ee3c 1441 if (b_status & NISTC_AO_STATUS1_UI2_TC)
4a6de832 1442 ack |= NISTC_INTB_ACK_AO_UI2_TC;
d123ee3c 1443 if (b_status & NISTC_AO_STATUS1_UPDATE)
4a6de832 1444 ack |= NISTC_INTB_ACK_AO_UPDATE;
03aef4b6 1445 if (ack)
4a6de832 1446 ni_stc_writew(dev, ack, NISTC_INTB_ACK_REG);
03aef4b6
DS		 1447}
1448
0a85b6f0
MT		 1449static void handle_b_interrupt(struct comedi_device *dev,
1450 unsigned short b_status, unsigned ao_mite_status)
03aef4b6 1451{
e879c315 1452 struct comedi_subdevice *s = dev->write_subdev;
2696fb57 1453 /* unsigned short ack=0; */
0e05c552 1454
03aef4b6
DS		 1455#ifdef PCIDMA
1456 /* Currently, mite.c requires us to handle LINKC */
00b14b1d
HS		 1457 if (ao_mite_status & CHSR_LINKC) {
1458 struct ni_private *devpriv = dev->private;
1459
03aef4b6 1460 mite_handle_b_linkc(devpriv->mite, dev);
00b14b1d 1461 }
03aef4b6
DS		 1462
1463 if (ao_mite_status & ~(CHSR_INT | CHSR_LINKC | CHSR_DONE | CHSR_MRDY |
0a85b6f0
MT		 1464 CHSR_DRDY | CHSR_DRQ1 | CHSR_DRQ0 | CHSR_ERROR |
1465 CHSR_SABORT | CHSR_XFERR | CHSR_LxERR_mask)) {
89c4695e
HS		 1466 dev_err(dev->class_dev,
1467 "unknown mite interrupt (ao_mite_status=%08x)\n",
1468 ao_mite_status);
3e6cb74f 1469 s->async->events |= COMEDI_CB_ERROR;
03aef4b6
DS		 1470 }
1471#endif
1472
1473 if (b_status == 0xffff)
1474 return;
d123ee3c 1475 if (b_status & NISTC_AO_STATUS1_OVERRUN) {
89c4695e
HS		 1476 dev_err(dev->class_dev,
1477 "AO FIFO underrun status=0x%04x status2=0x%04x\n",
63b2bb05 1478 b_status, ni_stc_readw(dev, NISTC_AO_STATUS2_REG));
03aef4b6
DS		 1479 s->async->events |= COMEDI_CB_OVERFLOW;
1480 }
1481
d123ee3c 1482 if (b_status & NISTC_AO_STATUS1_BC_TC)
03aef4b6 1483 s->async->events |= COMEDI_CB_EOA;
a7866a6e 1484
03aef4b6 1485#ifndef PCIDMA
d123ee3c 1486 if (b_status & NISTC_AO_STATUS1_FIFO_REQ) {
03aef4b6
DS		 1487 int ret;
1488
1489 ret = ni_ao_fifo_half_empty(dev, s);
1490 if (!ret) {
89c4695e 1491 dev_err(dev->class_dev, "AO buffer underrun\n");
4c9c1d2c
HS		 1492 ni_set_bits(dev, NISTC_INTB_ENA_REG,
1493 NISTC_INTB_ENA_AO_FIFO |
1494 NISTC_INTB_ENA_AO_ERR, 0);
03aef4b6
DS		 1495 s->async->events |= COMEDI_CB_OVERFLOW;
1496 }
1497 }
1498#endif
1499
b9a69a19 1500 comedi_handle_events(dev, s);
03aef4b6
DS		 1501}
1502
da91b269 1503static void ni_ai_munge(struct comedi_device *dev, struct comedi_subdevice *s,
0a85b6f0
MT		 1504 void *data, unsigned int num_bytes,
1505 unsigned int chan_index)
03aef4b6 1506{
0e05c552 1507 struct ni_private *devpriv = dev->private;
d163679c 1508 struct comedi_async *async = s->async;
9663ab1f 1509 struct comedi_cmd *cmd = &async->cmd;
c39e050d 1510 unsigned int nsamples = comedi_bytes_to_samples(s, num_bytes);
3a2b101c 1511 unsigned short *array = data;
790c5541 1512 unsigned int *larray = data;
9663ab1f 1513 unsigned int i;
0e05c552 1514
c39e050d 1515 for (i = 0; i < nsamples; i++) {
03aef4b6
DS		 1516#ifdef PCIDMA
1517 if (s->subdev_flags & SDF_LSAMPL)
1518 larray[i] = le32_to_cpu(larray[i]);
1519 else
1520 array[i] = le16_to_cpu(array[i]);
1521#endif
1522 if (s->subdev_flags & SDF_LSAMPL)
1523 larray[i] += devpriv->ai_offset[chan_index];
1524 else
1525 array[i] += devpriv->ai_offset[chan_index];
1526 chan_index++;
9663ab1f 1527 chan_index %= cmd->chanlist_len;
03aef4b6
DS		 1528 }
1529}
1530
1531#ifdef PCIDMA
1532
da91b269 1533static int ni_ai_setup_MITE_dma(struct comedi_device *dev)
03aef4b6 1534{
0e05c552 1535 struct ni_private *devpriv = dev->private;
5dce16e5 1536 struct comedi_subdevice *s = dev->read_subdev;
03aef4b6
DS		 1537 int retval;
1538 unsigned long flags;
1539
1540 retval = ni_request_ai_mite_channel(dev);
1541 if (retval)
1542 return retval;
03aef4b6
DS		 1543
1544 /* write alloc the entire buffer */
24e894bb 1545 comedi_buf_write_alloc(s, s->async->prealloc_bufsz);
03aef4b6 1546
5f74ea14 1547 spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
c6be1548 1548 if (!devpriv->ai_mite_chan) {
5f74ea14 1549 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
03aef4b6
DS		 1550 return -EIO;
1551 }
1552
a52b53e4 1553 if (devpriv->is_611x || devpriv->is_6143)
03aef4b6 1554 mite_prep_dma(devpriv->ai_mite_chan, 32, 16);
a52b53e4 1555 else if (devpriv->is_628x)
03aef4b6 1556 mite_prep_dma(devpriv->ai_mite_chan, 32, 32);
a52b53e4 1557 else
03aef4b6 1558 mite_prep_dma(devpriv->ai_mite_chan, 16, 16);
a52b53e4 1559
03aef4b6
DS		 1560 /*start the MITE */
1561 mite_dma_arm(devpriv->ai_mite_chan);
5f74ea14 1562 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
03aef4b6
DS		 1563
1564 return 0;
1565}
1566
da91b269 1567static int ni_ao_setup_MITE_dma(struct comedi_device *dev)
03aef4b6 1568{
0e05c552 1569 struct ni_private *devpriv = dev->private;
e879c315 1570 struct comedi_subdevice *s = dev->write_subdev;
03aef4b6
DS		 1571 int retval;
1572 unsigned long flags;
1573
1574 retval = ni_request_ao_mite_channel(dev);
1575 if (retval)
1576 return retval;
1577
1578 /* read alloc the entire buffer */
d13be55a 1579 comedi_buf_read_alloc(s, s->async->prealloc_bufsz);
03aef4b6 1580
5f74ea14 1581 spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
03aef4b6 1582 if (devpriv->ao_mite_chan) {
a52b53e4 1583 if (devpriv->is_611x || devpriv->is_6713) {
03aef4b6
DS		 1584 mite_prep_dma(devpriv->ao_mite_chan, 32, 32);
1585 } else {
1586 /* doing 32 instead of 16 bit wide transfers from memory
1587 makes the mite do 32 bit pci transfers, doubling pci bandwidth. */
1588 mite_prep_dma(devpriv->ao_mite_chan, 16, 32);
1589 }
1590 mite_dma_arm(devpriv->ao_mite_chan);
6ac986d0 1591 } else {
03aef4b6 1592 retval = -EIO;
6ac986d0 1593 }
5f74ea14 1594 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
03aef4b6
DS		 1595
1596 return retval;
1597}
1598
2696fb57 1599#endif /* PCIDMA */
03aef4b6
DS		 1600
1601/*
1602 used for both cancel ioctl and board initialization
1603
1604 this is pretty harsh for a cancel, but it works...
1605 */
1606
da91b269 1607static int ni_ai_reset(struct comedi_device *dev, struct comedi_subdevice *s)
03aef4b6 1608{
a52b53e4 1609 struct ni_private *devpriv = dev->private;
c1b74035 1610 unsigned ai_personal;
aa9d73ba 1611 unsigned ai_out_ctrl;
0e05c552 1612
03aef4b6
DS		 1613 ni_release_ai_mite_channel(dev);
1614 /* ai configuration */
707502f3
HS		 1615 ni_stc_writew(dev, NISTC_RESET_AI_CFG_START | NISTC_RESET_AI,
1616 NISTC_RESET_REG);
03aef4b6 1617
5cca26aa 1618 ni_set_bits(dev, NISTC_INTA_ENA_REG, NISTC_INTA_ENA_AI_MASK, 0);
03aef4b6
DS		 1619
1620 ni_clear_ai_fifo(dev);
1621
a52b53e4 1622 if (!devpriv->is_6143)
68885d9e 1623 ni_writeb(dev, NI_E_MISC_CMD_EXT_ATRIG, NI_E_MISC_CMD_REG);
03aef4b6 1624
4c4d715a 1625 ni_stc_writew(dev, NISTC_AI_CMD1_DISARM, NISTC_AI_CMD1_REG);
bd358f5e
HS		 1626 ni_stc_writew(dev, NISTC_AI_MODE1_START_STOP |
1627 NISTC_AI_MODE1_RSVD
1628 /*| NISTC_AI_MODE1_TRIGGER_ONCE */,
1629 NISTC_AI_MODE1_REG);
b134cc58 1630 ni_stc_writew(dev, 0, NISTC_AI_MODE2_REG);
03aef4b6 1631 /* generate FIFO interrupts on non-empty */
c7edadc1
HS		 1632 ni_stc_writew(dev, NISTC_AI_MODE3_FIFO_MODE_NE,
1633 NISTC_AI_MODE3_REG);
aa9d73ba 1634
c1b74035
HS		 1635 ai_personal = NISTC_AI_PERSONAL_SHIFTIN_PW |
1636 NISTC_AI_PERSONAL_SOC_POLARITY |
1637 NISTC_AI_PERSONAL_LOCALMUX_CLK_PW;
aa9d73ba
HS		 1638 ai_out_ctrl = NISTC_AI_OUT_CTRL_SCAN_IN_PROG_SEL(3) |
1639 NISTC_AI_OUT_CTRL_EXTMUX_CLK_SEL(0) |
1640 NISTC_AI_OUT_CTRL_LOCALMUX_CLK_SEL(2) |
1641 NISTC_AI_OUT_CTRL_SC_TC_SEL(3);
a52b53e4 1642 if (devpriv->is_611x) {
aa9d73ba 1643 ai_out_ctrl |= NISTC_AI_OUT_CTRL_CONVERT_HIGH;
a52b53e4 1644 } else if (devpriv->is_6143) {
aa9d73ba 1645 ai_out_ctrl |= NISTC_AI_OUT_CTRL_CONVERT_LOW;
03aef4b6 1646 } else {
c1b74035 1647 ai_personal |= NISTC_AI_PERSONAL_CONVERT_PW;
a52b53e4 1648 if (devpriv->is_622x)
aa9d73ba 1649 ai_out_ctrl |= NISTC_AI_OUT_CTRL_CONVERT_HIGH;
03aef4b6 1650 else
aa9d73ba 1651 ai_out_ctrl |= NISTC_AI_OUT_CTRL_CONVERT_LOW;
03aef4b6 1652 }
c1b74035 1653 ni_stc_writew(dev, ai_personal, NISTC_AI_PERSONAL_REG);
aa9d73ba
HS		 1654 ni_stc_writew(dev, ai_out_ctrl, NISTC_AI_OUT_CTRL_REG);
1655
03aef4b6
DS		 1656 /* the following registers should not be changed, because there
1657 * are no backup registers in devpriv. If you want to change
1658 * any of these, add a backup register and other appropriate code:
bd358f5e 1659 * NISTC_AI_MODE1_REG
c7edadc1 1660 * NISTC_AI_MODE3_REG
c1b74035 1661 * NISTC_AI_PERSONAL_REG
aa9d73ba 1662 * NISTC_AI_OUT_CTRL_REG
03aef4b6 1663 */
480456d3
HS		 1664
1665 /* clear interrupts */
1666 ni_stc_writew(dev, NISTC_INTA_ACK_AI_ALL, NISTC_INTA_ACK_REG);
00b14b1d 1667
707502f3 1668 ni_stc_writew(dev, NISTC_RESET_AI_CFG_END, NISTC_RESET_REG);
03aef4b6
DS		 1669
1670 return 0;
1671}
1672
da91b269 1673static int ni_ai_poll(struct comedi_device *dev, struct comedi_subdevice *s)
03aef4b6 1674{
3cd73bc1 1675 unsigned long flags;
03aef4b6
DS		 1676 int count;
1677
2696fb57 1678 /* lock to avoid race with interrupt handler */
3cd73bc1 1679 spin_lock_irqsave(&dev->spinlock, flags);
03aef4b6
DS		 1680#ifndef PCIDMA
1681 ni_handle_fifo_dregs(dev);
1682#else
1683 ni_sync_ai_dma(dev);
1684#endif
f4f3f7cf 1685 count = comedi_buf_n_bytes_ready(s);
3cd73bc1 1686 spin_unlock_irqrestore(&dev->spinlock, flags);
03aef4b6
DS		 1687
1688 return count;
1689}
1690
29aba763 1691static void ni_prime_channelgain_list(struct comedi_device *dev)
03aef4b6
DS		 1692{
1693 int i;
0e05c552 1694
4c4d715a 1695 ni_stc_writew(dev, NISTC_AI_CMD1_CONVERT_PULSE, NISTC_AI_CMD1_REG);
03aef4b6 1696 for (i = 0; i < NI_TIMEOUT; ++i) {
7b14fffd
HS		 1697 if (!(ni_stc_readw(dev, NISTC_AI_STATUS1_REG) &
1698 NISTC_AI_STATUS1_FIFO_E)) {
8102f3d0 1699 ni_stc_writew(dev, 1, NISTC_ADC_FIFO_CLR_REG);
03aef4b6
DS		 1700 return;
1701 }
5f74ea14 1702 udelay(1);
03aef4b6 1703 }
89c4695e 1704 dev_err(dev->class_dev, "timeout loading channel/gain list\n");
03aef4b6
DS		 1705}
1706
da91b269 1707static void ni_m_series_load_channelgain_list(struct comedi_device *dev,
0a85b6f0
MT		 1708 unsigned int n_chan,
1709 unsigned int *list)
03aef4b6 1710{
7cf94adc 1711 const struct ni_board_struct *board = dev->board_ptr;
0e05c552 1712 struct ni_private *devpriv = dev->private;
03aef4b6
DS		 1713 unsigned int chan, range, aref;
1714 unsigned int i;
03aef4b6
DS		 1715 unsigned int dither;
1716 unsigned range_code;
1717
8102f3d0 1718 ni_stc_writew(dev, 1, NISTC_CFG_MEM_CLR_REG);
03aef4b6 1719
03aef4b6
DS		 1720 if ((list[0] & CR_ALT_SOURCE)) {
1721 unsigned bypass_bits;
f7401979 1722
03aef4b6
DS		 1723 chan = CR_CHAN(list[0]);
1724 range = CR_RANGE(list[0]);
6293e357 1725 range_code = ni_gainlkup[board->gainlkup][range];
f0dff421 1726 dither = (list[0] & CR_ALT_FILTER) != 0;
41f9f0bf
HS		 1727 bypass_bits = NI_M_CFG_BYPASS_FIFO |
1728 NI_M_CFG_BYPASS_AI_CHAN(chan) |
1729 NI_M_CFG_BYPASS_AI_GAIN(range_code) |
1730 devpriv->ai_calib_source;
03aef4b6 1731 if (dither)
41f9f0bf 1732 bypass_bits |= NI_M_CFG_BYPASS_AI_DITHER;
2696fb57 1733 /* don't use 2's complement encoding */
41f9f0bf
HS		 1734 bypass_bits |= NI_M_CFG_BYPASS_AI_POLARITY;
1735 ni_writel(dev, bypass_bits, NI_M_CFG_BYPASS_FIFO_REG);
03aef4b6 1736 } else {
41f9f0bf 1737 ni_writel(dev, 0, NI_M_CFG_BYPASS_FIFO_REG);
03aef4b6 1738 }
03aef4b6
DS		 1739 for (i = 0; i < n_chan; i++) {
1740 unsigned config_bits = 0;
f7401979 1741
03aef4b6
DS		 1742 chan = CR_CHAN(list[i]);
1743 aref = CR_AREF(list[i]);
1744 range = CR_RANGE(list[i]);
f0dff421 1745 dither = (list[i] & CR_ALT_FILTER) != 0;
03aef4b6 1746
6293e357 1747 range_code = ni_gainlkup[board->gainlkup][range];
817144ae 1748 devpriv->ai_offset[i] = 0;
03aef4b6
DS		 1749 switch (aref) {
1750 case AREF_DIFF:
67d2d058 1751 config_bits |= NI_M_AI_CFG_CHAN_TYPE_DIFF;
03aef4b6
DS		 1752 break;
1753 case AREF_COMMON:
67d2d058 1754 config_bits |= NI_M_AI_CFG_CHAN_TYPE_COMMON;
03aef4b6
DS		 1755 break;
1756 case AREF_GROUND:
67d2d058 1757 config_bits |= NI_M_AI_CFG_CHAN_TYPE_GROUND;
03aef4b6
DS		 1758 break;
1759 case AREF_OTHER:
1760 break;
1761 }
67d2d058
HS		 1762 config_bits |= NI_M_AI_CFG_CHAN_SEL(chan);
1763 config_bits |= NI_M_AI_CFG_BANK_SEL(chan);
1764 config_bits |= NI_M_AI_CFG_GAIN(range_code);
03aef4b6 1765 if (i == n_chan - 1)
67d2d058 1766 config_bits |= NI_M_AI_CFG_LAST_CHAN;
03aef4b6 1767 if (dither)
67d2d058 1768 config_bits |= NI_M_AI_CFG_DITHER;
2696fb57 1769 /* don't use 2's complement encoding */
67d2d058 1770 config_bits |= NI_M_AI_CFG_POLARITY;
975b6d25 1771 ni_writew(dev, config_bits, NI_M_AI_CFG_FIFO_DATA_REG);
03aef4b6
DS		 1772 }
1773 ni_prime_channelgain_list(dev);
1774}
1775
1776/*
1777 * Notes on the 6110 and 6111:
1778 * These boards a slightly different than the rest of the series, since
1779 * they have multiple A/D converters.
1780 * From the driver side, the configuration memory is a
1781 * little different.
1782 * Configuration Memory Low:
1783 * bits 15-9: same
1784 * bit 8: unipolar/bipolar (should be 0 for bipolar)
1785 * bits 0-3: gain. This is 4 bits instead of 3 for the other boards
1786 * 1001 gain=0.1 (+/- 50)
1787 * 1010 0.2
1788 * 1011 0.1
1789 * 0001 1
1790 * 0010 2
1791 * 0011 5
1792 * 0100 10
1793 * 0101 20
1794 * 0110 50
1795 * Configuration Memory High:
1796 * bits 12-14: Channel Type
1797 * 001 for differential
1798 * 000 for calibration
1799 * bit 11: coupling (this is not currently handled)
1800 * 1 AC coupling
1801 * 0 DC coupling
1802 * bits 0-2: channel
1803 * valid channels are 0-3
1804 */
0a85b6f0 1805static void ni_load_channelgain_list(struct comedi_device *dev,
817144ae 1806 struct comedi_subdevice *s,
0a85b6f0 1807 unsigned int n_chan, unsigned int *list)
03aef4b6 1808{
7cf94adc 1809 const struct ni_board_struct *board = dev->board_ptr;
0e05c552 1810 struct ni_private *devpriv = dev->private;
817144ae 1811 unsigned int offset = (s->maxdata + 1) >> 1;
03aef4b6
DS		 1812 unsigned int chan, range, aref;
1813 unsigned int i;
1814 unsigned int hi, lo;
03aef4b6
DS		 1815 unsigned int dither;
1816
17733219 1817 if (devpriv->is_m_series) {
03aef4b6
DS		 1818 ni_m_series_load_channelgain_list(dev, n_chan, list);
1819 return;
1820 }
a52b53e4 1821 if (n_chan == 1 && !devpriv->is_611x && !devpriv->is_6143) {
03aef4b6 1822 if (devpriv->changain_state
0a85b6f0 1823 && devpriv->changain_spec == list[0]) {
2696fb57 1824 /* ready to go. */
03aef4b6
DS		 1825 return;
1826 }
1827 devpriv->changain_state = 1;
1828 devpriv->changain_spec = list[0];
1829 } else {
1830 devpriv->changain_state = 0;
1831 }
1832
8102f3d0 1833 ni_stc_writew(dev, 1, NISTC_CFG_MEM_CLR_REG);
03aef4b6 1834
2696fb57 1835 /* Set up Calibration mode if required */
a52b53e4 1836 if (devpriv->is_6143) {
03aef4b6 1837 if ((list[0] & CR_ALT_SOURCE)
0a85b6f0 1838 && !devpriv->ai_calib_source_enabled) {
2696fb57 1839 /* Strobe Relay enable bit */
5a92cac5
HS		 1840 ni_writew(dev, devpriv->ai_calib_source |
1841 Calibration_Channel_6143_RelayOn,
1842 Calibration_Channel_6143);
1843 ni_writew(dev, devpriv->ai_calib_source,
1844 Calibration_Channel_6143);
03aef4b6 1845 devpriv->ai_calib_source_enabled = 1;
2696fb57 1846 msleep_interruptible(100); /* Allow relays to change */
03aef4b6 1847 } else if (!(list[0] & CR_ALT_SOURCE)
0a85b6f0 1848 && devpriv->ai_calib_source_enabled) {
2696fb57 1849 /* Strobe Relay disable bit */
5a92cac5
HS		 1850 ni_writew(dev, devpriv->ai_calib_source |
1851 Calibration_Channel_6143_RelayOff,
1852 Calibration_Channel_6143);
1853 ni_writew(dev, devpriv->ai_calib_source,
1854 Calibration_Channel_6143);
03aef4b6 1855 devpriv->ai_calib_source_enabled = 0;
2696fb57 1856 msleep_interruptible(100); /* Allow relays to change */
03aef4b6
DS		 1857 }
1858 }
1859
03aef4b6 1860 for (i = 0; i < n_chan; i++) {
a6266977 1861 if (!devpriv->is_6143 && (list[i] & CR_ALT_SOURCE))
03aef4b6 1862 chan = devpriv->ai_calib_source;
a6266977 1863 else
03aef4b6 1864 chan = CR_CHAN(list[i]);
03aef4b6
DS		 1865 aref = CR_AREF(list[i]);
1866 range = CR_RANGE(list[i]);
f0dff421 1867 dither = (list[i] & CR_ALT_FILTER) != 0;
03aef4b6
DS		 1868
1869 /* fix the external/internal range differences */
6293e357 1870 range = ni_gainlkup[board->gainlkup][range];
a52b53e4 1871 if (devpriv->is_611x)
03aef4b6
DS		 1872 devpriv->ai_offset[i] = offset;
1873 else
1874 devpriv->ai_offset[i] = (range & 0x100) ? 0 : offset;
1875
1876 hi = 0;
1877 if ((list[i] & CR_ALT_SOURCE)) {
a52b53e4 1878 if (devpriv->is_611x)
5a92cac5
HS		 1879 ni_writew(dev, CR_CHAN(list[i]) & 0x0003,
1880 Calibration_Channel_Select_611x);
03aef4b6 1881 } else {
a52b53e4 1882 if (devpriv->is_611x)
03aef4b6 1883 aref = AREF_DIFF;
a52b53e4 1884 else if (devpriv->is_6143)
03aef4b6
DS		 1885 aref = AREF_OTHER;
1886 switch (aref) {
1887 case AREF_DIFF:
d504a6ee 1888 hi |= NI_E_AI_CFG_HI_TYPE_DIFF;
03aef4b6
DS		 1889 break;
1890 case AREF_COMMON:
d504a6ee 1891 hi |= NI_E_AI_CFG_HI_TYPE_COMMON;
03aef4b6
DS		 1892 break;
1893 case AREF_GROUND:
d504a6ee 1894 hi |= NI_E_AI_CFG_HI_TYPE_GROUND;
03aef4b6
DS		 1895 break;
1896 case AREF_OTHER:
1897 break;
1898 }
1899 }
d504a6ee 1900 hi |= NI_E_AI_CFG_HI_CHAN(chan);
03aef4b6 1901
d504a6ee 1902 ni_writew(dev, hi, NI_E_AI_CFG_HI_REG);
03aef4b6 1903
a52b53e4 1904 if (!devpriv->is_6143) {
76efac7f
HS		 1905 lo = NI_E_AI_CFG_LO_GAIN(range);
1906
03aef4b6 1907 if (i == n_chan - 1)
76efac7f 1908 lo |= NI_E_AI_CFG_LO_LAST_CHAN;
03aef4b6 1909 if (dither)
76efac7f 1910 lo |= NI_E_AI_CFG_LO_DITHER;
03aef4b6 1911
76efac7f 1912 ni_writew(dev, lo, NI_E_AI_CFG_LO_REG);
03aef4b6
DS		 1913 }
1914 }
1915
1916 /* prime the channel/gain list */
a52b53e4 1917 if (!devpriv->is_611x && !devpriv->is_6143)
03aef4b6 1918 ni_prime_channelgain_list(dev);
03aef4b6
DS		 1919}
1920
3d129c3e
HS		 1921static int ni_ai_insn_read(struct comedi_device *dev,
1922 struct comedi_subdevice *s,
1923 struct comedi_insn *insn,
1924 unsigned int *data)
1925{
3d129c3e 1926 struct ni_private *devpriv = dev->private;
817144ae 1927 unsigned int mask = (s->maxdata + 1) >> 1;
3d129c3e 1928 int i, n;
3d129c3e 1929 unsigned signbits;
0557344e 1930 unsigned int d;
3d129c3e
HS		 1931 unsigned long dl;
1932
817144ae 1933 ni_load_channelgain_list(dev, s, 1, &insn->chanspec);
3d129c3e
HS		 1934
1935 ni_clear_ai_fifo(dev);
1936
1937 signbits = devpriv->ai_offset[0];
a52b53e4 1938 if (devpriv->is_611x) {
3d129c3e 1939 for (n = 0; n < num_adc_stages_611x; n++) {
4c4d715a
HS		 1940 ni_stc_writew(dev, NISTC_AI_CMD1_CONVERT_PULSE,
1941 NISTC_AI_CMD1_REG);
3d129c3e
HS		 1942 udelay(1);
1943 }
1944 for (n = 0; n < insn->n; n++) {
4c4d715a
HS		 1945 ni_stc_writew(dev, NISTC_AI_CMD1_CONVERT_PULSE,
1946 NISTC_AI_CMD1_REG);
3d129c3e
HS		 1947 /* The 611x has screwy 32-bit FIFOs. */
1948 d = 0;
1949 for (i = 0; i < NI_TIMEOUT; i++) {
906170b8 1950 if (ni_readb(dev, NI_E_STATUS_REG) & 0x80) {
5a92cac5 1951 d = ni_readl(dev, ADC_FIFO_Data_611x);
9c340ac9
HS		 1952 d >>= 16;
1953 d &= 0xffff;
3d129c3e
HS		 1954 break;
1955 }
7b14fffd
HS		 1956 if (!(ni_stc_readw(dev, NISTC_AI_STATUS1_REG) &
1957 NISTC_AI_STATUS1_FIFO_E)) {
5a92cac5 1958 d = ni_readl(dev, ADC_FIFO_Data_611x);
9c340ac9 1959 d &= 0xffff;
3d129c3e
HS		 1960 break;
1961 }
1962 }
1963 if (i == NI_TIMEOUT) {
cd25503f 1964 dev_err(dev->class_dev, "timeout\n");
3d129c3e
HS		 1965 return -ETIME;
1966 }
1967 d += signbits;
1968 data[n] = d;
1969 }
a52b53e4 1970 } else if (devpriv->is_6143) {
3d129c3e 1971 for (n = 0; n < insn->n; n++) {
4c4d715a
HS		 1972 ni_stc_writew(dev, NISTC_AI_CMD1_CONVERT_PULSE,
1973 NISTC_AI_CMD1_REG);
3d129c3e
HS		 1974
1975 /* The 6143 has 32-bit FIFOs. You need to strobe a bit to move a single 16bit stranded sample into the FIFO */
1976 dl = 0;
1977 for (i = 0; i < NI_TIMEOUT; i++) {
5a92cac5 1978 if (ni_readl(dev, AIFIFO_Status_6143) & 0x01) {
9c340ac9 1979 /* Get stranded sample into FIFO */
5a92cac5
HS		 1980 ni_writel(dev, 0x01,
1981 AIFIFO_Control_6143);
1982 dl = ni_readl(dev, AIFIFO_Data_6143);
3d129c3e
HS		 1983 break;
1984 }
1985 }
1986 if (i == NI_TIMEOUT) {
cd25503f 1987 dev_err(dev->class_dev, "timeout\n");
3d129c3e
HS		 1988 return -ETIME;
1989 }
1990 data[n] = (((dl >> 16) & 0xFFFF) + signbits) & 0xFFFF;
1991 }
1992 } else {
1993 for (n = 0; n < insn->n; n++) {
4c4d715a
HS		 1994 ni_stc_writew(dev, NISTC_AI_CMD1_CONVERT_PULSE,
1995 NISTC_AI_CMD1_REG);
3d129c3e 1996 for (i = 0; i < NI_TIMEOUT; i++) {
7b14fffd
HS		 1997 if (!(ni_stc_readw(dev, NISTC_AI_STATUS1_REG) &
1998 NISTC_AI_STATUS1_FIFO_E))
3d129c3e
HS		 1999 break;
2000 }
2001 if (i == NI_TIMEOUT) {
cd25503f 2002 dev_err(dev->class_dev, "timeout\n");
3d129c3e
HS		 2003 return -ETIME;
2004 }
17733219 2005 if (devpriv->is_m_series) {
975b6d25 2006 dl = ni_readl(dev, NI_M_AI_FIFO_DATA_REG);
9c340ac9
HS		 2007 dl &= mask;
2008 data[n] = dl;
3d129c3e 2009 } else {
363f570e 2010 d = ni_readw(dev, NI_E_AI_FIFO_DATA_REG);
3d129c3e
HS		 2011 d += signbits; /* subtle: needs to be short addition */
2012 data[n] = d;
2013 }
2014 }
2015 }
2016 return insn->n;
2017}
2018
da91b269 2019static int ni_ns_to_timer(const struct comedi_device *dev, unsigned nanosec,
a207c12f 2020 unsigned int flags)
03aef4b6 2021{
0e05c552 2022 struct ni_private *devpriv = dev->private;
03aef4b6 2023 int divider;
0e05c552 2024
3280c2d2
IA		 2025 switch (flags & CMDF_ROUND_MASK) {
2026 case CMDF_ROUND_NEAREST:
03aef4b6
DS		 2027 default:
2028 divider = (nanosec + devpriv->clock_ns / 2) / devpriv->clock_ns;
2029 break;
3280c2d2 2030 case CMDF_ROUND_DOWN:
03aef4b6
DS		 2031 divider = (nanosec) / devpriv->clock_ns;
2032 break;
3280c2d2 2033 case CMDF_ROUND_UP:
03aef4b6
DS		 2034 divider = (nanosec + devpriv->clock_ns - 1) / devpriv->clock_ns;
2035 break;
2036 }
2037 return divider - 1;
2038}
2039
da91b269 2040static unsigned ni_timer_to_ns(const struct comedi_device *dev, int timer)
03aef4b6 2041{
0e05c552
HS		 2042 struct ni_private *devpriv = dev->private;
2043
03aef4b6
DS		 2044 return devpriv->clock_ns * (timer + 1);
2045}
2046
da91b269 2047static unsigned ni_min_ai_scan_period_ns(struct comedi_device *dev,
0a85b6f0 2048 unsigned num_channels)
03aef4b6 2049{
7cf94adc 2050 const struct ni_board_struct *board = dev->board_ptr;
a52b53e4 2051 struct ni_private *devpriv = dev->private;
6293e357 2052
a52b53e4
HS		 2053 /* simultaneously-sampled inputs */
2054 if (devpriv->is_611x || devpriv->is_6143)
6293e357 2055 return board->ai_speed;
a52b53e4
HS		 2056
2057 /* multiplexed inputs */
6293e357 2058 return board->ai_speed * num_channels;
03aef4b6
DS		 2059}
2060
da91b269 2061static int ni_ai_cmdtest(struct comedi_device *dev, struct comedi_subdevice *s,
0a85b6f0 2062 struct comedi_cmd *cmd)
03aef4b6 2063{
7cf94adc 2064 const struct ni_board_struct *board = dev->board_ptr;
0e05c552 2065 struct ni_private *devpriv = dev->private;
03aef4b6 2066 int err = 0;
ebb657ba 2067 unsigned int tmp;
27020ffe 2068 unsigned int sources;
03aef4b6 2069
27020ffe 2070 /* Step 1 : check if triggers are trivially valid */
03aef4b6 2071
311fd9b2 2072 err |= comedi_check_trigger_src(&cmd->start_src,
27020ffe 2073 TRIG_NOW | TRIG_INT | TRIG_EXT);
311fd9b2 2074 err |= comedi_check_trigger_src(&cmd->scan_begin_src,
27020ffe 2075 TRIG_TIMER | TRIG_EXT);
03aef4b6 2076
03aef4b6 2077 sources = TRIG_TIMER | TRIG_EXT;
a52b53e4 2078 if (devpriv->is_611x || devpriv->is_6143)
03aef4b6 2079 sources |= TRIG_NOW;
311fd9b2 2080 err |= comedi_check_trigger_src(&cmd->convert_src, sources);
03aef4b6 2081
311fd9b2
IA		 2082 err |= comedi_check_trigger_src(&cmd->scan_end_src, TRIG_COUNT);
2083 err |= comedi_check_trigger_src(&cmd->stop_src, TRIG_COUNT | TRIG_NONE);
03aef4b6
DS		 2084
2085 if (err)
2086 return 1;
2087
27020ffe 2088 /* Step 2a : make sure trigger sources are unique */
03aef4b6 2089
311fd9b2
IA		 2090 err |= comedi_check_trigger_is_unique(cmd->start_src);
2091 err |= comedi_check_trigger_is_unique(cmd->scan_begin_src);
2092 err |= comedi_check_trigger_is_unique(cmd->convert_src);
2093 err |= comedi_check_trigger_is_unique(cmd->stop_src);
27020ffe
HS		 2094
2095 /* Step 2b : and mutually compatible */
03aef4b6
DS		 2096
2097 if (err)
2098 return 2;
2099
c3be5c7f 2100 /* Step 3: check if arguments are trivially valid */
03aef4b6 2101
ebb657ba
HS		 2102 switch (cmd->start_src) {
2103 case TRIG_NOW:
2104 case TRIG_INT:
311fd9b2 2105 err |= comedi_check_trigger_arg_is(&cmd->start_arg, 0);
ebb657ba
HS		 2106 break;
2107 case TRIG_EXT:
2108 tmp = CR_CHAN(cmd->start_arg);
03aef4b6
DS		 2109
2110 if (tmp > 16)
2111 tmp = 16;
2112 tmp |= (cmd->start_arg & (CR_INVERT | CR_EDGE));
311fd9b2 2113 err |= comedi_check_trigger_arg_is(&cmd->start_arg, tmp);
ebb657ba 2114 break;
03aef4b6 2115 }
c3be5c7f 2116
03aef4b6 2117 if (cmd->scan_begin_src == TRIG_TIMER) {
311fd9b2 2118 err |= comedi_check_trigger_arg_min(&cmd->scan_begin_arg,
c3be5c7f 2119 ni_min_ai_scan_period_ns(dev, cmd->chanlist_len));
311fd9b2
IA		 2120 err |= comedi_check_trigger_arg_max(&cmd->scan_begin_arg,
2121 devpriv->clock_ns *
2122 0xffffff);
03aef4b6
DS		 2123 } else if (cmd->scan_begin_src == TRIG_EXT) {
2124 /* external trigger */
2125 unsigned int tmp = CR_CHAN(cmd->scan_begin_arg);
2126
2127 if (tmp > 16)
2128 tmp = 16;
2129 tmp |= (cmd->scan_begin_arg & (CR_INVERT | CR_EDGE));
311fd9b2 2130 err |= comedi_check_trigger_arg_is(&cmd->scan_begin_arg, tmp);
03aef4b6 2131 } else { /* TRIG_OTHER */
311fd9b2 2132 err |= comedi_check_trigger_arg_is(&cmd->scan_begin_arg, 0);
03aef4b6 2133 }
c3be5c7f 2134
03aef4b6 2135 if (cmd->convert_src == TRIG_TIMER) {
a52b53e4 2136 if (devpriv->is_611x || devpriv->is_6143) {
311fd9b2
IA		 2137 err |= comedi_check_trigger_arg_is(&cmd->convert_arg,
2138 0);
03aef4b6 2139 } else {
311fd9b2
IA		 2140 err |= comedi_check_trigger_arg_min(&cmd->convert_arg,
2141 board->ai_speed);
2142 err |= comedi_check_trigger_arg_max(&cmd->convert_arg,
2143 devpriv->clock_ns *
2144 0xffff);
03aef4b6
DS		 2145 }
2146 } else if (cmd->convert_src == TRIG_EXT) {
2147 /* external trigger */
2148 unsigned int tmp = CR_CHAN(cmd->convert_arg);
2149
2150 if (tmp > 16)
2151 tmp = 16;
2152 tmp |= (cmd->convert_arg & (CR_ALT_FILTER | CR_INVERT));
311fd9b2 2153 err |= comedi_check_trigger_arg_is(&cmd->convert_arg, tmp);
03aef4b6 2154 } else if (cmd->convert_src == TRIG_NOW) {
311fd9b2 2155 err |= comedi_check_trigger_arg_is(&cmd->convert_arg, 0);
03aef4b6
DS		 2156 }
2157
311fd9b2
IA		 2158 err |= comedi_check_trigger_arg_is(&cmd->scan_end_arg,
2159 cmd->chanlist_len);
c3be5c7f 2160
03aef4b6
DS		 2161 if (cmd->stop_src == TRIG_COUNT) {
2162 unsigned int max_count = 0x01000000;
2163
a52b53e4 2164 if (devpriv->is_611x)
03aef4b6 2165 max_count -= num_adc_stages_611x;
311fd9b2
IA		 2166 err |= comedi_check_trigger_arg_max(&cmd->stop_arg, max_count);
2167 err |= comedi_check_trigger_arg_min(&cmd->stop_arg, 1);
03aef4b6
DS		 2168 } else {
2169 /* TRIG_NONE */
311fd9b2 2170 err |= comedi_check_trigger_arg_is(&cmd->stop_arg, 0);
03aef4b6
DS		 2171 }
2172
2173 if (err)
2174 return 3;
2175
2176 /* step 4: fix up any arguments */
2177
2178 if (cmd->scan_begin_src == TRIG_TIMER) {
2179 tmp = cmd->scan_begin_arg;
2180 cmd->scan_begin_arg =
0a85b6f0
MT		 2181 ni_timer_to_ns(dev, ni_ns_to_timer(dev,
2182 cmd->scan_begin_arg,
a207c12f 2183 cmd->flags));
03aef4b6
DS		 2184 if (tmp != cmd->scan_begin_arg)
2185 err++;
2186 }
2187 if (cmd->convert_src == TRIG_TIMER) {
a52b53e4 2188 if (!devpriv->is_611x && !devpriv->is_6143) {
03aef4b6
DS		 2189 tmp = cmd->convert_arg;
2190 cmd->convert_arg =
0a85b6f0
MT		 2191 ni_timer_to_ns(dev, ni_ns_to_timer(dev,
2192 cmd->convert_arg,
a207c12f 2193 cmd->flags));
03aef4b6
DS		 2194 if (tmp != cmd->convert_arg)
2195 err++;
2196 if (cmd->scan_begin_src == TRIG_TIMER &&
0a85b6f0
MT		 2197 cmd->scan_begin_arg <
2198 cmd->convert_arg * cmd->scan_end_arg) {
03aef4b6 2199 cmd->scan_begin_arg =
0a85b6f0 2200 cmd->convert_arg * cmd->scan_end_arg;
03aef4b6
DS		 2201 err++;
2202 }
2203 }
2204 }
2205
2206 if (err)
2207 return 4;
2208
2209 return 0;
2210}
2211
8511b858
HS		 2212static int ni_ai_inttrig(struct comedi_device *dev,
2213 struct comedi_subdevice *s,
2214 unsigned int trig_num)
2215{
2216 struct ni_private *devpriv = dev->private;
2217 struct comedi_cmd *cmd = &s->async->cmd;
2218
2219 if (trig_num != cmd->start_arg)
2220 return -EINVAL;
2221
a1da35a5
HS		 2222 ni_stc_writew(dev, NISTC_AI_CMD2_START1_PULSE | devpriv->ai_cmd2,
2223 NISTC_AI_CMD2_REG);
8511b858
HS		 2224 s->async->inttrig = NULL;
2225
2226 return 1;
2227}
2228
da91b269 2229static int ni_ai_cmd(struct comedi_device *dev, struct comedi_subdevice *s)
03aef4b6 2230{
0e05c552 2231 struct ni_private *devpriv = dev->private;
ea6d0d4c 2232 const struct comedi_cmd *cmd = &s->async->cmd;
03aef4b6
DS		 2233 int timer;
2234 int mode1 = 0; /* mode1 is needed for both stop and convert */
2235 int mode2 = 0;
2236 int start_stop_select = 0;
2237 unsigned int stop_count;
2238 int interrupt_a_enable = 0;
f878071a 2239 unsigned ai_trig;
03aef4b6 2240
03aef4b6 2241 if (dev->irq == 0) {
5ac1d82b 2242 dev_err(dev->class_dev, "cannot run command without an irq\n");
03aef4b6
DS		 2243 return -EIO;
2244 }
2245 ni_clear_ai_fifo(dev);
2246
817144ae 2247 ni_load_channelgain_list(dev, s, cmd->chanlist_len, cmd->chanlist);
03aef4b6
DS		 2248
2249 /* start configuration */
707502f3 2250 ni_stc_writew(dev, NISTC_RESET_AI_CFG_START, NISTC_RESET_REG);
03aef4b6
DS		 2251
2252 /* disable analog triggering for now, since it
2253 * interferes with the use of pfi0 */
27cf6c02
HS		 2254 devpriv->an_trig_etc_reg &= ~NISTC_ATRIG_ETC_ENA;
2255 ni_stc_writew(dev, devpriv->an_trig_etc_reg, NISTC_ATRIG_ETC_REG);
03aef4b6 2256
f878071a 2257 ai_trig = NISTC_AI_TRIG_START2_SEL(0) | NISTC_AI_TRIG_START1_SYNC;
03aef4b6
DS		 2258 switch (cmd->start_src) {
2259 case TRIG_INT:
2260 case TRIG_NOW:
f878071a
HS		 2261 ai_trig |= NISTC_AI_TRIG_START1_EDGE |
2262 NISTC_AI_TRIG_START1_SEL(0),
2263 NISTC_AI_TRIG_SEL_REG;
03aef4b6
DS		 2264 break;
2265 case TRIG_EXT:
f878071a
HS		 2266 ai_trig |= NISTC_AI_TRIG_START1_SEL(CR_CHAN(cmd->start_arg) +
2267 1);
2268
2269 if (cmd->start_arg & CR_INVERT)
2270 ai_trig |= NISTC_AI_TRIG_START1_POLARITY;
2271 if (cmd->start_arg & CR_EDGE)
2272 ai_trig |= NISTC_AI_TRIG_START1_EDGE;
2273 break;
03aef4b6 2274 }
f878071a 2275 ni_stc_writew(dev, ai_trig, NISTC_AI_TRIG_SEL_REG);
03aef4b6 2276
b134cc58
HS		 2277 mode2 &= ~NISTC_AI_MODE2_PRE_TRIGGER;
2278 mode2 &= ~NISTC_AI_MODE2_SC_INIT_LOAD_SRC;
2279 mode2 &= ~NISTC_AI_MODE2_SC_RELOAD_MODE;
2280 ni_stc_writew(dev, mode2, NISTC_AI_MODE2_REG);
03aef4b6 2281
a52b53e4 2282 if (cmd->chanlist_len == 1 || devpriv->is_611x || devpriv->is_6143) {
3e908892
HS		 2283 /* logic low */
2284 start_stop_select |= NISTC_AI_STOP_POLARITY |
2285 NISTC_AI_STOP_SEL(31) |
2286 NISTC_AI_STOP_SYNC;
03aef4b6 2287 } else {
3e908892
HS		 2288 /* ai configuration memory */
2289 start_stop_select |= NISTC_AI_STOP_SEL(19);
03aef4b6 2290 }
3e908892 2291 ni_stc_writew(dev, start_stop_select, NISTC_AI_START_STOP_REG);
03aef4b6
DS		 2292
2293 devpriv->ai_cmd2 = 0;
2294 switch (cmd->stop_src) {
2295 case TRIG_COUNT:
2296 stop_count = cmd->stop_arg - 1;
2297
a52b53e4 2298 if (devpriv->is_611x) {
2696fb57 2299 /* have to take 3 stage adc pipeline into account */
03aef4b6
DS		 2300 stop_count += num_adc_stages_611x;
2301 }
2302 /* stage number of scans */
a2c53736 2303 ni_stc_writel(dev, stop_count, NISTC_AI_SC_LOADA_REG);
03aef4b6 2304
bd358f5e
HS		 2305 mode1 |= NISTC_AI_MODE1_START_STOP |
2306 NISTC_AI_MODE1_RSVD |
2307 NISTC_AI_MODE1_TRIGGER_ONCE;
2308 ni_stc_writew(dev, mode1, NISTC_AI_MODE1_REG);
03aef4b6 2309 /* load SC (Scan Count) */
4c4d715a 2310 ni_stc_writew(dev, NISTC_AI_CMD1_SC_LOAD, NISTC_AI_CMD1_REG);
03aef4b6 2311
03aef4b6 2312 if (stop_count == 0) {
a1da35a5 2313 devpriv->ai_cmd2 |= NISTC_AI_CMD2_END_ON_EOS;
5cca26aa 2314 interrupt_a_enable |= NISTC_INTA_ENA_AI_STOP;
2696fb57 2315 /* this is required to get the last sample for chanlist_len > 1, not sure why */
03aef4b6 2316 if (cmd->chanlist_len > 1)
3e908892
HS		 2317 start_stop_select |= NISTC_AI_STOP_POLARITY |
2318 NISTC_AI_STOP_EDGE;
03aef4b6
DS		 2319 }
2320 break;
2321 case TRIG_NONE:
2322 /* stage number of scans */
a2c53736 2323 ni_stc_writel(dev, 0, NISTC_AI_SC_LOADA_REG);
03aef4b6 2324
bd358f5e
HS		 2325 mode1 |= NISTC_AI_MODE1_START_STOP |
2326 NISTC_AI_MODE1_RSVD |
2327 NISTC_AI_MODE1_CONTINUOUS;
2328 ni_stc_writew(dev, mode1, NISTC_AI_MODE1_REG);
03aef4b6
DS		 2329
2330 /* load SC (Scan Count) */
4c4d715a 2331 ni_stc_writew(dev, NISTC_AI_CMD1_SC_LOAD, NISTC_AI_CMD1_REG);
03aef4b6
DS		 2332 break;
2333 }
2334
2335 switch (cmd->scan_begin_src) {
2336 case TRIG_TIMER:
2337 /*
3e908892 2338 * stop bits for non 611x boards
c7edadc1 2339 * NISTC_AI_MODE3_SI_TRIG_DELAY=0
3e908892
HS		 2340 * NISTC_AI_MODE2_PRE_TRIGGER=0
2341 * NISTC_AI_START_STOP_REG:
2342 * NISTC_AI_START_POLARITY=0 (?) rising edge
2343 * NISTC_AI_START_EDGE=1 edge triggered
2344 * NISTC_AI_START_SYNC=1 (?)
2345 * NISTC_AI_START_SEL=0 SI_TC
2346 * NISTC_AI_STOP_POLARITY=0 rising edge
2347 * NISTC_AI_STOP_EDGE=0 level
2348 * NISTC_AI_STOP_SYNC=1
2349 * NISTC_AI_STOP_SEL=19 external pin (configuration mem)
03aef4b6 2350 */
3e908892
HS		 2351 start_stop_select |= NISTC_AI_START_EDGE | NISTC_AI_START_SYNC;
2352 ni_stc_writew(dev, start_stop_select, NISTC_AI_START_STOP_REG);
03aef4b6 2353
b134cc58
HS		 2354 mode2 &= ~NISTC_AI_MODE2_SI_INIT_LOAD_SRC; /* A */
2355 mode2 |= NISTC_AI_MODE2_SI_RELOAD_MODE(0);
2356 /* mode2 |= NISTC_AI_MODE2_SC_RELOAD_MODE; */
2357 ni_stc_writew(dev, mode2, NISTC_AI_MODE2_REG);
03aef4b6
DS		 2358
2359 /* load SI */
2360 timer = ni_ns_to_timer(dev, cmd->scan_begin_arg,
3280c2d2 2361 CMDF_ROUND_NEAREST);
a2c53736 2362 ni_stc_writel(dev, timer, NISTC_AI_SI_LOADA_REG);
4c4d715a 2363 ni_stc_writew(dev, NISTC_AI_CMD1_SI_LOAD, NISTC_AI_CMD1_REG);
03aef4b6
DS		 2364 break;
2365 case TRIG_EXT:
2366 if (cmd->scan_begin_arg & CR_EDGE)
3e908892
HS		 2367 start_stop_select |= NISTC_AI_START_EDGE;
2368 if (cmd->scan_begin_arg & CR_INVERT) /* falling edge */
2369 start_stop_select |= NISTC_AI_START_POLARITY;
03aef4b6 2370 if (cmd->scan_begin_src != cmd->convert_src ||
0a85b6f0
MT		 2371 (cmd->scan_begin_arg & ~CR_EDGE) !=
2372 (cmd->convert_arg & ~CR_EDGE))
3e908892 2373 start_stop_select |= NISTC_AI_START_SYNC;
03aef4b6 2374 start_stop_select |=
3e908892
HS		 2375 NISTC_AI_START_SEL(1 + CR_CHAN(cmd->scan_begin_arg));
2376 ni_stc_writew(dev, start_stop_select, NISTC_AI_START_STOP_REG);
03aef4b6
DS		 2377 break;
2378 }
2379
2380 switch (cmd->convert_src) {
2381 case TRIG_TIMER:
2382 case TRIG_NOW:
2383 if (cmd->convert_arg == 0 || cmd->convert_src == TRIG_NOW)
2384 timer = 1;
2385 else
2386 timer = ni_ns_to_timer(dev, cmd->convert_arg,
3280c2d2 2387 CMDF_ROUND_NEAREST);
00b14b1d 2388 /* 0,0 does not work */
a2c53736
HS		 2389 ni_stc_writew(dev, 1, NISTC_AI_SI2_LOADA_REG);
2390 ni_stc_writew(dev, timer, NISTC_AI_SI2_LOADB_REG);
03aef4b6 2391
b134cc58
HS		 2392 mode2 &= ~NISTC_AI_MODE2_SI2_INIT_LOAD_SRC; /* A */
2393 mode2 |= NISTC_AI_MODE2_SI2_RELOAD_MODE; /* alternate */
2394 ni_stc_writew(dev, mode2, NISTC_AI_MODE2_REG);
03aef4b6 2395
4c4d715a 2396 ni_stc_writew(dev, NISTC_AI_CMD1_SI2_LOAD, NISTC_AI_CMD1_REG);
03aef4b6 2397
b134cc58
HS		 2398 mode2 |= NISTC_AI_MODE2_SI2_INIT_LOAD_SRC; /* B */
2399 mode2 |= NISTC_AI_MODE2_SI2_RELOAD_MODE; /* alternate */
2400 ni_stc_writew(dev, mode2, NISTC_AI_MODE2_REG);
03aef4b6
DS		 2401 break;
2402 case TRIG_EXT:
bd358f5e 2403 mode1 |= NISTC_AI_MODE1_CONVERT_SRC(1 + cmd->convert_arg);
03aef4b6 2404 if ((cmd->convert_arg & CR_INVERT) == 0)
bd358f5e
HS		 2405 mode1 |= NISTC_AI_MODE1_CONVERT_POLARITY;
2406 ni_stc_writew(dev, mode1, NISTC_AI_MODE1_REG);
03aef4b6 2407
b134cc58
HS		 2408 mode2 |= NISTC_AI_MODE2_SC_GATE_ENA |
2409 NISTC_AI_MODE2_START_STOP_GATE_ENA;
2410 ni_stc_writew(dev, mode2, NISTC_AI_MODE2_REG);
03aef4b6
DS		 2411
2412 break;
2413 }
2414
2415 if (dev->irq) {
03aef4b6 2416 /* interrupt on FIFO, errors, SC_TC */
5cca26aa
HS		 2417 interrupt_a_enable |= NISTC_INTA_ENA_AI_ERR |
2418 NISTC_INTA_ENA_AI_SC_TC;
03aef4b6
DS		 2419
2420#ifndef PCIDMA
5cca26aa 2421 interrupt_a_enable |= NISTC_INTA_ENA_AI_FIFO;
03aef4b6
DS		 2422#endif
2423
a1da35a5
HS		 2424 if ((cmd->flags & CMDF_WAKE_EOS) ||
2425 (devpriv->ai_cmd2 & NISTC_AI_CMD2_END_ON_EOS)) {
03aef4b6
DS		 2426 /* wake on end-of-scan */
2427 devpriv->aimode = AIMODE_SCAN;
2428 } else {
2429 devpriv->aimode = AIMODE_HALF_FULL;
2430 }
2431
2432 switch (devpriv->aimode) {
2433 case AIMODE_HALF_FULL:
2434 /*generate FIFO interrupts and DMA requests on half-full */
2435#ifdef PCIDMA
c7edadc1
HS		 2436 ni_stc_writew(dev, NISTC_AI_MODE3_FIFO_MODE_HF_E,
2437 NISTC_AI_MODE3_REG);
03aef4b6 2438#else
c7edadc1
HS		 2439 ni_stc_writew(dev, NISTC_AI_MODE3_FIFO_MODE_HF,
2440 NISTC_AI_MODE3_REG);
03aef4b6
DS		 2441#endif
2442 break;
2443 case AIMODE_SAMPLE:
2444 /*generate FIFO interrupts on non-empty */
c7edadc1
HS		 2445 ni_stc_writew(dev, NISTC_AI_MODE3_FIFO_MODE_NE,
2446 NISTC_AI_MODE3_REG);
03aef4b6
DS		 2447 break;
2448 case AIMODE_SCAN:
2449#ifdef PCIDMA
c7edadc1
HS		 2450 ni_stc_writew(dev, NISTC_AI_MODE3_FIFO_MODE_NE,
2451 NISTC_AI_MODE3_REG);
03aef4b6 2452#else
c7edadc1
HS		 2453 ni_stc_writew(dev, NISTC_AI_MODE3_FIFO_MODE_HF,
2454 NISTC_AI_MODE3_REG);
03aef4b6 2455#endif
5cca26aa 2456 interrupt_a_enable |= NISTC_INTA_ENA_AI_STOP;
03aef4b6
DS		 2457 break;
2458 default:
2459 break;
2460 }
2461
00b14b1d 2462 /* clear interrupts */
480456d3 2463 ni_stc_writew(dev, NISTC_INTA_ACK_AI_ALL, NISTC_INTA_ACK_REG);
03aef4b6 2464
5cca26aa 2465 ni_set_bits(dev, NISTC_INTA_ENA_REG, interrupt_a_enable, 1);
03aef4b6
DS		 2466 } else {
2467 /* interrupt on nothing */
5cca26aa 2468 ni_set_bits(dev, NISTC_INTA_ENA_REG, ~0, 0);
03aef4b6
DS		 2469
2470 /* XXX start polling if necessary */
03aef4b6
DS		 2471 }
2472
2473 /* end configuration */
707502f3 2474 ni_stc_writew(dev, NISTC_RESET_AI_CFG_END, NISTC_RESET_REG);
03aef4b6
DS		 2475
2476 switch (cmd->scan_begin_src) {
2477 case TRIG_TIMER:
4c4d715a
HS		 2478 ni_stc_writew(dev, NISTC_AI_CMD1_SI2_ARM |
2479 NISTC_AI_CMD1_SI_ARM |
2480 NISTC_AI_CMD1_DIV_ARM |
2481 NISTC_AI_CMD1_SC_ARM,
2482 NISTC_AI_CMD1_REG);
03aef4b6
DS		 2483 break;
2484 case TRIG_EXT:
4c4d715a
HS		 2485 ni_stc_writew(dev, NISTC_AI_CMD1_SI2_ARM |
2486 NISTC_AI_CMD1_SI_ARM | /* XXX ? */
2487 NISTC_AI_CMD1_DIV_ARM |
2488 NISTC_AI_CMD1_SC_ARM,
2489 NISTC_AI_CMD1_REG);
03aef4b6
DS		 2490 break;
2491 }
2492
2493#ifdef PCIDMA
2494 {
2495 int retval = ni_ai_setup_MITE_dma(dev);
f7401979 2496
03aef4b6
DS		 2497 if (retval)
2498 return retval;
2499 }
03aef4b6
DS		 2500#endif
2501
ebb657ba 2502 if (cmd->start_src == TRIG_NOW) {
a1da35a5
HS		 2503 ni_stc_writew(dev, NISTC_AI_CMD2_START1_PULSE |
2504 devpriv->ai_cmd2,
2505 NISTC_AI_CMD2_REG);
03aef4b6 2506 s->async->inttrig = NULL;
ebb657ba 2507 } else if (cmd->start_src == TRIG_EXT) {
03aef4b6 2508 s->async->inttrig = NULL;
ebb657ba
HS		 2509 } else { /* TRIG_INT */
2510 s->async->inttrig = ni_ai_inttrig;
03aef4b6
DS		 2511 }
2512
03aef4b6
DS		 2513 return 0;
2514}
2515
d2a577c0
HS		 2516static int ni_ai_insn_config(struct comedi_device *dev,
2517 struct comedi_subdevice *s,
2518 struct comedi_insn *insn, unsigned int *data)
2519{
d2a577c0
HS		 2520 struct ni_private *devpriv = dev->private;
2521
2522 if (insn->n < 1)
2523 return -EINVAL;
2524
2525 switch (data[0]) {
d2a577c0 2526 case INSN_CONFIG_ALT_SOURCE:
17733219 2527 if (devpriv->is_m_series) {
41f9f0bf 2528 if (data[1] & ~NI_M_CFG_BYPASS_AI_CAL_MASK)
d2a577c0 2529 return -EINVAL;
d2a577c0 2530 devpriv->ai_calib_source = data[1];
a52b53e4 2531 } else if (devpriv->is_6143) {
d2a577c0
HS		 2532 unsigned int calib_source;
2533
2534 calib_source = data[1] & 0xf;
2535
d2a577c0 2536 devpriv->ai_calib_source = calib_source;
5a92cac5 2537 ni_writew(dev, calib_source, Calibration_Channel_6143);
d2a577c0
HS		 2538 } else {
2539 unsigned int calib_source;
2540 unsigned int calib_source_adjust;
2541
2542 calib_source = data[1] & 0xf;
2543 calib_source_adjust = (data[1] >> 4) & 0xff;
2544
2545 if (calib_source >= 8)
2546 return -EINVAL;
2547 devpriv->ai_calib_source = calib_source;
a52b53e4 2548 if (devpriv->is_611x) {
5a92cac5
HS		 2549 ni_writeb(dev, calib_source_adjust,
2550 Cal_Gain_Select_611x);
d2a577c0
HS		 2551 }
2552 }
2553 return 2;
2554 default:
2555 break;
2556 }
2557
2558 return -EINVAL;
2559}
2560
da91b269 2561static void ni_ao_munge(struct comedi_device *dev, struct comedi_subdevice *s,
0a85b6f0
MT		 2562 void *data, unsigned int num_bytes,
2563 unsigned int chan_index)
03aef4b6 2564{
a10817d6 2565 struct comedi_cmd *cmd = &s->async->cmd;
c39e050d 2566 unsigned int nsamples = comedi_bytes_to_samples(s, num_bytes);
3a2b101c 2567 unsigned short *array = data;
9663ab1f 2568 unsigned int i;
03aef4b6 2569
c39e050d 2570 for (i = 0; i < nsamples; i++) {
a10817d6
HS		 2571 unsigned int range = CR_RANGE(cmd->chanlist[chan_index]);
2572 unsigned short val = array[i];
fed3c23b 2573
a10817d6
HS		 2574 /*
2575 * Munge data from unsigned to two's complement for
2576 * bipolar ranges.
2577 */
fed3c23b 2578 if (comedi_range_is_bipolar(s, range))
a10817d6 2579 val = comedi_offset_munge(s, val);
03aef4b6 2580#ifdef PCIDMA
a10817d6 2581 val = cpu_to_le16(val);
03aef4b6 2582#endif
a10817d6
HS		 2583 array[i] = val;
2584
03aef4b6 2585 chan_index++;
9663ab1f 2586 chan_index %= cmd->chanlist_len;
03aef4b6
DS		 2587 }
2588}
2589
da91b269 2590static int ni_m_series_ao_config_chanlist(struct comedi_device *dev,
0a85b6f0
MT		 2591 struct comedi_subdevice *s,
2592 unsigned int chanspec[],
2593 unsigned int n_chans, int timed)
03aef4b6 2594{
0e05c552 2595 struct ni_private *devpriv = dev->private;
03aef4b6
DS		 2596 unsigned int range;
2597 unsigned int chan;
2598 unsigned int conf;
2599 int i;
2600 int invert = 0;
2601
53106ae6 2602 if (timed) {
47277365 2603 for (i = 0; i < s->n_chan; ++i) {
bae45304 2604 devpriv->ao_conf[i] &= ~NI_M_AO_CFG_BANK_UPDATE_TIMED;
5a92cac5 2605 ni_writeb(dev, devpriv->ao_conf[i],
975b6d25
HS		 2606 NI_M_AO_CFG_BANK_REG(i));
2607 ni_writeb(dev, 0xf, NI_M_AO_WAVEFORM_ORDER_REG(i));
03aef4b6
DS		 2608 }
2609 }
2610 for (i = 0; i < n_chans; i++) {
1f6325d6 2611 const struct comedi_krange *krange;
f7401979 2612
03aef4b6
DS		 2613 chan = CR_CHAN(chanspec[i]);
2614 range = CR_RANGE(chanspec[i]);
2615 krange = s->range_table->range + range;
2616 invert = 0;
2617 conf = 0;
2618 switch (krange->max - krange->min) {
2619 case 20000000:
bae45304 2620 conf |= NI_M_AO_CFG_BANK_REF_INT_10V;
975b6d25 2621 ni_writeb(dev, 0, NI_M_AO_REF_ATTENUATION_REG(chan));
03aef4b6
DS		 2622 break;
2623 case 10000000:
bae45304 2624 conf |= NI_M_AO_CFG_BANK_REF_INT_5V;
975b6d25 2625 ni_writeb(dev, 0, NI_M_AO_REF_ATTENUATION_REG(chan));
03aef4b6
DS		 2626 break;
2627 case 4000000:
bae45304 2628 conf |= NI_M_AO_CFG_BANK_REF_INT_10V;
b06afa15 2629 ni_writeb(dev, NI_M_AO_REF_ATTENUATION_X5,
975b6d25 2630 NI_M_AO_REF_ATTENUATION_REG(chan));
03aef4b6
DS		 2631 break;
2632 case 2000000:
bae45304 2633 conf |= NI_M_AO_CFG_BANK_REF_INT_5V;
b06afa15 2634 ni_writeb(dev, NI_M_AO_REF_ATTENUATION_X5,
975b6d25 2635 NI_M_AO_REF_ATTENUATION_REG(chan));
03aef4b6
DS		 2636 break;
2637 default:
89c4695e 2638 dev_err(dev->class_dev,
cd25503f 2639 "bug! unhandled ao reference voltage\n");
03aef4b6
DS		 2640 break;
2641 }
2642 switch (krange->max + krange->min) {
2643 case 0:
bae45304 2644 conf |= NI_M_AO_CFG_BANK_OFFSET_0V;
03aef4b6
DS		 2645 break;
2646 case 10000000:
bae45304 2647 conf |= NI_M_AO_CFG_BANK_OFFSET_5V;
03aef4b6
DS		 2648 break;
2649 default:
89c4695e 2650 dev_err(dev->class_dev,
cd25503f 2651 "bug! unhandled ao offset voltage\n");
03aef4b6
DS		 2652 break;
2653 }
2654 if (timed)
bae45304 2655 conf |= NI_M_AO_CFG_BANK_UPDATE_TIMED;
975b6d25 2656 ni_writeb(dev, conf, NI_M_AO_CFG_BANK_REG(chan));
03aef4b6 2657 devpriv->ao_conf[chan] = conf;
975b6d25 2658 ni_writeb(dev, i, NI_M_AO_WAVEFORM_ORDER_REG(chan));
03aef4b6
DS		 2659 }
2660 return invert;
2661}
2662
0a85b6f0
MT		 2663static int ni_old_ao_config_chanlist(struct comedi_device *dev,
2664 struct comedi_subdevice *s,
2665 unsigned int chanspec[],
2666 unsigned int n_chans)
03aef4b6 2667{
0e05c552 2668 struct ni_private *devpriv = dev->private;
03aef4b6
DS		 2669 unsigned int range;
2670 unsigned int chan;
2671 unsigned int conf;
2672 int i;
2673 int invert = 0;
2674
2675 for (i = 0; i < n_chans; i++) {
2676 chan = CR_CHAN(chanspec[i]);
2677 range = CR_RANGE(chanspec[i]);
b497b8da 2678 conf = NI_E_AO_DACSEL(chan);
03aef4b6 2679
fed3c23b 2680 if (comedi_range_is_bipolar(s, range)) {
b497b8da 2681 conf |= NI_E_AO_CFG_BIP;
47277365 2682 invert = (s->maxdata + 1) >> 1;
fed3c23b
HS		 2683 } else {
2684 invert = 0;
03aef4b6 2685 }
fed3c23b 2686 if (comedi_range_is_external(s, range))
b497b8da 2687 conf |= NI_E_AO_EXT_REF;
03aef4b6
DS		 2688
2689 /* not all boards can deglitch, but this shouldn't hurt */
2690 if (chanspec[i] & CR_DEGLITCH)
b497b8da 2691 conf |= NI_E_AO_DEGLITCH;
03aef4b6
DS		 2692
2693 /* analog reference */
2694 /* AREF_OTHER connects AO ground to AI ground, i think */
b497b8da
HS		 2695 if (CR_AREF(chanspec[i]) == AREF_OTHER)
2696 conf |= NI_E_AO_GROUND_REF;
03aef4b6 2697
b497b8da 2698 ni_writew(dev, conf, NI_E_AO_CFG_REG);
03aef4b6
DS		 2699 devpriv->ao_conf[chan] = conf;
2700 }
2701 return invert;
2702}
2703
0a85b6f0
MT		 2704static int ni_ao_config_chanlist(struct comedi_device *dev,
2705 struct comedi_subdevice *s,
2706 unsigned int chanspec[], unsigned int n_chans,
2707 int timed)
03aef4b6 2708{
17733219 2709 struct ni_private *devpriv = dev->private;
6293e357 2710
17733219 2711 if (devpriv->is_m_series)
03aef4b6 2712 return ni_m_series_ao_config_chanlist(dev, s, chanspec, n_chans,
0a85b6f0 2713 timed);
03aef4b6
DS		 2714 else
2715 return ni_old_ao_config_chanlist(dev, s, chanspec, n_chans);
2716}
0a85b6f0 2717
0a85b6f0
MT		 2718static int ni_ao_insn_write(struct comedi_device *dev,
2719 struct comedi_subdevice *s,
bfb0c28b
HS		 2720 struct comedi_insn *insn,
2721 unsigned int *data)
03aef4b6 2722{
0e05c552 2723 struct ni_private *devpriv = dev->private;
03aef4b6 2724 unsigned int chan = CR_CHAN(insn->chanspec);
bfb0c28b
HS		 2725 unsigned int range = CR_RANGE(insn->chanspec);
2726 int reg;
2727 int i;
03aef4b6 2728
79816da1
HS		 2729 if (devpriv->is_6xxx) {
2730 ni_ao_win_outw(dev, 1 << chan, AO_Immediate_671x);
2731
2732 reg = DACx_Direct_Data_671x(chan);
2733 } else if (devpriv->is_m_series) {
975b6d25 2734 reg = NI_M_DAC_DIRECT_DATA_REG(chan);
79816da1 2735 } else {
bfb0c28b 2736 reg = (chan) ? DAC1_Direct_Data : DAC0_Direct_Data;
79816da1 2737 }
03aef4b6 2738
bfb0c28b 2739 ni_ao_config_chanlist(dev, s, &insn->chanspec, 1, 0);
03aef4b6 2740
bfb0c28b
HS		 2741 for (i = 0; i < insn->n; i++) {
2742 unsigned int val = data[i];
03aef4b6 2743
b6d977e9 2744 s->readback[chan] = val;
bfb0c28b 2745
79816da1
HS		 2746 if (devpriv->is_6xxx) {
2747 /*
2748 * 6xxx boards have bipolar outputs, munge the
2749 * unsigned comedi values to 2's complement
2750 */
2751 val = comedi_offset_munge(s, val);
2752
2753 ni_ao_win_outw(dev, val, reg);
2754 } else if (devpriv->is_m_series) {
2755 /*
2756 * M-series boards use offset binary values for
2757 * bipolar and uinpolar outputs
2758 */
bfb0c28b
HS		 2759 ni_writew(dev, val, reg);
2760 } else {
2761 /*
2762 * Non-M series boards need two's complement values
2763 * for bipolar ranges.
2764 */
2765 if (comedi_range_is_bipolar(s, range))
2766 val = comedi_offset_munge(s, val);
2767
2768 ni_writew(dev, val, reg);
2769 }
2770 }
2771
2772 return insn->n;
03aef4b6
DS		 2773}
2774
0a85b6f0
MT		 2775static int ni_ao_insn_config(struct comedi_device *dev,
2776 struct comedi_subdevice *s,
2777 struct comedi_insn *insn, unsigned int *data)
03aef4b6 2778{
7cf94adc 2779 const struct ni_board_struct *board = dev->board_ptr;
0e05c552 2780 struct ni_private *devpriv = dev->private;
836b571d 2781 unsigned int nbytes;
0e05c552 2782
03aef4b6
DS		 2783 switch (data[0]) {
2784 case INSN_CONFIG_GET_HARDWARE_BUFFER_SIZE:
0a85b6f0 2785 switch (data[1]) {
03aef4b6 2786 case COMEDI_OUTPUT:
836b571d
HS		 2787 nbytes = comedi_samples_to_bytes(s,
2788 board->ao_fifo_depth);
2789 data[2] = 1 + nbytes;
0a85b6f0
MT		 2790 if (devpriv->mite)
2791 data[2] += devpriv->mite->fifo_size;
03aef4b6
DS		 2792 break;
2793 case COMEDI_INPUT:
2794 data[2] = 0;
2795 break;
2796 default:
2797 return -EINVAL;
03aef4b6
DS		 2798 }
2799 return 0;
2800 default:
2801 break;
2802 }
2803
2804 return -EINVAL;
2805}
2806
ebb657ba
HS		 2807static int ni_ao_inttrig(struct comedi_device *dev,
2808 struct comedi_subdevice *s,
2809 unsigned int trig_num)
03aef4b6 2810{
0e05c552 2811 struct ni_private *devpriv = dev->private;
ebb657ba 2812 struct comedi_cmd *cmd = &s->async->cmd;
03aef4b6
DS		 2813 int ret;
2814 int interrupt_b_bits;
2815 int i;
2816 static const int timeout = 1000;
2817
ebb657ba 2818 if (trig_num != cmd->start_arg)
03aef4b6
DS		 2819 return -EINVAL;
2820
2821 /* Null trig at beginning prevent ao start trigger from executing more than
2822 once per command (and doing things like trying to allocate the ao dma channel
2823 multiple times) */
2824 s->async->inttrig = NULL;
2825
4c9c1d2c
HS		 2826 ni_set_bits(dev, NISTC_INTB_ENA_REG,
2827 NISTC_INTB_ENA_AO_FIFO | NISTC_INTB_ENA_AO_ERR, 0);
2828 interrupt_b_bits = NISTC_INTB_ENA_AO_ERR;
03aef4b6 2829#ifdef PCIDMA
8102f3d0 2830 ni_stc_writew(dev, 1, NISTC_DAC_FIFO_CLR_REG);
a52b53e4 2831 if (devpriv->is_6xxx)
03aef4b6
DS		 2832 ni_ao_win_outl(dev, 0x6, AO_FIFO_Offset_Load_611x);
2833 ret = ni_ao_setup_MITE_dma(dev);
2834 if (ret)
2835 return ret;
2836 ret = ni_ao_wait_for_dma_load(dev);
2837 if (ret < 0)
2838 return ret;
2839#else
2840 ret = ni_ao_prep_fifo(dev, s);
2841 if (ret == 0)
2842 return -EPIPE;
2843
4c9c1d2c 2844 interrupt_b_bits |= NISTC_INTB_ENA_AO_FIFO;
03aef4b6
DS		 2845#endif
2846
72bca4f5
HS		 2847 ni_stc_writew(dev, devpriv->ao_mode3 | NISTC_AO_MODE3_NOT_AN_UPDATE,
2848 NISTC_AO_MODE3_REG);
2849 ni_stc_writew(dev, devpriv->ao_mode3, NISTC_AO_MODE3_REG);
03aef4b6
DS		 2850 /* wait for DACs to be loaded */
2851 for (i = 0; i < timeout; i++) {
5f74ea14 2852 udelay(1);
bab382ef
HS		 2853 if ((ni_stc_readw(dev, NISTC_STATUS2_REG) &
2854 NISTC_STATUS2_AO_TMRDACWRS_IN_PROGRESS) == 0)
03aef4b6
DS		 2855 break;
2856 }
2857 if (i == timeout) {
5ac1d82b
HS		 2858 dev_err(dev->class_dev,
2859 "timed out waiting for AO_TMRDACWRs_In_Progress_St to clear\n");
03aef4b6
DS		 2860 return -EIO;
2861 }
00b14b1d
HS		 2862 /*
2863 * stc manual says we are need to clear error interrupt after
2864 * AO_TMRDACWRs_In_Progress_St clears
2865 */
4a6de832 2866 ni_stc_writew(dev, NISTC_INTB_ACK_AO_ERR, NISTC_INTB_ACK_REG);
03aef4b6 2867
4c9c1d2c 2868 ni_set_bits(dev, NISTC_INTB_ENA_REG, interrupt_b_bits, 1);
03aef4b6 2869
7bfcc2d4
HS		 2870 ni_stc_writew(dev, NISTC_AO_CMD1_UI_ARM |
2871 NISTC_AO_CMD1_UC_ARM |
2872 NISTC_AO_CMD1_BC_ARM |
2873 NISTC_AO_CMD1_DAC1_UPDATE_MODE |
2874 NISTC_AO_CMD1_DAC0_UPDATE_MODE |
2875 devpriv->ao_cmd1,
2876 NISTC_AO_CMD1_REG);
03aef4b6 2877
382b3c4f
HS		 2878 ni_stc_writew(dev, NISTC_AO_CMD2_START1_PULSE | devpriv->ao_cmd2,
2879 NISTC_AO_CMD2_REG);
03aef4b6
DS		 2880
2881 return 0;
2882}
2883
da91b269 2884static int ni_ao_cmd(struct comedi_device *dev, struct comedi_subdevice *s)
03aef4b6 2885{
7cf94adc 2886 const struct ni_board_struct *board = dev->board_ptr;
0e05c552 2887 struct ni_private *devpriv = dev->private;
ea6d0d4c 2888 const struct comedi_cmd *cmd = &s->async->cmd;
03aef4b6
DS		 2889 int bits;
2890 int i;
2891 unsigned trigvar;
f21844d3 2892 unsigned val;
03aef4b6
DS		 2893
2894 if (dev->irq == 0) {
5ac1d82b 2895 dev_err(dev->class_dev, "cannot run command without an irq\n");
03aef4b6
DS		 2896 return -EIO;
2897 }
2898
707502f3 2899 ni_stc_writew(dev, NISTC_RESET_AO_CFG_START, NISTC_RESET_REG);
03aef4b6 2900
7bfcc2d4 2901 ni_stc_writew(dev, NISTC_AO_CMD1_DISARM, NISTC_AO_CMD1_REG);
03aef4b6 2902
a52b53e4 2903 if (devpriv->is_6xxx) {
87b4fe5c 2904 ni_ao_win_outw(dev, CLEAR_WG, AO_Misc_611x);
03aef4b6
DS		 2905
2906 bits = 0;
2907 for (i = 0; i < cmd->chanlist_len; i++) {
2908 int chan;
2909
2910 chan = CR_CHAN(cmd->chanlist[i]);
2911 bits |= 1 << chan;
87b4fe5c 2912 ni_ao_win_outw(dev, chan, AO_Waveform_Generation_611x);
03aef4b6 2913 }
87b4fe5c 2914 ni_ao_win_outw(dev, bits, AO_Timed_611x);
03aef4b6
DS		 2915 }
2916
2917 ni_ao_config_chanlist(dev, s, cmd->chanlist, cmd->chanlist_len, 1);
2918
2919 if (cmd->stop_src == TRIG_NONE) {
4e5ce0a8
HS		 2920 devpriv->ao_mode1 |= NISTC_AO_MODE1_CONTINUOUS;
2921 devpriv->ao_mode1 &= ~NISTC_AO_MODE1_TRIGGER_ONCE;
03aef4b6 2922 } else {
4e5ce0a8
HS		 2923 devpriv->ao_mode1 &= ~NISTC_AO_MODE1_CONTINUOUS;
2924 devpriv->ao_mode1 |= NISTC_AO_MODE1_TRIGGER_ONCE;
03aef4b6 2925 }
4e5ce0a8 2926 ni_stc_writew(dev, devpriv->ao_mode1, NISTC_AO_MODE1_REG);
f21844d3
HS		 2927
2928 val = devpriv->ao_trigger_select;
03aef4b6
DS		 2929 switch (cmd->start_src) {
2930 case TRIG_INT:
2931 case TRIG_NOW:
f21844d3
HS		 2932 val &= ~(NISTC_AO_TRIG_START1_POLARITY |
2933 NISTC_AO_TRIG_START1_SEL_MASK);
2934 val |= NISTC_AO_TRIG_START1_EDGE |
2935 NISTC_AO_TRIG_START1_SYNC;
03aef4b6
DS		 2936 break;
2937 case TRIG_EXT:
f21844d3
HS		 2938 val = NISTC_AO_TRIG_START1_SEL(CR_CHAN(cmd->start_arg) + 1);
2939 if (cmd->start_arg & CR_INVERT) {
2940 /* 0=active high, 1=active low. see daq-stc 3-24 (p186) */
2941 val |= NISTC_AO_TRIG_START1_POLARITY;
2942 }
2943 if (cmd->start_arg & CR_EDGE) {
2944 /* 0=edge detection disabled, 1=enabled */
2945 val |= NISTC_AO_TRIG_START1_EDGE;
2946 }
00b14b1d 2947 ni_stc_writew(dev, devpriv->ao_trigger_select,
f21844d3 2948 NISTC_AO_TRIG_SEL_REG);
03aef4b6
DS		 2949 break;
2950 default:
2951 BUG();
2952 break;
2953 }
f21844d3
HS		 2954 devpriv->ao_trigger_select = val;
2955 ni_stc_writew(dev, devpriv->ao_trigger_select, NISTC_AO_TRIG_SEL_REG);
2956
72bca4f5
HS		 2957 devpriv->ao_mode3 &= ~NISTC_AO_MODE3_TRIG_LEN;
2958 ni_stc_writew(dev, devpriv->ao_mode3, NISTC_AO_MODE3_REG);
03aef4b6 2959
4e5ce0a8 2960 ni_stc_writew(dev, devpriv->ao_mode1, NISTC_AO_MODE1_REG);
ec8bf725
HS		 2961 devpriv->ao_mode2 &= ~NISTC_AO_MODE2_BC_INIT_LOAD_SRC;
2962 ni_stc_writew(dev, devpriv->ao_mode2, NISTC_AO_MODE2_REG);
bc461556 2963 if (cmd->stop_src == TRIG_NONE)
37e0ecee 2964 ni_stc_writel(dev, 0xffffff, NISTC_AO_BC_LOADA_REG);
bc461556 2965 else
37e0ecee 2966 ni_stc_writel(dev, 0, NISTC_AO_BC_LOADA_REG);
7bfcc2d4 2967 ni_stc_writew(dev, NISTC_AO_CMD1_BC_LOAD, NISTC_AO_CMD1_REG);
ec8bf725
HS		 2968 devpriv->ao_mode2 &= ~NISTC_AO_MODE2_UC_INIT_LOAD_SRC;
2969 ni_stc_writew(dev, devpriv->ao_mode2, NISTC_AO_MODE2_REG);
03aef4b6
DS		 2970 switch (cmd->stop_src) {
2971 case TRIG_COUNT:
17733219 2972 if (devpriv->is_m_series) {
2696fb57 2973 /* this is how the NI example code does it for m-series boards, verified correct with 6259 */
00b14b1d 2974 ni_stc_writel(dev, cmd->stop_arg - 1,
37e0ecee 2975 NISTC_AO_UC_LOADA_REG);
7bfcc2d4
HS		 2976 ni_stc_writew(dev, NISTC_AO_CMD1_UC_LOAD,
2977 NISTC_AO_CMD1_REG);
0a85b6f0 2978 } else {
00b14b1d 2979 ni_stc_writel(dev, cmd->stop_arg,
37e0ecee 2980 NISTC_AO_UC_LOADA_REG);
7bfcc2d4
HS		 2981 ni_stc_writew(dev, NISTC_AO_CMD1_UC_LOAD,
2982 NISTC_AO_CMD1_REG);
00b14b1d 2983 ni_stc_writel(dev, cmd->stop_arg - 1,
37e0ecee 2984 NISTC_AO_UC_LOADA_REG);
03aef4b6
DS		 2985 }
2986 break;
2987 case TRIG_NONE:
37e0ecee 2988 ni_stc_writel(dev, 0xffffff, NISTC_AO_UC_LOADA_REG);
7bfcc2d4 2989 ni_stc_writew(dev, NISTC_AO_CMD1_UC_LOAD, NISTC_AO_CMD1_REG);
37e0ecee 2990 ni_stc_writel(dev, 0xffffff, NISTC_AO_UC_LOADA_REG);
03aef4b6
DS		 2991 break;
2992 default:
37e0ecee 2993 ni_stc_writel(dev, 0, NISTC_AO_UC_LOADA_REG);
7bfcc2d4 2994 ni_stc_writew(dev, NISTC_AO_CMD1_UC_LOAD, NISTC_AO_CMD1_REG);
37e0ecee 2995 ni_stc_writel(dev, cmd->stop_arg, NISTC_AO_UC_LOADA_REG);
03aef4b6
DS		 2996 }
2997
4e5ce0a8
HS		 2998 devpriv->ao_mode1 &= ~(NISTC_AO_MODE1_UPDATE_SRC_MASK |
2999 NISTC_AO_MODE1_UI_SRC_MASK |
3000 NISTC_AO_MODE1_UPDATE_SRC_POLARITY |
3001 NISTC_AO_MODE1_UI_SRC_POLARITY);
03aef4b6
DS		 3002 switch (cmd->scan_begin_src) {
3003 case TRIG_TIMER:
382b3c4f 3004 devpriv->ao_cmd2 &= ~NISTC_AO_CMD2_BC_GATE_ENA;
03aef4b6 3005 trigvar =
0a85b6f0 3006 ni_ns_to_timer(dev, cmd->scan_begin_arg,
3280c2d2 3007 CMDF_ROUND_NEAREST);
37e0ecee 3008 ni_stc_writel(dev, 1, NISTC_AO_UI_LOADA_REG);
7bfcc2d4 3009 ni_stc_writew(dev, NISTC_AO_CMD1_UI_LOAD, NISTC_AO_CMD1_REG);
37e0ecee 3010 ni_stc_writel(dev, trigvar, NISTC_AO_UI_LOADA_REG);
03aef4b6
DS		 3011 break;
3012 case TRIG_EXT:
3013 devpriv->ao_mode1 |=
4e5ce0a8 3014 NISTC_AO_MODE1_UPDATE_SRC(cmd->scan_begin_arg);
03aef4b6 3015 if (cmd->scan_begin_arg & CR_INVERT)
4e5ce0a8 3016 devpriv->ao_mode1 |= NISTC_AO_MODE1_UPDATE_SRC_POLARITY;
382b3c4f 3017 devpriv->ao_cmd2 |= NISTC_AO_CMD2_BC_GATE_ENA;
03aef4b6
DS		 3018 break;
3019 default:
3020 BUG();
3021 break;
3022 }
382b3c4f 3023 ni_stc_writew(dev, devpriv->ao_cmd2, NISTC_AO_CMD2_REG);
4e5ce0a8 3024 ni_stc_writew(dev, devpriv->ao_mode1, NISTC_AO_MODE1_REG);
ec8bf725
HS		 3025 devpriv->ao_mode2 &= ~(NISTC_AO_MODE2_UI_RELOAD_MODE(3) |
3026 NISTC_AO_MODE2_UI_INIT_LOAD_SRC);
3027 ni_stc_writew(dev, devpriv->ao_mode2, NISTC_AO_MODE2_REG);
03aef4b6
DS		 3028
3029 if (cmd->scan_end_arg > 1) {
4e5ce0a8 3030 devpriv->ao_mode1 |= NISTC_AO_MODE1_MULTI_CHAN;
00b14b1d 3031 ni_stc_writew(dev,
5bd1c728
HS		 3032 NISTC_AO_OUT_CTRL_CHANS(cmd->scan_end_arg - 1) |
3033 NISTC_AO_OUT_CTRL_UPDATE_SEL_HIGHZ,
3034 NISTC_AO_OUT_CTRL_REG);
03aef4b6
DS		 3035 } else {
3036 unsigned bits;
f7401979 3037
4e5ce0a8 3038 devpriv->ao_mode1 &= ~NISTC_AO_MODE1_MULTI_CHAN;
5bd1c728 3039 bits = NISTC_AO_OUT_CTRL_UPDATE_SEL_HIGHZ;
a52b53e4 3040 if (devpriv->is_m_series || devpriv->is_6xxx) {
5bd1c728 3041 bits |= NISTC_AO_OUT_CTRL_CHANS(0);
03aef4b6 3042 } else {
0a85b6f0 3043 bits |=
5bd1c728 3044 NISTC_AO_OUT_CTRL_CHANS(CR_CHAN(cmd->chanlist[0]));
03aef4b6 3045 }
5bd1c728 3046 ni_stc_writew(dev, bits, NISTC_AO_OUT_CTRL_REG);
03aef4b6 3047 }
4e5ce0a8 3048 ni_stc_writew(dev, devpriv->ao_mode1, NISTC_AO_MODE1_REG);
03aef4b6 3049
7bfcc2d4
HS		 3050 ni_stc_writew(dev, NISTC_AO_CMD1_DAC1_UPDATE_MODE |
3051 NISTC_AO_CMD1_DAC0_UPDATE_MODE,
3052 NISTC_AO_CMD1_REG);
03aef4b6 3053
72bca4f5
HS		 3054 devpriv->ao_mode3 |= NISTC_AO_MODE3_STOP_ON_OVERRUN_ERR;
3055 ni_stc_writew(dev, devpriv->ao_mode3, NISTC_AO_MODE3_REG);
03aef4b6 3056
ec8bf725 3057 devpriv->ao_mode2 &= ~NISTC_AO_MODE2_FIFO_MODE_MASK;
03aef4b6 3058#ifdef PCIDMA
ec8bf725 3059 devpriv->ao_mode2 |= NISTC_AO_MODE2_FIFO_MODE_HF_F;
03aef4b6 3060#else
ec8bf725 3061 devpriv->ao_mode2 |= NISTC_AO_MODE2_FIFO_MODE_HF;
03aef4b6 3062#endif
ec8bf725
HS		 3063 devpriv->ao_mode2 &= ~NISTC_AO_MODE2_FIFO_REXMIT_ENA;
3064 ni_stc_writew(dev, devpriv->ao_mode2, NISTC_AO_MODE2_REG);
03aef4b6 3065
63ff3f2c
HS		 3066 bits = NISTC_AO_PERSONAL_BC_SRC_SEL |
3067 NISTC_AO_PERSONAL_UPDATE_PW |
3068 NISTC_AO_PERSONAL_TMRDACWR_PW;
6293e357 3069 if (board->ao_fifo_depth)
63ff3f2c 3070 bits |= NISTC_AO_PERSONAL_FIFO_ENA;
03aef4b6 3071 else
63ff3f2c 3072 bits |= NISTC_AO_PERSONAL_DMA_PIO_CTRL;
03aef4b6 3073#if 0
63ff3f2c
HS		 3074 /*
3075 * F Hess: windows driver does not set NISTC_AO_PERSONAL_NUM_DAC bit
3076 * for 6281, verified with bus analyzer.
3077 */
17733219 3078 if (devpriv->is_m_series)
63ff3f2c 3079 bits |= NISTC_AO_PERSONAL_NUM_DAC;
03aef4b6 3080#endif
63ff3f2c 3081 ni_stc_writew(dev, bits, NISTC_AO_PERSONAL_REG);
2696fb57 3082 /* enable sending of ao dma requests */
2b6285da 3083 ni_stc_writew(dev, NISTC_AO_START_AOFREQ_ENA, NISTC_AO_START_SEL_REG);
03aef4b6 3084
707502f3 3085 ni_stc_writew(dev, NISTC_RESET_AO_CFG_END, NISTC_RESET_REG);
03aef4b6
DS		 3086
3087 if (cmd->stop_src == TRIG_COUNT) {
4a6de832
HS		 3088 ni_stc_writew(dev, NISTC_INTB_ACK_AO_BC_TC,
3089 NISTC_INTB_ACK_REG);
4c9c1d2c
HS		 3090 ni_set_bits(dev, NISTC_INTB_ENA_REG,
3091 NISTC_INTB_ENA_AO_BC_TC, 1);
03aef4b6
DS		 3092 }
3093
ebb657ba 3094 s->async->inttrig = ni_ao_inttrig;
03aef4b6
DS		 3095
3096 return 0;
3097}
3098
da91b269 3099static int ni_ao_cmdtest(struct comedi_device *dev, struct comedi_subdevice *s,
0a85b6f0 3100 struct comedi_cmd *cmd)
03aef4b6 3101{
7cf94adc 3102 const struct ni_board_struct *board = dev->board_ptr;
0e05c552 3103 struct ni_private *devpriv = dev->private;
03aef4b6 3104 int err = 0;
ebb657ba 3105 unsigned int tmp;
03aef4b6 3106
27020ffe 3107 /* Step 1 : check if triggers are trivially valid */
03aef4b6 3108
311fd9b2
IA		 3109 err |= comedi_check_trigger_src(&cmd->start_src, TRIG_INT | TRIG_EXT);
3110 err |= comedi_check_trigger_src(&cmd->scan_begin_src,
27020ffe 3111 TRIG_TIMER | TRIG_EXT);
311fd9b2
IA		 3112 err |= comedi_check_trigger_src(&cmd->convert_src, TRIG_NOW);
3113 err |= comedi_check_trigger_src(&cmd->scan_end_src, TRIG_COUNT);
3114 err |= comedi_check_trigger_src(&cmd->stop_src, TRIG_COUNT | TRIG_NONE);
03aef4b6
DS		 3115
3116 if (err)
3117 return 1;
3118
27020ffe 3119 /* Step 2a : make sure trigger sources are unique */
03aef4b6 3120
311fd9b2
IA		 3121 err |= comedi_check_trigger_is_unique(cmd->start_src);
3122 err |= comedi_check_trigger_is_unique(cmd->scan_begin_src);
3123 err |= comedi_check_trigger_is_unique(cmd->stop_src);
27020ffe
HS		 3124
3125 /* Step 2b : and mutually compatible */
03aef4b6
DS		 3126
3127 if (err)
3128 return 2;
3129
c3be5c7f 3130 /* Step 3: check if arguments are trivially valid */
03aef4b6 3131
ebb657ba
HS		 3132 switch (cmd->start_src) {
3133 case TRIG_INT:
311fd9b2 3134 err |= comedi_check_trigger_arg_is(&cmd->start_arg, 0);
ebb657ba
HS		 3135 break;
3136 case TRIG_EXT:
3137 tmp = CR_CHAN(cmd->start_arg);
03aef4b6
DS		 3138
3139 if (tmp > 18)
3140 tmp = 18;
3141 tmp |= (cmd->start_arg & (CR_INVERT | CR_EDGE));
311fd9b2 3142 err |= comedi_check_trigger_arg_is(&cmd->start_arg, tmp);
ebb657ba 3143 break;
03aef4b6 3144 }
c3be5c7f 3145
03aef4b6 3146 if (cmd->scan_begin_src == TRIG_TIMER) {
311fd9b2
IA		 3147 err |= comedi_check_trigger_arg_min(&cmd->scan_begin_arg,
3148 board->ao_speed);
3149 err |= comedi_check_trigger_arg_max(&cmd->scan_begin_arg,
3150 devpriv->clock_ns *
3151 0xffffff);
03aef4b6
DS		 3152 }
3153
311fd9b2
IA		 3154 err |= comedi_check_trigger_arg_is(&cmd->convert_arg, 0);
3155 err |= comedi_check_trigger_arg_is(&cmd->scan_end_arg,
3156 cmd->chanlist_len);
c3be5c7f
HS		 3157
3158 if (cmd->stop_src == TRIG_COUNT)
311fd9b2 3159 err |= comedi_check_trigger_arg_max(&cmd->stop_arg, 0x00ffffff);
c3be5c7f 3160 else /* TRIG_NONE */
311fd9b2 3161 err |= comedi_check_trigger_arg_is(&cmd->stop_arg, 0);
c3be5c7f 3162
03aef4b6
DS		 3163 if (err)
3164 return 3;
3165
3166 /* step 4: fix up any arguments */
3167 if (cmd->scan_begin_src == TRIG_TIMER) {
3168 tmp = cmd->scan_begin_arg;
3169 cmd->scan_begin_arg =
0a85b6f0
MT		 3170 ni_timer_to_ns(dev, ni_ns_to_timer(dev,
3171 cmd->scan_begin_arg,
a207c12f 3172 cmd->flags));
03aef4b6
DS		 3173 if (tmp != cmd->scan_begin_arg)
3174 err++;
3175 }
3176 if (err)
3177 return 4;
3178
03aef4b6
DS		 3179 return 0;
3180}
3181
da91b269 3182static int ni_ao_reset(struct comedi_device *dev, struct comedi_subdevice *s)
03aef4b6 3183{
0e05c552
HS		 3184 struct ni_private *devpriv = dev->private;
3185
03aef4b6
DS		 3186 ni_release_ao_mite_channel(dev);
3187
707502f3 3188 ni_stc_writew(dev, NISTC_RESET_AO_CFG_START, NISTC_RESET_REG);
7bfcc2d4 3189 ni_stc_writew(dev, NISTC_AO_CMD1_DISARM, NISTC_AO_CMD1_REG);
4c9c1d2c 3190 ni_set_bits(dev, NISTC_INTB_ENA_REG, ~0, 0);
63ff3f2c 3191 ni_stc_writew(dev, NISTC_AO_PERSONAL_BC_SRC_SEL, NISTC_AO_PERSONAL_REG);
4a6de832 3192 ni_stc_writew(dev, NISTC_INTB_ACK_AO_ALL, NISTC_INTB_ACK_REG);
63ff3f2c
HS		 3193 ni_stc_writew(dev, NISTC_AO_PERSONAL_BC_SRC_SEL |
3194 NISTC_AO_PERSONAL_UPDATE_PW |
3195 NISTC_AO_PERSONAL_TMRDACWR_PW,
3196 NISTC_AO_PERSONAL_REG);
5bd1c728 3197 ni_stc_writew(dev, 0, NISTC_AO_OUT_CTRL_REG);
2b6285da 3198 ni_stc_writew(dev, 0, NISTC_AO_START_SEL_REG);
03aef4b6 3199 devpriv->ao_cmd1 = 0;
7bfcc2d4 3200 ni_stc_writew(dev, devpriv->ao_cmd1, NISTC_AO_CMD1_REG);
03aef4b6 3201 devpriv->ao_cmd2 = 0;
382b3c4f 3202 ni_stc_writew(dev, devpriv->ao_cmd2, NISTC_AO_CMD2_REG);
03aef4b6 3203 devpriv->ao_mode1 = 0;
4e5ce0a8 3204 ni_stc_writew(dev, devpriv->ao_mode1, NISTC_AO_MODE1_REG);
03aef4b6 3205 devpriv->ao_mode2 = 0;
ec8bf725 3206 ni_stc_writew(dev, devpriv->ao_mode2, NISTC_AO_MODE2_REG);
17733219 3207 if (devpriv->is_m_series)
72bca4f5 3208 devpriv->ao_mode3 = NISTC_AO_MODE3_LAST_GATE_DISABLE;
03aef4b6
DS		 3209 else
3210 devpriv->ao_mode3 = 0;
72bca4f5 3211 ni_stc_writew(dev, devpriv->ao_mode3, NISTC_AO_MODE3_REG);
03aef4b6 3212 devpriv->ao_trigger_select = 0;
00b14b1d 3213 ni_stc_writew(dev, devpriv->ao_trigger_select,
f21844d3 3214 NISTC_AO_TRIG_SEL_REG);
a52b53e4 3215 if (devpriv->is_6xxx) {
03aef4b6
DS		 3216 unsigned immediate_bits = 0;
3217 unsigned i;
f7401979 3218
bc461556 3219 for (i = 0; i < s->n_chan; ++i)
03aef4b6 3220 immediate_bits |= 1 << i;
87b4fe5c
HS		 3221 ni_ao_win_outw(dev, immediate_bits, AO_Immediate_671x);
3222 ni_ao_win_outw(dev, CLEAR_WG, AO_Misc_611x);
03aef4b6 3223 }
707502f3 3224 ni_stc_writew(dev, NISTC_RESET_AO_CFG_END, NISTC_RESET_REG);
03aef4b6
DS		 3225
3226 return 0;
3227}
3228
2696fb57 3229/* digital io */
03aef4b6 3230
0a85b6f0
MT		 3231static int ni_dio_insn_config(struct comedi_device *dev,
3232 struct comedi_subdevice *s,
ddf62f2c
HS		 3233 struct comedi_insn *insn,
3234 unsigned int *data)
03aef4b6 3235{
0e05c552 3236 struct ni_private *devpriv = dev->private;
ddf62f2c 3237 int ret;
0e05c552 3238
ddf62f2c
HS		 3239 ret = comedi_dio_insn_config(dev, s, insn, data, 0);
3240 if (ret)
3241 return ret;
03aef4b6 3242
59a97c3c
HS		 3243 devpriv->dio_control &= ~NISTC_DIO_CTRL_DIR_MASK;
3244 devpriv->dio_control |= NISTC_DIO_CTRL_DIR(s->io_bits);
3245 ni_stc_writew(dev, devpriv->dio_control, NISTC_DIO_CTRL_REG);
03aef4b6 3246
ddf62f2c 3247 return insn->n;
03aef4b6
DS		 3248}
3249
0a85b6f0
MT		 3250static int ni_dio_insn_bits(struct comedi_device *dev,
3251 struct comedi_subdevice *s,
6171667a
HS		 3252 struct comedi_insn *insn,
3253 unsigned int *data)
03aef4b6 3254{
0e05c552
HS		 3255 struct ni_private *devpriv = dev->private;
3256
6171667a 3257 /* Make sure we're not using the serial part of the dio */
05aafeea
HS		 3258 if ((data[0] & (NISTC_DIO_SDIN | NISTC_DIO_SDOUT)) &&
3259 devpriv->serial_interval_ns)
6171667a 3260 return -EBUSY;
03aef4b6 3261
6171667a 3262 if (comedi_dio_update_state(s, data)) {
05aafeea
HS		 3263 devpriv->dio_output &= ~NISTC_DIO_OUT_PARALLEL_MASK;
3264 devpriv->dio_output |= NISTC_DIO_OUT_PARALLEL(s->state);
3265 ni_stc_writew(dev, devpriv->dio_output, NISTC_DIO_OUT_REG);
03aef4b6 3266 }
6171667a 3267
6f764a47 3268 data[1] = ni_stc_readw(dev, NISTC_DIO_IN_REG);
03aef4b6 3269
a2714e3e 3270 return insn->n;
03aef4b6
DS		 3271}
3272
da91b269 3273static int ni_m_series_dio_insn_config(struct comedi_device *dev,
0a85b6f0
MT		 3274 struct comedi_subdevice *s,
3275 struct comedi_insn *insn,
3276 unsigned int *data)
03aef4b6 3277{
ddf62f2c 3278 int ret;
0e05c552 3279
ddf62f2c
HS		 3280 ret = comedi_dio_insn_config(dev, s, insn, data, 0);
3281 if (ret)
3282 return ret;
03aef4b6 3283
975b6d25 3284 ni_writel(dev, s->io_bits, NI_M_DIO_DIR_REG);
03aef4b6 3285
ddf62f2c 3286 return insn->n;
03aef4b6
DS		 3287}
3288
0a85b6f0
MT		 3289static int ni_m_series_dio_insn_bits(struct comedi_device *dev,
3290 struct comedi_subdevice *s,
3291 struct comedi_insn *insn,
3292 unsigned int *data)
03aef4b6 3293{
6171667a 3294 if (comedi_dio_update_state(s, data))
975b6d25 3295 ni_writel(dev, s->state, NI_M_DIO_REG);
6171667a 3296
975b6d25 3297 data[1] = ni_readl(dev, NI_M_DIO_REG);
03aef4b6 3298
a2714e3e 3299 return insn->n;
03aef4b6
DS		 3300}
3301
368c2dcd
HS		 3302static int ni_cdio_check_chanlist(struct comedi_device *dev,
3303 struct comedi_subdevice *s,
3304 struct comedi_cmd *cmd)
3305{
3306 int i;
3307
3308 for (i = 0; i < cmd->chanlist_len; ++i) {
3309 unsigned int chan = CR_CHAN(cmd->chanlist[i]);
3310
3311 if (chan != i)
3312 return -EINVAL;
3313 }
3314
3315 return 0;
3316}
3317
0a85b6f0
MT		 3318static int ni_cdio_cmdtest(struct comedi_device *dev,
3319 struct comedi_subdevice *s, struct comedi_cmd *cmd)
03aef4b6
DS		 3320{
3321 int err = 0;
3322 int tmp;
03aef4b6 3323
27020ffe 3324 /* Step 1 : check if triggers are trivially valid */
03aef4b6 3325
311fd9b2
IA		 3326 err |= comedi_check_trigger_src(&cmd->start_src, TRIG_INT);
3327 err |= comedi_check_trigger_src(&cmd->scan_begin_src, TRIG_EXT);
3328 err |= comedi_check_trigger_src(&cmd->convert_src, TRIG_NOW);
3329 err |= comedi_check_trigger_src(&cmd->scan_end_src, TRIG_COUNT);
3330 err |= comedi_check_trigger_src(&cmd->stop_src, TRIG_NONE);
03aef4b6
DS		 3331
3332 if (err)
3333 return 1;
3334
27020ffe
HS		 3335 /* Step 2a : make sure trigger sources are unique */
3336 /* Step 2b : and mutually compatible */
03aef4b6 3337
c3be5c7f 3338 /* Step 3: check if arguments are trivially valid */
03aef4b6 3339
311fd9b2 3340 err |= comedi_check_trigger_arg_is(&cmd->start_arg, 0);
03aef4b6 3341
c3be5c7f 3342 tmp = cmd->scan_begin_arg;
258f0047 3343 tmp &= CR_PACK_FLAGS(NI_M_CDO_MODE_SAMPLE_SRC_MASK, 0, 0, CR_INVERT);
c3be5c7f
HS		 3344 if (tmp != cmd->scan_begin_arg)
3345 err |= -EINVAL;
3346
311fd9b2
IA		 3347 err |= comedi_check_trigger_arg_is(&cmd->convert_arg, 0);
3348 err |= comedi_check_trigger_arg_is(&cmd->scan_end_arg,
3349 cmd->chanlist_len);
3350 err |= comedi_check_trigger_arg_is(&cmd->stop_arg, 0);
03aef4b6
DS		 3351
3352 if (err)
3353 return 3;
3354
b32381c5 3355 /* Step 4: fix up any arguments */
03aef4b6 3356
368c2dcd 3357 /* Step 5: check channel list if it exists */
b32381c5 3358
368c2dcd
HS		 3359 if (cmd->chanlist && cmd->chanlist_len > 0)
3360 err |= ni_cdio_check_chanlist(dev, s, cmd);
03aef4b6
DS		 3361
3362 if (err)
3363 return 5;
3364
3365 return 0;
3366}
3367
ebb657ba
HS		 3368static int ni_cdo_inttrig(struct comedi_device *dev,
3369 struct comedi_subdevice *s,
3370 unsigned int trig_num)
03aef4b6 3371{
ebb657ba 3372 struct comedi_cmd *cmd = &s->async->cmd;
9c340ac9 3373 const unsigned timeout = 1000;
03aef4b6
DS		 3374 int retval = 0;
3375 unsigned i;
9c340ac9 3376#ifdef PCIDMA
5a92cac5 3377 struct ni_private *devpriv = dev->private;
9c340ac9
HS		 3378 unsigned long flags;
3379#endif
03aef4b6 3380
ebb657ba
HS		 3381 if (trig_num != cmd->start_arg)
3382 return -EINVAL;
3383
03aef4b6
DS		 3384 s->async->inttrig = NULL;
3385
3386 /* read alloc the entire buffer */
d13be55a 3387 comedi_buf_read_alloc(s, s->async->prealloc_bufsz);
03aef4b6
DS		 3388
3389#ifdef PCIDMA
5f74ea14 3390 spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
03aef4b6
DS		 3391 if (devpriv->cdo_mite_chan) {
3392 mite_prep_dma(devpriv->cdo_mite_chan, 32, 32);
3393 mite_dma_arm(devpriv->cdo_mite_chan);
3394 } else {
5ac1d82b 3395 dev_err(dev->class_dev, "BUG: no cdo mite channel?\n");
03aef4b6
DS		 3396 retval = -EIO;
3397 }
5f74ea14 3398 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
03aef4b6
DS		 3399 if (retval < 0)
3400 return retval;
3401#endif
975b6d25
HS		 3402 /*
3403 * XXX not sure what interrupt C group does
3404 * wait for dma to fill output fifo
60f078f9 3405 * ni_writeb(dev, NI_M_INTC_ENA, NI_M_INTC_ENA_REG);
975b6d25 3406 */
03aef4b6 3407 for (i = 0; i < timeout; ++i) {
d53be924
HS		 3408 if (ni_readl(dev, NI_M_CDIO_STATUS_REG) &
3409 NI_M_CDIO_STATUS_CDO_FIFO_FULL)
03aef4b6 3410 break;
5f74ea14 3411 udelay(10);
03aef4b6
DS		 3412 }
3413 if (i == timeout) {
5ac1d82b 3414 dev_err(dev->class_dev, "dma failed to fill cdo fifo!\n");
fed37a1e 3415 s->cancel(dev, s);
03aef4b6
DS		 3416 return -EIO;
3417 }
3c3eb8ea
HS		 3418 ni_writel(dev, NI_M_CDO_CMD_ARM |
3419 NI_M_CDO_CMD_ERR_INT_ENA_SET |
3420 NI_M_CDO_CMD_F_E_INT_ENA_SET,
975b6d25 3421 NI_M_CDIO_CMD_REG);
03aef4b6
DS		 3422 return retval;
3423}
3424
0792928f
HS		 3425static int ni_cdio_cmd(struct comedi_device *dev, struct comedi_subdevice *s)
3426{
0792928f 3427 const struct comedi_cmd *cmd = &s->async->cmd;
258f0047 3428 unsigned cdo_mode_bits;
0792928f
HS		 3429 int retval;
3430
3c3eb8ea 3431 ni_writel(dev, NI_M_CDO_CMD_RESET, NI_M_CDIO_CMD_REG);
258f0047
HS		 3432 cdo_mode_bits = NI_M_CDO_MODE_FIFO_MODE |
3433 NI_M_CDO_MODE_HALT_ON_ERROR |
3434 NI_M_CDO_MODE_SAMPLE_SRC(CR_CHAN(cmd->scan_begin_arg));
0792928f 3435 if (cmd->scan_begin_arg & CR_INVERT)
258f0047 3436 cdo_mode_bits |= NI_M_CDO_MODE_POLARITY;
975b6d25 3437 ni_writel(dev, cdo_mode_bits, NI_M_CDO_MODE_REG);
0792928f 3438 if (s->io_bits) {
975b6d25 3439 ni_writel(dev, s->state, NI_M_CDO_FIFO_DATA_REG);
3c3eb8ea 3440 ni_writel(dev, NI_M_CDO_CMD_SW_UPDATE, NI_M_CDIO_CMD_REG);
975b6d25 3441 ni_writel(dev, s->io_bits, NI_M_CDO_MASK_ENA_REG);
0792928f 3442 } else {
5ac1d82b
HS		 3443 dev_err(dev->class_dev,
3444 "attempted to run digital output command with no lines configured as outputs\n");
0792928f
HS		 3445 return -EIO;
3446 }
3447 retval = ni_request_cdo_mite_channel(dev);
3448 if (retval < 0)
3449 return retval;
3450
3451 s->async->inttrig = ni_cdo_inttrig;
3452
3453 return 0;
3454}
3455
da91b269 3456static int ni_cdio_cancel(struct comedi_device *dev, struct comedi_subdevice *s)
03aef4b6 3457{
3c3eb8ea
HS		 3458 ni_writel(dev, NI_M_CDO_CMD_DISARM |
3459 NI_M_CDO_CMD_ERR_INT_ENA_CLR |
3460 NI_M_CDO_CMD_F_E_INT_ENA_CLR |
3461 NI_M_CDO_CMD_F_REQ_INT_ENA_CLR,
975b6d25
HS		 3462 NI_M_CDIO_CMD_REG);
3463 /*
3464 * XXX not sure what interrupt C group does
3465 * ni_writeb(dev, 0, NI_M_INTC_ENA_REG);
3466 */
3467 ni_writel(dev, 0, NI_M_CDO_MASK_ENA_REG);
03aef4b6
DS		 3468 ni_release_cdo_mite_channel(dev);
3469 return 0;
3470}
3471
da91b269 3472static void handle_cdio_interrupt(struct comedi_device *dev)
03aef4b6 3473{
9c340ac9 3474 struct ni_private *devpriv = dev->private;
03aef4b6 3475 unsigned cdio_status;
f9cd92eb 3476 struct comedi_subdevice *s = &dev->subdevices[NI_DIO_SUBDEV];
03aef4b6
DS		 3477#ifdef PCIDMA
3478 unsigned long flags;
3479#endif
3480
17733219 3481 if (!devpriv->is_m_series)
03aef4b6 3482 return;
03aef4b6 3483#ifdef PCIDMA
5f74ea14 3484 spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
03aef4b6
DS		 3485 if (devpriv->cdo_mite_chan) {
3486 unsigned cdo_mite_status =
0a85b6f0 3487 mite_get_status(devpriv->cdo_mite_chan);
03aef4b6
DS		 3488 if (cdo_mite_status & CHSR_LINKC) {
3489 writel(CHOR_CLRLC,
0a85b6f0
MT		 3490 devpriv->mite->mite_io_addr +
3491 MITE_CHOR(devpriv->cdo_mite_chan->channel));
03aef4b6 3492 }
1e575a9c 3493 mite_sync_output_dma(devpriv->cdo_mite_chan, s);
03aef4b6 3494 }
5f74ea14 3495 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
03aef4b6
DS		 3496#endif
3497
975b6d25 3498 cdio_status = ni_readl(dev, NI_M_CDIO_STATUS_REG);
d53be924 3499 if (cdio_status & NI_M_CDIO_STATUS_CDO_ERROR) {
9c340ac9 3500 /* XXX just guessing this is needed and does something useful */
3c3eb8ea 3501 ni_writel(dev, NI_M_CDO_CMD_ERR_INT_CONFIRM,
975b6d25 3502 NI_M_CDIO_CMD_REG);
03aef4b6
DS		 3503 s->async->events |= COMEDI_CB_OVERFLOW;
3504 }
d53be924 3505 if (cdio_status & NI_M_CDIO_STATUS_CDO_FIFO_EMPTY) {
3c3eb8ea 3506 ni_writel(dev, NI_M_CDO_CMD_F_E_INT_ENA_CLR,
975b6d25 3507 NI_M_CDIO_CMD_REG);
b9ede315 3508 /* s->async->events |= COMEDI_CB_EOA; */
03aef4b6 3509 }
b9a69a19 3510 comedi_handle_events(dev, s);
03aef4b6
DS		 3511}
3512
0a85b6f0
MT		 3513static int ni_serial_hw_readwrite8(struct comedi_device *dev,
3514 struct comedi_subdevice *s,
3515 unsigned char data_out,
3516 unsigned char *data_in)
03aef4b6 3517{
0e05c552 3518 struct ni_private *devpriv = dev->private;
03aef4b6
DS		 3519 unsigned int status1;
3520 int err = 0, count = 20;
3521
05aafeea
HS		 3522 devpriv->dio_output &= ~NISTC_DIO_OUT_SERIAL_MASK;
3523 devpriv->dio_output |= NISTC_DIO_OUT_SERIAL(data_out);
3524 ni_stc_writew(dev, devpriv->dio_output, NISTC_DIO_OUT_REG);
03aef4b6 3525
d3fed081
HS		 3526 status1 = ni_stc_readw(dev, NISTC_STATUS1_REG);
3527 if (status1 & NISTC_STATUS1_SERIO_IN_PROG) {
03aef4b6
DS		 3528 err = -EBUSY;
3529 goto Error;
3530 }
3531
59a97c3c
HS		 3532 devpriv->dio_control |= NISTC_DIO_CTRL_HW_SER_START;
3533 ni_stc_writew(dev, devpriv->dio_control, NISTC_DIO_CTRL_REG);
3534 devpriv->dio_control &= ~NISTC_DIO_CTRL_HW_SER_START;
03aef4b6
DS		 3535
3536 /* Wait until STC says we're done, but don't loop infinitely. */
d3fed081
HS		 3537 while ((status1 = ni_stc_readw(dev, NISTC_STATUS1_REG)) &
3538 NISTC_STATUS1_SERIO_IN_PROG) {
03aef4b6 3539 /* Delay one bit per loop */
5f74ea14 3540 udelay((devpriv->serial_interval_ns + 999) / 1000);
03aef4b6 3541 if (--count < 0) {
89c4695e 3542 dev_err(dev->class_dev,
cd25503f 3543 "SPI serial I/O didn't finish in time!\n");
03aef4b6
DS		 3544 err = -ETIME;
3545 goto Error;
3546 }
3547 }
3548
d3fed081
HS		 3549 /*
3550 * Delay for last bit. This delay is absolutely necessary, because
3551 * NISTC_STATUS1_SERIO_IN_PROG goes high one bit too early.
3552 */
5f74ea14 3553 udelay((devpriv->serial_interval_ns + 999) / 1000);
03aef4b6 3554
c6be1548 3555 if (data_in)
8fbb0154 3556 *data_in = ni_stc_readw(dev, NISTC_DIO_SERIAL_IN_REG);
03aef4b6 3557
0a85b6f0 3558Error:
59a97c3c 3559 ni_stc_writew(dev, devpriv->dio_control, NISTC_DIO_CTRL_REG);
03aef4b6
DS		 3560
3561 return err;
3562}
3563
0a85b6f0
MT		 3564static int ni_serial_sw_readwrite8(struct comedi_device *dev,
3565 struct comedi_subdevice *s,
3566 unsigned char data_out,
3567 unsigned char *data_in)
03aef4b6 3568{
0e05c552 3569 struct ni_private *devpriv = dev->private;
03aef4b6
DS		 3570 unsigned char mask, input = 0;
3571
03aef4b6 3572 /* Wait for one bit before transfer */
5f74ea14 3573 udelay((devpriv->serial_interval_ns + 999) / 1000);
03aef4b6
DS		 3574
3575 for (mask = 0x80; mask; mask >>= 1) {
3576 /* Output current bit; note that we cannot touch s->state
3577 because it is a per-subdevice field, and serial is
3578 a separate subdevice from DIO. */
05aafeea 3579 devpriv->dio_output &= ~NISTC_DIO_SDOUT;
bc461556 3580 if (data_out & mask)
05aafeea
HS		 3581 devpriv->dio_output |= NISTC_DIO_SDOUT;
3582 ni_stc_writew(dev, devpriv->dio_output, NISTC_DIO_OUT_REG);
03aef4b6
DS		 3583
3584 /* Assert SDCLK (active low, inverted), wait for half of
3585 the delay, deassert SDCLK, and wait for the other half. */
59a97c3c
HS		 3586 devpriv->dio_control |= NISTC_DIO_SDCLK;
3587 ni_stc_writew(dev, devpriv->dio_control, NISTC_DIO_CTRL_REG);
03aef4b6 3588
5f74ea14 3589 udelay((devpriv->serial_interval_ns + 999) / 2000);
03aef4b6 3590
59a97c3c
HS		 3591 devpriv->dio_control &= ~NISTC_DIO_SDCLK;
3592 ni_stc_writew(dev, devpriv->dio_control, NISTC_DIO_CTRL_REG);
03aef4b6 3593
5f74ea14 3594 udelay((devpriv->serial_interval_ns + 999) / 2000);
03aef4b6
DS		 3595
3596 /* Input current bit */
6f764a47 3597 if (ni_stc_readw(dev, NISTC_DIO_IN_REG) & NISTC_DIO_SDIN)
03aef4b6 3598 input |= mask;
03aef4b6 3599 }
9d6a0f6a 3600
03aef4b6
DS		 3601 if (data_in)
3602 *data_in = input;
3603
3604 return 0;
3605}
3606
189e1736
HS		 3607static int ni_serial_insn_config(struct comedi_device *dev,
3608 struct comedi_subdevice *s,
3609 struct comedi_insn *insn,
3610 unsigned int *data)
3611{
3612 struct ni_private *devpriv = dev->private;
a47fc02b 3613 unsigned clk_fout = devpriv->clock_and_fout;
189e1736
HS		 3614 int err = insn->n;
3615 unsigned char byte_out, byte_in = 0;
3616
3617 if (insn->n != 2)
3618 return -EINVAL;
3619
3620 switch (data[0]) {
3621 case INSN_CONFIG_SERIAL_CLOCK:
3622 devpriv->serial_hw_mode = 1;
59a97c3c 3623 devpriv->dio_control |= NISTC_DIO_CTRL_HW_SER_ENA;
189e1736
HS		 3624
3625 if (data[1] == SERIAL_DISABLED) {
3626 devpriv->serial_hw_mode = 0;
59a97c3c
HS		 3627 devpriv->dio_control &= ~(NISTC_DIO_CTRL_HW_SER_ENA |
3628 NISTC_DIO_SDCLK);
189e1736
HS		 3629 data[1] = SERIAL_DISABLED;
3630 devpriv->serial_interval_ns = data[1];
3631 } else if (data[1] <= SERIAL_600NS) {
3632 /* Warning: this clock speed is too fast to reliably
3633 control SCXI. */
59a97c3c 3634 devpriv->dio_control &= ~NISTC_DIO_CTRL_HW_SER_TIMEBASE;
a47fc02b
HS		 3635 clk_fout |= NISTC_CLK_FOUT_SLOW_TIMEBASE;
3636 clk_fout &= ~NISTC_CLK_FOUT_DIO_SER_OUT_DIV2;
189e1736
HS		 3637 data[1] = SERIAL_600NS;
3638 devpriv->serial_interval_ns = data[1];
3639 } else if (data[1] <= SERIAL_1_2US) {
59a97c3c 3640 devpriv->dio_control &= ~NISTC_DIO_CTRL_HW_SER_TIMEBASE;
a47fc02b
HS		 3641 clk_fout |= NISTC_CLK_FOUT_SLOW_TIMEBASE |
3642 NISTC_CLK_FOUT_DIO_SER_OUT_DIV2;
189e1736
HS		 3643 data[1] = SERIAL_1_2US;
3644 devpriv->serial_interval_ns = data[1];
3645 } else if (data[1] <= SERIAL_10US) {
59a97c3c 3646 devpriv->dio_control |= NISTC_DIO_CTRL_HW_SER_TIMEBASE;
a47fc02b
HS		 3647 clk_fout |= NISTC_CLK_FOUT_SLOW_TIMEBASE |
3648 NISTC_CLK_FOUT_DIO_SER_OUT_DIV2;
3649 /* Note: NISTC_CLK_FOUT_DIO_SER_OUT_DIV2 only affects
189e1736
HS		 3650 600ns/1.2us. If you turn divide_by_2 off with the
3651 slow clock, you will still get 10us, except then
3652 all your delays are wrong. */
3653 data[1] = SERIAL_10US;
3654 devpriv->serial_interval_ns = data[1];
3655 } else {
59a97c3c
HS		 3656 devpriv->dio_control &= ~(NISTC_DIO_CTRL_HW_SER_ENA |
3657 NISTC_DIO_SDCLK);
189e1736
HS		 3658 devpriv->serial_hw_mode = 0;
3659 data[1] = (data[1] / 1000) * 1000;
3660 devpriv->serial_interval_ns = data[1];
3661 }
a47fc02b 3662 devpriv->clock_and_fout = clk_fout;
189e1736 3663
59a97c3c 3664 ni_stc_writew(dev, devpriv->dio_control, NISTC_DIO_CTRL_REG);
a47fc02b 3665 ni_stc_writew(dev, devpriv->clock_and_fout, NISTC_CLK_FOUT_REG);
189e1736
HS		 3666 return 1;
3667
189e1736
HS		 3668 case INSN_CONFIG_BIDIRECTIONAL_DATA:
3669
3670 if (devpriv->serial_interval_ns == 0)
3671 return -EINVAL;
3672
3673 byte_out = data[1] & 0xFF;
3674
3675 if (devpriv->serial_hw_mode) {
3676 err = ni_serial_hw_readwrite8(dev, s, byte_out,
3677 &byte_in);
3678 } else if (devpriv->serial_interval_ns > 0) {
3679 err = ni_serial_sw_readwrite8(dev, s, byte_out,
3680 &byte_in);
3681 } else {
cd25503f 3682 dev_err(dev->class_dev, "serial disabled!\n");
189e1736
HS		 3683 return -EINVAL;
3684 }
3685 if (err < 0)
3686 return err;
3687 data[1] = byte_in & 0xFF;
3688 return insn->n;
3689
3690 break;
3691 default:
3692 return -EINVAL;
3693 }
189e1736
HS		 3694}
3695
da91b269 3696static void init_ao_67xx(struct comedi_device *dev, struct comedi_subdevice *s)
03aef4b6
DS		 3697{
3698 int i;
3699
0a85b6f0 3700 for (i = 0; i < s->n_chan; i++) {
b497b8da 3701 ni_ao_win_outw(dev, NI_E_AO_DACSEL(i) | 0x0,
0a85b6f0 3702 AO_Configuration_2_67xx);
03aef4b6 3703 }
87b4fe5c 3704 ni_ao_win_outw(dev, 0x0, AO_Later_Single_Point_Updates);
03aef4b6
DS		 3705}
3706
cfdb3429 3707static const struct mio_regmap ni_gpct_to_stc_regmap[] = {
38aba4c9
HS		 3708 [NITIO_G0_AUTO_INC] = { NISTC_G0_AUTOINC_REG, 2 },
3709 [NITIO_G1_AUTO_INC] = { NISTC_G1_AUTOINC_REG, 2 },
5fa2fa44
HS		 3710 [NITIO_G0_CMD] = { NISTC_G0_CMD_REG, 2 },
3711 [NITIO_G1_CMD] = { NISTC_G1_CMD_REG, 2 },
27650d99
HS		 3712 [NITIO_G0_HW_SAVE] = { NISTC_G0_HW_SAVE_REG, 4 },
3713 [NITIO_G1_HW_SAVE] = { NISTC_G1_HW_SAVE_REG, 4 },
d9c4115f
HS		 3714 [NITIO_G0_SW_SAVE] = { NISTC_G0_SAVE_REG, 4 },
3715 [NITIO_G1_SW_SAVE] = { NISTC_G1_SAVE_REG, 4 },
aff27008
HS		 3716 [NITIO_G0_MODE] = { NISTC_G0_MODE_REG, 2 },
3717 [NITIO_G1_MODE] = { NISTC_G1_MODE_REG, 2 },
3718 [NITIO_G0_LOADA] = { NISTC_G0_LOADA_REG, 4 },
3719 [NITIO_G1_LOADA] = { NISTC_G1_LOADA_REG, 4 },
3720 [NITIO_G0_LOADB] = { NISTC_G0_LOADB_REG, 4 },
3721 [NITIO_G1_LOADB] = { NISTC_G1_LOADB_REG, 4 },
3722 [NITIO_G0_INPUT_SEL] = { NISTC_G0_INPUT_SEL_REG, 2 },
3723 [NITIO_G1_INPUT_SEL] = { NISTC_G1_INPUT_SEL_REG, 2 },
0a9752d8
HS		 3724 [NITIO_G0_CNT_MODE] = { 0x1b0, 2 }, /* M-Series only */
3725 [NITIO_G1_CNT_MODE] = { 0x1b2, 2 }, /* M-Series only */
3726 [NITIO_G0_GATE2] = { 0x1b4, 2 }, /* M-Series only */
3727 [NITIO_G1_GATE2] = { 0x1b6, 2 }, /* M-Series only */
7f0e1bac 3728 [NITIO_G01_STATUS] = { NISTC_G01_STATUS_REG, 2 },
707502f3 3729 [NITIO_G01_RESET] = { NISTC_RESET_REG, 2 },
d3fed081 3730 [NITIO_G01_STATUS1] = { NISTC_STATUS1_REG, 2 },
bab382ef 3731 [NITIO_G01_STATUS2] = { NISTC_STATUS2_REG, 2 },
0a9752d8
HS		 3732 [NITIO_G0_DMA_CFG] = { 0x1b8, 2 }, /* M-Series only */
3733 [NITIO_G1_DMA_CFG] = { 0x1ba, 2 }, /* M-Series only */
3734 [NITIO_G0_DMA_STATUS] = { 0x1b8, 2 }, /* M-Series only */
3735 [NITIO_G1_DMA_STATUS] = { 0x1ba, 2 }, /* M-Series only */
3736 [NITIO_G0_ABZ] = { 0x1c0, 2 }, /* M-Series only */
3737 [NITIO_G1_ABZ] = { 0x1c2, 2 }, /* M-Series only */
480456d3 3738 [NITIO_G0_INT_ACK] = { NISTC_INTA_ACK_REG, 2 },
4a6de832 3739 [NITIO_G1_INT_ACK] = { NISTC_INTB_ACK_REG, 2 },
7b14fffd 3740 [NITIO_G0_STATUS] = { NISTC_AI_STATUS1_REG, 2 },
d123ee3c 3741 [NITIO_G1_STATUS] = { NISTC_AO_STATUS1_REG, 2 },
5cca26aa 3742 [NITIO_G0_INT_ENA] = { NISTC_INTA_ENA_REG, 2 },
4c9c1d2c 3743 [NITIO_G1_INT_ENA] = { NISTC_INTB_ENA_REG, 2 },
cfdb3429
HS		 3744};
3745
3746static unsigned int ni_gpct_to_stc_register(struct comedi_device *dev,
3747 enum ni_gpct_register reg)
03aef4b6 3748{
cfdb3429 3749 const struct mio_regmap *regmap;
f7401979 3750
cfdb3429
HS		 3751 if (reg < ARRAY_SIZE(ni_gpct_to_stc_regmap)) {
3752 regmap = &ni_gpct_to_stc_regmap[reg];
3753 } else {
3754 dev_warn(dev->class_dev,"%s: unhandled register 0x%x\n",
3755 __func__, reg);
03aef4b6 3756 return 0;
03aef4b6 3757 }
cfdb3429
HS		 3758
3759 return regmap->mio_reg;
03aef4b6
DS		 3760}
3761
3762static void ni_gpct_write_register(struct ni_gpct *counter, unsigned bits,
0a85b6f0 3763 enum ni_gpct_register reg)
03aef4b6 3764{
71b5f4f1 3765 struct comedi_device *dev = counter->counter_dev->dev;
cfdb3429 3766 unsigned int stc_register = ni_gpct_to_stc_register(dev, reg);
03aef4b6 3767 static const unsigned gpct_interrupt_a_enable_mask =
5cca26aa 3768 NISTC_INTA_ENA_G0_GATE | NISTC_INTA_ENA_G0_TC;
03aef4b6 3769 static const unsigned gpct_interrupt_b_enable_mask =
4c9c1d2c 3770 NISTC_INTB_ENA_G1_GATE | NISTC_INTB_ENA_G1_TC;
03aef4b6 3771
cfdb3429
HS		 3772 if (stc_register == 0)
3773 return;
3774
03aef4b6 3775 switch (reg) {
cfdb3429 3776 /* m-series only registers */
12375292 3777 case NITIO_G0_CNT_MODE:
12375292 3778 case NITIO_G1_CNT_MODE:
12375292 3779 case NITIO_G0_GATE2:
12375292 3780 case NITIO_G1_GATE2:
12375292 3781 case NITIO_G0_DMA_CFG:
12375292 3782 case NITIO_G1_DMA_CFG:
12375292 3783 case NITIO_G0_ABZ:
12375292 3784 case NITIO_G1_ABZ:
cfdb3429 3785 ni_writew(dev, bits, stc_register);
03aef4b6
DS		 3786 break;
3787
3788 /* 32 bit registers */
12375292
HS		 3789 case NITIO_G0_LOADA:
3790 case NITIO_G1_LOADA:
3791 case NITIO_G0_LOADB:
3792 case NITIO_G1_LOADB:
00b14b1d 3793 ni_stc_writel(dev, bits, stc_register);
03aef4b6
DS		 3794 break;
3795
3796 /* 16 bit registers */
12375292 3797 case NITIO_G0_INT_ENA:
03aef4b6 3798 BUG_ON(bits & ~gpct_interrupt_a_enable_mask);
cfdb3429 3799 ni_set_bitfield(dev, stc_register,
0a85b6f0 3800 gpct_interrupt_a_enable_mask, bits);
03aef4b6 3801 break;
12375292 3802 case NITIO_G1_INT_ENA:
03aef4b6 3803 BUG_ON(bits & ~gpct_interrupt_b_enable_mask);
cfdb3429 3804 ni_set_bitfield(dev, stc_register,
0a85b6f0 3805 gpct_interrupt_b_enable_mask, bits);
03aef4b6 3806 break;
12375292 3807 case NITIO_G01_RESET:
707502f3 3808 BUG_ON(bits & ~(NISTC_RESET_G0 | NISTC_RESET_G1));
03aef4b6
DS		 3809 /* fall-through */
3810 default:
00b14b1d 3811 ni_stc_writew(dev, bits, stc_register);
03aef4b6
DS		 3812 }
3813}
3814
3815static unsigned ni_gpct_read_register(struct ni_gpct *counter,
0a85b6f0 3816 enum ni_gpct_register reg)
03aef4b6 3817{
71b5f4f1 3818 struct comedi_device *dev = counter->counter_dev->dev;
cfdb3429
HS		 3819 unsigned int stc_register = ni_gpct_to_stc_register(dev, reg);
3820
3821 if (stc_register == 0)
3822 return 0;
0e05c552 3823
03aef4b6
DS		 3824 switch (reg) {
3825 /* m-series only registers */
12375292 3826 case NITIO_G0_DMA_STATUS:
12375292 3827 case NITIO_G1_DMA_STATUS:
cfdb3429 3828 return ni_readw(dev, stc_register);
03aef4b6
DS		 3829
3830 /* 32 bit registers */
12375292
HS		 3831 case NITIO_G0_HW_SAVE:
3832 case NITIO_G1_HW_SAVE:
3833 case NITIO_G0_SW_SAVE:
3834 case NITIO_G1_SW_SAVE:
00b14b1d 3835 return ni_stc_readl(dev, stc_register);
03aef4b6
DS		 3836
3837 /* 16 bit registers */
3838 default:
00b14b1d 3839 return ni_stc_readw(dev, stc_register);
03aef4b6 3840 }
03aef4b6
DS		 3841}
3842
da91b269 3843static int ni_freq_out_insn_read(struct comedi_device *dev,
0a85b6f0 3844 struct comedi_subdevice *s,
d9c4261f
HS		 3845 struct comedi_insn *insn,
3846 unsigned int *data)
03aef4b6 3847{
0e05c552 3848 struct ni_private *devpriv = dev->private;
a47fc02b 3849 unsigned int val = NISTC_CLK_FOUT_TO_DIVIDER(devpriv->clock_and_fout);
d9c4261f 3850 int i;
0e05c552 3851
d9c4261f
HS		 3852 for (i = 0; i < insn->n; i++)
3853 data[i] = val;
3854
3855 return insn->n;
03aef4b6
DS		 3856}
3857
da91b269 3858static int ni_freq_out_insn_write(struct comedi_device *dev,
0a85b6f0 3859 struct comedi_subdevice *s,
00a92c03
HS		 3860 struct comedi_insn *insn,
3861 unsigned int *data)
03aef4b6 3862{
0e05c552
HS		 3863 struct ni_private *devpriv = dev->private;
3864
00a92c03 3865 if (insn->n) {
a47fc02b
HS		 3866 unsigned int val = data[insn->n - 1];
3867
3868 devpriv->clock_and_fout &= ~NISTC_CLK_FOUT_ENA;
3869 ni_stc_writew(dev, devpriv->clock_and_fout, NISTC_CLK_FOUT_REG);
3870 devpriv->clock_and_fout &= ~NISTC_CLK_FOUT_DIVIDER_MASK;
00a92c03
HS		 3871
3872 /* use the last data value to set the fout divider */
a47fc02b 3873 devpriv->clock_and_fout |= NISTC_CLK_FOUT_DIVIDER(val);
00a92c03 3874
a47fc02b
HS		 3875 devpriv->clock_and_fout |= NISTC_CLK_FOUT_ENA;
3876 ni_stc_writew(dev, devpriv->clock_and_fout, NISTC_CLK_FOUT_REG);
00a92c03 3877 }
03aef4b6
DS		 3878 return insn->n;
3879}
3880
0a85b6f0
MT		 3881static int ni_freq_out_insn_config(struct comedi_device *dev,
3882 struct comedi_subdevice *s,
e63dabd0
HS		 3883 struct comedi_insn *insn,
3884 unsigned int *data)
03aef4b6 3885{
e63dabd0
HS		 3886 struct ni_private *devpriv = dev->private;
3887
03aef4b6
DS		 3888 switch (data[0]) {
3889 case INSN_CONFIG_SET_CLOCK_SRC:
e63dabd0
HS		 3890 switch (data[1]) {
3891 case NI_FREQ_OUT_TIMEBASE_1_DIV_2_CLOCK_SRC:
a47fc02b 3892 devpriv->clock_and_fout &= ~NISTC_CLK_FOUT_TIMEBASE_SEL;
e63dabd0
HS		 3893 break;
3894 case NI_FREQ_OUT_TIMEBASE_2_CLOCK_SRC:
a47fc02b 3895 devpriv->clock_and_fout |= NISTC_CLK_FOUT_TIMEBASE_SEL;
e63dabd0
HS		 3896 break;
3897 default:
3898 return -EINVAL;
3899 }
a47fc02b 3900 ni_stc_writew(dev, devpriv->clock_and_fout, NISTC_CLK_FOUT_REG);
03aef4b6
DS		 3901 break;
3902 case INSN_CONFIG_GET_CLOCK_SRC:
a47fc02b 3903 if (devpriv->clock_and_fout & NISTC_CLK_FOUT_TIMEBASE_SEL) {
e63dabd0
HS		 3904 data[1] = NI_FREQ_OUT_TIMEBASE_2_CLOCK_SRC;
3905 data[2] = TIMEBASE_2_NS;
3906 } else {
3907 data[1] = NI_FREQ_OUT_TIMEBASE_1_DIV_2_CLOCK_SRC;
3908 data[2] = TIMEBASE_1_NS * 2;
3909 }
03aef4b6 3910 break;
e63dabd0
HS		 3911 default:
3912 return -EINVAL;
03aef4b6 3913 }
e63dabd0 3914 return insn->n;
03aef4b6
DS		 3915}
3916
67393c4f
HS		 3917static int ni_8255_callback(struct comedi_device *dev,
3918 int dir, int port, int data, unsigned long iobase)
f5985867 3919{
f5985867 3920 if (dir) {
67393c4f 3921 ni_writeb(dev, data, iobase + 2 * port);
f5985867 3922 return 0;
f5985867 3923 }
0953ee4a 3924
67393c4f 3925 return ni_readb(dev, iobase + 2 * port);
f5985867
HS		 3926}
3927
1e49c5da
HS		 3928static int ni_get_pwm_config(struct comedi_device *dev, unsigned int *data)
3929{
3930 struct ni_private *devpriv = dev->private;
3931
3932 data[1] = devpriv->pwm_up_count * devpriv->clock_ns;
3933 data[2] = devpriv->pwm_down_count * devpriv->clock_ns;
3934 return 3;
3935}
3936
3937static int ni_m_series_pwm_config(struct comedi_device *dev,
3938 struct comedi_subdevice *s,
3939 struct comedi_insn *insn,
3940 unsigned int *data)
3941{
3942 struct ni_private *devpriv = dev->private;
3943 unsigned up_count, down_count;
3944
3945 switch (data[0]) {
3946 case INSN_CONFIG_PWM_OUTPUT:
3947 switch (data[1]) {
3280c2d2 3948 case CMDF_ROUND_NEAREST:
1e49c5da
HS		 3949 up_count =
3950 (data[2] +
3951 devpriv->clock_ns / 2) / devpriv->clock_ns;
3952 break;
3280c2d2 3953 case CMDF_ROUND_DOWN:
1e49c5da
HS		 3954 up_count = data[2] / devpriv->clock_ns;
3955 break;
3280c2d2 3956 case CMDF_ROUND_UP:
1e49c5da
HS		 3957 up_count =
3958 (data[2] + devpriv->clock_ns -
3959 1) / devpriv->clock_ns;
3960 break;
3961 default:
3962 return -EINVAL;
1e49c5da
HS		 3963 }
3964 switch (data[3]) {
3280c2d2 3965 case CMDF_ROUND_NEAREST:
1e49c5da
HS		 3966 down_count =
3967 (data[4] +
3968 devpriv->clock_ns / 2) / devpriv->clock_ns;
3969 break;
3280c2d2 3970 case CMDF_ROUND_DOWN:
1e49c5da
HS		 3971 down_count = data[4] / devpriv->clock_ns;
3972 break;
3280c2d2 3973 case CMDF_ROUND_UP:
1e49c5da
HS		 3974 down_count =
3975 (data[4] + devpriv->clock_ns -
3976 1) / devpriv->clock_ns;
3977 break;
3978 default:
3979 return -EINVAL;
1e49c5da
HS		 3980 }
3981 if (up_count * devpriv->clock_ns != data[2] ||
3982 down_count * devpriv->clock_ns != data[4]) {
3983 data[2] = up_count * devpriv->clock_ns;
3984 data[4] = down_count * devpriv->clock_ns;
3985 return -EAGAIN;
3986 }
cc679f97
HS		 3987 ni_writel(dev, NI_M_CAL_PWM_HIGH_TIME(up_count) |
3988 NI_M_CAL_PWM_LOW_TIME(down_count),
975b6d25 3989 NI_M_CAL_PWM_REG);
1e49c5da
HS		 3990 devpriv->pwm_up_count = up_count;
3991 devpriv->pwm_down_count = down_count;
3992 return 5;
1e49c5da
HS		 3993 case INSN_CONFIG_GET_PWM_OUTPUT:
3994 return ni_get_pwm_config(dev, data);
1e49c5da
HS		 3995 default:
3996 return -EINVAL;
1e49c5da
HS		 3997 }
3998 return 0;
3999}
4000
4001static int ni_6143_pwm_config(struct comedi_device *dev,
4002 struct comedi_subdevice *s,
4003 struct comedi_insn *insn,
4004 unsigned int *data)
4005{
4006 struct ni_private *devpriv = dev->private;
4007 unsigned up_count, down_count;
4008
4009 switch (data[0]) {
4010 case INSN_CONFIG_PWM_OUTPUT:
4011 switch (data[1]) {
3280c2d2 4012 case CMDF_ROUND_NEAREST:
1e49c5da
HS		 4013 up_count =
4014 (data[2] +
4015 devpriv->clock_ns / 2) / devpriv->clock_ns;
4016 break;
3280c2d2 4017 case CMDF_ROUND_DOWN:
1e49c5da
HS		 4018 up_count = data[2] / devpriv->clock_ns;
4019 break;
3280c2d2 4020 case CMDF_ROUND_UP:
1e49c5da
HS		 4021 up_count =
4022 (data[2] + devpriv->clock_ns -
4023 1) / devpriv->clock_ns;
4024 break;
4025 default:
4026 return -EINVAL;
1e49c5da
HS		 4027 }
4028 switch (data[3]) {
3280c2d2 4029 case CMDF_ROUND_NEAREST:
1e49c5da
HS		 4030 down_count =
4031 (data[4] +
4032 devpriv->clock_ns / 2) / devpriv->clock_ns;
4033 break;
3280c2d2 4034 case CMDF_ROUND_DOWN:
1e49c5da
HS		 4035 down_count = data[4] / devpriv->clock_ns;
4036 break;
3280c2d2 4037 case CMDF_ROUND_UP:
1e49c5da
HS		 4038 down_count =
4039 (data[4] + devpriv->clock_ns -
4040 1) / devpriv->clock_ns;
4041 break;
4042 default:
4043 return -EINVAL;
1e49c5da
HS		 4044 }
4045 if (up_count * devpriv->clock_ns != data[2] ||
4046 down_count * devpriv->clock_ns != data[4]) {
4047 data[2] = up_count * devpriv->clock_ns;
4048 data[4] = down_count * devpriv->clock_ns;
4049 return -EAGAIN;
4050 }
5a92cac5 4051 ni_writel(dev, up_count, Calibration_HighTime_6143);
1e49c5da 4052 devpriv->pwm_up_count = up_count;
5a92cac5 4053 ni_writel(dev, down_count, Calibration_LowTime_6143);
1e49c5da
HS		 4054 devpriv->pwm_down_count = down_count;
4055 return 5;
1e49c5da
HS		 4056 case INSN_CONFIG_GET_PWM_OUTPUT:
4057 return ni_get_pwm_config(dev, data);
4058 default:
4059 return -EINVAL;
1e49c5da
HS		 4060 }
4061 return 0;
4062}
4063
62c2bce0
HS		 4064static int pack_mb88341(int addr, int val, int *bitstring)
4065{
4066 /*
4067 Fujitsu MB 88341
4068 Note that address bits are reversed. Thanks to
4069 Ingo Keen for noticing this.
4070
4071 Note also that the 88341 expects address values from
4072 1-12, whereas we use channel numbers 0-11. The NI
4073 docs use 1-12, also, so be careful here.
4074 */
4075 addr++;
4076 *bitstring = ((addr & 0x1) << 11) |
4077 ((addr & 0x2) << 9) |
4078 ((addr & 0x4) << 7) | ((addr & 0x8) << 5) | (val & 0xff);
4079 return 12;
4080}
4081
4082static int pack_dac8800(int addr, int val, int *bitstring)
4083{
4084 *bitstring = ((addr & 0x7) << 8) | (val & 0xff);
4085 return 11;
4086}
4087
4088static int pack_dac8043(int addr, int val, int *bitstring)
4089{
4090 *bitstring = val & 0xfff;
4091 return 12;
4092}
4093
4094static int pack_ad8522(int addr, int val, int *bitstring)
4095{
4096 *bitstring = (val & 0xfff) | (addr ? 0xc000 : 0xa000);
4097 return 16;
4098}
4099
4100static int pack_ad8804(int addr, int val, int *bitstring)
4101{
4102 *bitstring = ((addr & 0xf) << 8) | (val & 0xff);
4103 return 12;
4104}
4105
4106static int pack_ad8842(int addr, int val, int *bitstring)
4107{
4108 *bitstring = ((addr + 1) << 8) | (val & 0xff);
4109 return 12;
4110}
4111
4112struct caldac_struct {
4113 int n_chans;
4114 int n_bits;
4115 int (*packbits)(int, int, int *);
4116};
4117
4118static struct caldac_struct caldacs[] = {
4119 [mb88341] = {12, 8, pack_mb88341},
4120 [dac8800] = {8, 8, pack_dac8800},
4121 [dac8043] = {1, 12, pack_dac8043},
4122 [ad8522] = {2, 12, pack_ad8522},
4123 [ad8804] = {12, 8, pack_ad8804},
4124 [ad8842] = {8, 8, pack_ad8842},
4125 [ad8804_debug] = {16, 8, pack_ad8804},
4126};
4127
4128static void ni_write_caldac(struct comedi_device *dev, int addr, int val)
4129{
7cf94adc 4130 const struct ni_board_struct *board = dev->board_ptr;
62c2bce0
HS		 4131 struct ni_private *devpriv = dev->private;
4132 unsigned int loadbit = 0, bits = 0, bit, bitstring = 0;
2ed183ff 4133 unsigned int cmd;
62c2bce0
HS		 4134 int i;
4135 int type;
4136
62c2bce0
HS		 4137 if (devpriv->caldacs[addr] == val)
4138 return;
4139 devpriv->caldacs[addr] = val;
4140
4141 for (i = 0; i < 3; i++) {
4142 type = board->caldac[i];
4143 if (type == caldac_none)
4144 break;
4145 if (addr < caldacs[type].n_chans) {
4146 bits = caldacs[type].packbits(addr, val, &bitstring);
2ed183ff 4147 loadbit = NI_E_SERIAL_CMD_DAC_LD(i);
62c2bce0
HS		 4148 break;
4149 }
4150 addr -= caldacs[type].n_chans;
4151 }
4152
accb298f
HS		 4153 /* bits will be 0 if there is no caldac for the given addr */
4154 if (bits == 0)
4155 return;
4156
62c2bce0 4157 for (bit = 1 << (bits - 1); bit; bit >>= 1) {
2ed183ff
HS		 4158 cmd = (bit & bitstring) ? NI_E_SERIAL_CMD_SDATA : 0;
4159 ni_writeb(dev, cmd, NI_E_SERIAL_CMD_REG);
62c2bce0 4160 udelay(1);
2ed183ff 4161 ni_writeb(dev, NI_E_SERIAL_CMD_SCLK | cmd, NI_E_SERIAL_CMD_REG);
62c2bce0
HS		 4162 udelay(1);
4163 }
2ed183ff 4164 ni_writeb(dev, loadbit, NI_E_SERIAL_CMD_REG);
62c2bce0 4165 udelay(1);
2ed183ff 4166 ni_writeb(dev, 0, NI_E_SERIAL_CMD_REG);
62c2bce0
HS		 4167}
4168
4169static int ni_calib_insn_write(struct comedi_device *dev,
4170 struct comedi_subdevice *s,
4171 struct comedi_insn *insn,
4172 unsigned int *data)
4173{
4174 ni_write_caldac(dev, CR_CHAN(insn->chanspec), data[0]);
4175
4176 return 1;
4177}
4178
4179static int ni_calib_insn_read(struct comedi_device *dev,
4180 struct comedi_subdevice *s,
4181 struct comedi_insn *insn,
4182 unsigned int *data)
4183{
4184 struct ni_private *devpriv = dev->private;
4185
4186 data[0] = devpriv->caldacs[CR_CHAN(insn->chanspec)];
4187
4188 return 1;
4189}
4190
4191static void caldac_setup(struct comedi_device *dev, struct comedi_subdevice *s)
4192{
7cf94adc 4193 const struct ni_board_struct *board = dev->board_ptr;
62c2bce0
HS		 4194 struct ni_private *devpriv = dev->private;
4195 int i, j;
4196 int n_dacs;
4197 int n_chans = 0;
4198 int n_bits;
4199 int diffbits = 0;
4200 int type;
4201 int chan;
4202
4203 type = board->caldac[0];
4204 if (type == caldac_none)
4205 return;
4206 n_bits = caldacs[type].n_bits;
4207 for (i = 0; i < 3; i++) {
4208 type = board->caldac[i];
4209 if (type == caldac_none)
4210 break;
4211 if (caldacs[type].n_bits != n_bits)
4212 diffbits = 1;
4213 n_chans += caldacs[type].n_chans;
4214 }
4215 n_dacs = i;
4216 s->n_chan = n_chans;
4217
4218 if (diffbits) {
4219 unsigned int *maxdata_list;
4220
4221 if (n_chans > MAX_N_CALDACS)
89c4695e
HS		 4222 dev_err(dev->class_dev,
4223 "BUG! MAX_N_CALDACS too small\n");
62c2bce0
HS		 4224 s->maxdata_list = maxdata_list = devpriv->caldac_maxdata_list;
4225 chan = 0;
4226 for (i = 0; i < n_dacs; i++) {
4227 type = board->caldac[i];
4228 for (j = 0; j < caldacs[type].n_chans; j++) {
4229 maxdata_list[chan] =
4230 (1 << caldacs[type].n_bits) - 1;
4231 chan++;
4232 }
4233 }
4234
4235 for (chan = 0; chan < s->n_chan; chan++)
4236 ni_write_caldac(dev, i, s->maxdata_list[i] / 2);
4237 } else {
4238 type = board->caldac[0];
4239 s->maxdata = (1 << caldacs[type].n_bits) - 1;
4240
4241 for (chan = 0; chan < s->n_chan; chan++)
4242 ni_write_caldac(dev, i, s->maxdata / 2);
4243 }
4244}
4245
36adeee1
HS		 4246static int ni_read_eeprom(struct comedi_device *dev, int addr)
4247{
2ed183ff 4248 unsigned int cmd = NI_E_SERIAL_CMD_EEPROM_CS;
36adeee1
HS		 4249 int bit;
4250 int bitstring;
4251
4252 bitstring = 0x0300 | ((addr & 0x100) << 3) | (addr & 0xff);
2ed183ff 4253 ni_writeb(dev, cmd, NI_E_SERIAL_CMD_REG);
36adeee1 4254 for (bit = 0x8000; bit; bit >>= 1) {
2ed183ff
HS		 4255 if (bit & bitstring)
4256 cmd |= NI_E_SERIAL_CMD_SDATA;
4257 else
4258 cmd &= ~NI_E_SERIAL_CMD_SDATA;
4259
4260 ni_writeb(dev, cmd, NI_E_SERIAL_CMD_REG);
4261 ni_writeb(dev, NI_E_SERIAL_CMD_SCLK | cmd, NI_E_SERIAL_CMD_REG);
36adeee1 4262 }
2ed183ff 4263 cmd = NI_E_SERIAL_CMD_EEPROM_CS;
36adeee1
HS		 4264 bitstring = 0;
4265 for (bit = 0x80; bit; bit >>= 1) {
2ed183ff
HS		 4266 ni_writeb(dev, cmd, NI_E_SERIAL_CMD_REG);
4267 ni_writeb(dev, NI_E_SERIAL_CMD_SCLK | cmd, NI_E_SERIAL_CMD_REG);
906170b8
HS		 4268 if (ni_readb(dev, NI_E_STATUS_REG) & NI_E_STATUS_PROMOUT)
4269 bitstring |= bit;
36adeee1 4270 }
2ed183ff 4271 ni_writeb(dev, 0, NI_E_SERIAL_CMD_REG);
36adeee1
HS		 4272
4273 return bitstring;
4274}
4275
4276static int ni_eeprom_insn_read(struct comedi_device *dev,
4277 struct comedi_subdevice *s,
4278 struct comedi_insn *insn,
4279 unsigned int *data)
4280{
4281 data[0] = ni_read_eeprom(dev, CR_CHAN(insn->chanspec));
4282
4283 return 1;
4284}
4285
4286static int ni_m_series_eeprom_insn_read(struct comedi_device *dev,
4287 struct comedi_subdevice *s,
4288 struct comedi_insn *insn,
4289 unsigned int *data)
4290{
4291 struct ni_private *devpriv = dev->private;
4292
4293 data[0] = devpriv->eeprom_buffer[CR_CHAN(insn->chanspec)];
4294
4295 return 1;
4296}
4297
4187a79a
HS		 4298static unsigned ni_old_get_pfi_routing(struct comedi_device *dev,
4299 unsigned chan)
4300{
4301 /* pre-m-series boards have fixed signals on pfi pins */
4302 switch (chan) {
4303 case 0:
4304 return NI_PFI_OUTPUT_AI_START1;
4187a79a
HS		 4305 case 1:
4306 return NI_PFI_OUTPUT_AI_START2;
4187a79a
HS		 4307 case 2:
4308 return NI_PFI_OUTPUT_AI_CONVERT;
4187a79a
HS		 4309 case 3:
4310 return NI_PFI_OUTPUT_G_SRC1;
4187a79a
HS		 4311 case 4:
4312 return NI_PFI_OUTPUT_G_GATE1;
4187a79a
HS		 4313 case 5:
4314 return NI_PFI_OUTPUT_AO_UPDATE_N;
4187a79a
HS		 4315 case 6:
4316 return NI_PFI_OUTPUT_AO_START1;
4187a79a
HS		 4317 case 7:
4318 return NI_PFI_OUTPUT_AI_START_PULSE;
4187a79a
HS		 4319 case 8:
4320 return NI_PFI_OUTPUT_G_SRC0;
4187a79a
HS		 4321 case 9:
4322 return NI_PFI_OUTPUT_G_GATE0;
4187a79a 4323 default:
cd25503f 4324 dev_err(dev->class_dev, "bug, unhandled case in switch.\n");
4187a79a
HS		 4325 break;
4326 }
4327 return 0;
4328}
4329
4330static int ni_old_set_pfi_routing(struct comedi_device *dev,
4331 unsigned chan, unsigned source)
4332{
4333 /* pre-m-series boards have fixed signals on pfi pins */
4334 if (source != ni_old_get_pfi_routing(dev, chan))
4335 return -EINVAL;
4336 return 2;
4337}
4338
4339static unsigned ni_m_series_get_pfi_routing(struct comedi_device *dev,
4340 unsigned chan)
4341{
4342 struct ni_private *devpriv = dev->private;
4343 const unsigned array_offset = chan / 3;
4344
43e9d883 4345 return NI_M_PFI_OUT_SEL_TO_SRC(chan,
4187a79a
HS		 4346 devpriv->pfi_output_select_reg[array_offset]);
4347}
4348
4349static int ni_m_series_set_pfi_routing(struct comedi_device *dev,
4350 unsigned chan, unsigned source)
4351{
4352 struct ni_private *devpriv = dev->private;
e0852f6a
HS		 4353 unsigned index = chan / 3;
4354 unsigned short val = devpriv->pfi_output_select_reg[index];
4187a79a
HS		 4355
4356 if ((source & 0x1f) != source)
4357 return -EINVAL;
e0852f6a 4358
43e9d883
HS		 4359 val &= ~NI_M_PFI_OUT_SEL_MASK(chan);
4360 val |= NI_M_PFI_OUT_SEL(chan, source);
975b6d25 4361 ni_writew(dev, val, NI_M_PFI_OUT_SEL_REG(index));
e0852f6a
HS		 4362 devpriv->pfi_output_select_reg[index] = val;
4363
4187a79a
HS		 4364 return 2;
4365}
4366
4367static unsigned ni_get_pfi_routing(struct comedi_device *dev, unsigned chan)
4368{
17733219 4369 struct ni_private *devpriv = dev->private;
4187a79a 4370
0953ee4a
HS		 4371 return (devpriv->is_m_series)
4372 ? ni_m_series_get_pfi_routing(dev, chan)
4373 : ni_old_get_pfi_routing(dev, chan);
4187a79a
HS		 4374}
4375
4376static int ni_set_pfi_routing(struct comedi_device *dev, unsigned chan,
4377 unsigned source)
4378{
17733219 4379 struct ni_private *devpriv = dev->private;
4187a79a 4380
0953ee4a
HS		 4381 return (devpriv->is_m_series)
4382 ? ni_m_series_set_pfi_routing(dev, chan, source)
4383 : ni_old_set_pfi_routing(dev, chan, source);
4187a79a
HS		 4384}
4385
4386static int ni_config_filter(struct comedi_device *dev,
4387 unsigned pfi_channel,
4388 enum ni_pfi_filter_select filter)
4389{
9c340ac9 4390 struct ni_private *devpriv = dev->private;
4187a79a
HS		 4391 unsigned bits;
4392
17733219 4393 if (!devpriv->is_m_series)
4187a79a 4394 return -ENOTSUPP;
17733219 4395
975b6d25 4396 bits = ni_readl(dev, NI_M_PFI_FILTER_REG);
0dee7ecc
HS		 4397 bits &= ~NI_M_PFI_FILTER_SEL_MASK(pfi_channel);
4398 bits |= NI_M_PFI_FILTER_SEL(pfi_channel, filter);
975b6d25 4399 ni_writel(dev, bits, NI_M_PFI_FILTER_REG);
4187a79a
HS		 4400 return 0;
4401}
4402
4403static int ni_pfi_insn_config(struct comedi_device *dev,
4404 struct comedi_subdevice *s,
4405 struct comedi_insn *insn,
4406 unsigned int *data)
4407{
4408 struct ni_private *devpriv = dev->private;
4409 unsigned int chan;
4410
4411 if (insn->n < 1)
4412 return -EINVAL;
4413
4414 chan = CR_CHAN(insn->chanspec);
4415
4416 switch (data[0]) {
4417 case COMEDI_OUTPUT:
5ecadf8c 4418 ni_set_bits(dev, NISTC_IO_BIDIR_PIN_REG, 1 << chan, 1);
4187a79a
HS		 4419 break;
4420 case COMEDI_INPUT:
5ecadf8c 4421 ni_set_bits(dev, NISTC_IO_BIDIR_PIN_REG, 1 << chan, 0);
4187a79a
HS		 4422 break;
4423 case INSN_CONFIG_DIO_QUERY:
4424 data[1] =
4425 (devpriv->io_bidirection_pin_reg & (1 << chan)) ?
4426 COMEDI_OUTPUT : COMEDI_INPUT;
4427 return 0;
4187a79a
HS		 4428 case INSN_CONFIG_SET_ROUTING:
4429 return ni_set_pfi_routing(dev, chan, data[1]);
4187a79a
HS		 4430 case INSN_CONFIG_GET_ROUTING:
4431 data[1] = ni_get_pfi_routing(dev, chan);
4432 break;
4433 case INSN_CONFIG_FILTER:
4434 return ni_config_filter(dev, chan, data[1]);
4187a79a
HS		 4435 default:
4436 return -EINVAL;
4437 }
4438 return 0;
4439}
4440
4441static int ni_pfi_insn_bits(struct comedi_device *dev,
4442 struct comedi_subdevice *s,
4443 struct comedi_insn *insn,
4444 unsigned int *data)
4445{
9c340ac9 4446 struct ni_private *devpriv = dev->private;
4187a79a 4447
17733219 4448 if (!devpriv->is_m_series)
4187a79a
HS		 4449 return -ENOTSUPP;
4450
4451 if (comedi_dio_update_state(s, data))
975b6d25 4452 ni_writew(dev, s->state, NI_M_PFI_DO_REG);
4187a79a 4453
975b6d25 4454 data[1] = ni_readw(dev, NI_M_PFI_DI_REG);
4187a79a
HS		 4455
4456 return insn->n;
4457}
4458
24e7c352
HS		 4459static int cs5529_wait_for_idle(struct comedi_device *dev)
4460{
4461 unsigned short status;
4462 const int timeout = HZ;
4463 int i;
4464
4465 for (i = 0; i < timeout; i++) {
4466 status = ni_ao_win_inw(dev, CAL_ADC_Status_67xx);
4467 if ((status & CSS_ADC_BUSY) == 0)
4468 break;
4469 set_current_state(TASK_INTERRUPTIBLE);
4470 if (schedule_timeout(1))
4471 return -EIO;
4472 }
24e7c352 4473 if (i == timeout) {
cd25503f 4474 dev_err(dev->class_dev, "timeout\n");
24e7c352
HS		 4475 return -ETIME;
4476 }
4477 return 0;
4478}
4479
4480static void cs5529_command(struct comedi_device *dev, unsigned short value)
4481{
4482 static const int timeout = 100;
4483 int i;
4484
4485 ni_ao_win_outw(dev, value, CAL_ADC_Command_67xx);
4486 /* give time for command to start being serially clocked into cs5529.
4487 * this insures that the CSS_ADC_BUSY bit will get properly
4488 * set before we exit this function.
4489 */
4490 for (i = 0; i < timeout; i++) {
4491 if ((ni_ao_win_inw(dev, CAL_ADC_Status_67xx) & CSS_ADC_BUSY))
4492 break;
4493 udelay(1);
4494 }
24e7c352 4495 if (i == timeout)
5ac1d82b
HS		 4496 dev_err(dev->class_dev,
4497 "possible problem - never saw adc go busy?\n");
24e7c352
HS		 4498}
4499
4500static int cs5529_do_conversion(struct comedi_device *dev,
4501 unsigned short *data)
4502{
4503 int retval;
4504 unsigned short status;
4505
4506 cs5529_command(dev, CSCMD_COMMAND | CSCMD_SINGLE_CONVERSION);
4507 retval = cs5529_wait_for_idle(dev);
4508 if (retval) {
5ac1d82b
HS		 4509 dev_err(dev->class_dev,
4510 "timeout or signal in cs5529_do_conversion()\n");
24e7c352
HS		 4511 return -ETIME;
4512 }
4513 status = ni_ao_win_inw(dev, CAL_ADC_Status_67xx);
4514 if (status & CSS_OSC_DETECT) {
89c4695e
HS		 4515 dev_err(dev->class_dev,
4516 "cs5529 conversion error, status CSS_OSC_DETECT\n");
24e7c352
HS		 4517 return -EIO;
4518 }
4519 if (status & CSS_OVERRANGE) {
89c4695e
HS		 4520 dev_err(dev->class_dev,
4521 "cs5529 conversion error, overrange (ignoring)\n");
24e7c352
HS		 4522 }
4523 if (data) {
4524 *data = ni_ao_win_inw(dev, CAL_ADC_Data_67xx);
4525 /* cs5529 returns 16 bit signed data in bipolar mode */
4526 *data ^= (1 << 15);
4527 }
4528 return 0;
4529}
4530
4531static int cs5529_ai_insn_read(struct comedi_device *dev,
4532 struct comedi_subdevice *s,
4533 struct comedi_insn *insn,
4534 unsigned int *data)
4535{
4536 int n, retval;
4537 unsigned short sample;
4538 unsigned int channel_select;
4539 const unsigned int INTERNAL_REF = 0x1000;
4540
4541 /* Set calibration adc source. Docs lie, reference select bits 8 to 11
4542 * do nothing. bit 12 seems to chooses internal reference voltage, bit
4543 * 13 causes the adc input to go overrange (maybe reads external reference?) */
4544 if (insn->chanspec & CR_ALT_SOURCE)
4545 channel_select = INTERNAL_REF;
4546 else
4547 channel_select = CR_CHAN(insn->chanspec);
4548 ni_ao_win_outw(dev, channel_select, AO_Calibration_Channel_Select_67xx);
4549
4550 for (n = 0; n < insn->n; n++) {
4551 retval = cs5529_do_conversion(dev, &sample);
4552 if (retval < 0)
4553 return retval;
4554 data[n] = sample;
4555 }
4556 return insn->n;
4557}
4558
4559static void cs5529_config_write(struct comedi_device *dev, unsigned int value,
4560 unsigned int reg_select_bits)
4561{
4562 ni_ao_win_outw(dev, ((value >> 16) & 0xff),
4563 CAL_ADC_Config_Data_High_Word_67xx);
4564 ni_ao_win_outw(dev, (value & 0xffff),
4565 CAL_ADC_Config_Data_Low_Word_67xx);
4566 reg_select_bits &= CSCMD_REGISTER_SELECT_MASK;
4567 cs5529_command(dev, CSCMD_COMMAND | reg_select_bits);
4568 if (cs5529_wait_for_idle(dev))
5ac1d82b
HS		 4569 dev_err(dev->class_dev,
4570 "timeout or signal in %s\n", __func__);
24e7c352
HS		 4571}
4572
4573static int init_cs5529(struct comedi_device *dev)
4574{
4575 unsigned int config_bits =
4576 CSCFG_PORT_MODE | CSCFG_WORD_RATE_2180_CYCLES;
4577
4578#if 1
4579 /* do self-calibration */
4580 cs5529_config_write(dev, config_bits | CSCFG_SELF_CAL_OFFSET_GAIN,
4581 CSCMD_CONFIG_REGISTER);
4582 /* need to force a conversion for calibration to run */
4583 cs5529_do_conversion(dev, NULL);
4584#else
4585 /* force gain calibration to 1 */
4586 cs5529_config_write(dev, 0x400000, CSCMD_GAIN_REGISTER);
4587 cs5529_config_write(dev, config_bits | CSCFG_SELF_CAL_OFFSET,
4588 CSCMD_CONFIG_REGISTER);
4589 if (cs5529_wait_for_idle(dev))
5ac1d82b
HS		 4590 dev_err(dev->class_dev,
4591 "timeout or signal in %s\n", __func__);
24e7c352
HS		 4592#endif
4593 return 0;
4594}
4595
624b161f
HS		 4596/*
4597 * Find best multiplier/divider to try and get the PLL running at 80 MHz
4598 * given an arbitrary frequency input clock.
4599 */
4600static int ni_mseries_get_pll_parameters(unsigned reference_period_ns,
4601 unsigned *freq_divider,
4602 unsigned *freq_multiplier,
4603 unsigned *actual_period_ns)
4604{
4605 unsigned div;
4606 unsigned best_div = 1;
624b161f
HS		 4607 unsigned mult;
4608 unsigned best_mult = 1;
624b161f
HS		 4609 static const unsigned pico_per_nano = 1000;
4610
4611 const unsigned reference_picosec = reference_period_ns * pico_per_nano;
4612 /* m-series wants the phased-locked loop to output 80MHz, which is divided by 4 to
4613 * 20 MHz for most timing clocks */
4614 static const unsigned target_picosec = 12500;
4615 static const unsigned fudge_factor_80_to_20Mhz = 4;
4616 int best_period_picosec = 0;
f7401979 4617
b965e6a4
HS		 4618 for (div = 1; div <= NI_M_PLL_MAX_DIVISOR; ++div) {
4619 for (mult = 1; mult <= NI_M_PLL_MAX_MULTIPLIER; ++mult) {
624b161f
HS		 4620 unsigned new_period_ps =
4621 (reference_picosec * div) / mult;
4622 if (abs(new_period_ps - target_picosec) <
4623 abs(best_period_picosec - target_picosec)) {
4624 best_period_picosec = new_period_ps;
4625 best_div = div;
4626 best_mult = mult;
4627 }
4628 }
4629 }
07e6b2e2 4630 if (best_period_picosec == 0)
624b161f 4631 return -EIO;
07e6b2e2 4632
624b161f
HS		 4633 *freq_divider = best_div;
4634 *freq_multiplier = best_mult;
4635 *actual_period_ns =
4636 (best_period_picosec * fudge_factor_80_to_20Mhz +
4637 (pico_per_nano / 2)) / pico_per_nano;
4638 return 0;
4639}
4640
4641static int ni_mseries_set_pll_master_clock(struct comedi_device *dev,
4642 unsigned source, unsigned period_ns)
4643{
4644 struct ni_private *devpriv = dev->private;
4645 static const unsigned min_period_ns = 50;
4646 static const unsigned max_period_ns = 1000;
4647 static const unsigned timeout = 1000;
4648 unsigned pll_control_bits;
4649 unsigned freq_divider;
4650 unsigned freq_multiplier;
40aafd79 4651 unsigned rtsi;
624b161f
HS		 4652 unsigned i;
4653 int retval;
4654
4655 if (source == NI_MIO_PLL_PXI10_CLOCK)
4656 period_ns = 100;
4657 /* these limits are somewhat arbitrary, but NI advertises 1 to 20MHz range so we'll use that */
4658 if (period_ns < min_period_ns || period_ns > max_period_ns) {
89c4695e
HS		 4659 dev_err(dev->class_dev,
4660 "%s: you must specify an input clock frequency between %i and %i nanosec for the phased-lock loop\n",
4661 __func__, min_period_ns, max_period_ns);
624b161f
HS		 4662 return -EINVAL;
4663 }
a4f18b1c 4664 devpriv->rtsi_trig_direction_reg &= ~NISTC_RTSI_TRIG_USE_CLK;
00b14b1d 4665 ni_stc_writew(dev, devpriv->rtsi_trig_direction_reg,
a4f18b1c 4666 NISTC_RTSI_TRIG_DIR_REG);
b965e6a4 4667 pll_control_bits = NI_M_PLL_CTRL_ENA | NI_M_PLL_CTRL_VCO_MODE_75_150MHZ;
40aafd79
HS		 4668 devpriv->clock_and_fout2 |= NI_M_CLK_FOUT2_TIMEBASE1_PLL |
4669 NI_M_CLK_FOUT2_TIMEBASE3_PLL;
4670 devpriv->clock_and_fout2 &= ~NI_M_CLK_FOUT2_PLL_SRC_MASK;
624b161f
HS		 4671 switch (source) {
4672 case NI_MIO_PLL_PXI_STAR_TRIGGER_CLOCK:
40aafd79 4673 devpriv->clock_and_fout2 |= NI_M_CLK_FOUT2_PLL_SRC_STAR;
624b161f
HS		 4674 break;
4675 case NI_MIO_PLL_PXI10_CLOCK:
4676 /* pxi clock is 10MHz */
40aafd79 4677 devpriv->clock_and_fout2 |= NI_M_CLK_FOUT2_PLL_SRC_PXI10;
624b161f
HS		 4678 break;
4679 default:
40aafd79
HS		 4680 for (rtsi = 0; rtsi <= NI_M_MAX_RTSI_CHAN; ++rtsi) {
4681 if (source == NI_MIO_PLL_RTSI_CLOCK(rtsi)) {
4682 devpriv->clock_and_fout2 |=
4683 NI_M_CLK_FOUT2_PLL_SRC_RTSI(rtsi);
4684 break;
624b161f 4685 }
624b161f 4686 }
40aafd79
HS		 4687 if (rtsi > NI_M_MAX_RTSI_CHAN)
4688 return -EINVAL;
624b161f
HS		 4689 break;
4690 }
07e6b2e2
HS		 4691 retval = ni_mseries_get_pll_parameters(period_ns,
4692 &freq_divider,
4693 &freq_multiplier,
4694 &devpriv->clock_ns);
4695 if (retval < 0) {
4696 dev_err(dev->class_dev,
cd25503f 4697 "bug, failed to find pll parameters\n");
07e6b2e2
HS		 4698 return retval;
4699 }
4700
975b6d25 4701 ni_writew(dev, devpriv->clock_and_fout2, NI_M_CLK_FOUT2_REG);
b965e6a4
HS		 4702 pll_control_bits |= NI_M_PLL_CTRL_DIVISOR(freq_divider) |
4703 NI_M_PLL_CTRL_MULTIPLIER(freq_multiplier);
624b161f 4704
975b6d25 4705 ni_writew(dev, pll_control_bits, NI_M_PLL_CTRL_REG);
624b161f
HS		 4706 devpriv->clock_source = source;
4707 /* it seems to typically take a few hundred microseconds for PLL to lock */
4708 for (i = 0; i < timeout; ++i) {
b1c70645 4709 if (ni_readw(dev, NI_M_PLL_STATUS_REG) & NI_M_PLL_STATUS_LOCKED)
624b161f
HS		 4710 break;
4711 udelay(1);
4712 }
4713 if (i == timeout) {
89c4695e
HS		 4714 dev_err(dev->class_dev,
4715 "%s: timed out waiting for PLL to lock to reference clock source %i with period %i ns\n",
4716 __func__, source, period_ns);
624b161f
HS		 4717 return -ETIMEDOUT;
4718 }
4719 return 3;
4720}
4721
4722static int ni_set_master_clock(struct comedi_device *dev,
4723 unsigned source, unsigned period_ns)
4724{
624b161f
HS		 4725 struct ni_private *devpriv = dev->private;
4726
4727 if (source == NI_MIO_INTERNAL_CLOCK) {
a4f18b1c 4728 devpriv->rtsi_trig_direction_reg &= ~NISTC_RTSI_TRIG_USE_CLK;
00b14b1d 4729 ni_stc_writew(dev, devpriv->rtsi_trig_direction_reg,
a4f18b1c 4730 NISTC_RTSI_TRIG_DIR_REG);
624b161f 4731 devpriv->clock_ns = TIMEBASE_1_NS;
17733219 4732 if (devpriv->is_m_series) {
624b161f 4733 devpriv->clock_and_fout2 &=
40aafd79
HS		 4734 ~(NI_M_CLK_FOUT2_TIMEBASE1_PLL |
4735 NI_M_CLK_FOUT2_TIMEBASE3_PLL);
5a92cac5 4736 ni_writew(dev, devpriv->clock_and_fout2,
975b6d25
HS		 4737 NI_M_CLK_FOUT2_REG);
4738 ni_writew(dev, 0, NI_M_PLL_CTRL_REG);
624b161f
HS		 4739 }
4740 devpriv->clock_source = source;
4741 } else {
17733219 4742 if (devpriv->is_m_series) {
624b161f
HS		 4743 return ni_mseries_set_pll_master_clock(dev, source,
4744 period_ns);
4745 } else {
4746 if (source == NI_MIO_RTSI_CLOCK) {
4747 devpriv->rtsi_trig_direction_reg |=
a4f18b1c 4748 NISTC_RTSI_TRIG_USE_CLK;
00b14b1d
HS		 4749 ni_stc_writew(dev,
4750 devpriv->rtsi_trig_direction_reg,
a4f18b1c 4751 NISTC_RTSI_TRIG_DIR_REG);
624b161f 4752 if (period_ns == 0) {
89c4695e 4753 dev_err(dev->class_dev,
cd25503f 4754 "we don't handle an unspecified clock period correctly yet, returning error\n");
624b161f 4755 return -EINVAL;
624b161f 4756 }
0953ee4a 4757 devpriv->clock_ns = period_ns;
624b161f 4758 devpriv->clock_source = source;
6ac986d0 4759 } else {
624b161f 4760 return -EINVAL;
6ac986d0 4761 }
624b161f
HS		 4762 }
4763 }
4764 return 3;
4765}
4766
ae43763d
HS		 4767static int ni_valid_rtsi_output_source(struct comedi_device *dev,
4768 unsigned chan, unsigned source)
4769{
17733219 4770 struct ni_private *devpriv = dev->private;
ae43763d 4771
a4f18b1c
HS		 4772 if (chan >= NISTC_RTSI_TRIG_NUM_CHAN(devpriv->is_m_series)) {
4773 if (chan == NISTC_RTSI_TRIG_OLD_CLK_CHAN) {
ae43763d
HS		 4774 if (source == NI_RTSI_OUTPUT_RTSI_OSC)
4775 return 1;
0953ee4a 4776
89c4695e
HS		 4777 dev_err(dev->class_dev,
4778 "%s: invalid source for channel=%i, channel %i is always the RTSI clock for pre-m-series boards\n",
a4f18b1c 4779 __func__, chan, NISTC_RTSI_TRIG_OLD_CLK_CHAN);
0953ee4a 4780 return 0;
ae43763d
HS		 4781 }
4782 return 0;
4783 }
4784 switch (source) {
4785 case NI_RTSI_OUTPUT_ADR_START1:
4786 case NI_RTSI_OUTPUT_ADR_START2:
4787 case NI_RTSI_OUTPUT_SCLKG:
4788 case NI_RTSI_OUTPUT_DACUPDN:
4789 case NI_RTSI_OUTPUT_DA_START1:
4790 case NI_RTSI_OUTPUT_G_SRC0:
4791 case NI_RTSI_OUTPUT_G_GATE0:
4792 case NI_RTSI_OUTPUT_RGOUT0:
4793 case NI_RTSI_OUTPUT_RTSI_BRD_0:
4794 return 1;
ae43763d 4795 case NI_RTSI_OUTPUT_RTSI_OSC:
95940961 4796 return (devpriv->is_m_series) ? 1 : 0;
ae43763d
HS		 4797 default:
4798 return 0;
ae43763d
HS		 4799 }
4800}
4801
4802static int ni_set_rtsi_routing(struct comedi_device *dev,
390bc6ff 4803 unsigned chan, unsigned src)
ae43763d
HS		 4804{
4805 struct ni_private *devpriv = dev->private;
4806
390bc6ff 4807 if (ni_valid_rtsi_output_source(dev, chan, src) == 0)
ae43763d
HS		 4808 return -EINVAL;
4809 if (chan < 4) {
390bc6ff
HS		 4810 devpriv->rtsi_trig_a_output_reg &= ~NISTC_RTSI_TRIG_MASK(chan);
4811 devpriv->rtsi_trig_a_output_reg |= NISTC_RTSI_TRIG(chan, src);
00b14b1d 4812 ni_stc_writew(dev, devpriv->rtsi_trig_a_output_reg,
390bc6ff 4813 NISTC_RTSI_TRIGA_OUT_REG);
ae43763d 4814 } else if (chan < 8) {
390bc6ff
HS		 4815 devpriv->rtsi_trig_b_output_reg &= ~NISTC_RTSI_TRIG_MASK(chan);
4816 devpriv->rtsi_trig_b_output_reg |= NISTC_RTSI_TRIG(chan, src);
00b14b1d 4817 ni_stc_writew(dev, devpriv->rtsi_trig_b_output_reg,
390bc6ff 4818 NISTC_RTSI_TRIGB_OUT_REG);
ae43763d
HS		 4819 }
4820 return 2;
4821}
4822
4823static unsigned ni_get_rtsi_routing(struct comedi_device *dev, unsigned chan)
4824{
4825 struct ni_private *devpriv = dev->private;
4826
4827 if (chan < 4) {
390bc6ff
HS		 4828 return NISTC_RTSI_TRIG_TO_SRC(chan,
4829 devpriv->rtsi_trig_a_output_reg);
a4f18b1c 4830 } else if (chan < NISTC_RTSI_TRIG_NUM_CHAN(devpriv->is_m_series)) {
390bc6ff
HS		 4831 return NISTC_RTSI_TRIG_TO_SRC(chan,
4832 devpriv->rtsi_trig_b_output_reg);
ae43763d 4833 } else {
a4f18b1c 4834 if (chan == NISTC_RTSI_TRIG_OLD_CLK_CHAN)
ae43763d 4835 return NI_RTSI_OUTPUT_RTSI_OSC;
cd25503f 4836 dev_err(dev->class_dev, "bug! should never get here?\n");
ae43763d
HS		 4837 return 0;
4838 }
4839}
4840
4841static int ni_rtsi_insn_config(struct comedi_device *dev,
4842 struct comedi_subdevice *s,
4843 struct comedi_insn *insn,
4844 unsigned int *data)
4845{
ae43763d
HS		 4846 struct ni_private *devpriv = dev->private;
4847 unsigned int chan = CR_CHAN(insn->chanspec);
a4f18b1c 4848 unsigned int max_chan = NISTC_RTSI_TRIG_NUM_CHAN(devpriv->is_m_series);
ae43763d
HS		 4849
4850 switch (data[0]) {
4851 case INSN_CONFIG_DIO_OUTPUT:
a4f18b1c 4852 if (chan < max_chan) {
ae43763d 4853 devpriv->rtsi_trig_direction_reg |=
a4f18b1c
HS		 4854 NISTC_RTSI_TRIG_DIR(chan, devpriv->is_m_series);
4855 } else if (chan == NISTC_RTSI_TRIG_OLD_CLK_CHAN) {
ae43763d 4856 devpriv->rtsi_trig_direction_reg |=
a4f18b1c 4857 NISTC_RTSI_TRIG_DRV_CLK;
ae43763d 4858 }
00b14b1d 4859 ni_stc_writew(dev, devpriv->rtsi_trig_direction_reg,
a4f18b1c 4860 NISTC_RTSI_TRIG_DIR_REG);
ae43763d
HS		 4861 break;
4862 case INSN_CONFIG_DIO_INPUT:
a4f18b1c 4863 if (chan < max_chan) {
ae43763d 4864 devpriv->rtsi_trig_direction_reg &=
a4f18b1c
HS		 4865 ~NISTC_RTSI_TRIG_DIR(chan, devpriv->is_m_series);
4866 } else if (chan == NISTC_RTSI_TRIG_OLD_CLK_CHAN) {
ae43763d 4867 devpriv->rtsi_trig_direction_reg &=
a4f18b1c 4868 ~NISTC_RTSI_TRIG_DRV_CLK;
ae43763d 4869 }
00b14b1d 4870 ni_stc_writew(dev, devpriv->rtsi_trig_direction_reg,
a4f18b1c 4871 NISTC_RTSI_TRIG_DIR_REG);
ae43763d
HS		 4872 break;
4873 case INSN_CONFIG_DIO_QUERY:
a4f18b1c 4874 if (chan < max_chan) {
ae43763d
HS		 4875 data[1] =
4876 (devpriv->rtsi_trig_direction_reg &
a4f18b1c 4877 NISTC_RTSI_TRIG_DIR(chan, devpriv->is_m_series))
ae43763d
HS		 4878 ? INSN_CONFIG_DIO_OUTPUT
4879 : INSN_CONFIG_DIO_INPUT;
a4f18b1c
HS		 4880 } else if (chan == NISTC_RTSI_TRIG_OLD_CLK_CHAN) {
4881 data[1] = (devpriv->rtsi_trig_direction_reg &
4882 NISTC_RTSI_TRIG_DRV_CLK)
4883 ? INSN_CONFIG_DIO_OUTPUT
4884 : INSN_CONFIG_DIO_INPUT;
ae43763d
HS		 4885 }
4886 return 2;
ae43763d
HS		 4887 case INSN_CONFIG_SET_CLOCK_SRC:
4888 return ni_set_master_clock(dev, data[1], data[2]);
ae43763d
HS		 4889 case INSN_CONFIG_GET_CLOCK_SRC:
4890 data[1] = devpriv->clock_source;
4891 data[2] = devpriv->clock_ns;
4892 return 3;
ae43763d
HS		 4893 case INSN_CONFIG_SET_ROUTING:
4894 return ni_set_rtsi_routing(dev, chan, data[1]);
ae43763d
HS		 4895 case INSN_CONFIG_GET_ROUTING:
4896 data[1] = ni_get_rtsi_routing(dev, chan);
4897 return 2;
ae43763d
HS		 4898 default:
4899 return -EINVAL;
ae43763d
HS		 4900 }
4901 return 1;
4902}
4903
12db1416
HS		 4904static int ni_rtsi_insn_bits(struct comedi_device *dev,
4905 struct comedi_subdevice *s,
4906 struct comedi_insn *insn,
4907 unsigned int *data)
4908{
4909 data[1] = 0;
4910
4911 return insn->n;
4912}
4913
892885ea
HS		 4914static void ni_rtsi_init(struct comedi_device *dev)
4915{
892885ea
HS		 4916 struct ni_private *devpriv = dev->private;
4917
4918 /* Initialises the RTSI bus signal switch to a default state */
4919
40aafd79
HS		 4920 /*
4921 * Use 10MHz instead of 20MHz for RTSI clock frequency. Appears
4922 * to have no effect, at least on pxi-6281, which always uses
4923 * 20MHz rtsi clock frequency
4924 */
4925 devpriv->clock_and_fout2 = NI_M_CLK_FOUT2_RTSI_10MHZ;
892885ea 4926 /* Set clock mode to internal */
892885ea 4927 if (ni_set_master_clock(dev, NI_MIO_INTERNAL_CLOCK, 0) < 0)
89c4695e 4928 dev_err(dev->class_dev, "ni_set_master_clock failed, bug?\n");
892885ea
HS		 4929 /* default internal lines routing to RTSI bus lines */
4930 devpriv->rtsi_trig_a_output_reg =
390bc6ff
HS		 4931 NISTC_RTSI_TRIG(0, NI_RTSI_OUTPUT_ADR_START1) |
4932 NISTC_RTSI_TRIG(1, NI_RTSI_OUTPUT_ADR_START2) |
4933 NISTC_RTSI_TRIG(2, NI_RTSI_OUTPUT_SCLKG) |
4934 NISTC_RTSI_TRIG(3, NI_RTSI_OUTPUT_DACUPDN);
00b14b1d 4935 ni_stc_writew(dev, devpriv->rtsi_trig_a_output_reg,
390bc6ff 4936 NISTC_RTSI_TRIGA_OUT_REG);
892885ea 4937 devpriv->rtsi_trig_b_output_reg =
390bc6ff
HS		 4938 NISTC_RTSI_TRIG(4, NI_RTSI_OUTPUT_DA_START1) |
4939 NISTC_RTSI_TRIG(5, NI_RTSI_OUTPUT_G_SRC0) |
4940 NISTC_RTSI_TRIG(6, NI_RTSI_OUTPUT_G_GATE0);
17733219 4941 if (devpriv->is_m_series)
892885ea 4942 devpriv->rtsi_trig_b_output_reg |=
390bc6ff 4943 NISTC_RTSI_TRIG(7, NI_RTSI_OUTPUT_RTSI_OSC);
00b14b1d 4944 ni_stc_writew(dev, devpriv->rtsi_trig_b_output_reg,
390bc6ff 4945 NISTC_RTSI_TRIGB_OUT_REG);
892885ea 4946
24a11ba6
HS		 4947 /*
4948 * Sets the source and direction of the 4 on board lines
4949 * ni_stc_writew(dev, 0, NISTC_RTSI_BOARD_REG);
4950 */
892885ea
HS		 4951}
4952
c8508a1d
HS		 4953#ifdef PCIDMA
4954static int ni_gpct_cmd(struct comedi_device *dev, struct comedi_subdevice *s)
4955{
4956 struct ni_gpct *counter = s->private;
4957 int retval;
4958
4959 retval = ni_request_gpct_mite_channel(dev, counter->counter_index,
4960 COMEDI_INPUT);
4961 if (retval) {
5ac1d82b
HS		 4962 dev_err(dev->class_dev,
4963 "no dma channel available for use by counter\n");
c8508a1d
HS		 4964 return retval;
4965 }
f8cfd0eb 4966 ni_tio_acknowledge(counter);
c8508a1d
HS		 4967 ni_e_series_enable_second_irq(dev, counter->counter_index, 1);
4968
4969 return ni_tio_cmd(dev, s);
4970}
4971
4972static int ni_gpct_cancel(struct comedi_device *dev, struct comedi_subdevice *s)
4973{
4974 struct ni_gpct *counter = s->private;
4975 int retval;
4976
4977 retval = ni_tio_cancel(counter);
4978 ni_e_series_enable_second_irq(dev, counter->counter_index, 0);
4979 ni_release_gpct_mite_channel(dev, counter->counter_index);
4980 return retval;
4981}
4982#endif
4983
c75527fb
HS		 4984static irqreturn_t ni_E_interrupt(int irq, void *d)
4985{
4986 struct comedi_device *dev = d;
c75527fb
HS		 4987 unsigned short a_status;
4988 unsigned short b_status;
4989 unsigned int ai_mite_status = 0;
4990 unsigned int ao_mite_status = 0;
4991 unsigned long flags;
4992#ifdef PCIDMA
00b14b1d 4993 struct ni_private *devpriv = dev->private;
c75527fb
HS		 4994 struct mite_struct *mite = devpriv->mite;
4995#endif
4996
4997 if (!dev->attached)
4998 return IRQ_NONE;
4999 smp_mb(); /* make sure dev->attached is checked before handler does anything else. */
5000
5001 /* lock to avoid race with comedi_poll */
5002 spin_lock_irqsave(&dev->spinlock, flags);
7b14fffd 5003 a_status = ni_stc_readw(dev, NISTC_AI_STATUS1_REG);
d123ee3c 5004 b_status = ni_stc_readw(dev, NISTC_AO_STATUS1_REG);
c75527fb
HS		 5005#ifdef PCIDMA
5006 if (mite) {
00b14b1d 5007 struct ni_private *devpriv = dev->private;
c75527fb
HS		 5008 unsigned long flags_too;
5009
5010 spin_lock_irqsave(&devpriv->mite_channel_lock, flags_too);
5011 if (devpriv->ai_mite_chan) {
5012 ai_mite_status = mite_get_status(devpriv->ai_mite_chan);
5013 if (ai_mite_status & CHSR_LINKC)
5014 writel(CHOR_CLRLC,
5015 devpriv->mite->mite_io_addr +
5016 MITE_CHOR(devpriv->
5017 ai_mite_chan->channel));
5018 }
5019 if (devpriv->ao_mite_chan) {
5020 ao_mite_status = mite_get_status(devpriv->ao_mite_chan);
5021 if (ao_mite_status & CHSR_LINKC)
5022 writel(CHOR_CLRLC,
5023 mite->mite_io_addr +
5024 MITE_CHOR(devpriv->
5025 ao_mite_chan->channel));
5026 }
5027 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags_too);
5028 }
5029#endif
5030 ack_a_interrupt(dev, a_status);
5031 ack_b_interrupt(dev, b_status);
7b14fffd 5032 if ((a_status & NISTC_AI_STATUS1_INTA) || (ai_mite_status & CHSR_INT))
c75527fb 5033 handle_a_interrupt(dev, a_status, ai_mite_status);
d123ee3c 5034 if ((b_status & NISTC_AO_STATUS1_INTB) || (ao_mite_status & CHSR_INT))
c75527fb
HS		 5035 handle_b_interrupt(dev, b_status, ao_mite_status);
5036 handle_gpct_interrupt(dev, 0);
5037 handle_gpct_interrupt(dev, 1);
5038 handle_cdio_interrupt(dev);
5039
5040 spin_unlock_irqrestore(&dev->spinlock, flags);
5041 return IRQ_HANDLED;
5042}
5043
2832b183
HS		 5044static int ni_alloc_private(struct comedi_device *dev)
5045{
5046 struct ni_private *devpriv;
5047
5048 devpriv = comedi_alloc_devpriv(dev, sizeof(*devpriv));
5049 if (!devpriv)
5050 return -ENOMEM;
5051
5052 spin_lock_init(&devpriv->window_lock);
5053 spin_lock_init(&devpriv->soft_reg_copy_lock);
5054 spin_lock_init(&devpriv->mite_channel_lock);
5055
5056 return 0;
5057}
5058
1fa955ba
HS		 5059static int ni_E_init(struct comedi_device *dev,
5060 unsigned interrupt_pin, unsigned irq_polarity)
03aef4b6 5061{
7cf94adc 5062 const struct ni_board_struct *board = dev->board_ptr;
0e05c552 5063 struct ni_private *devpriv = dev->private;
34c43922 5064 struct comedi_subdevice *s;
8b6c5694 5065 int ret;
43f2c8b7 5066 int i;
03aef4b6 5067
6293e357 5068 if (board->n_aochan > MAX_N_AO_CHAN) {
89c4695e 5069 dev_err(dev->class_dev, "bug! n_aochan > MAX_N_AO_CHAN\n");
03aef4b6
DS		 5070 return -EINVAL;
5071 }
5072
caedecfa 5073 /* initialize clock dividers */
a47fc02b
HS		 5074 devpriv->clock_and_fout = NISTC_CLK_FOUT_SLOW_DIV2 |
5075 NISTC_CLK_FOUT_SLOW_TIMEBASE |
5076 NISTC_CLK_FOUT_TO_BOARD_DIV2 |
5077 NISTC_CLK_FOUT_TO_BOARD;
caedecfa
HS		 5078 if (!devpriv->is_6xxx) {
5079 /* BEAM is this needed for PCI-6143 ?? */
a47fc02b
HS		 5080 devpriv->clock_and_fout |= (NISTC_CLK_FOUT_AI_OUT_DIV2 |
5081 NISTC_CLK_FOUT_AO_OUT_DIV2);
caedecfa 5082 }
a47fc02b 5083 ni_stc_writew(dev, devpriv->clock_and_fout, NISTC_CLK_FOUT_REG);
caedecfa 5084
8b6c5694
HS		 5085 ret = comedi_alloc_subdevices(dev, NI_NUM_SUBDEVICES);
5086 if (ret)
5087 return ret;
03aef4b6 5088
a06500b4 5089 /* Analog Input subdevice */
f9cd92eb 5090 s = &dev->subdevices[NI_AI_SUBDEV];
6293e357 5091 if (board->n_adchan) {
a06500b4
HS		 5092 s->type = COMEDI_SUBD_AI;
5093 s->subdev_flags = SDF_READABLE | SDF_DIFF | SDF_DITHER;
a52b53e4 5094 if (!devpriv->is_611x)
a06500b4 5095 s->subdev_flags |= SDF_GROUND | SDF_COMMON | SDF_OTHER;
db2255f5 5096 if (board->ai_maxdata > 0xffff)
a06500b4 5097 s->subdev_flags |= SDF_LSAMPL;
17733219 5098 if (devpriv->is_m_series)
a06500b4
HS		 5099 s->subdev_flags |= SDF_SOFT_CALIBRATED;
5100 s->n_chan = board->n_adchan;
5101 s->maxdata = board->ai_maxdata;
5102 s->range_table = ni_range_lkup[board->gainlkup];
5103 s->insn_read = ni_ai_insn_read;
5104 s->insn_config = ni_ai_insn_config;
5105 if (dev->irq) {
5106 dev->read_subdev = s;
5107 s->subdev_flags |= SDF_CMD_READ;
5108 s->len_chanlist = 512;
5109 s->do_cmdtest = ni_ai_cmdtest;
5110 s->do_cmd = ni_ai_cmd;
5111 s->cancel = ni_ai_reset;
5112 s->poll = ni_ai_poll;
5113 s->munge = ni_ai_munge;
5114
5115 if (devpriv->mite)
5116 s->async_dma_dir = DMA_FROM_DEVICE;
5117 }
eeca0caa
HS		 5118
5119 /* reset the analog input configuration */
5120 ni_ai_reset(dev, s);
03aef4b6 5121 } else {
a06500b4 5122 s->type = COMEDI_SUBD_UNUSED;
03aef4b6
DS		 5123 }
5124
80a94e40 5125 /* Analog Output subdevice */
f9cd92eb 5126 s = &dev->subdevices[NI_AO_SUBDEV];
6293e357 5127 if (board->n_aochan) {
80a94e40
HS		 5128 s->type = COMEDI_SUBD_AO;
5129 s->subdev_flags = SDF_WRITABLE | SDF_DEGLITCH | SDF_GROUND;
17733219 5130 if (devpriv->is_m_series)
80a94e40
HS		 5131 s->subdev_flags |= SDF_SOFT_CALIBRATED;
5132 s->n_chan = board->n_aochan;
5133 s->maxdata = board->ao_maxdata;
5134 s->range_table = board->ao_range_table;
80a94e40 5135 s->insn_config = ni_ao_insn_config;
b6d977e9 5136 s->insn_write = ni_ao_insn_write;
b6d977e9
HS		 5137
5138 ret = comedi_alloc_subdev_readback(s);
5139 if (ret)
5140 return ret;
80a94e40
HS		 5141
5142 /*
5143 * Along with the IRQ we need either a FIFO or DMA for
5144 * async command support.
5145 */
5146 if (dev->irq && (board->ao_fifo_depth || devpriv->mite)) {
03aef4b6 5147 dev->write_subdev = s;
80a94e40
HS		 5148 s->subdev_flags |= SDF_CMD_WRITE;
5149 s->len_chanlist = s->n_chan;
5150 s->do_cmdtest = ni_ao_cmdtest;
5151 s->do_cmd = ni_ao_cmd;
5152 s->cancel = ni_ao_reset;
17733219 5153 if (!devpriv->is_m_series)
80a94e40
HS		 5154 s->munge = ni_ao_munge;
5155
5156 if (devpriv->mite)
5157 s->async_dma_dir = DMA_TO_DEVICE;
03aef4b6 5158 }
80a94e40
HS		 5159
5160 if (devpriv->is_67xx)
5161 init_ao_67xx(dev, s);
eeca0caa
HS		 5162
5163 /* reset the analog output configuration */
5164 ni_ao_reset(dev, s);
03aef4b6 5165 } else {
80a94e40 5166 s->type = COMEDI_SUBD_UNUSED;
03aef4b6 5167 }
03aef4b6 5168
2d4ecc38 5169 /* Digital I/O subdevice */
f9cd92eb 5170 s = &dev->subdevices[NI_DIO_SUBDEV];
2d4ecc38
HS		 5171 s->type = COMEDI_SUBD_DIO;
5172 s->subdev_flags = SDF_WRITABLE | SDF_READABLE;
5173 s->n_chan = board->has_32dio_chan ? 32 : 8;
5174 s->maxdata = 1;
5175 s->range_table = &range_digital;
17733219 5176 if (devpriv->is_m_series) {
2d4ecc38
HS		 5177 s->subdev_flags |= SDF_LSAMPL;
5178 s->insn_bits = ni_m_series_dio_insn_bits;
5179 s->insn_config = ni_m_series_dio_insn_config;
5180 if (dev->irq) {
5181 s->subdev_flags |= SDF_CMD_WRITE /* | SDF_CMD_READ */;
5182 s->len_chanlist = s->n_chan;
5183 s->do_cmdtest = ni_cdio_cmdtest;
5184 s->do_cmd = ni_cdio_cmd;
5185 s->cancel = ni_cdio_cancel;
03aef4b6 5186
2d4ecc38
HS		 5187 /* M-series boards use DMA */
5188 s->async_dma_dir = DMA_BIDIRECTIONAL;
5189 }
5190
5191 /* reset DIO and set all channels to inputs */
3c3eb8ea
HS		 5192 ni_writel(dev, NI_M_CDO_CMD_RESET |
5193 NI_M_CDI_CMD_RESET,
975b6d25
HS		 5194 NI_M_CDIO_CMD_REG);
5195 ni_writel(dev, s->io_bits, NI_M_DIO_DIR_REG);
03aef4b6 5196 } else {
2d4ecc38
HS		 5197 s->insn_bits = ni_dio_insn_bits;
5198 s->insn_config = ni_dio_insn_config;
5199
5200 /* set all channels to inputs */
59a97c3c
HS		 5201 devpriv->dio_control = NISTC_DIO_CTRL_DIR(s->io_bits);
5202 ni_writew(dev, devpriv->dio_control, NISTC_DIO_CTRL_REG);
03aef4b6
DS		 5203 }
5204
5205 /* 8255 device */
f9cd92eb 5206 s = &dev->subdevices[NI_8255_DIO_SUBDEV];
e6439a45 5207 if (board->has_8255) {
61260f58
HS		 5208 ret = subdev_8255_init(dev, s, ni_8255_callback,
5209 NI_E_8255_BASE);
e6439a45
HS		 5210 if (ret)
5211 return ret;
5212 } else {
03aef4b6 5213 s->type = COMEDI_SUBD_UNUSED;
e6439a45 5214 }
03aef4b6
DS		 5215
5216 /* formerly general purpose counter/timer device, but no longer used */
f9cd92eb 5217 s = &dev->subdevices[NI_UNUSED_SUBDEV];
03aef4b6
DS		 5218 s->type = COMEDI_SUBD_UNUSED;
5219
cb429506 5220 /* Calibration subdevice */
f9cd92eb 5221 s = &dev->subdevices[NI_CALIBRATION_SUBDEV];
cb429506
HS		 5222 s->type = COMEDI_SUBD_CALIB;
5223 s->subdev_flags = SDF_INTERNAL;
5224 s->n_chan = 1;
5225 s->maxdata = 0;
17733219 5226 if (devpriv->is_m_series) {
cb429506
HS		 5227 /* internal PWM output used for AI nonlinearity calibration */
5228 s->insn_config = ni_m_series_pwm_config;
5229
975b6d25 5230 ni_writel(dev, 0x0, NI_M_CAL_PWM_REG);
a52b53e4 5231 } else if (devpriv->is_6143) {
cb429506
HS		 5232 /* internal PWM output used for AI nonlinearity calibration */
5233 s->insn_config = ni_6143_pwm_config;
03aef4b6 5234 } else {
cb429506
HS		 5235 s->subdev_flags |= SDF_WRITABLE;
5236 s->insn_read = ni_calib_insn_read;
5237 s->insn_write = ni_calib_insn_write;
5238
5239 /* setup the caldacs and find the real n_chan and maxdata */
03aef4b6
DS		 5240 caldac_setup(dev, s);
5241 }
5242
433c79f9 5243 /* EEPROM subdevice */
f9cd92eb 5244 s = &dev->subdevices[NI_EEPROM_SUBDEV];
433c79f9
HS		 5245 s->type = COMEDI_SUBD_MEMORY;
5246 s->subdev_flags = SDF_READABLE | SDF_INTERNAL;
5247 s->maxdata = 0xff;
17733219 5248 if (devpriv->is_m_series) {
433c79f9
HS		 5249 s->n_chan = M_SERIES_EEPROM_SIZE;
5250 s->insn_read = ni_m_series_eeprom_insn_read;
03aef4b6 5251 } else {
433c79f9
HS		 5252 s->n_chan = 512;
5253 s->insn_read = ni_eeprom_insn_read;
03aef4b6
DS		 5254 }
5255
43f2c8b7 5256 /* Digital I/O (PFI) subdevice */
f9cd92eb 5257 s = &dev->subdevices[NI_PFI_DIO_SUBDEV];
43f2c8b7
HS		 5258 s->type = COMEDI_SUBD_DIO;
5259 s->subdev_flags = SDF_READABLE | SDF_WRITABLE | SDF_INTERNAL;
5260 s->maxdata = 1;
17733219 5261 if (devpriv->is_m_series) {
43f2c8b7
HS		 5262 s->n_chan = 16;
5263 s->insn_bits = ni_pfi_insn_bits;
5264
975b6d25 5265 ni_writew(dev, s->state, NI_M_PFI_DO_REG);
03aef4b6 5266 for (i = 0; i < NUM_PFI_OUTPUT_SELECT_REGS; ++i) {
5a92cac5 5267 ni_writew(dev, devpriv->pfi_output_select_reg[i],
975b6d25 5268 NI_M_PFI_OUT_SEL_REG(i));
03aef4b6
DS		 5269 }
5270 } else {
43f2c8b7 5271 s->n_chan = 10;
03aef4b6 5272 }
43f2c8b7
HS		 5273 s->insn_config = ni_pfi_insn_config;
5274
5ecadf8c 5275 ni_set_bits(dev, NISTC_IO_BIDIR_PIN_REG, ~0, 0);
03aef4b6
DS		 5276
5277 /* cs5529 calibration adc */
f9cd92eb 5278 s = &dev->subdevices[NI_CS5529_CALIBRATION_SUBDEV];
a52b53e4 5279 if (devpriv->is_67xx) {
03aef4b6
DS		 5280 s->type = COMEDI_SUBD_AI;
5281 s->subdev_flags = SDF_READABLE | SDF_DIFF | SDF_INTERNAL;
2696fb57 5282 /* one channel for each analog output channel */
6293e357 5283 s->n_chan = board->n_aochan;
03aef4b6
DS		 5284 s->maxdata = (1 << 16) - 1;
5285 s->range_table = &range_unknown; /* XXX */
5286 s->insn_read = cs5529_ai_insn_read;
5287 s->insn_config = NULL;
5288 init_cs5529(dev);
5289 } else {
5290 s->type = COMEDI_SUBD_UNUSED;
5291 }
5292
5293 /* Serial */
f9cd92eb 5294 s = &dev->subdevices[NI_SERIAL_SUBDEV];
03aef4b6
DS		 5295 s->type = COMEDI_SUBD_SERIAL;
5296 s->subdev_flags = SDF_READABLE | SDF_WRITABLE | SDF_INTERNAL;
5297 s->n_chan = 1;
5298 s->maxdata = 0xff;
5299 s->insn_config = ni_serial_insn_config;
5300 devpriv->serial_interval_ns = 0;
5301 devpriv->serial_hw_mode = 0;
5302
5303 /* RTSI */
f9cd92eb 5304 s = &dev->subdevices[NI_RTSI_SUBDEV];
03aef4b6
DS		 5305 s->type = COMEDI_SUBD_DIO;
5306 s->subdev_flags = SDF_READABLE | SDF_WRITABLE | SDF_INTERNAL;
5307 s->n_chan = 8;
5308 s->maxdata = 1;
5309 s->insn_bits = ni_rtsi_insn_bits;
5310 s->insn_config = ni_rtsi_insn_config;
5311 ni_rtsi_init(dev);
5312
c607b331 5313 /* allocate and initialize the gpct counter device */
03aef4b6 5314 devpriv->counter_dev = ni_gpct_device_construct(dev,
c607b331
HS		 5315 ni_gpct_write_register,
5316 ni_gpct_read_register,
5317 (devpriv->is_m_series)
5318 ? ni_gpct_variant_m_series
5319 : ni_gpct_variant_e_series,
5320 NUM_GPCT);
c095fad3
KAM		 5321 if (!devpriv->counter_dev)
5322 return -ENOMEM;
5323
c607b331 5324 /* Counter (gpct) subdevices */
43f2c8b7 5325 for (i = 0; i < NUM_GPCT; ++i) {
c607b331
HS		 5326 struct ni_gpct *gpct = &devpriv->counter_dev->counters[i];
5327
5328 /* setup and initialize the counter */
5329 gpct->chip_index = 0;
5330 gpct->counter_index = i;
5331 ni_tio_init_counter(gpct);
5332
43f2c8b7 5333 s = &dev->subdevices[NI_GPCT_SUBDEV(i)];
c607b331
HS		 5334 s->type = COMEDI_SUBD_COUNTER;
5335 s->subdev_flags = SDF_READABLE | SDF_WRITABLE | SDF_LSAMPL;
5336 s->n_chan = 3;
5337 s->maxdata = (devpriv->is_m_series) ? 0xffffffff
5338 : 0x00ffffff;
5339 s->insn_read = ni_tio_insn_read;
5340 s->insn_write = ni_tio_insn_read;
5341 s->insn_config = ni_tio_insn_config;
bd304a73 5342#ifdef PCIDMA
c607b331
HS		 5343 if (dev->irq && devpriv->mite) {
5344 s->subdev_flags |= SDF_CMD_READ /* | SDF_CMD_WRITE */;
5345 s->len_chanlist = 1;
5346 s->do_cmdtest = ni_tio_cmdtest;
5347 s->do_cmd = ni_gpct_cmd;
5348 s->cancel = ni_gpct_cancel;
03aef4b6 5349
c607b331
HS		 5350 s->async_dma_dir = DMA_BIDIRECTIONAL;
5351 }
5352#endif
5353 s->private = gpct;
03aef4b6
DS		 5354 }
5355
4168ac9d 5356 /* Frequency output subdevice */
f9cd92eb 5357 s = &dev->subdevices[NI_FREQ_OUT_SUBDEV];
4168ac9d
HS		 5358 s->type = COMEDI_SUBD_COUNTER;
5359 s->subdev_flags = SDF_READABLE | SDF_WRITABLE;
5360 s->n_chan = 1;
5361 s->maxdata = 0xf;
5362 s->insn_read = ni_freq_out_insn_read;
5363 s->insn_write = ni_freq_out_insn_write;
5364 s->insn_config = ni_freq_out_insn_config;
03aef4b6 5365
03aef4b6 5366 if (dev->irq) {
00b14b1d 5367 ni_stc_writew(dev,
d8f62c46
HS		 5368 (irq_polarity ? NISTC_INT_CTRL_INT_POL : 0) |
5369 (NISTC_INT_CTRL_3PIN_INT & 0) |
5370 NISTC_INT_CTRL_INTA_ENA |
5371 NISTC_INT_CTRL_INTB_ENA |
5372 NISTC_INT_CTRL_INTA_SEL(interrupt_pin) |
5373 NISTC_INT_CTRL_INTB_SEL(interrupt_pin),
5374 NISTC_INT_CTRL_REG);
03aef4b6
DS		 5375 }
5376
5377 /* DMA setup */
5a92cac5
HS		 5378 ni_writeb(dev, devpriv->ai_ao_select_reg, AI_AO_Select);
5379 ni_writeb(dev, devpriv->g0_g1_select_reg, G0_G1_Select);
03aef4b6 5380
a52b53e4 5381 if (devpriv->is_6xxx) {
5a92cac5 5382 ni_writeb(dev, 0, Magic_611x);
17733219 5383 } else if (devpriv->is_m_series) {
03aef4b6 5384 int channel;
f7401979 5385
6293e357 5386 for (channel = 0; channel < board->n_aochan; ++channel) {
5a92cac5 5387 ni_writeb(dev, 0xf,
975b6d25 5388 NI_M_AO_WAVEFORM_ORDER_REG(channel));
5a92cac5 5389 ni_writeb(dev, 0x0,
975b6d25 5390 NI_M_AO_REF_ATTENUATION_REG(channel));
03aef4b6 5391 }
975b6d25 5392 ni_writeb(dev, 0x0, NI_M_AO_CALIB_REG);
03aef4b6
DS		 5393 }
5394
03aef4b6
DS		 5395 return 0;
5396}
2832b183
HS		 5397
5398static void mio_common_detach(struct comedi_device *dev)
5399{
5400 struct ni_private *devpriv = dev->private;
5401
5402 if (devpriv) {
5403 if (devpriv->counter_dev)
5404 ni_gpct_device_destroy(devpriv->counter_dev);
5405 }
5406}
Linux kernel - Deliverables
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