projects / deliverable / linux.git / blame
| Commit | Line | Data |
|---|---|---|
| e554840c MK |
1 | /* |
| 2 | * plx9080.h | |
| 3d9f0739 DC |
3 | * |
| 4 | * Copyright (C) 2002,2003 Frank Mori Hess <fmhess@users.sourceforge.net> | |
| 5 | * | |
| 3d9f0739 DC |
6 | ******************************************************************** |
| 7 | * | |
| 631dd1a8 | 8 | * Copyright (C) 1999 RG Studio s.c. |
| 3d9f0739 DC |
9 | * Written by Krzysztof Halasa <khc@rgstudio.com.pl> |
| 10 | * | |
| 11 | * Portions (C) SBE Inc., used by permission. | |
| 12 | * | |
| 13 | * This program is free software; you can redistribute it and/or | |
| 14 | * modify it under the terms of the GNU General Public License | |
| 15 | * as published by the Free Software Foundation; either version | |
| 16 | * 2 of the License, or (at your option) any later version. | |
| 17 | */ | |
| 18 | ||
| 19 | #ifndef __COMEDI_PLX9080_H | |
| 20 | #define __COMEDI_PLX9080_H | |
| 21 | ||
| 52caeb4a IA |
22 | #include <linux/compiler.h> |
| 23 | #include <linux/types.h> | |
| 24 | #include <linux/bitops.h> | |
| 25 | #include <linux/delay.h> | |
| 26 | #include <linux/errno.h> | |
| 27 | #include <linux/io.h> | |
| 28 | ||
| 6a64877f IA |
29 | /** |
| 30 | * struct plx_dma_desc - DMA descriptor format for PLX PCI 9080 | |
| 31 | * @pci_start_addr: PCI Bus address for transfer (DMAPADR). | |
| 32 | * @local_start_addr: Local Bus address for transfer (DMALADR). | |
| 33 | * @transfer_size: Transfer size in bytes (max 8 MiB) (DMASIZ). | |
| 34 | * @next: Address of next descriptor + flags (DMADPR). | |
| 35 | * | |
| 36 | * Describes the format of a scatter-gather DMA descriptor for the PLX | |
| 37 | * PCI 9080. All members are raw, little-endian register values that | |
| 38 | * will be transferred by the DMA engine from local or PCI memory into | |
| 39 | * corresponding registers for the DMA channel. | |
| 40 | * | |
| 41 | * The DMA descriptors must be aligned on a 16-byte boundary. Bits 3:0 | |
| 42 | * of @next contain flags describing the address space of the next | |
| 43 | * descriptor (local or PCI), an "end of chain" marker, an "interrupt on | |
| 44 | * terminal count" bit, and a data transfer direction. | |
| 45 | */ | |
| 3d9f0739 | 46 | struct plx_dma_desc { |
| 5c7895c0 HS |
47 | __le32 pci_start_addr; |
| 48 | __le32 local_start_addr; | |
| 5c7895c0 | 49 | __le32 transfer_size; |
| 5c7895c0 | 50 | __le32 next; |
| 3d9f0739 DC |
51 | }; |
| 52 | ||
| 457bec0f IA |
53 | /* |
| 54 | * Register Offsets and Bit Definitions | |
| 55 | */ | |
| 3d9f0739 | 56 | |
| c644a11a IA |
57 | /* Local Address Space 0 Range Register */ |
| 58 | #define PLX_REG_LAS0RR 0x0000 | |
| 59 | /* Local Address Space 1 Range Register */ | |
| 60 | #define PLX_REG_LAS1RR 0x00f0 | |
| 61 | ||
| be13e14e | 62 | #define PLX_LASRR_IO BIT(0) /* Map to: 1=I/O, 0=Mem */ |
| 686869b4 IA |
63 | #define PLX_LASRR_MLOC_ANY32 (BIT(1) * 0) /* Locate anywhere in 32 bit */ |
| 64 | #define PLX_LASRR_MLOC_LT1MB (BIT(1) * 1) /* Locate in 1st meg */ | |
| 65 | #define PLX_LASRR_MLOC_ANY64 (BIT(1) * 2) /* Locate anywhere in 64 bit */ | |
| be13e14e IA |
66 | #define PLX_LASRR_MLOC_MASK GENMASK(2, 1) /* Memory location bits */ |
| 67 | #define PLX_LASRR_PREFETCH BIT(3) /* Memory is prefetchable */ | |
| 68 | /* bits that specify range for memory space decode bits */ | |
| 69 | #define PLX_LASRR_MEM_MASK GENMASK(31, 4) | |
| 70 | /* bits that specify range for i/o space decode bits */ | |
| 71 | #define PLX_LASRR_IO_MASK GENMASK(31, 2) | |
| c644a11a IA |
72 | |
| 73 | /* Local Address Space 0 Local Base Address (Remap) Register */ | |
| 74 | #define PLX_REG_LAS0BA 0x0004 | |
| 75 | /* Local Address Space 1 Local Base Address (Remap) Register */ | |
| 76 | #define PLX_REG_LAS1BA 0x00f4 | |
| 77 | ||
| 5eaa593d IA |
78 | #define PLX_LASBA_EN BIT(0) /* Enable slave decode */ |
| 79 | /* bits that specify local base address for memory space */ | |
| 80 | #define PLX_LASBA_MEM_MASK GENMASK(31, 4) | |
| 81 | /* bits that specify local base address for i/o space */ | |
| 82 | #define PLX_LASBA_IO_MASK GENMASK(31, 2) | |
| 3d9f0739 | 83 | |
| c644a11a IA |
84 | /* Mode/Arbitration Register */ |
| 85 | #define PLX_REG_MARBR 0x0008 | |
| 86 | /* DMA Arbitration Register (alias of MARBR). */ | |
| 87 | #define PLX_REG_DMAARB 0x00ac | |
| 88 | ||
| b5dcdcea IA |
89 | /* Local Bus Latency Timer */ |
| 90 | #define PLX_MARBR_LT(x) (BIT(0) * ((x) & 0xff)) | |
| 91 | #define PLX_MARBR_LT_MASK GENMASK(7, 0) | |
| 6ad124d5 | 92 | #define PLX_MARBR_TO_LT(r) ((r) & PLX_MARBR_LT_MASK) |
| b5dcdcea IA |
93 | /* Local Bus Pause Timer */ |
| 94 | #define PLX_MARBR_PT(x) (BIT(8) * ((x) & 0xff)) | |
| 95 | #define PLX_MARBR_PT_MASK GENMASK(15, 8) | |
| 6ad124d5 | 96 | #define PLX_MARBR_TO_PT(r) (((r) & PLX_MARBR_PT_MASK) >> 8) |
| b5dcdcea IA |
97 | /* Local Bus Latency Timer Enable */ |
| 98 | #define PLX_MARBR_LTEN BIT(16) | |
| 99 | /* Local Bus Pause Timer Enable */ | |
| 100 | #define PLX_MARBR_PTEN BIT(17) | |
| 101 | /* Local Bus BREQ Enable */ | |
| 102 | #define PLX_MARBR_BREQEN BIT(18) | |
| 103 | /* DMA Channel Priority */ | |
| 104 | #define PLX_MARBR_PRIO_ROT (BIT(19) * 0) /* Rotational priority */ | |
| 105 | #define PLX_MARBR_PRIO_DMA0 (BIT(19) * 1) /* DMA channel 0 has priority */ | |
| 106 | #define PLX_MARBR_PRIO_DMA1 (BIT(19) * 2) /* DMA channel 1 has priority */ | |
| 107 | #define PLX_MARBR_PRIO_MASK GENMASK(20, 19) | |
| 108 | /* Local Bus Direct Slave Give Up Bus Mode */ | |
| 109 | #define PLX_MARBR_DSGUBM BIT(21) | |
| 110 | /* Direct Slace LLOCKo# Enable */ | |
| 111 | #define PLX_MARBR_DSLLOCKOEN BIT(22) | |
| 112 | /* PCI Request Mode */ | |
| 113 | #define PLX_MARBR_PCIREQM BIT(23) | |
| 114 | /* PCI Specification v2.1 Mode */ | |
| 115 | #define PLX_MARBR_PCIV21M BIT(24) | |
| 116 | /* PCI Read No Write Mode */ | |
| 117 | #define PLX_MARBR_PCIRNWM BIT(25) | |
| 118 | /* PCI Read with Write Flush Mode */ | |
| 119 | #define PLX_MARBR_PCIRWFM BIT(26) | |
| 120 | /* Gate Local Bus Latency Timer with BREQ */ | |
| 121 | #define PLX_MARBR_GLTBREQ BIT(27) | |
| 122 | /* PCI Read No Flush Mode */ | |
| 123 | #define PLX_MARBR_PCIRNFM BIT(28) | |
| 124 | /* | |
| 125 | * Make reads from PCI Configuration register 0 return Subsystem ID and | |
| 126 | * Subsystem Vendor ID instead of Device ID and Vendor ID | |
| 127 | */ | |
| 128 | #define PLX_MARBR_SUBSYSIDS BIT(29) | |
| 3d9f0739 | 129 | |
| c644a11a IA |
130 | /* Big/Little Endian Descriptor Register */ |
| 131 | #define PLX_REG_BIGEND 0x000c | |
| 132 | ||
| a9c254a7 IA |
133 | /* Configuration Register Big Endian Mode */ |
| 134 | #define PLX_BIGEND_CONFIG BIT(0) | |
| 135 | /* Direct Master Big Endian Mode */ | |
| 136 | #define PLX_BIGEND_DM BIT(1) | |
| 137 | /* Direct Slave Address Space 0 Big Endian Mode */ | |
| 138 | #define PLX_BIGEND_DSAS0 BIT(2) | |
| 139 | /* Direct Slave Expansion ROM Big Endian Mode */ | |
| 140 | #define PLX_BIGEND_EROM BIT(3) | |
| 141 | /* Big Endian Byte Lane Mode - use most significant byte lanes */ | |
| 142 | #define PLX_BIGEND_BEBLM BIT(4) | |
| 143 | /* Direct Slave Address Space 1 Big Endian Mode */ | |
| 144 | #define PLX_BIGEND_DSAS1 BIT(5) | |
| 145 | /* DMA Channel 1 Big Endian Mode */ | |
| 146 | #define PLX_BIGEND_DMA1 BIT(6) | |
| 147 | /* DMA Channel 0 Big Endian Mode */ | |
| 148 | #define PLX_BIGEND_DMA0 BIT(7) | |
| 149 | /* DMA Channel N Big Endian Mode (N <= 1) */ | |
| 150 | #define PLX_BIGEND_DMA(n) ((n) ? PLX_BIGEND_DMA1 : PLX_BIGEND_DMA0) | |
| 3d9f0739 | 151 | |
| e554840c | 152 | /* |
| 457bec0f IA |
153 | * Note: The Expansion ROM stuff is only relevant to the PC environment. |
| 154 | * This expansion ROM code is executed by the host CPU at boot time. | |
| 155 | * For this reason no bit definitions are provided here. | |
| e554840c | 156 | */ |
| 457bec0f | 157 | |
| c644a11a IA |
158 | /* Expansion ROM Range Register */ |
| 159 | #define PLX_REG_EROMRR 0x0010 | |
| 160 | /* Expansion ROM Local Base Address (Remap) Register */ | |
| 161 | #define PLX_REG_EROMBA 0x0014 | |
| 162 | ||
| 163 | /* Local Address Space 0/Expansion ROM Bus Region Descriptor Register */ | |
| 164 | #define PLX_REG_LBRD0 0x0018 | |
| 165 | /* Local Address Space 1 Bus Region Descriptor Register */ | |
| 166 | #define PLX_REG_LBRD1 0x00f8 | |
| 3d9f0739 | 167 | |
| 1ddb95d3 | 168 | /* Memory Space Local Bus Width */ |
| 686869b4 IA |
169 | #define PLX_LBRD_MSWIDTH_8 (BIT(0) * 0) /* 8 bits wide */ |
| 170 | #define PLX_LBRD_MSWIDTH_16 (BIT(0) * 1) /* 16 bits wide */ | |
| 171 | #define PLX_LBRD_MSWIDTH_32 (BIT(0) * 2) /* 32 bits wide */ | |
| 172 | #define PLX_LBRD_MSWIDTH_32A (BIT(0) * 3) /* 32 bits wide */ | |
| 1ddb95d3 | 173 | #define PLX_LBRD_MSWIDTH_MASK GENMASK(1, 0) |
| 1ddb95d3 IA |
174 | /* Memory Space Internal Wait States */ |
| 175 | #define PLX_LBRD_MSIWS(x) (BIT(2) * ((x) & 0xf)) | |
| 176 | #define PLX_LBRD_MSIWS_MASK GENMASK(5, 2) | |
| 6ad124d5 | 177 | #define PLX_LBRD_TO_MSIWS(r) (((r) & PLS_LBRD_MSIWS_MASK) >> 2) |
| 1ddb95d3 IA |
178 | /* Memory Space Ready Input Enable */ |
| 179 | #define PLX_LBRD_MSREADYIEN BIT(6) | |
| 180 | /* Memory Space BTERM# Input Enable */ | |
| 181 | #define PLX_LBRD_MSBTERMIEN BIT(7) | |
| 182 | /* Memory Space 0 Prefetch Disable (LBRD0 only) */ | |
| 183 | #define PLX_LBRD0_MSPREDIS BIT(8) | |
| 184 | /* Memory Space 1 Burst Enable (LBRD1 only) */ | |
| 185 | #define PLX_LBRD1_MSBURSTEN BIT(8) | |
| 186 | /* Expansion ROM Space Prefetch Disable (LBRD0 only) */ | |
| 187 | #define PLX_LBRD0_EROMPREDIS BIT(9) | |
| 188 | /* Memory Space 1 Prefetch Disable (LBRD1 only) */ | |
| 189 | #define PLX_LBRD1_MSPREDIS BIT(9) | |
| 190 | /* Read Prefetch Count Enable */ | |
| 191 | #define PLX_LBRD_RPFCOUNTEN BIT(10) | |
| 192 | /* Prefetch Counter */ | |
| 193 | #define PLX_LBRD_PFCOUNT(x) (BIT(11) * ((x) & 0xf)) | |
| 194 | #define PLX_LBRD_PFCOUNT_MASK GENMASK(14, 11) | |
| 6ad124d5 | 195 | #define PLX_LBRD_TO_PFCOUNT(r) (((r) & PLX_LBRD_PFCOUNT_MASK) >> 11) |
| 1ddb95d3 | 196 | /* Expansion ROM Space Local Bus Width (LBRD0 only) */ |
| 686869b4 IA |
197 | #define PLX_LBRD0_EROMWIDTH_8 (BIT(16) * 0) /* 8 bits wide */ |
| 198 | #define PLX_LBRD0_EROMWIDTH_16 (BIT(16) * 1) /* 16 bits wide */ | |
| 199 | #define PLX_LBRD0_EROMWIDTH_32 (BIT(16) * 2) /* 32 bits wide */ | |
| 200 | #define PLX_LBRD0_EROMWIDTH_32A (BIT(16) * 3) /* 32 bits wide */ | |
| 1ddb95d3 | 201 | #define PLX_LBRD0_EROMWIDTH_MASK GENMASK(17, 16) |
| 1ddb95d3 IA |
202 | /* Expansion ROM Space Internal Wait States (LBRD0 only) */ |
| 203 | #define PLX_LBRD0_EROMIWS(x) (BIT(18) * ((x) & 0xf)) | |
| 204 | #define PLX_LBRD0_EROMIWS_MASK GENMASK(21, 18) | |
| 6ad124d5 | 205 | #define PLX_LBRD0_TO_EROMIWS(r) (((r) & PLX_LBRD0_EROMIWS_MASK) >> 18) |
| 1ddb95d3 IA |
206 | /* Expansion ROM Space Ready Input Enable (LBDR0 only) */ |
| 207 | #define PLX_LBRD0_EROMREADYIEN BIT(22) | |
| 208 | /* Expansion ROM Space BTERM# Input Enable (LBRD0 only) */ | |
| 209 | #define PLX_LBRD0_EROMBTERMIEN BIT(23) | |
| 210 | /* Memory Space 0 Burst Enable (LBRD0 only) */ | |
| 211 | #define PLX_LBRD0_MSBURSTEN BIT(24) | |
| 212 | /* Extra Long Load From Serial EEPROM (LBRD0 only) */ | |
| 213 | #define PLX_LBRD0_EELONGLOAD BIT(25) | |
| 214 | /* Expansion ROM Space Burst Enable (LBRD0 only) */ | |
| 215 | #define PLX_LBRD0_EROMBURSTEN BIT(26) | |
| 216 | /* Direct Slave PCI Write Mode - assert TRDY# when FIFO full (LBRD0 only) */ | |
| 217 | #define PLX_LBRD0_DSWMTRDY BIT(27) | |
| 218 | /* PCI Target Retry Delay Clocks / 8 (LBRD0 only) */ | |
| 219 | #define PLX_LBRD0_TRDELAY(x) (BIT(28) * ((x) & 0xF)) | |
| 220 | #define PLX_LBRD0_TRDELAY_MASK GENMASK(31, 28) | |
| 6ad124d5 | 221 | #define PLX_LBRD0_TO_TRDELAY(r) (((r) & PLX_LBRD0_TRDELAY_MASK) >> 28) |
| 3d9f0739 | 222 | |
| c644a11a IA |
223 | /* Local Range Register for Direct Master to PCI */ |
| 224 | #define PLX_REG_DMRR 0x001c | |
| 3d9f0739 | 225 | |
| c644a11a IA |
226 | /* Local Bus Base Address Register for Direct Master to PCI Memory */ |
| 227 | #define PLX_REG_DMLBAM 0x0020 | |
| 3d9f0739 | 228 | |
| c644a11a IA |
229 | /* Local Base Address Register for Direct Master to PCI IO/CFG */ |
| 230 | #define PLX_REG_DMLBAI 0x0024 | |
| 3d9f0739 | 231 | |
| c644a11a IA |
232 | /* PCI Base Address (Remap) Register for Direct Master to PCI Memory */ |
| 233 | #define PLX_REG_DMPBAM 0x0028 | |
| 3d9f0739 | 234 | |
| e0045472 IA |
235 | /* Direct Master Memory Access Enable */ |
| 236 | #define PLX_DMPBAM_MEMACCEN BIT(0) | |
| 237 | /* Direct Master I/O Access Enable */ | |
| 238 | #define PLX_DMPBAM_IOACCEN BIT(1) | |
| 239 | /* LLOCK# Input Enable */ | |
| 240 | #define PLX_DMPBAM_LLOCKIEN BIT(2) | |
| 241 | /* Direct Master Read Prefetch Size Control (bits 12, 3) */ | |
| 686869b4 IA |
242 | #define PLX_DMPBAM_RPSIZE_CONT ((BIT(12) * 0) | (BIT(3) * 0)) |
| 243 | #define PLX_DMPBAM_RPSIZE_4 ((BIT(12) * 0) | (BIT(3) * 1)) | |
| 244 | #define PLX_DMPBAM_RPSIZE_8 ((BIT(12) * 1) | (BIT(3) * 0)) | |
| 245 | #define PLX_DMPBAM_RPSIZE_16 ((BIT(12) * 1) | (BIT(3) * 1)) | |
| e0045472 IA |
246 | #define PLX_DMPBAM_RPSIZE_MASK (BIT(12) | BIT(3)) |
| 247 | /* Direct Master PCI Read Mode - deassert IRDY when FIFO full */ | |
| 248 | #define PLX_DMPBAM_RMIRDY BIT(4) | |
| 249 | /* Programmable Almost Full Level (bits 10, 8:5) */ | |
| 250 | #define PLX_DMPBAM_PAFL(x) ((BIT(10) * !!((x) & 0x10)) | \ | |
| 251 | (BIT(5) * ((x) & 0xf))) | |
| 252 | #define PLX_DMPBAM_TO_PAFL(v) ((((BIT(10) & (v)) >> 1) | \ | |
| 253 | (GENMASK(8, 5) & (v))) >> 5) | |
| 254 | #define PLX_DMPBAM_PAFL_MASK (BIT(10) | GENMASK(8, 5)) | |
| 255 | /* Write And Invalidate Mode */ | |
| 256 | #define PLX_DMPBAM_WIM BIT(9) | |
| 257 | /* Direct Master Prefetch Limit */ | |
| 258 | #define PLX_DBPBAM_PFLIMIT BIT(11) | |
| 259 | /* I/O Remap Select */ | |
| 260 | #define PLX_DMPBAM_IOREMAPSEL BIT(13) | |
| 261 | /* Direct Master Write Delay */ | |
| 686869b4 IA |
262 | #define PLX_DMPBAM_WDELAY_NONE (BIT(14) * 0) |
| 263 | #define PLX_DMPBAM_WDELAY_4 (BIT(14) * 1) | |
| 264 | #define PLX_DMPBAM_WDELAY_8 (BIT(14) * 2) | |
| 265 | #define PLX_DMPBAM_WDELAY_16 (BIT(14) * 3) | |
| e0045472 IA |
266 | #define PLX_DMPBAM_WDELAY_MASK GENMASK(15, 14) |
| 267 | /* Remap of Local-to-PCI Space Into PCI Address Space */ | |
| 268 | #define PLX_DMPBAM_REMAP_MASK GENMASK(31, 16) | |
| 3d9f0739 | 269 | |
| c644a11a IA |
270 | /* PCI Configuration Address Register for Direct Master to PCI IO/CFG */ |
| 271 | #define PLX_REG_DMCFGA 0x002c | |
| 272 | ||
| ed5df5db IA |
273 | /* Congiguration Type */ |
| 274 | #define PLX_DMCFGA_TYPE0 (BIT(0) * 0) | |
| 275 | #define PLX_DMCFGA_TYPE1 (BIT(0) * 1) | |
| 276 | #define PLX_DMCFGA_TYPE_MASK GENMASK(1, 0) | |
| 277 | /* Register Number */ | |
| 278 | #define PLX_DMCFGA_REGNUM(x) (BIT(2) * ((x) & 0x3f)) | |
| 279 | #define PLX_DMCFGA_REGNUM_MASK GENMASK(7, 2) | |
| 6ad124d5 | 280 | #define PLX_DMCFGA_TO_REGNUM(r) (((r) & PLX_DMCFGA_REGNUM_MASK) >> 2) |
| ed5df5db IA |
281 | /* Function Number */ |
| 282 | #define PLX_DMCFGA_FUNCNUM(x) (BIT(8) * ((x) & 0x7)) | |
| 283 | #define PLX_DMCFGA_FUNCNUM_MASK GENMASK(10, 8) | |
| 6ad124d5 | 284 | #define PLX_DMCFGA_TO_FUNCNUM(r) (((r) & PLX_DMCFGA_FUNCNUM_MASK) >> 8) |
| ed5df5db IA |
285 | /* Device Number */ |
| 286 | #define PLX_DMCFGA_DEVNUM(x) (BIT(11) * ((x) & 0x1f)) | |
| 287 | #define PLX_DMCFGA_DEVNUM_MASK GENMASK(15, 11) | |
| 6ad124d5 | 288 | #define PLX_DMCFGA_TO_DEVNUM(r) (((r) & PLX_DMCFGA_DEVNUM_MASK) >> 11) |
| ed5df5db IA |
289 | /* Bus Number */ |
| 290 | #define PLX_DMCFGA_BUSNUM(x) (BIT(16) * ((x) & 0xff)) | |
| 291 | #define PLX_DMCFGA_BUSNUM_MASK GENMASK(23, 16) | |
| 6ad124d5 | 292 | #define PLX_DMCFGA_TO_BUSNUM(r) (((r) & PLX_DMCFGA_BUSNUM_MASK) >> 16) |
| ed5df5db IA |
293 | /* Configuration Enable */ |
| 294 | #define PLX_DMCFGA_CONFIGEN BIT(31) | |
| 3d9f0739 | 295 | |
| c644a11a IA |
296 | /* |
| 297 | * Mailbox Register N (N <= 7) | |
| 298 | * | |
| 299 | * Note that if the I2O feature is enabled (QSR[0] is set), Mailbox Register 0 | |
| 300 | * is replaced by the Inbound Queue Port, and Mailbox Register 1 is replaced | |
| 301 | * by the Outbound Queue Port. However, Mailbox Register 0 and 1 are always | |
| 302 | * accessible at alternative offsets if the I2O feature is enabled. | |
| 303 | */ | |
| 304 | #define PLX_REG_MBOX(n) (0x0040 + (n) * 4) | |
| 305 | #define PLX_REG_MBOX0 PLX_REG_MBOX(0) | |
| 306 | #define PLX_REG_MBOX1 PLX_REG_MBOX(1) | |
| 307 | #define PLX_REG_MBOX2 PLX_REG_MBOX(2) | |
| 308 | #define PLX_REG_MBOX3 PLX_REG_MBOX(3) | |
| 309 | #define PLX_REG_MBOX4 PLX_REG_MBOX(4) | |
| 310 | #define PLX_REG_MBOX5 PLX_REG_MBOX(5) | |
| 311 | #define PLX_REG_MBOX6 PLX_REG_MBOX(6) | |
| 312 | #define PLX_REG_MBOX7 PLX_REG_MBOX(7) | |
| 313 | ||
| 314 | /* Alternative offsets for Mailbox Registers 0 and 1 (in case I2O is enabled) */ | |
| 315 | #define PLX_REG_ALT_MBOX(n) ((n) < 2 ? 0x0078 + (n) * 4 : PLX_REG_MBOX(n)) | |
| 316 | #define PLX_REG_ALT_MBOX0 PLX_REG_ALT_MBOX(0) | |
| 317 | #define PLX_REG_ALT_MBOX1 PLX_REG_ALT_MBOX(1) | |
| 318 | ||
| 319 | /* PCI-to-Local Doorbell Register */ | |
| 320 | #define PLX_REG_P2LDBELL 0x0060 | |
| 321 | ||
| 322 | /* Local-to-PCI Doorbell Register */ | |
| 323 | #define PLX_REG_L2PDBELL 0x0064 | |
| 324 | ||
| 325 | /* Interrupt Control/Status Register */ | |
| 326 | #define PLX_REG_INTCSR 0x0068 | |
| 3d9f0739 | 327 | |
| 9dc53852 IA |
328 | /* Enable Local Bus LSERR# when PCI Bus Target Abort or Master Abort occurs */ |
| 329 | #define PLX_INTCSR_LSEABORTEN BIT(0) | |
| 330 | /* Enable Local Bus LSERR# when PCI parity error occurs */ | |
| 331 | #define PLX_INTCSR_LSEPARITYEN BIT(1) | |
| 332 | /* Generate PCI Bus SERR# when set to 1 */ | |
| 333 | #define PLX_INTCSR_GENSERR BIT(2) | |
| 334 | /* Mailbox Interrupt Enable (local bus interrupts on PCI write to MBOX0-3) */ | |
| 335 | #define PLX_INTCSR_MBIEN BIT(3) | |
| 336 | /* PCI Interrupt Enable */ | |
| 337 | #define PLX_INTCSR_PIEN BIT(8) | |
| 338 | /* PCI Doorbell Interrupt Enable */ | |
| 339 | #define PLX_INTCSR_PDBIEN BIT(9) | |
| 340 | /* PCI Abort Interrupt Enable */ | |
| 341 | #define PLX_INTCSR_PABORTIEN BIT(10) | |
| 342 | /* PCI Local Interrupt Enable */ | |
| 343 | #define PLX_INTCSR_PLIEN BIT(11) | |
| 344 | /* Retry Abort Enable (for diagnostic purposes only) */ | |
| 345 | #define PLX_INTCSR_RAEN BIT(12) | |
| 346 | /* PCI Doorbell Interrupt Active (read-only) */ | |
| 347 | #define PLX_INTCSR_PDBIA BIT(13) | |
| 348 | /* PCI Abort Interrupt Active (read-only) */ | |
| 349 | #define PLX_INTCSR_PABORTIA BIT(14) | |
| 350 | /* Local Interrupt (LINTi#) Active (read-only) */ | |
| 351 | #define PLX_INTCSR_PLIA BIT(15) | |
| 352 | /* Local Interrupt Output (LINTo#) Enable */ | |
| 353 | #define PLX_INTCSR_LIOEN BIT(16) | |
| 354 | /* Local Doorbell Interrupt Enable */ | |
| 355 | #define PLX_INTCSR_LDBIEN BIT(17) | |
| 356 | /* DMA Channel 0 Interrupt Enable */ | |
| 357 | #define PLX_INTCSR_DMA0IEN BIT(18) | |
| 358 | /* DMA Channel 1 Interrupt Enable */ | |
| 359 | #define PLX_INTCSR_DMA1IEN BIT(19) | |
| 360 | /* DMA Channel N Interrupt Enable (N <= 1) */ | |
| 361 | #define PLX_INTCSR_DMAIEN(n) ((n) ? PLX_INTCSR_DMA1IEN : PLX_INTCSR_DMA0IEN) | |
| 362 | /* Local Doorbell Interrupt Active (read-only) */ | |
| 363 | #define PLX_INTCSR_LDBIA BIT(20) | |
| 364 | /* DMA Channel 0 Interrupt Active (read-only) */ | |
| 365 | #define PLX_INTCSR_DMA0IA BIT(21) | |
| 366 | /* DMA Channel 1 Interrupt Active (read-only) */ | |
| 367 | #define PLX_INTCSR_DMA1IA BIT(22) | |
| 368 | /* DMA Channel N Interrupt Active (N <= 1) (read-only) */ | |
| 369 | #define PLX_INTCSR_DMAIA(n) ((n) ? PLX_INTCSR_DMA1IA : PLX_INTCSR_DMA0IA) | |
| 370 | /* BIST Interrupt Active (read-only) */ | |
| 371 | #define PLX_INTCSR_BISTIA BIT(23) | |
| 372 | /* Direct Master Not Bus Master During Master Or Target Abort (read-only) */ | |
| 373 | #define PLX_INTCSR_ABNOTDM BIT(24) | |
| 374 | /* DMA Channel 0 Not Bus Master During Master Or Target Abort (read-only) */ | |
| 375 | #define PLX_INTCSR_ABNOTDMA0 BIT(25) | |
| 376 | /* DMA Channel 1 Not Bus Master During Master Or Target Abort (read-only) */ | |
| 377 | #define PLX_INTCSR_ABNOTDMA1 BIT(26) | |
| 378 | /* DMA Channel N Not Bus Master During Master Or Target Abort (read-only) */ | |
| 379 | #define PLX_INTCSR_ABNOTDMA(n) ((n) ? PLX_INTCSR_ABNOTDMA1 \ | |
| 380 | : PLX_INTCSR_ABNOTDMA0) | |
| 381 | /* Target Abort Not Generated After 256 Master Retries (read-only) */ | |
| 382 | #define PLX_INTCSR_ABNOTRETRY BIT(27) | |
| 383 | /* PCI Wrote Mailbox 0 (enabled if bit 3 set) (read-only) */ | |
| 384 | #define PLX_INTCSR_MB0IA BIT(28) | |
| 385 | /* PCI Wrote Mailbox 1 (enabled if bit 3 set) (read-only) */ | |
| 386 | #define PLX_INTCSR_MB1IA BIT(29) | |
| 387 | /* PCI Wrote Mailbox 2 (enabled if bit 3 set) (read-only) */ | |
| 388 | #define PLX_INTCSR_MB2IA BIT(30) | |
| 389 | /* PCI Wrote Mailbox 3 (enabled if bit 3 set) (read-only) */ | |
| 390 | #define PLX_INTCSR_MB3IA BIT(31) | |
| 391 | /* PCI Wrote Mailbox N (N <= 3) (enabled if bit 3 set) (read-only) */ | |
| 392 | #define PLX_INTCSR_MBIA(n) BIT(28 + (n)) | |
| 3d9f0739 | 393 | |
| c644a11a IA |
394 | /* |
| 395 | * Serial EEPROM Control, PCI Command Codes, User I/O Control, | |
| 396 | * Init Control Register | |
| 397 | */ | |
| 398 | #define PLX_REG_CNTRL 0x006c | |
| 399 | ||
| a3228bc8 IA |
400 | /* PCI Read Command Code For DMA */ |
| 401 | #define PLX_CNTRL_CCRDMA(x) (BIT(0) * ((x) & 0xf)) | |
| 402 | #define PLX_CNTRL_CCRDMA_MASK GENMASK(3, 0) | |
| 6ad124d5 | 403 | #define PLX_CNTRL_TO_CCRDMA(r) ((r) & PLX_CNTRL_CCRDMA_MASK) |
| a3228bc8 IA |
404 | #define PLX_CNTRL_CCRDMA_NORMAL PLX_CNTRL_CCRDMA(14) /* value after reset */ |
| 405 | /* PCI Write Command Code For DMA 0 */ | |
| 406 | #define PLX_CNTRL_CCWDMA(x) (BIT(4) * ((x) & 0xf)) | |
| 407 | #define PLX_CNTRL_CCWDMA_MASK GENMASK(7, 4) | |
| 6ad124d5 | 408 | #define PLX_CNTRL_TO_CCWDMA(r) (((r) & PLX_CNTRL_CCWDMA_MASK) >> 4) |
| a3228bc8 IA |
409 | #define PLX_CNTRL_CCWDMA_NORMAL PLX_CNTRL_CCWDMA(7) /* value after reset */ |
| 410 | /* PCI Memory Read Command Code For Direct Master */ | |
| 411 | #define PLX_CNTRL_CCRDM(x) (BIT(8) * ((x) & 0xf)) | |
| 412 | #define PLX_CNTRL_CCRDM_MASK GENMASK(11, 8) | |
| 6ad124d5 | 413 | #define PLX_CNTRL_TO_CCRDM(r) (((r) & PLX_CNTRL_CCRDM_MASK) >> 8) |
| a3228bc8 IA |
414 | #define PLX_CNTRL_CCRDM_NORMAL PLX_CNTRL_CCRDM(6) /* value after reset */ |
| 415 | /* PCI Memory Write Command Code For Direct Master */ | |
| 416 | #define PLX_CNTRL_CCWDM(x) (BIT(12) * ((x) & 0xf)) | |
| 417 | #define PLX_CNTRL_CCWDM_MASK GENMASK(15, 12) | |
| 6ad124d5 | 418 | #define PLX_CNTRL_TO_CCWDM(r) (((r) & PLX_CNTRL_CCWDM_MASK) >> 12) |
| a3228bc8 IA |
419 | #define PLX_CNTRL_CCWDM_NORMAL PLX_CNTRL_CCWDM(7) /* value after reset */ |
| 420 | /* General Purpose Output (USERO) */ | |
| 421 | #define PLX_CNTRL_USERO BIT(16) | |
| 422 | /* General Purpose Input (USERI) (read-only) */ | |
| 423 | #define PLX_CNTRL_USERI BIT(17) | |
| 424 | /* Serial EEPROM Clock Output (EESK) */ | |
| 425 | #define PLX_CNTRL_EESK BIT(24) | |
| 426 | /* Serial EEPROM Chip Select Output (EECS) */ | |
| 427 | #define PLX_CNTRL_EECS BIT(25) | |
| 428 | /* Serial EEPROM Data Write Bit (EEDI (sic)) */ | |
| 429 | #define PLX_CNTRL_EEWB BIT(26) | |
| 430 | /* Serial EEPROM Data Read Bit (EEDO (sic)) (read-only) */ | |
| 431 | #define PLX_CNTRL_EERB BIT(27) | |
| 432 | /* Serial EEPROM Present (read-only) */ | |
| 433 | #define PLX_CNTRL_EEPRESENT BIT(28) | |
| 434 | /* Reload Configuration Registers from EEPROM */ | |
| 435 | #define PLX_CNTRL_EERELOAD BIT(29) | |
| 436 | /* PCI Adapter Software Reset (asserts LRESETo#) */ | |
| 437 | #define PLX_CNTRL_RESET BIT(30) | |
| 438 | /* Local Init Status (read-only) */ | |
| 439 | #define PLX_CNTRL_INITDONE BIT(31) | |
| 440 | /* | |
| 441 | * Combined command code stuff for convenience. | |
| 442 | */ | |
| 443 | #define PLX_CNTRL_CC_MASK \ | |
| 444 | (PLX_CNTRL_CCRDMA_MASK | PLX_CNTRL_CCWDMA_MASK | \ | |
| 445 | PLX_CNTRL_CCRDM_MASK | PLX_CNTRL_CCWDM_MASK) | |
| 446 | #define PLX_CNTRL_CC_NORMAL \ | |
| 447 | (PLX_CNTRL_CCRDMA_NORMAL | PLX_CNTRL_CCWDMA_NORMAL | \ | |
| 448 | PLX_CNTRL_CCRDM_NORMAL | PLX_CNTRL_CCWDM_NORMAL) /* val after reset */ | |
| 3d9f0739 | 449 | |
| c644a11a IA |
450 | /* PCI Permanent Configuration ID Register (hard-coded PLX vendor and device) */ |
| 451 | #define PLX_REG_PCIHIDR 0x0070 | |
| 452 | ||
| df04d3aa IA |
453 | /* Hard-coded ID for PLX PCI 9080 */ |
| 454 | #define PLX_PCIHIDR_9080 0x908010b5 | |
| 455 | ||
| c644a11a IA |
456 | /* PCI Permanent Revision ID Register (hard-coded silicon revision) (8-bit). */ |
| 457 | #define PLX_REG_PCIHREV 0x0074 | |
| 3d9f0739 | 458 | |
| c644a11a IA |
459 | /* DMA Channel N Mode Register (N <= 1) */ |
| 460 | #define PLX_REG_DMAMODE(n) ((n) ? PLX_REG_DMAMODE1 : PLX_REG_DMAMODE0) | |
| 461 | #define PLX_REG_DMAMODE0 0x0080 | |
| 462 | #define PLX_REG_DMAMODE1 0x0094 | |
| 3d9f0739 | 463 | |
| 65bf53de | 464 | /* Local Bus Width */ |
| 686869b4 IA |
465 | #define PLX_DMAMODE_WIDTH_8 (BIT(0) * 0) /* 8 bits wide */ |
| 466 | #define PLX_DMAMODE_WIDTH_16 (BIT(0) * 1) /* 16 bits wide */ | |
| 467 | #define PLX_DMAMODE_WIDTH_32 (BIT(0) * 2) /* 32 bits wide */ | |
| 468 | #define PLX_DMAMODE_WIDTH_32A (BIT(0) * 3) /* 32 bits wide */ | |
| 65bf53de | 469 | #define PLX_DMAMODE_WIDTH_MASK GENMASK(1, 0) |
| 65bf53de IA |
470 | /* Internal Wait States */ |
| 471 | #define PLX_DMAMODE_IWS(x) (BIT(2) * ((x) & 0xf)) | |
| 472 | #define PLX_DMAMODE_IWS_MASK GENMASK(5, 2) | |
| 6ad124d5 | 473 | #define PLX_DMAMODE_TO_IWS(r) (((r) & PLX_DMAMODE_IWS_MASK) >> 2) |
| 65bf53de IA |
474 | /* Ready Input Enable */ |
| 475 | #define PLX_DMAMODE_READYIEN BIT(6) | |
| 476 | /* BTERM# Input Enable */ | |
| 477 | #define PLX_DMAMODE_BTERMIEN BIT(7) | |
| 478 | /* Local Burst Enable */ | |
| 479 | #define PLX_DMAMODE_BURSTEN BIT(8) | |
| 480 | /* Chaining Enable */ | |
| 481 | #define PLX_DMAMODE_CHAINEN BIT(9) | |
| 482 | /* Done Interrupt Enable */ | |
| 483 | #define PLX_DMAMODE_DONEIEN BIT(10) | |
| 484 | /* Hold Local Address Constant */ | |
| 485 | #define PLX_DMAMODE_LACONST BIT(11) | |
| 486 | /* Demand Mode */ | |
| 487 | #define PLX_DMAMODE_DEMAND BIT(12) | |
| 488 | /* Write And Invalidate Mode */ | |
| 489 | #define PLX_DMAMODE_WINVALIDATE BIT(13) | |
| 490 | /* DMA EOT Enable - enables EOT0# or EOT1# input pin */ | |
| 491 | #define PLX_DMAMODE_EOTEN BIT(14) | |
| 492 | /* DMA Stop Data Transfer Mode - 0:BLAST; 1:EOT asserted or DREQ deasserted */ | |
| 493 | #define PLX_DMAMODE_STOP BIT(15) | |
| 494 | /* DMA Clear Count Mode - count in descriptor cleared on completion */ | |
| 495 | #define PLX_DMAMODE_CLRCOUNT BIT(16) | |
| 496 | /* DMA Channel Interrupt Select - 0:local bus interrupt; 1:PCI interrupt */ | |
| 497 | #define PLX_DMAMODE_INTRPCI BIT(17) | |
| 3d9f0739 | 498 | |
| c644a11a IA |
499 | /* DMA Channel N PCI Address Register (N <= 1) */ |
| 500 | #define PLX_REG_DMAPADR(n) ((n) ? PLX_REG_DMAPADR1 : PLX_REG_DMAPADR0) | |
| 501 | #define PLX_REG_DMAPADR0 0x0084 | |
| 502 | #define PLX_REG_DMAPADR1 0x0098 | |
| 503 | ||
| 504 | /* DMA Channel N Local Address Register (N <= 1) */ | |
| 505 | #define PLX_REG_DMALADR(n) ((n) ? PLX_REG_DMALADR1 : PLX_REG_DMALADR0) | |
| 506 | #define PLX_REG_DMALADR0 0x0088 | |
| 507 | #define PLX_REG_DMALADR1 0x009c | |
| 3d9f0739 | 508 | |
| c644a11a IA |
509 | /* DMA Channel N Transfer Size (Bytes) Register (N <= 1) (first 23 bits) */ |
| 510 | #define PLX_REG_DMASIZ(n) ((n) ? PLX_REG_DMASIZ1 : PLX_REG_DMASIZ0) | |
| 511 | #define PLX_REG_DMASIZ0 0x008c | |
| 512 | #define PLX_REG_DMASIZ1 0x00a0 | |
| 3d9f0739 | 513 | |
| c644a11a IA |
514 | /* DMA Channel N Descriptor Pointer Register (N <= 1) */ |
| 515 | #define PLX_REG_DMADPR(n) ((n) ? PLX_REG_DMADPR1 : PLX_REG_DMADPR0) | |
| 516 | #define PLX_REG_DMADPR0 0x0090 | |
| 517 | #define PLX_REG_DMADPR1 0x00a4 | |
| 3d9f0739 | 518 | |
| dde90d89 IA |
519 | /* Descriptor Located In PCI Address Space (not local address space) */ |
| 520 | #define PLX_DMADPR_DESCPCI BIT(0) | |
| 521 | /* End Of Chain */ | |
| 522 | #define PLX_DMADPR_CHAINEND BIT(1) | |
| 523 | /* Interrupt After Terminal Count */ | |
| 524 | #define PLX_DMADPR_TCINTR BIT(2) | |
| 525 | /* Direction Of Transfer Local Bus To PCI (not PCI to local) */ | |
| 526 | #define PLX_DMADPR_XFERL2P BIT(3) | |
| 527 | /* Next Descriptor Address Bits 31:4 (16 byte boundary) */ | |
| 528 | #define PLX_DMADPR_NEXT_MASK GENMASK(31, 4) | |
| 3d9f0739 | 529 | |
| c644a11a IA |
530 | /* DMA Channel N Command/Status Register (N <= 1) (8-bit) */ |
| 531 | #define PLX_REG_DMACSR(n) ((n) ? PLX_REG_DMACSR1 : PLX_REG_DMACSR0) | |
| 532 | #define PLX_REG_DMACSR0 0x00a8 | |
| 533 | #define PLX_REG_DMACSR1 0x00a9 | |
| 534 | ||
| 3dcf1b55 IA |
535 | /* Channel Enable */ |
| 536 | #define PLX_DMACSR_ENABLE BIT(0) | |
| 537 | /* Channel Start - write 1 to start transfer (write-only) */ | |
| 538 | #define PLX_DMACSR_START BIT(1) | |
| 539 | /* Channel Abort - write 1 to abort transfer (write-only) */ | |
| 540 | #define PLX_DMACSR_ABORT BIT(2) | |
| 541 | /* Clear Interrupt - write 1 to clear DMA Channel Interrupt (write-only) */ | |
| 542 | #define PLX_DMACSR_CLEARINTR BIT(3) | |
| 543 | /* Channel Done - transfer complete/inactive (read-only) */ | |
| 544 | #define PLX_DMACSR_DONE BIT(4) | |
| 3d9f0739 | 545 | |
| c644a11a IA |
546 | /* DMA Threshold Register */ |
| 547 | #define PLX_REG_DMATHR 0x00b0 | |
| 548 | ||
| eb893331 IA |
549 | /* |
| 550 | * DMA Threshold constraints: | |
| 551 | * (C0PLAF + 1) + (C0PLAE + 1) <= 32 | |
| 552 | * (C0LPAF + 1) + (C0LPAE + 1) <= 32 | |
| 553 | * (C1PLAF + 1) + (C1PLAE + 1) <= 16 | |
| 554 | * (C1LPAF + 1) + (C1LPAE + 1) <= 16 | |
| 555 | */ | |
| 556 | ||
| 557 | /* DMA Channel 0 PCI-to-Local Almost Full (divided by 2, minus 1) */ | |
| 558 | #define PLX_DMATHR_C0PLAF(x) (BIT(0) * ((x) & 0xf)) | |
| 559 | #define PLX_DMATHR_C0PLAF_MASK GENMASK(3, 0) | |
| 6ad124d5 | 560 | #define PLX_DMATHR_TO_C0PLAF(r) ((r) & PLX_DMATHR_C0PLAF_MASK) |
| eb893331 IA |
561 | /* DMA Channel 0 Local-to-PCI Almost Empty (divided by 2, minus 1) */ |
| 562 | #define PLX_DMATHR_C0LPAE(x) (BIT(4) * ((x) & 0xf)) | |
| 563 | #define PLX_DMATHR_C0LPAE_MASK GENMASK(7, 4) | |
| 6ad124d5 | 564 | #define PLX_DMATHR_TO_C0LPAE(r) (((r) & PLX_DMATHR_C0LPAE_MASK) >> 4) |
| eb893331 IA |
565 | /* DMA Channel 0 Local-to-PCI Almost Full (divided by 2, minus 1) */ |
| 566 | #define PLX_DMATHR_C0LPAF(x) (BIT(8) * ((x) & 0xf)) | |
| 567 | #define PLX_DMATHR_C0LPAF_MASK GENMASK(11, 8) | |
| 6ad124d5 | 568 | #define PLX_DMATHR_TO_C0LPAF(r) (((r) & PLX_DMATHR_C0LPAF_MASK) >> 8) |
| eb893331 IA |
569 | /* DMA Channel 0 PCI-to-Local Almost Empty (divided by 2, minus 1) */ |
| 570 | #define PLX_DMATHR_C0PLAE(x) (BIT(12) * ((x) & 0xf)) | |
| 571 | #define PLX_DMATHR_C0PLAE_MASK GENMASK(15, 12) | |
| 6ad124d5 | 572 | #define PLX_DMATHR_TO_C0PLAE(r) (((r) & PLX_DMATHR_C0PLAE_MASK) >> 12) |
| eb893331 IA |
573 | /* DMA Channel 1 PCI-to-Local Almost Full (divided by 2, minus 1) */ |
| 574 | #define PLX_DMATHR_C1PLAF(x) (BIT(16) * ((x) & 0xf)) | |
| 575 | #define PLX_DMATHR_C1PLAF_MASK GENMASK(19, 16) | |
| 6ad124d5 | 576 | #define PLX_DMATHR_TO_C1PLAF(r) (((r) & PLX_DMATHR_C1PLAF_MASK) >> 16) |
| eb893331 IA |
577 | /* DMA Channel 1 Local-to-PCI Almost Empty (divided by 2, minus 1) */ |
| 578 | #define PLX_DMATHR_C1LPAE(x) (BIT(20) * ((x) & 0xf)) | |
| 579 | #define PLX_DMATHR_C1LPAE_MASK GENMASK(23, 20) | |
| 6ad124d5 | 580 | #define PLX_DMATHR_TO_C1LPAE(r) (((r) & PLX_DMATHR_C1LPAE_MASK) >> 20) |
| eb893331 IA |
581 | /* DMA Channel 1 Local-to-PCI Almost Full (divided by 2, minus 1) */ |
| 582 | #define PLX_DMATHR_C1LPAF(x) (BIT(24) * ((x) & 0xf)) | |
| 583 | #define PLX_DMATHR_C1LPAF_MASK GENMASK(27, 24) | |
| 6ad124d5 | 584 | #define PLX_DMATHR_TO_C1LPAF(r) (((r) & PLX_DMATHR_C1LPAF_MASK) >> 24) |
| eb893331 IA |
585 | /* DMA Channel 1 PCI-to-Local Almost Empty (divided by 2, minus 1) */ |
| 586 | #define PLX_DMATHR_C1PLAE(x) (BIT(28) * ((x) & 0xf)) | |
| 587 | #define PLX_DMATHR_C1PLAE_MASK GENMASK(31, 28) | |
| 6ad124d5 | 588 | #define PLX_DMATHR_TO_C1PLAE(r) (((r) & PLX_DMATHR_C1PLAE_MASK) >> 28) |
| eb893331 | 589 | |
| c644a11a IA |
590 | /* |
| 591 | * Messaging Queue Registers OPLFIS, OPLFIM, IQP, OQP, MQCR, QBAR, IFHPR, | |
| 592 | * IFTPR, IPHPR, IPTPR, OFHPR, OFTPR, OPHPR, OPTPR, and QSR have been omitted. | |
| 593 | * They are used by the I2O feature. (IQP and OQP occupy the usual offsets of | |
| 594 | * the MBOX0 and MBOX1 registers if the I2O feature is enabled, but MBOX0 and | |
| 595 | * MBOX1 are accessible via alternative offsets. | |
| 596 | */ | |
| 597 | ||
| 598 | /* Queue Status/Control Register */ | |
| 599 | #define PLX_REG_QSR 0x00e8 | |
| 600 | ||
| 601 | /* Value of QSR after reset - disables I2O feature completely. */ | |
| 602 | #define PLX_QSR_VALUE_AFTER_RESET 0x00000050 | |
| 3d9f0739 DC |
603 | |
| 604 | /* | |
| 605 | * Accesses near the end of memory can cause the PLX chip | |
| 606 | * to pre-fetch data off of end-of-ram. Limit the size of | |
| 607 | * memory so host-side accesses cannot occur. | |
| 608 | */ | |
| 609 | ||
| 610 | #define PLX_PREFETCH 32 | |
| 611 | ||
| 6a64877f IA |
612 | /** |
| 613 | * plx9080_abort_dma - Abort a PLX PCI 9080 DMA transfer | |
| 614 | * @iobase: Remapped base address of configuration registers. | |
| 615 | * @channel: DMA channel number (0 or 1). | |
| 616 | * | |
| 617 | * Aborts the DMA transfer on the channel, which must have been enabled | |
| 618 | * and started beforehand. | |
| 619 | * | |
| 620 | * Return: | |
| 621 | * %0 on success. | |
| 622 | * -%ETIMEDOUT if timed out waiting for abort to complete. | |
| 623 | */ | |
| b74a9670 | 624 | static inline int plx9080_abort_dma(void __iomem *iobase, unsigned int channel) |
| 3d9f0739 | 625 | { |
| b74a9670 | 626 | void __iomem *dma_cs_addr; |
| f6e9b914 | 627 | u8 dma_status; |
| 3d9f0739 DC |
628 | const int timeout = 10000; |
| 629 | unsigned int i; | |
| 630 | ||
| c644a11a | 631 | dma_cs_addr = iobase + PLX_REG_DMACSR(channel); |
| 3d9f0739 | 632 | |
| 457bec0f | 633 | /* abort dma transfer if necessary */ |
| 3d9f0739 | 634 | dma_status = readb(dma_cs_addr); |
| 3dcf1b55 | 635 | if ((dma_status & PLX_DMACSR_ENABLE) == 0) |
| 3d9f0739 | 636 | return 0; |
| 82675f35 | 637 | |
| 457bec0f | 638 | /* wait to make sure done bit is zero */ |
| 3dcf1b55 | 639 | for (i = 0; (dma_status & PLX_DMACSR_DONE) && i < timeout; i++) { |
| 5f74ea14 | 640 | udelay(1); |
| 3d9f0739 DC |
641 | dma_status = readb(dma_cs_addr); |
| 642 | } | |
| 3c643061 | 643 | if (i == timeout) |
| 3d9f0739 | 644 | return -ETIMEDOUT; |
| 3c643061 | 645 | |
| 457bec0f | 646 | /* disable and abort channel */ |
| 3dcf1b55 | 647 | writeb(PLX_DMACSR_ABORT, dma_cs_addr); |
| 457bec0f | 648 | /* wait for dma done bit */ |
| 3d9f0739 | 649 | dma_status = readb(dma_cs_addr); |
| 3dcf1b55 | 650 | for (i = 0; (dma_status & PLX_DMACSR_DONE) == 0 && i < timeout; i++) { |
| 5f74ea14 | 651 | udelay(1); |
| 3d9f0739 DC |
652 | dma_status = readb(dma_cs_addr); |
| 653 | } | |
| 3c643061 | 654 | if (i == timeout) |
| 3d9f0739 | 655 | return -ETIMEDOUT; |
| 3d9f0739 DC |
656 | |
| 657 | return 0; | |
| 658 | } | |
| 659 | ||
| 660 | #endif /* __COMEDI_PLX9080_H */ |