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62ed6662 BB |
1 | /*====================================================================== |
2 | ||
3 | comedi/drivers/quatech_daqp_cs.c | |
4 | ||
5 | Quatech DAQP PCMCIA data capture cards COMEDI client driver | |
6 | Copyright (C) 2000, 2003 Brent Baccala <baccala@freesoft.org> | |
7 | The DAQP interface code in this file is released into the public domain. | |
8 | ||
9 | COMEDI - Linux Control and Measurement Device Interface | |
10 | Copyright (C) 1998 David A. Schleef <ds@schleef.org> | |
11 | http://www.comedi.org/ | |
12 | ||
13 | quatech_daqp_cs.c 1.10 | |
14 | ||
15 | Documentation for the DAQP PCMCIA cards can be found on Quatech's site: | |
16 | ||
3420f6b4 | 17 | ftp://ftp.quatech.com/Manuals/daqp-208.pdf |
62ed6662 BB |
18 | |
19 | This manual is for both the DAQP-208 and the DAQP-308. | |
20 | ||
21 | What works: | |
22 | ||
23 | - A/D conversion | |
24 | - 8 channels | |
25 | - 4 gain ranges | |
26 | - ground ref or differential | |
27 | - single-shot and timed both supported | |
28 | - D/A conversion, single-shot | |
29 | - digital I/O | |
30 | ||
31 | What doesn't: | |
32 | ||
33 | - any kind of triggering - external or D/A channel 1 | |
34 | - the card's optional expansion board | |
35 | - the card's timer (for anything other than A/D conversion) | |
36 | - D/A update modes other than immediate (i.e, timed) | |
37 | - fancier timing modes | |
38 | - setting card's FIFO buffer thresholds to anything but default | |
39 | ||
40 | ======================================================================*/ | |
41 | ||
42 | /* | |
43 | Driver: quatech_daqp_cs | |
44 | Description: Quatech DAQP PCMCIA data capture cards | |
45 | Author: Brent Baccala <baccala@freesoft.org> | |
46 | Status: works | |
47 | Devices: [Quatech] DAQP-208 (daqp), DAQP-308 | |
48 | */ | |
49 | ||
ce157f80 | 50 | #include <linux/module.h> |
62ed6662 | 51 | #include "../comedidev.h" |
3142788b | 52 | #include <linux/semaphore.h> |
62ed6662 | 53 | |
62ed6662 BB |
54 | #include <pcmcia/cistpl.h> |
55 | #include <pcmcia/cisreg.h> | |
56 | #include <pcmcia/ds.h> | |
57 | ||
7ec52ed2 AIB |
58 | #include <linux/completion.h> |
59 | ||
27020ffe HS |
60 | #include "comedi_fc.h" |
61 | ||
1801726e | 62 | struct daqp_private { |
62ed6662 | 63 | int stop; |
62ed6662 BB |
64 | |
65 | enum { semaphore, buffer } interrupt_mode; | |
66 | ||
7ec52ed2 | 67 | struct completion eos; |
62ed6662 | 68 | |
62ed6662 | 69 | int count; |
ab64f663 | 70 | }; |
62ed6662 | 71 | |
62ed6662 BB |
72 | /* The DAQP communicates with the system through a 16 byte I/O window. */ |
73 | ||
74 | #define DAQP_FIFO_SIZE 4096 | |
75 | ||
76 | #define DAQP_FIFO 0 | |
77 | #define DAQP_SCANLIST 1 | |
78 | #define DAQP_CONTROL 2 | |
79 | #define DAQP_STATUS 2 | |
80 | #define DAQP_DIGITAL_IO 3 | |
81 | #define DAQP_PACER_LOW 4 | |
82 | #define DAQP_PACER_MID 5 | |
83 | #define DAQP_PACER_HIGH 6 | |
84 | #define DAQP_COMMAND 7 | |
85 | #define DAQP_DA 8 | |
86 | #define DAQP_TIMER 10 | |
87 | #define DAQP_AUX 15 | |
88 | ||
89 | #define DAQP_SCANLIST_DIFFERENTIAL 0x4000 | |
90 | #define DAQP_SCANLIST_GAIN(x) ((x)<<12) | |
91 | #define DAQP_SCANLIST_CHANNEL(x) ((x)<<8) | |
92 | #define DAQP_SCANLIST_START 0x0080 | |
93 | #define DAQP_SCANLIST_EXT_GAIN(x) ((x)<<4) | |
94 | #define DAQP_SCANLIST_EXT_CHANNEL(x) (x) | |
95 | ||
96 | #define DAQP_CONTROL_PACER_100kHz 0xc0 | |
97 | #define DAQP_CONTROL_PACER_1MHz 0x80 | |
98 | #define DAQP_CONTROL_PACER_5MHz 0x40 | |
99 | #define DAQP_CONTROL_PACER_EXTERNAL 0x00 | |
100 | #define DAQP_CONTORL_EXPANSION 0x20 | |
101 | #define DAQP_CONTROL_EOS_INT_ENABLE 0x10 | |
102 | #define DAQP_CONTROL_FIFO_INT_ENABLE 0x08 | |
103 | #define DAQP_CONTROL_TRIGGER_ONESHOT 0x00 | |
104 | #define DAQP_CONTROL_TRIGGER_CONTINUOUS 0x04 | |
105 | #define DAQP_CONTROL_TRIGGER_INTERNAL 0x00 | |
106 | #define DAQP_CONTROL_TRIGGER_EXTERNAL 0x02 | |
107 | #define DAQP_CONTROL_TRIGGER_RISING 0x00 | |
108 | #define DAQP_CONTROL_TRIGGER_FALLING 0x01 | |
109 | ||
110 | #define DAQP_STATUS_IDLE 0x80 | |
111 | #define DAQP_STATUS_RUNNING 0x40 | |
112 | #define DAQP_STATUS_EVENTS 0x38 | |
113 | #define DAQP_STATUS_DATA_LOST 0x20 | |
114 | #define DAQP_STATUS_END_OF_SCAN 0x10 | |
115 | #define DAQP_STATUS_FIFO_THRESHOLD 0x08 | |
116 | #define DAQP_STATUS_FIFO_FULL 0x04 | |
117 | #define DAQP_STATUS_FIFO_NEARFULL 0x02 | |
118 | #define DAQP_STATUS_FIFO_EMPTY 0x01 | |
119 | ||
120 | #define DAQP_COMMAND_ARM 0x80 | |
121 | #define DAQP_COMMAND_RSTF 0x40 | |
122 | #define DAQP_COMMAND_RSTQ 0x20 | |
123 | #define DAQP_COMMAND_STOP 0x10 | |
124 | #define DAQP_COMMAND_LATCH 0x08 | |
125 | #define DAQP_COMMAND_100kHz 0x00 | |
126 | #define DAQP_COMMAND_50kHz 0x02 | |
127 | #define DAQP_COMMAND_25kHz 0x04 | |
128 | #define DAQP_COMMAND_FIFO_DATA 0x01 | |
129 | #define DAQP_COMMAND_FIFO_PROGRAM 0x00 | |
130 | ||
131 | #define DAQP_AUX_TRIGGER_TTL 0x00 | |
132 | #define DAQP_AUX_TRIGGER_ANALOG 0x80 | |
133 | #define DAQP_AUX_TRIGGER_PRETRIGGER 0x40 | |
134 | #define DAQP_AUX_TIMER_INT_ENABLE 0x20 | |
135 | #define DAQP_AUX_TIMER_RELOAD 0x00 | |
136 | #define DAQP_AUX_TIMER_PAUSE 0x08 | |
137 | #define DAQP_AUX_TIMER_GO 0x10 | |
138 | #define DAQP_AUX_TIMER_GO_EXTERNAL 0x18 | |
139 | #define DAQP_AUX_TIMER_EXTERNAL_SRC 0x04 | |
140 | #define DAQP_AUX_TIMER_INTERNAL_SRC 0x00 | |
141 | #define DAQP_AUX_DA_DIRECT 0x00 | |
142 | #define DAQP_AUX_DA_OVERFLOW 0x01 | |
143 | #define DAQP_AUX_DA_EXTERNAL 0x02 | |
144 | #define DAQP_AUX_DA_PACER 0x03 | |
145 | ||
146 | #define DAQP_AUX_RUNNING 0x80 | |
147 | #define DAQP_AUX_TRIGGERED 0x40 | |
148 | #define DAQP_AUX_DA_BUFFER 0x20 | |
149 | #define DAQP_AUX_TIMER_OVERFLOW 0x10 | |
150 | #define DAQP_AUX_CONVERSION 0x08 | |
151 | #define DAQP_AUX_DATA_LOST 0x04 | |
152 | #define DAQP_AUX_FIFO_NEARFULL 0x02 | |
153 | #define DAQP_AUX_FIFO_EMPTY 0x01 | |
154 | ||
e23fe9a1 HS |
155 | static const struct comedi_lrange range_daqp_ai = { |
156 | 4, { | |
157 | BIP_RANGE(10), | |
158 | BIP_RANGE(5), | |
159 | BIP_RANGE(2.5), | |
160 | BIP_RANGE(1.25) | |
161 | } | |
62ed6662 BB |
162 | }; |
163 | ||
62ed6662 BB |
164 | /* Cancel a running acquisition */ |
165 | ||
da91b269 | 166 | static int daqp_ai_cancel(struct comedi_device *dev, struct comedi_subdevice *s) |
62ed6662 | 167 | { |
1801726e | 168 | struct daqp_private *devpriv = dev->private; |
62ed6662 | 169 | |
1801726e | 170 | if (devpriv->stop) |
62ed6662 | 171 | return -EIO; |
3420f6b4 | 172 | |
62ed6662 BB |
173 | outb(DAQP_COMMAND_STOP, dev->iobase + DAQP_COMMAND); |
174 | ||
175 | /* flush any linguring data in FIFO - superfluous here */ | |
176 | /* outb(DAQP_COMMAND_RSTF, dev->iobase+DAQP_COMMAND); */ | |
177 | ||
1801726e | 178 | devpriv->interrupt_mode = semaphore; |
62ed6662 BB |
179 | |
180 | return 0; | |
181 | } | |
182 | ||
183 | /* Interrupt handler | |
184 | * | |
1801726e HS |
185 | * Operates in one of two modes. If devpriv->interrupt_mode is |
186 | * 'semaphore', just signal the devpriv->eos completion and return | |
62ed6662 BB |
187 | * (one-shot mode). Otherwise (continuous mode), read data in from |
188 | * the card, transfer it to the buffer provided by the higher-level | |
189 | * comedi kernel module, and signal various comedi callback routines, | |
190 | * which run pretty quick. | |
191 | */ | |
e3752a1d | 192 | static enum irqreturn daqp_interrupt(int irq, void *dev_id) |
62ed6662 | 193 | { |
c1271742 | 194 | struct comedi_device *dev = dev_id; |
1801726e | 195 | struct daqp_private *devpriv = dev->private; |
c1271742 | 196 | struct comedi_subdevice *s = dev->read_subdev; |
62ed6662 BB |
197 | int loop_limit = 10000; |
198 | int status; | |
199 | ||
c1271742 | 200 | if (!dev->attached) |
e3752a1d | 201 | return IRQ_NONE; |
62ed6662 | 202 | |
1801726e | 203 | switch (devpriv->interrupt_mode) { |
62ed6662 | 204 | case semaphore: |
1801726e | 205 | complete(&devpriv->eos); |
62ed6662 BB |
206 | break; |
207 | ||
208 | case buffer: | |
62ed6662 | 209 | while (!((status = inb(dev->iobase + DAQP_STATUS)) |
0a85b6f0 | 210 | & DAQP_STATUS_FIFO_EMPTY)) { |
8bab0d68 | 211 | unsigned short data; |
62ed6662 BB |
212 | |
213 | if (status & DAQP_STATUS_DATA_LOST) { | |
214 | s->async->events |= | |
0a85b6f0 | 215 | COMEDI_CB_EOA | COMEDI_CB_OVERFLOW; |
53f63dc7 | 216 | dev_warn(dev->class_dev, "data lost\n"); |
62ed6662 BB |
217 | daqp_ai_cancel(dev, s); |
218 | break; | |
219 | } | |
220 | ||
221 | data = inb(dev->iobase + DAQP_FIFO); | |
222 | data |= inb(dev->iobase + DAQP_FIFO) << 8; | |
223 | data ^= 0x8000; | |
224 | ||
225 | comedi_buf_put(s->async, data); | |
226 | ||
227 | /* If there's a limit, decrement it | |
228 | * and stop conversion if zero | |
229 | */ | |
230 | ||
1801726e HS |
231 | if (devpriv->count > 0) { |
232 | devpriv->count--; | |
233 | if (devpriv->count == 0) { | |
62ed6662 BB |
234 | daqp_ai_cancel(dev, s); |
235 | s->async->events |= COMEDI_CB_EOA; | |
236 | break; | |
237 | } | |
238 | } | |
239 | ||
240 | if ((loop_limit--) <= 0) | |
241 | break; | |
242 | } | |
243 | ||
244 | if (loop_limit <= 0) { | |
ce3ed9f0 YT |
245 | dev_warn(dev->class_dev, |
246 | "loop_limit reached in daqp_interrupt()\n"); | |
62ed6662 BB |
247 | daqp_ai_cancel(dev, s); |
248 | s->async->events |= COMEDI_CB_EOA | COMEDI_CB_ERROR; | |
249 | } | |
250 | ||
251 | s->async->events |= COMEDI_CB_BLOCK; | |
252 | ||
253 | comedi_event(dev, s); | |
254 | } | |
e3752a1d | 255 | return IRQ_HANDLED; |
62ed6662 BB |
256 | } |
257 | ||
bd7807f9 HS |
258 | static void daqp_ai_set_one_scanlist_entry(struct comedi_device *dev, |
259 | unsigned int chanspec, | |
260 | int start) | |
261 | { | |
262 | unsigned int chan = CR_CHAN(chanspec); | |
263 | unsigned int range = CR_RANGE(chanspec); | |
264 | unsigned int aref = CR_AREF(chanspec); | |
265 | unsigned int val; | |
266 | ||
267 | val = DAQP_SCANLIST_CHANNEL(chan) | DAQP_SCANLIST_GAIN(range); | |
268 | ||
269 | if (aref == AREF_DIFF) | |
270 | val |= DAQP_SCANLIST_DIFFERENTIAL; | |
271 | ||
272 | if (start) | |
273 | val |= DAQP_SCANLIST_START; | |
274 | ||
275 | outb(val & 0xff, dev->iobase + DAQP_SCANLIST); | |
276 | outb((val >> 8) & 0xff, dev->iobase + DAQP_SCANLIST); | |
277 | } | |
278 | ||
62ed6662 BB |
279 | /* One-shot analog data acquisition routine */ |
280 | ||
0a85b6f0 MT |
281 | static int daqp_ai_insn_read(struct comedi_device *dev, |
282 | struct comedi_subdevice *s, | |
283 | struct comedi_insn *insn, unsigned int *data) | |
62ed6662 | 284 | { |
1801726e | 285 | struct daqp_private *devpriv = dev->private; |
62ed6662 BB |
286 | int i; |
287 | int v; | |
288 | int counter = 10000; | |
289 | ||
1801726e | 290 | if (devpriv->stop) |
62ed6662 | 291 | return -EIO; |
3420f6b4 | 292 | |
62ed6662 BB |
293 | /* Stop any running conversion */ |
294 | daqp_ai_cancel(dev, s); | |
295 | ||
296 | outb(0, dev->iobase + DAQP_AUX); | |
297 | ||
298 | /* Reset scan list queue */ | |
299 | outb(DAQP_COMMAND_RSTQ, dev->iobase + DAQP_COMMAND); | |
300 | ||
301 | /* Program one scan list entry */ | |
bd7807f9 | 302 | daqp_ai_set_one_scanlist_entry(dev, insn->chanspec, 1); |
62ed6662 BB |
303 | |
304 | /* Reset data FIFO (see page 28 of DAQP User's Manual) */ | |
305 | ||
306 | outb(DAQP_COMMAND_RSTF, dev->iobase + DAQP_COMMAND); | |
307 | ||
308 | /* Set trigger */ | |
309 | ||
310 | v = DAQP_CONTROL_TRIGGER_ONESHOT | DAQP_CONTROL_TRIGGER_INTERNAL | |
0a85b6f0 | 311 | | DAQP_CONTROL_PACER_100kHz | DAQP_CONTROL_EOS_INT_ENABLE; |
62ed6662 BB |
312 | |
313 | outb(v, dev->iobase + DAQP_CONTROL); | |
314 | ||
25985edc | 315 | /* Reset any pending interrupts (my card has a tendency to require |
62ed6662 BB |
316 | * require multiple reads on the status register to achieve this) |
317 | */ | |
318 | ||
319 | while (--counter | |
543a09e9 YT |
320 | && (inb(dev->iobase + DAQP_STATUS) & DAQP_STATUS_EVENTS)) |
321 | ; | |
62ed6662 | 322 | if (!counter) { |
53f63dc7 YT |
323 | dev_err(dev->class_dev, |
324 | "couldn't clear interrupts in status register\n"); | |
62ed6662 BB |
325 | return -1; |
326 | } | |
327 | ||
1801726e HS |
328 | init_completion(&devpriv->eos); |
329 | devpriv->interrupt_mode = semaphore; | |
62ed6662 BB |
330 | |
331 | for (i = 0; i < insn->n; i++) { | |
332 | ||
333 | /* Start conversion */ | |
334 | outb(DAQP_COMMAND_ARM | DAQP_COMMAND_FIFO_DATA, | |
0a85b6f0 | 335 | dev->iobase + DAQP_COMMAND); |
62ed6662 | 336 | |
7ec52ed2 | 337 | /* Wait for interrupt service routine to unblock completion */ |
62ed6662 | 338 | /* Maybe could use a timeout here, but it's interruptible */ |
1801726e | 339 | if (wait_for_completion_interruptible(&devpriv->eos)) |
62ed6662 BB |
340 | return -EINTR; |
341 | ||
342 | data[i] = inb(dev->iobase + DAQP_FIFO); | |
343 | data[i] |= inb(dev->iobase + DAQP_FIFO) << 8; | |
344 | data[i] ^= 0x8000; | |
345 | } | |
346 | ||
347 | return insn->n; | |
348 | } | |
349 | ||
350 | /* This function converts ns nanoseconds to a counter value suitable | |
351 | * for programming the device. We always use the DAQP's 5 MHz clock, | |
352 | * which with its 24-bit counter, allows values up to 84 seconds. | |
353 | * Also, the function adjusts ns so that it cooresponds to the actual | |
354 | * time that the device will use. | |
355 | */ | |
356 | ||
357 | static int daqp_ns_to_timer(unsigned int *ns, int round) | |
358 | { | |
359 | int timer; | |
360 | ||
361 | timer = *ns / 200; | |
362 | *ns = timer * 200; | |
363 | ||
364 | return timer; | |
365 | } | |
366 | ||
367 | /* cmdtest tests a particular command to see if it is valid. | |
368 | * Using the cmdtest ioctl, a user can create a valid cmd | |
369 | * and then have it executed by the cmd ioctl. | |
370 | * | |
371 | * cmdtest returns 1,2,3,4 or 0, depending on which tests | |
372 | * the command passes. | |
373 | */ | |
374 | ||
0a85b6f0 MT |
375 | static int daqp_ai_cmdtest(struct comedi_device *dev, |
376 | struct comedi_subdevice *s, struct comedi_cmd *cmd) | |
62ed6662 BB |
377 | { |
378 | int err = 0; | |
379 | int tmp; | |
380 | ||
27020ffe | 381 | /* Step 1 : check if triggers are trivially valid */ |
62ed6662 | 382 | |
27020ffe HS |
383 | err |= cfc_check_trigger_src(&cmd->start_src, TRIG_NOW); |
384 | err |= cfc_check_trigger_src(&cmd->scan_begin_src, | |
385 | TRIG_TIMER | TRIG_FOLLOW); | |
386 | err |= cfc_check_trigger_src(&cmd->convert_src, | |
387 | TRIG_TIMER | TRIG_NOW); | |
388 | err |= cfc_check_trigger_src(&cmd->scan_end_src, TRIG_COUNT); | |
389 | err |= cfc_check_trigger_src(&cmd->stop_src, TRIG_COUNT | TRIG_NONE); | |
62ed6662 BB |
390 | |
391 | if (err) | |
392 | return 1; | |
393 | ||
27020ffe | 394 | /* Step 2a : make sure trigger sources are unique */ |
62ed6662 | 395 | |
27020ffe HS |
396 | err |= cfc_check_trigger_is_unique(cmd->scan_begin_src); |
397 | err |= cfc_check_trigger_is_unique(cmd->convert_src); | |
398 | err |= cfc_check_trigger_is_unique(cmd->stop_src); | |
399 | ||
400 | /* Step 2b : and mutually compatible */ | |
62ed6662 BB |
401 | |
402 | if (err) | |
403 | return 2; | |
404 | ||
42cae4a1 HS |
405 | /* Step 3: check if arguments are trivially valid */ |
406 | ||
407 | err |= cfc_check_trigger_arg_is(&cmd->start_arg, 0); | |
62ed6662 | 408 | |
62ed6662 BB |
409 | #define MAX_SPEED 10000 /* 100 kHz - in nanoseconds */ |
410 | ||
42cae4a1 HS |
411 | if (cmd->scan_begin_src == TRIG_TIMER) |
412 | err |= cfc_check_trigger_arg_min(&cmd->scan_begin_arg, | |
413 | MAX_SPEED); | |
62ed6662 BB |
414 | |
415 | /* If both scan_begin and convert are both timer values, the only | |
416 | * way that can make sense is if the scan time is the number of | |
417 | * conversions times the convert time | |
418 | */ | |
419 | ||
420 | if (cmd->scan_begin_src == TRIG_TIMER && cmd->convert_src == TRIG_TIMER | |
0a85b6f0 | 421 | && cmd->scan_begin_arg != cmd->convert_arg * cmd->scan_end_arg) { |
42cae4a1 | 422 | err |= -EINVAL; |
62ed6662 BB |
423 | } |
424 | ||
42cae4a1 HS |
425 | if (cmd->convert_src == TRIG_TIMER) |
426 | err |= cfc_check_trigger_arg_min(&cmd->convert_arg, MAX_SPEED); | |
62ed6662 | 427 | |
42cae4a1 HS |
428 | err |= cfc_check_trigger_arg_is(&cmd->scan_end_arg, cmd->chanlist_len); |
429 | ||
430 | if (cmd->stop_src == TRIG_COUNT) | |
431 | err |= cfc_check_trigger_arg_max(&cmd->stop_arg, 0x00ffffff); | |
432 | else /* TRIG_NONE */ | |
433 | err |= cfc_check_trigger_arg_is(&cmd->stop_arg, 0); | |
62ed6662 BB |
434 | |
435 | if (err) | |
436 | return 3; | |
437 | ||
438 | /* step 4: fix up any arguments */ | |
439 | ||
440 | if (cmd->scan_begin_src == TRIG_TIMER) { | |
441 | tmp = cmd->scan_begin_arg; | |
442 | daqp_ns_to_timer(&cmd->scan_begin_arg, | |
0a85b6f0 | 443 | cmd->flags & TRIG_ROUND_MASK); |
62ed6662 BB |
444 | if (tmp != cmd->scan_begin_arg) |
445 | err++; | |
446 | } | |
447 | ||
448 | if (cmd->convert_src == TRIG_TIMER) { | |
449 | tmp = cmd->convert_arg; | |
450 | daqp_ns_to_timer(&cmd->convert_arg, | |
0a85b6f0 | 451 | cmd->flags & TRIG_ROUND_MASK); |
62ed6662 BB |
452 | if (tmp != cmd->convert_arg) |
453 | err++; | |
454 | } | |
455 | ||
456 | if (err) | |
457 | return 4; | |
458 | ||
459 | return 0; | |
460 | } | |
461 | ||
da91b269 | 462 | static int daqp_ai_cmd(struct comedi_device *dev, struct comedi_subdevice *s) |
62ed6662 | 463 | { |
1801726e | 464 | struct daqp_private *devpriv = dev->private; |
ea6d0d4c | 465 | struct comedi_cmd *cmd = &s->async->cmd; |
e3752a1d | 466 | int counter; |
62ed6662 BB |
467 | int scanlist_start_on_every_entry; |
468 | int threshold; | |
469 | ||
470 | int i; | |
471 | int v; | |
472 | ||
1801726e | 473 | if (devpriv->stop) |
62ed6662 | 474 | return -EIO; |
3420f6b4 | 475 | |
62ed6662 BB |
476 | /* Stop any running conversion */ |
477 | daqp_ai_cancel(dev, s); | |
478 | ||
479 | outb(0, dev->iobase + DAQP_AUX); | |
480 | ||
481 | /* Reset scan list queue */ | |
482 | outb(DAQP_COMMAND_RSTQ, dev->iobase + DAQP_COMMAND); | |
483 | ||
484 | /* Program pacer clock | |
485 | * | |
486 | * There's two modes we can operate in. If convert_src is | |
487 | * TRIG_TIMER, then convert_arg specifies the time between | |
488 | * each conversion, so we program the pacer clock to that | |
489 | * frequency and set the SCANLIST_START bit on every scanlist | |
490 | * entry. Otherwise, convert_src is TRIG_NOW, which means | |
491 | * we want the fastest possible conversions, scan_begin_src | |
492 | * is TRIG_TIMER, and scan_begin_arg specifies the time between | |
493 | * each scan, so we program the pacer clock to this frequency | |
494 | * and only set the SCANLIST_START bit on the first entry. | |
495 | */ | |
496 | ||
497 | if (cmd->convert_src == TRIG_TIMER) { | |
e3752a1d | 498 | counter = daqp_ns_to_timer(&cmd->convert_arg, |
0a85b6f0 | 499 | cmd->flags & TRIG_ROUND_MASK); |
62ed6662 BB |
500 | outb(counter & 0xff, dev->iobase + DAQP_PACER_LOW); |
501 | outb((counter >> 8) & 0xff, dev->iobase + DAQP_PACER_MID); | |
502 | outb((counter >> 16) & 0xff, dev->iobase + DAQP_PACER_HIGH); | |
503 | scanlist_start_on_every_entry = 1; | |
504 | } else { | |
e3752a1d | 505 | counter = daqp_ns_to_timer(&cmd->scan_begin_arg, |
0a85b6f0 | 506 | cmd->flags & TRIG_ROUND_MASK); |
62ed6662 BB |
507 | outb(counter & 0xff, dev->iobase + DAQP_PACER_LOW); |
508 | outb((counter >> 8) & 0xff, dev->iobase + DAQP_PACER_MID); | |
509 | outb((counter >> 16) & 0xff, dev->iobase + DAQP_PACER_HIGH); | |
510 | scanlist_start_on_every_entry = 0; | |
511 | } | |
512 | ||
513 | /* Program scan list */ | |
62ed6662 | 514 | for (i = 0; i < cmd->chanlist_len; i++) { |
bd7807f9 | 515 | int start = (i == 0 || scanlist_start_on_every_entry); |
62ed6662 | 516 | |
bd7807f9 | 517 | daqp_ai_set_one_scanlist_entry(dev, cmd->chanlist[i], start); |
62ed6662 BB |
518 | } |
519 | ||
520 | /* Now it's time to program the FIFO threshold, basically the | |
521 | * number of samples the card will buffer before it interrupts | |
522 | * the CPU. | |
523 | * | |
524 | * If we don't have a stop count, then use half the size of | |
525 | * the FIFO (the manufacturer's recommendation). Consider | |
526 | * that the FIFO can hold 2K samples (4K bytes). With the | |
527 | * threshold set at half the FIFO size, we have a margin of | |
528 | * error of 1024 samples. At the chip's maximum sample rate | |
529 | * of 100,000 Hz, the CPU would have to delay interrupt | |
530 | * service for a full 10 milliseconds in order to lose data | |
531 | * here (as opposed to higher up in the kernel). I've never | |
532 | * seen it happen. However, for slow sample rates it may | |
533 | * buffer too much data and introduce too much delay for the | |
534 | * user application. | |
535 | * | |
536 | * If we have a stop count, then things get more interesting. | |
537 | * If the stop count is less than the FIFO size (actually | |
538 | * three-quarters of the FIFO size - see below), we just use | |
539 | * the stop count itself as the threshold, the card interrupts | |
540 | * us when that many samples have been taken, and we kill the | |
541 | * acquisition at that point and are done. If the stop count | |
542 | * is larger than that, then we divide it by 2 until it's less | |
543 | * than three quarters of the FIFO size (we always leave the | |
544 | * top quarter of the FIFO as protection against sluggish CPU | |
545 | * interrupt response) and use that as the threshold. So, if | |
546 | * the stop count is 4000 samples, we divide by two twice to | |
547 | * get 1000 samples, use that as the threshold, take four | |
548 | * interrupts to get our 4000 samples and are done. | |
549 | * | |
550 | * The algorithm could be more clever. For example, if 81000 | |
551 | * samples are requested, we could set the threshold to 1500 | |
552 | * samples and take 54 interrupts to get 81000. But 54 isn't | |
553 | * a power of two, so this algorithm won't find that option. | |
554 | * Instead, it'll set the threshold at 1266 and take 64 | |
555 | * interrupts to get 81024 samples, of which the last 24 will | |
556 | * be discarded... but we won't get the last interrupt until | |
557 | * they've been collected. To find the first option, the | |
558 | * computer could look at the prime decomposition of the | |
559 | * sample count (81000 = 3^4 * 5^3 * 2^3) and factor it into a | |
560 | * threshold (1500 = 3 * 5^3 * 2^2) and an interrupt count (54 | |
561 | * = 3^3 * 2). Hmmm... a one-line while loop or prime | |
562 | * decomposition of integers... I'll leave it the way it is. | |
563 | * | |
564 | * I'll also note a mini-race condition before ignoring it in | |
565 | * the code. Let's say we're taking 4000 samples, as before. | |
566 | * After 1000 samples, we get an interrupt. But before that | |
567 | * interrupt is completely serviced, another sample is taken | |
568 | * and loaded into the FIFO. Since the interrupt handler | |
569 | * empties the FIFO before returning, it will read 1001 samples. | |
570 | * If that happens four times, we'll end up taking 4004 samples, | |
571 | * not 4000. The interrupt handler will discard the extra four | |
572 | * samples (by halting the acquisition with four samples still | |
573 | * in the FIFO), but we will have to wait for them. | |
574 | * | |
575 | * In short, this code works pretty well, but for either of | |
576 | * the two reasons noted, might end up waiting for a few more | |
577 | * samples than actually requested. Shouldn't make too much | |
578 | * of a difference. | |
579 | */ | |
580 | ||
581 | /* Save away the number of conversions we should perform, and | |
582 | * compute the FIFO threshold (in bytes, not samples - that's | |
1801726e | 583 | * why we multiple devpriv->count by 2 = sizeof(sample)) |
62ed6662 BB |
584 | */ |
585 | ||
586 | if (cmd->stop_src == TRIG_COUNT) { | |
1801726e HS |
587 | devpriv->count = cmd->stop_arg * cmd->scan_end_arg; |
588 | threshold = 2 * devpriv->count; | |
62ed6662 BB |
589 | while (threshold > DAQP_FIFO_SIZE * 3 / 4) |
590 | threshold /= 2; | |
591 | } else { | |
1801726e | 592 | devpriv->count = -1; |
62ed6662 BB |
593 | threshold = DAQP_FIFO_SIZE / 2; |
594 | } | |
595 | ||
596 | /* Reset data FIFO (see page 28 of DAQP User's Manual) */ | |
597 | ||
598 | outb(DAQP_COMMAND_RSTF, dev->iobase + DAQP_COMMAND); | |
599 | ||
600 | /* Set FIFO threshold. First two bytes are near-empty | |
601 | * threshold, which is unused; next two bytes are near-full | |
602 | * threshold. We computed the number of bytes we want in the | |
603 | * FIFO when the interrupt is generated, what the card wants | |
604 | * is actually the number of available bytes left in the FIFO | |
605 | * when the interrupt is to happen. | |
606 | */ | |
607 | ||
608 | outb(0x00, dev->iobase + DAQP_FIFO); | |
609 | outb(0x00, dev->iobase + DAQP_FIFO); | |
610 | ||
611 | outb((DAQP_FIFO_SIZE - threshold) & 0xff, dev->iobase + DAQP_FIFO); | |
612 | outb((DAQP_FIFO_SIZE - threshold) >> 8, dev->iobase + DAQP_FIFO); | |
613 | ||
614 | /* Set trigger */ | |
615 | ||
616 | v = DAQP_CONTROL_TRIGGER_CONTINUOUS | DAQP_CONTROL_TRIGGER_INTERNAL | |
0a85b6f0 | 617 | | DAQP_CONTROL_PACER_5MHz | DAQP_CONTROL_FIFO_INT_ENABLE; |
62ed6662 BB |
618 | |
619 | outb(v, dev->iobase + DAQP_CONTROL); | |
620 | ||
25985edc | 621 | /* Reset any pending interrupts (my card has a tendency to require |
62ed6662 BB |
622 | * require multiple reads on the status register to achieve this) |
623 | */ | |
e3752a1d | 624 | counter = 100; |
62ed6662 | 625 | while (--counter |
543a09e9 YT |
626 | && (inb(dev->iobase + DAQP_STATUS) & DAQP_STATUS_EVENTS)) |
627 | ; | |
62ed6662 | 628 | if (!counter) { |
ce3ed9f0 YT |
629 | dev_err(dev->class_dev, |
630 | "couldn't clear interrupts in status register\n"); | |
62ed6662 BB |
631 | return -1; |
632 | } | |
633 | ||
1801726e | 634 | devpriv->interrupt_mode = buffer; |
62ed6662 BB |
635 | |
636 | /* Start conversion */ | |
637 | outb(DAQP_COMMAND_ARM | DAQP_COMMAND_FIFO_DATA, | |
0a85b6f0 | 638 | dev->iobase + DAQP_COMMAND); |
62ed6662 BB |
639 | |
640 | return 0; | |
641 | } | |
642 | ||
0a85b6f0 MT |
643 | static int daqp_ao_insn_write(struct comedi_device *dev, |
644 | struct comedi_subdevice *s, | |
d35dcc89 HS |
645 | struct comedi_insn *insn, |
646 | unsigned int *data) | |
62ed6662 | 647 | { |
1801726e | 648 | struct daqp_private *devpriv = dev->private; |
d35dcc89 HS |
649 | unsigned int chan = CR_CHAN(insn->chanspec); |
650 | unsigned int val; | |
651 | int i; | |
62ed6662 | 652 | |
1801726e | 653 | if (devpriv->stop) |
62ed6662 | 654 | return -EIO; |
62ed6662 | 655 | |
62ed6662 BB |
656 | /* Make sure D/A update mode is direct update */ |
657 | outb(0, dev->iobase + DAQP_AUX); | |
658 | ||
d35dcc89 HS |
659 | for (i = 0; i > insn->n; i++) { |
660 | val = data[0]; | |
661 | val &= 0x0fff; | |
662 | val ^= 0x0800; /* Flip the sign */ | |
663 | val |= (chan << 12); | |
62ed6662 | 664 | |
d35dcc89 HS |
665 | outw(val, dev->iobase + DAQP_DA); |
666 | } | |
667 | ||
668 | return insn->n; | |
62ed6662 BB |
669 | } |
670 | ||
62100fef | 671 | static int daqp_di_insn_bits(struct comedi_device *dev, |
0a85b6f0 | 672 | struct comedi_subdevice *s, |
62100fef HS |
673 | struct comedi_insn *insn, |
674 | unsigned int *data) | |
62ed6662 | 675 | { |
1801726e | 676 | struct daqp_private *devpriv = dev->private; |
62ed6662 | 677 | |
1801726e | 678 | if (devpriv->stop) |
62ed6662 | 679 | return -EIO; |
62ed6662 BB |
680 | |
681 | data[0] = inb(dev->iobase + DAQP_DIGITAL_IO); | |
682 | ||
62100fef | 683 | return insn->n; |
62ed6662 BB |
684 | } |
685 | ||
6a911d8a HS |
686 | static int daqp_do_insn_bits(struct comedi_device *dev, |
687 | struct comedi_subdevice *s, | |
688 | struct comedi_insn *insn, | |
689 | unsigned int *data) | |
62ed6662 | 690 | { |
1801726e | 691 | struct daqp_private *devpriv = dev->private; |
62ed6662 | 692 | |
1801726e | 693 | if (devpriv->stop) |
62ed6662 | 694 | return -EIO; |
62ed6662 | 695 | |
97f4289a | 696 | if (comedi_dio_update_state(s, data)) |
6a911d8a | 697 | outb(s->state, dev->iobase + DAQP_DIGITAL_IO); |
6a911d8a HS |
698 | |
699 | data[1] = s->state; | |
700 | ||
701 | return insn->n; | |
62ed6662 BB |
702 | } |
703 | ||
c04edbf2 HS |
704 | static int daqp_auto_attach(struct comedi_device *dev, |
705 | unsigned long context) | |
62ed6662 | 706 | { |
c04edbf2 | 707 | struct pcmcia_device *link = comedi_to_pcmcia_dev(dev); |
1801726e | 708 | struct daqp_private *devpriv; |
34c43922 | 709 | struct comedi_subdevice *s; |
c65c64d0 | 710 | int ret; |
62ed6662 | 711 | |
0bdab509 | 712 | devpriv = comedi_alloc_devpriv(dev, sizeof(*devpriv)); |
1801726e | 713 | if (!devpriv) |
c04edbf2 | 714 | return -ENOMEM; |
62ed6662 | 715 | |
c04edbf2 | 716 | link->config_flags |= CONF_AUTO_SET_IO | CONF_ENABLE_IRQ; |
a9d50943 | 717 | ret = comedi_pcmcia_enable(dev, NULL); |
c04edbf2 HS |
718 | if (ret) |
719 | return ret; | |
87fe1452 | 720 | dev->iobase = link->resource[0]->start; |
62ed6662 | 721 | |
c1271742 | 722 | link->priv = dev; |
c04edbf2 HS |
723 | ret = pcmcia_request_irq(link, daqp_interrupt); |
724 | if (ret) | |
725 | return ret; | |
726 | ||
2f0b9d08 | 727 | ret = comedi_alloc_subdevices(dev, 4); |
8b6c5694 | 728 | if (ret) |
62ed6662 BB |
729 | return ret; |
730 | ||
123c0e03 | 731 | s = &dev->subdevices[0]; |
62ed6662 | 732 | dev->read_subdev = s; |
b7c0afa4 HS |
733 | s->type = COMEDI_SUBD_AI; |
734 | s->subdev_flags = SDF_READABLE | SDF_GROUND | SDF_DIFF | SDF_CMD_READ; | |
735 | s->n_chan = 8; | |
736 | s->len_chanlist = 2048; | |
737 | s->maxdata = 0xffff; | |
738 | s->range_table = &range_daqp_ai; | |
739 | s->insn_read = daqp_ai_insn_read; | |
740 | s->do_cmdtest = daqp_ai_cmdtest; | |
741 | s->do_cmd = daqp_ai_cmd; | |
742 | s->cancel = daqp_ai_cancel; | |
62ed6662 | 743 | |
123c0e03 | 744 | s = &dev->subdevices[1]; |
b7c0afa4 HS |
745 | s->type = COMEDI_SUBD_AO; |
746 | s->subdev_flags = SDF_WRITEABLE; | |
747 | s->n_chan = 2; | |
748 | s->maxdata = 0x0fff; | |
749 | s->range_table = &range_bipolar5; | |
750 | s->insn_write = daqp_ao_insn_write; | |
62ed6662 | 751 | |
123c0e03 | 752 | s = &dev->subdevices[2]; |
b7c0afa4 HS |
753 | s->type = COMEDI_SUBD_DI; |
754 | s->subdev_flags = SDF_READABLE; | |
755 | s->n_chan = 1; | |
62100fef HS |
756 | s->maxdata = 1; |
757 | s->insn_bits = daqp_di_insn_bits; | |
62ed6662 | 758 | |
123c0e03 | 759 | s = &dev->subdevices[3]; |
b7c0afa4 HS |
760 | s->type = COMEDI_SUBD_DO; |
761 | s->subdev_flags = SDF_WRITEABLE; | |
762 | s->n_chan = 1; | |
6a911d8a HS |
763 | s->maxdata = 1; |
764 | s->insn_bits = daqp_do_insn_bits; | |
62ed6662 | 765 | |
b7c0afa4 | 766 | return 0; |
62ed6662 BB |
767 | } |
768 | ||
d1db2a41 HS |
769 | static struct comedi_driver driver_daqp = { |
770 | .driver_name = "quatech_daqp_cs", | |
771 | .module = THIS_MODULE, | |
c04edbf2 | 772 | .auto_attach = daqp_auto_attach, |
25736670 | 773 | .detach = comedi_pcmcia_disable, |
d1db2a41 HS |
774 | }; |
775 | ||
d1db2a41 | 776 | static int daqp_cs_suspend(struct pcmcia_device *link) |
62ed6662 | 777 | { |
c1271742 | 778 | struct comedi_device *dev = link->priv; |
1801726e | 779 | struct daqp_private *devpriv = dev ? dev->private : NULL; |
62ed6662 | 780 | |
d1db2a41 | 781 | /* Mark the device as stopped, to block IO until later */ |
1801726e HS |
782 | if (devpriv) |
783 | devpriv->stop = 1; | |
c1271742 | 784 | |
d1db2a41 HS |
785 | return 0; |
786 | } | |
62ed6662 | 787 | |
d1db2a41 HS |
788 | static int daqp_cs_resume(struct pcmcia_device *link) |
789 | { | |
c1271742 | 790 | struct comedi_device *dev = link->priv; |
1801726e | 791 | struct daqp_private *devpriv = dev ? dev->private : NULL; |
62ed6662 | 792 | |
1801726e HS |
793 | if (devpriv) |
794 | devpriv->stop = 0; | |
62ed6662 BB |
795 | |
796 | return 0; | |
d1db2a41 | 797 | } |
62ed6662 | 798 | |
d1db2a41 | 799 | static int daqp_cs_attach(struct pcmcia_device *link) |
62ed6662 | 800 | { |
c04edbf2 | 801 | return comedi_pcmcia_auto_config(link, &driver_daqp); |
62ed6662 BB |
802 | } |
803 | ||
2202a5a7 | 804 | static const struct pcmcia_device_id daqp_cs_id_table[] = { |
62ed6662 BB |
805 | PCMCIA_DEVICE_MANF_CARD(0x0137, 0x0027), |
806 | PCMCIA_DEVICE_NULL | |
807 | }; | |
62ed6662 BB |
808 | MODULE_DEVICE_TABLE(pcmcia, daqp_cs_id_table); |
809 | ||
e3752a1d | 810 | static struct pcmcia_driver daqp_cs_driver = { |
433a0e22 HS |
811 | .name = "quatech_daqp_cs", |
812 | .owner = THIS_MODULE, | |
813 | .id_table = daqp_cs_id_table, | |
814 | .probe = daqp_cs_attach, | |
c04edbf2 | 815 | .remove = comedi_pcmcia_auto_unconfig, |
433a0e22 HS |
816 | .suspend = daqp_cs_suspend, |
817 | .resume = daqp_cs_resume, | |
62ed6662 | 818 | }; |
f3493a97 | 819 | module_comedi_pcmcia_driver(driver_daqp, daqp_cs_driver); |
04c59041 HS |
820 | |
821 | MODULE_DESCRIPTION("Comedi driver for Quatech DAQP PCMCIA data capture cards"); | |
822 | MODULE_AUTHOR("Brent Baccala <baccala@freesoft.org>"); | |
823 | MODULE_LICENSE("GPL"); |