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62ed6662 BB |
1 | /*====================================================================== |
2 | ||
3 | comedi/drivers/quatech_daqp_cs.c | |
4 | ||
5 | Quatech DAQP PCMCIA data capture cards COMEDI client driver | |
6 | Copyright (C) 2000, 2003 Brent Baccala <baccala@freesoft.org> | |
7 | The DAQP interface code in this file is released into the public domain. | |
8 | ||
9 | COMEDI - Linux Control and Measurement Device Interface | |
10 | Copyright (C) 1998 David A. Schleef <ds@schleef.org> | |
11 | http://www.comedi.org/ | |
12 | ||
13 | quatech_daqp_cs.c 1.10 | |
14 | ||
15 | Documentation for the DAQP PCMCIA cards can be found on Quatech's site: | |
16 | ||
3420f6b4 | 17 | ftp://ftp.quatech.com/Manuals/daqp-208.pdf |
62ed6662 BB |
18 | |
19 | This manual is for both the DAQP-208 and the DAQP-308. | |
20 | ||
21 | What works: | |
22 | ||
23 | - A/D conversion | |
24 | - 8 channels | |
25 | - 4 gain ranges | |
26 | - ground ref or differential | |
27 | - single-shot and timed both supported | |
28 | - D/A conversion, single-shot | |
29 | - digital I/O | |
30 | ||
31 | What doesn't: | |
32 | ||
33 | - any kind of triggering - external or D/A channel 1 | |
34 | - the card's optional expansion board | |
35 | - the card's timer (for anything other than A/D conversion) | |
36 | - D/A update modes other than immediate (i.e, timed) | |
37 | - fancier timing modes | |
38 | - setting card's FIFO buffer thresholds to anything but default | |
39 | ||
40 | ======================================================================*/ | |
41 | ||
42 | /* | |
43 | Driver: quatech_daqp_cs | |
44 | Description: Quatech DAQP PCMCIA data capture cards | |
45 | Author: Brent Baccala <baccala@freesoft.org> | |
46 | Status: works | |
47 | Devices: [Quatech] DAQP-208 (daqp), DAQP-308 | |
48 | */ | |
49 | ||
ce157f80 | 50 | #include <linux/module.h> |
62ed6662 | 51 | #include "../comedidev.h" |
3142788b | 52 | #include <linux/semaphore.h> |
62ed6662 | 53 | |
62ed6662 BB |
54 | #include <pcmcia/cistpl.h> |
55 | #include <pcmcia/cisreg.h> | |
56 | #include <pcmcia/ds.h> | |
57 | ||
7ec52ed2 AIB |
58 | #include <linux/completion.h> |
59 | ||
27020ffe HS |
60 | #include "comedi_fc.h" |
61 | ||
1801726e | 62 | struct daqp_private { |
62ed6662 | 63 | int stop; |
62ed6662 BB |
64 | |
65 | enum { semaphore, buffer } interrupt_mode; | |
66 | ||
7ec52ed2 | 67 | struct completion eos; |
62ed6662 | 68 | |
62ed6662 | 69 | int count; |
ab64f663 | 70 | }; |
62ed6662 | 71 | |
62ed6662 BB |
72 | /* The DAQP communicates with the system through a 16 byte I/O window. */ |
73 | ||
74 | #define DAQP_FIFO_SIZE 4096 | |
75 | ||
76 | #define DAQP_FIFO 0 | |
77 | #define DAQP_SCANLIST 1 | |
78 | #define DAQP_CONTROL 2 | |
79 | #define DAQP_STATUS 2 | |
80 | #define DAQP_DIGITAL_IO 3 | |
81 | #define DAQP_PACER_LOW 4 | |
82 | #define DAQP_PACER_MID 5 | |
83 | #define DAQP_PACER_HIGH 6 | |
84 | #define DAQP_COMMAND 7 | |
85 | #define DAQP_DA 8 | |
86 | #define DAQP_TIMER 10 | |
87 | #define DAQP_AUX 15 | |
88 | ||
89 | #define DAQP_SCANLIST_DIFFERENTIAL 0x4000 | |
90 | #define DAQP_SCANLIST_GAIN(x) ((x)<<12) | |
91 | #define DAQP_SCANLIST_CHANNEL(x) ((x)<<8) | |
92 | #define DAQP_SCANLIST_START 0x0080 | |
93 | #define DAQP_SCANLIST_EXT_GAIN(x) ((x)<<4) | |
94 | #define DAQP_SCANLIST_EXT_CHANNEL(x) (x) | |
95 | ||
96 | #define DAQP_CONTROL_PACER_100kHz 0xc0 | |
97 | #define DAQP_CONTROL_PACER_1MHz 0x80 | |
98 | #define DAQP_CONTROL_PACER_5MHz 0x40 | |
99 | #define DAQP_CONTROL_PACER_EXTERNAL 0x00 | |
100 | #define DAQP_CONTORL_EXPANSION 0x20 | |
101 | #define DAQP_CONTROL_EOS_INT_ENABLE 0x10 | |
102 | #define DAQP_CONTROL_FIFO_INT_ENABLE 0x08 | |
103 | #define DAQP_CONTROL_TRIGGER_ONESHOT 0x00 | |
104 | #define DAQP_CONTROL_TRIGGER_CONTINUOUS 0x04 | |
105 | #define DAQP_CONTROL_TRIGGER_INTERNAL 0x00 | |
106 | #define DAQP_CONTROL_TRIGGER_EXTERNAL 0x02 | |
107 | #define DAQP_CONTROL_TRIGGER_RISING 0x00 | |
108 | #define DAQP_CONTROL_TRIGGER_FALLING 0x01 | |
109 | ||
110 | #define DAQP_STATUS_IDLE 0x80 | |
111 | #define DAQP_STATUS_RUNNING 0x40 | |
112 | #define DAQP_STATUS_EVENTS 0x38 | |
113 | #define DAQP_STATUS_DATA_LOST 0x20 | |
114 | #define DAQP_STATUS_END_OF_SCAN 0x10 | |
115 | #define DAQP_STATUS_FIFO_THRESHOLD 0x08 | |
116 | #define DAQP_STATUS_FIFO_FULL 0x04 | |
117 | #define DAQP_STATUS_FIFO_NEARFULL 0x02 | |
118 | #define DAQP_STATUS_FIFO_EMPTY 0x01 | |
119 | ||
120 | #define DAQP_COMMAND_ARM 0x80 | |
121 | #define DAQP_COMMAND_RSTF 0x40 | |
122 | #define DAQP_COMMAND_RSTQ 0x20 | |
123 | #define DAQP_COMMAND_STOP 0x10 | |
124 | #define DAQP_COMMAND_LATCH 0x08 | |
125 | #define DAQP_COMMAND_100kHz 0x00 | |
126 | #define DAQP_COMMAND_50kHz 0x02 | |
127 | #define DAQP_COMMAND_25kHz 0x04 | |
128 | #define DAQP_COMMAND_FIFO_DATA 0x01 | |
129 | #define DAQP_COMMAND_FIFO_PROGRAM 0x00 | |
130 | ||
131 | #define DAQP_AUX_TRIGGER_TTL 0x00 | |
132 | #define DAQP_AUX_TRIGGER_ANALOG 0x80 | |
133 | #define DAQP_AUX_TRIGGER_PRETRIGGER 0x40 | |
134 | #define DAQP_AUX_TIMER_INT_ENABLE 0x20 | |
135 | #define DAQP_AUX_TIMER_RELOAD 0x00 | |
136 | #define DAQP_AUX_TIMER_PAUSE 0x08 | |
137 | #define DAQP_AUX_TIMER_GO 0x10 | |
138 | #define DAQP_AUX_TIMER_GO_EXTERNAL 0x18 | |
139 | #define DAQP_AUX_TIMER_EXTERNAL_SRC 0x04 | |
140 | #define DAQP_AUX_TIMER_INTERNAL_SRC 0x00 | |
141 | #define DAQP_AUX_DA_DIRECT 0x00 | |
142 | #define DAQP_AUX_DA_OVERFLOW 0x01 | |
143 | #define DAQP_AUX_DA_EXTERNAL 0x02 | |
144 | #define DAQP_AUX_DA_PACER 0x03 | |
145 | ||
146 | #define DAQP_AUX_RUNNING 0x80 | |
147 | #define DAQP_AUX_TRIGGERED 0x40 | |
148 | #define DAQP_AUX_DA_BUFFER 0x20 | |
149 | #define DAQP_AUX_TIMER_OVERFLOW 0x10 | |
150 | #define DAQP_AUX_CONVERSION 0x08 | |
151 | #define DAQP_AUX_DATA_LOST 0x04 | |
152 | #define DAQP_AUX_FIFO_NEARFULL 0x02 | |
153 | #define DAQP_AUX_FIFO_EMPTY 0x01 | |
154 | ||
e23fe9a1 HS |
155 | static const struct comedi_lrange range_daqp_ai = { |
156 | 4, { | |
157 | BIP_RANGE(10), | |
158 | BIP_RANGE(5), | |
159 | BIP_RANGE(2.5), | |
160 | BIP_RANGE(1.25) | |
161 | } | |
62ed6662 BB |
162 | }; |
163 | ||
62ed6662 BB |
164 | /* Cancel a running acquisition */ |
165 | ||
da91b269 | 166 | static int daqp_ai_cancel(struct comedi_device *dev, struct comedi_subdevice *s) |
62ed6662 | 167 | { |
1801726e | 168 | struct daqp_private *devpriv = dev->private; |
62ed6662 | 169 | |
1801726e | 170 | if (devpriv->stop) |
62ed6662 | 171 | return -EIO; |
3420f6b4 | 172 | |
62ed6662 BB |
173 | outb(DAQP_COMMAND_STOP, dev->iobase + DAQP_COMMAND); |
174 | ||
175 | /* flush any linguring data in FIFO - superfluous here */ | |
176 | /* outb(DAQP_COMMAND_RSTF, dev->iobase+DAQP_COMMAND); */ | |
177 | ||
1801726e | 178 | devpriv->interrupt_mode = semaphore; |
62ed6662 BB |
179 | |
180 | return 0; | |
181 | } | |
182 | ||
183 | /* Interrupt handler | |
184 | * | |
1801726e HS |
185 | * Operates in one of two modes. If devpriv->interrupt_mode is |
186 | * 'semaphore', just signal the devpriv->eos completion and return | |
62ed6662 BB |
187 | * (one-shot mode). Otherwise (continuous mode), read data in from |
188 | * the card, transfer it to the buffer provided by the higher-level | |
189 | * comedi kernel module, and signal various comedi callback routines, | |
190 | * which run pretty quick. | |
191 | */ | |
e3752a1d | 192 | static enum irqreturn daqp_interrupt(int irq, void *dev_id) |
62ed6662 | 193 | { |
c1271742 | 194 | struct comedi_device *dev = dev_id; |
1801726e | 195 | struct daqp_private *devpriv = dev->private; |
c1271742 | 196 | struct comedi_subdevice *s = dev->read_subdev; |
62ed6662 BB |
197 | int loop_limit = 10000; |
198 | int status; | |
199 | ||
c1271742 | 200 | if (!dev->attached) |
e3752a1d | 201 | return IRQ_NONE; |
62ed6662 | 202 | |
1801726e | 203 | switch (devpriv->interrupt_mode) { |
62ed6662 | 204 | case semaphore: |
1801726e | 205 | complete(&devpriv->eos); |
62ed6662 BB |
206 | break; |
207 | ||
208 | case buffer: | |
62ed6662 | 209 | while (!((status = inb(dev->iobase + DAQP_STATUS)) |
0a85b6f0 | 210 | & DAQP_STATUS_FIFO_EMPTY)) { |
8bab0d68 | 211 | unsigned short data; |
62ed6662 BB |
212 | |
213 | if (status & DAQP_STATUS_DATA_LOST) { | |
214 | s->async->events |= | |
0a85b6f0 | 215 | COMEDI_CB_EOA | COMEDI_CB_OVERFLOW; |
53f63dc7 | 216 | dev_warn(dev->class_dev, "data lost\n"); |
62ed6662 BB |
217 | break; |
218 | } | |
219 | ||
220 | data = inb(dev->iobase + DAQP_FIFO); | |
221 | data |= inb(dev->iobase + DAQP_FIFO) << 8; | |
222 | data ^= 0x8000; | |
223 | ||
3672effd | 224 | comedi_buf_put(s, data); |
62ed6662 BB |
225 | |
226 | /* If there's a limit, decrement it | |
227 | * and stop conversion if zero | |
228 | */ | |
229 | ||
1801726e HS |
230 | if (devpriv->count > 0) { |
231 | devpriv->count--; | |
232 | if (devpriv->count == 0) { | |
62ed6662 BB |
233 | s->async->events |= COMEDI_CB_EOA; |
234 | break; | |
235 | } | |
236 | } | |
237 | ||
238 | if ((loop_limit--) <= 0) | |
239 | break; | |
240 | } | |
241 | ||
242 | if (loop_limit <= 0) { | |
ce3ed9f0 YT |
243 | dev_warn(dev->class_dev, |
244 | "loop_limit reached in daqp_interrupt()\n"); | |
62ed6662 BB |
245 | s->async->events |= COMEDI_CB_EOA | COMEDI_CB_ERROR; |
246 | } | |
247 | ||
248 | s->async->events |= COMEDI_CB_BLOCK; | |
249 | ||
fb6aa250 | 250 | cfc_handle_events(dev, s); |
62ed6662 | 251 | } |
e3752a1d | 252 | return IRQ_HANDLED; |
62ed6662 BB |
253 | } |
254 | ||
bd7807f9 HS |
255 | static void daqp_ai_set_one_scanlist_entry(struct comedi_device *dev, |
256 | unsigned int chanspec, | |
257 | int start) | |
258 | { | |
259 | unsigned int chan = CR_CHAN(chanspec); | |
260 | unsigned int range = CR_RANGE(chanspec); | |
261 | unsigned int aref = CR_AREF(chanspec); | |
262 | unsigned int val; | |
263 | ||
264 | val = DAQP_SCANLIST_CHANNEL(chan) | DAQP_SCANLIST_GAIN(range); | |
265 | ||
266 | if (aref == AREF_DIFF) | |
267 | val |= DAQP_SCANLIST_DIFFERENTIAL; | |
268 | ||
269 | if (start) | |
270 | val |= DAQP_SCANLIST_START; | |
271 | ||
272 | outb(val & 0xff, dev->iobase + DAQP_SCANLIST); | |
273 | outb((val >> 8) & 0xff, dev->iobase + DAQP_SCANLIST); | |
274 | } | |
275 | ||
62ed6662 BB |
276 | /* One-shot analog data acquisition routine */ |
277 | ||
0a85b6f0 MT |
278 | static int daqp_ai_insn_read(struct comedi_device *dev, |
279 | struct comedi_subdevice *s, | |
280 | struct comedi_insn *insn, unsigned int *data) | |
62ed6662 | 281 | { |
1801726e | 282 | struct daqp_private *devpriv = dev->private; |
62ed6662 BB |
283 | int i; |
284 | int v; | |
285 | int counter = 10000; | |
286 | ||
1801726e | 287 | if (devpriv->stop) |
62ed6662 | 288 | return -EIO; |
3420f6b4 | 289 | |
62ed6662 BB |
290 | /* Stop any running conversion */ |
291 | daqp_ai_cancel(dev, s); | |
292 | ||
293 | outb(0, dev->iobase + DAQP_AUX); | |
294 | ||
295 | /* Reset scan list queue */ | |
296 | outb(DAQP_COMMAND_RSTQ, dev->iobase + DAQP_COMMAND); | |
297 | ||
298 | /* Program one scan list entry */ | |
bd7807f9 | 299 | daqp_ai_set_one_scanlist_entry(dev, insn->chanspec, 1); |
62ed6662 BB |
300 | |
301 | /* Reset data FIFO (see page 28 of DAQP User's Manual) */ | |
302 | ||
303 | outb(DAQP_COMMAND_RSTF, dev->iobase + DAQP_COMMAND); | |
304 | ||
305 | /* Set trigger */ | |
306 | ||
307 | v = DAQP_CONTROL_TRIGGER_ONESHOT | DAQP_CONTROL_TRIGGER_INTERNAL | |
0a85b6f0 | 308 | | DAQP_CONTROL_PACER_100kHz | DAQP_CONTROL_EOS_INT_ENABLE; |
62ed6662 BB |
309 | |
310 | outb(v, dev->iobase + DAQP_CONTROL); | |
311 | ||
25985edc | 312 | /* Reset any pending interrupts (my card has a tendency to require |
62ed6662 BB |
313 | * require multiple reads on the status register to achieve this) |
314 | */ | |
315 | ||
316 | while (--counter | |
543a09e9 YT |
317 | && (inb(dev->iobase + DAQP_STATUS) & DAQP_STATUS_EVENTS)) |
318 | ; | |
62ed6662 | 319 | if (!counter) { |
53f63dc7 YT |
320 | dev_err(dev->class_dev, |
321 | "couldn't clear interrupts in status register\n"); | |
62ed6662 BB |
322 | return -1; |
323 | } | |
324 | ||
1801726e HS |
325 | init_completion(&devpriv->eos); |
326 | devpriv->interrupt_mode = semaphore; | |
62ed6662 BB |
327 | |
328 | for (i = 0; i < insn->n; i++) { | |
329 | ||
330 | /* Start conversion */ | |
331 | outb(DAQP_COMMAND_ARM | DAQP_COMMAND_FIFO_DATA, | |
0a85b6f0 | 332 | dev->iobase + DAQP_COMMAND); |
62ed6662 | 333 | |
7ec52ed2 | 334 | /* Wait for interrupt service routine to unblock completion */ |
62ed6662 | 335 | /* Maybe could use a timeout here, but it's interruptible */ |
1801726e | 336 | if (wait_for_completion_interruptible(&devpriv->eos)) |
62ed6662 BB |
337 | return -EINTR; |
338 | ||
339 | data[i] = inb(dev->iobase + DAQP_FIFO); | |
340 | data[i] |= inb(dev->iobase + DAQP_FIFO) << 8; | |
341 | data[i] ^= 0x8000; | |
342 | } | |
343 | ||
344 | return insn->n; | |
345 | } | |
346 | ||
347 | /* This function converts ns nanoseconds to a counter value suitable | |
348 | * for programming the device. We always use the DAQP's 5 MHz clock, | |
349 | * which with its 24-bit counter, allows values up to 84 seconds. | |
350 | * Also, the function adjusts ns so that it cooresponds to the actual | |
351 | * time that the device will use. | |
352 | */ | |
353 | ||
354 | static int daqp_ns_to_timer(unsigned int *ns, int round) | |
355 | { | |
356 | int timer; | |
357 | ||
358 | timer = *ns / 200; | |
359 | *ns = timer * 200; | |
360 | ||
361 | return timer; | |
362 | } | |
363 | ||
364 | /* cmdtest tests a particular command to see if it is valid. | |
365 | * Using the cmdtest ioctl, a user can create a valid cmd | |
366 | * and then have it executed by the cmd ioctl. | |
367 | * | |
368 | * cmdtest returns 1,2,3,4 or 0, depending on which tests | |
369 | * the command passes. | |
370 | */ | |
371 | ||
0a85b6f0 MT |
372 | static int daqp_ai_cmdtest(struct comedi_device *dev, |
373 | struct comedi_subdevice *s, struct comedi_cmd *cmd) | |
62ed6662 BB |
374 | { |
375 | int err = 0; | |
376 | int tmp; | |
377 | ||
27020ffe | 378 | /* Step 1 : check if triggers are trivially valid */ |
62ed6662 | 379 | |
27020ffe HS |
380 | err |= cfc_check_trigger_src(&cmd->start_src, TRIG_NOW); |
381 | err |= cfc_check_trigger_src(&cmd->scan_begin_src, | |
382 | TRIG_TIMER | TRIG_FOLLOW); | |
383 | err |= cfc_check_trigger_src(&cmd->convert_src, | |
384 | TRIG_TIMER | TRIG_NOW); | |
385 | err |= cfc_check_trigger_src(&cmd->scan_end_src, TRIG_COUNT); | |
386 | err |= cfc_check_trigger_src(&cmd->stop_src, TRIG_COUNT | TRIG_NONE); | |
62ed6662 BB |
387 | |
388 | if (err) | |
389 | return 1; | |
390 | ||
27020ffe | 391 | /* Step 2a : make sure trigger sources are unique */ |
62ed6662 | 392 | |
27020ffe HS |
393 | err |= cfc_check_trigger_is_unique(cmd->scan_begin_src); |
394 | err |= cfc_check_trigger_is_unique(cmd->convert_src); | |
395 | err |= cfc_check_trigger_is_unique(cmd->stop_src); | |
396 | ||
397 | /* Step 2b : and mutually compatible */ | |
62ed6662 BB |
398 | |
399 | if (err) | |
400 | return 2; | |
401 | ||
42cae4a1 HS |
402 | /* Step 3: check if arguments are trivially valid */ |
403 | ||
404 | err |= cfc_check_trigger_arg_is(&cmd->start_arg, 0); | |
62ed6662 | 405 | |
62ed6662 BB |
406 | #define MAX_SPEED 10000 /* 100 kHz - in nanoseconds */ |
407 | ||
42cae4a1 HS |
408 | if (cmd->scan_begin_src == TRIG_TIMER) |
409 | err |= cfc_check_trigger_arg_min(&cmd->scan_begin_arg, | |
410 | MAX_SPEED); | |
62ed6662 BB |
411 | |
412 | /* If both scan_begin and convert are both timer values, the only | |
413 | * way that can make sense is if the scan time is the number of | |
414 | * conversions times the convert time | |
415 | */ | |
416 | ||
417 | if (cmd->scan_begin_src == TRIG_TIMER && cmd->convert_src == TRIG_TIMER | |
0a85b6f0 | 418 | && cmd->scan_begin_arg != cmd->convert_arg * cmd->scan_end_arg) { |
42cae4a1 | 419 | err |= -EINVAL; |
62ed6662 BB |
420 | } |
421 | ||
42cae4a1 HS |
422 | if (cmd->convert_src == TRIG_TIMER) |
423 | err |= cfc_check_trigger_arg_min(&cmd->convert_arg, MAX_SPEED); | |
62ed6662 | 424 | |
42cae4a1 HS |
425 | err |= cfc_check_trigger_arg_is(&cmd->scan_end_arg, cmd->chanlist_len); |
426 | ||
427 | if (cmd->stop_src == TRIG_COUNT) | |
428 | err |= cfc_check_trigger_arg_max(&cmd->stop_arg, 0x00ffffff); | |
429 | else /* TRIG_NONE */ | |
430 | err |= cfc_check_trigger_arg_is(&cmd->stop_arg, 0); | |
62ed6662 BB |
431 | |
432 | if (err) | |
433 | return 3; | |
434 | ||
435 | /* step 4: fix up any arguments */ | |
436 | ||
437 | if (cmd->scan_begin_src == TRIG_TIMER) { | |
438 | tmp = cmd->scan_begin_arg; | |
439 | daqp_ns_to_timer(&cmd->scan_begin_arg, | |
0a85b6f0 | 440 | cmd->flags & TRIG_ROUND_MASK); |
62ed6662 BB |
441 | if (tmp != cmd->scan_begin_arg) |
442 | err++; | |
443 | } | |
444 | ||
445 | if (cmd->convert_src == TRIG_TIMER) { | |
446 | tmp = cmd->convert_arg; | |
447 | daqp_ns_to_timer(&cmd->convert_arg, | |
0a85b6f0 | 448 | cmd->flags & TRIG_ROUND_MASK); |
62ed6662 BB |
449 | if (tmp != cmd->convert_arg) |
450 | err++; | |
451 | } | |
452 | ||
453 | if (err) | |
454 | return 4; | |
455 | ||
456 | return 0; | |
457 | } | |
458 | ||
da91b269 | 459 | static int daqp_ai_cmd(struct comedi_device *dev, struct comedi_subdevice *s) |
62ed6662 | 460 | { |
1801726e | 461 | struct daqp_private *devpriv = dev->private; |
ea6d0d4c | 462 | struct comedi_cmd *cmd = &s->async->cmd; |
e3752a1d | 463 | int counter; |
62ed6662 BB |
464 | int scanlist_start_on_every_entry; |
465 | int threshold; | |
466 | ||
467 | int i; | |
468 | int v; | |
469 | ||
1801726e | 470 | if (devpriv->stop) |
62ed6662 | 471 | return -EIO; |
3420f6b4 | 472 | |
62ed6662 BB |
473 | /* Stop any running conversion */ |
474 | daqp_ai_cancel(dev, s); | |
475 | ||
476 | outb(0, dev->iobase + DAQP_AUX); | |
477 | ||
478 | /* Reset scan list queue */ | |
479 | outb(DAQP_COMMAND_RSTQ, dev->iobase + DAQP_COMMAND); | |
480 | ||
481 | /* Program pacer clock | |
482 | * | |
483 | * There's two modes we can operate in. If convert_src is | |
484 | * TRIG_TIMER, then convert_arg specifies the time between | |
485 | * each conversion, so we program the pacer clock to that | |
486 | * frequency and set the SCANLIST_START bit on every scanlist | |
487 | * entry. Otherwise, convert_src is TRIG_NOW, which means | |
488 | * we want the fastest possible conversions, scan_begin_src | |
489 | * is TRIG_TIMER, and scan_begin_arg specifies the time between | |
490 | * each scan, so we program the pacer clock to this frequency | |
491 | * and only set the SCANLIST_START bit on the first entry. | |
492 | */ | |
493 | ||
494 | if (cmd->convert_src == TRIG_TIMER) { | |
e3752a1d | 495 | counter = daqp_ns_to_timer(&cmd->convert_arg, |
0a85b6f0 | 496 | cmd->flags & TRIG_ROUND_MASK); |
62ed6662 BB |
497 | outb(counter & 0xff, dev->iobase + DAQP_PACER_LOW); |
498 | outb((counter >> 8) & 0xff, dev->iobase + DAQP_PACER_MID); | |
499 | outb((counter >> 16) & 0xff, dev->iobase + DAQP_PACER_HIGH); | |
500 | scanlist_start_on_every_entry = 1; | |
501 | } else { | |
e3752a1d | 502 | counter = daqp_ns_to_timer(&cmd->scan_begin_arg, |
0a85b6f0 | 503 | cmd->flags & TRIG_ROUND_MASK); |
62ed6662 BB |
504 | outb(counter & 0xff, dev->iobase + DAQP_PACER_LOW); |
505 | outb((counter >> 8) & 0xff, dev->iobase + DAQP_PACER_MID); | |
506 | outb((counter >> 16) & 0xff, dev->iobase + DAQP_PACER_HIGH); | |
507 | scanlist_start_on_every_entry = 0; | |
508 | } | |
509 | ||
510 | /* Program scan list */ | |
62ed6662 | 511 | for (i = 0; i < cmd->chanlist_len; i++) { |
bd7807f9 | 512 | int start = (i == 0 || scanlist_start_on_every_entry); |
62ed6662 | 513 | |
bd7807f9 | 514 | daqp_ai_set_one_scanlist_entry(dev, cmd->chanlist[i], start); |
62ed6662 BB |
515 | } |
516 | ||
517 | /* Now it's time to program the FIFO threshold, basically the | |
518 | * number of samples the card will buffer before it interrupts | |
519 | * the CPU. | |
520 | * | |
521 | * If we don't have a stop count, then use half the size of | |
522 | * the FIFO (the manufacturer's recommendation). Consider | |
523 | * that the FIFO can hold 2K samples (4K bytes). With the | |
524 | * threshold set at half the FIFO size, we have a margin of | |
525 | * error of 1024 samples. At the chip's maximum sample rate | |
526 | * of 100,000 Hz, the CPU would have to delay interrupt | |
527 | * service for a full 10 milliseconds in order to lose data | |
528 | * here (as opposed to higher up in the kernel). I've never | |
529 | * seen it happen. However, for slow sample rates it may | |
530 | * buffer too much data and introduce too much delay for the | |
531 | * user application. | |
532 | * | |
533 | * If we have a stop count, then things get more interesting. | |
534 | * If the stop count is less than the FIFO size (actually | |
535 | * three-quarters of the FIFO size - see below), we just use | |
536 | * the stop count itself as the threshold, the card interrupts | |
537 | * us when that many samples have been taken, and we kill the | |
538 | * acquisition at that point and are done. If the stop count | |
539 | * is larger than that, then we divide it by 2 until it's less | |
540 | * than three quarters of the FIFO size (we always leave the | |
541 | * top quarter of the FIFO as protection against sluggish CPU | |
542 | * interrupt response) and use that as the threshold. So, if | |
543 | * the stop count is 4000 samples, we divide by two twice to | |
544 | * get 1000 samples, use that as the threshold, take four | |
545 | * interrupts to get our 4000 samples and are done. | |
546 | * | |
547 | * The algorithm could be more clever. For example, if 81000 | |
548 | * samples are requested, we could set the threshold to 1500 | |
549 | * samples and take 54 interrupts to get 81000. But 54 isn't | |
550 | * a power of two, so this algorithm won't find that option. | |
551 | * Instead, it'll set the threshold at 1266 and take 64 | |
552 | * interrupts to get 81024 samples, of which the last 24 will | |
553 | * be discarded... but we won't get the last interrupt until | |
554 | * they've been collected. To find the first option, the | |
555 | * computer could look at the prime decomposition of the | |
556 | * sample count (81000 = 3^4 * 5^3 * 2^3) and factor it into a | |
557 | * threshold (1500 = 3 * 5^3 * 2^2) and an interrupt count (54 | |
558 | * = 3^3 * 2). Hmmm... a one-line while loop or prime | |
559 | * decomposition of integers... I'll leave it the way it is. | |
560 | * | |
561 | * I'll also note a mini-race condition before ignoring it in | |
562 | * the code. Let's say we're taking 4000 samples, as before. | |
563 | * After 1000 samples, we get an interrupt. But before that | |
564 | * interrupt is completely serviced, another sample is taken | |
565 | * and loaded into the FIFO. Since the interrupt handler | |
566 | * empties the FIFO before returning, it will read 1001 samples. | |
567 | * If that happens four times, we'll end up taking 4004 samples, | |
568 | * not 4000. The interrupt handler will discard the extra four | |
569 | * samples (by halting the acquisition with four samples still | |
570 | * in the FIFO), but we will have to wait for them. | |
571 | * | |
572 | * In short, this code works pretty well, but for either of | |
573 | * the two reasons noted, might end up waiting for a few more | |
574 | * samples than actually requested. Shouldn't make too much | |
575 | * of a difference. | |
576 | */ | |
577 | ||
578 | /* Save away the number of conversions we should perform, and | |
579 | * compute the FIFO threshold (in bytes, not samples - that's | |
1801726e | 580 | * why we multiple devpriv->count by 2 = sizeof(sample)) |
62ed6662 BB |
581 | */ |
582 | ||
583 | if (cmd->stop_src == TRIG_COUNT) { | |
1801726e HS |
584 | devpriv->count = cmd->stop_arg * cmd->scan_end_arg; |
585 | threshold = 2 * devpriv->count; | |
62ed6662 BB |
586 | while (threshold > DAQP_FIFO_SIZE * 3 / 4) |
587 | threshold /= 2; | |
588 | } else { | |
1801726e | 589 | devpriv->count = -1; |
62ed6662 BB |
590 | threshold = DAQP_FIFO_SIZE / 2; |
591 | } | |
592 | ||
593 | /* Reset data FIFO (see page 28 of DAQP User's Manual) */ | |
594 | ||
595 | outb(DAQP_COMMAND_RSTF, dev->iobase + DAQP_COMMAND); | |
596 | ||
597 | /* Set FIFO threshold. First two bytes are near-empty | |
598 | * threshold, which is unused; next two bytes are near-full | |
599 | * threshold. We computed the number of bytes we want in the | |
600 | * FIFO when the interrupt is generated, what the card wants | |
601 | * is actually the number of available bytes left in the FIFO | |
602 | * when the interrupt is to happen. | |
603 | */ | |
604 | ||
605 | outb(0x00, dev->iobase + DAQP_FIFO); | |
606 | outb(0x00, dev->iobase + DAQP_FIFO); | |
607 | ||
608 | outb((DAQP_FIFO_SIZE - threshold) & 0xff, dev->iobase + DAQP_FIFO); | |
609 | outb((DAQP_FIFO_SIZE - threshold) >> 8, dev->iobase + DAQP_FIFO); | |
610 | ||
611 | /* Set trigger */ | |
612 | ||
613 | v = DAQP_CONTROL_TRIGGER_CONTINUOUS | DAQP_CONTROL_TRIGGER_INTERNAL | |
0a85b6f0 | 614 | | DAQP_CONTROL_PACER_5MHz | DAQP_CONTROL_FIFO_INT_ENABLE; |
62ed6662 BB |
615 | |
616 | outb(v, dev->iobase + DAQP_CONTROL); | |
617 | ||
25985edc | 618 | /* Reset any pending interrupts (my card has a tendency to require |
62ed6662 BB |
619 | * require multiple reads on the status register to achieve this) |
620 | */ | |
e3752a1d | 621 | counter = 100; |
62ed6662 | 622 | while (--counter |
543a09e9 YT |
623 | && (inb(dev->iobase + DAQP_STATUS) & DAQP_STATUS_EVENTS)) |
624 | ; | |
62ed6662 | 625 | if (!counter) { |
ce3ed9f0 YT |
626 | dev_err(dev->class_dev, |
627 | "couldn't clear interrupts in status register\n"); | |
62ed6662 BB |
628 | return -1; |
629 | } | |
630 | ||
1801726e | 631 | devpriv->interrupt_mode = buffer; |
62ed6662 BB |
632 | |
633 | /* Start conversion */ | |
634 | outb(DAQP_COMMAND_ARM | DAQP_COMMAND_FIFO_DATA, | |
0a85b6f0 | 635 | dev->iobase + DAQP_COMMAND); |
62ed6662 BB |
636 | |
637 | return 0; | |
638 | } | |
639 | ||
0a85b6f0 MT |
640 | static int daqp_ao_insn_write(struct comedi_device *dev, |
641 | struct comedi_subdevice *s, | |
d35dcc89 HS |
642 | struct comedi_insn *insn, |
643 | unsigned int *data) | |
62ed6662 | 644 | { |
1801726e | 645 | struct daqp_private *devpriv = dev->private; |
d35dcc89 HS |
646 | unsigned int chan = CR_CHAN(insn->chanspec); |
647 | unsigned int val; | |
648 | int i; | |
62ed6662 | 649 | |
1801726e | 650 | if (devpriv->stop) |
62ed6662 | 651 | return -EIO; |
62ed6662 | 652 | |
62ed6662 BB |
653 | /* Make sure D/A update mode is direct update */ |
654 | outb(0, dev->iobase + DAQP_AUX); | |
655 | ||
d35dcc89 HS |
656 | for (i = 0; i > insn->n; i++) { |
657 | val = data[0]; | |
658 | val &= 0x0fff; | |
659 | val ^= 0x0800; /* Flip the sign */ | |
660 | val |= (chan << 12); | |
62ed6662 | 661 | |
d35dcc89 HS |
662 | outw(val, dev->iobase + DAQP_DA); |
663 | } | |
664 | ||
665 | return insn->n; | |
62ed6662 BB |
666 | } |
667 | ||
62100fef | 668 | static int daqp_di_insn_bits(struct comedi_device *dev, |
0a85b6f0 | 669 | struct comedi_subdevice *s, |
62100fef HS |
670 | struct comedi_insn *insn, |
671 | unsigned int *data) | |
62ed6662 | 672 | { |
1801726e | 673 | struct daqp_private *devpriv = dev->private; |
62ed6662 | 674 | |
1801726e | 675 | if (devpriv->stop) |
62ed6662 | 676 | return -EIO; |
62ed6662 BB |
677 | |
678 | data[0] = inb(dev->iobase + DAQP_DIGITAL_IO); | |
679 | ||
62100fef | 680 | return insn->n; |
62ed6662 BB |
681 | } |
682 | ||
6a911d8a HS |
683 | static int daqp_do_insn_bits(struct comedi_device *dev, |
684 | struct comedi_subdevice *s, | |
685 | struct comedi_insn *insn, | |
686 | unsigned int *data) | |
62ed6662 | 687 | { |
1801726e | 688 | struct daqp_private *devpriv = dev->private; |
62ed6662 | 689 | |
1801726e | 690 | if (devpriv->stop) |
62ed6662 | 691 | return -EIO; |
62ed6662 | 692 | |
97f4289a | 693 | if (comedi_dio_update_state(s, data)) |
6a911d8a | 694 | outb(s->state, dev->iobase + DAQP_DIGITAL_IO); |
6a911d8a HS |
695 | |
696 | data[1] = s->state; | |
697 | ||
698 | return insn->n; | |
62ed6662 BB |
699 | } |
700 | ||
c04edbf2 HS |
701 | static int daqp_auto_attach(struct comedi_device *dev, |
702 | unsigned long context) | |
62ed6662 | 703 | { |
c04edbf2 | 704 | struct pcmcia_device *link = comedi_to_pcmcia_dev(dev); |
1801726e | 705 | struct daqp_private *devpriv; |
34c43922 | 706 | struct comedi_subdevice *s; |
c65c64d0 | 707 | int ret; |
62ed6662 | 708 | |
0bdab509 | 709 | devpriv = comedi_alloc_devpriv(dev, sizeof(*devpriv)); |
1801726e | 710 | if (!devpriv) |
c04edbf2 | 711 | return -ENOMEM; |
62ed6662 | 712 | |
c04edbf2 | 713 | link->config_flags |= CONF_AUTO_SET_IO | CONF_ENABLE_IRQ; |
a9d50943 | 714 | ret = comedi_pcmcia_enable(dev, NULL); |
c04edbf2 HS |
715 | if (ret) |
716 | return ret; | |
87fe1452 | 717 | dev->iobase = link->resource[0]->start; |
62ed6662 | 718 | |
c1271742 | 719 | link->priv = dev; |
c04edbf2 HS |
720 | ret = pcmcia_request_irq(link, daqp_interrupt); |
721 | if (ret) | |
722 | return ret; | |
723 | ||
2f0b9d08 | 724 | ret = comedi_alloc_subdevices(dev, 4); |
8b6c5694 | 725 | if (ret) |
62ed6662 BB |
726 | return ret; |
727 | ||
123c0e03 | 728 | s = &dev->subdevices[0]; |
62ed6662 | 729 | dev->read_subdev = s; |
b7c0afa4 HS |
730 | s->type = COMEDI_SUBD_AI; |
731 | s->subdev_flags = SDF_READABLE | SDF_GROUND | SDF_DIFF | SDF_CMD_READ; | |
732 | s->n_chan = 8; | |
733 | s->len_chanlist = 2048; | |
734 | s->maxdata = 0xffff; | |
735 | s->range_table = &range_daqp_ai; | |
736 | s->insn_read = daqp_ai_insn_read; | |
737 | s->do_cmdtest = daqp_ai_cmdtest; | |
738 | s->do_cmd = daqp_ai_cmd; | |
739 | s->cancel = daqp_ai_cancel; | |
62ed6662 | 740 | |
123c0e03 | 741 | s = &dev->subdevices[1]; |
b7c0afa4 HS |
742 | s->type = COMEDI_SUBD_AO; |
743 | s->subdev_flags = SDF_WRITEABLE; | |
744 | s->n_chan = 2; | |
745 | s->maxdata = 0x0fff; | |
746 | s->range_table = &range_bipolar5; | |
747 | s->insn_write = daqp_ao_insn_write; | |
62ed6662 | 748 | |
123c0e03 | 749 | s = &dev->subdevices[2]; |
b7c0afa4 HS |
750 | s->type = COMEDI_SUBD_DI; |
751 | s->subdev_flags = SDF_READABLE; | |
752 | s->n_chan = 1; | |
62100fef HS |
753 | s->maxdata = 1; |
754 | s->insn_bits = daqp_di_insn_bits; | |
62ed6662 | 755 | |
123c0e03 | 756 | s = &dev->subdevices[3]; |
b7c0afa4 HS |
757 | s->type = COMEDI_SUBD_DO; |
758 | s->subdev_flags = SDF_WRITEABLE; | |
759 | s->n_chan = 1; | |
6a911d8a HS |
760 | s->maxdata = 1; |
761 | s->insn_bits = daqp_do_insn_bits; | |
62ed6662 | 762 | |
b7c0afa4 | 763 | return 0; |
62ed6662 BB |
764 | } |
765 | ||
d1db2a41 HS |
766 | static struct comedi_driver driver_daqp = { |
767 | .driver_name = "quatech_daqp_cs", | |
768 | .module = THIS_MODULE, | |
c04edbf2 | 769 | .auto_attach = daqp_auto_attach, |
25736670 | 770 | .detach = comedi_pcmcia_disable, |
d1db2a41 HS |
771 | }; |
772 | ||
d1db2a41 | 773 | static int daqp_cs_suspend(struct pcmcia_device *link) |
62ed6662 | 774 | { |
c1271742 | 775 | struct comedi_device *dev = link->priv; |
1801726e | 776 | struct daqp_private *devpriv = dev ? dev->private : NULL; |
62ed6662 | 777 | |
d1db2a41 | 778 | /* Mark the device as stopped, to block IO until later */ |
1801726e HS |
779 | if (devpriv) |
780 | devpriv->stop = 1; | |
c1271742 | 781 | |
d1db2a41 HS |
782 | return 0; |
783 | } | |
62ed6662 | 784 | |
d1db2a41 HS |
785 | static int daqp_cs_resume(struct pcmcia_device *link) |
786 | { | |
c1271742 | 787 | struct comedi_device *dev = link->priv; |
1801726e | 788 | struct daqp_private *devpriv = dev ? dev->private : NULL; |
62ed6662 | 789 | |
1801726e HS |
790 | if (devpriv) |
791 | devpriv->stop = 0; | |
62ed6662 BB |
792 | |
793 | return 0; | |
d1db2a41 | 794 | } |
62ed6662 | 795 | |
d1db2a41 | 796 | static int daqp_cs_attach(struct pcmcia_device *link) |
62ed6662 | 797 | { |
c04edbf2 | 798 | return comedi_pcmcia_auto_config(link, &driver_daqp); |
62ed6662 BB |
799 | } |
800 | ||
2202a5a7 | 801 | static const struct pcmcia_device_id daqp_cs_id_table[] = { |
62ed6662 BB |
802 | PCMCIA_DEVICE_MANF_CARD(0x0137, 0x0027), |
803 | PCMCIA_DEVICE_NULL | |
804 | }; | |
62ed6662 BB |
805 | MODULE_DEVICE_TABLE(pcmcia, daqp_cs_id_table); |
806 | ||
e3752a1d | 807 | static struct pcmcia_driver daqp_cs_driver = { |
433a0e22 HS |
808 | .name = "quatech_daqp_cs", |
809 | .owner = THIS_MODULE, | |
810 | .id_table = daqp_cs_id_table, | |
811 | .probe = daqp_cs_attach, | |
c04edbf2 | 812 | .remove = comedi_pcmcia_auto_unconfig, |
433a0e22 HS |
813 | .suspend = daqp_cs_suspend, |
814 | .resume = daqp_cs_resume, | |
62ed6662 | 815 | }; |
f3493a97 | 816 | module_comedi_pcmcia_driver(driver_daqp, daqp_cs_driver); |
04c59041 HS |
817 | |
818 | MODULE_DESCRIPTION("Comedi driver for Quatech DAQP PCMCIA data capture cards"); | |
819 | MODULE_AUTHOR("Brent Baccala <baccala@freesoft.org>"); | |
820 | MODULE_LICENSE("GPL"); |