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ed811a32 HS |
1 | /* |
2 | * quatech_daqp_cs.c | |
3 | * Quatech DAQP PCMCIA data capture cards COMEDI client driver | |
4 | * Copyright (C) 2000, 2003 Brent Baccala <baccala@freesoft.org> | |
5 | * The DAQP interface code in this file is released into the public domain. | |
6 | * | |
7 | * COMEDI - Linux Control and Measurement Device Interface | |
8 | * Copyright (C) 1998 David A. Schleef <ds@schleef.org> | |
9 | * http://www.comedi.org/ | |
10 | * | |
11 | * Documentation for the DAQP PCMCIA cards can be found on Quatech's site: | |
12 | * ftp://ftp.quatech.com/Manuals/daqp-208.pdf | |
13 | * | |
14 | * This manual is for both the DAQP-208 and the DAQP-308. | |
15 | * | |
16 | * What works: | |
17 | * - A/D conversion | |
18 | * - 8 channels | |
19 | * - 4 gain ranges | |
20 | * - ground ref or differential | |
21 | * - single-shot and timed both supported | |
22 | * - D/A conversion, single-shot | |
23 | * - digital I/O | |
24 | * | |
25 | * What doesn't: | |
26 | * - any kind of triggering - external or D/A channel 1 | |
27 | * - the card's optional expansion board | |
28 | * - the card's timer (for anything other than A/D conversion) | |
29 | * - D/A update modes other than immediate (i.e, timed) | |
30 | * - fancier timing modes | |
31 | * - setting card's FIFO buffer thresholds to anything but default | |
32 | */ | |
62ed6662 BB |
33 | |
34 | /* | |
ed811a32 HS |
35 | * Driver: quatech_daqp_cs |
36 | * Description: Quatech DAQP PCMCIA data capture cards | |
37 | * Devices: [Quatech] DAQP-208 (daqp), DAQP-308 | |
38 | * Author: Brent Baccala <baccala@freesoft.org> | |
39 | * Status: works | |
40 | */ | |
62ed6662 | 41 | |
ce157f80 | 42 | #include <linux/module.h> |
3142788b | 43 | #include <linux/semaphore.h> |
7ec52ed2 AIB |
44 | #include <linux/completion.h> |
45 | ||
f0dff1a4 | 46 | #include "../comedi_pcmcia.h" |
27020ffe | 47 | |
bd9d00f1 HS |
48 | /* |
49 | * Register I/O map | |
50 | * | |
51 | * The D/A and timer registers can be accessed with 16-bit or 8-bit I/O | |
52 | * instructions. All other registers can only use 8-bit instructions. | |
53 | * | |
54 | * The FIFO and scanlist registers require two 8-bit instructions to | |
55 | * access the 16-bit data. Data is transferred LSB then MSB. | |
56 | */ | |
57 | #define DAQP_AI_FIFO_REG 0x00 | |
77e546de | 58 | |
bd9d00f1 | 59 | #define DAQP_SCANLIST_REG 0x01 |
77e546de HS |
60 | #define DAQP_SCANLIST_DIFFERENTIAL BIT(14) |
61 | #define DAQP_SCANLIST_GAIN(x) (((x) & 0x3) << 12) | |
62 | #define DAQP_SCANLIST_CHANNEL(x) (((x) & 0xf) << 8) | |
63 | #define DAQP_SCANLIST_START BIT(7) | |
64 | #define DAQP_SCANLIST_EXT_GAIN(x) (((x) & 0x3) << 4) | |
65 | #define DAQP_SCANLIST_EXT_CHANNEL(x) (((x) & 0xf) << 0) | |
66 | ||
bd9d00f1 | 67 | #define DAQP_CTRL_REG 0x02 |
b0f9b0ad HS |
68 | #define DAQP_CTRL_PACER_CLK(x) (((x) & 0x3) << 6) |
69 | #define DAQP_CTRL_PACER_CLK_EXT DAQP_CTRL_PACER_CLK(0) | |
70 | #define DAQP_CTRL_PACER_CLK_5MHZ DAQP_CTRL_PACER_CLK(1) | |
71 | #define DAQP_CTRL_PACER_CLK_1MHZ DAQP_CTRL_PACER_CLK(2) | |
72 | #define DAQP_CTRL_PACER_CLK_100KHZ DAQP_CTRL_PACER_CLK(3) | |
73 | #define DAQP_CTRL_EXPANSION BIT(5) | |
74 | #define DAQP_CTRL_EOS_INT_ENA BIT(4) | |
75 | #define DAQP_CTRL_FIFO_INT_ENA BIT(3) | |
76 | #define DAQP_CTRL_TRIG_MODE BIT(2) /* 0=one-shot; 1=continuous */ | |
77 | #define DAQP_CTRL_TRIG_SRC BIT(1) /* 0=internal; 1=external */ | |
78 | #define DAQP_CTRL_TRIG_EDGE BIT(0) /* 0=rising; 1=falling */ | |
79 | ||
bd9d00f1 HS |
80 | #define DAQP_STATUS_REG 0x02 |
81 | #define DAQP_DI_REG 0x03 | |
82 | #define DAQP_DO_REG 0x03 | |
83 | #define DAQP_PACER_LOW_REG 0x04 | |
84 | #define DAQP_PACER_MID_REG 0x05 | |
85 | #define DAQP_PACER_HIGH_REG 0x06 | |
86 | #define DAQP_CMD_REG 0x07 | |
87 | #define DAQP_AO_REG 0x08 | |
88 | #define DAQP_TIMER_REG 0x0a | |
89 | #define DAQP_AUX_REG 0x0f | |
62ed6662 | 90 | |
62ed6662 BB |
91 | #define DAQP_STATUS_IDLE 0x80 |
92 | #define DAQP_STATUS_RUNNING 0x40 | |
93 | #define DAQP_STATUS_EVENTS 0x38 | |
94 | #define DAQP_STATUS_DATA_LOST 0x20 | |
95 | #define DAQP_STATUS_END_OF_SCAN 0x10 | |
96 | #define DAQP_STATUS_FIFO_THRESHOLD 0x08 | |
97 | #define DAQP_STATUS_FIFO_FULL 0x04 | |
98 | #define DAQP_STATUS_FIFO_NEARFULL 0x02 | |
99 | #define DAQP_STATUS_FIFO_EMPTY 0x01 | |
100 | ||
101 | #define DAQP_COMMAND_ARM 0x80 | |
102 | #define DAQP_COMMAND_RSTF 0x40 | |
103 | #define DAQP_COMMAND_RSTQ 0x20 | |
104 | #define DAQP_COMMAND_STOP 0x10 | |
105 | #define DAQP_COMMAND_LATCH 0x08 | |
106 | #define DAQP_COMMAND_100kHz 0x00 | |
107 | #define DAQP_COMMAND_50kHz 0x02 | |
108 | #define DAQP_COMMAND_25kHz 0x04 | |
109 | #define DAQP_COMMAND_FIFO_DATA 0x01 | |
110 | #define DAQP_COMMAND_FIFO_PROGRAM 0x00 | |
111 | ||
112 | #define DAQP_AUX_TRIGGER_TTL 0x00 | |
113 | #define DAQP_AUX_TRIGGER_ANALOG 0x80 | |
114 | #define DAQP_AUX_TRIGGER_PRETRIGGER 0x40 | |
115 | #define DAQP_AUX_TIMER_INT_ENABLE 0x20 | |
116 | #define DAQP_AUX_TIMER_RELOAD 0x00 | |
117 | #define DAQP_AUX_TIMER_PAUSE 0x08 | |
118 | #define DAQP_AUX_TIMER_GO 0x10 | |
119 | #define DAQP_AUX_TIMER_GO_EXTERNAL 0x18 | |
120 | #define DAQP_AUX_TIMER_EXTERNAL_SRC 0x04 | |
121 | #define DAQP_AUX_TIMER_INTERNAL_SRC 0x00 | |
122 | #define DAQP_AUX_DA_DIRECT 0x00 | |
123 | #define DAQP_AUX_DA_OVERFLOW 0x01 | |
124 | #define DAQP_AUX_DA_EXTERNAL 0x02 | |
125 | #define DAQP_AUX_DA_PACER 0x03 | |
126 | ||
127 | #define DAQP_AUX_RUNNING 0x80 | |
128 | #define DAQP_AUX_TRIGGERED 0x40 | |
129 | #define DAQP_AUX_DA_BUFFER 0x20 | |
130 | #define DAQP_AUX_TIMER_OVERFLOW 0x10 | |
131 | #define DAQP_AUX_CONVERSION 0x08 | |
132 | #define DAQP_AUX_DATA_LOST 0x04 | |
133 | #define DAQP_AUX_FIFO_NEARFULL 0x02 | |
134 | #define DAQP_AUX_FIFO_EMPTY 0x01 | |
135 | ||
bd9d00f1 HS |
136 | #define DAQP_FIFO_SIZE 4096 |
137 | ||
138 | struct daqp_private { | |
139 | int stop; | |
140 | ||
141 | enum { semaphore, buffer } interrupt_mode; | |
142 | ||
143 | struct completion eos; | |
144 | }; | |
145 | ||
e23fe9a1 HS |
146 | static const struct comedi_lrange range_daqp_ai = { |
147 | 4, { | |
148 | BIP_RANGE(10), | |
149 | BIP_RANGE(5), | |
150 | BIP_RANGE(2.5), | |
151 | BIP_RANGE(1.25) | |
152 | } | |
62ed6662 BB |
153 | }; |
154 | ||
d9952688 HS |
155 | static int daqp_clear_events(struct comedi_device *dev, int loops) |
156 | { | |
157 | unsigned int status; | |
158 | ||
159 | /* | |
160 | * Reset any pending interrupts (my card has a tendency to require | |
161 | * require multiple reads on the status register to achieve this). | |
162 | */ | |
163 | while (--loops) { | |
bd9d00f1 | 164 | status = inb(dev->iobase + DAQP_STATUS_REG); |
d9952688 HS |
165 | if ((status & DAQP_STATUS_EVENTS) == 0) |
166 | return 0; | |
167 | } | |
168 | dev_err(dev->class_dev, "couldn't clear events in status register\n"); | |
169 | return -EBUSY; | |
170 | } | |
171 | ||
62ed6662 BB |
172 | /* Cancel a running acquisition */ |
173 | ||
da91b269 | 174 | static int daqp_ai_cancel(struct comedi_device *dev, struct comedi_subdevice *s) |
62ed6662 | 175 | { |
1801726e | 176 | struct daqp_private *devpriv = dev->private; |
62ed6662 | 177 | |
1801726e | 178 | if (devpriv->stop) |
62ed6662 | 179 | return -EIO; |
3420f6b4 | 180 | |
bd9d00f1 | 181 | outb(DAQP_COMMAND_STOP, dev->iobase + DAQP_CMD_REG); |
62ed6662 BB |
182 | |
183 | /* flush any linguring data in FIFO - superfluous here */ | |
bd9d00f1 | 184 | /* outb(DAQP_COMMAND_RSTF, dev->iobase + DAQP_CMD_REG); */ |
62ed6662 | 185 | |
1801726e | 186 | devpriv->interrupt_mode = semaphore; |
62ed6662 BB |
187 | |
188 | return 0; | |
189 | } | |
190 | ||
c3f7e153 HS |
191 | static unsigned int daqp_ai_get_sample(struct comedi_device *dev, |
192 | struct comedi_subdevice *s) | |
193 | { | |
194 | unsigned int val; | |
195 | ||
196 | /* | |
197 | * Get a two's complement sample from the FIFO and | |
198 | * return the munged offset binary value. | |
199 | */ | |
bd9d00f1 HS |
200 | val = inb(dev->iobase + DAQP_AI_FIFO_REG); |
201 | val |= inb(dev->iobase + DAQP_AI_FIFO_REG) << 8; | |
c3f7e153 HS |
202 | return comedi_offset_munge(s, val); |
203 | } | |
204 | ||
62ed6662 BB |
205 | /* Interrupt handler |
206 | * | |
1801726e HS |
207 | * Operates in one of two modes. If devpriv->interrupt_mode is |
208 | * 'semaphore', just signal the devpriv->eos completion and return | |
62ed6662 BB |
209 | * (one-shot mode). Otherwise (continuous mode), read data in from |
210 | * the card, transfer it to the buffer provided by the higher-level | |
211 | * comedi kernel module, and signal various comedi callback routines, | |
212 | * which run pretty quick. | |
213 | */ | |
e3752a1d | 214 | static enum irqreturn daqp_interrupt(int irq, void *dev_id) |
62ed6662 | 215 | { |
c1271742 | 216 | struct comedi_device *dev = dev_id; |
1801726e | 217 | struct daqp_private *devpriv = dev->private; |
c1271742 | 218 | struct comedi_subdevice *s = dev->read_subdev; |
2d7840c7 | 219 | struct comedi_cmd *cmd = &s->async->cmd; |
62ed6662 BB |
220 | int loop_limit = 10000; |
221 | int status; | |
222 | ||
c1271742 | 223 | if (!dev->attached) |
e3752a1d | 224 | return IRQ_NONE; |
62ed6662 | 225 | |
1801726e | 226 | switch (devpriv->interrupt_mode) { |
62ed6662 | 227 | case semaphore: |
1801726e | 228 | complete(&devpriv->eos); |
62ed6662 BB |
229 | break; |
230 | ||
231 | case buffer: | |
bd9d00f1 | 232 | while (!((status = inb(dev->iobase + DAQP_STATUS_REG)) |
0a85b6f0 | 233 | & DAQP_STATUS_FIFO_EMPTY)) { |
8bab0d68 | 234 | unsigned short data; |
62ed6662 BB |
235 | |
236 | if (status & DAQP_STATUS_DATA_LOST) { | |
3e6cb74f | 237 | s->async->events |= COMEDI_CB_OVERFLOW; |
53f63dc7 | 238 | dev_warn(dev->class_dev, "data lost\n"); |
62ed6662 BB |
239 | break; |
240 | } | |
241 | ||
c3f7e153 | 242 | data = daqp_ai_get_sample(dev, s); |
a4a68fe2 | 243 | comedi_buf_write_samples(s, &data, 1); |
62ed6662 BB |
244 | |
245 | /* If there's a limit, decrement it | |
246 | * and stop conversion if zero | |
247 | */ | |
248 | ||
2d7840c7 HS |
249 | if (cmd->stop_src == TRIG_COUNT && |
250 | s->async->scans_done >= cmd->stop_arg) { | |
251 | s->async->events |= COMEDI_CB_EOA; | |
252 | break; | |
62ed6662 BB |
253 | } |
254 | ||
255 | if ((loop_limit--) <= 0) | |
256 | break; | |
257 | } | |
258 | ||
259 | if (loop_limit <= 0) { | |
ce3ed9f0 YT |
260 | dev_warn(dev->class_dev, |
261 | "loop_limit reached in daqp_interrupt()\n"); | |
3e6cb74f | 262 | s->async->events |= COMEDI_CB_ERROR; |
62ed6662 BB |
263 | } |
264 | ||
44aaad2d | 265 | comedi_handle_events(dev, s); |
62ed6662 | 266 | } |
e3752a1d | 267 | return IRQ_HANDLED; |
62ed6662 BB |
268 | } |
269 | ||
bd7807f9 HS |
270 | static void daqp_ai_set_one_scanlist_entry(struct comedi_device *dev, |
271 | unsigned int chanspec, | |
272 | int start) | |
273 | { | |
274 | unsigned int chan = CR_CHAN(chanspec); | |
275 | unsigned int range = CR_RANGE(chanspec); | |
276 | unsigned int aref = CR_AREF(chanspec); | |
277 | unsigned int val; | |
278 | ||
279 | val = DAQP_SCANLIST_CHANNEL(chan) | DAQP_SCANLIST_GAIN(range); | |
280 | ||
281 | if (aref == AREF_DIFF) | |
282 | val |= DAQP_SCANLIST_DIFFERENTIAL; | |
283 | ||
284 | if (start) | |
285 | val |= DAQP_SCANLIST_START; | |
286 | ||
bd9d00f1 HS |
287 | outb(val & 0xff, dev->iobase + DAQP_SCANLIST_REG); |
288 | outb((val >> 8) & 0xff, dev->iobase + DAQP_SCANLIST_REG); | |
bd7807f9 HS |
289 | } |
290 | ||
62ed6662 BB |
291 | /* One-shot analog data acquisition routine */ |
292 | ||
0a85b6f0 MT |
293 | static int daqp_ai_insn_read(struct comedi_device *dev, |
294 | struct comedi_subdevice *s, | |
295 | struct comedi_insn *insn, unsigned int *data) | |
62ed6662 | 296 | { |
1801726e | 297 | struct daqp_private *devpriv = dev->private; |
d9952688 | 298 | int ret; |
62ed6662 | 299 | int i; |
62ed6662 | 300 | |
1801726e | 301 | if (devpriv->stop) |
62ed6662 | 302 | return -EIO; |
3420f6b4 | 303 | |
62ed6662 BB |
304 | /* Stop any running conversion */ |
305 | daqp_ai_cancel(dev, s); | |
306 | ||
bd9d00f1 | 307 | outb(0, dev->iobase + DAQP_AUX_REG); |
62ed6662 BB |
308 | |
309 | /* Reset scan list queue */ | |
bd9d00f1 | 310 | outb(DAQP_COMMAND_RSTQ, dev->iobase + DAQP_CMD_REG); |
62ed6662 BB |
311 | |
312 | /* Program one scan list entry */ | |
bd7807f9 | 313 | daqp_ai_set_one_scanlist_entry(dev, insn->chanspec, 1); |
62ed6662 BB |
314 | |
315 | /* Reset data FIFO (see page 28 of DAQP User's Manual) */ | |
316 | ||
bd9d00f1 | 317 | outb(DAQP_COMMAND_RSTF, dev->iobase + DAQP_CMD_REG); |
62ed6662 | 318 | |
b0f9b0ad HS |
319 | /* Set trigger - one-shot, internal */ |
320 | outb(DAQP_CTRL_PACER_CLK_100KHZ | DAQP_CTRL_EOS_INT_ENA, | |
bd9d00f1 | 321 | dev->iobase + DAQP_CTRL_REG); |
62ed6662 | 322 | |
d9952688 HS |
323 | ret = daqp_clear_events(dev, 10000); |
324 | if (ret) | |
325 | return ret; | |
62ed6662 | 326 | |
1801726e HS |
327 | init_completion(&devpriv->eos); |
328 | devpriv->interrupt_mode = semaphore; | |
62ed6662 BB |
329 | |
330 | for (i = 0; i < insn->n; i++) { | |
62ed6662 BB |
331 | /* Start conversion */ |
332 | outb(DAQP_COMMAND_ARM | DAQP_COMMAND_FIFO_DATA, | |
bd9d00f1 | 333 | dev->iobase + DAQP_CMD_REG); |
62ed6662 | 334 | |
7ec52ed2 | 335 | /* Wait for interrupt service routine to unblock completion */ |
62ed6662 | 336 | /* Maybe could use a timeout here, but it's interruptible */ |
1801726e | 337 | if (wait_for_completion_interruptible(&devpriv->eos)) |
62ed6662 BB |
338 | return -EINTR; |
339 | ||
c3f7e153 | 340 | data[i] = daqp_ai_get_sample(dev, s); |
62ed6662 BB |
341 | } |
342 | ||
343 | return insn->n; | |
344 | } | |
345 | ||
346 | /* This function converts ns nanoseconds to a counter value suitable | |
347 | * for programming the device. We always use the DAQP's 5 MHz clock, | |
348 | * which with its 24-bit counter, allows values up to 84 seconds. | |
349 | * Also, the function adjusts ns so that it cooresponds to the actual | |
350 | * time that the device will use. | |
351 | */ | |
352 | ||
a207c12f | 353 | static int daqp_ns_to_timer(unsigned int *ns, unsigned int flags) |
62ed6662 BB |
354 | { |
355 | int timer; | |
356 | ||
357 | timer = *ns / 200; | |
358 | *ns = timer * 200; | |
359 | ||
360 | return timer; | |
361 | } | |
362 | ||
363 | /* cmdtest tests a particular command to see if it is valid. | |
364 | * Using the cmdtest ioctl, a user can create a valid cmd | |
365 | * and then have it executed by the cmd ioctl. | |
366 | * | |
367 | * cmdtest returns 1,2,3,4 or 0, depending on which tests | |
368 | * the command passes. | |
369 | */ | |
370 | ||
0a85b6f0 MT |
371 | static int daqp_ai_cmdtest(struct comedi_device *dev, |
372 | struct comedi_subdevice *s, struct comedi_cmd *cmd) | |
62ed6662 BB |
373 | { |
374 | int err = 0; | |
6c71941d | 375 | unsigned int arg; |
62ed6662 | 376 | |
27020ffe | 377 | /* Step 1 : check if triggers are trivially valid */ |
62ed6662 | 378 | |
75a12586 IA |
379 | err |= comedi_check_trigger_src(&cmd->start_src, TRIG_NOW); |
380 | err |= comedi_check_trigger_src(&cmd->scan_begin_src, | |
27020ffe | 381 | TRIG_TIMER | TRIG_FOLLOW); |
75a12586 | 382 | err |= comedi_check_trigger_src(&cmd->convert_src, |
27020ffe | 383 | TRIG_TIMER | TRIG_NOW); |
75a12586 IA |
384 | err |= comedi_check_trigger_src(&cmd->scan_end_src, TRIG_COUNT); |
385 | err |= comedi_check_trigger_src(&cmd->stop_src, TRIG_COUNT | TRIG_NONE); | |
62ed6662 BB |
386 | |
387 | if (err) | |
388 | return 1; | |
389 | ||
27020ffe | 390 | /* Step 2a : make sure trigger sources are unique */ |
62ed6662 | 391 | |
75a12586 IA |
392 | err |= comedi_check_trigger_is_unique(cmd->scan_begin_src); |
393 | err |= comedi_check_trigger_is_unique(cmd->convert_src); | |
394 | err |= comedi_check_trigger_is_unique(cmd->stop_src); | |
27020ffe HS |
395 | |
396 | /* Step 2b : and mutually compatible */ | |
62ed6662 BB |
397 | |
398 | if (err) | |
399 | return 2; | |
400 | ||
42cae4a1 HS |
401 | /* Step 3: check if arguments are trivially valid */ |
402 | ||
75a12586 | 403 | err |= comedi_check_trigger_arg_is(&cmd->start_arg, 0); |
62ed6662 | 404 | |
62ed6662 BB |
405 | #define MAX_SPEED 10000 /* 100 kHz - in nanoseconds */ |
406 | ||
75a12586 IA |
407 | if (cmd->scan_begin_src == TRIG_TIMER) { |
408 | err |= comedi_check_trigger_arg_min(&cmd->scan_begin_arg, | |
409 | MAX_SPEED); | |
410 | } | |
62ed6662 BB |
411 | |
412 | /* If both scan_begin and convert are both timer values, the only | |
413 | * way that can make sense is if the scan time is the number of | |
414 | * conversions times the convert time | |
415 | */ | |
416 | ||
417 | if (cmd->scan_begin_src == TRIG_TIMER && cmd->convert_src == TRIG_TIMER | |
0a85b6f0 | 418 | && cmd->scan_begin_arg != cmd->convert_arg * cmd->scan_end_arg) { |
42cae4a1 | 419 | err |= -EINVAL; |
62ed6662 BB |
420 | } |
421 | ||
75a12586 IA |
422 | if (cmd->convert_src == TRIG_TIMER) { |
423 | err |= comedi_check_trigger_arg_min(&cmd->convert_arg, | |
424 | MAX_SPEED); | |
425 | } | |
62ed6662 | 426 | |
75a12586 IA |
427 | err |= comedi_check_trigger_arg_is(&cmd->scan_end_arg, |
428 | cmd->chanlist_len); | |
42cae4a1 HS |
429 | |
430 | if (cmd->stop_src == TRIG_COUNT) | |
75a12586 | 431 | err |= comedi_check_trigger_arg_max(&cmd->stop_arg, 0x00ffffff); |
42cae4a1 | 432 | else /* TRIG_NONE */ |
75a12586 | 433 | err |= comedi_check_trigger_arg_is(&cmd->stop_arg, 0); |
62ed6662 BB |
434 | |
435 | if (err) | |
436 | return 3; | |
437 | ||
438 | /* step 4: fix up any arguments */ | |
439 | ||
440 | if (cmd->scan_begin_src == TRIG_TIMER) { | |
6c71941d | 441 | arg = cmd->scan_begin_arg; |
a207c12f | 442 | daqp_ns_to_timer(&arg, cmd->flags); |
75a12586 | 443 | err |= comedi_check_trigger_arg_is(&cmd->scan_begin_arg, arg); |
62ed6662 BB |
444 | } |
445 | ||
446 | if (cmd->convert_src == TRIG_TIMER) { | |
6c71941d | 447 | arg = cmd->convert_arg; |
a207c12f | 448 | daqp_ns_to_timer(&arg, cmd->flags); |
75a12586 | 449 | err |= comedi_check_trigger_arg_is(&cmd->convert_arg, arg); |
62ed6662 BB |
450 | } |
451 | ||
452 | if (err) | |
453 | return 4; | |
454 | ||
455 | return 0; | |
456 | } | |
457 | ||
da91b269 | 458 | static int daqp_ai_cmd(struct comedi_device *dev, struct comedi_subdevice *s) |
62ed6662 | 459 | { |
1801726e | 460 | struct daqp_private *devpriv = dev->private; |
ea6d0d4c | 461 | struct comedi_cmd *cmd = &s->async->cmd; |
e3752a1d | 462 | int counter; |
62ed6662 BB |
463 | int scanlist_start_on_every_entry; |
464 | int threshold; | |
d9952688 | 465 | int ret; |
62ed6662 | 466 | int i; |
62ed6662 | 467 | |
1801726e | 468 | if (devpriv->stop) |
62ed6662 | 469 | return -EIO; |
3420f6b4 | 470 | |
62ed6662 BB |
471 | /* Stop any running conversion */ |
472 | daqp_ai_cancel(dev, s); | |
473 | ||
bd9d00f1 | 474 | outb(0, dev->iobase + DAQP_AUX_REG); |
62ed6662 BB |
475 | |
476 | /* Reset scan list queue */ | |
bd9d00f1 | 477 | outb(DAQP_COMMAND_RSTQ, dev->iobase + DAQP_CMD_REG); |
62ed6662 BB |
478 | |
479 | /* Program pacer clock | |
480 | * | |
481 | * There's two modes we can operate in. If convert_src is | |
482 | * TRIG_TIMER, then convert_arg specifies the time between | |
483 | * each conversion, so we program the pacer clock to that | |
484 | * frequency and set the SCANLIST_START bit on every scanlist | |
485 | * entry. Otherwise, convert_src is TRIG_NOW, which means | |
486 | * we want the fastest possible conversions, scan_begin_src | |
487 | * is TRIG_TIMER, and scan_begin_arg specifies the time between | |
488 | * each scan, so we program the pacer clock to this frequency | |
489 | * and only set the SCANLIST_START bit on the first entry. | |
490 | */ | |
491 | ||
492 | if (cmd->convert_src == TRIG_TIMER) { | |
a207c12f | 493 | counter = daqp_ns_to_timer(&cmd->convert_arg, cmd->flags); |
bd9d00f1 HS |
494 | outb(counter & 0xff, dev->iobase + DAQP_PACER_LOW_REG); |
495 | outb((counter >> 8) & 0xff, dev->iobase + DAQP_PACER_MID_REG); | |
496 | outb((counter >> 16) & 0xff, dev->iobase + DAQP_PACER_HIGH_REG); | |
62ed6662 BB |
497 | scanlist_start_on_every_entry = 1; |
498 | } else { | |
a207c12f | 499 | counter = daqp_ns_to_timer(&cmd->scan_begin_arg, cmd->flags); |
bd9d00f1 HS |
500 | outb(counter & 0xff, dev->iobase + DAQP_PACER_LOW_REG); |
501 | outb((counter >> 8) & 0xff, dev->iobase + DAQP_PACER_MID_REG); | |
502 | outb((counter >> 16) & 0xff, dev->iobase + DAQP_PACER_HIGH_REG); | |
62ed6662 BB |
503 | scanlist_start_on_every_entry = 0; |
504 | } | |
505 | ||
506 | /* Program scan list */ | |
62ed6662 | 507 | for (i = 0; i < cmd->chanlist_len; i++) { |
bd7807f9 | 508 | int start = (i == 0 || scanlist_start_on_every_entry); |
62ed6662 | 509 | |
bd7807f9 | 510 | daqp_ai_set_one_scanlist_entry(dev, cmd->chanlist[i], start); |
62ed6662 BB |
511 | } |
512 | ||
513 | /* Now it's time to program the FIFO threshold, basically the | |
514 | * number of samples the card will buffer before it interrupts | |
515 | * the CPU. | |
516 | * | |
517 | * If we don't have a stop count, then use half the size of | |
518 | * the FIFO (the manufacturer's recommendation). Consider | |
519 | * that the FIFO can hold 2K samples (4K bytes). With the | |
520 | * threshold set at half the FIFO size, we have a margin of | |
521 | * error of 1024 samples. At the chip's maximum sample rate | |
522 | * of 100,000 Hz, the CPU would have to delay interrupt | |
523 | * service for a full 10 milliseconds in order to lose data | |
524 | * here (as opposed to higher up in the kernel). I've never | |
525 | * seen it happen. However, for slow sample rates it may | |
526 | * buffer too much data and introduce too much delay for the | |
527 | * user application. | |
528 | * | |
529 | * If we have a stop count, then things get more interesting. | |
530 | * If the stop count is less than the FIFO size (actually | |
531 | * three-quarters of the FIFO size - see below), we just use | |
532 | * the stop count itself as the threshold, the card interrupts | |
533 | * us when that many samples have been taken, and we kill the | |
534 | * acquisition at that point and are done. If the stop count | |
535 | * is larger than that, then we divide it by 2 until it's less | |
536 | * than three quarters of the FIFO size (we always leave the | |
537 | * top quarter of the FIFO as protection against sluggish CPU | |
538 | * interrupt response) and use that as the threshold. So, if | |
539 | * the stop count is 4000 samples, we divide by two twice to | |
540 | * get 1000 samples, use that as the threshold, take four | |
541 | * interrupts to get our 4000 samples and are done. | |
542 | * | |
543 | * The algorithm could be more clever. For example, if 81000 | |
544 | * samples are requested, we could set the threshold to 1500 | |
545 | * samples and take 54 interrupts to get 81000. But 54 isn't | |
546 | * a power of two, so this algorithm won't find that option. | |
547 | * Instead, it'll set the threshold at 1266 and take 64 | |
548 | * interrupts to get 81024 samples, of which the last 24 will | |
549 | * be discarded... but we won't get the last interrupt until | |
550 | * they've been collected. To find the first option, the | |
551 | * computer could look at the prime decomposition of the | |
552 | * sample count (81000 = 3^4 * 5^3 * 2^3) and factor it into a | |
553 | * threshold (1500 = 3 * 5^3 * 2^2) and an interrupt count (54 | |
554 | * = 3^3 * 2). Hmmm... a one-line while loop or prime | |
555 | * decomposition of integers... I'll leave it the way it is. | |
556 | * | |
557 | * I'll also note a mini-race condition before ignoring it in | |
558 | * the code. Let's say we're taking 4000 samples, as before. | |
559 | * After 1000 samples, we get an interrupt. But before that | |
560 | * interrupt is completely serviced, another sample is taken | |
561 | * and loaded into the FIFO. Since the interrupt handler | |
562 | * empties the FIFO before returning, it will read 1001 samples. | |
563 | * If that happens four times, we'll end up taking 4004 samples, | |
564 | * not 4000. The interrupt handler will discard the extra four | |
565 | * samples (by halting the acquisition with four samples still | |
566 | * in the FIFO), but we will have to wait for them. | |
567 | * | |
568 | * In short, this code works pretty well, but for either of | |
569 | * the two reasons noted, might end up waiting for a few more | |
570 | * samples than actually requested. Shouldn't make too much | |
571 | * of a difference. | |
572 | */ | |
573 | ||
574 | /* Save away the number of conversions we should perform, and | |
575 | * compute the FIFO threshold (in bytes, not samples - that's | |
1801726e | 576 | * why we multiple devpriv->count by 2 = sizeof(sample)) |
62ed6662 BB |
577 | */ |
578 | ||
579 | if (cmd->stop_src == TRIG_COUNT) { | |
2d7840c7 HS |
580 | unsigned long long nsamples; |
581 | unsigned long long nbytes; | |
582 | ||
583 | nsamples = (unsigned long long)cmd->stop_arg * | |
584 | cmd->scan_end_arg; | |
585 | nbytes = nsamples * comedi_bytes_per_sample(s); | |
586 | while (nbytes > DAQP_FIFO_SIZE * 3 / 4) | |
587 | nbytes /= 2; | |
588 | threshold = nbytes; | |
62ed6662 | 589 | } else { |
62ed6662 BB |
590 | threshold = DAQP_FIFO_SIZE / 2; |
591 | } | |
592 | ||
593 | /* Reset data FIFO (see page 28 of DAQP User's Manual) */ | |
594 | ||
bd9d00f1 | 595 | outb(DAQP_COMMAND_RSTF, dev->iobase + DAQP_CMD_REG); |
62ed6662 BB |
596 | |
597 | /* Set FIFO threshold. First two bytes are near-empty | |
598 | * threshold, which is unused; next two bytes are near-full | |
599 | * threshold. We computed the number of bytes we want in the | |
600 | * FIFO when the interrupt is generated, what the card wants | |
601 | * is actually the number of available bytes left in the FIFO | |
602 | * when the interrupt is to happen. | |
603 | */ | |
604 | ||
bd9d00f1 HS |
605 | outb(0x00, dev->iobase + DAQP_AI_FIFO_REG); |
606 | outb(0x00, dev->iobase + DAQP_AI_FIFO_REG); | |
62ed6662 | 607 | |
bd9d00f1 HS |
608 | outb((DAQP_FIFO_SIZE - threshold) & 0xff, |
609 | dev->iobase + DAQP_AI_FIFO_REG); | |
610 | outb((DAQP_FIFO_SIZE - threshold) >> 8, dev->iobase + DAQP_AI_FIFO_REG); | |
62ed6662 | 611 | |
b0f9b0ad HS |
612 | /* Set trigger - continuous, internal */ |
613 | outb(DAQP_CTRL_TRIG_MODE | DAQP_CTRL_PACER_CLK_5MHZ | | |
614 | DAQP_CTRL_FIFO_INT_ENA, dev->iobase + DAQP_CTRL_REG); | |
62ed6662 | 615 | |
d9952688 HS |
616 | ret = daqp_clear_events(dev, 100); |
617 | if (ret) | |
618 | return ret; | |
62ed6662 | 619 | |
1801726e | 620 | devpriv->interrupt_mode = buffer; |
62ed6662 BB |
621 | |
622 | /* Start conversion */ | |
623 | outb(DAQP_COMMAND_ARM | DAQP_COMMAND_FIFO_DATA, | |
bd9d00f1 | 624 | dev->iobase + DAQP_CMD_REG); |
62ed6662 BB |
625 | |
626 | return 0; | |
627 | } | |
628 | ||
e031642e HS |
629 | static int daqp_ao_empty(struct comedi_device *dev, |
630 | struct comedi_subdevice *s, | |
631 | struct comedi_insn *insn, | |
632 | unsigned long context) | |
633 | { | |
634 | unsigned int status; | |
635 | ||
bd9d00f1 | 636 | status = inb(dev->iobase + DAQP_AUX_REG); |
e031642e HS |
637 | if ((status & DAQP_AUX_DA_BUFFER) == 0) |
638 | return 0; | |
639 | return -EBUSY; | |
640 | } | |
641 | ||
0a85b6f0 MT |
642 | static int daqp_ao_insn_write(struct comedi_device *dev, |
643 | struct comedi_subdevice *s, | |
d35dcc89 HS |
644 | struct comedi_insn *insn, |
645 | unsigned int *data) | |
62ed6662 | 646 | { |
1801726e | 647 | struct daqp_private *devpriv = dev->private; |
d35dcc89 | 648 | unsigned int chan = CR_CHAN(insn->chanspec); |
d35dcc89 | 649 | int i; |
62ed6662 | 650 | |
1801726e | 651 | if (devpriv->stop) |
62ed6662 | 652 | return -EIO; |
62ed6662 | 653 | |
62ed6662 | 654 | /* Make sure D/A update mode is direct update */ |
bd9d00f1 | 655 | outb(0, dev->iobase + DAQP_AUX_REG); |
62ed6662 | 656 | |
d35dcc89 | 657 | for (i = 0; i > insn->n; i++) { |
e024181b | 658 | unsigned val = data[i]; |
e031642e | 659 | int ret; |
e024181b | 660 | |
e031642e HS |
661 | /* D/A transfer rate is about 8ms */ |
662 | ret = comedi_timeout(dev, s, insn, daqp_ao_empty, 0); | |
663 | if (ret) | |
664 | return ret; | |
92b66775 | 665 | |
1271dd24 HS |
666 | /* write the two's complement value to the channel */ |
667 | outw((chan << 12) | comedi_offset_munge(s, val), | |
bd9d00f1 | 668 | dev->iobase + DAQP_AO_REG); |
e031642e HS |
669 | |
670 | s->readback[chan] = val; | |
d35dcc89 HS |
671 | } |
672 | ||
673 | return insn->n; | |
62ed6662 BB |
674 | } |
675 | ||
62100fef | 676 | static int daqp_di_insn_bits(struct comedi_device *dev, |
0a85b6f0 | 677 | struct comedi_subdevice *s, |
62100fef HS |
678 | struct comedi_insn *insn, |
679 | unsigned int *data) | |
62ed6662 | 680 | { |
1801726e | 681 | struct daqp_private *devpriv = dev->private; |
62ed6662 | 682 | |
1801726e | 683 | if (devpriv->stop) |
62ed6662 | 684 | return -EIO; |
62ed6662 | 685 | |
bd9d00f1 | 686 | data[0] = inb(dev->iobase + DAQP_DI_REG); |
62ed6662 | 687 | |
62100fef | 688 | return insn->n; |
62ed6662 BB |
689 | } |
690 | ||
6a911d8a HS |
691 | static int daqp_do_insn_bits(struct comedi_device *dev, |
692 | struct comedi_subdevice *s, | |
693 | struct comedi_insn *insn, | |
694 | unsigned int *data) | |
62ed6662 | 695 | { |
1801726e | 696 | struct daqp_private *devpriv = dev->private; |
62ed6662 | 697 | |
1801726e | 698 | if (devpriv->stop) |
62ed6662 | 699 | return -EIO; |
62ed6662 | 700 | |
97f4289a | 701 | if (comedi_dio_update_state(s, data)) |
bd9d00f1 | 702 | outb(s->state, dev->iobase + DAQP_DO_REG); |
6a911d8a HS |
703 | |
704 | data[1] = s->state; | |
705 | ||
706 | return insn->n; | |
62ed6662 BB |
707 | } |
708 | ||
c04edbf2 HS |
709 | static int daqp_auto_attach(struct comedi_device *dev, |
710 | unsigned long context) | |
62ed6662 | 711 | { |
c04edbf2 | 712 | struct pcmcia_device *link = comedi_to_pcmcia_dev(dev); |
1801726e | 713 | struct daqp_private *devpriv; |
34c43922 | 714 | struct comedi_subdevice *s; |
c65c64d0 | 715 | int ret; |
62ed6662 | 716 | |
0bdab509 | 717 | devpriv = comedi_alloc_devpriv(dev, sizeof(*devpriv)); |
1801726e | 718 | if (!devpriv) |
c04edbf2 | 719 | return -ENOMEM; |
62ed6662 | 720 | |
c04edbf2 | 721 | link->config_flags |= CONF_AUTO_SET_IO | CONF_ENABLE_IRQ; |
a9d50943 | 722 | ret = comedi_pcmcia_enable(dev, NULL); |
c04edbf2 HS |
723 | if (ret) |
724 | return ret; | |
87fe1452 | 725 | dev->iobase = link->resource[0]->start; |
62ed6662 | 726 | |
c1271742 | 727 | link->priv = dev; |
c04edbf2 HS |
728 | ret = pcmcia_request_irq(link, daqp_interrupt); |
729 | if (ret) | |
730 | return ret; | |
731 | ||
2f0b9d08 | 732 | ret = comedi_alloc_subdevices(dev, 4); |
8b6c5694 | 733 | if (ret) |
62ed6662 BB |
734 | return ret; |
735 | ||
123c0e03 | 736 | s = &dev->subdevices[0]; |
62ed6662 | 737 | dev->read_subdev = s; |
b7c0afa4 HS |
738 | s->type = COMEDI_SUBD_AI; |
739 | s->subdev_flags = SDF_READABLE | SDF_GROUND | SDF_DIFF | SDF_CMD_READ; | |
740 | s->n_chan = 8; | |
741 | s->len_chanlist = 2048; | |
742 | s->maxdata = 0xffff; | |
743 | s->range_table = &range_daqp_ai; | |
744 | s->insn_read = daqp_ai_insn_read; | |
745 | s->do_cmdtest = daqp_ai_cmdtest; | |
746 | s->do_cmd = daqp_ai_cmd; | |
747 | s->cancel = daqp_ai_cancel; | |
62ed6662 | 748 | |
123c0e03 | 749 | s = &dev->subdevices[1]; |
b7c0afa4 | 750 | s->type = COMEDI_SUBD_AO; |
ef49d832 | 751 | s->subdev_flags = SDF_WRITABLE; |
b7c0afa4 HS |
752 | s->n_chan = 2; |
753 | s->maxdata = 0x0fff; | |
754 | s->range_table = &range_bipolar5; | |
755 | s->insn_write = daqp_ao_insn_write; | |
92b66775 HS |
756 | |
757 | ret = comedi_alloc_subdev_readback(s); | |
758 | if (ret) | |
759 | return ret; | |
62ed6662 | 760 | |
4d6b7008 HS |
761 | /* |
762 | * Digital Input subdevice | |
763 | * NOTE: The digital input lines are shared: | |
764 | * | |
765 | * Chan Normal Mode Expansion Mode | |
766 | * ---- ----------------- ---------------------------- | |
767 | * 0 DI0, ext. trigger Same as normal mode | |
768 | * 1 DI1 External gain select, lo bit | |
769 | * 2 DI2, ext. clock Same as normal mode | |
770 | * 3 DI3 External gain select, hi bit | |
771 | */ | |
123c0e03 | 772 | s = &dev->subdevices[2]; |
b7c0afa4 HS |
773 | s->type = COMEDI_SUBD_DI; |
774 | s->subdev_flags = SDF_READABLE; | |
4d6b7008 | 775 | s->n_chan = 4; |
62100fef HS |
776 | s->maxdata = 1; |
777 | s->insn_bits = daqp_di_insn_bits; | |
62ed6662 | 778 | |
23d4f024 HS |
779 | /* |
780 | * Digital Output subdevice | |
781 | * NOTE: The digital output lines share the same pins on the | |
782 | * interface connector as the four external channel selection | |
783 | * bits. If expansion mode is used the digital outputs do not | |
784 | * work. | |
785 | */ | |
123c0e03 | 786 | s = &dev->subdevices[3]; |
b7c0afa4 | 787 | s->type = COMEDI_SUBD_DO; |
ef49d832 | 788 | s->subdev_flags = SDF_WRITABLE; |
23d4f024 | 789 | s->n_chan = 4; |
6a911d8a HS |
790 | s->maxdata = 1; |
791 | s->insn_bits = daqp_do_insn_bits; | |
62ed6662 | 792 | |
b7c0afa4 | 793 | return 0; |
62ed6662 BB |
794 | } |
795 | ||
d1db2a41 HS |
796 | static struct comedi_driver driver_daqp = { |
797 | .driver_name = "quatech_daqp_cs", | |
798 | .module = THIS_MODULE, | |
c04edbf2 | 799 | .auto_attach = daqp_auto_attach, |
25736670 | 800 | .detach = comedi_pcmcia_disable, |
d1db2a41 HS |
801 | }; |
802 | ||
d1db2a41 | 803 | static int daqp_cs_suspend(struct pcmcia_device *link) |
62ed6662 | 804 | { |
c1271742 | 805 | struct comedi_device *dev = link->priv; |
1801726e | 806 | struct daqp_private *devpriv = dev ? dev->private : NULL; |
62ed6662 | 807 | |
d1db2a41 | 808 | /* Mark the device as stopped, to block IO until later */ |
1801726e HS |
809 | if (devpriv) |
810 | devpriv->stop = 1; | |
c1271742 | 811 | |
d1db2a41 HS |
812 | return 0; |
813 | } | |
62ed6662 | 814 | |
d1db2a41 HS |
815 | static int daqp_cs_resume(struct pcmcia_device *link) |
816 | { | |
c1271742 | 817 | struct comedi_device *dev = link->priv; |
1801726e | 818 | struct daqp_private *devpriv = dev ? dev->private : NULL; |
62ed6662 | 819 | |
1801726e HS |
820 | if (devpriv) |
821 | devpriv->stop = 0; | |
62ed6662 BB |
822 | |
823 | return 0; | |
d1db2a41 | 824 | } |
62ed6662 | 825 | |
d1db2a41 | 826 | static int daqp_cs_attach(struct pcmcia_device *link) |
62ed6662 | 827 | { |
c04edbf2 | 828 | return comedi_pcmcia_auto_config(link, &driver_daqp); |
62ed6662 BB |
829 | } |
830 | ||
2202a5a7 | 831 | static const struct pcmcia_device_id daqp_cs_id_table[] = { |
62ed6662 BB |
832 | PCMCIA_DEVICE_MANF_CARD(0x0137, 0x0027), |
833 | PCMCIA_DEVICE_NULL | |
834 | }; | |
62ed6662 BB |
835 | MODULE_DEVICE_TABLE(pcmcia, daqp_cs_id_table); |
836 | ||
e3752a1d | 837 | static struct pcmcia_driver daqp_cs_driver = { |
433a0e22 HS |
838 | .name = "quatech_daqp_cs", |
839 | .owner = THIS_MODULE, | |
840 | .id_table = daqp_cs_id_table, | |
841 | .probe = daqp_cs_attach, | |
c04edbf2 | 842 | .remove = comedi_pcmcia_auto_unconfig, |
433a0e22 HS |
843 | .suspend = daqp_cs_suspend, |
844 | .resume = daqp_cs_resume, | |
62ed6662 | 845 | }; |
f3493a97 | 846 | module_comedi_pcmcia_driver(driver_daqp, daqp_cs_driver); |
04c59041 HS |
847 | |
848 | MODULE_DESCRIPTION("Comedi driver for Quatech DAQP PCMCIA data capture cards"); | |
849 | MODULE_AUTHOR("Brent Baccala <baccala@freesoft.org>"); | |
850 | MODULE_LICENSE("GPL"); |