projects / deliverable / linux.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
Staging: comedi: Remove instances of assignments in conditionals
[deliverable/linux.git] / drivers / staging / comedi / drivers / s626.c
CommitLineData
11e865c1
GP		 1/*
2 comedi/drivers/s626.c
3 Sensoray s626 Comedi driver
4
5 COMEDI - Linux Control and Measurement Device Interface
6 Copyright (C) 2000 David A. Schleef <ds@schleef.org>
7
8 Based on Sensoray Model 626 Linux driver Version 0.2
9 Copyright (C) 2002-2004 Sensoray Co., Inc.
10
11 This program is free software; you can redistribute it and/or modify
12 it under the terms of the GNU General Public License as published by
13 the Free Software Foundation; either version 2 of the License, or
14 (at your option) any later version.
15
16 This program is distributed in the hope that it will be useful,
17 but WITHOUT ANY WARRANTY; without even the implied warranty of
18 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 GNU General Public License for more details.
20
21 You should have received a copy of the GNU General Public License
22 along with this program; if not, write to the Free Software
23 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
24
25*/
26
27/*
28Driver: s626
29Description: Sensoray 626 driver
30Devices: [Sensoray] 626 (s626)
31Authors: Gianluca Palli <gpalli@deis.unibo.it>,
32Updated: Fri, 15 Feb 2008 10:28:42 +0000
33Status: experimental
34
35Configuration options:
36 [0] - PCI bus of device (optional)
37 [1] - PCI slot of device (optional)
38 If bus/slot is not specified, the first supported
39 PCI device found will be used.
40
41INSN_CONFIG instructions:
42 analog input:
43 none
44
45 analog output:
46 none
47
48 digital channel:
49 s626 has 3 dio subdevices (2,3 and 4) each with 16 i/o channels
50 supported configuration options:
51 INSN_CONFIG_DIO_QUERY
52 COMEDI_INPUT
53 COMEDI_OUTPUT
54
55 encoder:
56 Every channel must be configured before reading.
57
58 Example code
59
60 insn.insn=INSN_CONFIG; //configuration instruction
61 insn.n=1; //number of operation (must be 1)
62 insn.data=&initialvalue; //initial value loaded into encoder
63 //during configuration
64 insn.subdev=5; //encoder subdevice
65 insn.chanspec=CR_PACK(encoder_channel,0,AREF_OTHER); //encoder_channel
66 //to configure
67
68 comedi_do_insn(cf,&insn); //executing configuration
69*/
70
71#include <linux/kernel.h>
72#include <linux/types.h>
73
74#include "../comedidev.h"
75
76#include "comedi_pci.h"
77
78#include "comedi_fc.h"
79#include "s626.h"
80
81MODULE_AUTHOR("Gianluca Palli <gpalli@deis.unibo.it>");
82MODULE_DESCRIPTION("Sensoray 626 Comedi driver module");
83MODULE_LICENSE("GPL");
84
85typedef struct s626_board_struct {
86 const char *name;
87 int ai_chans;
88 int ai_bits;
89 int ao_chans;
90 int ao_bits;
91 int dio_chans;
92 int dio_banks;
93 int enc_chans;
94} s626_board;
95
96static const s626_board s626_boards[] = {
97 {
98 name: "s626",
f7266a48 99 ai_chans : S626_ADC_CHANNELS,
11e865c1 100 ai_bits: 14,
f7266a48 101 ao_chans : S626_DAC_CHANNELS,
11e865c1 102 ao_bits: 13,
f7266a48
BP		 103 dio_chans : S626_DIO_CHANNELS,
104 dio_banks : S626_DIO_BANKS,
105 enc_chans : S626_ENCODER_CHANNELS,
11e865c1
GP		 106 }
107};
108
109#define thisboard ((const s626_board *)dev->board_ptr)
110#define PCI_VENDOR_ID_S626 0x1131
111#define PCI_DEVICE_ID_S626 0x7146
112
113static DEFINE_PCI_DEVICE_TABLE(s626_pci_table) = {
114 {PCI_VENDOR_ID_S626, PCI_DEVICE_ID_S626, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
115 0},
116 {0}
117};
118
119MODULE_DEVICE_TABLE(pci, s626_pci_table);
120
e473e912
BP		 121static int s626_attach(comedi_device *dev, comedi_devconfig *it);
122static int s626_detach(comedi_device *dev);
11e865c1
GP		 123
124static comedi_driver driver_s626 = {
125 driver_name:"s626",
f7266a48
BP		 126 module : THIS_MODULE,
127 attach : s626_attach,
128 detach : s626_detach,
11e865c1
GP		 129};
130
131typedef struct {
132 struct pci_dev *pdev;
133 void *base_addr;
134 int got_regions;
135 short allocatedBuf;
b6c77757
BP		 136 uint8_t ai_cmd_running; /* ai_cmd is running */
137 uint8_t ai_continous; /* continous aquisition */
138 int ai_sample_count; /* number of samples to aquire */
139 unsigned int ai_sample_timer;
140 /* time between samples in units of the timer */
141 int ai_convert_count; /* conversion counter */
142 unsigned int ai_convert_timer;
143 /* time between conversion in units of the timer */
144 uint16_t CounterIntEnabs;
145 /* Counter interrupt enable mask for MISC2 register. */
146 uint8_t AdcItems; /* Number of items in ADC poll list. */
147 DMABUF RPSBuf; /* DMA buffer used to hold ADC (RPS1) program. */
148 DMABUF ANABuf;
149 /* DMA buffer used to receive ADC data and hold DAC data. */
150 uint32_t *pDacWBuf;
151 /* Pointer to logical adrs of DMA buffer used to hold DAC data. */
152 uint16_t Dacpol; /* Image of DAC polarity register. */
153 uint8_t TrimSetpoint[12]; /* Images of TrimDAC setpoints */
154 uint16_t ChargeEnabled; /* Image of MISC2 Battery */
155 /* Charge Enabled (0 or WRMISC2_CHARGE_ENABLE). */
156 uint16_t WDInterval; /* Image of MISC2 watchdog interval control bits. */
157 uint32_t I2CAdrs;
158 /* I2C device address for onboard EEPROM (board rev dependent). */
159 /* short I2Cards; */
11e865c1
GP		 160 lsampl_t ao_readback[S626_DAC_CHANNELS];
161} s626_private;
162
163typedef struct {
164 uint16_t RDDIn;
165 uint16_t WRDOut;
166 uint16_t RDEdgSel;
167 uint16_t WREdgSel;
168 uint16_t RDCapSel;
169 uint16_t WRCapSel;
170 uint16_t RDCapFlg;
171 uint16_t RDIntSel;
172 uint16_t WRIntSel;
173} dio_private;
174
175static dio_private dio_private_A = {
176 RDDIn:LP_RDDINA,
f7266a48
BP		 177 WRDOut : LP_WRDOUTA,
178 RDEdgSel : LP_RDEDGSELA,
179 WREdgSel : LP_WREDGSELA,
180 RDCapSel : LP_RDCAPSELA,
181 WRCapSel : LP_WRCAPSELA,
182 RDCapFlg : LP_RDCAPFLGA,
183 RDIntSel : LP_RDINTSELA,
184 WRIntSel : LP_WRINTSELA,
11e865c1
GP		 185};
186
187static dio_private dio_private_B = {
188 RDDIn:LP_RDDINB,
f7266a48
BP		 189 WRDOut : LP_WRDOUTB,
190 RDEdgSel : LP_RDEDGSELB,
191 WREdgSel : LP_WREDGSELB,
192 RDCapSel : LP_RDCAPSELB,
193 WRCapSel : LP_WRCAPSELB,
194 RDCapFlg : LP_RDCAPFLGB,
195 RDIntSel : LP_RDINTSELB,
196 WRIntSel : LP_WRINTSELB,
11e865c1
GP		 197};
198
199static dio_private dio_private_C = {
200 RDDIn:LP_RDDINC,
f7266a48
BP		 201 WRDOut : LP_WRDOUTC,
202 RDEdgSel : LP_RDEDGSELC,
203 WREdgSel : LP_WREDGSELC,
204 RDCapSel : LP_RDCAPSELC,
205 WRCapSel : LP_WRCAPSELC,
206 RDCapFlg : LP_RDCAPFLGC,
207 RDIntSel : LP_RDINTSELC,
208 WRIntSel : LP_WRINTSELC,
11e865c1
GP		 209};
210
211/* to group dio devices (48 bits mask and data are not allowed ???)
212static dio_private *dio_private_word[]={
213 &dio_private_A,
214 &dio_private_B,
215 &dio_private_C,
216};
217*/
218
219#define devpriv ((s626_private *)dev->private)
220#define diopriv ((dio_private *)s->private)
221
222COMEDI_PCI_INITCLEANUP_NOMODULE(driver_s626, s626_pci_table);
223
b6c77757 224/* ioctl routines */
e473e912
BP		 225static int s626_ai_insn_config(comedi_device *dev, comedi_subdevice *s,
226 comedi_insn *insn, lsampl_t *data);
11e865c1 227/* static int s626_ai_rinsn(comedi_device *dev,comedi_subdevice *s,comedi_insn *insn,lsampl_t *data); */
e473e912
BP		 228static int s626_ai_insn_read(comedi_device *dev, comedi_subdevice *s,
229 comedi_insn *insn, lsampl_t *data);
230static int s626_ai_cmd(comedi_device *dev, comedi_subdevice *s);
231static int s626_ai_cmdtest(comedi_device *dev, comedi_subdevice *s,
232 comedi_cmd *cmd);
233static int s626_ai_cancel(comedi_device *dev, comedi_subdevice *s);
234static int s626_ao_winsn(comedi_device *dev, comedi_subdevice *s,
235 comedi_insn *insn, lsampl_t *data);
236static int s626_ao_rinsn(comedi_device *dev, comedi_subdevice *s,
237 comedi_insn *insn, lsampl_t *data);
238static int s626_dio_insn_bits(comedi_device *dev, comedi_subdevice *s,
239 comedi_insn *insn, lsampl_t *data);
240static int s626_dio_insn_config(comedi_device *dev, comedi_subdevice *s,
241 comedi_insn *insn, lsampl_t *data);
242static int s626_dio_set_irq(comedi_device *dev, unsigned int chan);
243static int s626_dio_reset_irq(comedi_device *dev, unsigned int gruop,
11e865c1 244 unsigned int mask);
e473e912
BP		 245static int s626_dio_clear_irq(comedi_device *dev);
246static int s626_enc_insn_config(comedi_device *dev, comedi_subdevice *s,
247 comedi_insn *insn, lsampl_t *data);
248static int s626_enc_insn_read(comedi_device *dev, comedi_subdevice *s,
249 comedi_insn *insn, lsampl_t *data);
250static int s626_enc_insn_write(comedi_device *dev, comedi_subdevice *s,
251 comedi_insn *insn, lsampl_t *data);
11e865c1 252static int s626_ns_to_timer(int *nanosec, int round_mode);
e473e912
BP		 253static int s626_ai_load_polllist(uint8_t *ppl, comedi_cmd *cmd);
254static int s626_ai_inttrig(comedi_device *dev, comedi_subdevice *s,
11e865c1
GP		 255 unsigned int trignum);
256static irqreturn_t s626_irq_handler(int irq, void *d PT_REGS_ARG);
257static lsampl_t s626_ai_reg_to_uint(int data);
258/* static lsampl_t s626_uint_to_reg(comedi_subdevice *s, int data); */
259
b6c77757 260/* end ioctl routines */
11e865c1 261
b6c77757 262/* internal routines */
e473e912
BP		 263static void s626_dio_init(comedi_device *dev);
264static void ResetADC(comedi_device *dev, uint8_t *ppl);
265static void LoadTrimDACs(comedi_device *dev);
266static void WriteTrimDAC(comedi_device *dev, uint8_t LogicalChan,
11e865c1 267 uint8_t DacData);
e473e912
BP		 268static uint8_t I2Cread(comedi_device *dev, uint8_t addr);
269static uint32_t I2Chandshake(comedi_device *dev, uint32_t val);
270static void SetDAC(comedi_device *dev, uint16_t chan, short dacdata);
271static void SendDAC(comedi_device *dev, uint32_t val);
272static void WriteMISC2(comedi_device *dev, uint16_t NewImage);
273static void DEBItransfer(comedi_device *dev);
274static uint16_t DEBIread(comedi_device *dev, uint16_t addr);
275static void DEBIwrite(comedi_device *dev, uint16_t addr, uint16_t wdata);
276static void DEBIreplace(comedi_device *dev, uint16_t addr, uint16_t mask,
11e865c1 277 uint16_t wdata);
e473e912 278static void CloseDMAB(comedi_device *dev, DMABUF *pdma, size_t bsize);
11e865c1 279
b6c77757 280/* COUNTER OBJECT ------------------------------------------------ */
11e865c1 281typedef struct enc_private_struct {
b6c77757 282 /* Pointers to functions that differ for A and B counters: */
e473e912
BP		 283 uint16_t(*GetEnable) (comedi_device *dev, struct enc_private_struct *); /* Return clock enable. */
284 uint16_t(*GetIntSrc) (comedi_device *dev, struct enc_private_struct *); /* Return interrupt source. */
285 uint16_t(*GetLoadTrig) (comedi_device *dev, struct enc_private_struct *); /* Return preload trigger source. */
286 uint16_t(*GetMode) (comedi_device *dev, struct enc_private_struct *); /* Return standardized operating mode. */
287 void (*PulseIndex) (comedi_device *dev, struct enc_private_struct *); /* Generate soft index strobe. */
288 void (*SetEnable) (comedi_device *dev, struct enc_private_struct *, uint16_t enab); /* Program clock enable. */
289 void (*SetIntSrc) (comedi_device *dev, struct enc_private_struct *, uint16_t IntSource); /* Program interrupt source. */
290 void (*SetLoadTrig) (comedi_device *dev, struct enc_private_struct *, uint16_t Trig); /* Program preload trigger source. */
291 void (*SetMode) (comedi_device *dev, struct enc_private_struct *, uint16_t Setup, uint16_t DisableIntSrc); /* Program standardized operating mode. */
292 void (*ResetCapFlags) (comedi_device *dev, struct enc_private_struct *); /* Reset event capture flags. */
b6c77757
BP		 293
294 uint16_t MyCRA; /* Address of CRA register. */
295 uint16_t MyCRB; /* Address of CRB register. */
296 uint16_t MyLatchLsw; /* Address of Latch least-significant-word */
297 /* register. */
298 uint16_t MyEventBits[4]; /* Bit translations for IntSrc -->RDMISC2. */
299} enc_private; /* counter object */
11e865c1
GP		 300
301#define encpriv ((enc_private *)(dev->subdevices+5)->private)
302
b6c77757 303/* counters routines */
e473e912
BP		 304static void s626_timer_load(comedi_device *dev, enc_private *k, int tick);
305static uint32_t ReadLatch(comedi_device *dev, enc_private *k);
306static void ResetCapFlags_A(comedi_device *dev, enc_private *k);
307static void ResetCapFlags_B(comedi_device *dev, enc_private *k);
308static uint16_t GetMode_A(comedi_device *dev, enc_private *k);
309static uint16_t GetMode_B(comedi_device *dev, enc_private *k);
310static void SetMode_A(comedi_device *dev, enc_private *k, uint16_t Setup,
11e865c1 311 uint16_t DisableIntSrc);
e473e912 312static void SetMode_B(comedi_device *dev, enc_private *k, uint16_t Setup,
11e865c1 313 uint16_t DisableIntSrc);
e473e912
BP		 314static void SetEnable_A(comedi_device *dev, enc_private *k, uint16_t enab);
315static void SetEnable_B(comedi_device *dev, enc_private *k, uint16_t enab);
316static uint16_t GetEnable_A(comedi_device *dev, enc_private *k);
317static uint16_t GetEnable_B(comedi_device *dev, enc_private *k);
318static void SetLatchSource(comedi_device *dev, enc_private *k,
11e865c1
GP		 319 uint16_t value);
320/* static uint16_t GetLatchSource(comedi_device *dev, enc_private *k ); */
e473e912
BP		 321static void SetLoadTrig_A(comedi_device *dev, enc_private *k, uint16_t Trig);
322static void SetLoadTrig_B(comedi_device *dev, enc_private *k, uint16_t Trig);
323static uint16_t GetLoadTrig_A(comedi_device *dev, enc_private *k);
324static uint16_t GetLoadTrig_B(comedi_device *dev, enc_private *k);
325static void SetIntSrc_B(comedi_device *dev, enc_private *k,
11e865c1 326 uint16_t IntSource);
e473e912 327static void SetIntSrc_A(comedi_device *dev, enc_private *k,
11e865c1 328 uint16_t IntSource);
e473e912
BP		 329static uint16_t GetIntSrc_A(comedi_device *dev, enc_private *k);
330static uint16_t GetIntSrc_B(comedi_device *dev, enc_private *k);
11e865c1
GP		 331/* static void SetClkMult(comedi_device *dev, enc_private *k, uint16_t value ) ; */
332/* static uint16_t GetClkMult(comedi_device *dev, enc_private *k ) ; */
333/* static void SetIndexPol(comedi_device *dev, enc_private *k, uint16_t value ); */
334/* static uint16_t GetClkPol(comedi_device *dev, enc_private *k ) ; */
335/* static void SetIndexSrc( comedi_device *dev,enc_private *k, uint16_t value ); */
336/* static uint16_t GetClkSrc( comedi_device *dev,enc_private *k ); */
337/* static void SetIndexSrc( comedi_device *dev,enc_private *k, uint16_t value ); */
338/* static uint16_t GetIndexSrc( comedi_device *dev,enc_private *k ); */
e473e912
BP		 339static void PulseIndex_A(comedi_device *dev, enc_private *k);
340static void PulseIndex_B(comedi_device *dev, enc_private *k);
341static void Preload(comedi_device *dev, enc_private *k, uint32_t value);
342static void CountersInit(comedi_device *dev);
b6c77757 343/* end internal routines */
11e865c1 344
b6c77757 345/* Counter objects constructor. */
11e865c1 346
b6c77757 347/* Counter overflow/index event flag masks for RDMISC2. */
6a98d36e
BP		 348#define INDXMASK(C) (1 << (((C) > 2) ? ((C) * 2 - 1) : ((C) * 2 + 4)))
349#define OVERMASK(C) (1 << (((C) > 2) ? ((C) * 2 + 5) : ((C) * 2 + 10)))
11e865c1
GP		 350#define EVBITS(C) { 0, OVERMASK(C), INDXMASK(C), OVERMASK(C) | INDXMASK(C) }
351
b6c77757
BP		 352/* Translation table to map IntSrc into equivalent RDMISC2 event flag bits. */
353/* static const uint16_t EventBits[][4] = { EVBITS(0), EVBITS(1), EVBITS(2), EVBITS(3), EVBITS(4), EVBITS(5) }; */
11e865c1
GP		 354
355/* enc_private; */
356static enc_private enc_private_data[] = {
357 {
358 GetEnable:GetEnable_A,
f7266a48
BP		 359 GetIntSrc : GetIntSrc_A,
360 GetLoadTrig : GetLoadTrig_A,
11e865c1 361 GetMode: GetMode_A,
f7266a48
BP		 362 PulseIndex : PulseIndex_A,
363 SetEnable : SetEnable_A,
364 SetIntSrc : SetIntSrc_A,
365 SetLoadTrig : SetLoadTrig_A,
11e865c1 366 SetMode: SetMode_A,
f7266a48 367 ResetCapFlags : ResetCapFlags_A,
11e865c1
GP		 368 MyCRA: LP_CR0A,
369 MyCRB: LP_CR0B,
f7266a48
BP		 370 MyLatchLsw : LP_CNTR0ALSW,
371 MyEventBits : EVBITS(0),
11e865c1
GP		 372 },
373 {
374 GetEnable:GetEnable_A,
f7266a48
BP		 375 GetIntSrc : GetIntSrc_A,
376 GetLoadTrig : GetLoadTrig_A,
11e865c1 377 GetMode: GetMode_A,
f7266a48
BP		 378 PulseIndex : PulseIndex_A,
379 SetEnable : SetEnable_A,
380 SetIntSrc : SetIntSrc_A,
381 SetLoadTrig : SetLoadTrig_A,
11e865c1 382 SetMode: SetMode_A,
f7266a48 383 ResetCapFlags : ResetCapFlags_A,
11e865c1
GP		 384 MyCRA: LP_CR1A,
385 MyCRB: LP_CR1B,
f7266a48
BP		 386 MyLatchLsw : LP_CNTR1ALSW,
387 MyEventBits : EVBITS(1),
11e865c1
GP		 388 },
389 {
390 GetEnable:GetEnable_A,
f7266a48
BP		 391 GetIntSrc : GetIntSrc_A,
392 GetLoadTrig : GetLoadTrig_A,
11e865c1 393 GetMode: GetMode_A,
f7266a48
BP		 394 PulseIndex : PulseIndex_A,
395 SetEnable : SetEnable_A,
396 SetIntSrc : SetIntSrc_A,
397 SetLoadTrig : SetLoadTrig_A,
11e865c1 398 SetMode: SetMode_A,
f7266a48 399 ResetCapFlags : ResetCapFlags_A,
11e865c1
GP		 400 MyCRA: LP_CR2A,
401 MyCRB: LP_CR2B,
f7266a48
BP		 402 MyLatchLsw : LP_CNTR2ALSW,
403 MyEventBits : EVBITS(2),
11e865c1
GP		 404 },
405 {
406 GetEnable:GetEnable_B,
f7266a48
BP		 407 GetIntSrc : GetIntSrc_B,
408 GetLoadTrig : GetLoadTrig_B,
11e865c1 409 GetMode: GetMode_B,
f7266a48
BP		 410 PulseIndex : PulseIndex_B,
411 SetEnable : SetEnable_B,
412 SetIntSrc : SetIntSrc_B,
413 SetLoadTrig : SetLoadTrig_B,
11e865c1 414 SetMode: SetMode_B,
f7266a48 415 ResetCapFlags : ResetCapFlags_B,
11e865c1
GP		 416 MyCRA: LP_CR0A,
417 MyCRB: LP_CR0B,
f7266a48
BP		 418 MyLatchLsw : LP_CNTR0BLSW,
419 MyEventBits : EVBITS(3),
11e865c1
GP		 420 },
421 {
422 GetEnable:GetEnable_B,
f7266a48
BP		 423 GetIntSrc : GetIntSrc_B,
424 GetLoadTrig : GetLoadTrig_B,
11e865c1 425 GetMode: GetMode_B,
f7266a48
BP		 426 PulseIndex : PulseIndex_B,
427 SetEnable : SetEnable_B,
428 SetIntSrc : SetIntSrc_B,
429 SetLoadTrig : SetLoadTrig_B,
11e865c1 430 SetMode: SetMode_B,
f7266a48 431 ResetCapFlags : ResetCapFlags_B,
11e865c1
GP		 432 MyCRA: LP_CR1A,
433 MyCRB: LP_CR1B,
f7266a48
BP		 434 MyLatchLsw : LP_CNTR1BLSW,
435 MyEventBits : EVBITS(4),
11e865c1
GP		 436 },
437 {
438 GetEnable:GetEnable_B,
f7266a48
BP		 439 GetIntSrc : GetIntSrc_B,
440 GetLoadTrig : GetLoadTrig_B,
11e865c1 441 GetMode: GetMode_B,
f7266a48
BP		 442 PulseIndex : PulseIndex_B,
443 SetEnable : SetEnable_B,
444 SetIntSrc : SetIntSrc_B,
445 SetLoadTrig : SetLoadTrig_B,
11e865c1 446 SetMode: SetMode_B,
f7266a48 447 ResetCapFlags : ResetCapFlags_B,
11e865c1
GP		 448 MyCRA: LP_CR2A,
449 MyCRB: LP_CR2B,
f7266a48
BP		 450 MyLatchLsw : LP_CNTR2BLSW,
451 MyEventBits : EVBITS(5),
11e865c1
GP		 452 },
453};
454
b6c77757
BP		 455/* enab/disable a function or test status bit(s) that are accessed */
456/* through Main Control Registers 1 or 2. */
6a98d36e 457#define MC_ENABLE(REGADRS, CTRLWORD) writel(((uint32_t)(CTRLWORD) << 16) | (uint32_t)(CTRLWORD), devpriv->base_addr+(REGADRS))
11e865c1 458
6a98d36e 459#define MC_DISABLE(REGADRS, CTRLWORD) writel((uint32_t)(CTRLWORD) << 16 , devpriv->base_addr+(REGADRS))
11e865c1 460
6a98d36e 461#define MC_TEST(REGADRS, CTRLWORD) ((readl(devpriv->base_addr+(REGADRS)) & CTRLWORD) != 0)
11e865c1
GP		 462
463/* #define WR7146(REGARDS,CTRLWORD)
464 writel(CTRLWORD,(uint32_t)(devpriv->base_addr+(REGARDS))) */
8086fff8 465#define WR7146(REGARDS, CTRLWORD) writel(CTRLWORD, devpriv->base_addr+(REGARDS))
11e865c1
GP		 466
467/* #define RR7146(REGARDS)
468 readl((uint32_t)(devpriv->base_addr+(REGARDS))) */
469#define RR7146(REGARDS) readl(devpriv->base_addr+(REGARDS))
470
6a98d36e 471#define BUGFIX_STREG(REGADRS) (REGADRS - 4)
11e865c1 472
b6c77757 473/* Write a time slot control record to TSL2. */
6a98d36e
BP		 474#define VECTPORT(VECTNUM) (P_TSL2 + ((VECTNUM) << 2))
475#define SETVECT(VECTNUM, VECTVAL) WR7146(VECTPORT(VECTNUM), (VECTVAL))
11e865c1 476
b6c77757 477/* Code macros used for constructing I2C command bytes. */
6a98d36e
BP		 478#define I2C_B2(ATTR, VAL) (((ATTR) << 6) | ((VAL) << 24))
479#define I2C_B1(ATTR, VAL) (((ATTR) << 4) | ((VAL) << 16))
480#define I2C_B0(ATTR, VAL) (((ATTR) << 2) | ((VAL) << 8))
11e865c1
GP		 481
482static const comedi_lrange s626_range_table = { 2, {
483 RANGE(-5, 5),
484 RANGE(-10, 10),
485 }
486};
487
e473e912 488static int s626_attach(comedi_device *dev, comedi_devconfig *it)
11e865c1
GP		 489{
490/* uint8_t PollList; */
491/* uint16_t AdcData; */
492/* uint16_t StartVal; */
493/* uint16_t index; */
494/* unsigned int data[16]; */
495 int result;
496 int i;
497 int ret;
498 resource_size_t resourceStart;
499 dma_addr_t appdma;
500 comedi_subdevice *s;
501 struct pci_dev *pdev;
502
503 if (alloc_private(dev, sizeof(s626_private)) < 0)
504 return -ENOMEM;
505
506 for (pdev = pci_get_device(PCI_VENDOR_ID_S626, PCI_DEVICE_ID_S626,
507 NULL); pdev != NULL;
508 pdev = pci_get_device(PCI_VENDOR_ID_S626,
509 PCI_DEVICE_ID_S626, pdev)) {
510 if (it->options[0] || it->options[1]) {
511 if (pdev->bus->number == it->options[0] &&
512 PCI_SLOT(pdev->devfn) == it->options[1]) {
513 /* matches requested bus/slot */
514 break;
515 }
516 } else {
517 /* no bus/slot specified */
518 break;
519 }
520 }
521 devpriv->pdev = pdev;
522
523 if (pdev == NULL) {
524 printk("s626_attach: Board not present!!!\n");
525 return -ENODEV;
526 }
527
197c82bf
BP		 528 result = comedi_pci_enable(pdev, "s626");
529 if (result < 0) {
11e865c1
GP		 530 printk("s626_attach: comedi_pci_enable fails\n");
531 return -ENODEV;
532 }
533 devpriv->got_regions = 1;
534
535 resourceStart = pci_resource_start(devpriv->pdev, 0);
536
537 devpriv->base_addr = ioremap(resourceStart, SIZEOF_ADDRESS_SPACE);
538 if (devpriv->base_addr == NULL) {
539 printk("s626_attach: IOREMAP failed\n");
540 return -ENODEV;
541 }
542
543 if (devpriv->base_addr) {
b6c77757 544 /* disable master interrupt */
11e865c1
GP		 545 writel(0, devpriv->base_addr + P_IER);
546
b6c77757 547 /* soft reset */
11e865c1
GP		 548 writel(MC1_SOFT_RESET, devpriv->base_addr + P_MC1);
549
b6c77757 550 /* DMA FIXME DMA// */
11e865c1
GP		 551 DEBUG("s626_attach: DMA ALLOCATION\n");
552
b6c77757 553 /* adc buffer allocation */
11e865c1
GP		 554 devpriv->allocatedBuf = 0;
555
197c82bf
BP		 556 devpriv->ANABuf.LogicalBase =
557 pci_alloc_consistent(devpriv->pdev, DMABUF_SIZE, &appdma);
558
559 if (devpriv->ANABuf.LogicalBase == NULL) {
11e865c1
GP		 560 printk("s626_attach: DMA Memory mapping error\n");
561 return -ENOMEM;
562 }
563
564 devpriv->ANABuf.PhysicalBase = appdma;
565
566 DEBUG("s626_attach: AllocDMAB ADC Logical=%p, bsize=%d, Physical=0x%x\n", devpriv->ANABuf.LogicalBase, DMABUF_SIZE, (uint32_t) devpriv->ANABuf.PhysicalBase);
567
568 devpriv->allocatedBuf++;
569
197c82bf
BP		 570 devpriv->RPSBuf.LogicalBase =
571 pci_alloc_consistent(devpriv->pdev, DMABUF_SIZE, &appdma);
572
573 if (devpriv->RPSBuf.LogicalBase == NULL) {
11e865c1
GP		 574 printk("s626_attach: DMA Memory mapping error\n");
575 return -ENOMEM;
576 }
577
578 devpriv->RPSBuf.PhysicalBase = appdma;
579
580 DEBUG("s626_attach: AllocDMAB RPS Logical=%p, bsize=%d, Physical=0x%x\n", devpriv->RPSBuf.LogicalBase, DMABUF_SIZE, (uint32_t) devpriv->RPSBuf.PhysicalBase);
581
582 devpriv->allocatedBuf++;
583
584 }
585
586 dev->board_ptr = s626_boards;
587 dev->board_name = thisboard->name;
588
589 if (alloc_subdevices(dev, 6) < 0)
590 return -ENOMEM;
591
592 dev->iobase = (unsigned long)devpriv->base_addr;
593 dev->irq = devpriv->pdev->irq;
594
b6c77757 595 /* set up interrupt handler */
11e865c1
GP		 596 if (dev->irq == 0) {
597 printk(" unknown irq (bad)\n");
598 } else {
197c82bf
BP		 599 ret = comedi_request_irq(dev->irq, s626_irq_handler,
600 IRQF_SHARED, "s626", dev);
601
602 if (ret < 0) {
11e865c1
GP		 603 printk(" irq not available\n");
604 dev->irq = 0;
605 }
606 }
607
608 DEBUG("s626_attach: -- it opts %d,%d -- \n",
609 it->options[0], it->options[1]);
610
611 s = dev->subdevices + 0;
612 /* analog input subdevice */
613 dev->read_subdev = s;
614 /* we support single-ended (ground) and differential */
615 s->type = COMEDI_SUBD_AI;
616 s->subdev_flags = SDF_READABLE | SDF_DIFF | SDF_CMD_READ;
617 s->n_chan = thisboard->ai_chans;
618 s->maxdata = (0xffff >> 2);
619 s->range_table = &s626_range_table;
620 s->len_chanlist = thisboard->ai_chans; /* This is the maximum chanlist
621 length that the board can
622 handle */
623 s->insn_config = s626_ai_insn_config;
624 s->insn_read = s626_ai_insn_read;
625 s->do_cmd = s626_ai_cmd;
626 s->do_cmdtest = s626_ai_cmdtest;
627 s->cancel = s626_ai_cancel;
628
629 s = dev->subdevices + 1;
630 /* analog output subdevice */
631 s->type = COMEDI_SUBD_AO;
632 s->subdev_flags = SDF_WRITABLE | SDF_READABLE;
633 s->n_chan = thisboard->ao_chans;
634 s->maxdata = (0x3fff);
635 s->range_table = &range_bipolar10;
636 s->insn_write = s626_ao_winsn;
637 s->insn_read = s626_ao_rinsn;
638
639 s = dev->subdevices + 2;
640 /* digital I/O subdevice */
641 s->type = COMEDI_SUBD_DIO;
642 s->subdev_flags = SDF_WRITABLE | SDF_READABLE;
643 s->n_chan = S626_DIO_CHANNELS;
644 s->maxdata = 1;
645 s->io_bits = 0xffff;
646 s->private = &dio_private_A;
647 s->range_table = &range_digital;
648 s->insn_config = s626_dio_insn_config;
649 s->insn_bits = s626_dio_insn_bits;
650
651 s = dev->subdevices + 3;
652 /* digital I/O subdevice */
653 s->type = COMEDI_SUBD_DIO;
654 s->subdev_flags = SDF_WRITABLE | SDF_READABLE;
655 s->n_chan = 16;
656 s->maxdata = 1;
657 s->io_bits = 0xffff;
658 s->private = &dio_private_B;
659 s->range_table = &range_digital;
660 s->insn_config = s626_dio_insn_config;
661 s->insn_bits = s626_dio_insn_bits;
662
663 s = dev->subdevices + 4;
664 /* digital I/O subdevice */
665 s->type = COMEDI_SUBD_DIO;
666 s->subdev_flags = SDF_WRITABLE | SDF_READABLE;
667 s->n_chan = 16;
668 s->maxdata = 1;
669 s->io_bits = 0xffff;
670 s->private = &dio_private_C;
671 s->range_table = &range_digital;
672 s->insn_config = s626_dio_insn_config;
673 s->insn_bits = s626_dio_insn_bits;
674
675 s = dev->subdevices + 5;
676 /* encoder (counter) subdevice */
677 s->type = COMEDI_SUBD_COUNTER;
678 s->subdev_flags = SDF_WRITABLE | SDF_READABLE | SDF_LSAMPL;
679 s->n_chan = thisboard->enc_chans;
680 s->private = enc_private_data;
681 s->insn_config = s626_enc_insn_config;
682 s->insn_read = s626_enc_insn_read;
683 s->insn_write = s626_enc_insn_write;
684 s->maxdata = 0xffffff;
685 s->range_table = &range_unknown;
686
b6c77757 687 /* stop ai_command */
11e865c1
GP		 688 devpriv->ai_cmd_running = 0;
689
690 if (devpriv->base_addr && (devpriv->allocatedBuf == 2)) {
691 dma_addr_t pPhysBuf;
692 uint16_t chan;
693
b6c77757 694 /* enab DEBI and audio pins, enable I2C interface. */
11e865c1 695 MC_ENABLE(P_MC1, MC1_DEBI | MC1_AUDIO | MC1_I2C);
b6c77757
BP		 696 /* Configure DEBI operating mode. */
697 WR7146(P_DEBICFG, DEBI_CFG_SLAVE16 /* Local bus is 16 */
698 /* bits wide. */
699 | (DEBI_TOUT << DEBI_CFG_TOUT_BIT) /* Declare DEBI */
700 /* transfer timeout */
701 /* interval. */
702 | DEBI_SWAP /* Set up byte lane */
703 /* steering. */
704 | DEBI_CFG_INTEL); /* Intel-compatible */
705 /* local bus (DEBI */
706 /* never times out). */
11e865c1
GP		 707 DEBUG("s626_attach: %d debi init -- %d\n",
708 DEBI_CFG_SLAVE16 | (DEBI_TOUT << DEBI_CFG_TOUT_BIT) |
709 DEBI_SWAP | DEBI_CFG_INTEL,
710 DEBI_CFG_INTEL | DEBI_CFG_TOQ | DEBI_CFG_INCQ |
711 DEBI_CFG_16Q);
712
b6c77757
BP		 713 /* DEBI INIT S626 WR7146( P_DEBICFG, DEBI_CFG_INTEL | DEBI_CFG_TOQ */
714 /* | DEBI_CFG_INCQ| DEBI_CFG_16Q); //end */
11e865c1 715
b6c77757
BP		 716 /* Paging is disabled. */
717 WR7146(P_DEBIPAGE, DEBI_PAGE_DISABLE); /* Disable MMU paging. */
11e865c1 718
b6c77757 719 /* Init GPIO so that ADC Start* is negated. */
11e865c1
GP		 720 WR7146(P_GPIO, GPIO_BASE | GPIO1_HI);
721
b6c77757
BP		 722 /* IsBoardRevA is a boolean that indicates whether the board is RevA.
723 *
724 * VERSION 2.01 CHANGE: REV A & B BOARDS NOW SUPPORTED BY DYNAMIC
725 * EEPROM ADDRESS SELECTION. Initialize the I2C interface, which
726 * is used to access the onboard serial EEPROM. The EEPROM's I2C
727 * DeviceAddress is hardwired to a value that is dependent on the
728 * 626 board revision. On all board revisions, the EEPROM stores
729 * TrimDAC calibration constants for analog I/O. On RevB and
730 * higher boards, the DeviceAddress is hardwired to 0 to enable
731 * the EEPROM to also store the PCI SubVendorID and SubDeviceID;
732 * this is the address at which the SAA7146 expects a
733 * configuration EEPROM to reside. On RevA boards, the EEPROM
734 * device address, which is hardwired to 4, prevents the SAA7146
735 * from retrieving PCI sub-IDs, so the SAA7146 uses its built-in
736 * default values, instead.
737 */
738
739 /* devpriv->I2Cards= IsBoardRevA ? 0xA8 : 0xA0; // Set I2C EEPROM */
740 /* DeviceType (0xA0) */
741 /* and DeviceAddress<<1. */
742
743 devpriv->I2CAdrs = 0xA0; /* I2C device address for onboard */
744 /* eeprom(revb) */
745
746 /* Issue an I2C ABORT command to halt any I2C operation in */
747 /* progress and reset BUSY flag. */
748 WR7146(P_I2CSTAT, I2C_CLKSEL | I2C_ABORT);
749 /* Write I2C control: abort any I2C activity. */
750 MC_ENABLE(P_MC2, MC2_UPLD_IIC);
751 /* Invoke command upload */
752 while ((RR7146(P_MC2) & MC2_UPLD_IIC) == 0);
753 /* and wait for upload to complete. */
754
755 /* Per SAA7146 data sheet, write to STATUS reg twice to
756 * reset all I2C error flags. */
11e865c1 757 for (i = 0; i < 2; i++) {
b6c77757
BP		 758 WR7146(P_I2CSTAT, I2C_CLKSEL);
759 /* Write I2C control: reset error flags. */
760 MC_ENABLE(P_MC2, MC2_UPLD_IIC); /* Invoke command upload */
761 while (!MC_TEST(P_MC2, MC2_UPLD_IIC));
762 /* and wait for upload to complete. */
11e865c1
GP		 763 }
764
b6c77757
BP		 765 /* Init audio interface functional attributes: set DAC/ADC
766 * serial clock rates, invert DAC serial clock so that
767 * DAC data setup times are satisfied, enable DAC serial
768 * clock out.
769 */
770
11e865c1
GP		 771 WR7146(P_ACON2, ACON2_INIT);
772
b6c77757
BP		 773 /* Set up TSL1 slot list, which is used to control the
774 * accumulation of ADC data: RSD1 = shift data in on SD1.
775 * SIB_A1 = store data uint8_t at next available location in
776 * FB BUFFER1 register. */
777 WR7146(P_TSL1, RSD1 | SIB_A1);
778 /* Fetch ADC high data uint8_t. */
779 WR7146(P_TSL1 + 4, RSD1 | SIB_A1 | EOS);
780 /* Fetch ADC low data uint8_t; end of TSL1. */
781
782 /* enab TSL1 slot list so that it executes all the time. */
11e865c1
GP		 783 WR7146(P_ACON1, ACON1_ADCSTART);
784
b6c77757 785 /* Initialize RPS registers used for ADC. */
11e865c1 786
b6c77757 787 /* Physical start of RPS program. */
11e865c1
GP		 788 WR7146(P_RPSADDR1, (uint32_t) devpriv->RPSBuf.PhysicalBase);
789
b6c77757
BP		 790 WR7146(P_RPSPAGE1, 0);
791 /* RPS program performs no explicit mem writes. */
792 WR7146(P_RPS1_TOUT, 0); /* Disable RPS timeouts. */
11e865c1 793
b6c77757
BP		 794 /* SAA7146 BUG WORKAROUND. Initialize SAA7146 ADC interface
795 * to a known state by invoking ADCs until FB BUFFER 1
796 * register shows that it is correctly receiving ADC data.
797 * This is necessary because the SAA7146 ADC interface does
798 * not start up in a defined state after a PCI reset.
799 */
11e865c1
GP		 800
801/* PollList = EOPL; // Create a simple polling */
802/* // list for analog input */
803/* // channel 0. */
804/* ResetADC( dev, &PollList ); */
805
806/* s626_ai_rinsn(dev,dev->subdevices,NULL,data); //( &AdcData ); // */
807/* //Get initial ADC */
808/* //value. */
809
810/* StartVal = data[0]; */
811
812/* // VERSION 2.01 CHANGE: TIMEOUT ADDED TO PREVENT HANGED EXECUTION. */
813/* // Invoke ADCs until the new ADC value differs from the initial */
814/* // value or a timeout occurs. The timeout protects against the */
815/* // possibility that the driver is restarting and the ADC data is a */
816/* // fixed value resulting from the applied ADC analog input being */
817/* // unusually quiet or at the rail. */
818
819/* for ( index = 0; index < 500; index++ ) */
820/* { */
821/* s626_ai_rinsn(dev,dev->subdevices,NULL,data); */
822/* AdcData = data[0]; //ReadADC( &AdcData ); */
823/* if ( AdcData != StartVal ) */
824/* break; */
825/* } */
826
b6c77757 827 /* end initADC */
11e865c1 828
b6c77757 829 /* init the DAC interface */
11e865c1 830
b6c77757
BP		 831 /* Init Audio2's output DMAC attributes: burst length = 1
832 * DWORD, threshold = 1 DWORD.
833 */
11e865c1
GP		 834 WR7146(P_PCI_BT_A, 0);
835
b6c77757
BP		 836 /* Init Audio2's output DMA physical addresses. The protection
837 * address is set to 1 DWORD past the base address so that a
838 * single DWORD will be transferred each time a DMA transfer is
839 * enabled. */
11e865c1
GP		 840
841 pPhysBuf =
842 devpriv->ANABuf.PhysicalBase +
843 (DAC_WDMABUF_OS * sizeof(uint32_t));
844
b6c77757
BP		 845 WR7146(P_BASEA2_OUT, (uint32_t) pPhysBuf); /* Buffer base adrs. */
846 WR7146(P_PROTA2_OUT, (uint32_t) (pPhysBuf + sizeof(uint32_t))); /* Protection address. */
11e865c1 847
b6c77757
BP		 848 /* Cache Audio2's output DMA buffer logical address. This is
849 * where DAC data is buffered for A2 output DMA transfers. */
11e865c1
GP		 850 devpriv->pDacWBuf =
851 (uint32_t *) devpriv->ANABuf.LogicalBase +
852 DAC_WDMABUF_OS;
853
b6c77757
BP		 854 /* Audio2's output channels does not use paging. The protection
855 * violation handling bit is set so that the DMAC will
856 * automatically halt and its PCI address pointer will be reset
857 * when the protection address is reached. */
858
11e865c1
GP		 859 WR7146(P_PAGEA2_OUT, 8);
860
b6c77757
BP		 861 /* Initialize time slot list 2 (TSL2), which is used to control
862 * the clock generation for and serialization of data to be sent
863 * to the DAC devices. Slot 0 is a NOP that is used to trap TSL
864 * execution; this permits other slots to be safely modified
865 * without first turning off the TSL sequencer (which is
866 * apparently impossible to do). Also, SD3 (which is driven by a
867 * pull-up resistor) is shifted in and stored to the MSB of
868 * FB_BUFFER2 to be used as evidence that the slot sequence has
869 * not yet finished executing.
870 */
871
872 SETVECT(0, XSD2 | RSD3 | SIB_A2 | EOS);
873 /* Slot 0: Trap TSL execution, shift 0xFF into FB_BUFFER2. */
874
875 /* Initialize slot 1, which is constant. Slot 1 causes a
876 * DWORD to be transferred from audio channel 2's output FIFO
877 * to the FIFO's output buffer so that it can be serialized
878 * and sent to the DAC during subsequent slots. All remaining
879 * slots are dynamically populated as required by the target
880 * DAC device.
881 */
882 SETVECT(1, LF_A2);
883 /* Slot 1: Fetch DWORD from Audio2's output FIFO. */
884
885 /* Start DAC's audio interface (TSL2) running. */
11e865c1
GP		 886 WR7146(P_ACON1, ACON1_DACSTART);
887
b6c77757 888 /* end init DAC interface */
11e865c1 889
b6c77757
BP		 890 /* Init Trim DACs to calibrated values. Do it twice because the
891 * SAA7146 audio channel does not always reset properly and
892 * sometimes causes the first few TrimDAC writes to malfunction.
893 */
11e865c1
GP		 894
895 LoadTrimDACs(dev);
b6c77757 896 LoadTrimDACs(dev); /* Insurance. */
11e865c1 897
b6c77757
BP		 898 /* Manually init all gate array hardware in case this is a soft
899 * reset (we have no way of determining whether this is a warm
900 * or cold start). This is necessary because the gate array will
901 * reset only in response to a PCI hard reset; there is no soft
902 * reset function. */
11e865c1 903
b6c77757
BP		 904 /* Init all DAC outputs to 0V and init all DAC setpoint and
905 * polarity images.
906 */
11e865c1
GP		 907 for (chan = 0; chan < S626_DAC_CHANNELS; chan++)
908 SetDAC(dev, chan, 0);
909
b6c77757
BP		 910 /* Init image of WRMISC2 Battery Charger Enabled control bit.
911 * This image is used when the state of the charger control bit,
912 * which has no direct hardware readback mechanism, is queried.
913 */
11e865c1
GP		 914 devpriv->ChargeEnabled = 0;
915
b6c77757
BP		 916 /* Init image of watchdog timer interval in WRMISC2. This image
917 * maintains the value of the control bits of MISC2 are
918 * continuously reset to zero as long as the WD timer is disabled.
919 */
11e865c1
GP		 920 devpriv->WDInterval = 0;
921
b6c77757
BP		 922 /* Init Counter Interrupt enab mask for RDMISC2. This mask is
923 * applied against MISC2 when testing to determine which timer
924 * events are requesting interrupt service.
925 */
11e865c1
GP		 926 devpriv->CounterIntEnabs = 0;
927
b6c77757 928 /* Init counters. */
11e865c1
GP		 929 CountersInit(dev);
930
b6c77757
BP		 931 /* Without modifying the state of the Battery Backup enab, disable
932 * the watchdog timer, set DIO channels 0-5 to operate in the
933 * standard DIO (vs. counter overflow) mode, disable the battery
934 * charger, and reset the watchdog interval selector to zero.
935 */
11e865c1
GP		 936 WriteMISC2(dev, (uint16_t) (DEBIread(dev,
937 LP_RDMISC2) & MISC2_BATT_ENABLE));
938
b6c77757 939 /* Initialize the digital I/O subsystem. */
11e865c1
GP		 940 s626_dio_init(dev);
941
b6c77757
BP		 942 /* enable interrupt test */
943 /* writel(IRQ_GPIO3 | IRQ_RPS1,devpriv->base_addr+P_IER); */
11e865c1
GP		 944 }
945
946 DEBUG("s626_attach: comedi%d s626 attached %04x\n", dev->minor,
947 (uint32_t) devpriv->base_addr);
948
949 return 1;
950}
951
952static lsampl_t s626_ai_reg_to_uint(int data)
953{
954 lsampl_t tempdata;
955
956 tempdata = (data >> 18);
957 if (tempdata & 0x2000)
958 tempdata &= 0x1fff;
959 else
960 tempdata += (1 << 13);
961
962 return tempdata;
963}
964
965/* static lsampl_t s626_uint_to_reg(comedi_subdevice *s, int data){ */
966/* return 0; */
967/* } */
968
969static irqreturn_t s626_irq_handler(int irq, void *d PT_REGS_ARG)
970{
971 comedi_device *dev = d;
972 comedi_subdevice *s;
973 comedi_cmd *cmd;
974 enc_private *k;
975 unsigned long flags;
976 int32_t *readaddr;
977 uint32_t irqtype, irqstatus;
978 int i = 0;
979 sampl_t tempdata;
980 uint8_t group;
981 uint16_t irqbit;
982
983 DEBUG("s626_irq_handler: interrupt request recieved!!!\n");
984
985 if (dev->attached == 0)
986 return IRQ_NONE;
b6c77757 987 /* lock to avoid race with comedi_poll */
11e865c1
GP		 988 comedi_spin_lock_irqsave(&dev->spinlock, flags);
989
b6c77757 990 /* save interrupt enable register state */
11e865c1
GP		 991 irqstatus = readl(devpriv->base_addr + P_IER);
992
b6c77757 993 /* read interrupt type */
11e865c1
GP		 994 irqtype = readl(devpriv->base_addr + P_ISR);
995
b6c77757 996 /* disable master interrupt */
11e865c1
GP		 997 writel(0, devpriv->base_addr + P_IER);
998
b6c77757 999 /* clear interrupt */
11e865c1
GP		 1000 writel(irqtype, devpriv->base_addr + P_ISR);
1001
b6c77757 1002 /* do somethings */
11e865c1
GP		 1003 DEBUG("s626_irq_handler: interrupt type %d\n", irqtype);
1004
1005 switch (irqtype) {
b6c77757 1006 case IRQ_RPS1: /* end_of_scan occurs */
11e865c1
GP		 1007
1008 DEBUG("s626_irq_handler: RPS1 irq detected\n");
1009
b6c77757 1010 /* manage ai subdevice */
11e865c1
GP		 1011 s = dev->subdevices;
1012 cmd = &(s->async->cmd);
1013
b6c77757
BP		 1014 /* Init ptr to DMA buffer that holds new ADC data. We skip the
1015 * first uint16_t in the buffer because it contains junk data from
1016 * the final ADC of the previous poll list scan.
1017 */
11e865c1
GP		 1018 readaddr = (int32_t *) devpriv->ANABuf.LogicalBase + 1;
1019
b6c77757 1020 /* get the data and hand it over to comedi */
11e865c1 1021 for (i = 0; i < (s->async->cmd.chanlist_len); i++) {
b6c77757
BP		 1022 /* Convert ADC data to 16-bit integer values and copy to application */
1023 /* buffer. */
11e865c1
GP		 1024 tempdata = s626_ai_reg_to_uint((int)*readaddr);
1025 readaddr++;
1026
b6c77757
BP		 1027 /* put data into read buffer */
1028 /* comedi_buf_put(s->async, tempdata); */
11e865c1
GP		 1029 if (cfc_write_to_buffer(s, tempdata) == 0)
1030 printk("s626_irq_handler: cfc_write_to_buffer error!\n");
1031
1032 DEBUG("s626_irq_handler: ai channel %d acquired: %d\n",
1033 i, tempdata);
1034 }
1035
b6c77757 1036 /* end of scan occurs */
11e865c1
GP		 1037 s->async->events |= COMEDI_CB_EOS;
1038
1039 if (!(devpriv->ai_continous))
1040 devpriv->ai_sample_count--;
1041 if (devpriv->ai_sample_count <= 0) {
1042 devpriv->ai_cmd_running = 0;
1043
b6c77757 1044 /* Stop RPS program. */
11e865c1
GP		 1045 MC_DISABLE(P_MC1, MC1_ERPS1);
1046
b6c77757 1047 /* send end of acquisition */
11e865c1
GP		 1048 s->async->events |= COMEDI_CB_EOA;
1049
b6c77757 1050 /* disable master interrupt */
11e865c1
GP		 1051 irqstatus = 0;
1052 }
1053
1054 if (devpriv->ai_cmd_running && cmd->scan_begin_src == TRIG_EXT) {
1055 DEBUG("s626_irq_handler: enable interrupt on dio channel %d\n", cmd->scan_begin_arg);
1056
1057 s626_dio_set_irq(dev, cmd->scan_begin_arg);
1058
1059 DEBUG("s626_irq_handler: External trigger is set!!!\n");
1060 }
b6c77757 1061 /* tell comedi that data is there */
11e865c1
GP		 1062 DEBUG("s626_irq_handler: events %d\n", s->async->events);
1063 comedi_event(dev, s);
1064 break;
b6c77757 1065 case IRQ_GPIO3: /* check dio and conter interrupt */
11e865c1
GP		 1066
1067 DEBUG("s626_irq_handler: GPIO3 irq detected\n");
1068
b6c77757 1069 /* manage ai subdevice */
11e865c1
GP		 1070 s = dev->subdevices;
1071 cmd = &(s->async->cmd);
1072
b6c77757 1073 /* s626_dio_clear_irq(dev); */
11e865c1
GP		 1074
1075 for (group = 0; group < S626_DIO_BANKS; group++) {
1076 irqbit = 0;
b6c77757 1077 /* read interrupt type */
11e865c1
GP		 1078 irqbit = DEBIread(dev,
1079 ((dio_private *) (dev->subdevices + 2 +
1080 group)->private)->RDCapFlg);
1081
b6c77757 1082 /* check if interrupt is generated from dio channels */
11e865c1
GP		 1083 if (irqbit) {
1084 s626_dio_reset_irq(dev, group, irqbit);
1085 DEBUG("s626_irq_handler: check interrupt on dio group %d %d\n", group, i);
1086 if (devpriv->ai_cmd_running) {
b6c77757 1087 /* check if interrupt is an ai acquisition start trigger */
11e865c1
GP		 1088 if ((irqbit >> (cmd->start_arg -
1089 (16 * group)))
1090 == 1
1091 && cmd->start_src == TRIG_EXT) {
1092 DEBUG("s626_irq_handler: Edge capture interrupt recieved from channel %d\n", cmd->start_arg);
1093
b6c77757 1094 /* Start executing the RPS program. */
11e865c1
GP		 1095 MC_ENABLE(P_MC1, MC1_ERPS1);
1096
1097 DEBUG("s626_irq_handler: aquisition start triggered!!!\n");
1098
1099 if (cmd->scan_begin_src ==
1100 TRIG_EXT) {
1101 DEBUG("s626_ai_cmd: enable interrupt on dio channel %d\n", cmd->scan_begin_arg);
1102
1103 s626_dio_set_irq(dev,
1104 cmd->
1105 scan_begin_arg);
1106
1107 DEBUG("s626_irq_handler: External scan trigger is set!!!\n");
1108 }
1109 }
1110 if ((irqbit >> (cmd->scan_begin_arg -
1111 (16 * group)))
1112 == 1
1113 && cmd->scan_begin_src ==
1114 TRIG_EXT) {
1115 DEBUG("s626_irq_handler: Edge capture interrupt recieved from channel %d\n", cmd->scan_begin_arg);
1116
b6c77757 1117 /* Trigger ADC scan loop start by setting RPS Signal 0. */
11e865c1
GP		 1118 MC_ENABLE(P_MC2, MC2_ADC_RPS);
1119
1120 DEBUG("s626_irq_handler: scan triggered!!! %d\n", devpriv->ai_sample_count);
1121 if (cmd->convert_src ==
1122 TRIG_EXT) {
1123
1124 DEBUG("s626_ai_cmd: enable interrupt on dio channel %d group %d\n", cmd->convert_arg - (16 * group), group);
1125
1126 devpriv->
1127 ai_convert_count
1128 =
1129 cmd->
1130 chanlist_len;
1131
1132 s626_dio_set_irq(dev,
1133 cmd->
1134 convert_arg);
1135
1136 DEBUG("s626_irq_handler: External convert trigger is set!!!\n");
1137 }
1138
1139 if (cmd->convert_src ==
1140 TRIG_TIMER) {
1141 k = &encpriv[5];
1142 devpriv->
1143 ai_convert_count
1144 =
1145 cmd->
1146 chanlist_len;
1147 k->SetEnable(dev, k,
1148 CLKENAB_ALWAYS);
1149 }
1150 }
1151 if ((irqbit >> (cmd->convert_arg -
1152 (16 * group)))
1153 == 1
1154 && cmd->convert_src ==
1155 TRIG_EXT) {
1156 DEBUG("s626_irq_handler: Edge capture interrupt recieved from channel %d\n", cmd->convert_arg);
1157
b6c77757 1158 /* Trigger ADC scan loop start by setting RPS Signal 0. */
11e865c1
GP		 1159 MC_ENABLE(P_MC2, MC2_ADC_RPS);
1160
1161 DEBUG("s626_irq_handler: adc convert triggered!!!\n");
1162
1163 devpriv->ai_convert_count--;
1164
1165 if (devpriv->ai_convert_count >
1166 0) {
1167
1168 DEBUG("s626_ai_cmd: enable interrupt on dio channel %d group %d\n", cmd->convert_arg - (16 * group), group);
1169
1170 s626_dio_set_irq(dev,
1171 cmd->
1172 convert_arg);
1173
1174 DEBUG("s626_irq_handler: External trigger is set!!!\n");
1175 }
1176 }
1177 }
1178 break;
1179 }
1180 }
1181
b6c77757 1182 /* read interrupt type */
11e865c1
GP		 1183 irqbit = DEBIread(dev, LP_RDMISC2);
1184
b6c77757 1185 /* check interrupt on counters */
11e865c1
GP		 1186 DEBUG("s626_irq_handler: check counters interrupt %d\n",
1187 irqbit);
1188
1189 if (irqbit & IRQ_COINT1A) {
1190 DEBUG("s626_irq_handler: interrupt on counter 1A overflow\n");
1191 k = &encpriv[0];
1192
b6c77757 1193 /* clear interrupt capture flag */
11e865c1
GP		 1194 k->ResetCapFlags(dev, k);
1195 }
1196 if (irqbit & IRQ_COINT2A) {
1197 DEBUG("s626_irq_handler: interrupt on counter 2A overflow\n");
1198 k = &encpriv[1];
1199
b6c77757 1200 /* clear interrupt capture flag */
11e865c1
GP		 1201 k->ResetCapFlags(dev, k);
1202 }
1203 if (irqbit & IRQ_COINT3A) {
1204 DEBUG("s626_irq_handler: interrupt on counter 3A overflow\n");
1205 k = &encpriv[2];
1206
b6c77757 1207 /* clear interrupt capture flag */
11e865c1
GP		 1208 k->ResetCapFlags(dev, k);
1209 }
1210 if (irqbit & IRQ_COINT1B) {
1211 DEBUG("s626_irq_handler: interrupt on counter 1B overflow\n");
1212 k = &encpriv[3];
1213
b6c77757 1214 /* clear interrupt capture flag */
11e865c1
GP		 1215 k->ResetCapFlags(dev, k);
1216 }
1217 if (irqbit & IRQ_COINT2B) {
1218 DEBUG("s626_irq_handler: interrupt on counter 2B overflow\n");
1219 k = &encpriv[4];
1220
b6c77757 1221 /* clear interrupt capture flag */
11e865c1
GP		 1222 k->ResetCapFlags(dev, k);
1223
1224 if (devpriv->ai_convert_count > 0) {
1225 devpriv->ai_convert_count--;
1226 if (devpriv->ai_convert_count == 0)
1227 k->SetEnable(dev, k, CLKENAB_INDEX);
1228
1229 if (cmd->convert_src == TRIG_TIMER) {
1230 DEBUG("s626_irq_handler: conver timer trigger!!! %d\n", devpriv->ai_convert_count);
1231
b6c77757 1232 /* Trigger ADC scan loop start by setting RPS Signal 0. */
11e865c1
GP		 1233 MC_ENABLE(P_MC2, MC2_ADC_RPS);
1234 }
1235 }
1236 }
1237 if (irqbit & IRQ_COINT3B) {
1238 DEBUG("s626_irq_handler: interrupt on counter 3B overflow\n");
1239 k = &encpriv[5];
1240
b6c77757 1241 /* clear interrupt capture flag */
11e865c1
GP		 1242 k->ResetCapFlags(dev, k);
1243
1244 if (cmd->scan_begin_src == TRIG_TIMER) {
1245 DEBUG("s626_irq_handler: scan timer trigger!!!\n");
1246
b6c77757 1247 /* Trigger ADC scan loop start by setting RPS Signal 0. */
11e865c1
GP		 1248 MC_ENABLE(P_MC2, MC2_ADC_RPS);
1249 }
1250
1251 if (cmd->convert_src == TRIG_TIMER) {
1252 DEBUG("s626_irq_handler: convert timer trigger is set\n");
1253 k = &encpriv[4];
1254 devpriv->ai_convert_count = cmd->chanlist_len;
1255 k->SetEnable(dev, k, CLKENAB_ALWAYS);
1256 }
1257 }
1258 }
1259
b6c77757 1260 /* enable interrupt */
11e865c1
GP		 1261 writel(irqstatus, devpriv->base_addr + P_IER);
1262
1263 DEBUG("s626_irq_handler: exit interrupt service routine.\n");
1264
1265 comedi_spin_unlock_irqrestore(&dev->spinlock, flags);
1266 return IRQ_HANDLED;
1267}
1268
e473e912 1269static int s626_detach(comedi_device *dev)
11e865c1
GP		 1270{
1271 if (devpriv) {
b6c77757 1272 /* stop ai_command */
11e865c1
GP		 1273 devpriv->ai_cmd_running = 0;
1274
1275 if (devpriv->base_addr) {
b6c77757
BP		 1276 /* interrupt mask */
1277 WR7146(P_IER, 0); /* Disable master interrupt. */
1278 WR7146(P_ISR, IRQ_GPIO3 | IRQ_RPS1); /* Clear board's IRQ status flag. */
11e865c1 1279
b6c77757 1280 /* Disable the watchdog timer and battery charger. */
11e865c1
GP		 1281 WriteMISC2(dev, 0);
1282
b6c77757 1283 /* Close all interfaces on 7146 device. */
11e865c1
GP		 1284 WR7146(P_MC1, MC1_SHUTDOWN);
1285 WR7146(P_ACON1, ACON1_BASE);
1286
1287 CloseDMAB(dev, &devpriv->RPSBuf, DMABUF_SIZE);
1288 CloseDMAB(dev, &devpriv->ANABuf, DMABUF_SIZE);
1289 }
1290
1291 if (dev->irq) {
1292 comedi_free_irq(dev->irq, dev);
1293 }
1294
1295 if (devpriv->base_addr) {
1296 iounmap(devpriv->base_addr);
1297 }
1298
1299 if (devpriv->pdev) {
1300 if (devpriv->got_regions) {
1301 comedi_pci_disable(devpriv->pdev);
1302 }
1303 pci_dev_put(devpriv->pdev);
1304 }
1305 }
1306
1307 DEBUG("s626_detach: S626 detached!\n");
1308
1309 return 0;
1310}
1311
1312/*
1313 * this functions build the RPS program for hardware driven acquistion
1314 */
e473e912 1315void ResetADC(comedi_device *dev, uint8_t *ppl)
11e865c1
GP		 1316{
1317 register uint32_t *pRPS;
1318 uint32_t JmpAdrs;
1319 uint16_t i;
1320 uint16_t n;
1321 uint32_t LocalPPL;
1322 comedi_cmd *cmd = &(dev->subdevices->async->cmd);
1323
b6c77757 1324 /* Stop RPS program in case it is currently running. */
11e865c1
GP		 1325 MC_DISABLE(P_MC1, MC1_ERPS1);
1326
b6c77757 1327 /* Set starting logical address to write RPS commands. */
11e865c1
GP		 1328 pRPS = (uint32_t *) devpriv->RPSBuf.LogicalBase;
1329
b6c77757 1330 /* Initialize RPS instruction pointer. */
11e865c1
GP		 1331 WR7146(P_RPSADDR1, (uint32_t) devpriv->RPSBuf.PhysicalBase);
1332
b6c77757 1333 /* Construct RPS program in RPSBuf DMA buffer */
11e865c1
GP		 1334
1335 if (cmd != NULL && cmd->scan_begin_src != TRIG_FOLLOW) {
1336 DEBUG("ResetADC: scan_begin pause inserted\n");
b6c77757 1337 /* Wait for Start trigger. */
11e865c1
GP		 1338 *pRPS++ = RPS_PAUSE | RPS_SIGADC;
1339 *pRPS++ = RPS_CLRSIGNAL | RPS_SIGADC;
1340 }
b6c77757
BP		 1341
1342 /* SAA7146 BUG WORKAROUND Do a dummy DEBI Write. This is necessary
1343 * because the first RPS DEBI Write following a non-RPS DEBI write
1344 * seems to always fail. If we don't do this dummy write, the ADC
1345 * gain might not be set to the value required for the first slot in
1346 * the poll list; the ADC gain would instead remain unchanged from
1347 * the previously programmed value.
1348 */
1349 *pRPS++ = RPS_LDREG | (P_DEBICMD >> 2);
1350 /* Write DEBI Write command and address to shadow RAM. */
1351
11e865c1 1352 *pRPS++ = DEBI_CMD_WRWORD | LP_GSEL;
b6c77757
BP		 1353 *pRPS++ = RPS_LDREG | (P_DEBIAD >> 2);
1354 /* Write DEBI immediate data to shadow RAM: */
1355
1356 *pRPS++ = GSEL_BIPOLAR5V;
1357 /* arbitrary immediate data value. */
1358
1359 *pRPS++ = RPS_CLRSIGNAL | RPS_DEBI;
1360 /* Reset "shadow RAM uploaded" flag. */
1361 *pRPS++ = RPS_UPLOAD | RPS_DEBI; /* Invoke shadow RAM upload. */
1362 *pRPS++ = RPS_PAUSE | RPS_DEBI; /* Wait for shadow upload to finish. */
1363
1364 /* Digitize all slots in the poll list. This is implemented as a
1365 * for loop to limit the slot count to 16 in case the application
1366 * forgot to set the EOPL flag in the final slot.
1367 */
11e865c1 1368 for (devpriv->AdcItems = 0; devpriv->AdcItems < 16; devpriv->AdcItems++) {
b6c77757
BP		 1369 /* Convert application's poll list item to private board class
1370 * format. Each app poll list item is an uint8_t with form
1371 * (EOPL,x,x,RANGE,CHAN<3:0>), where RANGE code indicates 0 =
1372 * +-10V, 1 = +-5V, and EOPL = End of Poll List marker.
1373 */
11e865c1
GP		 1374 LocalPPL =
1375 (*ppl << 8) | (*ppl & 0x10 ? GSEL_BIPOLAR5V :
1376 GSEL_BIPOLAR10V);
1377
b6c77757
BP		 1378 /* Switch ADC analog gain. */
1379 *pRPS++ = RPS_LDREG | (P_DEBICMD >> 2); /* Write DEBI command */
1380 /* and address to */
1381 /* shadow RAM. */
11e865c1 1382 *pRPS++ = DEBI_CMD_WRWORD | LP_GSEL;
b6c77757
BP		 1383 *pRPS++ = RPS_LDREG | (P_DEBIAD >> 2); /* Write DEBI */
1384 /* immediate data to */
1385 /* shadow RAM. */
11e865c1 1386 *pRPS++ = LocalPPL;
b6c77757
BP		 1387 *pRPS++ = RPS_CLRSIGNAL | RPS_DEBI; /* Reset "shadow RAM uploaded" */
1388 /* flag. */
1389 *pRPS++ = RPS_UPLOAD | RPS_DEBI; /* Invoke shadow RAM upload. */
1390 *pRPS++ = RPS_PAUSE | RPS_DEBI; /* Wait for shadow upload to */
1391 /* finish. */
1392
1393 /* Select ADC analog input channel. */
1394 *pRPS++ = RPS_LDREG | (P_DEBICMD >> 2);
1395 /* Write DEBI command and address to shadow RAM. */
11e865c1 1396 *pRPS++ = DEBI_CMD_WRWORD | LP_ISEL;
b6c77757
BP		 1397 *pRPS++ = RPS_LDREG | (P_DEBIAD >> 2);
1398 /* Write DEBI immediate data to shadow RAM. */
11e865c1 1399 *pRPS++ = LocalPPL;
b6c77757
BP		 1400 *pRPS++ = RPS_CLRSIGNAL | RPS_DEBI;
1401 /* Reset "shadow RAM uploaded" flag. */
1402
1403 *pRPS++ = RPS_UPLOAD | RPS_DEBI;
1404 /* Invoke shadow RAM upload. */
1405
1406 *pRPS++ = RPS_PAUSE | RPS_DEBI;
1407 /* Wait for shadow upload to finish. */
1408
1409 /* Delay at least 10 microseconds for analog input settling.
1410 * Instead of padding with NOPs, we use RPS_JUMP instructions
1411 * here; this allows us to produce a longer delay than is
1412 * possible with NOPs because each RPS_JUMP flushes the RPS'
1413 * instruction prefetch pipeline.
1414 */
11e865c1
GP		 1415 JmpAdrs =
1416 (uint32_t) devpriv->RPSBuf.PhysicalBase +
1417 (uint32_t) ((unsigned long)pRPS -
1418 (unsigned long)devpriv->RPSBuf.LogicalBase);
1419 for (i = 0; i < (10 * RPSCLK_PER_US / 2); i++) {
b6c77757
BP		 1420 JmpAdrs += 8; /* Repeat to implement time delay: */
1421 *pRPS++ = RPS_JUMP; /* Jump to next RPS instruction. */
11e865c1
GP		 1422 *pRPS++ = JmpAdrs;
1423 }
1424
1425 if (cmd != NULL && cmd->convert_src != TRIG_NOW) {
1426 DEBUG("ResetADC: convert pause inserted\n");
b6c77757 1427 /* Wait for Start trigger. */
11e865c1
GP		 1428 *pRPS++ = RPS_PAUSE | RPS_SIGADC;
1429 *pRPS++ = RPS_CLRSIGNAL | RPS_SIGADC;
1430 }
b6c77757
BP		 1431 /* Start ADC by pulsing GPIO1. */
1432 *pRPS++ = RPS_LDREG | (P_GPIO >> 2); /* Begin ADC Start pulse. */
11e865c1
GP		 1433 *pRPS++ = GPIO_BASE | GPIO1_LO;
1434 *pRPS++ = RPS_NOP;
b6c77757
BP		 1435 /* VERSION 2.03 CHANGE: STRETCH OUT ADC START PULSE. */
1436 *pRPS++ = RPS_LDREG | (P_GPIO >> 2); /* End ADC Start pulse. */
11e865c1
GP		 1437 *pRPS++ = GPIO_BASE | GPIO1_HI;
1438
b6c77757
BP		 1439 /* Wait for ADC to complete (GPIO2 is asserted high when ADC not
1440 * busy) and for data from previous conversion to shift into FB
1441 * BUFFER 1 register.
1442 */
1443 *pRPS++ = RPS_PAUSE | RPS_GPIO2; /* Wait for ADC done. */
11e865c1 1444
b6c77757 1445 /* Transfer ADC data from FB BUFFER 1 register to DMA buffer. */
11e865c1
GP		 1446 *pRPS++ = RPS_STREG | (BUGFIX_STREG(P_FB_BUFFER1) >> 2);
1447 *pRPS++ =
1448 (uint32_t) devpriv->ANABuf.PhysicalBase +
1449 (devpriv->AdcItems << 2);
1450
b6c77757
BP		 1451 /* If this slot's EndOfPollList flag is set, all channels have */
1452 /* now been processed. */
11e865c1 1453 if (*ppl++ & EOPL) {
b6c77757
BP		 1454 devpriv->AdcItems++; /* Adjust poll list item count. */
1455 break; /* Exit poll list processing loop. */
11e865c1
GP		 1456 }
1457 }
1458 DEBUG("ResetADC: ADC items %d \n", devpriv->AdcItems);
1459
b6c77757
BP		 1460 /* VERSION 2.01 CHANGE: DELAY CHANGED FROM 250NS to 2US. Allow the
1461 * ADC to stabilize for 2 microseconds before starting the final
1462 * (dummy) conversion. This delay is necessary to allow sufficient
1463 * time between last conversion finished and the start of the dummy
1464 * conversion. Without this delay, the last conversion's data value
1465 * is sometimes set to the previous conversion's data value.
1466 */
11e865c1
GP		 1467 for (n = 0; n < (2 * RPSCLK_PER_US); n++)
1468 *pRPS++ = RPS_NOP;
1469
b6c77757
BP		 1470 /* Start a dummy conversion to cause the data from the last
1471 * conversion of interest to be shifted in.
1472 */
1473 *pRPS++ = RPS_LDREG | (P_GPIO >> 2); /* Begin ADC Start pulse. */
11e865c1
GP		 1474 *pRPS++ = GPIO_BASE | GPIO1_LO;
1475 *pRPS++ = RPS_NOP;
b6c77757
BP		 1476 /* VERSION 2.03 CHANGE: STRETCH OUT ADC START PULSE. */
1477 *pRPS++ = RPS_LDREG | (P_GPIO >> 2); /* End ADC Start pulse. */
11e865c1
GP		 1478 *pRPS++ = GPIO_BASE | GPIO1_HI;
1479
b6c77757
BP		 1480 /* Wait for the data from the last conversion of interest to arrive
1481 * in FB BUFFER 1 register.
1482 */
1483 *pRPS++ = RPS_PAUSE | RPS_GPIO2; /* Wait for ADC done. */
11e865c1 1484
b6c77757
BP		 1485 /* Transfer final ADC data from FB BUFFER 1 register to DMA buffer. */
1486 *pRPS++ = RPS_STREG | (BUGFIX_STREG(P_FB_BUFFER1) >> 2); /* */
11e865c1
GP		 1487 *pRPS++ =
1488 (uint32_t) devpriv->ANABuf.PhysicalBase +
1489 (devpriv->AdcItems << 2);
1490
b6c77757
BP		 1491 /* Indicate ADC scan loop is finished. */
1492 /* *pRPS++= RPS_CLRSIGNAL | RPS_SIGADC ; // Signal ReadADC() that scan is done. */
11e865c1 1493
b6c77757 1494 /* invoke interrupt */
11e865c1
GP		 1495 if (devpriv->ai_cmd_running == 1) {
1496 DEBUG("ResetADC: insert irq in ADC RPS task\n");
1497 *pRPS++ = RPS_IRQ;
1498 }
b6c77757
BP		 1499 /* Restart RPS program at its beginning. */
1500 *pRPS++ = RPS_JUMP; /* Branch to start of RPS program. */
11e865c1
GP		 1501 *pRPS++ = (uint32_t) devpriv->RPSBuf.PhysicalBase;
1502
b6c77757 1503 /* End of RPS program build */
11e865c1
GP		 1504}
1505
1506/* TO COMPLETE, IF NECESSARY */
e473e912
BP		 1507static int s626_ai_insn_config(comedi_device *dev, comedi_subdevice *s,
1508 comedi_insn *insn, lsampl_t *data)
11e865c1
GP		 1509{
1510
1511 return -EINVAL;
1512}
1513
1514/* static int s626_ai_rinsn(comedi_device *dev,comedi_subdevice *s,comedi_insn *insn,lsampl_t *data) */
1515/* { */
1516/* register uint8_t i; */
1517/* register int32_t *readaddr; */
1518
1519/* DEBUG("as626_ai_rinsn: ai_rinsn enter \n"); */
1520
b6c77757 1521/* Trigger ADC scan loop start by setting RPS Signal 0. */
11e865c1
GP		 1522/* MC_ENABLE( P_MC2, MC2_ADC_RPS ); */
1523
b6c77757 1524/* Wait until ADC scan loop is finished (RPS Signal 0 reset). */
11e865c1
GP		 1525/* while ( MC_TEST( P_MC2, MC2_ADC_RPS ) ); */
1526
b6c77757
BP		 1527/* Init ptr to DMA buffer that holds new ADC data. We skip the
1528 * first uint16_t in the buffer because it contains junk data from
1529 * the final ADC of the previous poll list scan.
1530 */
11e865c1
GP		 1531/* readaddr = (uint32_t *)devpriv->ANABuf.LogicalBase + 1; */
1532
b6c77757 1533/* Convert ADC data to 16-bit integer values and copy to application buffer. */
11e865c1
GP		 1534/* for ( i = 0; i < devpriv->AdcItems; i++ ) { */
1535/* *data = s626_ai_reg_to_uint( *readaddr++ ); */
1536/* DEBUG("s626_ai_rinsn: data %d \n",*data); */
1537/* data++; */
1538/* } */
1539
1540/* DEBUG("s626_ai_rinsn: ai_rinsn escape \n"); */
1541/* return i; */
1542/* } */
1543
e473e912
BP		 1544static int s626_ai_insn_read(comedi_device *dev, comedi_subdevice *s,
1545 comedi_insn *insn, lsampl_t *data)
11e865c1
GP		 1546{
1547 uint16_t chan = CR_CHAN(insn->chanspec);
1548 uint16_t range = CR_RANGE(insn->chanspec);
1549 uint16_t AdcSpec = 0;
1550 uint32_t GpioImage;
1551 int n;
1552
b6c77757
BP		 1553 /* interrupt call test */
1554/* writel(IRQ_GPIO3,devpriv->base_addr+P_PSR); */
1555 /* Writing a logical 1 into any of the RPS_PSR bits causes the
1556 * corresponding interrupt to be generated if enabled
1557 */
11e865c1
GP		 1558
1559 DEBUG("s626_ai_insn_read: entering\n");
1560
b6c77757
BP		 1561 /* Convert application's ADC specification into form
1562 * appropriate for register programming.
1563 */
11e865c1
GP		 1564 if (range == 0)
1565 AdcSpec = (chan << 8) | (GSEL_BIPOLAR5V);
1566 else
1567 AdcSpec = (chan << 8) | (GSEL_BIPOLAR10V);
1568
b6c77757
BP		 1569 /* Switch ADC analog gain. */
1570 DEBIwrite(dev, LP_GSEL, AdcSpec); /* Set gain. */
11e865c1 1571
b6c77757
BP		 1572 /* Select ADC analog input channel. */
1573 DEBIwrite(dev, LP_ISEL, AdcSpec); /* Select channel. */
11e865c1
GP		 1574
1575 for (n = 0; n < insn->n; n++) {
1576
b6c77757 1577 /* Delay 10 microseconds for analog input settling. */
11e865c1
GP		 1578 comedi_udelay(10);
1579
b6c77757 1580 /* Start ADC by pulsing GPIO1 low. */
11e865c1 1581 GpioImage = RR7146(P_GPIO);
b6c77757 1582 /* Assert ADC Start command */
11e865c1 1583 WR7146(P_GPIO, GpioImage & ~GPIO1_HI);
b6c77757 1584 /* and stretch it out. */
11e865c1
GP		 1585 WR7146(P_GPIO, GpioImage & ~GPIO1_HI);
1586 WR7146(P_GPIO, GpioImage & ~GPIO1_HI);
b6c77757 1587 /* Negate ADC Start command. */
11e865c1
GP		 1588 WR7146(P_GPIO, GpioImage | GPIO1_HI);
1589
b6c77757
BP		 1590 /* Wait for ADC to complete (GPIO2 is asserted high when */
1591 /* ADC not busy) and for data from previous conversion to */
1592 /* shift into FB BUFFER 1 register. */
11e865c1 1593
b6c77757 1594 /* Wait for ADC done. */
11e865c1
GP		 1595 while (!(RR7146(P_PSR) & PSR_GPIO2)) ;
1596
b6c77757 1597 /* Fetch ADC data. */
11e865c1
GP		 1598 if (n != 0)
1599 data[n - 1] = s626_ai_reg_to_uint(RR7146(P_FB_BUFFER1));
1600
b6c77757
BP		 1601 /* Allow the ADC to stabilize for 4 microseconds before
1602 * starting the next (final) conversion. This delay is
1603 * necessary to allow sufficient time between last
1604 * conversion finished and the start of the next
1605 * conversion. Without this delay, the last conversion's
1606 * data value is sometimes set to the previous
1607 * conversion's data value.
1608 */
11e865c1
GP		 1609 comedi_udelay(4);
1610 }
1611
b6c77757
BP		 1612 /* Start a dummy conversion to cause the data from the
1613 * previous conversion to be shifted in. */
11e865c1
GP		 1614 GpioImage = RR7146(P_GPIO);
1615
b6c77757 1616 /* Assert ADC Start command */
11e865c1 1617 WR7146(P_GPIO, GpioImage & ~GPIO1_HI);
b6c77757 1618 /* and stretch it out. */
11e865c1
GP		 1619 WR7146(P_GPIO, GpioImage & ~GPIO1_HI);
1620 WR7146(P_GPIO, GpioImage & ~GPIO1_HI);
b6c77757 1621 /* Negate ADC Start command. */
11e865c1
GP		 1622 WR7146(P_GPIO, GpioImage | GPIO1_HI);
1623
b6c77757 1624 /* Wait for the data to arrive in FB BUFFER 1 register. */
11e865c1 1625
b6c77757 1626 /* Wait for ADC done. */
11e865c1
GP		 1627 while (!(RR7146(P_PSR) & PSR_GPIO2)) ;
1628
b6c77757 1629 /* Fetch ADC data from audio interface's input shift register. */
11e865c1 1630
b6c77757 1631 /* Fetch ADC data. */
11e865c1
GP		 1632 if (n != 0)
1633 data[n - 1] = s626_ai_reg_to_uint(RR7146(P_FB_BUFFER1));
1634
1635 DEBUG("s626_ai_insn_read: samples %d, data %d\n", n, data[n - 1]);
1636
1637 return n;
1638}
1639
e473e912 1640static int s626_ai_load_polllist(uint8_t *ppl, comedi_cmd *cmd)
11e865c1
GP		 1641{
1642
1643 int n;
1644
1645 for (n = 0; n < cmd->chanlist_len; n++) {
1646 if (CR_RANGE((cmd->chanlist)[n]) == 0)
1647 ppl[n] = (CR_CHAN((cmd->chanlist)[n])) | (RANGE_5V);
1648 else
1649 ppl[n] = (CR_CHAN((cmd->chanlist)[n])) | (RANGE_10V);
1650 }
1651 ppl[n - 1] |= EOPL;
1652
1653 return n;
1654}
1655
e473e912 1656static int s626_ai_inttrig(comedi_device *dev, comedi_subdevice *s,
11e865c1
GP		 1657 unsigned int trignum)
1658{
1659 if (trignum != 0)
1660 return -EINVAL;
1661
1662 DEBUG("s626_ai_inttrig: trigger adc start...");
1663
b6c77757 1664 /* Start executing the RPS program. */
11e865c1
GP		 1665 MC_ENABLE(P_MC1, MC1_ERPS1);
1666
1667 s->async->inttrig = NULL;
1668
1669 DEBUG(" done\n");
1670
1671 return 1;
1672}
1673
1674/* TO COMPLETE */
e473e912 1675static int s626_ai_cmd(comedi_device *dev, comedi_subdevice *s)
11e865c1
GP		 1676{
1677
1678 uint8_t ppl[16];
1679 comedi_cmd *cmd = &s->async->cmd;
1680 enc_private *k;
1681 int tick;
1682
1683 DEBUG("s626_ai_cmd: entering command function\n");
1684
1685 if (devpriv->ai_cmd_running) {
1686 printk("s626_ai_cmd: Another ai_cmd is running %d\n",
1687 dev->minor);
1688 return -EBUSY;
1689 }
b6c77757 1690 /* disable interrupt */
11e865c1
GP		 1691 writel(0, devpriv->base_addr + P_IER);
1692
b6c77757 1693 /* clear interrupt request */
11e865c1
GP		 1694 writel(IRQ_RPS1 | IRQ_GPIO3, devpriv->base_addr + P_ISR);
1695
b6c77757 1696 /* clear any pending interrupt */
11e865c1 1697 s626_dio_clear_irq(dev);
b6c77757 1698 /* s626_enc_clear_irq(dev); */
11e865c1 1699
b6c77757 1700 /* reset ai_cmd_running flag */
11e865c1
GP		 1701 devpriv->ai_cmd_running = 0;
1702
b6c77757 1703 /* test if cmd is valid */
11e865c1
GP		 1704 if (cmd == NULL) {
1705 DEBUG("s626_ai_cmd: NULL command\n");
1706 return -EINVAL;
1707 } else {
1708 DEBUG("s626_ai_cmd: command recieved!!!\n");
1709 }
1710
1711 if (dev->irq == 0) {
1712 comedi_error(dev,
1713 "s626_ai_cmd: cannot run command without an irq");
1714 return -EIO;
1715 }
1716
1717 s626_ai_load_polllist(ppl, cmd);
1718 devpriv->ai_cmd_running = 1;
1719 devpriv->ai_convert_count = 0;
1720
1721 switch (cmd->scan_begin_src) {
1722 case TRIG_FOLLOW:
1723 break;
1724 case TRIG_TIMER:
b6c77757 1725 /* set a conter to generate adc trigger at scan_begin_arg interval */
11e865c1
GP		 1726 k = &encpriv[5];
1727 tick = s626_ns_to_timer((int *)&cmd->scan_begin_arg,
1728 cmd->flags & TRIG_ROUND_MASK);
1729
b6c77757 1730 /* load timer value and enable interrupt */
11e865c1
GP		 1731 s626_timer_load(dev, k, tick);
1732 k->SetEnable(dev, k, CLKENAB_ALWAYS);
1733
1734 DEBUG("s626_ai_cmd: scan trigger timer is set with value %d\n",
1735 tick);
1736
1737 break;
1738 case TRIG_EXT:
b6c77757 1739 /* set the digital line and interrupt for scan trigger */
11e865c1
GP		 1740 if (cmd->start_src != TRIG_EXT)
1741 s626_dio_set_irq(dev, cmd->scan_begin_arg);
1742
1743 DEBUG("s626_ai_cmd: External scan trigger is set!!!\n");
1744
1745 break;
1746 }
1747
1748 switch (cmd->convert_src) {
1749 case TRIG_NOW:
1750 break;
1751 case TRIG_TIMER:
b6c77757 1752 /* set a conter to generate adc trigger at convert_arg interval */
11e865c1
GP		 1753 k = &encpriv[4];
1754 tick = s626_ns_to_timer((int *)&cmd->convert_arg,
1755 cmd->flags & TRIG_ROUND_MASK);
1756
b6c77757 1757 /* load timer value and enable interrupt */
11e865c1
GP		 1758 s626_timer_load(dev, k, tick);
1759 k->SetEnable(dev, k, CLKENAB_INDEX);
1760
1761 DEBUG("s626_ai_cmd: convert trigger timer is set with value %d\n", tick);
1762 break;
1763 case TRIG_EXT:
b6c77757 1764 /* set the digital line and interrupt for convert trigger */
11e865c1
GP		 1765 if (cmd->scan_begin_src != TRIG_EXT
1766 && cmd->start_src == TRIG_EXT)
1767 s626_dio_set_irq(dev, cmd->convert_arg);
1768
1769 DEBUG("s626_ai_cmd: External convert trigger is set!!!\n");
1770
1771 break;
1772 }
1773
1774 switch (cmd->stop_src) {
1775 case TRIG_COUNT:
b6c77757 1776 /* data arrives as one packet */
11e865c1
GP		 1777 devpriv->ai_sample_count = cmd->stop_arg;
1778 devpriv->ai_continous = 0;
1779 break;
1780 case TRIG_NONE:
b6c77757 1781 /* continous aquisition */
11e865c1
GP		 1782 devpriv->ai_continous = 1;
1783 devpriv->ai_sample_count = 0;
1784 break;
1785 }
1786
1787 ResetADC(dev, ppl);
1788
1789 switch (cmd->start_src) {
1790 case TRIG_NOW:
b6c77757
BP		 1791 /* Trigger ADC scan loop start by setting RPS Signal 0. */
1792 /* MC_ENABLE( P_MC2, MC2_ADC_RPS ); */
11e865c1 1793
b6c77757 1794 /* Start executing the RPS program. */
11e865c1
GP		 1795 MC_ENABLE(P_MC1, MC1_ERPS1);
1796
1797 DEBUG("s626_ai_cmd: ADC triggered\n");
1798 s->async->inttrig = NULL;
1799 break;
1800 case TRIG_EXT:
b6c77757 1801 /* configure DIO channel for acquisition trigger */
11e865c1
GP		 1802 s626_dio_set_irq(dev, cmd->start_arg);
1803
1804 DEBUG("s626_ai_cmd: External start trigger is set!!!\n");
1805
1806 s->async->inttrig = NULL;
1807 break;
1808 case TRIG_INT:
1809 s->async->inttrig = s626_ai_inttrig;
1810 break;
1811 }
1812
b6c77757 1813 /* enable interrupt */
11e865c1
GP		 1814 writel(IRQ_GPIO3 | IRQ_RPS1, devpriv->base_addr + P_IER);
1815
1816 DEBUG("s626_ai_cmd: command function terminated\n");
1817
1818 return 0;
1819}
1820
e473e912
BP		 1821static int s626_ai_cmdtest(comedi_device *dev, comedi_subdevice *s,
1822 comedi_cmd *cmd)
11e865c1
GP		 1823{
1824 int err = 0;
1825 int tmp;
1826
1827 /* cmdtest tests a particular command to see if it is valid. Using
1828 * the cmdtest ioctl, a user can create a valid cmd and then have it
1829 * executes by the cmd ioctl.
1830 *
1831 * cmdtest returns 1,2,3,4 or 0, depending on which tests the
1832 * command passes. */
1833
1834 /* step 1: make sure trigger sources are trivially valid */
1835
1836 tmp = cmd->start_src;
1837 cmd->start_src &= TRIG_NOW | TRIG_INT | TRIG_EXT;
1838 if (!cmd->start_src || tmp != cmd->start_src)
1839 err++;
1840
1841 tmp = cmd->scan_begin_src;
1842 cmd->scan_begin_src &= TRIG_TIMER | TRIG_EXT | TRIG_FOLLOW;
1843 if (!cmd->scan_begin_src || tmp != cmd->scan_begin_src)
1844 err++;
1845
1846 tmp = cmd->convert_src;
1847 cmd->convert_src &= TRIG_TIMER | TRIG_EXT | TRIG_NOW;
1848 if (!cmd->convert_src || tmp != cmd->convert_src)
1849 err++;
1850
1851 tmp = cmd->scan_end_src;
1852 cmd->scan_end_src &= TRIG_COUNT;
1853 if (!cmd->scan_end_src || tmp != cmd->scan_end_src)
1854 err++;
1855
1856 tmp = cmd->stop_src;
1857 cmd->stop_src &= TRIG_COUNT | TRIG_NONE;
1858 if (!cmd->stop_src || tmp != cmd->stop_src)
1859 err++;
1860
1861 if (err)
1862 return 1;
1863
1864 /* step 2: make sure trigger sources are unique and mutually
1865 compatible */
1866
1867 /* note that mutual compatiblity is not an issue here */
1868 if (cmd->scan_begin_src != TRIG_TIMER &&
1869 cmd->scan_begin_src != TRIG_EXT
1870 && cmd->scan_begin_src != TRIG_FOLLOW)
1871 err++;
1872 if (cmd->convert_src != TRIG_TIMER &&
1873 cmd->convert_src != TRIG_EXT && cmd->convert_src != TRIG_NOW)
1874 err++;
1875 if (cmd->stop_src != TRIG_COUNT && cmd->stop_src != TRIG_NONE)
1876 err++;
1877
1878 if (err)
1879 return 2;
1880
1881 /* step 3: make sure arguments are trivially compatible */
1882
1883 if (cmd->start_src != TRIG_EXT && cmd->start_arg != 0) {
1884 cmd->start_arg = 0;
1885 err++;
1886 }
1887
1888 if (cmd->start_src == TRIG_EXT && cmd->start_arg < 0) {
1889 cmd->start_arg = 0;
1890 err++;
1891 }
1892
1893 if (cmd->start_src == TRIG_EXT && cmd->start_arg > 39) {
1894 cmd->start_arg = 39;
1895 err++;
1896 }
1897
1898 if (cmd->scan_begin_src == TRIG_EXT && cmd->scan_begin_arg < 0) {
1899 cmd->scan_begin_arg = 0;
1900 err++;
1901 }
1902
1903 if (cmd->scan_begin_src == TRIG_EXT && cmd->scan_begin_arg > 39) {
1904 cmd->scan_begin_arg = 39;
1905 err++;
1906 }
1907
1908 if (cmd->convert_src == TRIG_EXT && cmd->convert_arg < 0) {
1909 cmd->convert_arg = 0;
1910 err++;
1911 }
1912
1913 if (cmd->convert_src == TRIG_EXT && cmd->convert_arg > 39) {
1914 cmd->convert_arg = 39;
1915 err++;
1916 }
1917#define MAX_SPEED 200000 /* in nanoseconds */
1918#define MIN_SPEED 2000000000 /* in nanoseconds */
1919
1920 if (cmd->scan_begin_src == TRIG_TIMER) {
1921 if (cmd->scan_begin_arg < MAX_SPEED) {
1922 cmd->scan_begin_arg = MAX_SPEED;
1923 err++;
1924 }
1925 if (cmd->scan_begin_arg > MIN_SPEED) {
1926 cmd->scan_begin_arg = MIN_SPEED;
1927 err++;
1928 }
1929 } else {
1930 /* external trigger */
1931 /* should be level/edge, hi/lo specification here */
1932 /* should specify multiple external triggers */
1933/* if(cmd->scan_begin_arg>9){ */
1934/* cmd->scan_begin_arg=9; */
1935/* err++; */
1936/* } */
1937 }
1938 if (cmd->convert_src == TRIG_TIMER) {
1939 if (cmd->convert_arg < MAX_SPEED) {
1940 cmd->convert_arg = MAX_SPEED;
1941 err++;
1942 }
1943 if (cmd->convert_arg > MIN_SPEED) {
1944 cmd->convert_arg = MIN_SPEED;
1945 err++;
1946 }
1947 } else {
1948 /* external trigger */
1949 /* see above */
1950/* if(cmd->convert_arg>9){ */
1951/* cmd->convert_arg=9; */
1952/* err++; */
1953/* } */
1954 }
1955
1956 if (cmd->scan_end_arg != cmd->chanlist_len) {
1957 cmd->scan_end_arg = cmd->chanlist_len;
1958 err++;
1959 }
1960 if (cmd->stop_src == TRIG_COUNT) {
1961 if (cmd->stop_arg > 0x00ffffff) {
1962 cmd->stop_arg = 0x00ffffff;
1963 err++;
1964 }
1965 } else {
1966 /* TRIG_NONE */
1967 if (cmd->stop_arg != 0) {
1968 cmd->stop_arg = 0;
1969 err++;
1970 }
1971 }
1972
1973 if (err)
1974 return 3;
1975
1976 /* step 4: fix up any arguments */
1977
1978 if (cmd->scan_begin_src == TRIG_TIMER) {
1979 tmp = cmd->scan_begin_arg;
1980 s626_ns_to_timer((int *)&cmd->scan_begin_arg,
1981 cmd->flags & TRIG_ROUND_MASK);
1982 if (tmp != cmd->scan_begin_arg)
1983 err++;
1984 }
1985 if (cmd->convert_src == TRIG_TIMER) {
1986 tmp = cmd->convert_arg;
1987 s626_ns_to_timer((int *)&cmd->convert_arg,
1988 cmd->flags & TRIG_ROUND_MASK);
1989 if (tmp != cmd->convert_arg)
1990 err++;
1991 if (cmd->scan_begin_src == TRIG_TIMER &&
1992 cmd->scan_begin_arg <
1993 cmd->convert_arg * cmd->scan_end_arg) {
1994 cmd->scan_begin_arg =
1995 cmd->convert_arg * cmd->scan_end_arg;
1996 err++;
1997 }
1998 }
1999
2000 if (err)
2001 return 4;
2002
2003 return 0;
2004}
2005
e473e912 2006static int s626_ai_cancel(comedi_device *dev, comedi_subdevice *s)
11e865c1 2007{
b6c77757 2008 /* Stop RPS program in case it is currently running. */
11e865c1
GP		 2009 MC_DISABLE(P_MC1, MC1_ERPS1);
2010
b6c77757 2011 /* disable master interrupt */
11e865c1
GP		 2012 writel(0, devpriv->base_addr + P_IER);
2013
2014 devpriv->ai_cmd_running = 0;
2015
2016 return 0;
2017}
2018
2019/* This function doesn't require a particular form, this is just what
2020 * happens to be used in some of the drivers. It should convert ns
2021 * nanoseconds to a counter value suitable for programming the device.
2022 * Also, it should adjust ns so that it cooresponds to the actual time
2023 * that the device will use. */
2024static int s626_ns_to_timer(int *nanosec, int round_mode)
2025{
2026 int divider, base;
2027
b6c77757 2028 base = 500; /* 2MHz internal clock */
11e865c1
GP		 2029
2030 switch (round_mode) {
2031 case TRIG_ROUND_NEAREST:
2032 default:
2033 divider = (*nanosec + base / 2) / base;
2034 break;
2035 case TRIG_ROUND_DOWN:
2036 divider = (*nanosec) / base;
2037 break;
2038 case TRIG_ROUND_UP:
2039 divider = (*nanosec + base - 1) / base;
2040 break;
2041 }
2042
2043 *nanosec = base * divider;
2044 return divider - 1;
2045}
2046
e473e912
BP		 2047static int s626_ao_winsn(comedi_device *dev, comedi_subdevice *s,
2048 comedi_insn *insn, lsampl_t *data)
11e865c1
GP		 2049{
2050
2051 int i;
2052 uint16_t chan = CR_CHAN(insn->chanspec);
2053 int16_t dacdata;
2054
2055 for (i = 0; i < insn->n; i++) {
2056 dacdata = (int16_t) data[i];
2057 devpriv->ao_readback[CR_CHAN(insn->chanspec)] = data[i];
2058 dacdata -= (0x1fff);
2059
2060 SetDAC(dev, chan, dacdata);
2061 }
2062
2063 return i;
2064}
2065
e473e912
BP		 2066static int s626_ao_rinsn(comedi_device *dev, comedi_subdevice *s,
2067 comedi_insn *insn, lsampl_t *data)
11e865c1
GP		 2068{
2069 int i;
2070
2071 for (i = 0; i < insn->n; i++) {
2072 data[i] = devpriv->ao_readback[CR_CHAN(insn->chanspec)];
2073 }
2074
2075 return i;
2076}
2077
b6c77757
BP		 2078/* *************** DIGITAL I/O FUNCTIONS ***************
2079 * All DIO functions address a group of DIO channels by means of
2080 * "group" argument. group may be 0, 1 or 2, which correspond to DIO
2081 * ports A, B and C, respectively.
2082 */
11e865c1 2083
e473e912 2084static void s626_dio_init(comedi_device *dev)
11e865c1
GP		 2085{
2086 uint16_t group;
2087 comedi_subdevice *s;
2088
b6c77757 2089 /* Prepare to treat writes to WRCapSel as capture disables. */
11e865c1
GP		 2090 DEBIwrite(dev, LP_MISC1, MISC1_NOEDCAP);
2091
b6c77757 2092 /* For each group of sixteen channels ... */
11e865c1
GP		 2093 for (group = 0; group < S626_DIO_BANKS; group++) {
2094 s = dev->subdevices + 2 + group;
b6c77757
BP		 2095 DEBIwrite(dev, diopriv->WRIntSel, 0); /* Disable all interrupts. */
2096 DEBIwrite(dev, diopriv->WRCapSel, 0xFFFF); /* Disable all event */
2097 /* captures. */
2098 DEBIwrite(dev, diopriv->WREdgSel, 0); /* Init all DIOs to */
2099 /* default edge */
2100 /* polarity. */
2101 DEBIwrite(dev, diopriv->WRDOut, 0); /* Program all outputs */
2102 /* to inactive state. */
11e865c1
GP		 2103 }
2104 DEBUG("s626_dio_init: DIO initialized \n");
2105}
2106
2107/* DIO devices are slightly special. Although it is possible to
2108 * implement the insn_read/insn_write interface, it is much more
2109 * useful to applications if you implement the insn_bits interface.
2110 * This allows packed reading/writing of the DIO channels. The comedi
2111 * core can convert between insn_bits and insn_read/write */
2112
e473e912
BP		 2113static int s626_dio_insn_bits(comedi_device *dev, comedi_subdevice *s,
2114 comedi_insn *insn, lsampl_t *data)
11e865c1
GP		 2115{
2116
2117 /* Length of data must be 2 (mask and new data, see below) */
2118 if (insn->n == 0) {
2119 return 0;
2120 }
2121 if (insn->n != 2) {
2122 printk("comedi%d: s626: s626_dio_insn_bits(): Invalid instruction length\n", dev->minor);
2123 return -EINVAL;
2124 }
2125
2126 /*
2127 * The insn data consists of a mask in data[0] and the new data in
2128 * data[1]. The mask defines which bits we are concerning about.
2129 * The new data must be anded with the mask. Each channel
2130 * corresponds to a bit.
2131 */
2132 if (data[0]) {
2133 /* Check if requested ports are configured for output */
2134 if ((s->io_bits & data[0]) != data[0])
2135 return -EIO;
2136
2137 s->state &= ~data[0];
2138 s->state |= data[0] & data[1];
2139
2140 /* Write out the new digital output lines */
2141
2142 DEBIwrite(dev, diopriv->WRDOut, s->state);
2143 }
2144 data[1] = DEBIread(dev, diopriv->RDDIn);
2145
2146 return 2;
2147}
2148
e473e912
BP		 2149static int s626_dio_insn_config(comedi_device *dev, comedi_subdevice *s,
2150 comedi_insn *insn, lsampl_t *data)
11e865c1
GP		 2151{
2152
2153 switch (data[0]) {
2154 case INSN_CONFIG_DIO_QUERY:
2155 data[1] =
2156 (s->io_bits & (1 << CR_CHAN(insn->
2157 chanspec))) ? COMEDI_OUTPUT :
2158 COMEDI_INPUT;
2159 return insn->n;
2160 break;
2161 case COMEDI_INPUT:
2162 s->io_bits &= ~(1 << CR_CHAN(insn->chanspec));
2163 break;
2164 case COMEDI_OUTPUT:
2165 s->io_bits |= 1 << CR_CHAN(insn->chanspec);
2166 break;
2167 default:
2168 return -EINVAL;
2169 break;
2170 }
2171 DEBIwrite(dev, diopriv->WRDOut, s->io_bits);
2172
2173 return 1;
2174}
2175
e473e912 2176static int s626_dio_set_irq(comedi_device *dev, unsigned int chan)
11e865c1
GP		 2177{
2178 unsigned int group;
2179 unsigned int bitmask;
2180 unsigned int status;
2181
b6c77757 2182 /* select dio bank */
11e865c1
GP		 2183 group = chan / 16;
2184 bitmask = 1 << (chan - (16 * group));
2185 DEBUG("s626_dio_set_irq: enable interrupt on dio channel %d group %d\n",
2186 chan - (16 * group), group);
2187
b6c77757 2188 /* set channel to capture positive edge */
11e865c1
GP		 2189 status = DEBIread(dev,
2190 ((dio_private *) (dev->subdevices + 2 +
2191 group)->private)->RDEdgSel);
2192 DEBIwrite(dev,
2193 ((dio_private *) (dev->subdevices + 2 +
2194 group)->private)->WREdgSel, bitmask | status);
2195
b6c77757 2196 /* enable interrupt on selected channel */
11e865c1
GP		 2197 status = DEBIread(dev,
2198 ((dio_private *) (dev->subdevices + 2 +
2199 group)->private)->RDIntSel);
2200 DEBIwrite(dev,
2201 ((dio_private *) (dev->subdevices + 2 +
2202 group)->private)->WRIntSel, bitmask | status);
2203
b6c77757 2204 /* enable edge capture write command */
11e865c1
GP		 2205 DEBIwrite(dev, LP_MISC1, MISC1_EDCAP);
2206
b6c77757 2207 /* enable edge capture on selected channel */
11e865c1
GP		 2208 status = DEBIread(dev,
2209 ((dio_private *) (dev->subdevices + 2 +
2210 group)->private)->RDCapSel);
2211 DEBIwrite(dev,
2212 ((dio_private *) (dev->subdevices + 2 +
2213 group)->private)->WRCapSel, bitmask | status);
2214
2215 return 0;
2216}
2217
e473e912 2218static int s626_dio_reset_irq(comedi_device *dev, unsigned int group,
11e865c1
GP		 2219 unsigned int mask)
2220{
2221 DEBUG("s626_dio_reset_irq: disable interrupt on dio channel %d group %d\n", mask, group);
2222
b6c77757 2223 /* disable edge capture write command */
11e865c1
GP		 2224 DEBIwrite(dev, LP_MISC1, MISC1_NOEDCAP);
2225
b6c77757 2226 /* enable edge capture on selected channel */
11e865c1
GP		 2227 DEBIwrite(dev,
2228 ((dio_private *) (dev->subdevices + 2 +
2229 group)->private)->WRCapSel, mask);
2230
2231 return 0;
2232}
2233
e473e912 2234static int s626_dio_clear_irq(comedi_device *dev)
11e865c1
GP		 2235{
2236 unsigned int group;
2237
b6c77757 2238 /* disable edge capture write command */
11e865c1
GP		 2239 DEBIwrite(dev, LP_MISC1, MISC1_NOEDCAP);
2240
2241 for (group = 0; group < S626_DIO_BANKS; group++) {
b6c77757 2242 /* clear pending events and interrupt */
11e865c1
GP		 2243 DEBIwrite(dev,
2244 ((dio_private *) (dev->subdevices + 2 +
2245 group)->private)->WRCapSel, 0xffff);
2246 }
2247
2248 return 0;
2249}
2250
2251/* Now this function initializes the value of the counter (data[0])
2252 and set the subdevice. To complete with trigger and interrupt
2253 configuration */
e473e912
BP		 2254static int s626_enc_insn_config(comedi_device *dev, comedi_subdevice *s,
2255 comedi_insn *insn, lsampl_t *data)
11e865c1 2256{
b6c77757
BP		 2257 uint16_t Setup = (LOADSRC_INDX << BF_LOADSRC) | /* Preload upon */
2258 /* index. */
2259 (INDXSRC_SOFT << BF_INDXSRC) | /* Disable hardware index. */
2260 (CLKSRC_COUNTER << BF_CLKSRC) | /* Operating mode is Counter. */
2261 (CLKPOL_POS << BF_CLKPOL) | /* Active high clock. */
2262 /* ( CNTDIR_UP << BF_CLKPOL ) | // Count direction is Down. */
2263 (CLKMULT_1X << BF_CLKMULT) | /* Clock multiplier is 1x. */
11e865c1
GP		 2264 (CLKENAB_INDEX << BF_CLKENAB);
2265 /* uint16_t DisableIntSrc=TRUE; */
b6c77757 2266 /* uint32_t Preloadvalue; //Counter initial value */
11e865c1
GP		 2267 uint16_t valueSrclatch = LATCHSRC_AB_READ;
2268 uint16_t enab = CLKENAB_ALWAYS;
2269 enc_private *k = &encpriv[CR_CHAN(insn->chanspec)];
2270
2271 DEBUG("s626_enc_insn_config: encoder config\n");
2272
b6c77757 2273 /* (data==NULL) ? (Preloadvalue=0) : (Preloadvalue=data[0]); */
11e865c1
GP		 2274
2275 k->SetMode(dev, k, Setup, TRUE);
2276 Preload(dev, k, *(insn->data));
2277 k->PulseIndex(dev, k);
2278 SetLatchSource(dev, k, valueSrclatch);
2279 k->SetEnable(dev, k, (uint16_t) (enab != 0));
2280
2281 return insn->n;
2282}
2283
e473e912
BP		 2284static int s626_enc_insn_read(comedi_device *dev, comedi_subdevice *s,
2285 comedi_insn *insn, lsampl_t *data)
11e865c1
GP		 2286{
2287
2288 int n;
2289 enc_private *k = &encpriv[CR_CHAN(insn->chanspec)];
2290
2291 DEBUG("s626_enc_insn_read: encoder read channel %d \n",
2292 CR_CHAN(insn->chanspec));
2293
2294 for (n = 0; n < insn->n; n++)
2295 data[n] = ReadLatch(dev, k);
2296
2297 DEBUG("s626_enc_insn_read: encoder sample %d\n", data[n]);
2298
2299 return n;
2300}
2301
e473e912
BP		 2302static int s626_enc_insn_write(comedi_device *dev, comedi_subdevice *s,
2303 comedi_insn *insn, lsampl_t *data)
11e865c1
GP		 2304{
2305
2306 enc_private *k = &encpriv[CR_CHAN(insn->chanspec)];
2307
2308 DEBUG("s626_enc_insn_write: encoder write channel %d \n",
2309 CR_CHAN(insn->chanspec));
2310
b6c77757 2311 /* Set the preload register */
11e865c1
GP		 2312 Preload(dev, k, data[0]);
2313
b6c77757
BP		 2314 /* Software index pulse forces the preload register to load */
2315 /* into the counter */
11e865c1
GP		 2316 k->SetLoadTrig(dev, k, 0);
2317 k->PulseIndex(dev, k);
2318 k->SetLoadTrig(dev, k, 2);
2319
2320 DEBUG("s626_enc_insn_write: End encoder write\n");
2321
2322 return 1;
2323}
2324
e473e912 2325static void s626_timer_load(comedi_device *dev, enc_private *k, int tick)
11e865c1 2326{
b6c77757
BP		 2327 uint16_t Setup = (LOADSRC_INDX << BF_LOADSRC) | /* Preload upon */
2328 /* index. */
2329 (INDXSRC_SOFT << BF_INDXSRC) | /* Disable hardware index. */
2330 (CLKSRC_TIMER << BF_CLKSRC) | /* Operating mode is Timer. */
2331 (CLKPOL_POS << BF_CLKPOL) | /* Active high clock. */
2332 (CNTDIR_DOWN << BF_CLKPOL) | /* Count direction is Down. */
2333 (CLKMULT_1X << BF_CLKMULT) | /* Clock multiplier is 1x. */
11e865c1
GP		 2334 (CLKENAB_INDEX << BF_CLKENAB);
2335 uint16_t valueSrclatch = LATCHSRC_A_INDXA;
b6c77757 2336 /* uint16_t enab=CLKENAB_ALWAYS; */
11e865c1
GP		 2337
2338 k->SetMode(dev, k, Setup, FALSE);
2339
b6c77757 2340 /* Set the preload register */
11e865c1
GP		 2341 Preload(dev, k, tick);
2342
b6c77757
BP		 2343 /* Software index pulse forces the preload register to load */
2344 /* into the counter */
11e865c1
GP		 2345 k->SetLoadTrig(dev, k, 0);
2346 k->PulseIndex(dev, k);
2347
b6c77757 2348 /* set reload on counter overflow */
11e865c1
GP		 2349 k->SetLoadTrig(dev, k, 1);
2350
b6c77757 2351 /* set interrupt on overflow */
11e865c1
GP		 2352 k->SetIntSrc(dev, k, INTSRC_OVER);
2353
2354 SetLatchSource(dev, k, valueSrclatch);
b6c77757 2355 /* k->SetEnable(dev,k,(uint16_t)(enab != 0)); */
11e865c1
GP		 2356}
2357
b6c77757 2358/* *********** DAC FUNCTIONS *********** */
11e865c1 2359
b6c77757 2360/* Slot 0 base settings. */
6a98d36e 2361#define VECT0 (XSD2 | RSD3 | SIB_A2)
b6c77757 2362/* Slot 0 always shifts in 0xFF and store it to FB_BUFFER2. */
11e865c1 2363
b6c77757 2364/* TrimDac LogicalChan-to-PhysicalChan mapping table. */
11e865c1
GP		 2365static uint8_t trimchan[] = { 10, 9, 8, 3, 2, 7, 6, 1, 0, 5, 4 };
2366
b6c77757 2367/* TrimDac LogicalChan-to-EepromAdrs mapping table. */
11e865c1
GP		 2368static uint8_t trimadrs[] =
2369 { 0x40, 0x41, 0x42, 0x50, 0x51, 0x52, 0x53, 0x60, 0x61, 0x62, 0x63 };
2370
e473e912 2371static void LoadTrimDACs(comedi_device *dev)
11e865c1
GP		 2372{
2373 register uint8_t i;
2374
b6c77757 2375 /* Copy TrimDac setpoint values from EEPROM to TrimDacs. */
11e865c1
GP		 2376 for (i = 0; i < (sizeof(trimchan) / sizeof(trimchan[0])); i++)
2377 WriteTrimDAC(dev, i, I2Cread(dev, trimadrs[i]));
2378}
2379
e473e912 2380static void WriteTrimDAC(comedi_device *dev, uint8_t LogicalChan,
11e865c1
GP		 2381 uint8_t DacData)
2382{
2383 uint32_t chan;
2384
b6c77757 2385 /* Save the new setpoint in case the application needs to read it back later. */
11e865c1
GP		 2386 devpriv->TrimSetpoint[LogicalChan] = (uint8_t) DacData;
2387
b6c77757 2388 /* Map logical channel number to physical channel number. */
11e865c1
GP		 2389 chan = (uint32_t) trimchan[LogicalChan];
2390
b6c77757
BP		 2391 /* Set up TSL2 records for TrimDac write operation. All slots shift
2392 * 0xFF in from pulled-up SD3 so that the end of the slot sequence
2393 * can be detected.
2394 */
2395
2396 SETVECT(2, XSD2 | XFIFO_1 | WS3);
2397 /* Slot 2: Send high uint8_t to target TrimDac. */
2398 SETVECT(3, XSD2 | XFIFO_0 | WS3);
2399 /* Slot 3: Send low uint8_t to target TrimDac. */
2400 SETVECT(4, XSD2 | XFIFO_3 | WS1);
2401 /* Slot 4: Send NOP high uint8_t to DAC0 to keep clock running. */
2402 SETVECT(5, XSD2 | XFIFO_2 | WS1 | EOS);
2403 /* Slot 5: Send NOP low uint8_t to DAC0. */
2404
2405 /* Construct and transmit target DAC's serial packet:
2406 * ( 0000 AAAA ), ( DDDD DDDD ),( 0x00 ),( 0x00 ) where A<3:0> is the
2407 * DAC channel's address, and D<7:0> is the DAC setpoint. Append a
2408 * WORD value (that writes a channel 0 NOP command to a non-existent
2409 * main DAC channel) that serves to keep the clock running after the
2410 * packet has been sent to the target DAC.
2411 */
11e865c1 2412
b6c77757
BP		 2413 /* Address the DAC channel within the trimdac device. */
2414 SendDAC(dev, ((uint32_t) chan << 8)
2415 | (uint32_t) DacData); /* Include DAC setpoint data. */
2416}
11e865c1 2417
b6c77757
BP		 2418/* ************** EEPROM ACCESS FUNCTIONS ************** */
2419/* Read uint8_t from EEPROM. */
11e865c1 2420
e473e912 2421static uint8_t I2Cread(comedi_device *dev, uint8_t addr)
11e865c1
GP		 2422{
2423 uint8_t rtnval;
2424
b6c77757
BP		 2425 /* Send EEPROM target address. */
2426 if (I2Chandshake(dev, I2C_B2(I2C_ATTRSTART, I2CW)
2427 /* Byte2 = I2C command: write to I2C EEPROM device. */
2428 | I2C_B1(I2C_ATTRSTOP, addr)
2429 /* Byte1 = EEPROM internal target address. */
2430 | I2C_B0(I2C_ATTRNOP, 0))) /* Byte0 = Not sent. */
11e865c1 2431 {
b6c77757 2432 /* Abort function and declare error if handshake failed. */
11e865c1
GP		 2433 DEBUG("I2Cread: error handshake I2Cread a\n");
2434 return 0;
2435 }
b6c77757
BP		 2436 /* Execute EEPROM read. */
2437 if (I2Chandshake(dev, I2C_B2(I2C_ATTRSTART, I2CR) /* Byte2 = I2C */
2438 /* command: read */
2439 /* from I2C EEPROM */
2440 /* device. */
2441 | I2C_B1(I2C_ATTRSTOP, 0) /* Byte1 receives */
2442 /* uint8_t from */
2443 /* EEPROM. */
2444 | I2C_B0(I2C_ATTRNOP, 0))) /* Byte0 = Not */
2445 /* sent. */
11e865c1 2446 {
b6c77757 2447 /* Abort function and declare error if handshake failed. */
11e865c1
GP		 2448 DEBUG("I2Cread: error handshake I2Cread b\n");
2449 return 0;
2450 }
b6c77757 2451 /* Return copy of EEPROM value. */
11e865c1
GP		 2452 rtnval = (uint8_t) (RR7146(P_I2CCTRL) >> 16);
2453 return rtnval;
2454}
2455
e473e912 2456static uint32_t I2Chandshake(comedi_device *dev, uint32_t val)
11e865c1 2457{
b6c77757 2458 /* Write I2C command to I2C Transfer Control shadow register. */
11e865c1
GP		 2459 WR7146(P_I2CCTRL, val);
2460
b6c77757
BP		 2461 /* Upload I2C shadow registers into working registers and wait for */
2462 /* upload confirmation. */
11e865c1
GP		 2463
2464 MC_ENABLE(P_MC2, MC2_UPLD_IIC);
2465 while (!MC_TEST(P_MC2, MC2_UPLD_IIC)) ;
2466
b6c77757 2467 /* Wait until I2C bus transfer is finished or an error occurs. */
11e865c1
GP		 2468 while ((RR7146(P_I2CCTRL) & (I2C_BUSY | I2C_ERR)) == I2C_BUSY) ;
2469
b6c77757 2470 /* Return non-zero if I2C error occured. */
11e865c1
GP		 2471 return RR7146(P_I2CCTRL) & I2C_ERR;
2472
2473}
2474
b6c77757 2475/* Private helper function: Write setpoint to an application DAC channel. */
11e865c1 2476
e473e912 2477static void SetDAC(comedi_device *dev, uint16_t chan, short dacdata)
11e865c1
GP		 2478{
2479 register uint16_t signmask;
2480 register uint32_t WSImage;
2481
b6c77757
BP		 2482 /* Adjust DAC data polarity and set up Polarity Control Register */
2483 /* image. */
11e865c1
GP		 2484 signmask = 1 << chan;
2485 if (dacdata < 0) {
2486 dacdata = -dacdata;
2487 devpriv->Dacpol |= signmask;
2488 } else
2489 devpriv->Dacpol &= ~signmask;
2490
b6c77757 2491 /* Limit DAC setpoint value to valid range. */
11e865c1
GP		 2492 if ((uint16_t) dacdata > 0x1FFF)
2493 dacdata = 0x1FFF;
2494
b6c77757
BP		 2495 /* Set up TSL2 records (aka "vectors") for DAC update. Vectors V2
2496 * and V3 transmit the setpoint to the target DAC. V4 and V5 send
2497 * data to a non-existent TrimDac channel just to keep the clock
2498 * running after sending data to the target DAC. This is necessary
2499 * to eliminate the clock glitch that would otherwise occur at the
2500 * end of the target DAC's serial data stream. When the sequence
2501 * restarts at V0 (after executing V5), the gate array automatically
2502 * disables gating for the DAC clock and all DAC chip selects.
2503 */
2504
2505 WSImage = (chan & 2) ? WS1 : WS2;
2506 /* Choose DAC chip select to be asserted. */
2507 SETVECT(2, XSD2 | XFIFO_1 | WSImage);
2508 /* Slot 2: Transmit high data byte to target DAC. */
2509 SETVECT(3, XSD2 | XFIFO_0 | WSImage);
2510 /* Slot 3: Transmit low data byte to target DAC. */
2511 SETVECT(4, XSD2 | XFIFO_3 | WS3);
2512 /* Slot 4: Transmit to non-existent TrimDac channel to keep clock */
2513 SETVECT(5, XSD2 | XFIFO_2 | WS3 | EOS);
2514 /* Slot 5: running after writing target DAC's low data byte. */
2515
2516 /* Construct and transmit target DAC's serial packet:
2517 * ( A10D DDDD ),( DDDD DDDD ),( 0x0F ),( 0x00 ) where A is chan<0>,
2518 * and D<12:0> is the DAC setpoint. Append a WORD value (that writes
2519 * to a non-existent TrimDac channel) that serves to keep the clock
2520 * running after the packet has been sent to the target DAC.
2521 */
2522 SendDAC(dev, 0x0F000000
2523 /* Continue clock after target DAC data (write to non-existent trimdac). */
2524 | 0x00004000
2525 /* Address the two main dual-DAC devices (TSL's chip select enables
2526 * target device). */
2527 | ((uint32_t) (chan & 1) << 15)
2528 /* Address the DAC channel within the device. */
2529 | (uint32_t) dacdata); /* Include DAC setpoint data. */
11e865c1
GP		 2530
2531}
2532
b6c77757
BP		 2533/* Private helper function: Transmit serial data to DAC via Audio
2534 * channel 2. Assumes: (1) TSL2 slot records initialized, and (2)
2535 * Dacpol contains valid target image.
2536 */
11e865c1 2537
e473e912 2538static void SendDAC(comedi_device *dev, uint32_t val)
11e865c1
GP		 2539{
2540
b6c77757 2541 /* START THE SERIAL CLOCK RUNNING ------------- */
11e865c1 2542
b6c77757
BP		 2543 /* Assert DAC polarity control and enable gating of DAC serial clock
2544 * and audio bit stream signals. At this point in time we must be
2545 * assured of being in time slot 0. If we are not in slot 0, the
2546 * serial clock and audio stream signals will be disabled; this is
2547 * because the following DEBIwrite statement (which enables signals
2548 * to be passed through the gate array) would execute before the
2549 * trailing edge of WS1/WS3 (which turns off the signals), thus
2550 * causing the signals to be inactive during the DAC write.
2551 */
11e865c1
GP		 2552 DEBIwrite(dev, LP_DACPOL, devpriv->Dacpol);
2553
b6c77757 2554 /* TRANSFER OUTPUT DWORD VALUE INTO A2'S OUTPUT FIFO ---------------- */
11e865c1 2555
b6c77757 2556 /* Copy DAC setpoint value to DAC's output DMA buffer. */
11e865c1 2557
b6c77757 2558 /* WR7146( (uint32_t)devpriv->pDacWBuf, val ); */
11e865c1
GP		 2559 *devpriv->pDacWBuf = val;
2560
b6c77757
BP		 2561 /* enab the output DMA transfer. This will cause the DMAC to copy
2562 * the DAC's data value to A2's output FIFO. The DMA transfer will
2563 * then immediately terminate because the protection address is
2564 * reached upon transfer of the first DWORD value.
2565 */
11e865c1
GP		 2566 MC_ENABLE(P_MC1, MC1_A2OUT);
2567
b6c77757 2568 /* While the DMA transfer is executing ... */
11e865c1 2569
b6c77757
BP		 2570 /* Reset Audio2 output FIFO's underflow flag (along with any other
2571 * FIFO underflow/overflow flags). When set, this flag will
2572 * indicate that we have emerged from slot 0.
2573 */
11e865c1
GP		 2574 WR7146(P_ISR, ISR_AFOU);
2575
b6c77757
BP		 2576 /* Wait for the DMA transfer to finish so that there will be data
2577 * available in the FIFO when time slot 1 tries to transfer a DWORD
2578 * from the FIFO to the output buffer register. We test for DMA
2579 * Done by polling the DMAC enable flag; this flag is automatically
2580 * cleared when the transfer has finished.
2581 */
11e865c1
GP		 2582 while ((RR7146(P_MC1) & MC1_A2OUT) != 0) ;
2583
b6c77757 2584 /* START THE OUTPUT STREAM TO THE TARGET DAC -------------------- */
11e865c1 2585
b6c77757
BP		 2586 /* FIFO data is now available, so we enable execution of time slots
2587 * 1 and higher by clearing the EOS flag in slot 0. Note that SD3
2588 * will be shifted in and stored in FB_BUFFER2 for end-of-slot-list
2589 * detection.
2590 */
11e865c1
GP		 2591 SETVECT(0, XSD2 | RSD3 | SIB_A2);
2592
b6c77757
BP		 2593 /* Wait for slot 1 to execute to ensure that the Packet will be
2594 * transmitted. This is detected by polling the Audio2 output FIFO
2595 * underflow flag, which will be set when slot 1 execution has
2596 * finished transferring the DAC's data DWORD from the output FIFO
2597 * to the output buffer register.
2598 */
11e865c1
GP		 2599 while ((RR7146(P_SSR) & SSR_AF2_OUT) == 0) ;
2600
b6c77757
BP		 2601 /* Set up to trap execution at slot 0 when the TSL sequencer cycles
2602 * back to slot 0 after executing the EOS in slot 5. Also,
2603 * simultaneously shift out and in the 0x00 that is ALWAYS the value
2604 * stored in the last byte to be shifted out of the FIFO's DWORD
2605 * buffer register.
2606 */
11e865c1
GP		 2607 SETVECT(0, XSD2 | XFIFO_2 | RSD2 | SIB_A2 | EOS);
2608
b6c77757
BP		 2609 /* WAIT FOR THE TRANSACTION TO FINISH ----------------------- */
2610
2611 /* Wait for the TSL to finish executing all time slots before
2612 * exiting this function. We must do this so that the next DAC
2613 * write doesn't start, thereby enabling clock/chip select signals:
2614 *
2615 * 1. Before the TSL sequence cycles back to slot 0, which disables
2616 * the clock/cs signal gating and traps slot // list execution.
2617 * we have not yet finished slot 5 then the clock/cs signals are
2618 * still gated and we have not finished transmitting the stream.
2619 *
2620 * 2. While slots 2-5 are executing due to a late slot 0 trap. In
2621 * this case, the slot sequence is currently repeating, but with
2622 * clock/cs signals disabled. We must wait for slot 0 to trap
2623 * execution before setting up the next DAC setpoint DMA transfer
2624 * and enabling the clock/cs signals. To detect the end of slot 5,
2625 * we test for the FB_BUFFER2 MSB contents to be equal to 0xFF. If
2626 * the TSL has not yet finished executing slot 5 ...
2627 */
11e865c1 2628 if ((RR7146(P_FB_BUFFER2) & 0xFF000000) != 0) {
b6c77757
BP		 2629 /* The trap was set on time and we are still executing somewhere
2630 * in slots 2-5, so we now wait for slot 0 to execute and trap
2631 * TSL execution. This is detected when FB_BUFFER2 MSB changes
2632 * from 0xFF to 0x00, which slot 0 causes to happen by shifting
2633 * out/in on SD2 the 0x00 that is always referenced by slot 5.
2634 */
2635 while ((RR7146(P_FB_BUFFER2) & 0xFF000000) != 0) ;
11e865c1 2636 }
b6c77757
BP		 2637 /* Either (1) we were too late setting the slot 0 trap; the TSL
2638 * sequencer restarted slot 0 before we could set the EOS trap flag,
2639 * or (2) we were not late and execution is now trapped at slot 0.
2640 * In either case, we must now change slot 0 so that it will store
2641 * value 0xFF (instead of 0x00) to FB_BUFFER2 next time it executes.
2642 * In order to do this, we reprogram slot 0 so that it will shift in
2643 * SD3, which is driven only by a pull-up resistor.
2644 */
11e865c1
GP		 2645 SETVECT(0, RSD3 | SIB_A2 | EOS);
2646
b6c77757
BP		 2647 /* Wait for slot 0 to execute, at which time the TSL is setup for
2648 * the next DAC write. This is detected when FB_BUFFER2 MSB changes
2649 * from 0x00 to 0xFF.
2650 */
11e865c1
GP		 2651 while ((RR7146(P_FB_BUFFER2) & 0xFF000000) == 0) ;
2652}
2653
e473e912 2654static void WriteMISC2(comedi_device *dev, uint16_t NewImage)
11e865c1 2655{
b6c77757
BP		 2656 DEBIwrite(dev, LP_MISC1, MISC1_WENABLE); /* enab writes to */
2657 /* MISC2 register. */
2658 DEBIwrite(dev, LP_WRMISC2, NewImage); /* Write new image to MISC2. */
2659 DEBIwrite(dev, LP_MISC1, MISC1_WDISABLE); /* Disable writes to MISC2. */
11e865c1
GP		 2660}
2661
b6c77757 2662/* Initialize the DEBI interface for all transfers. */
11e865c1 2663
e473e912 2664static uint16_t DEBIread(comedi_device *dev, uint16_t addr)
11e865c1
GP		 2665{
2666 uint16_t retval;
2667
b6c77757 2668 /* Set up DEBI control register value in shadow RAM. */
11e865c1
GP		 2669 WR7146(P_DEBICMD, DEBI_CMD_RDWORD | addr);
2670
b6c77757 2671 /* Execute the DEBI transfer. */
11e865c1
GP		 2672 DEBItransfer(dev);
2673
b6c77757 2674 /* Fetch target register value. */
11e865c1
GP		 2675 retval = (uint16_t) RR7146(P_DEBIAD);
2676
b6c77757 2677 /* Return register value. */
11e865c1
GP		 2678 return retval;
2679}
2680
b6c77757
BP		 2681/* Execute a DEBI transfer. This must be called from within a */
2682/* critical section. */
e473e912 2683static void DEBItransfer(comedi_device *dev)
11e865c1 2684{
b6c77757 2685 /* Initiate upload of shadow RAM to DEBI control register. */
11e865c1
GP		 2686 MC_ENABLE(P_MC2, MC2_UPLD_DEBI);
2687
b6c77757
BP		 2688 /* Wait for completion of upload from shadow RAM to DEBI control */
2689 /* register. */
11e865c1
GP		 2690 while (!MC_TEST(P_MC2, MC2_UPLD_DEBI)) ;
2691
b6c77757 2692 /* Wait until DEBI transfer is done. */
11e865c1
GP		 2693 while (RR7146(P_PSR) & PSR_DEBI_S) ;
2694}
2695
b6c77757 2696/* Write a value to a gate array register. */
e473e912 2697static void DEBIwrite(comedi_device *dev, uint16_t addr, uint16_t wdata)
11e865c1
GP		 2698{
2699
b6c77757 2700 /* Set up DEBI control register value in shadow RAM. */
11e865c1
GP		 2701 WR7146(P_DEBICMD, DEBI_CMD_WRWORD | addr);
2702 WR7146(P_DEBIAD, wdata);
2703
b6c77757 2704 /* Execute the DEBI transfer. */
11e865c1
GP		 2705 DEBItransfer(dev);
2706}
2707
b6c77757
BP		 2708/* Replace the specified bits in a gate array register. Imports: mask
2709 * specifies bits that are to be preserved, wdata is new value to be
2710 * or'd with the masked original.
2711 */
e473e912 2712static void DEBIreplace(comedi_device *dev, uint16_t addr, uint16_t mask,
11e865c1
GP		 2713 uint16_t wdata)
2714{
2715
b6c77757
BP		 2716 /* Copy target gate array register into P_DEBIAD register. */
2717 WR7146(P_DEBICMD, DEBI_CMD_RDWORD | addr);
2718 /* Set up DEBI control reg value in shadow RAM. */
2719 DEBItransfer(dev); /* Execute the DEBI Read transfer. */
11e865c1 2720
b6c77757
BP		 2721 /* Write back the modified image. */
2722 WR7146(P_DEBICMD, DEBI_CMD_WRWORD | addr);
2723 /* Set up DEBI control reg value in shadow RAM. */
11e865c1 2724
b6c77757
BP		 2725 WR7146(P_DEBIAD, wdata | ((uint16_t) RR7146(P_DEBIAD) & mask));
2726 /* Modify the register image. */
2727 DEBItransfer(dev); /* Execute the DEBI Write transfer. */
11e865c1
GP		 2728}
2729
e473e912 2730static void CloseDMAB(comedi_device *dev, DMABUF *pdma, size_t bsize)
11e865c1
GP		 2731{
2732 void *vbptr;
2733 dma_addr_t vpptr;
2734
2735 DEBUG("CloseDMAB: Entering S626DRV_CloseDMAB():\n");
2736 if (pdma == NULL)
2737 return;
b6c77757 2738 /* find the matching allocation from the board struct */
11e865c1
GP		 2739
2740 vbptr = pdma->LogicalBase;
2741 vpptr = pdma->PhysicalBase;
2742 if (vbptr) {
2743 pci_free_consistent(devpriv->pdev, bsize, vbptr, vpptr);
2744 pdma->LogicalBase = 0;
2745 pdma->PhysicalBase = 0;
2746
2747 DEBUG("CloseDMAB(): Logical=%p, bsize=%d, Physical=0x%x\n",
2748 vbptr, bsize, (uint32_t) vpptr);
2749 }
2750}
2751
b6c77757
BP		 2752/* ****** COUNTER FUNCTIONS ******* */
2753/* All counter functions address a specific counter by means of the
2754 * "Counter" argument, which is a logical counter number. The Counter
2755 * argument may have any of the following legal values: 0=0A, 1=1A,
2756 * 2=2A, 3=0B, 4=1B, 5=2B.
2757 */
11e865c1 2758
b6c77757 2759/* Forward declarations for functions that are common to both A and B counters: */
11e865c1 2760
b6c77757 2761/* ****** PRIVATE COUNTER FUNCTIONS ****** */
11e865c1 2762
b6c77757 2763/* Read a counter's output latch. */
11e865c1 2764
e473e912 2765static uint32_t ReadLatch(comedi_device *dev, enc_private *k)
11e865c1
GP		 2766{
2767 register uint32_t value;
b6c77757 2768 /* DEBUG FIXME DEBUG("ReadLatch: Read Latch enter\n"); */
11e865c1 2769
b6c77757 2770 /* Latch counts and fetch LSW of latched counts value. */
11e865c1
GP		 2771 value = (uint32_t) DEBIread(dev, k->MyLatchLsw);
2772
b6c77757 2773 /* Fetch MSW of latched counts and combine with LSW. */
11e865c1
GP		 2774 value |= ((uint32_t) DEBIread(dev, k->MyLatchLsw + 2) << 16);
2775
b6c77757 2776 /* DEBUG FIXME DEBUG("ReadLatch: Read Latch exit\n"); */
11e865c1 2777
b6c77757 2778 /* Return latched counts. */
11e865c1
GP		 2779 return value;
2780}
2781
b6c77757 2782/* Reset a counter's index and overflow event capture flags. */
11e865c1 2783
e473e912 2784static void ResetCapFlags_A(comedi_device *dev, enc_private *k)
11e865c1
GP		 2785{
2786 DEBIreplace(dev, k->MyCRB, (uint16_t) (~CRBMSK_INTCTRL),
2787 CRBMSK_INTRESETCMD | CRBMSK_INTRESET_A);
2788}
2789
e473e912 2790static void ResetCapFlags_B(comedi_device *dev, enc_private *k)
11e865c1
GP		 2791{
2792 DEBIreplace(dev, k->MyCRB, (uint16_t) (~CRBMSK_INTCTRL),
2793 CRBMSK_INTRESETCMD | CRBMSK_INTRESET_B);
2794}
2795
b6c77757
BP		 2796/* Return counter setup in a format (COUNTER_SETUP) that is consistent */
2797/* for both A and B counters. */
11e865c1 2798
e473e912 2799static uint16_t GetMode_A(comedi_device *dev, enc_private *k)
11e865c1
GP		 2800{
2801 register uint16_t cra;
2802 register uint16_t crb;
2803 register uint16_t setup;
2804
b6c77757 2805 /* Fetch CRA and CRB register images. */
11e865c1
GP		 2806 cra = DEBIread(dev, k->MyCRA);
2807 crb = DEBIread(dev, k->MyCRB);
2808
b6c77757
BP		 2809 /* Populate the standardized counter setup bit fields. Note: */
2810 /* IndexSrc is restricted to ENC_X or IndxPol. */
2811 setup = ((cra & STDMSK_LOADSRC) /* LoadSrc = LoadSrcA. */
2812 | ((crb << (STDBIT_LATCHSRC - CRBBIT_LATCHSRC)) & STDMSK_LATCHSRC) /* LatchSrc = LatchSrcA. */
2813 | ((cra << (STDBIT_INTSRC - CRABIT_INTSRC_A)) & STDMSK_INTSRC) /* IntSrc = IntSrcA. */
2814 | ((cra << (STDBIT_INDXSRC - (CRABIT_INDXSRC_A + 1))) & STDMSK_INDXSRC) /* IndxSrc = IndxSrcA<1>. */
2815 | ((cra >> (CRABIT_INDXPOL_A - STDBIT_INDXPOL)) & STDMSK_INDXPOL) /* IndxPol = IndxPolA. */
2816 | ((crb >> (CRBBIT_CLKENAB_A - STDBIT_CLKENAB)) & STDMSK_CLKENAB)); /* ClkEnab = ClkEnabA. */
2817
2818 /* Adjust mode-dependent parameters. */
2819 if (cra & (2 << CRABIT_CLKSRC_A)) /* If Timer mode (ClkSrcA<1> == 1): */
2820 setup |= ((CLKSRC_TIMER << STDBIT_CLKSRC) /* Indicate Timer mode. */
2821 | ((cra << (STDBIT_CLKPOL - CRABIT_CLKSRC_A)) & STDMSK_CLKPOL) /* Set ClkPol to indicate count direction (ClkSrcA<0>). */
2822 | (MULT_X1 << STDBIT_CLKMULT)); /* ClkMult must be 1x in Timer mode. */
2823
2824 else /* If Counter mode (ClkSrcA<1> == 0): */
2825 setup |= ((CLKSRC_COUNTER << STDBIT_CLKSRC) /* Indicate Counter mode. */
2826 | ((cra >> (CRABIT_CLKPOL_A - STDBIT_CLKPOL)) & STDMSK_CLKPOL) /* Pass through ClkPol. */
2827 | (((cra & CRAMSK_CLKMULT_A) == (MULT_X0 << CRABIT_CLKMULT_A)) ? /* Force ClkMult to 1x if not legal, else pass through. */
11e865c1
GP		 2828 (MULT_X1 << STDBIT_CLKMULT) :
2829 ((cra >> (CRABIT_CLKMULT_A -
2830 STDBIT_CLKMULT)) &
2831 STDMSK_CLKMULT)));
2832
b6c77757 2833 /* Return adjusted counter setup. */
11e865c1
GP		 2834 return setup;
2835}
2836
e473e912 2837static uint16_t GetMode_B(comedi_device *dev, enc_private *k)
11e865c1
GP		 2838{
2839 register uint16_t cra;
2840 register uint16_t crb;
2841 register uint16_t setup;
2842
b6c77757 2843 /* Fetch CRA and CRB register images. */
11e865c1
GP		 2844 cra = DEBIread(dev, k->MyCRA);
2845 crb = DEBIread(dev, k->MyCRB);
2846
b6c77757
BP		 2847 /* Populate the standardized counter setup bit fields. Note: */
2848 /* IndexSrc is restricted to ENC_X or IndxPol. */
2849 setup = (((crb << (STDBIT_INTSRC - CRBBIT_INTSRC_B)) & STDMSK_INTSRC) /* IntSrc = IntSrcB. */
2850 | ((crb << (STDBIT_LATCHSRC - CRBBIT_LATCHSRC)) & STDMSK_LATCHSRC) /* LatchSrc = LatchSrcB. */
2851 | ((crb << (STDBIT_LOADSRC - CRBBIT_LOADSRC_B)) & STDMSK_LOADSRC) /* LoadSrc = LoadSrcB. */
2852 | ((crb << (STDBIT_INDXPOL - CRBBIT_INDXPOL_B)) & STDMSK_INDXPOL) /* IndxPol = IndxPolB. */
2853 | ((crb >> (CRBBIT_CLKENAB_B - STDBIT_CLKENAB)) & STDMSK_CLKENAB) /* ClkEnab = ClkEnabB. */
2854 | ((cra >> ((CRABIT_INDXSRC_B + 1) - STDBIT_INDXSRC)) & STDMSK_INDXSRC)); /* IndxSrc = IndxSrcB<1>. */
2855
2856 /* Adjust mode-dependent parameters. */
2857 if ((crb & CRBMSK_CLKMULT_B) == (MULT_X0 << CRBBIT_CLKMULT_B)) /* If Extender mode (ClkMultB == MULT_X0): */
2858 setup |= ((CLKSRC_EXTENDER << STDBIT_CLKSRC) /* Indicate Extender mode. */
2859 | (MULT_X1 << STDBIT_CLKMULT) /* Indicate multiplier is 1x. */
2860 | ((cra >> (CRABIT_CLKSRC_B - STDBIT_CLKPOL)) & STDMSK_CLKPOL)); /* Set ClkPol equal to Timer count direction (ClkSrcB<0>). */
2861
2862 else if (cra & (2 << CRABIT_CLKSRC_B)) /* If Timer mode (ClkSrcB<1> == 1): */
2863 setup |= ((CLKSRC_TIMER << STDBIT_CLKSRC) /* Indicate Timer mode. */
2864 | (MULT_X1 << STDBIT_CLKMULT) /* Indicate multiplier is 1x. */
2865 | ((cra >> (CRABIT_CLKSRC_B - STDBIT_CLKPOL)) & STDMSK_CLKPOL)); /* Set ClkPol equal to Timer count direction (ClkSrcB<0>). */
2866
2867 else /* If Counter mode (ClkSrcB<1> == 0): */
2868 setup |= ((CLKSRC_COUNTER << STDBIT_CLKSRC) /* Indicate Timer mode. */
2869 | ((crb >> (CRBBIT_CLKMULT_B - STDBIT_CLKMULT)) & STDMSK_CLKMULT) /* Clock multiplier is passed through. */
2870 | ((crb << (STDBIT_CLKPOL - CRBBIT_CLKPOL_B)) & STDMSK_CLKPOL)); /* Clock polarity is passed through. */
2871
2872 /* Return adjusted counter setup. */
11e865c1
GP		 2873 return setup;
2874}
2875
b6c77757
BP		 2876/*
2877 * Set the operating mode for the specified counter. The setup
2878 * parameter is treated as a COUNTER_SETUP data type. The following
2879 * parameters are programmable (all other parms are ignored): ClkMult,
2880 * ClkPol, ClkEnab, IndexSrc, IndexPol, LoadSrc.
2881 */
11e865c1 2882
e473e912 2883static void SetMode_A(comedi_device *dev, enc_private *k, uint16_t Setup,
11e865c1
GP		 2884 uint16_t DisableIntSrc)
2885{
2886 register uint16_t cra;
2887 register uint16_t crb;
b6c77757 2888 register uint16_t setup = Setup; /* Cache the Standard Setup. */
11e865c1 2889
b6c77757
BP		 2890 /* Initialize CRA and CRB images. */
2891 cra = ((setup & CRAMSK_LOADSRC_A) /* Preload trigger is passed through. */
2892 | ((setup & STDMSK_INDXSRC) >> (STDBIT_INDXSRC - (CRABIT_INDXSRC_A + 1)))); /* IndexSrc is restricted to ENC_X or IndxPol. */
11e865c1 2893
b6c77757
BP		 2894 crb = (CRBMSK_INTRESETCMD | CRBMSK_INTRESET_A /* Reset any pending CounterA event captures. */
2895 | ((setup & STDMSK_CLKENAB) << (CRBBIT_CLKENAB_A - STDBIT_CLKENAB))); /* Clock enable is passed through. */
11e865c1 2896
b6c77757 2897 /* Force IntSrc to Disabled if DisableIntSrc is asserted. */
11e865c1
GP		 2898 if (!DisableIntSrc)
2899 cra |= ((setup & STDMSK_INTSRC) >> (STDBIT_INTSRC -
2900 CRABIT_INTSRC_A));
2901
b6c77757 2902 /* Populate all mode-dependent attributes of CRA & CRB images. */
11e865c1 2903 switch ((setup & STDMSK_CLKSRC) >> STDBIT_CLKSRC) {
b6c77757
BP		 2904 case CLKSRC_EXTENDER: /* Extender Mode: Force to Timer mode */
2905 /* (Extender valid only for B counters). */
2906
2907 case CLKSRC_TIMER: /* Timer Mode: */
2908 cra |= ((2 << CRABIT_CLKSRC_A) /* ClkSrcA<1> selects system clock */
2909 | ((setup & STDMSK_CLKPOL) >> (STDBIT_CLKPOL - CRABIT_CLKSRC_A)) /* with count direction (ClkSrcA<0>) obtained from ClkPol. */
2910 | (1 << CRABIT_CLKPOL_A) /* ClkPolA behaves as always-on clock enable. */
2911 | (MULT_X1 << CRABIT_CLKMULT_A)); /* ClkMult must be 1x. */
11e865c1
GP		 2912 break;
2913
b6c77757
BP		 2914 default: /* Counter Mode: */
2915 cra |= (CLKSRC_COUNTER /* Select ENC_C and ENC_D as clock/direction inputs. */
2916 | ((setup & STDMSK_CLKPOL) << (CRABIT_CLKPOL_A - STDBIT_CLKPOL)) /* Clock polarity is passed through. */
2917 | (((setup & STDMSK_CLKMULT) == (MULT_X0 << STDBIT_CLKMULT)) ? /* Force multiplier to x1 if not legal, otherwise pass through. */
11e865c1
GP		 2918 (MULT_X1 << CRABIT_CLKMULT_A) :
2919 ((setup & STDMSK_CLKMULT) << (CRABIT_CLKMULT_A -
2920 STDBIT_CLKMULT))));
2921 }
2922
b6c77757
BP		 2923 /* Force positive index polarity if IndxSrc is software-driven only, */
2924 /* otherwise pass it through. */
11e865c1
GP		 2925 if (~setup & STDMSK_INDXSRC)
2926 cra |= ((setup & STDMSK_INDXPOL) << (CRABIT_INDXPOL_A -
2927 STDBIT_INDXPOL));
2928
b6c77757
BP		 2929 /* If IntSrc has been forced to Disabled, update the MISC2 interrupt */
2930 /* enable mask to indicate the counter interrupt is disabled. */
11e865c1
GP		 2931 if (DisableIntSrc)
2932 devpriv->CounterIntEnabs &= ~k->MyEventBits[3];
2933
b6c77757
BP		 2934 /* While retaining CounterB and LatchSrc configurations, program the */
2935 /* new counter operating mode. */
11e865c1
GP		 2936 DEBIreplace(dev, k->MyCRA, CRAMSK_INDXSRC_B | CRAMSK_CLKSRC_B, cra);
2937 DEBIreplace(dev, k->MyCRB,
2938 (uint16_t) (~(CRBMSK_INTCTRL | CRBMSK_CLKENAB_A)), crb);
2939}
2940
e473e912 2941static void SetMode_B(comedi_device *dev, enc_private *k, uint16_t Setup,
11e865c1
GP		 2942 uint16_t DisableIntSrc)
2943{
2944 register uint16_t cra;
2945 register uint16_t crb;
b6c77757 2946 register uint16_t setup = Setup; /* Cache the Standard Setup. */
11e865c1 2947
b6c77757
BP		 2948 /* Initialize CRA and CRB images. */
2949 cra = ((setup & STDMSK_INDXSRC) << ((CRABIT_INDXSRC_B + 1) - STDBIT_INDXSRC)); /* IndexSrc field is restricted to ENC_X or IndxPol. */
11e865c1 2950
b6c77757
BP		 2951 crb = (CRBMSK_INTRESETCMD | CRBMSK_INTRESET_B /* Reset event captures and disable interrupts. */
2952 | ((setup & STDMSK_CLKENAB) << (CRBBIT_CLKENAB_B - STDBIT_CLKENAB)) /* Clock enable is passed through. */
2953 | ((setup & STDMSK_LOADSRC) >> (STDBIT_LOADSRC - CRBBIT_LOADSRC_B))); /* Preload trigger source is passed through. */
11e865c1 2954
b6c77757 2955 /* Force IntSrc to Disabled if DisableIntSrc is asserted. */
11e865c1
GP		 2956 if (!DisableIntSrc)
2957 crb |= ((setup & STDMSK_INTSRC) >> (STDBIT_INTSRC -
2958 CRBBIT_INTSRC_B));
2959
b6c77757 2960 /* Populate all mode-dependent attributes of CRA & CRB images. */
11e865c1 2961 switch ((setup & STDMSK_CLKSRC) >> STDBIT_CLKSRC) {
b6c77757
BP		 2962 case CLKSRC_TIMER: /* Timer Mode: */
2963 cra |= ((2 << CRABIT_CLKSRC_B) /* ClkSrcB<1> selects system clock */
2964 | ((setup & STDMSK_CLKPOL) << (CRABIT_CLKSRC_B - STDBIT_CLKPOL))); /* with direction (ClkSrcB<0>) obtained from ClkPol. */
2965 crb |= ((1 << CRBBIT_CLKPOL_B) /* ClkPolB behaves as always-on clock enable. */
2966 | (MULT_X1 << CRBBIT_CLKMULT_B)); /* ClkMultB must be 1x. */
11e865c1
GP		 2967 break;
2968
b6c77757
BP		 2969 case CLKSRC_EXTENDER: /* Extender Mode: */
2970 cra |= ((2 << CRABIT_CLKSRC_B) /* ClkSrcB source is OverflowA (same as "timer") */
2971 | ((setup & STDMSK_CLKPOL) << (CRABIT_CLKSRC_B - STDBIT_CLKPOL))); /* with direction obtained from ClkPol. */
2972 crb |= ((1 << CRBBIT_CLKPOL_B) /* ClkPolB controls IndexB -- always set to active. */
2973 | (MULT_X0 << CRBBIT_CLKMULT_B)); /* ClkMultB selects OverflowA as the clock source. */
11e865c1
GP		 2974 break;
2975
b6c77757
BP		 2976 default: /* Counter Mode: */
2977 cra |= (CLKSRC_COUNTER << CRABIT_CLKSRC_B); /* Select ENC_C and ENC_D as clock/direction inputs. */
2978 crb |= (((setup & STDMSK_CLKPOL) >> (STDBIT_CLKPOL - CRBBIT_CLKPOL_B)) /* ClkPol is passed through. */
2979 | (((setup & STDMSK_CLKMULT) == (MULT_X0 << STDBIT_CLKMULT)) ? /* Force ClkMult to x1 if not legal, otherwise pass through. */
11e865c1
GP		 2980 (MULT_X1 << CRBBIT_CLKMULT_B) :
2981 ((setup & STDMSK_CLKMULT) << (CRBBIT_CLKMULT_B -
2982 STDBIT_CLKMULT))));
2983 }
2984
b6c77757
BP		 2985 /* Force positive index polarity if IndxSrc is software-driven only, */
2986 /* otherwise pass it through. */
11e865c1
GP		 2987 if (~setup & STDMSK_INDXSRC)
2988 crb |= ((setup & STDMSK_INDXPOL) >> (STDBIT_INDXPOL -
2989 CRBBIT_INDXPOL_B));
2990
b6c77757
BP		 2991 /* If IntSrc has been forced to Disabled, update the MISC2 interrupt */
2992 /* enable mask to indicate the counter interrupt is disabled. */
11e865c1
GP		 2993 if (DisableIntSrc)
2994 devpriv->CounterIntEnabs &= ~k->MyEventBits[3];
2995
b6c77757
BP		 2996 /* While retaining CounterA and LatchSrc configurations, program the */
2997 /* new counter operating mode. */
11e865c1
GP		 2998 DEBIreplace(dev, k->MyCRA,
2999 (uint16_t) (~(CRAMSK_INDXSRC_B | CRAMSK_CLKSRC_B)), cra);
3000 DEBIreplace(dev, k->MyCRB, CRBMSK_CLKENAB_A | CRBMSK_LATCHSRC, crb);
3001}
3002
b6c77757 3003/* Return/set a counter's enable. enab: 0=always enabled, 1=enabled by index. */
11e865c1 3004
e473e912 3005static void SetEnable_A(comedi_device *dev, enc_private *k, uint16_t enab)
11e865c1
GP		 3006{
3007 DEBUG("SetEnable_A: SetEnable_A enter 3541\n");
3008 DEBIreplace(dev, k->MyCRB,
3009 (uint16_t) (~(CRBMSK_INTCTRL | CRBMSK_CLKENAB_A)),
3010 (uint16_t) (enab << CRBBIT_CLKENAB_A));
3011}
3012
e473e912 3013static void SetEnable_B(comedi_device *dev, enc_private *k, uint16_t enab)
11e865c1
GP		 3014{
3015 DEBIreplace(dev, k->MyCRB,
3016 (uint16_t) (~(CRBMSK_INTCTRL | CRBMSK_CLKENAB_B)),
3017 (uint16_t) (enab << CRBBIT_CLKENAB_B));
3018}
3019
e473e912 3020static uint16_t GetEnable_A(comedi_device *dev, enc_private *k)
11e865c1
GP		 3021{
3022 return (DEBIread(dev, k->MyCRB) >> CRBBIT_CLKENAB_A) & 1;
3023}
3024
e473e912 3025static uint16_t GetEnable_B(comedi_device *dev, enc_private *k)
11e865c1
GP		 3026{
3027 return (DEBIread(dev, k->MyCRB) >> CRBBIT_CLKENAB_B) & 1;
3028}
3029
b6c77757
BP		 3030/* Return/set a counter pair's latch trigger source. 0: On read
3031 * access, 1: A index latches A, 2: B index latches B, 3: A overflow
3032 * latches B.
3033 */
11e865c1 3034
e473e912 3035static void SetLatchSource(comedi_device *dev, enc_private *k, uint16_t value)
11e865c1
GP		 3036{
3037 DEBUG("SetLatchSource: SetLatchSource enter 3550 \n");
3038 DEBIreplace(dev, k->MyCRB,
3039 (uint16_t) (~(CRBMSK_INTCTRL | CRBMSK_LATCHSRC)),
3040 (uint16_t) (value << CRBBIT_LATCHSRC));
3041
3042 DEBUG("SetLatchSource: SetLatchSource exit \n");
3043}
3044
b6c77757
BP		 3045/*
3046 * static uint16_t GetLatchSource(comedi_device *dev, enc_private *k )
3047 * {
3048 * return ( DEBIread( dev, k->MyCRB) >> CRBBIT_LATCHSRC ) & 3;
3049 * }
3050 */
11e865c1 3051
b6c77757
BP		 3052/*
3053 * Return/set the event that will trigger transfer of the preload
3054 * register into the counter. 0=ThisCntr_Index, 1=ThisCntr_Overflow,
3055 * 2=OverflowA (B counters only), 3=disabled.
3056 */
11e865c1 3057
e473e912 3058static void SetLoadTrig_A(comedi_device *dev, enc_private *k, uint16_t Trig)
11e865c1
GP		 3059{
3060 DEBIreplace(dev, k->MyCRA, (uint16_t) (~CRAMSK_LOADSRC_A),
3061 (uint16_t) (Trig << CRABIT_LOADSRC_A));
3062}
3063
e473e912 3064static void SetLoadTrig_B(comedi_device *dev, enc_private *k, uint16_t Trig)
11e865c1
GP		 3065{
3066 DEBIreplace(dev, k->MyCRB,
3067 (uint16_t) (~(CRBMSK_LOADSRC_B | CRBMSK_INTCTRL)),
3068 (uint16_t) (Trig << CRBBIT_LOADSRC_B));
3069}
3070
e473e912 3071static uint16_t GetLoadTrig_A(comedi_device *dev, enc_private *k)
11e865c1
GP		 3072{
3073 return (DEBIread(dev, k->MyCRA) >> CRABIT_LOADSRC_A) & 3;
3074}
3075
e473e912 3076static uint16_t GetLoadTrig_B(comedi_device *dev, enc_private *k)
11e865c1
GP		 3077{
3078 return (DEBIread(dev, k->MyCRB) >> CRBBIT_LOADSRC_B) & 3;
3079}
3080
b6c77757
BP		 3081/* Return/set counter interrupt source and clear any captured
3082 * index/overflow events. IntSource: 0=Disabled, 1=OverflowOnly,
3083 * 2=IndexOnly, 3=IndexAndOverflow.
3084 */
11e865c1 3085
e473e912 3086static void SetIntSrc_A(comedi_device *dev, enc_private *k,
11e865c1
GP		 3087 uint16_t IntSource)
3088{
b6c77757 3089 /* Reset any pending counter overflow or index captures. */
11e865c1
GP		 3090 DEBIreplace(dev, k->MyCRB, (uint16_t) (~CRBMSK_INTCTRL),
3091 CRBMSK_INTRESETCMD | CRBMSK_INTRESET_A);
3092
b6c77757 3093 /* Program counter interrupt source. */
11e865c1
GP		 3094 DEBIreplace(dev, k->MyCRA, ~CRAMSK_INTSRC_A,
3095 (uint16_t) (IntSource << CRABIT_INTSRC_A));
3096
b6c77757 3097 /* Update MISC2 interrupt enable mask. */
11e865c1
GP		 3098 devpriv->CounterIntEnabs =
3099 (devpriv->CounterIntEnabs & ~k->MyEventBits[3]) | k->
3100 MyEventBits[IntSource];
3101}
3102
e473e912 3103static void SetIntSrc_B(comedi_device *dev, enc_private *k,
11e865c1
GP		 3104 uint16_t IntSource)
3105{
3106 uint16_t crb;
3107
b6c77757 3108 /* Cache writeable CRB register image. */
11e865c1
GP		 3109 crb = DEBIread(dev, k->MyCRB) & ~CRBMSK_INTCTRL;
3110
b6c77757 3111 /* Reset any pending counter overflow or index captures. */
11e865c1
GP		 3112 DEBIwrite(dev, k->MyCRB,
3113 (uint16_t) (crb | CRBMSK_INTRESETCMD | CRBMSK_INTRESET_B));
3114
b6c77757 3115 /* Program counter interrupt source. */
11e865c1
GP		 3116 DEBIwrite(dev, k->MyCRB,
3117 (uint16_t) ((crb & ~CRBMSK_INTSRC_B) | (IntSource <<
3118 CRBBIT_INTSRC_B)));
3119
b6c77757 3120 /* Update MISC2 interrupt enable mask. */
11e865c1
GP		 3121 devpriv->CounterIntEnabs =
3122 (devpriv->CounterIntEnabs & ~k->MyEventBits[3]) | k->
3123 MyEventBits[IntSource];
3124}
3125
e473e912 3126static uint16_t GetIntSrc_A(comedi_device *dev, enc_private *k)
11e865c1
GP		 3127{
3128 return (DEBIread(dev, k->MyCRA) >> CRABIT_INTSRC_A) & 3;
3129}
3130
e473e912 3131static uint16_t GetIntSrc_B(comedi_device *dev, enc_private *k)
11e865c1
GP		 3132{
3133 return (DEBIread(dev, k->MyCRB) >> CRBBIT_INTSRC_B) & 3;
3134}
3135
b6c77757 3136/* Return/set the clock multiplier. */
11e865c1
GP		 3137
3138/* static void SetClkMult(comedi_device *dev, enc_private *k, uint16_t value ) */
3139/* { */
3140/* k->SetMode(dev, k, (uint16_t)( ( k->GetMode(dev, k ) & ~STDMSK_CLKMULT ) | ( value << STDBIT_CLKMULT ) ), FALSE ); */
3141/* } */
3142
3143/* static uint16_t GetClkMult(comedi_device *dev, enc_private *k ) */
3144/* { */
3145/* return ( k->GetMode(dev, k ) >> STDBIT_CLKMULT ) & 3; */
3146/* } */
3147
b6c77757 3148/* Return/set the clock polarity. */
11e865c1
GP		 3149
3150/* static void SetClkPol( comedi_device *dev,enc_private *k, uint16_t value ) */
3151/* { */
3152/* k->SetMode(dev, k, (uint16_t)( ( k->GetMode(dev, k ) & ~STDMSK_CLKPOL ) | ( value << STDBIT_CLKPOL ) ), FALSE ); */
3153/* } */
3154
3155/* static uint16_t GetClkPol(comedi_device *dev, enc_private *k ) */
3156/* { */
3157/* return ( k->GetMode(dev, k ) >> STDBIT_CLKPOL ) & 1; */
3158/* } */
3159
b6c77757 3160/* Return/set the clock source. */
11e865c1
GP		 3161
3162/* static void SetClkSrc( comedi_device *dev,enc_private *k, uint16_t value ) */
3163/* { */
3164/* k->SetMode(dev, k, (uint16_t)( ( k->GetMode(dev, k ) & ~STDMSK_CLKSRC ) | ( value << STDBIT_CLKSRC ) ), FALSE ); */
3165/* } */
3166
3167/* static uint16_t GetClkSrc( comedi_device *dev,enc_private *k ) */
3168/* { */
3169/* return ( k->GetMode(dev, k ) >> STDBIT_CLKSRC ) & 3; */
3170/* } */
3171
b6c77757 3172/* Return/set the index polarity. */
11e865c1
GP		 3173
3174/* static void SetIndexPol(comedi_device *dev, enc_private *k, uint16_t value ) */
3175/* { */
3176/* k->SetMode(dev, k, (uint16_t)( ( k->GetMode(dev, k ) & ~STDMSK_INDXPOL ) | ( (value != 0) << STDBIT_INDXPOL ) ), FALSE ); */
3177/* } */
3178
3179/* static uint16_t GetIndexPol(comedi_device *dev, enc_private *k ) */
3180/* { */
3181/* return ( k->GetMode(dev, k ) >> STDBIT_INDXPOL ) & 1; */
3182/* } */
3183
b6c77757 3184/* Return/set the index source. */
11e865c1
GP		 3185
3186/* static void SetIndexSrc(comedi_device *dev, enc_private *k, uint16_t value ) */
3187/* { */
3188/* DEBUG("SetIndexSrc: set index src enter 3700\n"); */
3189/* k->SetMode(dev, k, (uint16_t)( ( k->GetMode(dev, k ) & ~STDMSK_INDXSRC ) | ( (value != 0) << STDBIT_INDXSRC ) ), FALSE ); */
3190/* } */
3191
3192/* static uint16_t GetIndexSrc(comedi_device *dev, enc_private *k ) */
3193/* { */
3194/* return ( k->GetMode(dev, k ) >> STDBIT_INDXSRC ) & 1; */
3195/* } */
3196
b6c77757 3197/* Generate an index pulse. */
11e865c1 3198
e473e912 3199static void PulseIndex_A(comedi_device *dev, enc_private *k)
11e865c1
GP		 3200{
3201 register uint16_t cra;
3202
3203 DEBUG("PulseIndex_A: pulse index enter\n");
3204
b6c77757 3205 cra = DEBIread(dev, k->MyCRA); /* Pulse index. */
11e865c1
GP		 3206 DEBIwrite(dev, k->MyCRA, (uint16_t) (cra ^ CRAMSK_INDXPOL_A));
3207 DEBUG("PulseIndex_A: pulse index step1\n");
3208 DEBIwrite(dev, k->MyCRA, cra);
3209}
3210
e473e912 3211static void PulseIndex_B(comedi_device *dev, enc_private *k)
11e865c1
GP		 3212{
3213 register uint16_t crb;
3214
b6c77757 3215 crb = DEBIread(dev, k->MyCRB) & ~CRBMSK_INTCTRL; /* Pulse index. */
11e865c1
GP		 3216 DEBIwrite(dev, k->MyCRB, (uint16_t) (crb ^ CRBMSK_INDXPOL_B));
3217 DEBIwrite(dev, k->MyCRB, crb);
3218}
3219
b6c77757 3220/* Write value into counter preload register. */
11e865c1 3221
e473e912 3222static void Preload(comedi_device *dev, enc_private *k, uint32_t value)
11e865c1
GP		 3223{
3224 DEBUG("Preload: preload enter\n");
b6c77757 3225 DEBIwrite(dev, (uint16_t) (k->MyLatchLsw), (uint16_t) value); /* Write value to preload register. */
11e865c1
GP		 3226 DEBUG("Preload: preload step 1\n");
3227 DEBIwrite(dev, (uint16_t) (k->MyLatchLsw + 2),
3228 (uint16_t) (value >> 16));
3229}
3230
e473e912 3231static void CountersInit(comedi_device *dev)
11e865c1
GP		 3232{
3233 int chan;
3234 enc_private *k;
b6c77757
BP		 3235 uint16_t Setup = (LOADSRC_INDX << BF_LOADSRC) | /* Preload upon */
3236 /* index. */
3237 (INDXSRC_SOFT << BF_INDXSRC) | /* Disable hardware index. */
3238 (CLKSRC_COUNTER << BF_CLKSRC) | /* Operating mode is counter. */
3239 (CLKPOL_POS << BF_CLKPOL) | /* Active high clock. */
3240 (CNTDIR_UP << BF_CLKPOL) | /* Count direction is up. */
3241 (CLKMULT_1X << BF_CLKMULT) | /* Clock multiplier is 1x. */
3242 (CLKENAB_INDEX << BF_CLKENAB); /* Enabled by index */
3243
3244 /* Disable all counter interrupts and clear any captured counter events. */
11e865c1
GP		 3245 for (chan = 0; chan < S626_ENCODER_CHANNELS; chan++) {
3246 k = &encpriv[chan];
3247 k->SetMode(dev, k, Setup, TRUE);
3248 k->SetIntSrc(dev, k, 0);
3249 k->ResetCapFlags(dev, k);
3250 k->SetEnable(dev, k, CLKENAB_ALWAYS);
3251 }
3252 DEBUG("CountersInit: counters initialized \n");
3253
3254}
Linux kernel - Deliverables
This page took 0.199743 seconds and 5 git commands to generate.