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Fix common misspellings
[deliverable/linux.git] / drivers / staging / comedi / drivers / s626.c
CommitLineData
11e865c1
GP		 1/*
2 comedi/drivers/s626.c
3 Sensoray s626 Comedi driver
4
5 COMEDI - Linux Control and Measurement Device Interface
6 Copyright (C) 2000 David A. Schleef <ds@schleef.org>
7
8 Based on Sensoray Model 626 Linux driver Version 0.2
9 Copyright (C) 2002-2004 Sensoray Co., Inc.
10
11 This program is free software; you can redistribute it and/or modify
12 it under the terms of the GNU General Public License as published by
13 the Free Software Foundation; either version 2 of the License, or
14 (at your option) any later version.
15
16 This program is distributed in the hope that it will be useful,
17 but WITHOUT ANY WARRANTY; without even the implied warranty of
18 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 GNU General Public License for more details.
20
21 You should have received a copy of the GNU General Public License
22 along with this program; if not, write to the Free Software
23 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
24
25*/
26
27/*
28Driver: s626
29Description: Sensoray 626 driver
30Devices: [Sensoray] 626 (s626)
31Authors: Gianluca Palli <gpalli@deis.unibo.it>,
32Updated: Fri, 15 Feb 2008 10:28:42 +0000
33Status: experimental
34
35Configuration options:
36 [0] - PCI bus of device (optional)
37 [1] - PCI slot of device (optional)
38 If bus/slot is not specified, the first supported
39 PCI device found will be used.
40
41INSN_CONFIG instructions:
42 analog input:
43 none
44
45 analog output:
46 none
47
48 digital channel:
49 s626 has 3 dio subdevices (2,3 and 4) each with 16 i/o channels
50 supported configuration options:
51 INSN_CONFIG_DIO_QUERY
52 COMEDI_INPUT
53 COMEDI_OUTPUT
54
55 encoder:
56 Every channel must be configured before reading.
57
58 Example code
59
60 insn.insn=INSN_CONFIG; //configuration instruction
61 insn.n=1; //number of operation (must be 1)
62 insn.data=&initialvalue; //initial value loaded into encoder
add74595 63 //during configuration
11e865c1
GP		 64 insn.subdev=5; //encoder subdevice
65 insn.chanspec=CR_PACK(encoder_channel,0,AREF_OTHER); //encoder_channel
add74595 66 //to configure
11e865c1
GP		 67
68 comedi_do_insn(cf,&insn); //executing configuration
69*/
70
25436dc9 71#include <linux/interrupt.h>
11e865c1
GP		 72#include <linux/kernel.h>
73#include <linux/types.h>
74
75#include "../comedidev.h"
76
77#include "comedi_pci.h"
78
79#include "comedi_fc.h"
80#include "s626.h"
81
82MODULE_AUTHOR("Gianluca Palli <gpalli@deis.unibo.it>");
83MODULE_DESCRIPTION("Sensoray 626 Comedi driver module");
84MODULE_LICENSE("GPL");
85
eb5e029e 86struct s626_board {
11e865c1
GP		 87 const char *name;
88 int ai_chans;
89 int ai_bits;
90 int ao_chans;
91 int ao_bits;
92 int dio_chans;
93 int dio_banks;
94 int enc_chans;
eb5e029e 95};
11e865c1 96
eb5e029e 97static const struct s626_board s626_boards[] = {
11e865c1 98 {
0a85b6f0
MT		 99 .name = "s626",
100 .ai_chans = S626_ADC_CHANNELS,
101 .ai_bits = 14,
102 .ao_chans = S626_DAC_CHANNELS,
103 .ao_bits = 13,
104 .dio_chans = S626_DIO_CHANNELS,
105 .dio_banks = S626_DIO_BANKS,
106 .enc_chans = S626_ENCODER_CHANNELS,
107 }
11e865c1
GP		 108};
109
eb5e029e 110#define thisboard ((const struct s626_board *)dev->board_ptr)
11e865c1
GP		 111#define PCI_VENDOR_ID_S626 0x1131
112#define PCI_DEVICE_ID_S626 0x7146
113
8231eb56
HRK		 114/*
115 * For devices with vendor:device id == 0x1131:0x7146 you must specify
116 * also subvendor:subdevice ids, because otherwise it will conflict with
117 * Philips SAA7146 media/dvb based cards.
118 */
11e865c1 119static DEFINE_PCI_DEVICE_TABLE(s626_pci_table) = {
8231eb56 120 {PCI_VENDOR_ID_S626, PCI_DEVICE_ID_S626, 0x6000, 0x0272, 0, 0, 0},
11e865c1
GP		 121 {0}
122};
123
124MODULE_DEVICE_TABLE(pci, s626_pci_table);
125
0707bb04 126static int s626_attach(struct comedi_device *dev, struct comedi_devconfig *it);
71b5f4f1 127static int s626_detach(struct comedi_device *dev);
11e865c1 128
139dfbdf 129static struct comedi_driver driver_s626 = {
b4918808
BP		 130 .driver_name = "s626",
131 .module = THIS_MODULE,
132 .attach = s626_attach,
133 .detach = s626_detach,
11e865c1
GP		 134};
135
eb5e029e 136struct s626_private {
11e865c1
GP		 137 struct pci_dev *pdev;
138 void *base_addr;
139 int got_regions;
140 short allocatedBuf;
b6c77757 141 uint8_t ai_cmd_running; /* ai_cmd is running */
25985edc 142 uint8_t ai_continous; /* continous acquisition */
9d220c6b 143 int ai_sample_count; /* number of samples to acquire */
b6c77757
BP		 144 unsigned int ai_sample_timer;
145 /* time between samples in units of the timer */
146 int ai_convert_count; /* conversion counter */
147 unsigned int ai_convert_timer;
148 /* time between conversion in units of the timer */
149 uint16_t CounterIntEnabs;
150 /* Counter interrupt enable mask for MISC2 register. */
151 uint8_t AdcItems; /* Number of items in ADC poll list. */
0a85b6f0 152 struct bufferDMA RPSBuf; /* DMA buffer used to hold ADC (RPS1) program. */
4753d235 153 struct bufferDMA ANABuf;
b6c77757
BP		 154 /* DMA buffer used to receive ADC data and hold DAC data. */
155 uint32_t *pDacWBuf;
156 /* Pointer to logical adrs of DMA buffer used to hold DAC data. */
157 uint16_t Dacpol; /* Image of DAC polarity register. */
158 uint8_t TrimSetpoint[12]; /* Images of TrimDAC setpoints */
159 uint16_t ChargeEnabled; /* Image of MISC2 Battery */
160 /* Charge Enabled (0 or WRMISC2_CHARGE_ENABLE). */
161 uint16_t WDInterval; /* Image of MISC2 watchdog interval control bits. */
162 uint32_t I2CAdrs;
163 /* I2C device address for onboard EEPROM (board rev dependent). */
164 /* short I2Cards; */
790c5541 165 unsigned int ao_readback[S626_DAC_CHANNELS];
eb5e029e 166};
11e865c1 167
eb5e029e 168struct dio_private {
11e865c1
GP		 169 uint16_t RDDIn;
170 uint16_t WRDOut;
171 uint16_t RDEdgSel;
172 uint16_t WREdgSel;
173 uint16_t RDCapSel;
174 uint16_t WRCapSel;
175 uint16_t RDCapFlg;
176 uint16_t RDIntSel;
177 uint16_t WRIntSel;
eb5e029e 178};
11e865c1 179
eb5e029e 180static struct dio_private dio_private_A = {
b4918808
BP		 181 .RDDIn = LP_RDDINA,
182 .WRDOut = LP_WRDOUTA,
183 .RDEdgSel = LP_RDEDGSELA,
184 .WREdgSel = LP_WREDGSELA,
185 .RDCapSel = LP_RDCAPSELA,
186 .WRCapSel = LP_WRCAPSELA,
187 .RDCapFlg = LP_RDCAPFLGA,
188 .RDIntSel = LP_RDINTSELA,
189 .WRIntSel = LP_WRINTSELA,
11e865c1
GP		 190};
191
eb5e029e 192static struct dio_private dio_private_B = {
b4918808
BP		 193 .RDDIn = LP_RDDINB,
194 .WRDOut = LP_WRDOUTB,
195 .RDEdgSel = LP_RDEDGSELB,
196 .WREdgSel = LP_WREDGSELB,
197 .RDCapSel = LP_RDCAPSELB,
198 .WRCapSel = LP_WRCAPSELB,
199 .RDCapFlg = LP_RDCAPFLGB,
200 .RDIntSel = LP_RDINTSELB,
201 .WRIntSel = LP_WRINTSELB,
11e865c1
GP		 202};
203
eb5e029e 204static struct dio_private dio_private_C = {
b4918808
BP		 205 .RDDIn = LP_RDDINC,
206 .WRDOut = LP_WRDOUTC,
207 .RDEdgSel = LP_RDEDGSELC,
208 .WREdgSel = LP_WREDGSELC,
209 .RDCapSel = LP_RDCAPSELC,
210 .WRCapSel = LP_WRCAPSELC,
211 .RDCapFlg = LP_RDCAPFLGC,
212 .RDIntSel = LP_RDINTSELC,
213 .WRIntSel = LP_WRINTSELC,
11e865c1
GP		 214};
215
216/* to group dio devices (48 bits mask and data are not allowed ???)
eb5e029e 217static struct dio_private *dio_private_word[]={
11e865c1
GP		 218 &dio_private_A,
219 &dio_private_B,
220 &dio_private_C,
221};
222*/
223
eb5e029e
BP		 224#define devpriv ((struct s626_private *)dev->private)
225#define diopriv ((struct dio_private *)s->private)
11e865c1 226
727b286b
AT		 227static int __devinit driver_s626_pci_probe(struct pci_dev *dev,
228 const struct pci_device_id *ent)
229{
230 return comedi_pci_auto_config(dev, driver_s626.driver_name);
231}
232
233static void __devexit driver_s626_pci_remove(struct pci_dev *dev)
234{
235 comedi_pci_auto_unconfig(dev);
236}
237
238static struct pci_driver driver_s626_pci_driver = {
239 .id_table = s626_pci_table,
240 .probe = &driver_s626_pci_probe,
241 .remove = __devexit_p(&driver_s626_pci_remove)
242};
243
244static int __init driver_s626_init_module(void)
245{
246 int retval;
247
248 retval = comedi_driver_register(&driver_s626);
249 if (retval < 0)
250 return retval;
251
252 driver_s626_pci_driver.name = (char *)driver_s626.driver_name;
253 return pci_register_driver(&driver_s626_pci_driver);
254}
255
256static void __exit driver_s626_cleanup_module(void)
257{
258 pci_unregister_driver(&driver_s626_pci_driver);
259 comedi_driver_unregister(&driver_s626);
260}
261
262module_init(driver_s626_init_module);
263module_exit(driver_s626_cleanup_module);
11e865c1 264
b6c77757 265/* ioctl routines */
0a85b6f0
MT		 266static int s626_ai_insn_config(struct comedi_device *dev,
267 struct comedi_subdevice *s,
268 struct comedi_insn *insn, unsigned int *data);
90035c08 269/* static int s626_ai_rinsn(struct comedi_device *dev,struct comedi_subdevice *s,struct comedi_insn *insn,unsigned int *data); */
0a85b6f0
MT		 270static int s626_ai_insn_read(struct comedi_device *dev,
271 struct comedi_subdevice *s,
272 struct comedi_insn *insn, unsigned int *data);
34c43922 273static int s626_ai_cmd(struct comedi_device *dev, struct comedi_subdevice *s);
0a85b6f0
MT		 274static int s626_ai_cmdtest(struct comedi_device *dev,
275 struct comedi_subdevice *s, struct comedi_cmd *cmd);
276static int s626_ai_cancel(struct comedi_device *dev,
277 struct comedi_subdevice *s);
34c43922 278static int s626_ao_winsn(struct comedi_device *dev, struct comedi_subdevice *s,
0a85b6f0 279 struct comedi_insn *insn, unsigned int *data);
34c43922 280static int s626_ao_rinsn(struct comedi_device *dev, struct comedi_subdevice *s,
0a85b6f0
MT		 281 struct comedi_insn *insn, unsigned int *data);
282static int s626_dio_insn_bits(struct comedi_device *dev,
283 struct comedi_subdevice *s,
284 struct comedi_insn *insn, unsigned int *data);
285static int s626_dio_insn_config(struct comedi_device *dev,
286 struct comedi_subdevice *s,
287 struct comedi_insn *insn, unsigned int *data);
71b5f4f1
BP		 288static int s626_dio_set_irq(struct comedi_device *dev, unsigned int chan);
289static int s626_dio_reset_irq(struct comedi_device *dev, unsigned int gruop,
0a85b6f0 290 unsigned int mask);
71b5f4f1 291static int s626_dio_clear_irq(struct comedi_device *dev);
0a85b6f0
MT		 292static int s626_enc_insn_config(struct comedi_device *dev,
293 struct comedi_subdevice *s,
294 struct comedi_insn *insn, unsigned int *data);
295static int s626_enc_insn_read(struct comedi_device *dev,
296 struct comedi_subdevice *s,
297 struct comedi_insn *insn, unsigned int *data);
298static int s626_enc_insn_write(struct comedi_device *dev,
299 struct comedi_subdevice *s,
300 struct comedi_insn *insn, unsigned int *data);
11e865c1 301static int s626_ns_to_timer(int *nanosec, int round_mode);
add74595 302static int s626_ai_load_polllist(uint8_t *ppl, struct comedi_cmd *cmd);
0a85b6f0
MT		 303static int s626_ai_inttrig(struct comedi_device *dev,
304 struct comedi_subdevice *s, unsigned int trignum);
70265d24 305static irqreturn_t s626_irq_handler(int irq, void *d);
790c5541 306static unsigned int s626_ai_reg_to_uint(int data);
34c43922 307/* static unsigned int s626_uint_to_reg(struct comedi_subdevice *s, int data); */
11e865c1 308
b6c77757 309/* end ioctl routines */
11e865c1 310
b6c77757 311/* internal routines */
71b5f4f1 312static void s626_dio_init(struct comedi_device *dev);
0a85b6f0 313static void ResetADC(struct comedi_device *dev, uint8_t * ppl);
71b5f4f1
BP		 314static void LoadTrimDACs(struct comedi_device *dev);
315static void WriteTrimDAC(struct comedi_device *dev, uint8_t LogicalChan,
0a85b6f0 316 uint8_t DacData);
71b5f4f1
BP		 317static uint8_t I2Cread(struct comedi_device *dev, uint8_t addr);
318static uint32_t I2Chandshake(struct comedi_device *dev, uint32_t val);
319static void SetDAC(struct comedi_device *dev, uint16_t chan, short dacdata);
320static void SendDAC(struct comedi_device *dev, uint32_t val);
321static void WriteMISC2(struct comedi_device *dev, uint16_t NewImage);
322static void DEBItransfer(struct comedi_device *dev);
323static uint16_t DEBIread(struct comedi_device *dev, uint16_t addr);
324static void DEBIwrite(struct comedi_device *dev, uint16_t addr, uint16_t wdata);
325static void DEBIreplace(struct comedi_device *dev, uint16_t addr, uint16_t mask,
0a85b6f0
MT		 326 uint16_t wdata);
327static void CloseDMAB(struct comedi_device *dev, struct bufferDMA *pdma,
328 size_t bsize);
11e865c1 329
b6c77757 330/* COUNTER OBJECT ------------------------------------------------ */
eb5e029e 331struct enc_private {
b6c77757 332 /* Pointers to functions that differ for A and B counters: */
add74595
JS		 333 uint16_t(*GetEnable) (struct comedi_device *dev, struct enc_private *); /* Return clock enable. */
334 uint16_t(*GetIntSrc) (struct comedi_device *dev, struct enc_private *); /* Return interrupt source. */
335 uint16_t(*GetLoadTrig) (struct comedi_device *dev, struct enc_private *); /* Return preload trigger source. */
336 uint16_t(*GetMode) (struct comedi_device *dev, struct enc_private *); /* Return standardized operating mode. */
337 void (*PulseIndex) (struct comedi_device *dev, struct enc_private *); /* Generate soft index strobe. */
338 void (*SetEnable) (struct comedi_device *dev, struct enc_private *, uint16_t enab); /* Program clock enable. */
339 void (*SetIntSrc) (struct comedi_device *dev, struct enc_private *, uint16_t IntSource); /* Program interrupt source. */
340 void (*SetLoadTrig) (struct comedi_device *dev, struct enc_private *, uint16_t Trig); /* Program preload trigger source. */
341 void (*SetMode) (struct comedi_device *dev, struct enc_private *, uint16_t Setup, uint16_t DisableIntSrc); /* Program standardized operating mode. */
342 void (*ResetCapFlags) (struct comedi_device *dev, struct enc_private *); /* Reset event capture flags. */
b6c77757
BP		 343
344 uint16_t MyCRA; /* Address of CRA register. */
345 uint16_t MyCRB; /* Address of CRB register. */
346 uint16_t MyLatchLsw; /* Address of Latch least-significant-word */
347 /* register. */
348 uint16_t MyEventBits[4]; /* Bit translations for IntSrc -->RDMISC2. */
eb5e029e 349};
11e865c1 350
eb5e029e 351#define encpriv ((struct enc_private *)(dev->subdevices+5)->private)
11e865c1 352
b6c77757 353/* counters routines */
0a85b6f0
MT		 354static void s626_timer_load(struct comedi_device *dev, struct enc_private *k,
355 int tick);
71b5f4f1
BP		 356static uint32_t ReadLatch(struct comedi_device *dev, struct enc_private *k);
357static void ResetCapFlags_A(struct comedi_device *dev, struct enc_private *k);
358static void ResetCapFlags_B(struct comedi_device *dev, struct enc_private *k);
359static uint16_t GetMode_A(struct comedi_device *dev, struct enc_private *k);
360static uint16_t GetMode_B(struct comedi_device *dev, struct enc_private *k);
0a85b6f0
MT		 361static void SetMode_A(struct comedi_device *dev, struct enc_private *k,
362 uint16_t Setup, uint16_t DisableIntSrc);
363static void SetMode_B(struct comedi_device *dev, struct enc_private *k,
364 uint16_t Setup, uint16_t DisableIntSrc);
365static void SetEnable_A(struct comedi_device *dev, struct enc_private *k,
366 uint16_t enab);
367static void SetEnable_B(struct comedi_device *dev, struct enc_private *k,
368 uint16_t enab);
71b5f4f1
BP		 369static uint16_t GetEnable_A(struct comedi_device *dev, struct enc_private *k);
370static uint16_t GetEnable_B(struct comedi_device *dev, struct enc_private *k);
371static void SetLatchSource(struct comedi_device *dev, struct enc_private *k,
0a85b6f0 372 uint16_t value);
71b5f4f1 373/* static uint16_t GetLatchSource(struct comedi_device *dev, struct enc_private *k ); */
0a85b6f0
MT		 374static void SetLoadTrig_A(struct comedi_device *dev, struct enc_private *k,
375 uint16_t Trig);
376static void SetLoadTrig_B(struct comedi_device *dev, struct enc_private *k,
377 uint16_t Trig);
71b5f4f1
BP		 378static uint16_t GetLoadTrig_A(struct comedi_device *dev, struct enc_private *k);
379static uint16_t GetLoadTrig_B(struct comedi_device *dev, struct enc_private *k);
380static void SetIntSrc_B(struct comedi_device *dev, struct enc_private *k,
0a85b6f0 381 uint16_t IntSource);
71b5f4f1 382static void SetIntSrc_A(struct comedi_device *dev, struct enc_private *k,
0a85b6f0 383 uint16_t IntSource);
71b5f4f1
BP		 384static uint16_t GetIntSrc_A(struct comedi_device *dev, struct enc_private *k);
385static uint16_t GetIntSrc_B(struct comedi_device *dev, struct enc_private *k);
386/* static void SetClkMult(struct comedi_device *dev, struct enc_private *k, uint16_t value ) ; */
387/* static uint16_t GetClkMult(struct comedi_device *dev, struct enc_private *k ) ; */
388/* static void SetIndexPol(struct comedi_device *dev, struct enc_private *k, uint16_t value ); */
389/* static uint16_t GetClkPol(struct comedi_device *dev, struct enc_private *k ) ; */
390/* static void SetIndexSrc( struct comedi_device *dev,struct enc_private *k, uint16_t value ); */
391/* static uint16_t GetClkSrc( struct comedi_device *dev,struct enc_private *k ); */
392/* static void SetIndexSrc( struct comedi_device *dev,struct enc_private *k, uint16_t value ); */
393/* static uint16_t GetIndexSrc( struct comedi_device *dev,struct enc_private *k ); */
394static void PulseIndex_A(struct comedi_device *dev, struct enc_private *k);
395static void PulseIndex_B(struct comedi_device *dev, struct enc_private *k);
0a85b6f0
MT		 396static void Preload(struct comedi_device *dev, struct enc_private *k,
397 uint32_t value);
71b5f4f1 398static void CountersInit(struct comedi_device *dev);
b6c77757 399/* end internal routines */
11e865c1 400
b6c77757 401/* Counter objects constructor. */
11e865c1 402
b6c77757 403/* Counter overflow/index event flag masks for RDMISC2. */
6a98d36e
BP		 404#define INDXMASK(C) (1 << (((C) > 2) ? ((C) * 2 - 1) : ((C) * 2 + 4)))
405#define OVERMASK(C) (1 << (((C) > 2) ? ((C) * 2 + 5) : ((C) * 2 + 10)))
11e865c1
GP		 406#define EVBITS(C) { 0, OVERMASK(C), INDXMASK(C), OVERMASK(C) | INDXMASK(C) }
407
b6c77757
BP		 408/* Translation table to map IntSrc into equivalent RDMISC2 event flag bits. */
409/* static const uint16_t EventBits[][4] = { EVBITS(0), EVBITS(1), EVBITS(2), EVBITS(3), EVBITS(4), EVBITS(5) }; */
11e865c1 410
eb5e029e
BP		 411/* struct enc_private; */
412static struct enc_private enc_private_data[] = {
11e865c1 413 {
0a85b6f0
MT		 414 .GetEnable = GetEnable_A,
415 .GetIntSrc = GetIntSrc_A,
416 .GetLoadTrig = GetLoadTrig_A,
417 .GetMode = GetMode_A,
418 .PulseIndex = PulseIndex_A,
419 .SetEnable = SetEnable_A,
420 .SetIntSrc = SetIntSrc_A,
421 .SetLoadTrig = SetLoadTrig_A,
422 .SetMode = SetMode_A,
423 .ResetCapFlags = ResetCapFlags_A,
424 .MyCRA = LP_CR0A,
425 .MyCRB = LP_CR0B,
426 .MyLatchLsw = LP_CNTR0ALSW,
427 .MyEventBits = EVBITS(0),
428 },
11e865c1 429 {
0a85b6f0
MT		 430 .GetEnable = GetEnable_A,
431 .GetIntSrc = GetIntSrc_A,
432 .GetLoadTrig = GetLoadTrig_A,
433 .GetMode = GetMode_A,
434 .PulseIndex = PulseIndex_A,
435 .SetEnable = SetEnable_A,
436 .SetIntSrc = SetIntSrc_A,
437 .SetLoadTrig = SetLoadTrig_A,
438 .SetMode = SetMode_A,
439 .ResetCapFlags = ResetCapFlags_A,
440 .MyCRA = LP_CR1A,
441 .MyCRB = LP_CR1B,
442 .MyLatchLsw = LP_CNTR1ALSW,
443 .MyEventBits = EVBITS(1),
444 },
11e865c1 445 {
0a85b6f0
MT		 446 .GetEnable = GetEnable_A,
447 .GetIntSrc = GetIntSrc_A,
448 .GetLoadTrig = GetLoadTrig_A,
449 .GetMode = GetMode_A,
450 .PulseIndex = PulseIndex_A,
451 .SetEnable = SetEnable_A,
452 .SetIntSrc = SetIntSrc_A,
453 .SetLoadTrig = SetLoadTrig_A,
454 .SetMode = SetMode_A,
455 .ResetCapFlags = ResetCapFlags_A,
456 .MyCRA = LP_CR2A,
457 .MyCRB = LP_CR2B,
458 .MyLatchLsw = LP_CNTR2ALSW,
459 .MyEventBits = EVBITS(2),
460 },
11e865c1 461 {
0a85b6f0
MT		 462 .GetEnable = GetEnable_B,
463 .GetIntSrc = GetIntSrc_B,
464 .GetLoadTrig = GetLoadTrig_B,
465 .GetMode = GetMode_B,
466 .PulseIndex = PulseIndex_B,
467 .SetEnable = SetEnable_B,
468 .SetIntSrc = SetIntSrc_B,
469 .SetLoadTrig = SetLoadTrig_B,
470 .SetMode = SetMode_B,
471 .ResetCapFlags = ResetCapFlags_B,
472 .MyCRA = LP_CR0A,
473 .MyCRB = LP_CR0B,
474 .MyLatchLsw = LP_CNTR0BLSW,
475 .MyEventBits = EVBITS(3),
476 },
11e865c1 477 {
0a85b6f0
MT		 478 .GetEnable = GetEnable_B,
479 .GetIntSrc = GetIntSrc_B,
480 .GetLoadTrig = GetLoadTrig_B,
481 .GetMode = GetMode_B,
482 .PulseIndex = PulseIndex_B,
483 .SetEnable = SetEnable_B,
484 .SetIntSrc = SetIntSrc_B,
485 .SetLoadTrig = SetLoadTrig_B,
486 .SetMode = SetMode_B,
487 .ResetCapFlags = ResetCapFlags_B,
488 .MyCRA = LP_CR1A,
489 .MyCRB = LP_CR1B,
490 .MyLatchLsw = LP_CNTR1BLSW,
491 .MyEventBits = EVBITS(4),
492 },
11e865c1 493 {
0a85b6f0
MT		 494 .GetEnable = GetEnable_B,
495 .GetIntSrc = GetIntSrc_B,
496 .GetLoadTrig = GetLoadTrig_B,
497 .GetMode = GetMode_B,
498 .PulseIndex = PulseIndex_B,
499 .SetEnable = SetEnable_B,
500 .SetIntSrc = SetIntSrc_B,
501 .SetLoadTrig = SetLoadTrig_B,
502 .SetMode = SetMode_B,
503 .ResetCapFlags = ResetCapFlags_B,
504 .MyCRA = LP_CR2A,
505 .MyCRB = LP_CR2B,
506 .MyLatchLsw = LP_CNTR2BLSW,
507 .MyEventBits = EVBITS(5),
508 },
11e865c1
GP		 509};
510
b6c77757
BP		 511/* enab/disable a function or test status bit(s) that are accessed */
512/* through Main Control Registers 1 or 2. */
6a98d36e 513#define MC_ENABLE(REGADRS, CTRLWORD) writel(((uint32_t)(CTRLWORD) << 16) | (uint32_t)(CTRLWORD), devpriv->base_addr+(REGADRS))
11e865c1 514
6a98d36e 515#define MC_DISABLE(REGADRS, CTRLWORD) writel((uint32_t)(CTRLWORD) << 16 , devpriv->base_addr+(REGADRS))
11e865c1 516
6a98d36e 517#define MC_TEST(REGADRS, CTRLWORD) ((readl(devpriv->base_addr+(REGADRS)) & CTRLWORD) != 0)
11e865c1
GP		 518
519/* #define WR7146(REGARDS,CTRLWORD)
520 writel(CTRLWORD,(uint32_t)(devpriv->base_addr+(REGARDS))) */
8086fff8 521#define WR7146(REGARDS, CTRLWORD) writel(CTRLWORD, devpriv->base_addr+(REGARDS))
11e865c1
GP		 522
523/* #define RR7146(REGARDS)
524 readl((uint32_t)(devpriv->base_addr+(REGARDS))) */
525#define RR7146(REGARDS) readl(devpriv->base_addr+(REGARDS))
526
6a98d36e 527#define BUGFIX_STREG(REGADRS) (REGADRS - 4)
11e865c1 528
b6c77757 529/* Write a time slot control record to TSL2. */
6a98d36e
BP		 530#define VECTPORT(VECTNUM) (P_TSL2 + ((VECTNUM) << 2))
531#define SETVECT(VECTNUM, VECTVAL) WR7146(VECTPORT(VECTNUM), (VECTVAL))
11e865c1 532
b6c77757 533/* Code macros used for constructing I2C command bytes. */
6a98d36e
BP		 534#define I2C_B2(ATTR, VAL) (((ATTR) << 6) | ((VAL) << 24))
535#define I2C_B1(ATTR, VAL) (((ATTR) << 4) | ((VAL) << 16))
536#define I2C_B0(ATTR, VAL) (((ATTR) << 2) | ((VAL) << 8))
11e865c1 537
9ced1de6 538static const struct comedi_lrange s626_range_table = { 2, {
0a85b6f0
MT		 539 RANGE(-5, 5),
540 RANGE(-10, 10),
541 }
11e865c1
GP		 542};
543
0707bb04 544static int s626_attach(struct comedi_device *dev, struct comedi_devconfig *it)
11e865c1
GP		 545{
546/* uint8_t PollList; */
547/* uint16_t AdcData; */
548/* uint16_t StartVal; */
549/* uint16_t index; */
550/* unsigned int data[16]; */
551 int result;
552 int i;
553 int ret;
554 resource_size_t resourceStart;
555 dma_addr_t appdma;
34c43922 556 struct comedi_subdevice *s;
8231eb56
HRK		 557 const struct pci_device_id *ids;
558 struct pci_dev *pdev = NULL;
11e865c1 559
eb5e029e 560 if (alloc_private(dev, sizeof(struct s626_private)) < 0)
11e865c1
GP		 561 return -ENOMEM;
562
8231eb56
HRK		 563 for (i = 0; i < (ARRAY_SIZE(s626_pci_table) - 1) && !pdev; i++) {
564 ids = &s626_pci_table[i];
565 do {
0a85b6f0
MT		 566 pdev = pci_get_subsys(ids->vendor, ids->device,
567 ids->subvendor, ids->subdevice,
568 pdev);
8231eb56
HRK		 569
570 if ((it->options[0] || it->options[1]) && pdev) {
11e865c1 571 /* matches requested bus/slot */
8231eb56
HRK		 572 if (pdev->bus->number == it->options[0] &&
573 PCI_SLOT(pdev->devfn) == it->options[1])
574 break;
575 } else
11e865c1 576 break;
8231eb56 577 } while (1);
11e865c1
GP		 578 }
579 devpriv->pdev = pdev;
580
581 if (pdev == NULL) {
daca497d 582 printk(KERN_ERR "s626_attach: Board not present!!!\n");
11e865c1
GP		 583 return -ENODEV;
584 }
585
197c82bf
BP		 586 result = comedi_pci_enable(pdev, "s626");
587 if (result < 0) {
daca497d 588 printk(KERN_ERR "s626_attach: comedi_pci_enable fails\n");
11e865c1
GP		 589 return -ENODEV;
590 }
591 devpriv->got_regions = 1;
592
593 resourceStart = pci_resource_start(devpriv->pdev, 0);
594
595 devpriv->base_addr = ioremap(resourceStart, SIZEOF_ADDRESS_SPACE);
596 if (devpriv->base_addr == NULL) {
daca497d 597 printk(KERN_ERR "s626_attach: IOREMAP failed\n");
11e865c1
GP		 598 return -ENODEV;
599 }
600
601 if (devpriv->base_addr) {
b6c77757 602 /* disable master interrupt */
11e865c1
GP		 603 writel(0, devpriv->base_addr + P_IER);
604
b6c77757 605 /* soft reset */
11e865c1
GP		 606 writel(MC1_SOFT_RESET, devpriv->base_addr + P_MC1);
607
b6c77757 608 /* DMA FIXME DMA// */
11e865c1
GP		 609 DEBUG("s626_attach: DMA ALLOCATION\n");
610
b6c77757 611 /* adc buffer allocation */
11e865c1
GP		 612 devpriv->allocatedBuf = 0;
613
197c82bf 614 devpriv->ANABuf.LogicalBase =
0a85b6f0 615 pci_alloc_consistent(devpriv->pdev, DMABUF_SIZE, &appdma);
197c82bf
BP		 616
617 if (devpriv->ANABuf.LogicalBase == NULL) {
daca497d 618 printk(KERN_ERR "s626_attach: DMA Memory mapping error\n");
11e865c1
GP		 619 return -ENOMEM;
620 }
621
622 devpriv->ANABuf.PhysicalBase = appdma;
623
0a85b6f0
MT		 624 DEBUG
625 ("s626_attach: AllocDMAB ADC Logical=%p, bsize=%d, Physical=0x%x\n",
626 devpriv->ANABuf.LogicalBase, DMABUF_SIZE,
627 (uint32_t) devpriv->ANABuf.PhysicalBase);
11e865c1
GP		 628
629 devpriv->allocatedBuf++;
630
197c82bf 631 devpriv->RPSBuf.LogicalBase =
0a85b6f0 632 pci_alloc_consistent(devpriv->pdev, DMABUF_SIZE, &appdma);
197c82bf
BP		 633
634 if (devpriv->RPSBuf.LogicalBase == NULL) {
daca497d 635 printk(KERN_ERR "s626_attach: DMA Memory mapping error\n");
11e865c1
GP		 636 return -ENOMEM;
637 }
638
639 devpriv->RPSBuf.PhysicalBase = appdma;
640
0a85b6f0
MT		 641 DEBUG
642 ("s626_attach: AllocDMAB RPS Logical=%p, bsize=%d, Physical=0x%x\n",
643 devpriv->RPSBuf.LogicalBase, DMABUF_SIZE,
644 (uint32_t) devpriv->RPSBuf.PhysicalBase);
11e865c1
GP		 645
646 devpriv->allocatedBuf++;
647
648 }
649
650 dev->board_ptr = s626_boards;
651 dev->board_name = thisboard->name;
652
653 if (alloc_subdevices(dev, 6) < 0)
654 return -ENOMEM;
655
656 dev->iobase = (unsigned long)devpriv->base_addr;
657 dev->irq = devpriv->pdev->irq;
658
b6c77757 659 /* set up interrupt handler */
11e865c1 660 if (dev->irq == 0) {
daca497d 661 printk(KERN_ERR " unknown irq (bad)\n");
11e865c1 662 } else {
5f74ea14
GKH		 663 ret = request_irq(dev->irq, s626_irq_handler, IRQF_SHARED,
664 "s626", dev);
197c82bf
BP		 665
666 if (ret < 0) {
daca497d 667 printk(KERN_ERR " irq not available\n");
11e865c1
GP		 668 dev->irq = 0;
669 }
670 }
671
daca497d 672 DEBUG("s626_attach: -- it opts %d,%d --\n",
0a85b6f0 673 it->options[0], it->options[1]);
11e865c1
GP		 674
675 s = dev->subdevices + 0;
676 /* analog input subdevice */
677 dev->read_subdev = s;
678 /* we support single-ended (ground) and differential */
679 s->type = COMEDI_SUBD_AI;
680 s->subdev_flags = SDF_READABLE | SDF_DIFF | SDF_CMD_READ;
681 s->n_chan = thisboard->ai_chans;
682 s->maxdata = (0xffff >> 2);
683 s->range_table = &s626_range_table;
684 s->len_chanlist = thisboard->ai_chans; /* This is the maximum chanlist
685 length that the board can
686 handle */
687 s->insn_config = s626_ai_insn_config;
688 s->insn_read = s626_ai_insn_read;
689 s->do_cmd = s626_ai_cmd;
690 s->do_cmdtest = s626_ai_cmdtest;
691 s->cancel = s626_ai_cancel;
692
693 s = dev->subdevices + 1;
694 /* analog output subdevice */
695 s->type = COMEDI_SUBD_AO;
696 s->subdev_flags = SDF_WRITABLE | SDF_READABLE;
697 s->n_chan = thisboard->ao_chans;
698 s->maxdata = (0x3fff);
699 s->range_table = &range_bipolar10;
700 s->insn_write = s626_ao_winsn;
701 s->insn_read = s626_ao_rinsn;
702
703 s = dev->subdevices + 2;
704 /* digital I/O subdevice */
705 s->type = COMEDI_SUBD_DIO;
706 s->subdev_flags = SDF_WRITABLE | SDF_READABLE;
707 s->n_chan = S626_DIO_CHANNELS;
708 s->maxdata = 1;
709 s->io_bits = 0xffff;
710 s->private = &dio_private_A;
711 s->range_table = &range_digital;
712 s->insn_config = s626_dio_insn_config;
713 s->insn_bits = s626_dio_insn_bits;
714
715 s = dev->subdevices + 3;
716 /* digital I/O subdevice */
717 s->type = COMEDI_SUBD_DIO;
718 s->subdev_flags = SDF_WRITABLE | SDF_READABLE;
719 s->n_chan = 16;
720 s->maxdata = 1;
721 s->io_bits = 0xffff;
722 s->private = &dio_private_B;
723 s->range_table = &range_digital;
724 s->insn_config = s626_dio_insn_config;
725 s->insn_bits = s626_dio_insn_bits;
726
727 s = dev->subdevices + 4;
728 /* digital I/O subdevice */
729 s->type = COMEDI_SUBD_DIO;
730 s->subdev_flags = SDF_WRITABLE | SDF_READABLE;
731 s->n_chan = 16;
732 s->maxdata = 1;
733 s->io_bits = 0xffff;
734 s->private = &dio_private_C;
735 s->range_table = &range_digital;
736 s->insn_config = s626_dio_insn_config;
737 s->insn_bits = s626_dio_insn_bits;
738
739 s = dev->subdevices + 5;
740 /* encoder (counter) subdevice */
741 s->type = COMEDI_SUBD_COUNTER;
742 s->subdev_flags = SDF_WRITABLE | SDF_READABLE | SDF_LSAMPL;
743 s->n_chan = thisboard->enc_chans;
744 s->private = enc_private_data;
745 s->insn_config = s626_enc_insn_config;
746 s->insn_read = s626_enc_insn_read;
747 s->insn_write = s626_enc_insn_write;
748 s->maxdata = 0xffffff;
749 s->range_table = &range_unknown;
750
b6c77757 751 /* stop ai_command */
11e865c1
GP		 752 devpriv->ai_cmd_running = 0;
753
754 if (devpriv->base_addr && (devpriv->allocatedBuf == 2)) {
755 dma_addr_t pPhysBuf;
756 uint16_t chan;
757
b6c77757 758 /* enab DEBI and audio pins, enable I2C interface. */
11e865c1 759 MC_ENABLE(P_MC1, MC1_DEBI | MC1_AUDIO | MC1_I2C);
b6c77757
BP		 760 /* Configure DEBI operating mode. */
761 WR7146(P_DEBICFG, DEBI_CFG_SLAVE16 /* Local bus is 16 */
0a85b6f0
MT		 762 /* bits wide. */
763 | (DEBI_TOUT << DEBI_CFG_TOUT_BIT)
764
765 /* Declare DEBI */
766 /* transfer timeout */
767 /* interval. */
768 |DEBI_SWAP /* Set up byte lane */
769 /* steering. */
770 | DEBI_CFG_INTEL); /* Intel-compatible */
b6c77757
BP		 771 /* local bus (DEBI */
772 /* never times out). */
11e865c1 773 DEBUG("s626_attach: %d debi init -- %d\n",
0a85b6f0
MT		 774 DEBI_CFG_SLAVE16 | (DEBI_TOUT << DEBI_CFG_TOUT_BIT) |
775 DEBI_SWAP | DEBI_CFG_INTEL,
776 DEBI_CFG_INTEL | DEBI_CFG_TOQ | DEBI_CFG_INCQ |
777 DEBI_CFG_16Q);
11e865c1 778
b6c77757
BP		 779 /* DEBI INIT S626 WR7146( P_DEBICFG, DEBI_CFG_INTEL | DEBI_CFG_TOQ */
780 /* | DEBI_CFG_INCQ| DEBI_CFG_16Q); //end */
11e865c1 781
b6c77757
BP		 782 /* Paging is disabled. */
783 WR7146(P_DEBIPAGE, DEBI_PAGE_DISABLE); /* Disable MMU paging. */
11e865c1 784
b6c77757 785 /* Init GPIO so that ADC Start* is negated. */
11e865c1
GP		 786 WR7146(P_GPIO, GPIO_BASE | GPIO1_HI);
787
0a85b6f0
MT		 788 /* IsBoardRevA is a boolean that indicates whether the board is RevA.
789 *
790 * VERSION 2.01 CHANGE: REV A & B BOARDS NOW SUPPORTED BY DYNAMIC
791 * EEPROM ADDRESS SELECTION. Initialize the I2C interface, which
792 * is used to access the onboard serial EEPROM. The EEPROM's I2C
793 * DeviceAddress is hardwired to a value that is dependent on the
794 * 626 board revision. On all board revisions, the EEPROM stores
795 * TrimDAC calibration constants for analog I/O. On RevB and
796 * higher boards, the DeviceAddress is hardwired to 0 to enable
797 * the EEPROM to also store the PCI SubVendorID and SubDeviceID;
798 * this is the address at which the SAA7146 expects a
799 * configuration EEPROM to reside. On RevA boards, the EEPROM
800 * device address, which is hardwired to 4, prevents the SAA7146
801 * from retrieving PCI sub-IDs, so the SAA7146 uses its built-in
802 * default values, instead.
803 */
b6c77757
BP		 804
805 /* devpriv->I2Cards= IsBoardRevA ? 0xA8 : 0xA0; // Set I2C EEPROM */
806 /* DeviceType (0xA0) */
807 /* and DeviceAddress<<1. */
808
809 devpriv->I2CAdrs = 0xA0; /* I2C device address for onboard */
810 /* eeprom(revb) */
811
812 /* Issue an I2C ABORT command to halt any I2C operation in */
813 /* progress and reset BUSY flag. */
814 WR7146(P_I2CSTAT, I2C_CLKSEL | I2C_ABORT);
815 /* Write I2C control: abort any I2C activity. */
816 MC_ENABLE(P_MC2, MC2_UPLD_IIC);
817 /* Invoke command upload */
add74595 818 while ((RR7146(P_MC2) & MC2_UPLD_IIC) == 0)
ae6eb75c 819 ;
b6c77757
BP		 820 /* and wait for upload to complete. */
821
822 /* Per SAA7146 data sheet, write to STATUS reg twice to
823 * reset all I2C error flags. */
11e865c1 824 for (i = 0; i < 2; i++) {
b6c77757
BP		 825 WR7146(P_I2CSTAT, I2C_CLKSEL);
826 /* Write I2C control: reset error flags. */
827 MC_ENABLE(P_MC2, MC2_UPLD_IIC); /* Invoke command upload */
add74595 828 while (!MC_TEST(P_MC2, MC2_UPLD_IIC))
ae6eb75c 829 ;
b6c77757 830 /* and wait for upload to complete. */
11e865c1
GP		 831 }
832
b6c77757
BP		 833 /* Init audio interface functional attributes: set DAC/ADC
834 * serial clock rates, invert DAC serial clock so that
835 * DAC data setup times are satisfied, enable DAC serial
836 * clock out.
837 */
838
11e865c1
GP		 839 WR7146(P_ACON2, ACON2_INIT);
840
b6c77757
BP		 841 /* Set up TSL1 slot list, which is used to control the
842 * accumulation of ADC data: RSD1 = shift data in on SD1.
843 * SIB_A1 = store data uint8_t at next available location in
844 * FB BUFFER1 register. */
845 WR7146(P_TSL1, RSD1 | SIB_A1);
846 /* Fetch ADC high data uint8_t. */
847 WR7146(P_TSL1 + 4, RSD1 | SIB_A1 | EOS);
848 /* Fetch ADC low data uint8_t; end of TSL1. */
849
850 /* enab TSL1 slot list so that it executes all the time. */
11e865c1
GP		 851 WR7146(P_ACON1, ACON1_ADCSTART);
852
b6c77757 853 /* Initialize RPS registers used for ADC. */
11e865c1 854
b6c77757 855 /* Physical start of RPS program. */
11e865c1
GP		 856 WR7146(P_RPSADDR1, (uint32_t) devpriv->RPSBuf.PhysicalBase);
857
b6c77757
BP		 858 WR7146(P_RPSPAGE1, 0);
859 /* RPS program performs no explicit mem writes. */
860 WR7146(P_RPS1_TOUT, 0); /* Disable RPS timeouts. */
11e865c1 861
b6c77757
BP		 862 /* SAA7146 BUG WORKAROUND. Initialize SAA7146 ADC interface
863 * to a known state by invoking ADCs until FB BUFFER 1
864 * register shows that it is correctly receiving ADC data.
865 * This is necessary because the SAA7146 ADC interface does
866 * not start up in a defined state after a PCI reset.
867 */
11e865c1 868
ae6eb75c
JS		 869/* PollList = EOPL; // Create a simple polling */
870/* // list for analog input */
871/* // channel 0. */
11e865c1
GP		 872/* ResetADC( dev, &PollList ); */
873
874/* s626_ai_rinsn(dev,dev->subdevices,NULL,data); //( &AdcData ); // */
ae6eb75c
JS		 875/* //Get initial ADC */
876/* //value. */
11e865c1
GP		 877
878/* StartVal = data[0]; */
879
880/* // VERSION 2.01 CHANGE: TIMEOUT ADDED TO PREVENT HANGED EXECUTION. */
881/* // Invoke ADCs until the new ADC value differs from the initial */
882/* // value or a timeout occurs. The timeout protects against the */
883/* // possibility that the driver is restarting and the ADC data is a */
884/* // fixed value resulting from the applied ADC analog input being */
885/* // unusually quiet or at the rail. */
886
887/* for ( index = 0; index < 500; index++ ) */
888/* { */
ae6eb75c
JS		 889/* s626_ai_rinsn(dev,dev->subdevices,NULL,data); */
890/* AdcData = data[0]; //ReadADC( &AdcData ); */
891/* if ( AdcData != StartVal ) */
892/* break; */
11e865c1
GP		 893/* } */
894
b6c77757 895 /* end initADC */
11e865c1 896
b6c77757 897 /* init the DAC interface */
11e865c1 898
b6c77757
BP		 899 /* Init Audio2's output DMAC attributes: burst length = 1
900 * DWORD, threshold = 1 DWORD.
901 */
11e865c1
GP		 902 WR7146(P_PCI_BT_A, 0);
903
b6c77757
BP		 904 /* Init Audio2's output DMA physical addresses. The protection
905 * address is set to 1 DWORD past the base address so that a
906 * single DWORD will be transferred each time a DMA transfer is
907 * enabled. */
11e865c1
GP		 908
909 pPhysBuf =
0a85b6f0
MT		 910 devpriv->ANABuf.PhysicalBase +
911 (DAC_WDMABUF_OS * sizeof(uint32_t));
11e865c1 912
b6c77757
BP		 913 WR7146(P_BASEA2_OUT, (uint32_t) pPhysBuf); /* Buffer base adrs. */
914 WR7146(P_PROTA2_OUT, (uint32_t) (pPhysBuf + sizeof(uint32_t))); /* Protection address. */
11e865c1 915
b6c77757
BP		 916 /* Cache Audio2's output DMA buffer logical address. This is
917 * where DAC data is buffered for A2 output DMA transfers. */
11e865c1 918 devpriv->pDacWBuf =
0a85b6f0 919 (uint32_t *) devpriv->ANABuf.LogicalBase + DAC_WDMABUF_OS;
11e865c1 920
b6c77757
BP		 921 /* Audio2's output channels does not use paging. The protection
922 * violation handling bit is set so that the DMAC will
923 * automatically halt and its PCI address pointer will be reset
924 * when the protection address is reached. */
925
11e865c1
GP		 926 WR7146(P_PAGEA2_OUT, 8);
927
b6c77757
BP		 928 /* Initialize time slot list 2 (TSL2), which is used to control
929 * the clock generation for and serialization of data to be sent
930 * to the DAC devices. Slot 0 is a NOP that is used to trap TSL
931 * execution; this permits other slots to be safely modified
932 * without first turning off the TSL sequencer (which is
933 * apparently impossible to do). Also, SD3 (which is driven by a
934 * pull-up resistor) is shifted in and stored to the MSB of
935 * FB_BUFFER2 to be used as evidence that the slot sequence has
936 * not yet finished executing.
937 */
938
939 SETVECT(0, XSD2 | RSD3 | SIB_A2 | EOS);
940 /* Slot 0: Trap TSL execution, shift 0xFF into FB_BUFFER2. */
941
942 /* Initialize slot 1, which is constant. Slot 1 causes a
943 * DWORD to be transferred from audio channel 2's output FIFO
944 * to the FIFO's output buffer so that it can be serialized
945 * and sent to the DAC during subsequent slots. All remaining
946 * slots are dynamically populated as required by the target
947 * DAC device.
948 */
949 SETVECT(1, LF_A2);
950 /* Slot 1: Fetch DWORD from Audio2's output FIFO. */
951
952 /* Start DAC's audio interface (TSL2) running. */
11e865c1
GP		 953 WR7146(P_ACON1, ACON1_DACSTART);
954
b6c77757 955 /* end init DAC interface */
11e865c1 956
b6c77757
BP		 957 /* Init Trim DACs to calibrated values. Do it twice because the
958 * SAA7146 audio channel does not always reset properly and
959 * sometimes causes the first few TrimDAC writes to malfunction.
960 */
11e865c1
GP		 961
962 LoadTrimDACs(dev);
b6c77757 963 LoadTrimDACs(dev); /* Insurance. */
11e865c1 964
b6c77757
BP		 965 /* Manually init all gate array hardware in case this is a soft
966 * reset (we have no way of determining whether this is a warm
967 * or cold start). This is necessary because the gate array will
968 * reset only in response to a PCI hard reset; there is no soft
969 * reset function. */
11e865c1 970
b6c77757
BP		 971 /* Init all DAC outputs to 0V and init all DAC setpoint and
972 * polarity images.
973 */
11e865c1
GP		 974 for (chan = 0; chan < S626_DAC_CHANNELS; chan++)
975 SetDAC(dev, chan, 0);
976
b6c77757
BP		 977 /* Init image of WRMISC2 Battery Charger Enabled control bit.
978 * This image is used when the state of the charger control bit,
979 * which has no direct hardware readback mechanism, is queried.
980 */
11e865c1
GP		 981 devpriv->ChargeEnabled = 0;
982
b6c77757
BP		 983 /* Init image of watchdog timer interval in WRMISC2. This image
984 * maintains the value of the control bits of MISC2 are
985 * continuously reset to zero as long as the WD timer is disabled.
986 */
11e865c1
GP		 987 devpriv->WDInterval = 0;
988
b6c77757
BP		 989 /* Init Counter Interrupt enab mask for RDMISC2. This mask is
990 * applied against MISC2 when testing to determine which timer
991 * events are requesting interrupt service.
992 */
11e865c1
GP		 993 devpriv->CounterIntEnabs = 0;
994
b6c77757 995 /* Init counters. */
11e865c1
GP		 996 CountersInit(dev);
997
b6c77757
BP		 998 /* Without modifying the state of the Battery Backup enab, disable
999 * the watchdog timer, set DIO channels 0-5 to operate in the
1000 * standard DIO (vs. counter overflow) mode, disable the battery
1001 * charger, and reset the watchdog interval selector to zero.
1002 */
11e865c1 1003 WriteMISC2(dev, (uint16_t) (DEBIread(dev,
0a85b6f0
MT		 1004 LP_RDMISC2) &
1005 MISC2_BATT_ENABLE));
11e865c1 1006
b6c77757 1007 /* Initialize the digital I/O subsystem. */
11e865c1
GP		 1008 s626_dio_init(dev);
1009
b6c77757
BP		 1010 /* enable interrupt test */
1011 /* writel(IRQ_GPIO3 | IRQ_RPS1,devpriv->base_addr+P_IER); */
11e865c1
GP		 1012 }
1013
1014 DEBUG("s626_attach: comedi%d s626 attached %04x\n", dev->minor,
0a85b6f0 1015 (uint32_t) devpriv->base_addr);
11e865c1
GP		 1016
1017 return 1;
1018}
1019
790c5541 1020static unsigned int s626_ai_reg_to_uint(int data)
11e865c1 1021{
790c5541 1022 unsigned int tempdata;
11e865c1
GP		 1023
1024 tempdata = (data >> 18);
1025 if (tempdata & 0x2000)
1026 tempdata &= 0x1fff;
1027 else
1028 tempdata += (1 << 13);
1029
1030 return tempdata;
1031}
1032
34c43922 1033/* static unsigned int s626_uint_to_reg(struct comedi_subdevice *s, int data){ */
11e865c1
GP		 1034/* return 0; */
1035/* } */
1036
70265d24 1037static irqreturn_t s626_irq_handler(int irq, void *d)
11e865c1 1038{
71b5f4f1 1039 struct comedi_device *dev = d;
34c43922 1040 struct comedi_subdevice *s;
ea6d0d4c 1041 struct comedi_cmd *cmd;
eb5e029e 1042 struct enc_private *k;
11e865c1
GP		 1043 unsigned long flags;
1044 int32_t *readaddr;
1045 uint32_t irqtype, irqstatus;
1046 int i = 0;
790c5541 1047 short tempdata;
11e865c1
GP		 1048 uint8_t group;
1049 uint16_t irqbit;
1050
25985edc 1051 DEBUG("s626_irq_handler: interrupt request received!!!\n");
11e865c1
GP		 1052
1053 if (dev->attached == 0)
1054 return IRQ_NONE;
b6c77757 1055 /* lock to avoid race with comedi_poll */
5f74ea14 1056 spin_lock_irqsave(&dev->spinlock, flags);
11e865c1 1057
b6c77757 1058 /* save interrupt enable register state */
11e865c1
GP		 1059 irqstatus = readl(devpriv->base_addr + P_IER);
1060
b6c77757 1061 /* read interrupt type */
11e865c1
GP		 1062 irqtype = readl(devpriv->base_addr + P_ISR);
1063
b6c77757 1064 /* disable master interrupt */
11e865c1
GP		 1065 writel(0, devpriv->base_addr + P_IER);
1066
b6c77757 1067 /* clear interrupt */
11e865c1
GP		 1068 writel(irqtype, devpriv->base_addr + P_ISR);
1069
b6c77757 1070 /* do somethings */
11e865c1
GP		 1071 DEBUG("s626_irq_handler: interrupt type %d\n", irqtype);
1072
1073 switch (irqtype) {
b6c77757 1074 case IRQ_RPS1: /* end_of_scan occurs */
11e865c1
GP		 1075
1076 DEBUG("s626_irq_handler: RPS1 irq detected\n");
1077
b6c77757 1078 /* manage ai subdevice */
11e865c1
GP		 1079 s = dev->subdevices;
1080 cmd = &(s->async->cmd);
1081
b6c77757
BP		 1082 /* Init ptr to DMA buffer that holds new ADC data. We skip the
1083 * first uint16_t in the buffer because it contains junk data from
1084 * the final ADC of the previous poll list scan.
1085 */
11e865c1
GP		 1086 readaddr = (int32_t *) devpriv->ANABuf.LogicalBase + 1;
1087
b6c77757 1088 /* get the data and hand it over to comedi */
11e865c1 1089 for (i = 0; i < (s->async->cmd.chanlist_len); i++) {
b6c77757
BP		 1090 /* Convert ADC data to 16-bit integer values and copy to application */
1091 /* buffer. */
11e865c1
GP		 1092 tempdata = s626_ai_reg_to_uint((int)*readaddr);
1093 readaddr++;
1094
b6c77757
BP		 1095 /* put data into read buffer */
1096 /* comedi_buf_put(s->async, tempdata); */
11e865c1 1097 if (cfc_write_to_buffer(s, tempdata) == 0)
0a85b6f0
MT		 1098 printk
1099 ("s626_irq_handler: cfc_write_to_buffer error!\n");
11e865c1
GP		 1100
1101 DEBUG("s626_irq_handler: ai channel %d acquired: %d\n",
0a85b6f0 1102 i, tempdata);
11e865c1
GP		 1103 }
1104
b6c77757 1105 /* end of scan occurs */
11e865c1
GP		 1106 s->async->events |= COMEDI_CB_EOS;
1107
1108 if (!(devpriv->ai_continous))
1109 devpriv->ai_sample_count--;
1110 if (devpriv->ai_sample_count <= 0) {
1111 devpriv->ai_cmd_running = 0;
1112
b6c77757 1113 /* Stop RPS program. */
11e865c1
GP		 1114 MC_DISABLE(P_MC1, MC1_ERPS1);
1115
b6c77757 1116 /* send end of acquisition */
11e865c1
GP		 1117 s->async->events |= COMEDI_CB_EOA;
1118
b6c77757 1119 /* disable master interrupt */
11e865c1
GP		 1120 irqstatus = 0;
1121 }
1122
1123 if (devpriv->ai_cmd_running && cmd->scan_begin_src == TRIG_EXT) {
0a85b6f0
MT		 1124 DEBUG
1125 ("s626_irq_handler: enable interrupt on dio channel %d\n",
1126 cmd->scan_begin_arg);
11e865c1
GP		 1127
1128 s626_dio_set_irq(dev, cmd->scan_begin_arg);
1129
1130 DEBUG("s626_irq_handler: External trigger is set!!!\n");
1131 }
b6c77757 1132 /* tell comedi that data is there */
11e865c1
GP		 1133 DEBUG("s626_irq_handler: events %d\n", s->async->events);
1134 comedi_event(dev, s);
1135 break;
b6c77757 1136 case IRQ_GPIO3: /* check dio and conter interrupt */
11e865c1
GP		 1137
1138 DEBUG("s626_irq_handler: GPIO3 irq detected\n");
1139
b6c77757 1140 /* manage ai subdevice */
11e865c1
GP		 1141 s = dev->subdevices;
1142 cmd = &(s->async->cmd);
1143
b6c77757 1144 /* s626_dio_clear_irq(dev); */
11e865c1
GP		 1145
1146 for (group = 0; group < S626_DIO_BANKS; group++) {
1147 irqbit = 0;
b6c77757 1148 /* read interrupt type */
11e865c1 1149 irqbit = DEBIread(dev,
0a85b6f0
MT		 1150 ((struct dio_private *)(dev->
1151 subdevices +
1152 2 +
1153 group)->
1154 private)->RDCapFlg);
11e865c1 1155
b6c77757 1156 /* check if interrupt is generated from dio channels */
11e865c1
GP		 1157 if (irqbit) {
1158 s626_dio_reset_irq(dev, group, irqbit);
0a85b6f0
MT		 1159 DEBUG
1160 ("s626_irq_handler: check interrupt on dio group %d %d\n",
1161 group, i);
11e865c1 1162 if (devpriv->ai_cmd_running) {
b6c77757 1163 /* check if interrupt is an ai acquisition start trigger */
11e865c1 1164 if ((irqbit >> (cmd->start_arg -
0a85b6f0
MT		 1165 (16 * group)))
1166 == 1 && cmd->start_src == TRIG_EXT) {
1167 DEBUG
25985edc 1168 ("s626_irq_handler: Edge capture interrupt received from channel %d\n",
0a85b6f0 1169 cmd->start_arg);
11e865c1 1170
b6c77757 1171 /* Start executing the RPS program. */
11e865c1
GP		 1172 MC_ENABLE(P_MC1, MC1_ERPS1);
1173
0a85b6f0 1174 DEBUG
25985edc 1175 ("s626_irq_handler: acquisition start triggered!!!\n");
11e865c1
GP		 1176
1177 if (cmd->scan_begin_src ==
0a85b6f0
MT		 1178 TRIG_EXT) {
1179 DEBUG
1180 ("s626_ai_cmd: enable interrupt on dio channel %d\n",
1181 cmd->
1182 scan_begin_arg);
11e865c1
GP		 1183
1184 s626_dio_set_irq(dev,
0a85b6f0 1185 cmd->scan_begin_arg);
11e865c1 1186
0a85b6f0
MT		 1187 DEBUG
1188 ("s626_irq_handler: External scan trigger is set!!!\n");
11e865c1
GP		 1189 }
1190 }
1191 if ((irqbit >> (cmd->scan_begin_arg -
0a85b6f0
MT		 1192 (16 * group)))
1193 == 1
1194 && cmd->scan_begin_src ==
1195 TRIG_EXT) {
1196 DEBUG
25985edc 1197 ("s626_irq_handler: Edge capture interrupt received from channel %d\n",
0a85b6f0 1198 cmd->scan_begin_arg);
11e865c1 1199
b6c77757 1200 /* Trigger ADC scan loop start by setting RPS Signal 0. */
11e865c1
GP		 1201 MC_ENABLE(P_MC2, MC2_ADC_RPS);
1202
0a85b6f0
MT		 1203 DEBUG
1204 ("s626_irq_handler: scan triggered!!! %d\n",
1205 devpriv->ai_sample_count);
11e865c1 1206 if (cmd->convert_src ==
0a85b6f0 1207 TRIG_EXT) {
11e865c1 1208
0a85b6f0
MT		 1209 DEBUG
1210 ("s626_ai_cmd: enable interrupt on dio channel %d group %d\n",
1211 cmd->convert_arg -
1212 (16 * group),
1213 group);
11e865c1 1214
0a85b6f0
MT		 1215 devpriv->ai_convert_count
1216 = cmd->chanlist_len;
11e865c1
GP		 1217
1218 s626_dio_set_irq(dev,
0a85b6f0 1219 cmd->convert_arg);
11e865c1 1220
0a85b6f0
MT		 1221 DEBUG
1222 ("s626_irq_handler: External convert trigger is set!!!\n");
11e865c1
GP		 1223 }
1224
1225 if (cmd->convert_src ==
0a85b6f0 1226 TRIG_TIMER) {
11e865c1 1227 k = &encpriv[5];
0a85b6f0
MT		 1228 devpriv->ai_convert_count
1229 = cmd->chanlist_len;
11e865c1 1230 k->SetEnable(dev, k,
0a85b6f0 1231 CLKENAB_ALWAYS);
11e865c1
GP		 1232 }
1233 }
1234 if ((irqbit >> (cmd->convert_arg -
0a85b6f0
MT		 1235 (16 * group)))
1236 == 1
1237 && cmd->convert_src == TRIG_EXT) {
1238 DEBUG
25985edc 1239 ("s626_irq_handler: Edge capture interrupt received from channel %d\n",
0a85b6f0 1240 cmd->convert_arg);
11e865c1 1241
b6c77757 1242 /* Trigger ADC scan loop start by setting RPS Signal 0. */
11e865c1
GP		 1243 MC_ENABLE(P_MC2, MC2_ADC_RPS);
1244
0a85b6f0
MT		 1245 DEBUG
1246 ("s626_irq_handler: adc convert triggered!!!\n");
11e865c1
GP		 1247
1248 devpriv->ai_convert_count--;
1249
1250 if (devpriv->ai_convert_count >
0a85b6f0 1251 0) {
11e865c1 1252
0a85b6f0
MT		 1253 DEBUG
1254 ("s626_ai_cmd: enable interrupt on dio channel %d group %d\n",
1255 cmd->convert_arg -
1256 (16 * group),
1257 group);
11e865c1
GP		 1258
1259 s626_dio_set_irq(dev,
0a85b6f0 1260 cmd->convert_arg);
11e865c1 1261
0a85b6f0
MT		 1262 DEBUG
1263 ("s626_irq_handler: External trigger is set!!!\n");
11e865c1
GP		 1264 }
1265 }
1266 }
1267 break;
1268 }
1269 }
1270
b6c77757 1271 /* read interrupt type */
11e865c1
GP		 1272 irqbit = DEBIread(dev, LP_RDMISC2);
1273
b6c77757 1274 /* check interrupt on counters */
11e865c1 1275 DEBUG("s626_irq_handler: check counters interrupt %d\n",
0a85b6f0 1276 irqbit);
11e865c1
GP		 1277
1278 if (irqbit & IRQ_COINT1A) {
0a85b6f0
MT		 1279 DEBUG
1280 ("s626_irq_handler: interrupt on counter 1A overflow\n");
11e865c1
GP		 1281 k = &encpriv[0];
1282
b6c77757 1283 /* clear interrupt capture flag */
11e865c1
GP		 1284 k->ResetCapFlags(dev, k);
1285 }
1286 if (irqbit & IRQ_COINT2A) {
0a85b6f0
MT		 1287 DEBUG
1288 ("s626_irq_handler: interrupt on counter 2A overflow\n");
11e865c1
GP		 1289 k = &encpriv[1];
1290
b6c77757 1291 /* clear interrupt capture flag */
11e865c1
GP		 1292 k->ResetCapFlags(dev, k);
1293 }
1294 if (irqbit & IRQ_COINT3A) {
0a85b6f0
MT		 1295 DEBUG
1296 ("s626_irq_handler: interrupt on counter 3A overflow\n");
11e865c1
GP		 1297 k = &encpriv[2];
1298
b6c77757 1299 /* clear interrupt capture flag */
11e865c1
GP		 1300 k->ResetCapFlags(dev, k);
1301 }
1302 if (irqbit & IRQ_COINT1B) {
0a85b6f0
MT		 1303 DEBUG
1304 ("s626_irq_handler: interrupt on counter 1B overflow\n");
11e865c1
GP		 1305 k = &encpriv[3];
1306
b6c77757 1307 /* clear interrupt capture flag */
11e865c1
GP		 1308 k->ResetCapFlags(dev, k);
1309 }
1310 if (irqbit & IRQ_COINT2B) {
0a85b6f0
MT		 1311 DEBUG
1312 ("s626_irq_handler: interrupt on counter 2B overflow\n");
11e865c1
GP		 1313 k = &encpriv[4];
1314
b6c77757 1315 /* clear interrupt capture flag */
11e865c1
GP		 1316 k->ResetCapFlags(dev, k);
1317
1318 if (devpriv->ai_convert_count > 0) {
1319 devpriv->ai_convert_count--;
1320 if (devpriv->ai_convert_count == 0)
1321 k->SetEnable(dev, k, CLKENAB_INDEX);
1322
1323 if (cmd->convert_src == TRIG_TIMER) {
0a85b6f0
MT		 1324 DEBUG
1325 ("s626_irq_handler: conver timer trigger!!! %d\n",
1326 devpriv->ai_convert_count);
11e865c1 1327
b6c77757 1328 /* Trigger ADC scan loop start by setting RPS Signal 0. */
11e865c1
GP		 1329 MC_ENABLE(P_MC2, MC2_ADC_RPS);
1330 }
1331 }
1332 }
1333 if (irqbit & IRQ_COINT3B) {
0a85b6f0
MT		 1334 DEBUG
1335 ("s626_irq_handler: interrupt on counter 3B overflow\n");
11e865c1
GP		 1336 k = &encpriv[5];
1337
b6c77757 1338 /* clear interrupt capture flag */
11e865c1
GP		 1339 k->ResetCapFlags(dev, k);
1340
1341 if (cmd->scan_begin_src == TRIG_TIMER) {
0a85b6f0
MT		 1342 DEBUG
1343 ("s626_irq_handler: scan timer trigger!!!\n");
11e865c1 1344
b6c77757 1345 /* Trigger ADC scan loop start by setting RPS Signal 0. */
11e865c1
GP		 1346 MC_ENABLE(P_MC2, MC2_ADC_RPS);
1347 }
1348
1349 if (cmd->convert_src == TRIG_TIMER) {
0a85b6f0
MT		 1350 DEBUG
1351 ("s626_irq_handler: convert timer trigger is set\n");
11e865c1
GP		 1352 k = &encpriv[4];
1353 devpriv->ai_convert_count = cmd->chanlist_len;
1354 k->SetEnable(dev, k, CLKENAB_ALWAYS);
1355 }
1356 }
1357 }
1358
b6c77757 1359 /* enable interrupt */
11e865c1
GP		 1360 writel(irqstatus, devpriv->base_addr + P_IER);
1361
1362 DEBUG("s626_irq_handler: exit interrupt service routine.\n");
1363
5f74ea14 1364 spin_unlock_irqrestore(&dev->spinlock, flags);
11e865c1
GP		 1365 return IRQ_HANDLED;
1366}
1367
71b5f4f1 1368static int s626_detach(struct comedi_device *dev)
11e865c1
GP		 1369{
1370 if (devpriv) {
b6c77757 1371 /* stop ai_command */
11e865c1
GP		 1372 devpriv->ai_cmd_running = 0;
1373
1374 if (devpriv->base_addr) {
b6c77757
BP		 1375 /* interrupt mask */
1376 WR7146(P_IER, 0); /* Disable master interrupt. */
1377 WR7146(P_ISR, IRQ_GPIO3 | IRQ_RPS1); /* Clear board's IRQ status flag. */
11e865c1 1378
b6c77757 1379 /* Disable the watchdog timer and battery charger. */
11e865c1
GP		 1380 WriteMISC2(dev, 0);
1381
b6c77757 1382 /* Close all interfaces on 7146 device. */
11e865c1
GP		 1383 WR7146(P_MC1, MC1_SHUTDOWN);
1384 WR7146(P_ACON1, ACON1_BASE);
1385
1386 CloseDMAB(dev, &devpriv->RPSBuf, DMABUF_SIZE);
1387 CloseDMAB(dev, &devpriv->ANABuf, DMABUF_SIZE);
1388 }
1389
82675f35 1390 if (dev->irq)
5f74ea14 1391 free_irq(dev->irq, dev);
11e865c1 1392
82675f35 1393 if (devpriv->base_addr)
11e865c1 1394 iounmap(devpriv->base_addr);
11e865c1
GP		 1395
1396 if (devpriv->pdev) {
82675f35 1397 if (devpriv->got_regions)
11e865c1 1398 comedi_pci_disable(devpriv->pdev);
11e865c1
GP		 1399 pci_dev_put(devpriv->pdev);
1400 }
1401 }
1402
1403 DEBUG("s626_detach: S626 detached!\n");
1404
1405 return 0;
1406}
1407
1408/*
1409 * this functions build the RPS program for hardware driven acquistion
1410 */
0a85b6f0 1411void ResetADC(struct comedi_device *dev, uint8_t * ppl)
11e865c1
GP		 1412{
1413 register uint32_t *pRPS;
1414 uint32_t JmpAdrs;
1415 uint16_t i;
1416 uint16_t n;
1417 uint32_t LocalPPL;
ea6d0d4c 1418 struct comedi_cmd *cmd = &(dev->subdevices->async->cmd);
11e865c1 1419
b6c77757 1420 /* Stop RPS program in case it is currently running. */
11e865c1
GP		 1421 MC_DISABLE(P_MC1, MC1_ERPS1);
1422
b6c77757 1423 /* Set starting logical address to write RPS commands. */
11e865c1
GP		 1424 pRPS = (uint32_t *) devpriv->RPSBuf.LogicalBase;
1425
b6c77757 1426 /* Initialize RPS instruction pointer. */
11e865c1
GP		 1427 WR7146(P_RPSADDR1, (uint32_t) devpriv->RPSBuf.PhysicalBase);
1428
b6c77757 1429 /* Construct RPS program in RPSBuf DMA buffer */
11e865c1
GP		 1430
1431 if (cmd != NULL && cmd->scan_begin_src != TRIG_FOLLOW) {
1432 DEBUG("ResetADC: scan_begin pause inserted\n");
b6c77757 1433 /* Wait for Start trigger. */
11e865c1
GP		 1434 *pRPS++ = RPS_PAUSE | RPS_SIGADC;
1435 *pRPS++ = RPS_CLRSIGNAL | RPS_SIGADC;
1436 }
b6c77757
BP		 1437
1438 /* SAA7146 BUG WORKAROUND Do a dummy DEBI Write. This is necessary
1439 * because the first RPS DEBI Write following a non-RPS DEBI write
1440 * seems to always fail. If we don't do this dummy write, the ADC
1441 * gain might not be set to the value required for the first slot in
1442 * the poll list; the ADC gain would instead remain unchanged from
1443 * the previously programmed value.
1444 */
1445 *pRPS++ = RPS_LDREG | (P_DEBICMD >> 2);
1446 /* Write DEBI Write command and address to shadow RAM. */
1447
11e865c1 1448 *pRPS++ = DEBI_CMD_WRWORD | LP_GSEL;
b6c77757
BP		 1449 *pRPS++ = RPS_LDREG | (P_DEBIAD >> 2);
1450 /* Write DEBI immediate data to shadow RAM: */
1451
1452 *pRPS++ = GSEL_BIPOLAR5V;
1453 /* arbitrary immediate data value. */
1454
1455 *pRPS++ = RPS_CLRSIGNAL | RPS_DEBI;
1456 /* Reset "shadow RAM uploaded" flag. */
1457 *pRPS++ = RPS_UPLOAD | RPS_DEBI; /* Invoke shadow RAM upload. */
1458 *pRPS++ = RPS_PAUSE | RPS_DEBI; /* Wait for shadow upload to finish. */
1459
1460 /* Digitize all slots in the poll list. This is implemented as a
1461 * for loop to limit the slot count to 16 in case the application
1462 * forgot to set the EOPL flag in the final slot.
1463 */
11e865c1 1464 for (devpriv->AdcItems = 0; devpriv->AdcItems < 16; devpriv->AdcItems++) {
0a85b6f0
MT		 1465 /* Convert application's poll list item to private board class
1466 * format. Each app poll list item is an uint8_t with form
1467 * (EOPL,x,x,RANGE,CHAN<3:0>), where RANGE code indicates 0 =
1468 * +-10V, 1 = +-5V, and EOPL = End of Poll List marker.
1469 */
11e865c1 1470 LocalPPL =
0a85b6f0
MT		 1471 (*ppl << 8) | (*ppl & 0x10 ? GSEL_BIPOLAR5V :
1472 GSEL_BIPOLAR10V);
11e865c1 1473
b6c77757
BP		 1474 /* Switch ADC analog gain. */
1475 *pRPS++ = RPS_LDREG | (P_DEBICMD >> 2); /* Write DEBI command */
1476 /* and address to */
1477 /* shadow RAM. */
11e865c1 1478 *pRPS++ = DEBI_CMD_WRWORD | LP_GSEL;
b6c77757
BP		 1479 *pRPS++ = RPS_LDREG | (P_DEBIAD >> 2); /* Write DEBI */
1480 /* immediate data to */
1481 /* shadow RAM. */
11e865c1 1482 *pRPS++ = LocalPPL;
b6c77757
BP		 1483 *pRPS++ = RPS_CLRSIGNAL | RPS_DEBI; /* Reset "shadow RAM uploaded" */
1484 /* flag. */
1485 *pRPS++ = RPS_UPLOAD | RPS_DEBI; /* Invoke shadow RAM upload. */
1486 *pRPS++ = RPS_PAUSE | RPS_DEBI; /* Wait for shadow upload to */
1487 /* finish. */
1488
1489 /* Select ADC analog input channel. */
1490 *pRPS++ = RPS_LDREG | (P_DEBICMD >> 2);
1491 /* Write DEBI command and address to shadow RAM. */
11e865c1 1492 *pRPS++ = DEBI_CMD_WRWORD | LP_ISEL;
b6c77757
BP		 1493 *pRPS++ = RPS_LDREG | (P_DEBIAD >> 2);
1494 /* Write DEBI immediate data to shadow RAM. */
11e865c1 1495 *pRPS++ = LocalPPL;
b6c77757
BP		 1496 *pRPS++ = RPS_CLRSIGNAL | RPS_DEBI;
1497 /* Reset "shadow RAM uploaded" flag. */
1498
1499 *pRPS++ = RPS_UPLOAD | RPS_DEBI;
1500 /* Invoke shadow RAM upload. */
1501
1502 *pRPS++ = RPS_PAUSE | RPS_DEBI;
1503 /* Wait for shadow upload to finish. */
1504
1505 /* Delay at least 10 microseconds for analog input settling.
1506 * Instead of padding with NOPs, we use RPS_JUMP instructions
1507 * here; this allows us to produce a longer delay than is
1508 * possible with NOPs because each RPS_JUMP flushes the RPS'
1509 * instruction prefetch pipeline.
1510 */
11e865c1 1511 JmpAdrs =
0a85b6f0
MT		 1512 (uint32_t) devpriv->RPSBuf.PhysicalBase +
1513 (uint32_t) ((unsigned long)pRPS -
1514 (unsigned long)devpriv->RPSBuf.LogicalBase);
11e865c1 1515 for (i = 0; i < (10 * RPSCLK_PER_US / 2); i++) {
b6c77757
BP		 1516 JmpAdrs += 8; /* Repeat to implement time delay: */
1517 *pRPS++ = RPS_JUMP; /* Jump to next RPS instruction. */
11e865c1
GP		 1518 *pRPS++ = JmpAdrs;
1519 }
1520
1521 if (cmd != NULL && cmd->convert_src != TRIG_NOW) {
1522 DEBUG("ResetADC: convert pause inserted\n");
b6c77757 1523 /* Wait for Start trigger. */
11e865c1
GP		 1524 *pRPS++ = RPS_PAUSE | RPS_SIGADC;
1525 *pRPS++ = RPS_CLRSIGNAL | RPS_SIGADC;
1526 }
b6c77757
BP		 1527 /* Start ADC by pulsing GPIO1. */
1528 *pRPS++ = RPS_LDREG | (P_GPIO >> 2); /* Begin ADC Start pulse. */
11e865c1
GP		 1529 *pRPS++ = GPIO_BASE | GPIO1_LO;
1530 *pRPS++ = RPS_NOP;
b6c77757
BP		 1531 /* VERSION 2.03 CHANGE: STRETCH OUT ADC START PULSE. */
1532 *pRPS++ = RPS_LDREG | (P_GPIO >> 2); /* End ADC Start pulse. */
11e865c1
GP		 1533 *pRPS++ = GPIO_BASE | GPIO1_HI;
1534
b6c77757
BP		 1535 /* Wait for ADC to complete (GPIO2 is asserted high when ADC not
1536 * busy) and for data from previous conversion to shift into FB
1537 * BUFFER 1 register.
1538 */
1539 *pRPS++ = RPS_PAUSE | RPS_GPIO2; /* Wait for ADC done. */
11e865c1 1540
b6c77757 1541 /* Transfer ADC data from FB BUFFER 1 register to DMA buffer. */
11e865c1
GP		 1542 *pRPS++ = RPS_STREG | (BUGFIX_STREG(P_FB_BUFFER1) >> 2);
1543 *pRPS++ =
0a85b6f0
MT		 1544 (uint32_t) devpriv->ANABuf.PhysicalBase +
1545 (devpriv->AdcItems << 2);
11e865c1 1546
b6c77757
BP		 1547 /* If this slot's EndOfPollList flag is set, all channels have */
1548 /* now been processed. */
11e865c1 1549 if (*ppl++ & EOPL) {
b6c77757
BP		 1550 devpriv->AdcItems++; /* Adjust poll list item count. */
1551 break; /* Exit poll list processing loop. */
11e865c1
GP		 1552 }
1553 }
daca497d 1554 DEBUG("ResetADC: ADC items %d\n", devpriv->AdcItems);
11e865c1 1555
b6c77757
BP		 1556 /* VERSION 2.01 CHANGE: DELAY CHANGED FROM 250NS to 2US. Allow the
1557 * ADC to stabilize for 2 microseconds before starting the final
1558 * (dummy) conversion. This delay is necessary to allow sufficient
1559 * time between last conversion finished and the start of the dummy
1560 * conversion. Without this delay, the last conversion's data value
1561 * is sometimes set to the previous conversion's data value.
1562 */
11e865c1
GP		 1563 for (n = 0; n < (2 * RPSCLK_PER_US); n++)
1564 *pRPS++ = RPS_NOP;
1565
b6c77757
BP		 1566 /* Start a dummy conversion to cause the data from the last
1567 * conversion of interest to be shifted in.
1568 */
1569 *pRPS++ = RPS_LDREG | (P_GPIO >> 2); /* Begin ADC Start pulse. */
11e865c1
GP		 1570 *pRPS++ = GPIO_BASE | GPIO1_LO;
1571 *pRPS++ = RPS_NOP;
b6c77757
BP		 1572 /* VERSION 2.03 CHANGE: STRETCH OUT ADC START PULSE. */
1573 *pRPS++ = RPS_LDREG | (P_GPIO >> 2); /* End ADC Start pulse. */
11e865c1
GP		 1574 *pRPS++ = GPIO_BASE | GPIO1_HI;
1575
b6c77757
BP		 1576 /* Wait for the data from the last conversion of interest to arrive
1577 * in FB BUFFER 1 register.
1578 */
1579 *pRPS++ = RPS_PAUSE | RPS_GPIO2; /* Wait for ADC done. */
11e865c1 1580
b6c77757
BP		 1581 /* Transfer final ADC data from FB BUFFER 1 register to DMA buffer. */
1582 *pRPS++ = RPS_STREG | (BUGFIX_STREG(P_FB_BUFFER1) >> 2); /* */
11e865c1 1583 *pRPS++ =
0a85b6f0 1584 (uint32_t) devpriv->ANABuf.PhysicalBase + (devpriv->AdcItems << 2);
11e865c1 1585
b6c77757
BP		 1586 /* Indicate ADC scan loop is finished. */
1587 /* *pRPS++= RPS_CLRSIGNAL | RPS_SIGADC ; // Signal ReadADC() that scan is done. */
11e865c1 1588
b6c77757 1589 /* invoke interrupt */
11e865c1
GP		 1590 if (devpriv->ai_cmd_running == 1) {
1591 DEBUG("ResetADC: insert irq in ADC RPS task\n");
1592 *pRPS++ = RPS_IRQ;
1593 }
b6c77757
BP		 1594 /* Restart RPS program at its beginning. */
1595 *pRPS++ = RPS_JUMP; /* Branch to start of RPS program. */
11e865c1
GP		 1596 *pRPS++ = (uint32_t) devpriv->RPSBuf.PhysicalBase;
1597
b6c77757 1598 /* End of RPS program build */
11e865c1
GP		 1599}
1600
1601/* TO COMPLETE, IF NECESSARY */
0a85b6f0
MT		 1602static int s626_ai_insn_config(struct comedi_device *dev,
1603 struct comedi_subdevice *s,
1604 struct comedi_insn *insn, unsigned int *data)
11e865c1
GP		 1605{
1606
1607 return -EINVAL;
1608}
1609
90035c08 1610/* static int s626_ai_rinsn(struct comedi_device *dev,struct comedi_subdevice *s,struct comedi_insn *insn,unsigned int *data) */
11e865c1
GP		 1611/* { */
1612/* register uint8_t i; */
1613/* register int32_t *readaddr; */
1614
daca497d 1615/* DEBUG("as626_ai_rinsn: ai_rinsn enter\n"); */
11e865c1 1616
b6c77757 1617/* Trigger ADC scan loop start by setting RPS Signal 0. */
11e865c1
GP		 1618/* MC_ENABLE( P_MC2, MC2_ADC_RPS ); */
1619
b6c77757 1620/* Wait until ADC scan loop is finished (RPS Signal 0 reset). */
11e865c1
GP		 1621/* while ( MC_TEST( P_MC2, MC2_ADC_RPS ) ); */
1622
b6c77757
BP		 1623/* Init ptr to DMA buffer that holds new ADC data. We skip the
1624 * first uint16_t in the buffer because it contains junk data from
1625 * the final ADC of the previous poll list scan.
1626 */
11e865c1
GP		 1627/* readaddr = (uint32_t *)devpriv->ANABuf.LogicalBase + 1; */
1628
b6c77757 1629/* Convert ADC data to 16-bit integer values and copy to application buffer. */
11e865c1
GP		 1630/* for ( i = 0; i < devpriv->AdcItems; i++ ) { */
1631/* *data = s626_ai_reg_to_uint( *readaddr++ ); */
daca497d 1632/* DEBUG("s626_ai_rinsn: data %d\n",*data); */
11e865c1
GP		 1633/* data++; */
1634/* } */
1635
daca497d 1636/* DEBUG("s626_ai_rinsn: ai_rinsn escape\n"); */
11e865c1
GP		 1637/* return i; */
1638/* } */
1639
0a85b6f0
MT		 1640static int s626_ai_insn_read(struct comedi_device *dev,
1641 struct comedi_subdevice *s,
1642 struct comedi_insn *insn, unsigned int *data)
11e865c1
GP		 1643{
1644 uint16_t chan = CR_CHAN(insn->chanspec);
1645 uint16_t range = CR_RANGE(insn->chanspec);
1646 uint16_t AdcSpec = 0;
1647 uint32_t GpioImage;
1648 int n;
1649
0a85b6f0 1650 /* interrupt call test */
b6c77757
BP		 1651/* writel(IRQ_GPIO3,devpriv->base_addr+P_PSR); */
1652 /* Writing a logical 1 into any of the RPS_PSR bits causes the
1653 * corresponding interrupt to be generated if enabled
1654 */
11e865c1
GP		 1655
1656 DEBUG("s626_ai_insn_read: entering\n");
1657
b6c77757
BP		 1658 /* Convert application's ADC specification into form
1659 * appropriate for register programming.
1660 */
11e865c1
GP		 1661 if (range == 0)
1662 AdcSpec = (chan << 8) | (GSEL_BIPOLAR5V);
1663 else
1664 AdcSpec = (chan << 8) | (GSEL_BIPOLAR10V);
1665
b6c77757
BP		 1666 /* Switch ADC analog gain. */
1667 DEBIwrite(dev, LP_GSEL, AdcSpec); /* Set gain. */
11e865c1 1668
b6c77757
BP		 1669 /* Select ADC analog input channel. */
1670 DEBIwrite(dev, LP_ISEL, AdcSpec); /* Select channel. */
11e865c1
GP		 1671
1672 for (n = 0; n < insn->n; n++) {
1673
b6c77757 1674 /* Delay 10 microseconds for analog input settling. */
5f74ea14 1675 udelay(10);
11e865c1 1676
b6c77757 1677 /* Start ADC by pulsing GPIO1 low. */
11e865c1 1678 GpioImage = RR7146(P_GPIO);
b6c77757 1679 /* Assert ADC Start command */
11e865c1 1680 WR7146(P_GPIO, GpioImage & ~GPIO1_HI);
b6c77757 1681 /* and stretch it out. */
11e865c1
GP		 1682 WR7146(P_GPIO, GpioImage & ~GPIO1_HI);
1683 WR7146(P_GPIO, GpioImage & ~GPIO1_HI);
b6c77757 1684 /* Negate ADC Start command. */
11e865c1
GP		 1685 WR7146(P_GPIO, GpioImage | GPIO1_HI);
1686
b6c77757
BP		 1687 /* Wait for ADC to complete (GPIO2 is asserted high when */
1688 /* ADC not busy) and for data from previous conversion to */
1689 /* shift into FB BUFFER 1 register. */
11e865c1 1690
b6c77757 1691 /* Wait for ADC done. */
add74595 1692 while (!(RR7146(P_PSR) & PSR_GPIO2))
ae6eb75c 1693 ;
11e865c1 1694
b6c77757 1695 /* Fetch ADC data. */
11e865c1
GP		 1696 if (n != 0)
1697 data[n - 1] = s626_ai_reg_to_uint(RR7146(P_FB_BUFFER1));
1698
b6c77757
BP		 1699 /* Allow the ADC to stabilize for 4 microseconds before
1700 * starting the next (final) conversion. This delay is
1701 * necessary to allow sufficient time between last
1702 * conversion finished and the start of the next
1703 * conversion. Without this delay, the last conversion's
1704 * data value is sometimes set to the previous
1705 * conversion's data value.
1706 */
5f74ea14 1707 udelay(4);
11e865c1
GP		 1708 }
1709
b6c77757
BP		 1710 /* Start a dummy conversion to cause the data from the
1711 * previous conversion to be shifted in. */
11e865c1
GP		 1712 GpioImage = RR7146(P_GPIO);
1713
b6c77757 1714 /* Assert ADC Start command */
11e865c1 1715 WR7146(P_GPIO, GpioImage & ~GPIO1_HI);
b6c77757 1716 /* and stretch it out. */
11e865c1
GP		 1717 WR7146(P_GPIO, GpioImage & ~GPIO1_HI);
1718 WR7146(P_GPIO, GpioImage & ~GPIO1_HI);
b6c77757 1719 /* Negate ADC Start command. */
11e865c1
GP		 1720 WR7146(P_GPIO, GpioImage | GPIO1_HI);
1721
b6c77757 1722 /* Wait for the data to arrive in FB BUFFER 1 register. */
11e865c1 1723
b6c77757 1724 /* Wait for ADC done. */
add74595 1725 while (!(RR7146(P_PSR) & PSR_GPIO2))
ae6eb75c 1726 ;
11e865c1 1727
b6c77757 1728 /* Fetch ADC data from audio interface's input shift register. */
11e865c1 1729
b6c77757 1730 /* Fetch ADC data. */
11e865c1
GP		 1731 if (n != 0)
1732 data[n - 1] = s626_ai_reg_to_uint(RR7146(P_FB_BUFFER1));
1733
1734 DEBUG("s626_ai_insn_read: samples %d, data %d\n", n, data[n - 1]);
1735
1736 return n;
1737}
1738
add74595 1739static int s626_ai_load_polllist(uint8_t *ppl, struct comedi_cmd *cmd)
11e865c1
GP		 1740{
1741
1742 int n;
1743
1744 for (n = 0; n < cmd->chanlist_len; n++) {
1745 if (CR_RANGE((cmd->chanlist)[n]) == 0)
1746 ppl[n] = (CR_CHAN((cmd->chanlist)[n])) | (RANGE_5V);
1747 else
1748 ppl[n] = (CR_CHAN((cmd->chanlist)[n])) | (RANGE_10V);
1749 }
4ff863b1
RK		 1750 if (n != 0)
1751 ppl[n - 1] |= EOPL;
11e865c1
GP		 1752
1753 return n;
1754}
1755
0a85b6f0
MT		 1756static int s626_ai_inttrig(struct comedi_device *dev,
1757 struct comedi_subdevice *s, unsigned int trignum)
11e865c1
GP		 1758{
1759 if (trignum != 0)
1760 return -EINVAL;
1761
1762 DEBUG("s626_ai_inttrig: trigger adc start...");
1763
b6c77757 1764 /* Start executing the RPS program. */
11e865c1
GP		 1765 MC_ENABLE(P_MC1, MC1_ERPS1);
1766
1767 s->async->inttrig = NULL;
1768
1769 DEBUG(" done\n");
1770
1771 return 1;
1772}
1773
1774/* TO COMPLETE */
34c43922 1775static int s626_ai_cmd(struct comedi_device *dev, struct comedi_subdevice *s)
11e865c1
GP		 1776{
1777
1778 uint8_t ppl[16];
ea6d0d4c 1779 struct comedi_cmd *cmd = &s->async->cmd;
eb5e029e 1780 struct enc_private *k;
11e865c1
GP		 1781 int tick;
1782
1783 DEBUG("s626_ai_cmd: entering command function\n");
1784
1785 if (devpriv->ai_cmd_running) {
daca497d 1786 printk(KERN_ERR "s626_ai_cmd: Another ai_cmd is running %d\n",
0a85b6f0 1787 dev->minor);
11e865c1
GP		 1788 return -EBUSY;
1789 }
b6c77757 1790 /* disable interrupt */
11e865c1
GP		 1791 writel(0, devpriv->base_addr + P_IER);
1792
b6c77757 1793 /* clear interrupt request */
11e865c1
GP		 1794 writel(IRQ_RPS1 | IRQ_GPIO3, devpriv->base_addr + P_ISR);
1795
b6c77757 1796 /* clear any pending interrupt */
11e865c1 1797 s626_dio_clear_irq(dev);
b6c77757 1798 /* s626_enc_clear_irq(dev); */
11e865c1 1799
b6c77757 1800 /* reset ai_cmd_running flag */
11e865c1
GP		 1801 devpriv->ai_cmd_running = 0;
1802
b6c77757 1803 /* test if cmd is valid */
11e865c1
GP		 1804 if (cmd == NULL) {
1805 DEBUG("s626_ai_cmd: NULL command\n");
1806 return -EINVAL;
1807 } else {
25985edc 1808 DEBUG("s626_ai_cmd: command received!!!\n");
11e865c1
GP		 1809 }
1810
1811 if (dev->irq == 0) {
1812 comedi_error(dev,
0a85b6f0 1813 "s626_ai_cmd: cannot run command without an irq");
11e865c1
GP		 1814 return -EIO;
1815 }
1816
1817 s626_ai_load_polllist(ppl, cmd);
1818 devpriv->ai_cmd_running = 1;
1819 devpriv->ai_convert_count = 0;
1820
1821 switch (cmd->scan_begin_src) {
1822 case TRIG_FOLLOW:
1823 break;
1824 case TRIG_TIMER:
b6c77757 1825 /* set a conter to generate adc trigger at scan_begin_arg interval */
11e865c1
GP		 1826 k = &encpriv[5];
1827 tick = s626_ns_to_timer((int *)&cmd->scan_begin_arg,
0a85b6f0 1828 cmd->flags & TRIG_ROUND_MASK);
11e865c1 1829
b6c77757 1830 /* load timer value and enable interrupt */
11e865c1
GP		 1831 s626_timer_load(dev, k, tick);
1832 k->SetEnable(dev, k, CLKENAB_ALWAYS);
1833
1834 DEBUG("s626_ai_cmd: scan trigger timer is set with value %d\n",
0a85b6f0 1835 tick);
11e865c1
GP		 1836
1837 break;
1838 case TRIG_EXT:
b6c77757 1839 /* set the digital line and interrupt for scan trigger */
11e865c1
GP		 1840 if (cmd->start_src != TRIG_EXT)
1841 s626_dio_set_irq(dev, cmd->scan_begin_arg);
1842
1843 DEBUG("s626_ai_cmd: External scan trigger is set!!!\n");
1844
1845 break;
1846 }
1847
1848 switch (cmd->convert_src) {
1849 case TRIG_NOW:
1850 break;
1851 case TRIG_TIMER:
b6c77757 1852 /* set a conter to generate adc trigger at convert_arg interval */
11e865c1
GP		 1853 k = &encpriv[4];
1854 tick = s626_ns_to_timer((int *)&cmd->convert_arg,
0a85b6f0 1855 cmd->flags & TRIG_ROUND_MASK);
11e865c1 1856
b6c77757 1857 /* load timer value and enable interrupt */
11e865c1
GP		 1858 s626_timer_load(dev, k, tick);
1859 k->SetEnable(dev, k, CLKENAB_INDEX);
1860
0a85b6f0
MT		 1861 DEBUG
1862 ("s626_ai_cmd: convert trigger timer is set with value %d\n",
1863 tick);
11e865c1
GP		 1864 break;
1865 case TRIG_EXT:
b6c77757 1866 /* set the digital line and interrupt for convert trigger */
11e865c1 1867 if (cmd->scan_begin_src != TRIG_EXT
0a85b6f0 1868 && cmd->start_src == TRIG_EXT)
11e865c1
GP		 1869 s626_dio_set_irq(dev, cmd->convert_arg);
1870
1871 DEBUG("s626_ai_cmd: External convert trigger is set!!!\n");
1872
1873 break;
1874 }
1875
1876 switch (cmd->stop_src) {
1877 case TRIG_COUNT:
b6c77757 1878 /* data arrives as one packet */
11e865c1
GP		 1879 devpriv->ai_sample_count = cmd->stop_arg;
1880 devpriv->ai_continous = 0;
1881 break;
1882 case TRIG_NONE:
25985edc 1883 /* continous acquisition */
11e865c1
GP		 1884 devpriv->ai_continous = 1;
1885 devpriv->ai_sample_count = 0;
1886 break;
1887 }
1888
1889 ResetADC(dev, ppl);
1890
1891 switch (cmd->start_src) {
1892 case TRIG_NOW:
b6c77757
BP		 1893 /* Trigger ADC scan loop start by setting RPS Signal 0. */
1894 /* MC_ENABLE( P_MC2, MC2_ADC_RPS ); */
11e865c1 1895
b6c77757 1896 /* Start executing the RPS program. */
11e865c1
GP		 1897 MC_ENABLE(P_MC1, MC1_ERPS1);
1898
1899 DEBUG("s626_ai_cmd: ADC triggered\n");
1900 s->async->inttrig = NULL;
1901 break;
1902 case TRIG_EXT:
b6c77757 1903 /* configure DIO channel for acquisition trigger */
11e865c1
GP		 1904 s626_dio_set_irq(dev, cmd->start_arg);
1905
1906 DEBUG("s626_ai_cmd: External start trigger is set!!!\n");
1907
1908 s->async->inttrig = NULL;
1909 break;
1910 case TRIG_INT:
1911 s->async->inttrig = s626_ai_inttrig;
1912 break;
1913 }
1914
b6c77757 1915 /* enable interrupt */
11e865c1
GP		 1916 writel(IRQ_GPIO3 | IRQ_RPS1, devpriv->base_addr + P_IER);
1917
1918 DEBUG("s626_ai_cmd: command function terminated\n");
1919
1920 return 0;
1921}
1922
0a85b6f0
MT		 1923static int s626_ai_cmdtest(struct comedi_device *dev,
1924 struct comedi_subdevice *s, struct comedi_cmd *cmd)
11e865c1
GP		 1925{
1926 int err = 0;
1927 int tmp;
1928
1929 /* cmdtest tests a particular command to see if it is valid. Using
1930 * the cmdtest ioctl, a user can create a valid cmd and then have it
1931 * executes by the cmd ioctl.
1932 *
1933 * cmdtest returns 1,2,3,4 or 0, depending on which tests the
1934 * command passes. */
1935
1936 /* step 1: make sure trigger sources are trivially valid */
1937
1938 tmp = cmd->start_src;
1939 cmd->start_src &= TRIG_NOW | TRIG_INT | TRIG_EXT;
1940 if (!cmd->start_src || tmp != cmd->start_src)
1941 err++;
1942
1943 tmp = cmd->scan_begin_src;
1944 cmd->scan_begin_src &= TRIG_TIMER | TRIG_EXT | TRIG_FOLLOW;
1945 if (!cmd->scan_begin_src || tmp != cmd->scan_begin_src)
1946 err++;
1947
1948 tmp = cmd->convert_src;
1949 cmd->convert_src &= TRIG_TIMER | TRIG_EXT | TRIG_NOW;
1950 if (!cmd->convert_src || tmp != cmd->convert_src)
1951 err++;
1952
1953 tmp = cmd->scan_end_src;
1954 cmd->scan_end_src &= TRIG_COUNT;
1955 if (!cmd->scan_end_src || tmp != cmd->scan_end_src)
1956 err++;
1957
1958 tmp = cmd->stop_src;
1959 cmd->stop_src &= TRIG_COUNT | TRIG_NONE;
1960 if (!cmd->stop_src || tmp != cmd->stop_src)
1961 err++;
1962
1963 if (err)
1964 return 1;
1965
1966 /* step 2: make sure trigger sources are unique and mutually
1967 compatible */
1968
828684f9 1969 /* note that mutual compatibility is not an issue here */
11e865c1 1970 if (cmd->scan_begin_src != TRIG_TIMER &&
0a85b6f0
MT		 1971 cmd->scan_begin_src != TRIG_EXT
1972 && cmd->scan_begin_src != TRIG_FOLLOW)
11e865c1
GP		 1973 err++;
1974 if (cmd->convert_src != TRIG_TIMER &&
0a85b6f0 1975 cmd->convert_src != TRIG_EXT && cmd->convert_src != TRIG_NOW)
11e865c1
GP		 1976 err++;
1977 if (cmd->stop_src != TRIG_COUNT && cmd->stop_src != TRIG_NONE)
1978 err++;
1979
1980 if (err)
1981 return 2;
1982
1983 /* step 3: make sure arguments are trivially compatible */
1984
1985 if (cmd->start_src != TRIG_EXT && cmd->start_arg != 0) {
1986 cmd->start_arg = 0;
1987 err++;
1988 }
1989
11e865c1
GP		 1990 if (cmd->start_src == TRIG_EXT && cmd->start_arg > 39) {
1991 cmd->start_arg = 39;
1992 err++;
1993 }
1994
11e865c1
GP		 1995 if (cmd->scan_begin_src == TRIG_EXT && cmd->scan_begin_arg > 39) {
1996 cmd->scan_begin_arg = 39;
1997 err++;
1998 }
1999
11e865c1
GP		 2000 if (cmd->convert_src == TRIG_EXT && cmd->convert_arg > 39) {
2001 cmd->convert_arg = 39;
2002 err++;
2003 }
2004#define MAX_SPEED 200000 /* in nanoseconds */
2005#define MIN_SPEED 2000000000 /* in nanoseconds */
2006
2007 if (cmd->scan_begin_src == TRIG_TIMER) {
2008 if (cmd->scan_begin_arg < MAX_SPEED) {
2009 cmd->scan_begin_arg = MAX_SPEED;
2010 err++;
2011 }
2012 if (cmd->scan_begin_arg > MIN_SPEED) {
2013 cmd->scan_begin_arg = MIN_SPEED;
2014 err++;
2015 }
2016 } else {
2017 /* external trigger */
2018 /* should be level/edge, hi/lo specification here */
2019 /* should specify multiple external triggers */
2020/* if(cmd->scan_begin_arg>9){ */
2021/* cmd->scan_begin_arg=9; */
2022/* err++; */
2023/* } */
2024 }
2025 if (cmd->convert_src == TRIG_TIMER) {
2026 if (cmd->convert_arg < MAX_SPEED) {
2027 cmd->convert_arg = MAX_SPEED;
2028 err++;
2029 }
2030 if (cmd->convert_arg > MIN_SPEED) {
2031 cmd->convert_arg = MIN_SPEED;
2032 err++;
2033 }
2034 } else {
2035 /* external trigger */
2036 /* see above */
2037/* if(cmd->convert_arg>9){ */
2038/* cmd->convert_arg=9; */
2039/* err++; */
2040/* } */
2041 }
2042
2043 if (cmd->scan_end_arg != cmd->chanlist_len) {
2044 cmd->scan_end_arg = cmd->chanlist_len;
2045 err++;
2046 }
2047 if (cmd->stop_src == TRIG_COUNT) {
2048 if (cmd->stop_arg > 0x00ffffff) {
2049 cmd->stop_arg = 0x00ffffff;
2050 err++;
2051 }
2052 } else {
2053 /* TRIG_NONE */
2054 if (cmd->stop_arg != 0) {
2055 cmd->stop_arg = 0;
2056 err++;
2057 }
2058 }
2059
2060 if (err)
2061 return 3;
2062
2063 /* step 4: fix up any arguments */
2064
2065 if (cmd->scan_begin_src == TRIG_TIMER) {
2066 tmp = cmd->scan_begin_arg;
2067 s626_ns_to_timer((int *)&cmd->scan_begin_arg,
0a85b6f0 2068 cmd->flags & TRIG_ROUND_MASK);
11e865c1
GP		 2069 if (tmp != cmd->scan_begin_arg)
2070 err++;
2071 }
2072 if (cmd->convert_src == TRIG_TIMER) {
2073 tmp = cmd->convert_arg;
2074 s626_ns_to_timer((int *)&cmd->convert_arg,
0a85b6f0 2075 cmd->flags & TRIG_ROUND_MASK);
11e865c1
GP		 2076 if (tmp != cmd->convert_arg)
2077 err++;
2078 if (cmd->scan_begin_src == TRIG_TIMER &&
0a85b6f0
MT		 2079 cmd->scan_begin_arg <
2080 cmd->convert_arg * cmd->scan_end_arg) {
11e865c1 2081 cmd->scan_begin_arg =
0a85b6f0 2082 cmd->convert_arg * cmd->scan_end_arg;
11e865c1
GP		 2083 err++;
2084 }
2085 }
2086
2087 if (err)
2088 return 4;
2089
2090 return 0;
2091}
2092
34c43922 2093static int s626_ai_cancel(struct comedi_device *dev, struct comedi_subdevice *s)
11e865c1 2094{
b6c77757 2095 /* Stop RPS program in case it is currently running. */
11e865c1
GP		 2096 MC_DISABLE(P_MC1, MC1_ERPS1);
2097
b6c77757 2098 /* disable master interrupt */
11e865c1
GP		 2099 writel(0, devpriv->base_addr + P_IER);
2100
2101 devpriv->ai_cmd_running = 0;
2102
2103 return 0;
2104}
2105
2106/* This function doesn't require a particular form, this is just what
2107 * happens to be used in some of the drivers. It should convert ns
2108 * nanoseconds to a counter value suitable for programming the device.
2109 * Also, it should adjust ns so that it cooresponds to the actual time
2110 * that the device will use. */
2111static int s626_ns_to_timer(int *nanosec, int round_mode)
2112{
2113 int divider, base;
2114
b6c77757 2115 base = 500; /* 2MHz internal clock */
11e865c1
GP		 2116
2117 switch (round_mode) {
2118 case TRIG_ROUND_NEAREST:
2119 default:
2120 divider = (*nanosec + base / 2) / base;
2121 break;
2122 case TRIG_ROUND_DOWN:
2123 divider = (*nanosec) / base;
2124 break;
2125 case TRIG_ROUND_UP:
2126 divider = (*nanosec + base - 1) / base;
2127 break;
2128 }
2129
2130 *nanosec = base * divider;
2131 return divider - 1;
2132}
2133
34c43922 2134static int s626_ao_winsn(struct comedi_device *dev, struct comedi_subdevice *s,
0a85b6f0 2135 struct comedi_insn *insn, unsigned int *data)
11e865c1
GP		 2136{
2137
2138 int i;
2139 uint16_t chan = CR_CHAN(insn->chanspec);
2140 int16_t dacdata;
2141
2142 for (i = 0; i < insn->n; i++) {
2143 dacdata = (int16_t) data[i];
2144 devpriv->ao_readback[CR_CHAN(insn->chanspec)] = data[i];
2145 dacdata -= (0x1fff);
2146
2147 SetDAC(dev, chan, dacdata);
2148 }
2149
2150 return i;
2151}
2152
34c43922 2153static int s626_ao_rinsn(struct comedi_device *dev, struct comedi_subdevice *s,
0a85b6f0 2154 struct comedi_insn *insn, unsigned int *data)
11e865c1
GP		 2155{
2156 int i;
2157
82675f35 2158 for (i = 0; i < insn->n; i++)
11e865c1 2159 data[i] = devpriv->ao_readback[CR_CHAN(insn->chanspec)];
11e865c1
GP		 2160
2161 return i;
2162}
2163
b6c77757
BP		 2164/* *************** DIGITAL I/O FUNCTIONS ***************
2165 * All DIO functions address a group of DIO channels by means of
2166 * "group" argument. group may be 0, 1 or 2, which correspond to DIO
2167 * ports A, B and C, respectively.
2168 */
11e865c1 2169
71b5f4f1 2170static void s626_dio_init(struct comedi_device *dev)
11e865c1
GP		 2171{
2172 uint16_t group;
34c43922 2173 struct comedi_subdevice *s;
11e865c1 2174
b6c77757 2175 /* Prepare to treat writes to WRCapSel as capture disables. */
11e865c1
GP		 2176 DEBIwrite(dev, LP_MISC1, MISC1_NOEDCAP);
2177
b6c77757 2178 /* For each group of sixteen channels ... */
11e865c1
GP		 2179 for (group = 0; group < S626_DIO_BANKS; group++) {
2180 s = dev->subdevices + 2 + group;
b6c77757
BP		 2181 DEBIwrite(dev, diopriv->WRIntSel, 0); /* Disable all interrupts. */
2182 DEBIwrite(dev, diopriv->WRCapSel, 0xFFFF); /* Disable all event */
2183 /* captures. */
2184 DEBIwrite(dev, diopriv->WREdgSel, 0); /* Init all DIOs to */
2185 /* default edge */
2186 /* polarity. */
2187 DEBIwrite(dev, diopriv->WRDOut, 0); /* Program all outputs */
2188 /* to inactive state. */
11e865c1 2189 }
daca497d 2190 DEBUG("s626_dio_init: DIO initialized\n");
11e865c1
GP		 2191}
2192
2193/* DIO devices are slightly special. Although it is possible to
2194 * implement the insn_read/insn_write interface, it is much more
2195 * useful to applications if you implement the insn_bits interface.
2196 * This allows packed reading/writing of the DIO channels. The comedi
2197 * core can convert between insn_bits and insn_read/write */
2198
0a85b6f0
MT		 2199static int s626_dio_insn_bits(struct comedi_device *dev,
2200 struct comedi_subdevice *s,
2201 struct comedi_insn *insn, unsigned int *data)
11e865c1
GP		 2202{
2203
2204 /* Length of data must be 2 (mask and new data, see below) */
82675f35 2205 if (insn->n == 0)
11e865c1 2206 return 0;
82675f35 2207
11e865c1 2208 if (insn->n != 2) {
0a85b6f0
MT		 2209 printk
2210 ("comedi%d: s626: s626_dio_insn_bits(): Invalid instruction length\n",
2211 dev->minor);
11e865c1
GP		 2212 return -EINVAL;
2213 }
2214
2215 /*
2216 * The insn data consists of a mask in data[0] and the new data in
2217 * data[1]. The mask defines which bits we are concerning about.
2218 * The new data must be anded with the mask. Each channel
2219 * corresponds to a bit.
2220 */
2221 if (data[0]) {
2222 /* Check if requested ports are configured for output */
2223 if ((s->io_bits & data[0]) != data[0])
2224 return -EIO;
2225
2226 s->state &= ~data[0];
2227 s->state |= data[0] & data[1];
2228
2229 /* Write out the new digital output lines */
2230
2231 DEBIwrite(dev, diopriv->WRDOut, s->state);
2232 }
2233 data[1] = DEBIread(dev, diopriv->RDDIn);
2234
2235 return 2;
2236}
2237
0a85b6f0
MT		 2238static int s626_dio_insn_config(struct comedi_device *dev,
2239 struct comedi_subdevice *s,
2240 struct comedi_insn *insn, unsigned int *data)
11e865c1
GP		 2241{
2242
2243 switch (data[0]) {
2244 case INSN_CONFIG_DIO_QUERY:
2245 data[1] =
0a85b6f0
MT		 2246 (s->
2247 io_bits & (1 << CR_CHAN(insn->chanspec))) ? COMEDI_OUTPUT :
2248 COMEDI_INPUT;
11e865c1
GP		 2249 return insn->n;
2250 break;
2251 case COMEDI_INPUT:
2252 s->io_bits &= ~(1 << CR_CHAN(insn->chanspec));
2253 break;
2254 case COMEDI_OUTPUT:
2255 s->io_bits |= 1 << CR_CHAN(insn->chanspec);
2256 break;
2257 default:
2258 return -EINVAL;
2259 break;
2260 }
2261 DEBIwrite(dev, diopriv->WRDOut, s->io_bits);
2262
2263 return 1;
2264}
2265
71b5f4f1 2266static int s626_dio_set_irq(struct comedi_device *dev, unsigned int chan)
11e865c1
GP		 2267{
2268 unsigned int group;
2269 unsigned int bitmask;
2270 unsigned int status;
2271
b6c77757 2272 /* select dio bank */
11e865c1
GP		 2273 group = chan / 16;
2274 bitmask = 1 << (chan - (16 * group));
2275 DEBUG("s626_dio_set_irq: enable interrupt on dio channel %d group %d\n",
0a85b6f0 2276 chan - (16 * group), group);
11e865c1 2277
b6c77757 2278 /* set channel to capture positive edge */
11e865c1 2279 status = DEBIread(dev,
0a85b6f0
MT		 2280 ((struct dio_private *)(dev->subdevices + 2 +
2281 group)->private)->RDEdgSel);
11e865c1 2282 DEBIwrite(dev,
0a85b6f0
MT		 2283 ((struct dio_private *)(dev->subdevices + 2 +
2284 group)->private)->WREdgSel,
2285 bitmask | status);
11e865c1 2286
b6c77757 2287 /* enable interrupt on selected channel */
11e865c1 2288 status = DEBIread(dev,
0a85b6f0
MT		 2289 ((struct dio_private *)(dev->subdevices + 2 +
2290 group)->private)->RDIntSel);
11e865c1 2291 DEBIwrite(dev,
0a85b6f0
MT		 2292 ((struct dio_private *)(dev->subdevices + 2 +
2293 group)->private)->WRIntSel,
2294 bitmask | status);
11e865c1 2295
b6c77757 2296 /* enable edge capture write command */
11e865c1
GP		 2297 DEBIwrite(dev, LP_MISC1, MISC1_EDCAP);
2298
b6c77757 2299 /* enable edge capture on selected channel */
11e865c1 2300 status = DEBIread(dev,
0a85b6f0
MT		 2301 ((struct dio_private *)(dev->subdevices + 2 +
2302 group)->private)->RDCapSel);
11e865c1 2303 DEBIwrite(dev,
0a85b6f0
MT		 2304 ((struct dio_private *)(dev->subdevices + 2 +
2305 group)->private)->WRCapSel,
2306 bitmask | status);
11e865c1
GP		 2307
2308 return 0;
2309}
2310
71b5f4f1 2311static int s626_dio_reset_irq(struct comedi_device *dev, unsigned int group,
0a85b6f0 2312 unsigned int mask)
11e865c1 2313{
0a85b6f0
MT		 2314 DEBUG
2315 ("s626_dio_reset_irq: disable interrupt on dio channel %d group %d\n",
2316 mask, group);
11e865c1 2317
b6c77757 2318 /* disable edge capture write command */
11e865c1
GP		 2319 DEBIwrite(dev, LP_MISC1, MISC1_NOEDCAP);
2320
b6c77757 2321 /* enable edge capture on selected channel */
11e865c1 2322 DEBIwrite(dev,
0a85b6f0
MT		 2323 ((struct dio_private *)(dev->subdevices + 2 +
2324 group)->private)->WRCapSel, mask);
11e865c1
GP		 2325
2326 return 0;
2327}
2328
71b5f4f1 2329static int s626_dio_clear_irq(struct comedi_device *dev)
11e865c1
GP		 2330{
2331 unsigned int group;
2332
b6c77757 2333 /* disable edge capture write command */
11e865c1
GP		 2334 DEBIwrite(dev, LP_MISC1, MISC1_NOEDCAP);
2335
2336 for (group = 0; group < S626_DIO_BANKS; group++) {
b6c77757 2337 /* clear pending events and interrupt */
11e865c1 2338 DEBIwrite(dev,
0a85b6f0
MT		 2339 ((struct dio_private *)(dev->subdevices + 2 +
2340 group)->private)->WRCapSel,
2341 0xffff);
11e865c1
GP		 2342 }
2343
2344 return 0;
2345}
2346
2347/* Now this function initializes the value of the counter (data[0])
2348 and set the subdevice. To complete with trigger and interrupt
2349 configuration */
0a85b6f0
MT		 2350static int s626_enc_insn_config(struct comedi_device *dev,
2351 struct comedi_subdevice *s,
2352 struct comedi_insn *insn, unsigned int *data)
11e865c1 2353{
b6c77757 2354 uint16_t Setup = (LOADSRC_INDX << BF_LOADSRC) | /* Preload upon */
0a85b6f0
MT		 2355 /* index. */
2356 (INDXSRC_SOFT << BF_INDXSRC) | /* Disable hardware index. */
2357 (CLKSRC_COUNTER << BF_CLKSRC) | /* Operating mode is Counter. */
2358 (CLKPOL_POS << BF_CLKPOL) | /* Active high clock. */
2359 /* ( CNTDIR_UP << BF_CLKPOL ) | // Count direction is Down. */
2360 (CLKMULT_1X << BF_CLKMULT) | /* Clock multiplier is 1x. */
2361 (CLKENAB_INDEX << BF_CLKENAB);
11e865c1 2362 /* uint16_t DisableIntSrc=TRUE; */
b6c77757 2363 /* uint32_t Preloadvalue; //Counter initial value */
11e865c1
GP		 2364 uint16_t valueSrclatch = LATCHSRC_AB_READ;
2365 uint16_t enab = CLKENAB_ALWAYS;
eb5e029e 2366 struct enc_private *k = &encpriv[CR_CHAN(insn->chanspec)];
11e865c1
GP		 2367
2368 DEBUG("s626_enc_insn_config: encoder config\n");
2369
b6c77757 2370 /* (data==NULL) ? (Preloadvalue=0) : (Preloadvalue=data[0]); */
11e865c1
GP		 2371
2372 k->SetMode(dev, k, Setup, TRUE);
2373 Preload(dev, k, *(insn->data));
2374 k->PulseIndex(dev, k);
2375 SetLatchSource(dev, k, valueSrclatch);
2376 k->SetEnable(dev, k, (uint16_t) (enab != 0));
2377
2378 return insn->n;
2379}
2380
0a85b6f0
MT		 2381static int s626_enc_insn_read(struct comedi_device *dev,
2382 struct comedi_subdevice *s,
2383 struct comedi_insn *insn, unsigned int *data)
11e865c1
GP		 2384{
2385
2386 int n;
eb5e029e 2387 struct enc_private *k = &encpriv[CR_CHAN(insn->chanspec)];
11e865c1 2388
daca497d 2389 DEBUG("s626_enc_insn_read: encoder read channel %d\n",
0a85b6f0 2390 CR_CHAN(insn->chanspec));
11e865c1
GP		 2391
2392 for (n = 0; n < insn->n; n++)
2393 data[n] = ReadLatch(dev, k);
2394
2395 DEBUG("s626_enc_insn_read: encoder sample %d\n", data[n]);
2396
2397 return n;
2398}
2399
0a85b6f0
MT		 2400static int s626_enc_insn_write(struct comedi_device *dev,
2401 struct comedi_subdevice *s,
2402 struct comedi_insn *insn, unsigned int *data)
11e865c1
GP		 2403{
2404
eb5e029e 2405 struct enc_private *k = &encpriv[CR_CHAN(insn->chanspec)];
11e865c1 2406
daca497d 2407 DEBUG("s626_enc_insn_write: encoder write channel %d\n",
0a85b6f0 2408 CR_CHAN(insn->chanspec));
11e865c1 2409
b6c77757 2410 /* Set the preload register */
11e865c1
GP		 2411 Preload(dev, k, data[0]);
2412
b6c77757
BP		 2413 /* Software index pulse forces the preload register to load */
2414 /* into the counter */
11e865c1
GP		 2415 k->SetLoadTrig(dev, k, 0);
2416 k->PulseIndex(dev, k);
2417 k->SetLoadTrig(dev, k, 2);
2418
2419 DEBUG("s626_enc_insn_write: End encoder write\n");
2420
2421 return 1;
2422}
2423
0a85b6f0
MT		 2424static void s626_timer_load(struct comedi_device *dev, struct enc_private *k,
2425 int tick)
11e865c1 2426{
b6c77757 2427 uint16_t Setup = (LOADSRC_INDX << BF_LOADSRC) | /* Preload upon */
0a85b6f0
MT		 2428 /* index. */
2429 (INDXSRC_SOFT << BF_INDXSRC) | /* Disable hardware index. */
2430 (CLKSRC_TIMER << BF_CLKSRC) | /* Operating mode is Timer. */
2431 (CLKPOL_POS << BF_CLKPOL) | /* Active high clock. */
2432 (CNTDIR_DOWN << BF_CLKPOL) | /* Count direction is Down. */
2433 (CLKMULT_1X << BF_CLKMULT) | /* Clock multiplier is 1x. */
2434 (CLKENAB_INDEX << BF_CLKENAB);
11e865c1 2435 uint16_t valueSrclatch = LATCHSRC_A_INDXA;
b6c77757 2436 /* uint16_t enab=CLKENAB_ALWAYS; */
11e865c1
GP		 2437
2438 k->SetMode(dev, k, Setup, FALSE);
2439
b6c77757 2440 /* Set the preload register */
11e865c1
GP		 2441 Preload(dev, k, tick);
2442
b6c77757
BP		 2443 /* Software index pulse forces the preload register to load */
2444 /* into the counter */
11e865c1
GP		 2445 k->SetLoadTrig(dev, k, 0);
2446 k->PulseIndex(dev, k);
2447
b6c77757 2448 /* set reload on counter overflow */
11e865c1
GP		 2449 k->SetLoadTrig(dev, k, 1);
2450
b6c77757 2451 /* set interrupt on overflow */
11e865c1
GP		 2452 k->SetIntSrc(dev, k, INTSRC_OVER);
2453
2454 SetLatchSource(dev, k, valueSrclatch);
b6c77757 2455 /* k->SetEnable(dev,k,(uint16_t)(enab != 0)); */
11e865c1
GP		 2456}
2457
b6c77757 2458/* *********** DAC FUNCTIONS *********** */
11e865c1 2459
b6c77757 2460/* Slot 0 base settings. */
6a98d36e 2461#define VECT0 (XSD2 | RSD3 | SIB_A2)
b6c77757 2462/* Slot 0 always shifts in 0xFF and store it to FB_BUFFER2. */
11e865c1 2463
b6c77757 2464/* TrimDac LogicalChan-to-PhysicalChan mapping table. */
11e865c1
GP		 2465static uint8_t trimchan[] = { 10, 9, 8, 3, 2, 7, 6, 1, 0, 5, 4 };
2466
b6c77757 2467/* TrimDac LogicalChan-to-EepromAdrs mapping table. */
add74595 2468static uint8_t trimadrs[] = { 0x40, 0x41, 0x42, 0x50, 0x51, 0x52, 0x53, 0x60, 0x61, 0x62, 0x63 };
11e865c1 2469
71b5f4f1 2470static void LoadTrimDACs(struct comedi_device *dev)
11e865c1
GP		 2471{
2472 register uint8_t i;
2473
b6c77757 2474 /* Copy TrimDac setpoint values from EEPROM to TrimDacs. */
8629efa4 2475 for (i = 0; i < ARRAY_SIZE(trimchan); i++)
11e865c1
GP		 2476 WriteTrimDAC(dev, i, I2Cread(dev, trimadrs[i]));
2477}
2478
71b5f4f1 2479static void WriteTrimDAC(struct comedi_device *dev, uint8_t LogicalChan,
0a85b6f0 2480 uint8_t DacData)
11e865c1
GP		 2481{
2482 uint32_t chan;
2483
b6c77757 2484 /* Save the new setpoint in case the application needs to read it back later. */
11e865c1
GP		 2485 devpriv->TrimSetpoint[LogicalChan] = (uint8_t) DacData;
2486
b6c77757 2487 /* Map logical channel number to physical channel number. */
11e865c1
GP		 2488 chan = (uint32_t) trimchan[LogicalChan];
2489
b6c77757
BP		 2490 /* Set up TSL2 records for TrimDac write operation. All slots shift
2491 * 0xFF in from pulled-up SD3 so that the end of the slot sequence
2492 * can be detected.
2493 */
2494
2495 SETVECT(2, XSD2 | XFIFO_1 | WS3);
2496 /* Slot 2: Send high uint8_t to target TrimDac. */
2497 SETVECT(3, XSD2 | XFIFO_0 | WS3);
2498 /* Slot 3: Send low uint8_t to target TrimDac. */
2499 SETVECT(4, XSD2 | XFIFO_3 | WS1);
2500 /* Slot 4: Send NOP high uint8_t to DAC0 to keep clock running. */
2501 SETVECT(5, XSD2 | XFIFO_2 | WS1 | EOS);
2502 /* Slot 5: Send NOP low uint8_t to DAC0. */
2503
2504 /* Construct and transmit target DAC's serial packet:
2505 * ( 0000 AAAA ), ( DDDD DDDD ),( 0x00 ),( 0x00 ) where A<3:0> is the
2506 * DAC channel's address, and D<7:0> is the DAC setpoint. Append a
2507 * WORD value (that writes a channel 0 NOP command to a non-existent
2508 * main DAC channel) that serves to keep the clock running after the
2509 * packet has been sent to the target DAC.
2510 */
11e865c1 2511
b6c77757
BP		 2512 /* Address the DAC channel within the trimdac device. */
2513 SendDAC(dev, ((uint32_t) chan << 8)
2514 | (uint32_t) DacData); /* Include DAC setpoint data. */
2515}
11e865c1 2516
b6c77757
BP		 2517/* ************** EEPROM ACCESS FUNCTIONS ************** */
2518/* Read uint8_t from EEPROM. */
11e865c1 2519
71b5f4f1 2520static uint8_t I2Cread(struct comedi_device *dev, uint8_t addr)
11e865c1
GP		 2521{
2522 uint8_t rtnval;
2523
b6c77757
BP		 2524 /* Send EEPROM target address. */
2525 if (I2Chandshake(dev, I2C_B2(I2C_ATTRSTART, I2CW)
2526 /* Byte2 = I2C command: write to I2C EEPROM device. */
0a85b6f0 2527 | I2C_B1(I2C_ATTRSTOP, addr)
b6c77757 2528 /* Byte1 = EEPROM internal target address. */
0a85b6f0 2529 | I2C_B0(I2C_ATTRNOP, 0))) { /* Byte0 = Not sent. */
b6c77757 2530 /* Abort function and declare error if handshake failed. */
11e865c1
GP		 2531 DEBUG("I2Cread: error handshake I2Cread a\n");
2532 return 0;
2533 }
b6c77757 2534 /* Execute EEPROM read. */
0a85b6f0
MT		 2535 if (I2Chandshake(dev, I2C_B2(I2C_ATTRSTART, I2CR)
2536
2537 /* Byte2 = I2C */
2538 /* command: read */
2539 /* from I2C EEPROM */
2540 /* device. */
2541 |I2C_B1(I2C_ATTRSTOP, 0)
2542
2543 /* Byte1 receives */
2544 /* uint8_t from */
2545 /* EEPROM. */
2546 |I2C_B0(I2C_ATTRNOP, 0))) { /* Byte0 = Not sent. */
f10fe574 2547
b6c77757 2548 /* Abort function and declare error if handshake failed. */
11e865c1
GP		 2549 DEBUG("I2Cread: error handshake I2Cread b\n");
2550 return 0;
2551 }
b6c77757 2552 /* Return copy of EEPROM value. */
11e865c1
GP		 2553 rtnval = (uint8_t) (RR7146(P_I2CCTRL) >> 16);
2554 return rtnval;
2555}
2556
71b5f4f1 2557static uint32_t I2Chandshake(struct comedi_device *dev, uint32_t val)
11e865c1 2558{
b6c77757 2559 /* Write I2C command to I2C Transfer Control shadow register. */
11e865c1
GP		 2560 WR7146(P_I2CCTRL, val);
2561
b6c77757
BP		 2562 /* Upload I2C shadow registers into working registers and wait for */
2563 /* upload confirmation. */
11e865c1
GP		 2564
2565 MC_ENABLE(P_MC2, MC2_UPLD_IIC);
add74595 2566 while (!MC_TEST(P_MC2, MC2_UPLD_IIC))
ae6eb75c 2567 ;
11e865c1 2568
b6c77757 2569 /* Wait until I2C bus transfer is finished or an error occurs. */
add74595 2570 while ((RR7146(P_I2CCTRL) & (I2C_BUSY | I2C_ERR)) == I2C_BUSY)
ae6eb75c 2571 ;
11e865c1 2572
25985edc 2573 /* Return non-zero if I2C error occurred. */
11e865c1
GP		 2574 return RR7146(P_I2CCTRL) & I2C_ERR;
2575
2576}
2577
b6c77757 2578/* Private helper function: Write setpoint to an application DAC channel. */
11e865c1 2579
71b5f4f1 2580static void SetDAC(struct comedi_device *dev, uint16_t chan, short dacdata)
11e865c1
GP		 2581{
2582 register uint16_t signmask;
2583 register uint32_t WSImage;
2584
b6c77757
BP		 2585 /* Adjust DAC data polarity and set up Polarity Control Register */
2586 /* image. */
11e865c1
GP		 2587 signmask = 1 << chan;
2588 if (dacdata < 0) {
2589 dacdata = -dacdata;
2590 devpriv->Dacpol |= signmask;
2591 } else
2592 devpriv->Dacpol &= ~signmask;
2593
b6c77757 2594 /* Limit DAC setpoint value to valid range. */
11e865c1
GP		 2595 if ((uint16_t) dacdata > 0x1FFF)
2596 dacdata = 0x1FFF;
2597
b6c77757
BP		 2598 /* Set up TSL2 records (aka "vectors") for DAC update. Vectors V2
2599 * and V3 transmit the setpoint to the target DAC. V4 and V5 send
2600 * data to a non-existent TrimDac channel just to keep the clock
2601 * running after sending data to the target DAC. This is necessary
2602 * to eliminate the clock glitch that would otherwise occur at the
2603 * end of the target DAC's serial data stream. When the sequence
2604 * restarts at V0 (after executing V5), the gate array automatically
2605 * disables gating for the DAC clock and all DAC chip selects.
2606 */
2607
2608 WSImage = (chan & 2) ? WS1 : WS2;
2609 /* Choose DAC chip select to be asserted. */
2610 SETVECT(2, XSD2 | XFIFO_1 | WSImage);
2611 /* Slot 2: Transmit high data byte to target DAC. */
2612 SETVECT(3, XSD2 | XFIFO_0 | WSImage);
2613 /* Slot 3: Transmit low data byte to target DAC. */
2614 SETVECT(4, XSD2 | XFIFO_3 | WS3);
2615 /* Slot 4: Transmit to non-existent TrimDac channel to keep clock */
2616 SETVECT(5, XSD2 | XFIFO_2 | WS3 | EOS);
2617 /* Slot 5: running after writing target DAC's low data byte. */
2618
2619 /* Construct and transmit target DAC's serial packet:
2620 * ( A10D DDDD ),( DDDD DDDD ),( 0x0F ),( 0x00 ) where A is chan<0>,
2621 * and D<12:0> is the DAC setpoint. Append a WORD value (that writes
2622 * to a non-existent TrimDac channel) that serves to keep the clock
2623 * running after the packet has been sent to the target DAC.
2624 */
2625 SendDAC(dev, 0x0F000000
2626 /* Continue clock after target DAC data (write to non-existent trimdac). */
2627 | 0x00004000
2628 /* Address the two main dual-DAC devices (TSL's chip select enables
2629 * target device). */
2630 | ((uint32_t) (chan & 1) << 15)
2631 /* Address the DAC channel within the device. */
2632 | (uint32_t) dacdata); /* Include DAC setpoint data. */
11e865c1
GP		 2633
2634}
2635
b6c77757
BP		 2636/* Private helper function: Transmit serial data to DAC via Audio
2637 * channel 2. Assumes: (1) TSL2 slot records initialized, and (2)
2638 * Dacpol contains valid target image.
2639 */
11e865c1 2640
71b5f4f1 2641static void SendDAC(struct comedi_device *dev, uint32_t val)
11e865c1
GP		 2642{
2643
b6c77757 2644 /* START THE SERIAL CLOCK RUNNING ------------- */
11e865c1 2645
b6c77757
BP		 2646 /* Assert DAC polarity control and enable gating of DAC serial clock
2647 * and audio bit stream signals. At this point in time we must be
2648 * assured of being in time slot 0. If we are not in slot 0, the
2649 * serial clock and audio stream signals will be disabled; this is
2650 * because the following DEBIwrite statement (which enables signals
2651 * to be passed through the gate array) would execute before the
2652 * trailing edge of WS1/WS3 (which turns off the signals), thus
2653 * causing the signals to be inactive during the DAC write.
2654 */
11e865c1
GP		 2655 DEBIwrite(dev, LP_DACPOL, devpriv->Dacpol);
2656
b6c77757 2657 /* TRANSFER OUTPUT DWORD VALUE INTO A2'S OUTPUT FIFO ---------------- */
11e865c1 2658
b6c77757 2659 /* Copy DAC setpoint value to DAC's output DMA buffer. */
11e865c1 2660
b6c77757 2661 /* WR7146( (uint32_t)devpriv->pDacWBuf, val ); */
11e865c1
GP		 2662 *devpriv->pDacWBuf = val;
2663
b6c77757
BP		 2664 /* enab the output DMA transfer. This will cause the DMAC to copy
2665 * the DAC's data value to A2's output FIFO. The DMA transfer will
2666 * then immediately terminate because the protection address is
2667 * reached upon transfer of the first DWORD value.
2668 */
11e865c1
GP		 2669 MC_ENABLE(P_MC1, MC1_A2OUT);
2670
b6c77757 2671 /* While the DMA transfer is executing ... */
11e865c1 2672
b6c77757
BP		 2673 /* Reset Audio2 output FIFO's underflow flag (along with any other
2674 * FIFO underflow/overflow flags). When set, this flag will
2675 * indicate that we have emerged from slot 0.
2676 */
11e865c1
GP		 2677 WR7146(P_ISR, ISR_AFOU);
2678
b6c77757
BP		 2679 /* Wait for the DMA transfer to finish so that there will be data
2680 * available in the FIFO when time slot 1 tries to transfer a DWORD
2681 * from the FIFO to the output buffer register. We test for DMA
2682 * Done by polling the DMAC enable flag; this flag is automatically
2683 * cleared when the transfer has finished.
2684 */
add74595 2685 while ((RR7146(P_MC1) & MC1_A2OUT) != 0)
ae6eb75c 2686 ;
11e865c1 2687
b6c77757 2688 /* START THE OUTPUT STREAM TO THE TARGET DAC -------------------- */
11e865c1 2689
b6c77757
BP		 2690 /* FIFO data is now available, so we enable execution of time slots
2691 * 1 and higher by clearing the EOS flag in slot 0. Note that SD3
2692 * will be shifted in and stored in FB_BUFFER2 for end-of-slot-list
2693 * detection.
2694 */
11e865c1
GP		 2695 SETVECT(0, XSD2 | RSD3 | SIB_A2);
2696
b6c77757
BP		 2697 /* Wait for slot 1 to execute to ensure that the Packet will be
2698 * transmitted. This is detected by polling the Audio2 output FIFO
2699 * underflow flag, which will be set when slot 1 execution has
2700 * finished transferring the DAC's data DWORD from the output FIFO
2701 * to the output buffer register.
2702 */
add74595 2703 while ((RR7146(P_SSR) & SSR_AF2_OUT) == 0)
ae6eb75c 2704 ;
11e865c1 2705
b6c77757
BP		 2706 /* Set up to trap execution at slot 0 when the TSL sequencer cycles
2707 * back to slot 0 after executing the EOS in slot 5. Also,
2708 * simultaneously shift out and in the 0x00 that is ALWAYS the value
2709 * stored in the last byte to be shifted out of the FIFO's DWORD
2710 * buffer register.
2711 */
11e865c1
GP		 2712 SETVECT(0, XSD2 | XFIFO_2 | RSD2 | SIB_A2 | EOS);
2713
b6c77757
BP		 2714 /* WAIT FOR THE TRANSACTION TO FINISH ----------------------- */
2715
2716 /* Wait for the TSL to finish executing all time slots before
2717 * exiting this function. We must do this so that the next DAC
2718 * write doesn't start, thereby enabling clock/chip select signals:
2719 *
2720 * 1. Before the TSL sequence cycles back to slot 0, which disables
2721 * the clock/cs signal gating and traps slot // list execution.
2722 * we have not yet finished slot 5 then the clock/cs signals are
2723 * still gated and we have not finished transmitting the stream.
2724 *
2725 * 2. While slots 2-5 are executing due to a late slot 0 trap. In
2726 * this case, the slot sequence is currently repeating, but with
2727 * clock/cs signals disabled. We must wait for slot 0 to trap
2728 * execution before setting up the next DAC setpoint DMA transfer
2729 * and enabling the clock/cs signals. To detect the end of slot 5,
2730 * we test for the FB_BUFFER2 MSB contents to be equal to 0xFF. If
2731 * the TSL has not yet finished executing slot 5 ...
2732 */
11e865c1 2733 if ((RR7146(P_FB_BUFFER2) & 0xFF000000) != 0) {
b6c77757
BP		 2734 /* The trap was set on time and we are still executing somewhere
2735 * in slots 2-5, so we now wait for slot 0 to execute and trap
2736 * TSL execution. This is detected when FB_BUFFER2 MSB changes
2737 * from 0xFF to 0x00, which slot 0 causes to happen by shifting
2738 * out/in on SD2 the 0x00 that is always referenced by slot 5.
2739 */
add74595 2740 while ((RR7146(P_FB_BUFFER2) & 0xFF000000) != 0)
ae6eb75c 2741 ;
11e865c1 2742 }
b6c77757
BP		 2743 /* Either (1) we were too late setting the slot 0 trap; the TSL
2744 * sequencer restarted slot 0 before we could set the EOS trap flag,
2745 * or (2) we were not late and execution is now trapped at slot 0.
2746 * In either case, we must now change slot 0 so that it will store
2747 * value 0xFF (instead of 0x00) to FB_BUFFER2 next time it executes.
2748 * In order to do this, we reprogram slot 0 so that it will shift in
2749 * SD3, which is driven only by a pull-up resistor.
2750 */
11e865c1
GP		 2751 SETVECT(0, RSD3 | SIB_A2 | EOS);
2752
b6c77757
BP		 2753 /* Wait for slot 0 to execute, at which time the TSL is setup for
2754 * the next DAC write. This is detected when FB_BUFFER2 MSB changes
2755 * from 0x00 to 0xFF.
2756 */
add74595 2757 while ((RR7146(P_FB_BUFFER2) & 0xFF000000) == 0)
ae6eb75c 2758 ;
11e865c1
GP		 2759}
2760
71b5f4f1 2761static void WriteMISC2(struct comedi_device *dev, uint16_t NewImage)
11e865c1 2762{
b6c77757
BP		 2763 DEBIwrite(dev, LP_MISC1, MISC1_WENABLE); /* enab writes to */
2764 /* MISC2 register. */
2765 DEBIwrite(dev, LP_WRMISC2, NewImage); /* Write new image to MISC2. */
2766 DEBIwrite(dev, LP_MISC1, MISC1_WDISABLE); /* Disable writes to MISC2. */
11e865c1
GP		 2767}
2768
b6c77757 2769/* Initialize the DEBI interface for all transfers. */
11e865c1 2770
71b5f4f1 2771static uint16_t DEBIread(struct comedi_device *dev, uint16_t addr)
11e865c1
GP		 2772{
2773 uint16_t retval;
2774
b6c77757 2775 /* Set up DEBI control register value in shadow RAM. */
11e865c1
GP		 2776 WR7146(P_DEBICMD, DEBI_CMD_RDWORD | addr);
2777
b6c77757 2778 /* Execute the DEBI transfer. */
11e865c1
GP		 2779 DEBItransfer(dev);
2780
b6c77757 2781 /* Fetch target register value. */
11e865c1
GP		 2782 retval = (uint16_t) RR7146(P_DEBIAD);
2783
b6c77757 2784 /* Return register value. */
11e865c1
GP		 2785 return retval;
2786}
2787
b6c77757
BP		 2788/* Execute a DEBI transfer. This must be called from within a */
2789/* critical section. */
71b5f4f1 2790static void DEBItransfer(struct comedi_device *dev)
11e865c1 2791{
b6c77757 2792 /* Initiate upload of shadow RAM to DEBI control register. */
11e865c1
GP		 2793 MC_ENABLE(P_MC2, MC2_UPLD_DEBI);
2794
b6c77757
BP		 2795 /* Wait for completion of upload from shadow RAM to DEBI control */
2796 /* register. */
add74595 2797 while (!MC_TEST(P_MC2, MC2_UPLD_DEBI))
ae6eb75c 2798 ;
11e865c1 2799
b6c77757 2800 /* Wait until DEBI transfer is done. */
add74595 2801 while (RR7146(P_PSR) & PSR_DEBI_S)
ae6eb75c 2802 ;
11e865c1
GP		 2803}
2804
b6c77757 2805/* Write a value to a gate array register. */
71b5f4f1 2806static void DEBIwrite(struct comedi_device *dev, uint16_t addr, uint16_t wdata)
11e865c1
GP		 2807{
2808
b6c77757 2809 /* Set up DEBI control register value in shadow RAM. */
11e865c1
GP		 2810 WR7146(P_DEBICMD, DEBI_CMD_WRWORD | addr);
2811 WR7146(P_DEBIAD, wdata);
2812
b6c77757 2813 /* Execute the DEBI transfer. */
11e865c1
GP		 2814 DEBItransfer(dev);
2815}
2816
b6c77757
BP		 2817/* Replace the specified bits in a gate array register. Imports: mask
2818 * specifies bits that are to be preserved, wdata is new value to be
2819 * or'd with the masked original.
2820 */
71b5f4f1 2821static void DEBIreplace(struct comedi_device *dev, uint16_t addr, uint16_t mask,
0a85b6f0 2822 uint16_t wdata)
11e865c1
GP		 2823{
2824
b6c77757
BP		 2825 /* Copy target gate array register into P_DEBIAD register. */
2826 WR7146(P_DEBICMD, DEBI_CMD_RDWORD | addr);
2827 /* Set up DEBI control reg value in shadow RAM. */
2828 DEBItransfer(dev); /* Execute the DEBI Read transfer. */
11e865c1 2829
b6c77757
BP		 2830 /* Write back the modified image. */
2831 WR7146(P_DEBICMD, DEBI_CMD_WRWORD | addr);
2832 /* Set up DEBI control reg value in shadow RAM. */
11e865c1 2833
b6c77757
BP		 2834 WR7146(P_DEBIAD, wdata | ((uint16_t) RR7146(P_DEBIAD) & mask));
2835 /* Modify the register image. */
2836 DEBItransfer(dev); /* Execute the DEBI Write transfer. */
11e865c1
GP		 2837}
2838
0a85b6f0
MT		 2839static void CloseDMAB(struct comedi_device *dev, struct bufferDMA *pdma,
2840 size_t bsize)
11e865c1
GP		 2841{
2842 void *vbptr;
2843 dma_addr_t vpptr;
2844
2845 DEBUG("CloseDMAB: Entering S626DRV_CloseDMAB():\n");
2846 if (pdma == NULL)
2847 return;
b6c77757 2848 /* find the matching allocation from the board struct */
11e865c1
GP		 2849
2850 vbptr = pdma->LogicalBase;
2851 vpptr = pdma->PhysicalBase;
2852 if (vbptr) {
2853 pci_free_consistent(devpriv->pdev, bsize, vbptr, vpptr);
2854 pdma->LogicalBase = 0;
2855 pdma->PhysicalBase = 0;
2856
2857 DEBUG("CloseDMAB(): Logical=%p, bsize=%d, Physical=0x%x\n",
0a85b6f0 2858 vbptr, bsize, (uint32_t) vpptr);
11e865c1
GP		 2859 }
2860}
2861
b6c77757
BP		 2862/* ****** COUNTER FUNCTIONS ******* */
2863/* All counter functions address a specific counter by means of the
2864 * "Counter" argument, which is a logical counter number. The Counter
2865 * argument may have any of the following legal values: 0=0A, 1=1A,
2866 * 2=2A, 3=0B, 4=1B, 5=2B.
2867 */
11e865c1 2868
b6c77757 2869/* Forward declarations for functions that are common to both A and B counters: */
11e865c1 2870
b6c77757 2871/* ****** PRIVATE COUNTER FUNCTIONS ****** */
11e865c1 2872
b6c77757 2873/* Read a counter's output latch. */
11e865c1 2874
71b5f4f1 2875static uint32_t ReadLatch(struct comedi_device *dev, struct enc_private *k)
11e865c1
GP		 2876{
2877 register uint32_t value;
b6c77757 2878 /* DEBUG FIXME DEBUG("ReadLatch: Read Latch enter\n"); */
11e865c1 2879
b6c77757 2880 /* Latch counts and fetch LSW of latched counts value. */
11e865c1
GP		 2881 value = (uint32_t) DEBIread(dev, k->MyLatchLsw);
2882
b6c77757 2883 /* Fetch MSW of latched counts and combine with LSW. */
11e865c1
GP		 2884 value |= ((uint32_t) DEBIread(dev, k->MyLatchLsw + 2) << 16);
2885
b6c77757 2886 /* DEBUG FIXME DEBUG("ReadLatch: Read Latch exit\n"); */
11e865c1 2887
b6c77757 2888 /* Return latched counts. */
11e865c1
GP		 2889 return value;
2890}
2891
b6c77757 2892/* Reset a counter's index and overflow event capture flags. */
11e865c1 2893
71b5f4f1 2894static void ResetCapFlags_A(struct comedi_device *dev, struct enc_private *k)
11e865c1
GP		 2895{
2896 DEBIreplace(dev, k->MyCRB, (uint16_t) (~CRBMSK_INTCTRL),
0a85b6f0 2897 CRBMSK_INTRESETCMD | CRBMSK_INTRESET_A);
11e865c1
GP		 2898}
2899
71b5f4f1 2900static void ResetCapFlags_B(struct comedi_device *dev, struct enc_private *k)
11e865c1
GP		 2901{
2902 DEBIreplace(dev, k->MyCRB, (uint16_t) (~CRBMSK_INTCTRL),
0a85b6f0 2903 CRBMSK_INTRESETCMD | CRBMSK_INTRESET_B);
11e865c1
GP		 2904}
2905
b6c77757
BP		 2906/* Return counter setup in a format (COUNTER_SETUP) that is consistent */
2907/* for both A and B counters. */
11e865c1 2908
71b5f4f1 2909static uint16_t GetMode_A(struct comedi_device *dev, struct enc_private *k)
11e865c1
GP		 2910{
2911 register uint16_t cra;
2912 register uint16_t crb;
2913 register uint16_t setup;
2914
b6c77757 2915 /* Fetch CRA and CRB register images. */
11e865c1
GP		 2916 cra = DEBIread(dev, k->MyCRA);
2917 crb = DEBIread(dev, k->MyCRB);
2918
b6c77757
BP		 2919 /* Populate the standardized counter setup bit fields. Note: */
2920 /* IndexSrc is restricted to ENC_X or IndxPol. */
2921 setup = ((cra & STDMSK_LOADSRC) /* LoadSrc = LoadSrcA. */
0a85b6f0
MT		 2922 |((crb << (STDBIT_LATCHSRC - CRBBIT_LATCHSRC)) & STDMSK_LATCHSRC) /* LatchSrc = LatchSrcA. */
2923 |((cra << (STDBIT_INTSRC - CRABIT_INTSRC_A)) & STDMSK_INTSRC) /* IntSrc = IntSrcA. */
2924 |((cra << (STDBIT_INDXSRC - (CRABIT_INDXSRC_A + 1))) & STDMSK_INDXSRC) /* IndxSrc = IndxSrcA<1>. */
2925 |((cra >> (CRABIT_INDXPOL_A - STDBIT_INDXPOL)) & STDMSK_INDXPOL) /* IndxPol = IndxPolA. */
2926 |((crb >> (CRBBIT_CLKENAB_A - STDBIT_CLKENAB)) & STDMSK_CLKENAB)); /* ClkEnab = ClkEnabA. */
b6c77757
BP		 2927
2928 /* Adjust mode-dependent parameters. */
2929 if (cra & (2 << CRABIT_CLKSRC_A)) /* If Timer mode (ClkSrcA<1> == 1): */
2930 setup |= ((CLKSRC_TIMER << STDBIT_CLKSRC) /* Indicate Timer mode. */
0a85b6f0
MT		 2931 |((cra << (STDBIT_CLKPOL - CRABIT_CLKSRC_A)) & STDMSK_CLKPOL) /* Set ClkPol to indicate count direction (ClkSrcA<0>). */
2932 |(MULT_X1 << STDBIT_CLKMULT)); /* ClkMult must be 1x in Timer mode. */
b6c77757
BP		 2933
2934 else /* If Counter mode (ClkSrcA<1> == 0): */
2935 setup |= ((CLKSRC_COUNTER << STDBIT_CLKSRC) /* Indicate Counter mode. */
0a85b6f0
MT		 2936 |((cra >> (CRABIT_CLKPOL_A - STDBIT_CLKPOL)) & STDMSK_CLKPOL) /* Pass through ClkPol. */
2937 |(((cra & CRAMSK_CLKMULT_A) == (MULT_X0 << CRABIT_CLKMULT_A)) ? /* Force ClkMult to 1x if not legal, else pass through. */
2938 (MULT_X1 << STDBIT_CLKMULT) :
2939 ((cra >> (CRABIT_CLKMULT_A -
2940 STDBIT_CLKMULT)) & STDMSK_CLKMULT)));
11e865c1 2941
b6c77757 2942 /* Return adjusted counter setup. */
11e865c1
GP		 2943 return setup;
2944}
2945
71b5f4f1 2946static uint16_t GetMode_B(struct comedi_device *dev, struct enc_private *k)
11e865c1
GP		 2947{
2948 register uint16_t cra;
2949 register uint16_t crb;
2950 register uint16_t setup;
2951
b6c77757 2952 /* Fetch CRA and CRB register images. */
11e865c1
GP		 2953 cra = DEBIread(dev, k->MyCRA);
2954 crb = DEBIread(dev, k->MyCRB);
2955
b6c77757
BP		 2956 /* Populate the standardized counter setup bit fields. Note: */
2957 /* IndexSrc is restricted to ENC_X or IndxPol. */
2958 setup = (((crb << (STDBIT_INTSRC - CRBBIT_INTSRC_B)) & STDMSK_INTSRC) /* IntSrc = IntSrcB. */
0a85b6f0
MT		 2959 |((crb << (STDBIT_LATCHSRC - CRBBIT_LATCHSRC)) & STDMSK_LATCHSRC) /* LatchSrc = LatchSrcB. */
2960 |((crb << (STDBIT_LOADSRC - CRBBIT_LOADSRC_B)) & STDMSK_LOADSRC) /* LoadSrc = LoadSrcB. */
2961 |((crb << (STDBIT_INDXPOL - CRBBIT_INDXPOL_B)) & STDMSK_INDXPOL) /* IndxPol = IndxPolB. */
2962 |((crb >> (CRBBIT_CLKENAB_B - STDBIT_CLKENAB)) & STDMSK_CLKENAB) /* ClkEnab = ClkEnabB. */
2963 |((cra >> ((CRABIT_INDXSRC_B + 1) - STDBIT_INDXSRC)) & STDMSK_INDXSRC)); /* IndxSrc = IndxSrcB<1>. */
b6c77757
BP		 2964
2965 /* Adjust mode-dependent parameters. */
2966 if ((crb & CRBMSK_CLKMULT_B) == (MULT_X0 << CRBBIT_CLKMULT_B)) /* If Extender mode (ClkMultB == MULT_X0): */
2967 setup |= ((CLKSRC_EXTENDER << STDBIT_CLKSRC) /* Indicate Extender mode. */
0a85b6f0
MT		 2968 |(MULT_X1 << STDBIT_CLKMULT) /* Indicate multiplier is 1x. */
2969 |((cra >> (CRABIT_CLKSRC_B - STDBIT_CLKPOL)) & STDMSK_CLKPOL)); /* Set ClkPol equal to Timer count direction (ClkSrcB<0>). */
b6c77757
BP		 2970
2971 else if (cra & (2 << CRABIT_CLKSRC_B)) /* If Timer mode (ClkSrcB<1> == 1): */
2972 setup |= ((CLKSRC_TIMER << STDBIT_CLKSRC) /* Indicate Timer mode. */
0a85b6f0
MT		 2973 |(MULT_X1 << STDBIT_CLKMULT) /* Indicate multiplier is 1x. */
2974 |((cra >> (CRABIT_CLKSRC_B - STDBIT_CLKPOL)) & STDMSK_CLKPOL)); /* Set ClkPol equal to Timer count direction (ClkSrcB<0>). */
b6c77757
BP		 2975
2976 else /* If Counter mode (ClkSrcB<1> == 0): */
2977 setup |= ((CLKSRC_COUNTER << STDBIT_CLKSRC) /* Indicate Timer mode. */
0a85b6f0
MT		 2978 |((crb >> (CRBBIT_CLKMULT_B - STDBIT_CLKMULT)) & STDMSK_CLKMULT) /* Clock multiplier is passed through. */
2979 |((crb << (STDBIT_CLKPOL - CRBBIT_CLKPOL_B)) & STDMSK_CLKPOL)); /* Clock polarity is passed through. */
b6c77757
BP		 2980
2981 /* Return adjusted counter setup. */
11e865c1
GP		 2982 return setup;
2983}
2984
b6c77757
BP		 2985/*
2986 * Set the operating mode for the specified counter. The setup
2987 * parameter is treated as a COUNTER_SETUP data type. The following
2988 * parameters are programmable (all other parms are ignored): ClkMult,
2989 * ClkPol, ClkEnab, IndexSrc, IndexPol, LoadSrc.
2990 */
11e865c1 2991
0a85b6f0
MT		 2992static void SetMode_A(struct comedi_device *dev, struct enc_private *k,
2993 uint16_t Setup, uint16_t DisableIntSrc)
11e865c1
GP		 2994{
2995 register uint16_t cra;
2996 register uint16_t crb;
b6c77757 2997 register uint16_t setup = Setup; /* Cache the Standard Setup. */
11e865c1 2998
b6c77757
BP		 2999 /* Initialize CRA and CRB images. */
3000 cra = ((setup & CRAMSK_LOADSRC_A) /* Preload trigger is passed through. */
0a85b6f0 3001 |((setup & STDMSK_INDXSRC) >> (STDBIT_INDXSRC - (CRABIT_INDXSRC_A + 1)))); /* IndexSrc is restricted to ENC_X or IndxPol. */
11e865c1 3002
b6c77757 3003 crb = (CRBMSK_INTRESETCMD | CRBMSK_INTRESET_A /* Reset any pending CounterA event captures. */
0a85b6f0 3004 | ((setup & STDMSK_CLKENAB) << (CRBBIT_CLKENAB_A - STDBIT_CLKENAB))); /* Clock enable is passed through. */
11e865c1 3005
b6c77757 3006 /* Force IntSrc to Disabled if DisableIntSrc is asserted. */
11e865c1
GP		 3007 if (!DisableIntSrc)
3008 cra |= ((setup & STDMSK_INTSRC) >> (STDBIT_INTSRC -
0a85b6f0 3009 CRABIT_INTSRC_A));
11e865c1 3010
b6c77757 3011 /* Populate all mode-dependent attributes of CRA & CRB images. */
11e865c1 3012 switch ((setup & STDMSK_CLKSRC) >> STDBIT_CLKSRC) {
b6c77757
BP		 3013 case CLKSRC_EXTENDER: /* Extender Mode: Force to Timer mode */
3014 /* (Extender valid only for B counters). */
3015
3016 case CLKSRC_TIMER: /* Timer Mode: */
3017 cra |= ((2 << CRABIT_CLKSRC_A) /* ClkSrcA<1> selects system clock */
0a85b6f0
MT		 3018 |((setup & STDMSK_CLKPOL) >> (STDBIT_CLKPOL - CRABIT_CLKSRC_A)) /* with count direction (ClkSrcA<0>) obtained from ClkPol. */
3019 |(1 << CRABIT_CLKPOL_A) /* ClkPolA behaves as always-on clock enable. */
3020 |(MULT_X1 << CRABIT_CLKMULT_A)); /* ClkMult must be 1x. */
11e865c1
GP		 3021 break;
3022
b6c77757
BP		 3023 default: /* Counter Mode: */
3024 cra |= (CLKSRC_COUNTER /* Select ENC_C and ENC_D as clock/direction inputs. */
3025 | ((setup & STDMSK_CLKPOL) << (CRABIT_CLKPOL_A - STDBIT_CLKPOL)) /* Clock polarity is passed through. */
0a85b6f0
MT		 3026 |(((setup & STDMSK_CLKMULT) == (MULT_X0 << STDBIT_CLKMULT)) ? /* Force multiplier to x1 if not legal, otherwise pass through. */
3027 (MULT_X1 << CRABIT_CLKMULT_A) :
3028 ((setup & STDMSK_CLKMULT) << (CRABIT_CLKMULT_A -
3029 STDBIT_CLKMULT))));
11e865c1
GP		 3030 }
3031
b6c77757
BP		 3032 /* Force positive index polarity if IndxSrc is software-driven only, */
3033 /* otherwise pass it through. */
11e865c1
GP		 3034 if (~setup & STDMSK_INDXSRC)
3035 cra |= ((setup & STDMSK_INDXPOL) << (CRABIT_INDXPOL_A -
0a85b6f0 3036 STDBIT_INDXPOL));
11e865c1 3037
b6c77757
BP		 3038 /* If IntSrc has been forced to Disabled, update the MISC2 interrupt */
3039 /* enable mask to indicate the counter interrupt is disabled. */
11e865c1
GP		 3040 if (DisableIntSrc)
3041 devpriv->CounterIntEnabs &= ~k->MyEventBits[3];
3042
b6c77757
BP		 3043 /* While retaining CounterB and LatchSrc configurations, program the */
3044 /* new counter operating mode. */
11e865c1
GP		 3045 DEBIreplace(dev, k->MyCRA, CRAMSK_INDXSRC_B | CRAMSK_CLKSRC_B, cra);
3046 DEBIreplace(dev, k->MyCRB,
0a85b6f0 3047 (uint16_t) (~(CRBMSK_INTCTRL | CRBMSK_CLKENAB_A)), crb);
11e865c1
GP		 3048}
3049
0a85b6f0
MT		 3050static void SetMode_B(struct comedi_device *dev, struct enc_private *k,
3051 uint16_t Setup, uint16_t DisableIntSrc)
11e865c1
GP		 3052{
3053 register uint16_t cra;
3054 register uint16_t crb;
b6c77757 3055 register uint16_t setup = Setup; /* Cache the Standard Setup. */
11e865c1 3056
b6c77757
BP		 3057 /* Initialize CRA and CRB images. */
3058 cra = ((setup & STDMSK_INDXSRC) << ((CRABIT_INDXSRC_B + 1) - STDBIT_INDXSRC)); /* IndexSrc field is restricted to ENC_X or IndxPol. */
11e865c1 3059
b6c77757 3060 crb = (CRBMSK_INTRESETCMD | CRBMSK_INTRESET_B /* Reset event captures and disable interrupts. */
0a85b6f0
MT		 3061 | ((setup & STDMSK_CLKENAB) << (CRBBIT_CLKENAB_B - STDBIT_CLKENAB)) /* Clock enable is passed through. */
3062 |((setup & STDMSK_LOADSRC) >> (STDBIT_LOADSRC - CRBBIT_LOADSRC_B))); /* Preload trigger source is passed through. */
11e865c1 3063
b6c77757 3064 /* Force IntSrc to Disabled if DisableIntSrc is asserted. */
11e865c1
GP		 3065 if (!DisableIntSrc)
3066 crb |= ((setup & STDMSK_INTSRC) >> (STDBIT_INTSRC -
0a85b6f0 3067 CRBBIT_INTSRC_B));
11e865c1 3068
b6c77757 3069 /* Populate all mode-dependent attributes of CRA & CRB images. */
11e865c1 3070 switch ((setup & STDMSK_CLKSRC) >> STDBIT_CLKSRC) {
b6c77757
BP		 3071 case CLKSRC_TIMER: /* Timer Mode: */
3072 cra |= ((2 << CRABIT_CLKSRC_B) /* ClkSrcB<1> selects system clock */
0a85b6f0 3073 |((setup & STDMSK_CLKPOL) << (CRABIT_CLKSRC_B - STDBIT_CLKPOL))); /* with direction (ClkSrcB<0>) obtained from ClkPol. */
b6c77757 3074 crb |= ((1 << CRBBIT_CLKPOL_B) /* ClkPolB behaves as always-on clock enable. */
0a85b6f0 3075 |(MULT_X1 << CRBBIT_CLKMULT_B)); /* ClkMultB must be 1x. */
11e865c1
GP		 3076 break;
3077
b6c77757
BP		 3078 case CLKSRC_EXTENDER: /* Extender Mode: */
3079 cra |= ((2 << CRABIT_CLKSRC_B) /* ClkSrcB source is OverflowA (same as "timer") */
0a85b6f0 3080 |((setup & STDMSK_CLKPOL) << (CRABIT_CLKSRC_B - STDBIT_CLKPOL))); /* with direction obtained from ClkPol. */
b6c77757 3081 crb |= ((1 << CRBBIT_CLKPOL_B) /* ClkPolB controls IndexB -- always set to active. */
0a85b6f0 3082 |(MULT_X0 << CRBBIT_CLKMULT_B)); /* ClkMultB selects OverflowA as the clock source. */
11e865c1
GP		 3083 break;
3084
b6c77757
BP		 3085 default: /* Counter Mode: */
3086 cra |= (CLKSRC_COUNTER << CRABIT_CLKSRC_B); /* Select ENC_C and ENC_D as clock/direction inputs. */
3087 crb |= (((setup & STDMSK_CLKPOL) >> (STDBIT_CLKPOL - CRBBIT_CLKPOL_B)) /* ClkPol is passed through. */
0a85b6f0
MT		 3088 |(((setup & STDMSK_CLKMULT) == (MULT_X0 << STDBIT_CLKMULT)) ? /* Force ClkMult to x1 if not legal, otherwise pass through. */
3089 (MULT_X1 << CRBBIT_CLKMULT_B) :
3090 ((setup & STDMSK_CLKMULT) << (CRBBIT_CLKMULT_B -
3091 STDBIT_CLKMULT))));
11e865c1
GP		 3092 }
3093
b6c77757
BP		 3094 /* Force positive index polarity if IndxSrc is software-driven only, */
3095 /* otherwise pass it through. */
11e865c1
GP		 3096 if (~setup & STDMSK_INDXSRC)
3097 crb |= ((setup & STDMSK_INDXPOL) >> (STDBIT_INDXPOL -
0a85b6f0 3098 CRBBIT_INDXPOL_B));
11e865c1 3099
b6c77757
BP		 3100 /* If IntSrc has been forced to Disabled, update the MISC2 interrupt */
3101 /* enable mask to indicate the counter interrupt is disabled. */
11e865c1
GP		 3102 if (DisableIntSrc)
3103 devpriv->CounterIntEnabs &= ~k->MyEventBits[3];
3104
b6c77757
BP		 3105 /* While retaining CounterA and LatchSrc configurations, program the */
3106 /* new counter operating mode. */
11e865c1 3107 DEBIreplace(dev, k->MyCRA,
0a85b6f0 3108 (uint16_t) (~(CRAMSK_INDXSRC_B | CRAMSK_CLKSRC_B)), cra);
11e865c1
GP		 3109 DEBIreplace(dev, k->MyCRB, CRBMSK_CLKENAB_A | CRBMSK_LATCHSRC, crb);
3110}
3111
b6c77757 3112/* Return/set a counter's enable. enab: 0=always enabled, 1=enabled by index. */
11e865c1 3113
0a85b6f0
MT		 3114static void SetEnable_A(struct comedi_device *dev, struct enc_private *k,
3115 uint16_t enab)
11e865c1
GP		 3116{
3117 DEBUG("SetEnable_A: SetEnable_A enter 3541\n");
3118 DEBIreplace(dev, k->MyCRB,
0a85b6f0
MT		 3119 (uint16_t) (~(CRBMSK_INTCTRL | CRBMSK_CLKENAB_A)),
3120 (uint16_t) (enab << CRBBIT_CLKENAB_A));
11e865c1
GP		 3121}
3122
0a85b6f0
MT		 3123static void SetEnable_B(struct comedi_device *dev, struct enc_private *k,
3124 uint16_t enab)
11e865c1
GP		 3125{
3126 DEBIreplace(dev, k->MyCRB,
0a85b6f0
MT		 3127 (uint16_t) (~(CRBMSK_INTCTRL | CRBMSK_CLKENAB_B)),
3128 (uint16_t) (enab << CRBBIT_CLKENAB_B));
11e865c1
GP		 3129}
3130
71b5f4f1 3131static uint16_t GetEnable_A(struct comedi_device *dev, struct enc_private *k)
11e865c1
GP		 3132{
3133 return (DEBIread(dev, k->MyCRB) >> CRBBIT_CLKENAB_A) & 1;
3134}
3135
71b5f4f1 3136static uint16_t GetEnable_B(struct comedi_device *dev, struct enc_private *k)
11e865c1
GP		 3137{
3138 return (DEBIread(dev, k->MyCRB) >> CRBBIT_CLKENAB_B) & 1;
3139}
3140
b6c77757
BP		 3141/* Return/set a counter pair's latch trigger source. 0: On read
3142 * access, 1: A index latches A, 2: B index latches B, 3: A overflow
3143 * latches B.
3144 */
11e865c1 3145
0a85b6f0
MT		 3146static void SetLatchSource(struct comedi_device *dev, struct enc_private *k,
3147 uint16_t value)
11e865c1 3148{
daca497d 3149 DEBUG("SetLatchSource: SetLatchSource enter 3550\n");
11e865c1 3150 DEBIreplace(dev, k->MyCRB,
0a85b6f0
MT		 3151 (uint16_t) (~(CRBMSK_INTCTRL | CRBMSK_LATCHSRC)),
3152 (uint16_t) (value << CRBBIT_LATCHSRC));
11e865c1 3153
daca497d 3154 DEBUG("SetLatchSource: SetLatchSource exit\n");
11e865c1
GP		 3155}
3156
b6c77757 3157/*
71b5f4f1 3158 * static uint16_t GetLatchSource(struct comedi_device *dev, struct enc_private *k )
b6c77757 3159 * {
ae6eb75c 3160 * return ( DEBIread( dev, k->MyCRB) >> CRBBIT_LATCHSRC ) & 3;
b6c77757
BP		 3161 * }
3162 */
11e865c1 3163
b6c77757
BP		 3164/*
3165 * Return/set the event that will trigger transfer of the preload
3166 * register into the counter. 0=ThisCntr_Index, 1=ThisCntr_Overflow,
3167 * 2=OverflowA (B counters only), 3=disabled.
3168 */
11e865c1 3169
0a85b6f0
MT		 3170static void SetLoadTrig_A(struct comedi_device *dev, struct enc_private *k,
3171 uint16_t Trig)
11e865c1
GP		 3172{
3173 DEBIreplace(dev, k->MyCRA, (uint16_t) (~CRAMSK_LOADSRC_A),
0a85b6f0 3174 (uint16_t) (Trig << CRABIT_LOADSRC_A));
11e865c1
GP		 3175}
3176
0a85b6f0
MT		 3177static void SetLoadTrig_B(struct comedi_device *dev, struct enc_private *k,
3178 uint16_t Trig)
11e865c1
GP		 3179{
3180 DEBIreplace(dev, k->MyCRB,
0a85b6f0
MT		 3181 (uint16_t) (~(CRBMSK_LOADSRC_B | CRBMSK_INTCTRL)),
3182 (uint16_t) (Trig << CRBBIT_LOADSRC_B));
11e865c1
GP		 3183}
3184
71b5f4f1 3185static uint16_t GetLoadTrig_A(struct comedi_device *dev, struct enc_private *k)
11e865c1
GP		 3186{
3187 return (DEBIread(dev, k->MyCRA) >> CRABIT_LOADSRC_A) & 3;
3188}
3189
71b5f4f1 3190static uint16_t GetLoadTrig_B(struct comedi_device *dev, struct enc_private *k)
11e865c1
GP		 3191{
3192 return (DEBIread(dev, k->MyCRB) >> CRBBIT_LOADSRC_B) & 3;
3193}
3194
b6c77757
BP		 3195/* Return/set counter interrupt source and clear any captured
3196 * index/overflow events. IntSource: 0=Disabled, 1=OverflowOnly,
3197 * 2=IndexOnly, 3=IndexAndOverflow.
3198 */
11e865c1 3199
71b5f4f1 3200static void SetIntSrc_A(struct comedi_device *dev, struct enc_private *k,
0a85b6f0 3201 uint16_t IntSource)
11e865c1 3202{
b6c77757 3203 /* Reset any pending counter overflow or index captures. */
11e865c1 3204 DEBIreplace(dev, k->MyCRB, (uint16_t) (~CRBMSK_INTCTRL),
0a85b6f0 3205 CRBMSK_INTRESETCMD | CRBMSK_INTRESET_A);
11e865c1 3206
b6c77757 3207 /* Program counter interrupt source. */
11e865c1 3208 DEBIreplace(dev, k->MyCRA, ~CRAMSK_INTSRC_A,
0a85b6f0 3209 (uint16_t) (IntSource << CRABIT_INTSRC_A));
11e865c1 3210
b6c77757 3211 /* Update MISC2 interrupt enable mask. */
11e865c1 3212 devpriv->CounterIntEnabs =
0a85b6f0
MT		 3213 (devpriv->CounterIntEnabs & ~k->
3214 MyEventBits[3]) | k->MyEventBits[IntSource];
11e865c1
GP		 3215}
3216
71b5f4f1 3217static void SetIntSrc_B(struct comedi_device *dev, struct enc_private *k,
0a85b6f0 3218 uint16_t IntSource)
11e865c1
GP		 3219{
3220 uint16_t crb;
3221
b6c77757 3222 /* Cache writeable CRB register image. */
11e865c1
GP		 3223 crb = DEBIread(dev, k->MyCRB) & ~CRBMSK_INTCTRL;
3224
b6c77757 3225 /* Reset any pending counter overflow or index captures. */
11e865c1 3226 DEBIwrite(dev, k->MyCRB,
0a85b6f0 3227 (uint16_t) (crb | CRBMSK_INTRESETCMD | CRBMSK_INTRESET_B));
11e865c1 3228
b6c77757 3229 /* Program counter interrupt source. */
11e865c1 3230 DEBIwrite(dev, k->MyCRB,
0a85b6f0
MT		 3231 (uint16_t) ((crb & ~CRBMSK_INTSRC_B) | (IntSource <<
3232 CRBBIT_INTSRC_B)));
11e865c1 3233
b6c77757 3234 /* Update MISC2 interrupt enable mask. */
11e865c1 3235 devpriv->CounterIntEnabs =
0a85b6f0
MT		 3236 (devpriv->CounterIntEnabs & ~k->
3237 MyEventBits[3]) | k->MyEventBits[IntSource];
11e865c1
GP		 3238}
3239
71b5f4f1 3240static uint16_t GetIntSrc_A(struct comedi_device *dev, struct enc_private *k)
11e865c1
GP		 3241{
3242 return (DEBIread(dev, k->MyCRA) >> CRABIT_INTSRC_A) & 3;
3243}
3244
71b5f4f1 3245static uint16_t GetIntSrc_B(struct comedi_device *dev, struct enc_private *k)
11e865c1
GP		 3246{
3247 return (DEBIread(dev, k->MyCRB) >> CRBBIT_INTSRC_B) & 3;
3248}
3249
b6c77757 3250/* Return/set the clock multiplier. */
11e865c1 3251
71b5f4f1 3252/* static void SetClkMult(struct comedi_device *dev, struct enc_private *k, uint16_t value ) */
11e865c1
GP		 3253/* { */
3254/* k->SetMode(dev, k, (uint16_t)( ( k->GetMode(dev, k ) & ~STDMSK_CLKMULT ) | ( value << STDBIT_CLKMULT ) ), FALSE ); */
3255/* } */
3256
71b5f4f1 3257/* static uint16_t GetClkMult(struct comedi_device *dev, struct enc_private *k ) */
11e865c1
GP		 3258/* { */
3259/* return ( k->GetMode(dev, k ) >> STDBIT_CLKMULT ) & 3; */
3260/* } */
3261
b6c77757 3262/* Return/set the clock polarity. */
11e865c1 3263
71b5f4f1 3264/* static void SetClkPol( struct comedi_device *dev,struct enc_private *k, uint16_t value ) */
11e865c1
GP		 3265/* { */
3266/* k->SetMode(dev, k, (uint16_t)( ( k->GetMode(dev, k ) & ~STDMSK_CLKPOL ) | ( value << STDBIT_CLKPOL ) ), FALSE ); */
3267/* } */
3268
71b5f4f1 3269/* static uint16_t GetClkPol(struct comedi_device *dev, struct enc_private *k ) */
11e865c1
GP		 3270/* { */
3271/* return ( k->GetMode(dev, k ) >> STDBIT_CLKPOL ) & 1; */
3272/* } */
3273
b6c77757 3274/* Return/set the clock source. */
11e865c1 3275
71b5f4f1 3276/* static void SetClkSrc( struct comedi_device *dev,struct enc_private *k, uint16_t value ) */
11e865c1
GP		 3277/* { */
3278/* k->SetMode(dev, k, (uint16_t)( ( k->GetMode(dev, k ) & ~STDMSK_CLKSRC ) | ( value << STDBIT_CLKSRC ) ), FALSE ); */
3279/* } */
3280
71b5f4f1 3281/* static uint16_t GetClkSrc( struct comedi_device *dev,struct enc_private *k ) */
11e865c1
GP		 3282/* { */
3283/* return ( k->GetMode(dev, k ) >> STDBIT_CLKSRC ) & 3; */
3284/* } */
3285
b6c77757 3286/* Return/set the index polarity. */
11e865c1 3287
71b5f4f1 3288/* static void SetIndexPol(struct comedi_device *dev, struct enc_private *k, uint16_t value ) */
11e865c1
GP		 3289/* { */
3290/* k->SetMode(dev, k, (uint16_t)( ( k->GetMode(dev, k ) & ~STDMSK_INDXPOL ) | ( (value != 0) << STDBIT_INDXPOL ) ), FALSE ); */
3291/* } */
3292
71b5f4f1 3293/* static uint16_t GetIndexPol(struct comedi_device *dev, struct enc_private *k ) */
11e865c1
GP		 3294/* { */
3295/* return ( k->GetMode(dev, k ) >> STDBIT_INDXPOL ) & 1; */
3296/* } */
3297
b6c77757 3298/* Return/set the index source. */
11e865c1 3299
71b5f4f1 3300/* static void SetIndexSrc(struct comedi_device *dev, struct enc_private *k, uint16_t value ) */
11e865c1
GP		 3301/* { */
3302/* DEBUG("SetIndexSrc: set index src enter 3700\n"); */
3303/* k->SetMode(dev, k, (uint16_t)( ( k->GetMode(dev, k ) & ~STDMSK_INDXSRC ) | ( (value != 0) << STDBIT_INDXSRC ) ), FALSE ); */
3304/* } */
3305
71b5f4f1 3306/* static uint16_t GetIndexSrc(struct comedi_device *dev, struct enc_private *k ) */
11e865c1
GP		 3307/* { */
3308/* return ( k->GetMode(dev, k ) >> STDBIT_INDXSRC ) & 1; */
3309/* } */
3310
b6c77757 3311/* Generate an index pulse. */
11e865c1 3312
71b5f4f1 3313static void PulseIndex_A(struct comedi_device *dev, struct enc_private *k)
11e865c1
GP		 3314{
3315 register uint16_t cra;
3316
3317 DEBUG("PulseIndex_A: pulse index enter\n");
3318
b6c77757 3319 cra = DEBIread(dev, k->MyCRA); /* Pulse index. */
11e865c1
GP		 3320 DEBIwrite(dev, k->MyCRA, (uint16_t) (cra ^ CRAMSK_INDXPOL_A));
3321 DEBUG("PulseIndex_A: pulse index step1\n");
3322 DEBIwrite(dev, k->MyCRA, cra);
3323}
3324
71b5f4f1 3325static void PulseIndex_B(struct comedi_device *dev, struct enc_private *k)
11e865c1
GP		 3326{
3327 register uint16_t crb;
3328
b6c77757 3329 crb = DEBIread(dev, k->MyCRB) & ~CRBMSK_INTCTRL; /* Pulse index. */
11e865c1
GP		 3330 DEBIwrite(dev, k->MyCRB, (uint16_t) (crb ^ CRBMSK_INDXPOL_B));
3331 DEBIwrite(dev, k->MyCRB, crb);
3332}
3333
b6c77757 3334/* Write value into counter preload register. */
11e865c1 3335
0a85b6f0
MT		 3336static void Preload(struct comedi_device *dev, struct enc_private *k,
3337 uint32_t value)
11e865c1
GP		 3338{
3339 DEBUG("Preload: preload enter\n");
b6c77757 3340 DEBIwrite(dev, (uint16_t) (k->MyLatchLsw), (uint16_t) value); /* Write value to preload register. */
11e865c1
GP		 3341 DEBUG("Preload: preload step 1\n");
3342 DEBIwrite(dev, (uint16_t) (k->MyLatchLsw + 2),
0a85b6f0 3343 (uint16_t) (value >> 16));
11e865c1
GP		 3344}
3345
71b5f4f1 3346static void CountersInit(struct comedi_device *dev)
11e865c1
GP		 3347{
3348 int chan;
eb5e029e 3349 struct enc_private *k;
b6c77757 3350 uint16_t Setup = (LOADSRC_INDX << BF_LOADSRC) | /* Preload upon */
0a85b6f0
MT		 3351 /* index. */
3352 (INDXSRC_SOFT << BF_INDXSRC) | /* Disable hardware index. */
3353 (CLKSRC_COUNTER << BF_CLKSRC) | /* Operating mode is counter. */
3354 (CLKPOL_POS << BF_CLKPOL) | /* Active high clock. */
3355 (CNTDIR_UP << BF_CLKPOL) | /* Count direction is up. */
3356 (CLKMULT_1X << BF_CLKMULT) | /* Clock multiplier is 1x. */
3357 (CLKENAB_INDEX << BF_CLKENAB); /* Enabled by index */
b6c77757
BP		 3358
3359 /* Disable all counter interrupts and clear any captured counter events. */
11e865c1
GP		 3360 for (chan = 0; chan < S626_ENCODER_CHANNELS; chan++) {
3361 k = &encpriv[chan];
3362 k->SetMode(dev, k, Setup, TRUE);
3363 k->SetIntSrc(dev, k, 0);
3364 k->ResetCapFlags(dev, k);
3365 k->SetEnable(dev, k, CLKENAB_ALWAYS);
3366 }
daca497d 3367 DEBUG("CountersInit: counters initialized\n");
11e865c1
GP		 3368
3369}
Linux kernel - Deliverables
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