Commit | Line | Data |
---|---|---|
11e865c1 | 1 | /* |
7f32c7c4 IA |
2 | * comedi/drivers/s626.c |
3 | * Sensoray s626 Comedi driver | |
4 | * | |
5 | * COMEDI - Linux Control and Measurement Device Interface | |
6 | * Copyright (C) 2000 David A. Schleef <ds@schleef.org> | |
7 | * | |
8 | * Based on Sensoray Model 626 Linux driver Version 0.2 | |
9 | * Copyright (C) 2002-2004 Sensoray Co., Inc. | |
10 | * | |
11 | * This program is free software; you can redistribute it and/or modify | |
12 | * it under the terms of the GNU General Public License as published by | |
13 | * the Free Software Foundation; either version 2 of the License, or | |
14 | * (at your option) any later version. | |
15 | * | |
16 | * This program is distributed in the hope that it will be useful, | |
17 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
18 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
19 | * GNU General Public License for more details. | |
20 | */ | |
11e865c1 GP |
21 | |
22 | /* | |
7f32c7c4 IA |
23 | * Driver: s626 |
24 | * Description: Sensoray 626 driver | |
25 | * Devices: [Sensoray] 626 (s626) | |
26 | * Authors: Gianluca Palli <gpalli@deis.unibo.it>, | |
27 | * Updated: Fri, 15 Feb 2008 10:28:42 +0000 | |
28 | * Status: experimental | |
29 | ||
30 | * Configuration options: not applicable, uses PCI auto config | |
31 | ||
32 | * INSN_CONFIG instructions: | |
33 | * analog input: | |
34 | * none | |
35 | * | |
36 | * analog output: | |
37 | * none | |
38 | * | |
39 | * digital channel: | |
40 | * s626 has 3 dio subdevices (2,3 and 4) each with 16 i/o channels | |
41 | * supported configuration options: | |
42 | * INSN_CONFIG_DIO_QUERY | |
43 | * COMEDI_INPUT | |
44 | * COMEDI_OUTPUT | |
45 | * | |
46 | * encoder: | |
47 | * Every channel must be configured before reading. | |
48 | * | |
49 | * Example code | |
50 | * | |
51 | * insn.insn=INSN_CONFIG; //configuration instruction | |
52 | * insn.n=1; //number of operation (must be 1) | |
53 | * insn.data=&initialvalue; //initial value loaded into encoder | |
54 | * //during configuration | |
55 | * insn.subdev=5; //encoder subdevice | |
56 | * insn.chanspec=CR_PACK(encoder_channel,0,AREF_OTHER); //encoder_channel | |
57 | * //to configure | |
58 | * | |
59 | * comedi_do_insn(cf,&insn); //executing configuration | |
60 | */ | |
11e865c1 | 61 | |
ce157f80 HS |
62 | #include <linux/module.h> |
63 | #include <linux/delay.h> | |
25436dc9 | 64 | #include <linux/interrupt.h> |
11e865c1 GP |
65 | #include <linux/kernel.h> |
66 | #include <linux/types.h> | |
67 | ||
6ab38b05 | 68 | #include "../comedi_pci.h" |
11e865c1 | 69 | |
11e865c1 GP |
70 | #include "s626.h" |
71 | ||
dbb263f5 | 72 | struct s626_buffer_dma { |
8e06d662 IA |
73 | dma_addr_t physical_base; |
74 | void *logical_base; | |
75 | }; | |
76 | ||
eb5e029e | 77 | struct s626_private { |
8ee52611 | 78 | uint8_t ai_cmd_running; /* ai_cmd is running */ |
8ee52611 IA |
79 | unsigned int ai_sample_timer; /* time between samples in |
80 | * units of the timer */ | |
81 | int ai_convert_count; /* conversion counter */ | |
82 | unsigned int ai_convert_timer; /* time between conversion in | |
83 | * units of the timer */ | |
07a36d66 | 84 | uint16_t counter_int_enabs; /* counter interrupt enable mask |
8ee52611 | 85 | * for MISC2 register */ |
07a36d66 | 86 | uint8_t adc_items; /* number of items in ADC poll list */ |
dbb263f5 | 87 | struct s626_buffer_dma rps_buf; /* DMA buffer used to hold ADC (RPS1) |
8ee52611 | 88 | * program */ |
dbb263f5 | 89 | struct s626_buffer_dma ana_buf; /* DMA buffer used to receive ADC data |
8ee52611 | 90 | * and hold DAC data */ |
07a36d66 | 91 | uint32_t *dac_wbuf; /* pointer to logical adrs of DMA buffer |
8ee52611 | 92 | * used to hold DAC data */ |
07a36d66 IA |
93 | uint16_t dacpol; /* image of DAC polarity register */ |
94 | uint8_t trim_setpoint[12]; /* images of TrimDAC setpoints */ | |
95 | uint32_t i2c_adrs; /* I2C device address for onboard EEPROM | |
8ee52611 | 96 | * (board rev dependent) */ |
eb5e029e | 97 | }; |
11e865c1 | 98 | |
8ee52611 | 99 | /* Counter overflow/index event flag masks for RDMISC2. */ |
676921c9 IA |
100 | #define S626_INDXMASK(C) (1 << (((C) > 2) ? ((C) * 2 - 1) : ((C) * 2 + 4))) |
101 | #define S626_OVERMASK(C) (1 << (((C) > 2) ? ((C) * 2 + 5) : ((C) * 2 + 10))) | |
11e865c1 | 102 | |
ddd9813e HS |
103 | /* |
104 | * Enable/disable a function or test status bit(s) that are accessed | |
105 | * through Main Control Registers 1 or 2. | |
106 | */ | |
107 | static void s626_mc_enable(struct comedi_device *dev, | |
108 | unsigned int cmd, unsigned int reg) | |
109 | { | |
ddd9813e HS |
110 | unsigned int val = (cmd << 16) | cmd; |
111 | ||
bb49cddc | 112 | mmiowb(); |
de9cd5ca | 113 | writel(val, dev->mmio + reg); |
ddd9813e | 114 | } |
11e865c1 | 115 | |
c5cf4606 HS |
116 | static void s626_mc_disable(struct comedi_device *dev, |
117 | unsigned int cmd, unsigned int reg) | |
118 | { | |
ddd54d65 | 119 | writel(cmd << 16, dev->mmio + reg); |
bb49cddc | 120 | mmiowb(); |
c5cf4606 | 121 | } |
11e865c1 | 122 | |
95bb7982 HS |
123 | static bool s626_mc_test(struct comedi_device *dev, |
124 | unsigned int cmd, unsigned int reg) | |
125 | { | |
95bb7982 HS |
126 | unsigned int val; |
127 | ||
de9cd5ca | 128 | val = readl(dev->mmio + reg); |
95bb7982 HS |
129 | |
130 | return (val & cmd) ? true : false; | |
131 | } | |
11e865c1 | 132 | |
676921c9 | 133 | #define S626_BUGFIX_STREG(REGADRS) ((REGADRS) - 4) |
11e865c1 | 134 | |
8ee52611 | 135 | /* Write a time slot control record to TSL2. */ |
d8515652 | 136 | #define S626_VECTPORT(VECTNUM) (S626_P_TSL2 + ((VECTNUM) << 2)) |
11e865c1 | 137 | |
90d54ff2 HS |
138 | static const struct comedi_lrange s626_range_table = { |
139 | 2, { | |
140 | BIP_RANGE(5), | |
481ac510 | 141 | BIP_RANGE(10) |
90d54ff2 | 142 | } |
11e865c1 GP |
143 | }; |
144 | ||
8ee52611 IA |
145 | /* |
146 | * Execute a DEBI transfer. This must be called from within a critical section. | |
147 | */ | |
31de1948 | 148 | static void s626_debi_transfer(struct comedi_device *dev) |
6b387b70 | 149 | { |
59a32a46 CS |
150 | static const int timeout = 10000; |
151 | int i; | |
7f2f7e05 | 152 | |
ddd9813e | 153 | /* Initiate upload of shadow RAM to DEBI control register */ |
d8515652 | 154 | s626_mc_enable(dev, S626_MC2_UPLD_DEBI, S626_P_MC2); |
6b387b70 | 155 | |
95bb7982 HS |
156 | /* |
157 | * Wait for completion of upload from shadow RAM to | |
158 | * DEBI control register. | |
159 | */ | |
59a32a46 CS |
160 | for (i = 0; i < timeout; i++) { |
161 | if (s626_mc_test(dev, S626_MC2_UPLD_DEBI, S626_P_MC2)) | |
162 | break; | |
163 | udelay(1); | |
164 | } | |
165 | if (i == timeout) | |
cefe9336 HS |
166 | dev_err(dev->class_dev, |
167 | "Timeout while uploading to DEBI control register\n"); | |
6b387b70 | 168 | |
be008602 | 169 | /* Wait until DEBI transfer is done */ |
59a32a46 | 170 | for (i = 0; i < timeout; i++) { |
de9cd5ca | 171 | if (!(readl(dev->mmio + S626_P_PSR) & S626_PSR_DEBI_S)) |
59a32a46 CS |
172 | break; |
173 | udelay(1); | |
174 | } | |
175 | if (i == timeout) | |
cefe9336 | 176 | dev_err(dev->class_dev, "DEBI transfer timeout\n"); |
6b387b70 HS |
177 | } |
178 | ||
8ee52611 IA |
179 | /* |
180 | * Read a value from a gate array register. | |
181 | */ | |
31de1948 | 182 | static uint16_t s626_debi_read(struct comedi_device *dev, uint16_t addr) |
6b387b70 | 183 | { |
25f8fd5e | 184 | /* Set up DEBI control register value in shadow RAM */ |
de9cd5ca | 185 | writel(S626_DEBI_CMD_RDWORD | addr, dev->mmio + S626_P_DEBICMD); |
6b387b70 HS |
186 | |
187 | /* Execute the DEBI transfer. */ | |
31de1948 | 188 | s626_debi_transfer(dev); |
6b387b70 | 189 | |
de9cd5ca | 190 | return readl(dev->mmio + S626_P_DEBIAD); |
6b387b70 HS |
191 | } |
192 | ||
8ee52611 IA |
193 | /* |
194 | * Write a value to a gate array register. | |
195 | */ | |
31de1948 IA |
196 | static void s626_debi_write(struct comedi_device *dev, uint16_t addr, |
197 | uint16_t wdata) | |
6b387b70 | 198 | { |
25f8fd5e | 199 | /* Set up DEBI control register value in shadow RAM */ |
de9cd5ca HS |
200 | writel(S626_DEBI_CMD_WRWORD | addr, dev->mmio + S626_P_DEBICMD); |
201 | writel(wdata, dev->mmio + S626_P_DEBIAD); | |
6b387b70 HS |
202 | |
203 | /* Execute the DEBI transfer. */ | |
31de1948 | 204 | s626_debi_transfer(dev); |
6b387b70 HS |
205 | } |
206 | ||
8ee52611 IA |
207 | /* |
208 | * Replace the specified bits in a gate array register. Imports: mask | |
6b387b70 HS |
209 | * specifies bits that are to be preserved, wdata is new value to be |
210 | * or'd with the masked original. | |
211 | */ | |
31de1948 IA |
212 | static void s626_debi_replace(struct comedi_device *dev, unsigned int addr, |
213 | unsigned int mask, unsigned int wdata) | |
6b387b70 | 214 | { |
be008602 | 215 | unsigned int val; |
6b387b70 | 216 | |
12f4e2f2 | 217 | addr &= 0xffff; |
de9cd5ca | 218 | writel(S626_DEBI_CMD_RDWORD | addr, dev->mmio + S626_P_DEBICMD); |
31de1948 | 219 | s626_debi_transfer(dev); |
6b387b70 | 220 | |
de9cd5ca HS |
221 | writel(S626_DEBI_CMD_WRWORD | addr, dev->mmio + S626_P_DEBICMD); |
222 | val = readl(dev->mmio + S626_P_DEBIAD); | |
be008602 HS |
223 | val &= mask; |
224 | val |= wdata; | |
de9cd5ca | 225 | writel(val & 0xffff, dev->mmio + S626_P_DEBIAD); |
31de1948 | 226 | s626_debi_transfer(dev); |
6b387b70 HS |
227 | } |
228 | ||
982e3d11 HS |
229 | /* ************** EEPROM ACCESS FUNCTIONS ************** */ |
230 | ||
571845c6 | 231 | static int s626_i2c_handshake_eoc(struct comedi_device *dev, |
6c7d2c8b HS |
232 | struct comedi_subdevice *s, |
233 | struct comedi_insn *insn, | |
234 | unsigned long context) | |
571845c6 CS |
235 | { |
236 | bool status; | |
237 | ||
238 | status = s626_mc_test(dev, S626_MC2_UPLD_IIC, S626_P_MC2); | |
239 | if (status) | |
240 | return 0; | |
241 | return -EBUSY; | |
242 | } | |
243 | ||
244 | static int s626_i2c_handshake(struct comedi_device *dev, uint32_t val) | |
982e3d11 | 245 | { |
be008602 | 246 | unsigned int ctrl; |
571845c6 | 247 | int ret; |
7f2f7e05 | 248 | |
25f8fd5e | 249 | /* Write I2C command to I2C Transfer Control shadow register */ |
de9cd5ca | 250 | writel(val, dev->mmio + S626_P_I2CCTRL); |
982e3d11 | 251 | |
ddd9813e HS |
252 | /* |
253 | * Upload I2C shadow registers into working registers and | |
254 | * wait for upload confirmation. | |
255 | */ | |
d8515652 | 256 | s626_mc_enable(dev, S626_MC2_UPLD_IIC, S626_P_MC2); |
571845c6 CS |
257 | ret = comedi_timeout(dev, NULL, NULL, s626_i2c_handshake_eoc, 0); |
258 | if (ret) | |
259 | return ret; | |
982e3d11 | 260 | |
be008602 HS |
261 | /* Wait until I2C bus transfer is finished or an error occurs */ |
262 | do { | |
de9cd5ca | 263 | ctrl = readl(dev->mmio + S626_P_I2CCTRL); |
d8515652 | 264 | } while ((ctrl & (S626_I2C_BUSY | S626_I2C_ERR)) == S626_I2C_BUSY); |
982e3d11 | 265 | |
be008602 | 266 | /* Return non-zero if I2C error occurred */ |
d8515652 | 267 | return ctrl & S626_I2C_ERR; |
982e3d11 HS |
268 | } |
269 | ||
8ee52611 | 270 | /* Read uint8_t from EEPROM. */ |
31de1948 | 271 | static uint8_t s626_i2c_read(struct comedi_device *dev, uint8_t addr) |
982e3d11 | 272 | { |
7f2f7e05 | 273 | struct s626_private *devpriv = dev->private; |
982e3d11 | 274 | |
8ee52611 IA |
275 | /* |
276 | * Send EEPROM target address: | |
277 | * Byte2 = I2C command: write to I2C EEPROM device. | |
278 | * Byte1 = EEPROM internal target address. | |
279 | * Byte0 = Not sent. | |
280 | */ | |
d8515652 IA |
281 | if (s626_i2c_handshake(dev, S626_I2C_B2(S626_I2C_ATTRSTART, |
282 | devpriv->i2c_adrs) | | |
283 | S626_I2C_B1(S626_I2C_ATTRSTOP, addr) | | |
284 | S626_I2C_B0(S626_I2C_ATTRNOP, 0))) | |
8ee52611 | 285 | /* Abort function and declare error if handshake failed. */ |
982e3d11 | 286 | return 0; |
982e3d11 | 287 | |
8ee52611 IA |
288 | /* |
289 | * Execute EEPROM read: | |
290 | * Byte2 = I2C command: read from I2C EEPROM device. | |
291 | * Byte1 receives uint8_t from EEPROM. | |
292 | * Byte0 = Not sent. | |
293 | */ | |
d8515652 | 294 | if (s626_i2c_handshake(dev, S626_I2C_B2(S626_I2C_ATTRSTART, |
6c7d2c8b | 295 | (devpriv->i2c_adrs | 1)) | |
d8515652 IA |
296 | S626_I2C_B1(S626_I2C_ATTRSTOP, 0) | |
297 | S626_I2C_B0(S626_I2C_ATTRNOP, 0))) | |
8ee52611 | 298 | /* Abort function and declare error if handshake failed. */ |
982e3d11 | 299 | return 0; |
be008602 | 300 | |
de9cd5ca | 301 | return (readl(dev->mmio + S626_P_I2CCTRL) >> 16) & 0xff; |
982e3d11 HS |
302 | } |
303 | ||
95414729 HS |
304 | /* *********** DAC FUNCTIONS *********** */ |
305 | ||
8ee52611 | 306 | /* TrimDac LogicalChan-to-PhysicalChan mapping table. */ |
31de1948 | 307 | static const uint8_t s626_trimchan[] = { 10, 9, 8, 3, 2, 7, 6, 1, 0, 5, 4 }; |
95414729 | 308 | |
8ee52611 | 309 | /* TrimDac LogicalChan-to-EepromAdrs mapping table. */ |
31de1948 | 310 | static const uint8_t s626_trimadrs[] = { |
8ee52611 IA |
311 | 0x40, 0x41, 0x42, 0x50, 0x51, 0x52, 0x53, 0x60, 0x61, 0x62, 0x63 |
312 | }; | |
95414729 | 313 | |
59a32a46 CS |
314 | enum { |
315 | s626_send_dac_wait_not_mc1_a2out, | |
316 | s626_send_dac_wait_ssr_af2_out, | |
317 | s626_send_dac_wait_fb_buffer2_msb_00, | |
318 | s626_send_dac_wait_fb_buffer2_msb_ff | |
319 | }; | |
320 | ||
321 | static int s626_send_dac_eoc(struct comedi_device *dev, | |
322 | struct comedi_subdevice *s, | |
323 | struct comedi_insn *insn, | |
324 | unsigned long context) | |
325 | { | |
59a32a46 CS |
326 | unsigned int status; |
327 | ||
328 | switch (context) { | |
329 | case s626_send_dac_wait_not_mc1_a2out: | |
de9cd5ca | 330 | status = readl(dev->mmio + S626_P_MC1); |
59a32a46 CS |
331 | if (!(status & S626_MC1_A2OUT)) |
332 | return 0; | |
333 | break; | |
334 | case s626_send_dac_wait_ssr_af2_out: | |
de9cd5ca | 335 | status = readl(dev->mmio + S626_P_SSR); |
59a32a46 CS |
336 | if (status & S626_SSR_AF2_OUT) |
337 | return 0; | |
338 | break; | |
339 | case s626_send_dac_wait_fb_buffer2_msb_00: | |
de9cd5ca | 340 | status = readl(dev->mmio + S626_P_FB_BUFFER2); |
59a32a46 CS |
341 | if (!(status & 0xff000000)) |
342 | return 0; | |
343 | break; | |
344 | case s626_send_dac_wait_fb_buffer2_msb_ff: | |
de9cd5ca | 345 | status = readl(dev->mmio + S626_P_FB_BUFFER2); |
59a32a46 CS |
346 | if (status & 0xff000000) |
347 | return 0; | |
348 | break; | |
349 | default: | |
350 | return -EINVAL; | |
351 | } | |
352 | return -EBUSY; | |
353 | } | |
354 | ||
8ee52611 IA |
355 | /* |
356 | * Private helper function: Transmit serial data to DAC via Audio | |
95414729 | 357 | * channel 2. Assumes: (1) TSL2 slot records initialized, and (2) |
07a36d66 | 358 | * dacpol contains valid target image. |
95414729 | 359 | */ |
a7aa94ce | 360 | static int s626_send_dac(struct comedi_device *dev, uint32_t val) |
95414729 | 361 | { |
7f2f7e05 | 362 | struct s626_private *devpriv = dev->private; |
59a32a46 | 363 | int ret; |
95414729 HS |
364 | |
365 | /* START THE SERIAL CLOCK RUNNING ------------- */ | |
366 | ||
8ee52611 IA |
367 | /* |
368 | * Assert DAC polarity control and enable gating of DAC serial clock | |
95414729 HS |
369 | * and audio bit stream signals. At this point in time we must be |
370 | * assured of being in time slot 0. If we are not in slot 0, the | |
371 | * serial clock and audio stream signals will be disabled; this is | |
31de1948 IA |
372 | * because the following s626_debi_write statement (which enables |
373 | * signals to be passed through the gate array) would execute before | |
374 | * the trailing edge of WS1/WS3 (which turns off the signals), thus | |
95414729 HS |
375 | * causing the signals to be inactive during the DAC write. |
376 | */ | |
d8515652 | 377 | s626_debi_write(dev, S626_LP_DACPOL, devpriv->dacpol); |
95414729 HS |
378 | |
379 | /* TRANSFER OUTPUT DWORD VALUE INTO A2'S OUTPUT FIFO ---------------- */ | |
380 | ||
381 | /* Copy DAC setpoint value to DAC's output DMA buffer. */ | |
de9cd5ca | 382 | /* writel(val, dev->mmio + (uint32_t)devpriv->dac_wbuf); */ |
07a36d66 | 383 | *devpriv->dac_wbuf = val; |
95414729 | 384 | |
ddd9813e HS |
385 | /* |
386 | * Enable the output DMA transfer. This will cause the DMAC to copy | |
387 | * the DAC's data value to A2's output FIFO. The DMA transfer will | |
95414729 HS |
388 | * then immediately terminate because the protection address is |
389 | * reached upon transfer of the first DWORD value. | |
390 | */ | |
d8515652 | 391 | s626_mc_enable(dev, S626_MC1_A2OUT, S626_P_MC1); |
95414729 | 392 | |
8ee52611 | 393 | /* While the DMA transfer is executing ... */ |
95414729 | 394 | |
25f8fd5e HS |
395 | /* |
396 | * Reset Audio2 output FIFO's underflow flag (along with any | |
397 | * other FIFO underflow/overflow flags). When set, this flag | |
398 | * will indicate that we have emerged from slot 0. | |
95414729 | 399 | */ |
de9cd5ca | 400 | writel(S626_ISR_AFOU, dev->mmio + S626_P_ISR); |
95414729 | 401 | |
8ee52611 IA |
402 | /* |
403 | * Wait for the DMA transfer to finish so that there will be data | |
95414729 HS |
404 | * available in the FIFO when time slot 1 tries to transfer a DWORD |
405 | * from the FIFO to the output buffer register. We test for DMA | |
406 | * Done by polling the DMAC enable flag; this flag is automatically | |
407 | * cleared when the transfer has finished. | |
408 | */ | |
59a32a46 CS |
409 | ret = comedi_timeout(dev, NULL, NULL, s626_send_dac_eoc, |
410 | s626_send_dac_wait_not_mc1_a2out); | |
a7aa94ce | 411 | if (ret) { |
cefe9336 | 412 | dev_err(dev->class_dev, "DMA transfer timeout\n"); |
a7aa94ce CS |
413 | return ret; |
414 | } | |
95414729 HS |
415 | |
416 | /* START THE OUTPUT STREAM TO THE TARGET DAC -------------------- */ | |
417 | ||
8ee52611 IA |
418 | /* |
419 | * FIFO data is now available, so we enable execution of time slots | |
95414729 HS |
420 | * 1 and higher by clearing the EOS flag in slot 0. Note that SD3 |
421 | * will be shifted in and stored in FB_BUFFER2 for end-of-slot-list | |
422 | * detection. | |
423 | */ | |
d8515652 | 424 | writel(S626_XSD2 | S626_RSD3 | S626_SIB_A2, |
de9cd5ca | 425 | dev->mmio + S626_VECTPORT(0)); |
95414729 | 426 | |
8ee52611 IA |
427 | /* |
428 | * Wait for slot 1 to execute to ensure that the Packet will be | |
95414729 HS |
429 | * transmitted. This is detected by polling the Audio2 output FIFO |
430 | * underflow flag, which will be set when slot 1 execution has | |
431 | * finished transferring the DAC's data DWORD from the output FIFO | |
432 | * to the output buffer register. | |
433 | */ | |
59a32a46 CS |
434 | ret = comedi_timeout(dev, NULL, NULL, s626_send_dac_eoc, |
435 | s626_send_dac_wait_ssr_af2_out); | |
a7aa94ce | 436 | if (ret) { |
cefe9336 HS |
437 | dev_err(dev->class_dev, |
438 | "TSL timeout waiting for slot 1 to execute\n"); | |
a7aa94ce CS |
439 | return ret; |
440 | } | |
95414729 | 441 | |
8ee52611 IA |
442 | /* |
443 | * Set up to trap execution at slot 0 when the TSL sequencer cycles | |
95414729 HS |
444 | * back to slot 0 after executing the EOS in slot 5. Also, |
445 | * simultaneously shift out and in the 0x00 that is ALWAYS the value | |
446 | * stored in the last byte to be shifted out of the FIFO's DWORD | |
447 | * buffer register. | |
448 | */ | |
d8515652 | 449 | writel(S626_XSD2 | S626_XFIFO_2 | S626_RSD2 | S626_SIB_A2 | S626_EOS, |
de9cd5ca | 450 | dev->mmio + S626_VECTPORT(0)); |
95414729 HS |
451 | |
452 | /* WAIT FOR THE TRANSACTION TO FINISH ----------------------- */ | |
453 | ||
8ee52611 IA |
454 | /* |
455 | * Wait for the TSL to finish executing all time slots before | |
95414729 HS |
456 | * exiting this function. We must do this so that the next DAC |
457 | * write doesn't start, thereby enabling clock/chip select signals: | |
458 | * | |
459 | * 1. Before the TSL sequence cycles back to slot 0, which disables | |
460 | * the clock/cs signal gating and traps slot // list execution. | |
461 | * we have not yet finished slot 5 then the clock/cs signals are | |
462 | * still gated and we have not finished transmitting the stream. | |
463 | * | |
464 | * 2. While slots 2-5 are executing due to a late slot 0 trap. In | |
465 | * this case, the slot sequence is currently repeating, but with | |
466 | * clock/cs signals disabled. We must wait for slot 0 to trap | |
467 | * execution before setting up the next DAC setpoint DMA transfer | |
468 | * and enabling the clock/cs signals. To detect the end of slot 5, | |
469 | * we test for the FB_BUFFER2 MSB contents to be equal to 0xFF. If | |
470 | * the TSL has not yet finished executing slot 5 ... | |
471 | */ | |
de9cd5ca | 472 | if (readl(dev->mmio + S626_P_FB_BUFFER2) & 0xff000000) { |
8ee52611 IA |
473 | /* |
474 | * The trap was set on time and we are still executing somewhere | |
95414729 HS |
475 | * in slots 2-5, so we now wait for slot 0 to execute and trap |
476 | * TSL execution. This is detected when FB_BUFFER2 MSB changes | |
477 | * from 0xFF to 0x00, which slot 0 causes to happen by shifting | |
478 | * out/in on SD2 the 0x00 that is always referenced by slot 5. | |
479 | */ | |
59a32a46 CS |
480 | ret = comedi_timeout(dev, NULL, NULL, s626_send_dac_eoc, |
481 | s626_send_dac_wait_fb_buffer2_msb_00); | |
a7aa94ce | 482 | if (ret) { |
cefe9336 HS |
483 | dev_err(dev->class_dev, |
484 | "TSL timeout waiting for slot 0 to execute\n"); | |
a7aa94ce CS |
485 | return ret; |
486 | } | |
95414729 | 487 | } |
8ee52611 IA |
488 | /* |
489 | * Either (1) we were too late setting the slot 0 trap; the TSL | |
95414729 HS |
490 | * sequencer restarted slot 0 before we could set the EOS trap flag, |
491 | * or (2) we were not late and execution is now trapped at slot 0. | |
492 | * In either case, we must now change slot 0 so that it will store | |
493 | * value 0xFF (instead of 0x00) to FB_BUFFER2 next time it executes. | |
494 | * In order to do this, we reprogram slot 0 so that it will shift in | |
495 | * SD3, which is driven only by a pull-up resistor. | |
496 | */ | |
d8515652 | 497 | writel(S626_RSD3 | S626_SIB_A2 | S626_EOS, |
de9cd5ca | 498 | dev->mmio + S626_VECTPORT(0)); |
95414729 | 499 | |
8ee52611 IA |
500 | /* |
501 | * Wait for slot 0 to execute, at which time the TSL is setup for | |
95414729 HS |
502 | * the next DAC write. This is detected when FB_BUFFER2 MSB changes |
503 | * from 0x00 to 0xFF. | |
504 | */ | |
59a32a46 CS |
505 | ret = comedi_timeout(dev, NULL, NULL, s626_send_dac_eoc, |
506 | s626_send_dac_wait_fb_buffer2_msb_ff); | |
a7aa94ce | 507 | if (ret) { |
cefe9336 HS |
508 | dev_err(dev->class_dev, |
509 | "TSL timeout waiting for slot 0 to execute\n"); | |
a7aa94ce CS |
510 | return ret; |
511 | } | |
512 | return 0; | |
95414729 HS |
513 | } |
514 | ||
8ee52611 IA |
515 | /* |
516 | * Private helper function: Write setpoint to an application DAC channel. | |
517 | */ | |
6c7d2c8b HS |
518 | static int s626_set_dac(struct comedi_device *dev, |
519 | uint16_t chan, int16_t dacdata) | |
95414729 | 520 | { |
7f2f7e05 | 521 | struct s626_private *devpriv = dev->private; |
8ee52611 | 522 | uint16_t signmask; |
f1f7efce | 523 | uint32_t ws_image; |
8ee52611 | 524 | uint32_t val; |
95414729 | 525 | |
8ee52611 IA |
526 | /* |
527 | * Adjust DAC data polarity and set up Polarity Control Register image. | |
528 | */ | |
95414729 HS |
529 | signmask = 1 << chan; |
530 | if (dacdata < 0) { | |
531 | dacdata = -dacdata; | |
07a36d66 | 532 | devpriv->dacpol |= signmask; |
8ee52611 | 533 | } else { |
07a36d66 | 534 | devpriv->dacpol &= ~signmask; |
8ee52611 | 535 | } |
95414729 | 536 | |
8ee52611 IA |
537 | /* Limit DAC setpoint value to valid range. */ |
538 | if ((uint16_t)dacdata > 0x1FFF) | |
95414729 HS |
539 | dacdata = 0x1FFF; |
540 | ||
8ee52611 IA |
541 | /* |
542 | * Set up TSL2 records (aka "vectors") for DAC update. Vectors V2 | |
95414729 HS |
543 | * and V3 transmit the setpoint to the target DAC. V4 and V5 send |
544 | * data to a non-existent TrimDac channel just to keep the clock | |
545 | * running after sending data to the target DAC. This is necessary | |
546 | * to eliminate the clock glitch that would otherwise occur at the | |
547 | * end of the target DAC's serial data stream. When the sequence | |
548 | * restarts at V0 (after executing V5), the gate array automatically | |
549 | * disables gating for the DAC clock and all DAC chip selects. | |
550 | */ | |
551 | ||
25f8fd5e | 552 | /* Choose DAC chip select to be asserted */ |
d8515652 | 553 | ws_image = (chan & 2) ? S626_WS1 : S626_WS2; |
25f8fd5e | 554 | /* Slot 2: Transmit high data byte to target DAC */ |
d8515652 | 555 | writel(S626_XSD2 | S626_XFIFO_1 | ws_image, |
de9cd5ca | 556 | dev->mmio + S626_VECTPORT(2)); |
25f8fd5e | 557 | /* Slot 3: Transmit low data byte to target DAC */ |
d8515652 | 558 | writel(S626_XSD2 | S626_XFIFO_0 | ws_image, |
de9cd5ca | 559 | dev->mmio + S626_VECTPORT(3)); |
95414729 | 560 | /* Slot 4: Transmit to non-existent TrimDac channel to keep clock */ |
d8515652 | 561 | writel(S626_XSD2 | S626_XFIFO_3 | S626_WS3, |
de9cd5ca | 562 | dev->mmio + S626_VECTPORT(4)); |
25f8fd5e | 563 | /* Slot 5: running after writing target DAC's low data byte */ |
d8515652 | 564 | writel(S626_XSD2 | S626_XFIFO_2 | S626_WS3 | S626_EOS, |
de9cd5ca | 565 | dev->mmio + S626_VECTPORT(5)); |
95414729 | 566 | |
8ee52611 IA |
567 | /* |
568 | * Construct and transmit target DAC's serial packet: | |
569 | * (A10D DDDD), (DDDD DDDD), (0x0F), (0x00) where A is chan<0>, | |
95414729 HS |
570 | * and D<12:0> is the DAC setpoint. Append a WORD value (that writes |
571 | * to a non-existent TrimDac channel) that serves to keep the clock | |
572 | * running after the packet has been sent to the target DAC. | |
573 | */ | |
8ee52611 IA |
574 | val = 0x0F000000; /* Continue clock after target DAC data |
575 | * (write to non-existent trimdac). */ | |
576 | val |= 0x00004000; /* Address the two main dual-DAC devices | |
577 | * (TSL's chip select enables target device). */ | |
578 | val |= ((uint32_t)(chan & 1) << 15); /* Address the DAC channel | |
579 | * within the device. */ | |
580 | val |= (uint32_t)dacdata; /* Include DAC setpoint data. */ | |
a7aa94ce | 581 | return s626_send_dac(dev, val); |
95414729 HS |
582 | } |
583 | ||
6c7d2c8b HS |
584 | static int s626_write_trim_dac(struct comedi_device *dev, |
585 | uint8_t logical_chan, uint8_t dac_data) | |
95414729 | 586 | { |
7f2f7e05 | 587 | struct s626_private *devpriv = dev->private; |
95414729 HS |
588 | uint32_t chan; |
589 | ||
8ee52611 IA |
590 | /* |
591 | * Save the new setpoint in case the application needs to read it back | |
592 | * later. | |
593 | */ | |
f1f7efce | 594 | devpriv->trim_setpoint[logical_chan] = (uint8_t)dac_data; |
95414729 | 595 | |
8ee52611 | 596 | /* Map logical channel number to physical channel number. */ |
31de1948 | 597 | chan = s626_trimchan[logical_chan]; |
95414729 | 598 | |
8ee52611 IA |
599 | /* |
600 | * Set up TSL2 records for TrimDac write operation. All slots shift | |
95414729 HS |
601 | * 0xFF in from pulled-up SD3 so that the end of the slot sequence |
602 | * can be detected. | |
603 | */ | |
604 | ||
25f8fd5e | 605 | /* Slot 2: Send high uint8_t to target TrimDac */ |
d8515652 | 606 | writel(S626_XSD2 | S626_XFIFO_1 | S626_WS3, |
de9cd5ca | 607 | dev->mmio + S626_VECTPORT(2)); |
25f8fd5e | 608 | /* Slot 3: Send low uint8_t to target TrimDac */ |
d8515652 | 609 | writel(S626_XSD2 | S626_XFIFO_0 | S626_WS3, |
de9cd5ca | 610 | dev->mmio + S626_VECTPORT(3)); |
25f8fd5e | 611 | /* Slot 4: Send NOP high uint8_t to DAC0 to keep clock running */ |
d8515652 | 612 | writel(S626_XSD2 | S626_XFIFO_3 | S626_WS1, |
de9cd5ca | 613 | dev->mmio + S626_VECTPORT(4)); |
25f8fd5e | 614 | /* Slot 5: Send NOP low uint8_t to DAC0 */ |
d8515652 | 615 | writel(S626_XSD2 | S626_XFIFO_2 | S626_WS1 | S626_EOS, |
de9cd5ca | 616 | dev->mmio + S626_VECTPORT(5)); |
95414729 | 617 | |
8ee52611 IA |
618 | /* |
619 | * Construct and transmit target DAC's serial packet: | |
620 | * (0000 AAAA), (DDDD DDDD), (0x00), (0x00) where A<3:0> is the | |
95414729 HS |
621 | * DAC channel's address, and D<7:0> is the DAC setpoint. Append a |
622 | * WORD value (that writes a channel 0 NOP command to a non-existent | |
623 | * main DAC channel) that serves to keep the clock running after the | |
624 | * packet has been sent to the target DAC. | |
625 | */ | |
626 | ||
8ee52611 IA |
627 | /* |
628 | * Address the DAC channel within the trimdac device. | |
629 | * Include DAC setpoint data. | |
630 | */ | |
a7aa94ce | 631 | return s626_send_dac(dev, (chan << 8) | dac_data); |
95414729 HS |
632 | } |
633 | ||
a7aa94ce | 634 | static int s626_load_trim_dacs(struct comedi_device *dev) |
95414729 | 635 | { |
8ee52611 | 636 | uint8_t i; |
a7aa94ce | 637 | int ret; |
95414729 | 638 | |
8ee52611 | 639 | /* Copy TrimDac setpoint values from EEPROM to TrimDacs. */ |
a7aa94ce CS |
640 | for (i = 0; i < ARRAY_SIZE(s626_trimchan); i++) { |
641 | ret = s626_write_trim_dac(dev, i, | |
6c7d2c8b | 642 | s626_i2c_read(dev, s626_trimadrs[i])); |
a7aa94ce CS |
643 | if (ret) |
644 | return ret; | |
645 | } | |
646 | return 0; | |
95414729 HS |
647 | } |
648 | ||
e3eb08d0 | 649 | /* ****** COUNTER FUNCTIONS ******* */ |
8ee52611 IA |
650 | |
651 | /* | |
652 | * All counter functions address a specific counter by means of the | |
e3eb08d0 HS |
653 | * "Counter" argument, which is a logical counter number. The Counter |
654 | * argument may have any of the following legal values: 0=0A, 1=1A, | |
655 | * 2=2A, 3=0B, 4=1B, 5=2B. | |
656 | */ | |
657 | ||
8ee52611 IA |
658 | /* |
659 | * Return/set a counter pair's latch trigger source. 0: On read | |
e3eb08d0 HS |
660 | * access, 1: A index latches A, 2: B index latches B, 3: A overflow |
661 | * latches B. | |
662 | */ | |
31de1948 | 663 | static void s626_set_latch_source(struct comedi_device *dev, |
0c9a057c | 664 | unsigned int chan, uint16_t value) |
e3eb08d0 | 665 | { |
0c9a057c | 666 | s626_debi_replace(dev, S626_LP_CRB(chan), |
d8515652 | 667 | ~(S626_CRBMSK_INTCTRL | S626_CRBMSK_LATCHSRC), |
0830ada5 | 668 | S626_SET_CRB_LATCHSRC(value)); |
e3eb08d0 HS |
669 | } |
670 | ||
8ee52611 IA |
671 | /* |
672 | * Write value into counter preload register. | |
673 | */ | |
31de1948 | 674 | static void s626_preload(struct comedi_device *dev, |
0c9a057c | 675 | unsigned int chan, uint32_t value) |
e3eb08d0 | 676 | { |
0c9a057c HS |
677 | s626_debi_write(dev, S626_LP_CNTR(chan), value); |
678 | s626_debi_write(dev, S626_LP_CNTR(chan) + 2, value >> 16); | |
e3eb08d0 HS |
679 | } |
680 | ||
010be96f IA |
681 | /* ****** PRIVATE COUNTER FUNCTIONS ****** */ |
682 | ||
683 | /* | |
684 | * Reset a counter's index and overflow event capture flags. | |
685 | */ | |
26499b8b | 686 | static void s626_reset_cap_flags(struct comedi_device *dev, |
0c9a057c | 687 | unsigned int chan) |
010be96f | 688 | { |
26499b8b | 689 | uint16_t set; |
010be96f | 690 | |
26499b8b | 691 | set = S626_SET_CRB_INTRESETCMD(1); |
0c9a057c | 692 | if (chan < 3) |
26499b8b HS |
693 | set |= S626_SET_CRB_INTRESET_A(1); |
694 | else | |
695 | set |= S626_SET_CRB_INTRESET_B(1); | |
696 | ||
0c9a057c | 697 | s626_debi_replace(dev, S626_LP_CRB(chan), ~S626_CRBMSK_INTCTRL, set); |
010be96f IA |
698 | } |
699 | ||
0a984491 | 700 | #ifdef unused |
010be96f IA |
701 | /* |
702 | * Return counter setup in a format (COUNTER_SETUP) that is consistent | |
703 | * for both A and B counters. | |
704 | */ | |
31de1948 | 705 | static uint16_t s626_get_mode_a(struct comedi_device *dev, |
0c9a057c | 706 | unsigned int chan) |
010be96f IA |
707 | { |
708 | uint16_t cra; | |
709 | uint16_t crb; | |
710 | uint16_t setup; | |
f7ede00d | 711 | unsigned int cntsrc, clkmult, clkpol, encmode; |
010be96f IA |
712 | |
713 | /* Fetch CRA and CRB register images. */ | |
0c9a057c HS |
714 | cra = s626_debi_read(dev, S626_LP_CRA(chan)); |
715 | crb = s626_debi_read(dev, S626_LP_CRB(chan)); | |
010be96f IA |
716 | |
717 | /* | |
718 | * Populate the standardized counter setup bit fields. | |
010be96f | 719 | */ |
0830ada5 IA |
720 | setup = |
721 | /* LoadSrc = LoadSrcA. */ | |
722 | S626_SET_STD_LOADSRC(S626_GET_CRA_LOADSRC_A(cra)) | | |
723 | /* LatchSrc = LatchSrcA. */ | |
724 | S626_SET_STD_LATCHSRC(S626_GET_CRB_LATCHSRC(crb)) | | |
725 | /* IntSrc = IntSrcA. */ | |
726 | S626_SET_STD_INTSRC(S626_GET_CRA_INTSRC_A(cra)) | | |
2cea19fa IA |
727 | /* IndxSrc = IndxSrcA. */ |
728 | S626_SET_STD_INDXSRC(S626_GET_CRA_INDXSRC_A(cra)) | | |
0830ada5 IA |
729 | /* IndxPol = IndxPolA. */ |
730 | S626_SET_STD_INDXPOL(S626_GET_CRA_INDXPOL_A(cra)) | | |
731 | /* ClkEnab = ClkEnabA. */ | |
732 | S626_SET_STD_CLKENAB(S626_GET_CRB_CLKENAB_A(crb)); | |
010be96f IA |
733 | |
734 | /* Adjust mode-dependent parameters. */ | |
0830ada5 IA |
735 | cntsrc = S626_GET_CRA_CNTSRC_A(cra); |
736 | if (cntsrc & S626_CNTSRC_SYSCLK) { | |
622ec01a | 737 | /* Timer mode (CntSrcA<1> == 1): */ |
0830ada5 | 738 | encmode = S626_ENCMODE_TIMER; |
622ec01a | 739 | /* Set ClkPol to indicate count direction (CntSrcA<0>). */ |
0830ada5 | 740 | clkpol = cntsrc & 1; |
010be96f | 741 | /* ClkMult must be 1x in Timer mode. */ |
7a1046e5 | 742 | clkmult = S626_CLKMULT_1X; |
010be96f | 743 | } else { |
622ec01a | 744 | /* Counter mode (CntSrcA<1> == 0): */ |
0830ada5 | 745 | encmode = S626_ENCMODE_COUNTER; |
010be96f | 746 | /* Pass through ClkPol. */ |
0830ada5 | 747 | clkpol = S626_GET_CRA_CLKPOL_A(cra); |
010be96f | 748 | /* Force ClkMult to 1x if not legal, else pass through. */ |
0830ada5 | 749 | clkmult = S626_GET_CRA_CLKMULT_A(cra); |
7a1046e5 IA |
750 | if (clkmult == S626_CLKMULT_SPECIAL) |
751 | clkmult = S626_CLKMULT_1X; | |
010be96f | 752 | } |
0830ada5 IA |
753 | setup |= S626_SET_STD_ENCMODE(encmode) | S626_SET_STD_CLKMULT(clkmult) | |
754 | S626_SET_STD_CLKPOL(clkpol); | |
010be96f IA |
755 | |
756 | /* Return adjusted counter setup. */ | |
757 | return setup; | |
758 | } | |
759 | ||
31de1948 | 760 | static uint16_t s626_get_mode_b(struct comedi_device *dev, |
0c9a057c | 761 | unsigned int chan) |
010be96f IA |
762 | { |
763 | uint16_t cra; | |
764 | uint16_t crb; | |
765 | uint16_t setup; | |
f7ede00d | 766 | unsigned int cntsrc, clkmult, clkpol, encmode; |
010be96f IA |
767 | |
768 | /* Fetch CRA and CRB register images. */ | |
0c9a057c HS |
769 | cra = s626_debi_read(dev, S626_LP_CRA(chan)); |
770 | crb = s626_debi_read(dev, S626_LP_CRB(chan)); | |
010be96f IA |
771 | |
772 | /* | |
773 | * Populate the standardized counter setup bit fields. | |
010be96f | 774 | */ |
0830ada5 IA |
775 | setup = |
776 | /* IntSrc = IntSrcB. */ | |
777 | S626_SET_STD_INTSRC(S626_GET_CRB_INTSRC_B(crb)) | | |
778 | /* LatchSrc = LatchSrcB. */ | |
779 | S626_SET_STD_LATCHSRC(S626_GET_CRB_LATCHSRC(crb)) | | |
780 | /* LoadSrc = LoadSrcB. */ | |
781 | S626_SET_STD_LOADSRC(S626_GET_CRB_LOADSRC_B(crb)) | | |
782 | /* IndxPol = IndxPolB. */ | |
783 | S626_SET_STD_INDXPOL(S626_GET_CRB_INDXPOL_B(crb)) | | |
784 | /* ClkEnab = ClkEnabB. */ | |
785 | S626_SET_STD_CLKENAB(S626_GET_CRB_CLKENAB_B(crb)) | | |
2cea19fa IA |
786 | /* IndxSrc = IndxSrcB. */ |
787 | S626_SET_STD_INDXSRC(S626_GET_CRA_INDXSRC_B(cra)); | |
010be96f IA |
788 | |
789 | /* Adjust mode-dependent parameters. */ | |
0830ada5 IA |
790 | cntsrc = S626_GET_CRA_CNTSRC_B(cra); |
791 | clkmult = S626_GET_CRB_CLKMULT_B(crb); | |
7a1046e5 IA |
792 | if (clkmult == S626_CLKMULT_SPECIAL) { |
793 | /* Extender mode (ClkMultB == S626_CLKMULT_SPECIAL): */ | |
0830ada5 | 794 | encmode = S626_ENCMODE_EXTENDER; |
010be96f | 795 | /* Indicate multiplier is 1x. */ |
7a1046e5 | 796 | clkmult = S626_CLKMULT_1X; |
622ec01a | 797 | /* Set ClkPol equal to Timer count direction (CntSrcB<0>). */ |
0830ada5 IA |
798 | clkpol = cntsrc & 1; |
799 | } else if (cntsrc & S626_CNTSRC_SYSCLK) { | |
622ec01a | 800 | /* Timer mode (CntSrcB<1> == 1): */ |
0830ada5 | 801 | encmode = S626_ENCMODE_TIMER; |
010be96f | 802 | /* Indicate multiplier is 1x. */ |
7a1046e5 | 803 | clkmult = S626_CLKMULT_1X; |
622ec01a | 804 | /* Set ClkPol equal to Timer count direction (CntSrcB<0>). */ |
0830ada5 | 805 | clkpol = cntsrc & 1; |
010be96f | 806 | } else { |
622ec01a | 807 | /* If Counter mode (CntSrcB<1> == 0): */ |
0830ada5 | 808 | encmode = S626_ENCMODE_COUNTER; |
010be96f | 809 | /* Clock multiplier is passed through. */ |
010be96f | 810 | /* Clock polarity is passed through. */ |
0830ada5 | 811 | clkpol = S626_GET_CRB_CLKPOL_B(crb); |
010be96f | 812 | } |
0830ada5 IA |
813 | setup |= S626_SET_STD_ENCMODE(encmode) | S626_SET_STD_CLKMULT(clkmult) | |
814 | S626_SET_STD_CLKPOL(clkpol); | |
010be96f IA |
815 | |
816 | /* Return adjusted counter setup. */ | |
817 | return setup; | |
818 | } | |
819 | ||
0a984491 | 820 | static uint16_t s626_get_mode(struct comedi_device *dev, |
0c9a057c | 821 | unsigned int chan) |
0a984491 | 822 | { |
193725ba HS |
823 | return (chan < 3) ? s626_get_mode_a(dev, chan) |
824 | : s626_get_mode_b(dev, chan); | |
0a984491 HS |
825 | } |
826 | #endif | |
827 | ||
17afeac2 IA |
828 | /* |
829 | * Set the operating mode for the specified counter. The setup | |
830 | * parameter is treated as a COUNTER_SETUP data type. The following | |
831 | * parameters are programmable (all other parms are ignored): ClkMult, | |
832 | * ClkPol, ClkEnab, IndexSrc, IndexPol, LoadSrc. | |
833 | */ | |
31de1948 | 834 | static void s626_set_mode_a(struct comedi_device *dev, |
0c9a057c | 835 | unsigned int chan, uint16_t setup, |
31de1948 | 836 | uint16_t disable_int_src) |
17afeac2 IA |
837 | { |
838 | struct s626_private *devpriv = dev->private; | |
839 | uint16_t cra; | |
840 | uint16_t crb; | |
f7ede00d | 841 | unsigned int cntsrc, clkmult, clkpol; |
17afeac2 IA |
842 | |
843 | /* Initialize CRA and CRB images. */ | |
844 | /* Preload trigger is passed through. */ | |
0830ada5 | 845 | cra = S626_SET_CRA_LOADSRC_A(S626_GET_STD_LOADSRC(setup)); |
2cea19fa IA |
846 | /* IndexSrc is passed through. */ |
847 | cra |= S626_SET_CRA_INDXSRC_A(S626_GET_STD_INDXSRC(setup)); | |
17afeac2 IA |
848 | |
849 | /* Reset any pending CounterA event captures. */ | |
0830ada5 | 850 | crb = S626_SET_CRB_INTRESETCMD(1) | S626_SET_CRB_INTRESET_A(1); |
17afeac2 | 851 | /* Clock enable is passed through. */ |
0830ada5 | 852 | crb |= S626_SET_CRB_CLKENAB_A(S626_GET_STD_CLKENAB(setup)); |
17afeac2 IA |
853 | |
854 | /* Force IntSrc to Disabled if disable_int_src is asserted. */ | |
855 | if (!disable_int_src) | |
0830ada5 | 856 | cra |= S626_SET_CRA_INTSRC_A(S626_GET_STD_INTSRC(setup)); |
17afeac2 IA |
857 | |
858 | /* Populate all mode-dependent attributes of CRA & CRB images. */ | |
0830ada5 IA |
859 | clkpol = S626_GET_STD_CLKPOL(setup); |
860 | switch (S626_GET_STD_ENCMODE(setup)) { | |
622ec01a | 861 | case S626_ENCMODE_EXTENDER: /* Extender Mode: */ |
d8515652 | 862 | /* Force to Timer mode (Extender valid only for B counters). */ |
622ec01a IA |
863 | /* Fall through to case S626_ENCMODE_TIMER: */ |
864 | case S626_ENCMODE_TIMER: /* Timer Mode: */ | |
865 | /* CntSrcA<1> selects system clock */ | |
0830ada5 | 866 | cntsrc = S626_CNTSRC_SYSCLK; |
622ec01a | 867 | /* Count direction (CntSrcA<0>) obtained from ClkPol. */ |
0830ada5 | 868 | cntsrc |= clkpol; |
17afeac2 | 869 | /* ClkPolA behaves as always-on clock enable. */ |
0830ada5 | 870 | clkpol = 1; |
17afeac2 | 871 | /* ClkMult must be 1x. */ |
7a1046e5 | 872 | clkmult = S626_CLKMULT_1X; |
17afeac2 IA |
873 | break; |
874 | default: /* Counter Mode: */ | |
875 | /* Select ENC_C and ENC_D as clock/direction inputs. */ | |
0830ada5 | 876 | cntsrc = S626_CNTSRC_ENCODER; |
17afeac2 | 877 | /* Clock polarity is passed through. */ |
17afeac2 | 878 | /* Force multiplier to x1 if not legal, else pass through. */ |
0830ada5 | 879 | clkmult = S626_GET_STD_CLKMULT(setup); |
7a1046e5 IA |
880 | if (clkmult == S626_CLKMULT_SPECIAL) |
881 | clkmult = S626_CLKMULT_1X; | |
17afeac2 IA |
882 | break; |
883 | } | |
0830ada5 IA |
884 | cra |= S626_SET_CRA_CNTSRC_A(cntsrc) | S626_SET_CRA_CLKPOL_A(clkpol) | |
885 | S626_SET_CRA_CLKMULT_A(clkmult); | |
17afeac2 IA |
886 | |
887 | /* | |
888 | * Force positive index polarity if IndxSrc is software-driven only, | |
889 | * otherwise pass it through. | |
890 | */ | |
2cea19fa | 891 | if (S626_GET_STD_INDXSRC(setup) != S626_INDXSRC_SOFT) |
0830ada5 | 892 | cra |= S626_SET_CRA_INDXPOL_A(S626_GET_STD_INDXPOL(setup)); |
17afeac2 IA |
893 | |
894 | /* | |
895 | * If IntSrc has been forced to Disabled, update the MISC2 interrupt | |
896 | * enable mask to indicate the counter interrupt is disabled. | |
897 | */ | |
898 | if (disable_int_src) | |
0c9a057c HS |
899 | devpriv->counter_int_enabs &= ~(S626_OVERMASK(chan) | |
900 | S626_INDXMASK(chan)); | |
17afeac2 IA |
901 | |
902 | /* | |
903 | * While retaining CounterB and LatchSrc configurations, program the | |
904 | * new counter operating mode. | |
905 | */ | |
0c9a057c | 906 | s626_debi_replace(dev, S626_LP_CRA(chan), |
622ec01a | 907 | S626_CRAMSK_INDXSRC_B | S626_CRAMSK_CNTSRC_B, cra); |
0c9a057c | 908 | s626_debi_replace(dev, S626_LP_CRB(chan), |
d8515652 | 909 | ~(S626_CRBMSK_INTCTRL | S626_CRBMSK_CLKENAB_A), crb); |
17afeac2 IA |
910 | } |
911 | ||
31de1948 | 912 | static void s626_set_mode_b(struct comedi_device *dev, |
0c9a057c | 913 | unsigned int chan, uint16_t setup, |
31de1948 | 914 | uint16_t disable_int_src) |
17afeac2 IA |
915 | { |
916 | struct s626_private *devpriv = dev->private; | |
917 | uint16_t cra; | |
918 | uint16_t crb; | |
f7ede00d | 919 | unsigned int cntsrc, clkmult, clkpol; |
17afeac2 IA |
920 | |
921 | /* Initialize CRA and CRB images. */ | |
2cea19fa IA |
922 | /* IndexSrc is passed through. */ |
923 | cra = S626_SET_CRA_INDXSRC_B(S626_GET_STD_INDXSRC(setup)); | |
17afeac2 IA |
924 | |
925 | /* Reset event captures and disable interrupts. */ | |
0830ada5 | 926 | crb = S626_SET_CRB_INTRESETCMD(1) | S626_SET_CRB_INTRESET_B(1); |
17afeac2 | 927 | /* Clock enable is passed through. */ |
0830ada5 | 928 | crb |= S626_SET_CRB_CLKENAB_B(S626_GET_STD_CLKENAB(setup)); |
17afeac2 | 929 | /* Preload trigger source is passed through. */ |
0830ada5 | 930 | crb |= S626_SET_CRB_LOADSRC_B(S626_GET_STD_LOADSRC(setup)); |
17afeac2 IA |
931 | |
932 | /* Force IntSrc to Disabled if disable_int_src is asserted. */ | |
933 | if (!disable_int_src) | |
0830ada5 | 934 | crb |= S626_SET_CRB_INTSRC_B(S626_GET_STD_INTSRC(setup)); |
17afeac2 IA |
935 | |
936 | /* Populate all mode-dependent attributes of CRA & CRB images. */ | |
0830ada5 IA |
937 | clkpol = S626_GET_STD_CLKPOL(setup); |
938 | switch (S626_GET_STD_ENCMODE(setup)) { | |
622ec01a IA |
939 | case S626_ENCMODE_TIMER: /* Timer Mode: */ |
940 | /* CntSrcB<1> selects system clock */ | |
0830ada5 | 941 | cntsrc = S626_CNTSRC_SYSCLK; |
622ec01a | 942 | /* with direction (CntSrcB<0>) obtained from ClkPol. */ |
0830ada5 | 943 | cntsrc |= clkpol; |
17afeac2 | 944 | /* ClkPolB behaves as always-on clock enable. */ |
0830ada5 | 945 | clkpol = 1; |
17afeac2 | 946 | /* ClkMultB must be 1x. */ |
7a1046e5 | 947 | clkmult = S626_CLKMULT_1X; |
17afeac2 | 948 | break; |
622ec01a IA |
949 | case S626_ENCMODE_EXTENDER: /* Extender Mode: */ |
950 | /* CntSrcB source is OverflowA (same as "timer") */ | |
0830ada5 | 951 | cntsrc = S626_CNTSRC_SYSCLK; |
17afeac2 | 952 | /* with direction obtained from ClkPol. */ |
0830ada5 | 953 | cntsrc |= clkpol; |
17afeac2 | 954 | /* ClkPolB controls IndexB -- always set to active. */ |
0830ada5 | 955 | clkpol = 1; |
17afeac2 | 956 | /* ClkMultB selects OverflowA as the clock source. */ |
7a1046e5 | 957 | clkmult = S626_CLKMULT_SPECIAL; |
17afeac2 IA |
958 | break; |
959 | default: /* Counter Mode: */ | |
960 | /* Select ENC_C and ENC_D as clock/direction inputs. */ | |
0830ada5 | 961 | cntsrc = S626_CNTSRC_ENCODER; |
17afeac2 | 962 | /* ClkPol is passed through. */ |
17afeac2 | 963 | /* Force ClkMult to x1 if not legal, otherwise pass through. */ |
0830ada5 | 964 | clkmult = S626_GET_STD_CLKMULT(setup); |
7a1046e5 IA |
965 | if (clkmult == S626_CLKMULT_SPECIAL) |
966 | clkmult = S626_CLKMULT_1X; | |
17afeac2 IA |
967 | break; |
968 | } | |
0830ada5 IA |
969 | cra |= S626_SET_CRA_CNTSRC_B(cntsrc); |
970 | crb |= S626_SET_CRB_CLKPOL_B(clkpol) | S626_SET_CRB_CLKMULT_B(clkmult); | |
17afeac2 IA |
971 | |
972 | /* | |
973 | * Force positive index polarity if IndxSrc is software-driven only, | |
974 | * otherwise pass it through. | |
975 | */ | |
2cea19fa | 976 | if (S626_GET_STD_INDXSRC(setup) != S626_INDXSRC_SOFT) |
0830ada5 | 977 | crb |= S626_SET_CRB_INDXPOL_B(S626_GET_STD_INDXPOL(setup)); |
17afeac2 IA |
978 | |
979 | /* | |
980 | * If IntSrc has been forced to Disabled, update the MISC2 interrupt | |
981 | * enable mask to indicate the counter interrupt is disabled. | |
982 | */ | |
983 | if (disable_int_src) | |
0c9a057c HS |
984 | devpriv->counter_int_enabs &= ~(S626_OVERMASK(chan) | |
985 | S626_INDXMASK(chan)); | |
17afeac2 IA |
986 | |
987 | /* | |
988 | * While retaining CounterA and LatchSrc configurations, program the | |
989 | * new counter operating mode. | |
990 | */ | |
0c9a057c | 991 | s626_debi_replace(dev, S626_LP_CRA(chan), |
622ec01a | 992 | ~(S626_CRAMSK_INDXSRC_B | S626_CRAMSK_CNTSRC_B), cra); |
0c9a057c | 993 | s626_debi_replace(dev, S626_LP_CRB(chan), |
d8515652 | 994 | S626_CRBMSK_CLKENAB_A | S626_CRBMSK_LATCHSRC, crb); |
17afeac2 IA |
995 | } |
996 | ||
b35d6a38 | 997 | static void s626_set_mode(struct comedi_device *dev, |
0c9a057c | 998 | unsigned int chan, |
b35d6a38 HS |
999 | uint16_t setup, uint16_t disable_int_src) |
1000 | { | |
0c9a057c HS |
1001 | if (chan < 3) |
1002 | s626_set_mode_a(dev, chan, setup, disable_int_src); | |
b35d6a38 | 1003 | else |
0c9a057c | 1004 | s626_set_mode_b(dev, chan, setup, disable_int_src); |
b35d6a38 HS |
1005 | } |
1006 | ||
17afeac2 IA |
1007 | /* |
1008 | * Return/set a counter's enable. enab: 0=always enabled, 1=enabled by index. | |
1009 | */ | |
c718f4a1 | 1010 | static void s626_set_enable(struct comedi_device *dev, |
0c9a057c | 1011 | unsigned int chan, uint16_t enab) |
17afeac2 | 1012 | { |
c718f4a1 HS |
1013 | unsigned int mask = S626_CRBMSK_INTCTRL; |
1014 | unsigned int set; | |
17afeac2 | 1015 | |
0c9a057c | 1016 | if (chan < 3) { |
c718f4a1 HS |
1017 | mask |= S626_CRBMSK_CLKENAB_A; |
1018 | set = S626_SET_CRB_CLKENAB_A(enab); | |
1019 | } else { | |
1020 | mask |= S626_CRBMSK_CLKENAB_B; | |
1021 | set = S626_SET_CRB_CLKENAB_B(enab); | |
1022 | } | |
0c9a057c | 1023 | s626_debi_replace(dev, S626_LP_CRB(chan), ~mask, set); |
17afeac2 IA |
1024 | } |
1025 | ||
4487502e HS |
1026 | #ifdef unused |
1027 | static uint16_t s626_get_enable(struct comedi_device *dev, | |
0c9a057c | 1028 | unsigned int chan) |
17afeac2 | 1029 | { |
0c9a057c | 1030 | uint16_t crb = s626_debi_read(dev, S626_LP_CRB(chan)); |
17afeac2 | 1031 | |
193725ba HS |
1032 | return (chan < 3) ? S626_GET_CRB_CLKENAB_A(crb) |
1033 | : S626_GET_CRB_CLKENAB_B(crb); | |
17afeac2 | 1034 | } |
4487502e | 1035 | #endif |
17afeac2 IA |
1036 | |
1037 | #ifdef unused | |
31de1948 | 1038 | static uint16_t s626_get_latch_source(struct comedi_device *dev, |
0c9a057c | 1039 | unsigned int chan) |
17afeac2 | 1040 | { |
0c9a057c | 1041 | return S626_GET_CRB_LATCHSRC(s626_debi_read(dev, S626_LP_CRB(chan))); |
17afeac2 IA |
1042 | } |
1043 | #endif | |
1044 | ||
1045 | /* | |
1046 | * Return/set the event that will trigger transfer of the preload | |
1047 | * register into the counter. 0=ThisCntr_Index, 1=ThisCntr_Overflow, | |
1048 | * 2=OverflowA (B counters only), 3=disabled. | |
1049 | */ | |
7f03b749 | 1050 | static void s626_set_load_trig(struct comedi_device *dev, |
0c9a057c | 1051 | unsigned int chan, uint16_t trig) |
17afeac2 | 1052 | { |
7f03b749 HS |
1053 | uint16_t reg; |
1054 | uint16_t mask; | |
1055 | uint16_t set; | |
17afeac2 | 1056 | |
0c9a057c HS |
1057 | if (chan < 3) { |
1058 | reg = S626_LP_CRA(chan); | |
7f03b749 HS |
1059 | mask = S626_CRAMSK_LOADSRC_A; |
1060 | set = S626_SET_CRA_LOADSRC_A(trig); | |
1061 | } else { | |
0c9a057c | 1062 | reg = S626_LP_CRB(chan); |
7f03b749 HS |
1063 | mask = S626_CRBMSK_LOADSRC_B | S626_CRBMSK_INTCTRL; |
1064 | set = S626_SET_CRB_LOADSRC_B(trig); | |
1065 | } | |
1066 | s626_debi_replace(dev, reg, ~mask, set); | |
17afeac2 IA |
1067 | } |
1068 | ||
c35b86a7 HS |
1069 | #ifdef unused |
1070 | static uint16_t s626_get_load_trig(struct comedi_device *dev, | |
0c9a057c | 1071 | unsigned int chan) |
17afeac2 | 1072 | { |
0c9a057c | 1073 | if (chan < 3) |
c35b86a7 | 1074 | return S626_GET_CRA_LOADSRC_A(s626_debi_read(dev, |
0c9a057c | 1075 | S626_LP_CRA(chan))); |
c35b86a7 HS |
1076 | else |
1077 | return S626_GET_CRB_LOADSRC_B(s626_debi_read(dev, | |
0c9a057c | 1078 | S626_LP_CRB(chan))); |
17afeac2 | 1079 | } |
c35b86a7 | 1080 | #endif |
17afeac2 | 1081 | |
bc284a2a IA |
1082 | /* |
1083 | * Return/set counter interrupt source and clear any captured | |
1084 | * index/overflow events. int_source: 0=Disabled, 1=OverflowOnly, | |
1085 | * 2=IndexOnly, 3=IndexAndOverflow. | |
1086 | */ | |
253e2ee4 | 1087 | static void s626_set_int_src(struct comedi_device *dev, |
0c9a057c | 1088 | unsigned int chan, uint16_t int_source) |
bc284a2a IA |
1089 | { |
1090 | struct s626_private *devpriv = dev->private; | |
0c9a057c HS |
1091 | uint16_t cra_reg = S626_LP_CRA(chan); |
1092 | uint16_t crb_reg = S626_LP_CRB(chan); | |
bc284a2a | 1093 | |
0c9a057c | 1094 | if (chan < 3) { |
253e2ee4 HS |
1095 | /* Reset any pending counter overflow or index captures */ |
1096 | s626_debi_replace(dev, crb_reg, ~S626_CRBMSK_INTCTRL, | |
1097 | S626_SET_CRB_INTRESETCMD(1) | | |
1098 | S626_SET_CRB_INTRESET_A(1)); | |
1099 | ||
1100 | /* Program counter interrupt source */ | |
1101 | s626_debi_replace(dev, cra_reg, ~S626_CRAMSK_INTSRC_A, | |
1102 | S626_SET_CRA_INTSRC_A(int_source)); | |
1103 | } else { | |
1104 | uint16_t crb; | |
bc284a2a | 1105 | |
253e2ee4 HS |
1106 | /* Cache writeable CRB register image */ |
1107 | crb = s626_debi_read(dev, crb_reg); | |
1108 | crb &= ~S626_CRBMSK_INTCTRL; | |
bc284a2a | 1109 | |
253e2ee4 HS |
1110 | /* Reset any pending counter overflow or index captures */ |
1111 | s626_debi_write(dev, crb_reg, | |
1112 | crb | S626_SET_CRB_INTRESETCMD(1) | | |
1113 | S626_SET_CRB_INTRESET_B(1)); | |
bc284a2a | 1114 | |
253e2ee4 HS |
1115 | /* Program counter interrupt source */ |
1116 | s626_debi_write(dev, crb_reg, | |
1117 | (crb & ~S626_CRBMSK_INTSRC_B) | | |
1118 | S626_SET_CRB_INTSRC_B(int_source)); | |
1119 | } | |
bc284a2a IA |
1120 | |
1121 | /* Update MISC2 interrupt enable mask. */ | |
0c9a057c HS |
1122 | devpriv->counter_int_enabs &= ~(S626_OVERMASK(chan) | |
1123 | S626_INDXMASK(chan)); | |
f76d02f8 HS |
1124 | switch (int_source) { |
1125 | case 0: | |
1126 | default: | |
1127 | break; | |
1128 | case 1: | |
0c9a057c | 1129 | devpriv->counter_int_enabs |= S626_OVERMASK(chan); |
f76d02f8 HS |
1130 | break; |
1131 | case 2: | |
0c9a057c | 1132 | devpriv->counter_int_enabs |= S626_INDXMASK(chan); |
f76d02f8 HS |
1133 | break; |
1134 | case 3: | |
0c9a057c HS |
1135 | devpriv->counter_int_enabs |= (S626_OVERMASK(chan) | |
1136 | S626_INDXMASK(chan)); | |
f76d02f8 HS |
1137 | break; |
1138 | } | |
bc284a2a IA |
1139 | } |
1140 | ||
13f2609d HS |
1141 | #ifdef unused |
1142 | static uint16_t s626_get_int_src(struct comedi_device *dev, | |
0c9a057c | 1143 | unsigned int chan) |
bc284a2a | 1144 | { |
13f2609d HS |
1145 | if (chan < 3) |
1146 | return S626_GET_CRA_INTSRC_A(s626_debi_read(dev, | |
0c9a057c | 1147 | S626_LP_CRA(chan))); |
13f2609d HS |
1148 | else |
1149 | return S626_GET_CRB_INTSRC_B(s626_debi_read(dev, | |
0c9a057c | 1150 | S626_LP_CRB(chan))); |
bc284a2a | 1151 | } |
13f2609d | 1152 | #endif |
bc284a2a IA |
1153 | |
1154 | #ifdef unused | |
1155 | /* | |
1156 | * Return/set the clock multiplier. | |
1157 | */ | |
31de1948 | 1158 | static void s626_set_clk_mult(struct comedi_device *dev, |
0c9a057c | 1159 | unsigned int chan, uint16_t value) |
bc284a2a | 1160 | { |
0c9a057c HS |
1161 | uint16_t mode; |
1162 | ||
1163 | mode = s626_get_mode(dev, chan); | |
1164 | mode &= ~S626_STDMSK_CLKMULT; | |
1165 | mode |= S626_SET_STD_CLKMULT(value); | |
1166 | ||
1167 | s626_set_mode(dev, chan, mode, false); | |
bc284a2a IA |
1168 | } |
1169 | ||
bc284a2a IA |
1170 | /* |
1171 | * Return/set the clock polarity. | |
1172 | */ | |
31de1948 | 1173 | static void s626_set_clk_pol(struct comedi_device *dev, |
0c9a057c | 1174 | unsigned int chan, uint16_t value) |
bc284a2a | 1175 | { |
0c9a057c HS |
1176 | uint16_t mode; |
1177 | ||
1178 | mode = s626_get_mode(dev, chan); | |
1179 | mode &= ~S626_STDMSK_CLKPOL; | |
1180 | mode |= S626_SET_STD_CLKPOL(value); | |
1181 | ||
1182 | s626_set_mode(dev, chan, mode, false); | |
bc284a2a IA |
1183 | } |
1184 | ||
bc284a2a | 1185 | /* |
622ec01a | 1186 | * Return/set the encoder mode. |
bc284a2a | 1187 | */ |
622ec01a | 1188 | static void s626_set_enc_mode(struct comedi_device *dev, |
0c9a057c | 1189 | unsigned int chan, uint16_t value) |
bc284a2a | 1190 | { |
0c9a057c HS |
1191 | uint16_t mode; |
1192 | ||
1193 | mode = s626_get_mode(dev, chan); | |
1194 | mode &= ~S626_STDMSK_ENCMODE; | |
1195 | mode |= S626_SET_STD_ENCMODE(value); | |
1196 | ||
1197 | s626_set_mode(dev, chan, mode, false); | |
bc284a2a IA |
1198 | } |
1199 | ||
31de1948 | 1200 | static uint16_t s626_get_index_pol(struct comedi_device *dev, |
0c9a057c | 1201 | unsigned int chan) |
bc284a2a | 1202 | { |
0c9a057c | 1203 | return S626_GET_STD_INDXPOL(s626_get_mode(dev, chan)); |
bc284a2a IA |
1204 | } |
1205 | ||
1206 | /* | |
1207 | * Return/set the index source. | |
1208 | */ | |
31de1948 | 1209 | static void s626_set_index_src(struct comedi_device *dev, |
0c9a057c | 1210 | unsigned int chan, uint16_t value) |
bc284a2a | 1211 | { |
0c9a057c HS |
1212 | uint16_t mode; |
1213 | ||
1214 | mode = s626_get_mode(dev, chan); | |
1215 | mode &= ~S626_STDMSK_INDXSRC; | |
1216 | mode |= S626_SET_STD_INDXSRC(value != 0); | |
1217 | ||
1218 | s626_set_mode(dev, chan, mode, false); | |
bc284a2a IA |
1219 | } |
1220 | ||
31de1948 | 1221 | static uint16_t s626_get_index_src(struct comedi_device *dev, |
0c9a057c | 1222 | unsigned int chan) |
bc284a2a | 1223 | { |
0c9a057c | 1224 | return S626_GET_STD_INDXSRC(s626_get_mode(dev, chan)); |
bc284a2a IA |
1225 | } |
1226 | #endif | |
1227 | ||
1228 | /* | |
1229 | * Generate an index pulse. | |
1230 | */ | |
92249e1f | 1231 | static void s626_pulse_index(struct comedi_device *dev, |
0c9a057c | 1232 | unsigned int chan) |
bc284a2a | 1233 | { |
0c9a057c | 1234 | if (chan < 3) { |
92249e1f | 1235 | uint16_t cra; |
bc284a2a | 1236 | |
0c9a057c | 1237 | cra = s626_debi_read(dev, S626_LP_CRA(chan)); |
bc284a2a | 1238 | |
92249e1f | 1239 | /* Pulse index */ |
0c9a057c | 1240 | s626_debi_write(dev, S626_LP_CRA(chan), |
92249e1f | 1241 | (cra ^ S626_CRAMSK_INDXPOL_A)); |
0c9a057c | 1242 | s626_debi_write(dev, S626_LP_CRA(chan), cra); |
92249e1f HS |
1243 | } else { |
1244 | uint16_t crb; | |
bc284a2a | 1245 | |
0c9a057c | 1246 | crb = s626_debi_read(dev, S626_LP_CRB(chan)); |
92249e1f HS |
1247 | crb &= ~S626_CRBMSK_INTCTRL; |
1248 | ||
1249 | /* Pulse index */ | |
0c9a057c | 1250 | s626_debi_write(dev, S626_LP_CRB(chan), |
92249e1f | 1251 | (crb ^ S626_CRBMSK_INDXPOL_B)); |
0c9a057c | 1252 | s626_debi_write(dev, S626_LP_CRB(chan), crb); |
92249e1f | 1253 | } |
bc284a2a IA |
1254 | } |
1255 | ||
5fd4b711 | 1256 | static unsigned int s626_ai_reg_to_uint(unsigned int data) |
11e865c1 | 1257 | { |
5fd4b711 | 1258 | return ((data >> 18) & 0x3fff) ^ 0x2000; |
020c44f3 | 1259 | } |
8231eb56 | 1260 | |
6baffbc2 HS |
1261 | static int s626_dio_set_irq(struct comedi_device *dev, unsigned int chan) |
1262 | { | |
100b4edc HS |
1263 | unsigned int group = chan / 16; |
1264 | unsigned int mask = 1 << (chan - (16 * group)); | |
6baffbc2 HS |
1265 | unsigned int status; |
1266 | ||
6baffbc2 | 1267 | /* set channel to capture positive edge */ |
d8515652 IA |
1268 | status = s626_debi_read(dev, S626_LP_RDEDGSEL(group)); |
1269 | s626_debi_write(dev, S626_LP_WREDGSEL(group), mask | status); | |
6baffbc2 HS |
1270 | |
1271 | /* enable interrupt on selected channel */ | |
d8515652 IA |
1272 | status = s626_debi_read(dev, S626_LP_RDINTSEL(group)); |
1273 | s626_debi_write(dev, S626_LP_WRINTSEL(group), mask | status); | |
6baffbc2 HS |
1274 | |
1275 | /* enable edge capture write command */ | |
d8515652 | 1276 | s626_debi_write(dev, S626_LP_MISC1, S626_MISC1_EDCAP); |
6baffbc2 HS |
1277 | |
1278 | /* enable edge capture on selected channel */ | |
d8515652 IA |
1279 | status = s626_debi_read(dev, S626_LP_RDCAPSEL(group)); |
1280 | s626_debi_write(dev, S626_LP_WRCAPSEL(group), mask | status); | |
6baffbc2 HS |
1281 | |
1282 | return 0; | |
1283 | } | |
1284 | ||
1285 | static int s626_dio_reset_irq(struct comedi_device *dev, unsigned int group, | |
1286 | unsigned int mask) | |
1287 | { | |
6baffbc2 | 1288 | /* disable edge capture write command */ |
d8515652 | 1289 | s626_debi_write(dev, S626_LP_MISC1, S626_MISC1_NOEDCAP); |
6baffbc2 HS |
1290 | |
1291 | /* enable edge capture on selected channel */ | |
d8515652 | 1292 | s626_debi_write(dev, S626_LP_WRCAPSEL(group), mask); |
6baffbc2 HS |
1293 | |
1294 | return 0; | |
1295 | } | |
1296 | ||
1297 | static int s626_dio_clear_irq(struct comedi_device *dev) | |
1298 | { | |
1299 | unsigned int group; | |
1300 | ||
1301 | /* disable edge capture write command */ | |
d8515652 | 1302 | s626_debi_write(dev, S626_LP_MISC1, S626_MISC1_NOEDCAP); |
6baffbc2 | 1303 | |
100b4edc HS |
1304 | /* clear all dio pending events and interrupt */ |
1305 | for (group = 0; group < S626_DIO_BANKS; group++) | |
d8515652 | 1306 | s626_debi_write(dev, S626_LP_WRCAPSEL(group), 0xffff); |
6baffbc2 HS |
1307 | |
1308 | return 0; | |
1309 | } | |
1310 | ||
31de1948 IA |
1311 | static void s626_handle_dio_interrupt(struct comedi_device *dev, |
1312 | uint16_t irqbit, uint8_t group) | |
65a17c29 HS |
1313 | { |
1314 | struct s626_private *devpriv = dev->private; | |
1315 | struct comedi_subdevice *s = dev->read_subdev; | |
1316 | struct comedi_cmd *cmd = &s->async->cmd; | |
1317 | ||
1318 | s626_dio_reset_irq(dev, group, irqbit); | |
1319 | ||
1320 | if (devpriv->ai_cmd_running) { | |
1321 | /* check if interrupt is an ai acquisition start trigger */ | |
1322 | if ((irqbit >> (cmd->start_arg - (16 * group))) == 1 && | |
1323 | cmd->start_src == TRIG_EXT) { | |
1324 | /* Start executing the RPS program */ | |
d8515652 | 1325 | s626_mc_enable(dev, S626_MC1_ERPS1, S626_P_MC1); |
65a17c29 HS |
1326 | |
1327 | if (cmd->scan_begin_src == TRIG_EXT) | |
1328 | s626_dio_set_irq(dev, cmd->scan_begin_arg); | |
1329 | } | |
1330 | if ((irqbit >> (cmd->scan_begin_arg - (16 * group))) == 1 && | |
1331 | cmd->scan_begin_src == TRIG_EXT) { | |
ddd9813e | 1332 | /* Trigger ADC scan loop start */ |
d8515652 | 1333 | s626_mc_enable(dev, S626_MC2_ADC_RPS, S626_P_MC2); |
65a17c29 HS |
1334 | |
1335 | if (cmd->convert_src == TRIG_EXT) { | |
1336 | devpriv->ai_convert_count = cmd->chanlist_len; | |
1337 | ||
1338 | s626_dio_set_irq(dev, cmd->convert_arg); | |
1339 | } | |
1340 | ||
1341 | if (cmd->convert_src == TRIG_TIMER) { | |
65a17c29 | 1342 | devpriv->ai_convert_count = cmd->chanlist_len; |
0c9a057c | 1343 | s626_set_enable(dev, 5, S626_CLKENAB_ALWAYS); |
65a17c29 HS |
1344 | } |
1345 | } | |
1346 | if ((irqbit >> (cmd->convert_arg - (16 * group))) == 1 && | |
1347 | cmd->convert_src == TRIG_EXT) { | |
ddd9813e | 1348 | /* Trigger ADC scan loop start */ |
d8515652 | 1349 | s626_mc_enable(dev, S626_MC2_ADC_RPS, S626_P_MC2); |
65a17c29 HS |
1350 | |
1351 | devpriv->ai_convert_count--; | |
1352 | if (devpriv->ai_convert_count > 0) | |
1353 | s626_dio_set_irq(dev, cmd->convert_arg); | |
1354 | } | |
1355 | } | |
1356 | } | |
1357 | ||
31de1948 | 1358 | static void s626_check_dio_interrupts(struct comedi_device *dev) |
65a17c29 HS |
1359 | { |
1360 | uint16_t irqbit; | |
1361 | uint8_t group; | |
1362 | ||
1363 | for (group = 0; group < S626_DIO_BANKS; group++) { | |
65a17c29 | 1364 | /* read interrupt type */ |
d8515652 | 1365 | irqbit = s626_debi_read(dev, S626_LP_RDCAPFLG(group)); |
65a17c29 HS |
1366 | |
1367 | /* check if interrupt is generated from dio channels */ | |
1368 | if (irqbit) { | |
31de1948 | 1369 | s626_handle_dio_interrupt(dev, irqbit, group); |
65a17c29 HS |
1370 | return; |
1371 | } | |
1372 | } | |
1373 | } | |
1374 | ||
31de1948 | 1375 | static void s626_check_counter_interrupts(struct comedi_device *dev) |
0b9675d5 HS |
1376 | { |
1377 | struct s626_private *devpriv = dev->private; | |
1378 | struct comedi_subdevice *s = dev->read_subdev; | |
1379 | struct comedi_async *async = s->async; | |
1380 | struct comedi_cmd *cmd = &async->cmd; | |
0b9675d5 HS |
1381 | uint16_t irqbit; |
1382 | ||
1383 | /* read interrupt type */ | |
d8515652 | 1384 | irqbit = s626_debi_read(dev, S626_LP_RDMISC2); |
0b9675d5 HS |
1385 | |
1386 | /* check interrupt on counters */ | |
d8515652 | 1387 | if (irqbit & S626_IRQ_COINT1A) { |
0b9675d5 | 1388 | /* clear interrupt capture flag */ |
0c9a057c | 1389 | s626_reset_cap_flags(dev, 0); |
0b9675d5 | 1390 | } |
d8515652 | 1391 | if (irqbit & S626_IRQ_COINT2A) { |
0b9675d5 | 1392 | /* clear interrupt capture flag */ |
0c9a057c | 1393 | s626_reset_cap_flags(dev, 1); |
0b9675d5 | 1394 | } |
d8515652 | 1395 | if (irqbit & S626_IRQ_COINT3A) { |
0b9675d5 | 1396 | /* clear interrupt capture flag */ |
0c9a057c | 1397 | s626_reset_cap_flags(dev, 2); |
0b9675d5 | 1398 | } |
d8515652 | 1399 | if (irqbit & S626_IRQ_COINT1B) { |
0b9675d5 | 1400 | /* clear interrupt capture flag */ |
0c9a057c | 1401 | s626_reset_cap_flags(dev, 3); |
0b9675d5 | 1402 | } |
d8515652 | 1403 | if (irqbit & S626_IRQ_COINT2B) { |
0b9675d5 | 1404 | /* clear interrupt capture flag */ |
0c9a057c | 1405 | s626_reset_cap_flags(dev, 4); |
0b9675d5 HS |
1406 | |
1407 | if (devpriv->ai_convert_count > 0) { | |
1408 | devpriv->ai_convert_count--; | |
1409 | if (devpriv->ai_convert_count == 0) | |
0c9a057c | 1410 | s626_set_enable(dev, 4, S626_CLKENAB_INDEX); |
0b9675d5 HS |
1411 | |
1412 | if (cmd->convert_src == TRIG_TIMER) { | |
ddd9813e | 1413 | /* Trigger ADC scan loop start */ |
d8515652 IA |
1414 | s626_mc_enable(dev, S626_MC2_ADC_RPS, |
1415 | S626_P_MC2); | |
0b9675d5 HS |
1416 | } |
1417 | } | |
1418 | } | |
d8515652 | 1419 | if (irqbit & S626_IRQ_COINT3B) { |
0b9675d5 | 1420 | /* clear interrupt capture flag */ |
0c9a057c | 1421 | s626_reset_cap_flags(dev, 5); |
0b9675d5 HS |
1422 | |
1423 | if (cmd->scan_begin_src == TRIG_TIMER) { | |
ddd9813e | 1424 | /* Trigger ADC scan loop start */ |
d8515652 | 1425 | s626_mc_enable(dev, S626_MC2_ADC_RPS, S626_P_MC2); |
0b9675d5 HS |
1426 | } |
1427 | ||
1428 | if (cmd->convert_src == TRIG_TIMER) { | |
0b9675d5 | 1429 | devpriv->ai_convert_count = cmd->chanlist_len; |
0c9a057c | 1430 | s626_set_enable(dev, 4, S626_CLKENAB_ALWAYS); |
0b9675d5 HS |
1431 | } |
1432 | } | |
1433 | } | |
1434 | ||
31de1948 | 1435 | static bool s626_handle_eos_interrupt(struct comedi_device *dev) |
4c2d13e0 HS |
1436 | { |
1437 | struct s626_private *devpriv = dev->private; | |
1438 | struct comedi_subdevice *s = dev->read_subdev; | |
1439 | struct comedi_async *async = s->async; | |
1440 | struct comedi_cmd *cmd = &async->cmd; | |
1441 | /* | |
1442 | * Init ptr to DMA buffer that holds new ADC data. We skip the | |
1443 | * first uint16_t in the buffer because it contains junk data | |
1444 | * from the final ADC of the previous poll list scan. | |
1445 | */ | |
5fd4b711 | 1446 | uint32_t *readaddr = (uint32_t *)devpriv->ana_buf.logical_base + 1; |
4c2d13e0 HS |
1447 | int i; |
1448 | ||
1449 | /* get the data and hand it over to comedi */ | |
1450 | for (i = 0; i < cmd->chanlist_len; i++) { | |
5fd4b711 | 1451 | unsigned short tempdata; |
4c2d13e0 HS |
1452 | |
1453 | /* | |
1454 | * Convert ADC data to 16-bit integer values and copy | |
1455 | * to application buffer. | |
1456 | */ | |
5fd4b711 | 1457 | tempdata = s626_ai_reg_to_uint(*readaddr); |
4c2d13e0 HS |
1458 | readaddr++; |
1459 | ||
0e017a4b | 1460 | comedi_buf_write_samples(s, &tempdata, 1); |
4c2d13e0 HS |
1461 | } |
1462 | ||
aee15aea HS |
1463 | if (cmd->stop_src == TRIG_COUNT && async->scans_done >= cmd->stop_arg) |
1464 | async->events |= COMEDI_CB_EOA; | |
4c2d13e0 | 1465 | |
aee15aea HS |
1466 | if (async->events & COMEDI_CB_CANCEL_MASK) |
1467 | devpriv->ai_cmd_running = 0; | |
4c2d13e0 HS |
1468 | |
1469 | if (devpriv->ai_cmd_running && cmd->scan_begin_src == TRIG_EXT) | |
1470 | s626_dio_set_irq(dev, cmd->scan_begin_arg); | |
1471 | ||
365dae93 | 1472 | comedi_handle_events(dev, s); |
4c2d13e0 | 1473 | |
365dae93 | 1474 | return !devpriv->ai_cmd_running; |
4c2d13e0 HS |
1475 | } |
1476 | ||
020c44f3 HS |
1477 | static irqreturn_t s626_irq_handler(int irq, void *d) |
1478 | { | |
1479 | struct comedi_device *dev = d; | |
020c44f3 | 1480 | unsigned long flags; |
020c44f3 | 1481 | uint32_t irqtype, irqstatus; |
11e865c1 | 1482 | |
a7401cdd | 1483 | if (!dev->attached) |
020c44f3 | 1484 | return IRQ_NONE; |
8ee52611 | 1485 | /* lock to avoid race with comedi_poll */ |
020c44f3 | 1486 | spin_lock_irqsave(&dev->spinlock, flags); |
11e865c1 | 1487 | |
020c44f3 | 1488 | /* save interrupt enable register state */ |
de9cd5ca | 1489 | irqstatus = readl(dev->mmio + S626_P_IER); |
11e865c1 | 1490 | |
020c44f3 | 1491 | /* read interrupt type */ |
de9cd5ca | 1492 | irqtype = readl(dev->mmio + S626_P_ISR); |
11e865c1 | 1493 | |
020c44f3 | 1494 | /* disable master interrupt */ |
de9cd5ca | 1495 | writel(0, dev->mmio + S626_P_IER); |
11e865c1 | 1496 | |
020c44f3 | 1497 | /* clear interrupt */ |
de9cd5ca | 1498 | writel(irqtype, dev->mmio + S626_P_ISR); |
11e865c1 | 1499 | |
020c44f3 | 1500 | switch (irqtype) { |
d8515652 | 1501 | case S626_IRQ_RPS1: /* end_of_scan occurs */ |
31de1948 | 1502 | if (s626_handle_eos_interrupt(dev)) |
020c44f3 | 1503 | irqstatus = 0; |
020c44f3 | 1504 | break; |
d8515652 | 1505 | case S626_IRQ_GPIO3: /* check dio and counter interrupt */ |
020c44f3 | 1506 | /* s626_dio_clear_irq(dev); */ |
31de1948 IA |
1507 | s626_check_dio_interrupts(dev); |
1508 | s626_check_counter_interrupts(dev); | |
0b9675d5 | 1509 | break; |
020c44f3 | 1510 | } |
11e865c1 | 1511 | |
020c44f3 | 1512 | /* enable interrupt */ |
de9cd5ca | 1513 | writel(irqstatus, dev->mmio + S626_P_IER); |
b6c77757 | 1514 | |
020c44f3 HS |
1515 | spin_unlock_irqrestore(&dev->spinlock, flags); |
1516 | return IRQ_HANDLED; | |
1517 | } | |
b6c77757 | 1518 | |
020c44f3 | 1519 | /* |
8ee52611 | 1520 | * This function builds the RPS program for hardware driven acquisition. |
020c44f3 | 1521 | */ |
31de1948 | 1522 | static void s626_reset_adc(struct comedi_device *dev, uint8_t *ppl) |
020c44f3 | 1523 | { |
7f2f7e05 | 1524 | struct s626_private *devpriv = dev->private; |
9c9ab3c1 HS |
1525 | struct comedi_subdevice *s = dev->read_subdev; |
1526 | struct comedi_cmd *cmd = &s->async->cmd; | |
f1f7efce IA |
1527 | uint32_t *rps; |
1528 | uint32_t jmp_adrs; | |
020c44f3 HS |
1529 | uint16_t i; |
1530 | uint16_t n; | |
f1f7efce | 1531 | uint32_t local_ppl; |
11e865c1 | 1532 | |
c5cf4606 | 1533 | /* Stop RPS program in case it is currently running */ |
d8515652 | 1534 | s626_mc_disable(dev, S626_MC1_ERPS1, S626_P_MC1); |
11e865c1 | 1535 | |
8ee52611 | 1536 | /* Set starting logical address to write RPS commands. */ |
f1f7efce | 1537 | rps = (uint32_t *)devpriv->rps_buf.logical_base; |
11e865c1 | 1538 | |
25f8fd5e | 1539 | /* Initialize RPS instruction pointer */ |
07a36d66 | 1540 | writel((uint32_t)devpriv->rps_buf.physical_base, |
de9cd5ca | 1541 | dev->mmio + S626_P_RPSADDR1); |
11e865c1 | 1542 | |
07a36d66 | 1543 | /* Construct RPS program in rps_buf DMA buffer */ |
857ced45 | 1544 | if (cmd->scan_begin_src != TRIG_FOLLOW) { |
8ee52611 | 1545 | /* Wait for Start trigger. */ |
d8515652 IA |
1546 | *rps++ = S626_RPS_PAUSE | S626_RPS_SIGADC; |
1547 | *rps++ = S626_RPS_CLRSIGNAL | S626_RPS_SIGADC; | |
020c44f3 | 1548 | } |
11e865c1 | 1549 | |
8ee52611 IA |
1550 | /* |
1551 | * SAA7146 BUG WORKAROUND Do a dummy DEBI Write. This is necessary | |
020c44f3 HS |
1552 | * because the first RPS DEBI Write following a non-RPS DEBI write |
1553 | * seems to always fail. If we don't do this dummy write, the ADC | |
1554 | * gain might not be set to the value required for the first slot in | |
1555 | * the poll list; the ADC gain would instead remain unchanged from | |
1556 | * the previously programmed value. | |
1557 | */ | |
020c44f3 | 1558 | /* Write DEBI Write command and address to shadow RAM. */ |
d8515652 IA |
1559 | *rps++ = S626_RPS_LDREG | (S626_P_DEBICMD >> 2); |
1560 | *rps++ = S626_DEBI_CMD_WRWORD | S626_LP_GSEL; | |
1561 | *rps++ = S626_RPS_LDREG | (S626_P_DEBIAD >> 2); | |
8ee52611 | 1562 | /* Write DEBI immediate data to shadow RAM: */ |
d8515652 IA |
1563 | *rps++ = S626_GSEL_BIPOLAR5V; /* arbitrary immediate data value. */ |
1564 | *rps++ = S626_RPS_CLRSIGNAL | S626_RPS_DEBI; | |
8ee52611 | 1565 | /* Reset "shadow RAM uploaded" flag. */ |
d8515652 IA |
1566 | /* Invoke shadow RAM upload. */ |
1567 | *rps++ = S626_RPS_UPLOAD | S626_RPS_DEBI; | |
1568 | /* Wait for shadow upload to finish. */ | |
1569 | *rps++ = S626_RPS_PAUSE | S626_RPS_DEBI; | |
11e865c1 | 1570 | |
8ee52611 IA |
1571 | /* |
1572 | * Digitize all slots in the poll list. This is implemented as a | |
020c44f3 | 1573 | * for loop to limit the slot count to 16 in case the application |
d8515652 | 1574 | * forgot to set the S626_EOPL flag in the final slot. |
020c44f3 | 1575 | */ |
07a36d66 IA |
1576 | for (devpriv->adc_items = 0; devpriv->adc_items < 16; |
1577 | devpriv->adc_items++) { | |
8ee52611 IA |
1578 | /* |
1579 | * Convert application's poll list item to private board class | |
020c44f3 HS |
1580 | * format. Each app poll list item is an uint8_t with form |
1581 | * (EOPL,x,x,RANGE,CHAN<3:0>), where RANGE code indicates 0 = | |
1582 | * +-10V, 1 = +-5V, and EOPL = End of Poll List marker. | |
b6c77757 | 1583 | */ |
d8515652 IA |
1584 | local_ppl = (*ppl << 8) | (*ppl & 0x10 ? S626_GSEL_BIPOLAR5V : |
1585 | S626_GSEL_BIPOLAR10V); | |
8ee52611 IA |
1586 | |
1587 | /* Switch ADC analog gain. */ | |
1588 | /* Write DEBI command and address to shadow RAM. */ | |
d8515652 IA |
1589 | *rps++ = S626_RPS_LDREG | (S626_P_DEBICMD >> 2); |
1590 | *rps++ = S626_DEBI_CMD_WRWORD | S626_LP_GSEL; | |
8ee52611 | 1591 | /* Write DEBI immediate data to shadow RAM. */ |
d8515652 | 1592 | *rps++ = S626_RPS_LDREG | (S626_P_DEBIAD >> 2); |
f1f7efce | 1593 | *rps++ = local_ppl; |
8ee52611 | 1594 | /* Reset "shadow RAM uploaded" flag. */ |
d8515652 | 1595 | *rps++ = S626_RPS_CLRSIGNAL | S626_RPS_DEBI; |
8ee52611 | 1596 | /* Invoke shadow RAM upload. */ |
d8515652 | 1597 | *rps++ = S626_RPS_UPLOAD | S626_RPS_DEBI; |
8ee52611 | 1598 | /* Wait for shadow upload to finish. */ |
d8515652 | 1599 | *rps++ = S626_RPS_PAUSE | S626_RPS_DEBI; |
8ee52611 | 1600 | /* Select ADC analog input channel. */ |
d8515652 | 1601 | *rps++ = S626_RPS_LDREG | (S626_P_DEBICMD >> 2); |
8ee52611 | 1602 | /* Write DEBI command and address to shadow RAM. */ |
d8515652 IA |
1603 | *rps++ = S626_DEBI_CMD_WRWORD | S626_LP_ISEL; |
1604 | *rps++ = S626_RPS_LDREG | (S626_P_DEBIAD >> 2); | |
8ee52611 | 1605 | /* Write DEBI immediate data to shadow RAM. */ |
f1f7efce | 1606 | *rps++ = local_ppl; |
8ee52611 | 1607 | /* Reset "shadow RAM uploaded" flag. */ |
d8515652 | 1608 | *rps++ = S626_RPS_CLRSIGNAL | S626_RPS_DEBI; |
8ee52611 | 1609 | /* Invoke shadow RAM upload. */ |
d8515652 | 1610 | *rps++ = S626_RPS_UPLOAD | S626_RPS_DEBI; |
8ee52611 | 1611 | /* Wait for shadow upload to finish. */ |
d8515652 | 1612 | *rps++ = S626_RPS_PAUSE | S626_RPS_DEBI; |
11e865c1 | 1613 | |
8ee52611 IA |
1614 | /* |
1615 | * Delay at least 10 microseconds for analog input settling. | |
d8515652 IA |
1616 | * Instead of padding with NOPs, we use S626_RPS_JUMP |
1617 | * instructions here; this allows us to produce a longer delay | |
1618 | * than is possible with NOPs because each S626_RPS_JUMP | |
1619 | * flushes the RPS' instruction prefetch pipeline. | |
020c44f3 | 1620 | */ |
f1f7efce | 1621 | jmp_adrs = |
07a36d66 | 1622 | (uint32_t)devpriv->rps_buf.physical_base + |
f1f7efce | 1623 | (uint32_t)((unsigned long)rps - |
07a36d66 IA |
1624 | (unsigned long)devpriv-> |
1625 | rps_buf.logical_base); | |
d8515652 | 1626 | for (i = 0; i < (10 * S626_RPSCLK_PER_US / 2); i++) { |
f1f7efce | 1627 | jmp_adrs += 8; /* Repeat to implement time delay: */ |
d8515652 IA |
1628 | /* Jump to next RPS instruction. */ |
1629 | *rps++ = S626_RPS_JUMP; | |
f1f7efce | 1630 | *rps++ = jmp_adrs; |
020c44f3 | 1631 | } |
11e865c1 | 1632 | |
857ced45 | 1633 | if (cmd->convert_src != TRIG_NOW) { |
8ee52611 | 1634 | /* Wait for Start trigger. */ |
d8515652 IA |
1635 | *rps++ = S626_RPS_PAUSE | S626_RPS_SIGADC; |
1636 | *rps++ = S626_RPS_CLRSIGNAL | S626_RPS_SIGADC; | |
020c44f3 | 1637 | } |
8ee52611 IA |
1638 | /* Start ADC by pulsing GPIO1. */ |
1639 | /* Begin ADC Start pulse. */ | |
d8515652 IA |
1640 | *rps++ = S626_RPS_LDREG | (S626_P_GPIO >> 2); |
1641 | *rps++ = S626_GPIO_BASE | S626_GPIO1_LO; | |
1642 | *rps++ = S626_RPS_NOP; | |
8ee52611 IA |
1643 | /* VERSION 2.03 CHANGE: STRETCH OUT ADC START PULSE. */ |
1644 | /* End ADC Start pulse. */ | |
d8515652 IA |
1645 | *rps++ = S626_RPS_LDREG | (S626_P_GPIO >> 2); |
1646 | *rps++ = S626_GPIO_BASE | S626_GPIO1_HI; | |
8ee52611 IA |
1647 | /* |
1648 | * Wait for ADC to complete (GPIO2 is asserted high when ADC not | |
020c44f3 HS |
1649 | * busy) and for data from previous conversion to shift into FB |
1650 | * BUFFER 1 register. | |
1651 | */ | |
d8515652 IA |
1652 | /* Wait for ADC done. */ |
1653 | *rps++ = S626_RPS_PAUSE | S626_RPS_GPIO2; | |
11e865c1 | 1654 | |
8ee52611 | 1655 | /* Transfer ADC data from FB BUFFER 1 register to DMA buffer. */ |
d8515652 IA |
1656 | *rps++ = S626_RPS_STREG | |
1657 | (S626_BUGFIX_STREG(S626_P_FB_BUFFER1) >> 2); | |
f1f7efce IA |
1658 | *rps++ = (uint32_t)devpriv->ana_buf.physical_base + |
1659 | (devpriv->adc_items << 2); | |
11e865c1 | 1660 | |
8ee52611 IA |
1661 | /* |
1662 | * If this slot's EndOfPollList flag is set, all channels have | |
1663 | * now been processed. | |
1664 | */ | |
d8515652 | 1665 | if (*ppl++ & S626_EOPL) { |
07a36d66 | 1666 | devpriv->adc_items++; /* Adjust poll list item count. */ |
8ee52611 | 1667 | break; /* Exit poll list processing loop. */ |
020c44f3 HS |
1668 | } |
1669 | } | |
11e865c1 | 1670 | |
8ee52611 IA |
1671 | /* |
1672 | * VERSION 2.01 CHANGE: DELAY CHANGED FROM 250NS to 2US. Allow the | |
020c44f3 HS |
1673 | * ADC to stabilize for 2 microseconds before starting the final |
1674 | * (dummy) conversion. This delay is necessary to allow sufficient | |
1675 | * time between last conversion finished and the start of the dummy | |
1676 | * conversion. Without this delay, the last conversion's data value | |
1677 | * is sometimes set to the previous conversion's data value. | |
1678 | */ | |
d8515652 IA |
1679 | for (n = 0; n < (2 * S626_RPSCLK_PER_US); n++) |
1680 | *rps++ = S626_RPS_NOP; | |
11e865c1 | 1681 | |
8ee52611 IA |
1682 | /* |
1683 | * Start a dummy conversion to cause the data from the last | |
020c44f3 HS |
1684 | * conversion of interest to be shifted in. |
1685 | */ | |
d8515652 IA |
1686 | /* Begin ADC Start pulse. */ |
1687 | *rps++ = S626_RPS_LDREG | (S626_P_GPIO >> 2); | |
1688 | *rps++ = S626_GPIO_BASE | S626_GPIO1_LO; | |
1689 | *rps++ = S626_RPS_NOP; | |
020c44f3 | 1690 | /* VERSION 2.03 CHANGE: STRETCH OUT ADC START PULSE. */ |
d8515652 IA |
1691 | *rps++ = S626_RPS_LDREG | (S626_P_GPIO >> 2); /* End ADC Start pulse. */ |
1692 | *rps++ = S626_GPIO_BASE | S626_GPIO1_HI; | |
11e865c1 | 1693 | |
8ee52611 IA |
1694 | /* |
1695 | * Wait for the data from the last conversion of interest to arrive | |
020c44f3 HS |
1696 | * in FB BUFFER 1 register. |
1697 | */ | |
d8515652 | 1698 | *rps++ = S626_RPS_PAUSE | S626_RPS_GPIO2; /* Wait for ADC done. */ |
11e865c1 | 1699 | |
8ee52611 | 1700 | /* Transfer final ADC data from FB BUFFER 1 register to DMA buffer. */ |
d8515652 | 1701 | *rps++ = S626_RPS_STREG | (S626_BUGFIX_STREG(S626_P_FB_BUFFER1) >> 2); |
f1f7efce IA |
1702 | *rps++ = (uint32_t)devpriv->ana_buf.physical_base + |
1703 | (devpriv->adc_items << 2); | |
11e865c1 | 1704 | |
8ee52611 IA |
1705 | /* Indicate ADC scan loop is finished. */ |
1706 | /* Signal ReadADC() that scan is done. */ | |
d8515652 | 1707 | /* *rps++= S626_RPS_CLRSIGNAL | S626_RPS_SIGADC; */ |
11e865c1 | 1708 | |
020c44f3 | 1709 | /* invoke interrupt */ |
8ee52611 | 1710 | if (devpriv->ai_cmd_running == 1) |
d8515652 | 1711 | *rps++ = S626_RPS_IRQ; |
11e865c1 | 1712 | |
8ee52611 | 1713 | /* Restart RPS program at its beginning. */ |
d8515652 | 1714 | *rps++ = S626_RPS_JUMP; /* Branch to start of RPS program. */ |
f1f7efce | 1715 | *rps++ = (uint32_t)devpriv->rps_buf.physical_base; |
8ee52611 IA |
1716 | |
1717 | /* End of RPS program build */ | |
020c44f3 | 1718 | } |
11e865c1 | 1719 | |
e4632a71 HS |
1720 | #ifdef unused_code |
1721 | static int s626_ai_rinsn(struct comedi_device *dev, | |
1722 | struct comedi_subdevice *s, | |
1723 | struct comedi_insn *insn, | |
1724 | unsigned int *data) | |
1725 | { | |
1726 | struct s626_private *devpriv = dev->private; | |
8ee52611 IA |
1727 | uint8_t i; |
1728 | int32_t *readaddr; | |
11e865c1 | 1729 | |
ddd9813e | 1730 | /* Trigger ADC scan loop start */ |
d8515652 | 1731 | s626_mc_enable(dev, S626_MC2_ADC_RPS, S626_P_MC2); |
11e865c1 | 1732 | |
e4632a71 | 1733 | /* Wait until ADC scan loop is finished (RPS Signal 0 reset) */ |
d8515652 | 1734 | while (s626_mc_test(dev, S626_MC2_ADC_RPS, S626_P_MC2)) |
e4632a71 | 1735 | ; |
11e865c1 | 1736 | |
e4632a71 HS |
1737 | /* |
1738 | * Init ptr to DMA buffer that holds new ADC data. We skip the | |
1739 | * first uint16_t in the buffer because it contains junk data from | |
1740 | * the final ADC of the previous poll list scan. | |
1741 | */ | |
07a36d66 | 1742 | readaddr = (uint32_t *)devpriv->ana_buf.logical_base + 1; |
11e865c1 | 1743 | |
e4632a71 HS |
1744 | /* |
1745 | * Convert ADC data to 16-bit integer values and | |
1746 | * copy to application buffer. | |
1747 | */ | |
07a36d66 | 1748 | for (i = 0; i < devpriv->adc_items; i++) { |
e4632a71 HS |
1749 | *data = s626_ai_reg_to_uint(*readaddr++); |
1750 | data++; | |
1751 | } | |
11e865c1 | 1752 | |
e4632a71 HS |
1753 | return i; |
1754 | } | |
1755 | #endif | |
11e865c1 | 1756 | |
45b281e4 HS |
1757 | static int s626_ai_eoc(struct comedi_device *dev, |
1758 | struct comedi_subdevice *s, | |
1759 | struct comedi_insn *insn, | |
1760 | unsigned long context) | |
1761 | { | |
45b281e4 HS |
1762 | unsigned int status; |
1763 | ||
de9cd5ca | 1764 | status = readl(dev->mmio + S626_P_PSR); |
45b281e4 HS |
1765 | if (status & S626_PSR_GPIO2) |
1766 | return 0; | |
1767 | return -EBUSY; | |
1768 | } | |
1769 | ||
020c44f3 HS |
1770 | static int s626_ai_insn_read(struct comedi_device *dev, |
1771 | struct comedi_subdevice *s, | |
de9cd5ca HS |
1772 | struct comedi_insn *insn, |
1773 | unsigned int *data) | |
020c44f3 HS |
1774 | { |
1775 | uint16_t chan = CR_CHAN(insn->chanspec); | |
1776 | uint16_t range = CR_RANGE(insn->chanspec); | |
f1f7efce IA |
1777 | uint16_t adc_spec = 0; |
1778 | uint32_t gpio_image; | |
5fd4b711 | 1779 | uint32_t tmp; |
45b281e4 | 1780 | int ret; |
020c44f3 | 1781 | int n; |
11e865c1 | 1782 | |
8ee52611 IA |
1783 | /* |
1784 | * Convert application's ADC specification into form | |
020c44f3 HS |
1785 | * appropriate for register programming. |
1786 | */ | |
1787 | if (range == 0) | |
d8515652 | 1788 | adc_spec = (chan << 8) | (S626_GSEL_BIPOLAR5V); |
020c44f3 | 1789 | else |
d8515652 | 1790 | adc_spec = (chan << 8) | (S626_GSEL_BIPOLAR10V); |
11e865c1 | 1791 | |
8ee52611 | 1792 | /* Switch ADC analog gain. */ |
d8515652 | 1793 | s626_debi_write(dev, S626_LP_GSEL, adc_spec); /* Set gain. */ |
11e865c1 | 1794 | |
8ee52611 | 1795 | /* Select ADC analog input channel. */ |
d8515652 | 1796 | s626_debi_write(dev, S626_LP_ISEL, adc_spec); /* Select channel. */ |
11e865c1 | 1797 | |
020c44f3 | 1798 | for (n = 0; n < insn->n; n++) { |
8ee52611 | 1799 | /* Delay 10 microseconds for analog input settling. */ |
020c44f3 | 1800 | udelay(10); |
11e865c1 | 1801 | |
be008602 | 1802 | /* Start ADC by pulsing GPIO1 low */ |
de9cd5ca | 1803 | gpio_image = readl(dev->mmio + S626_P_GPIO); |
25f8fd5e | 1804 | /* Assert ADC Start command */ |
de9cd5ca | 1805 | writel(gpio_image & ~S626_GPIO1_HI, dev->mmio + S626_P_GPIO); |
25f8fd5e | 1806 | /* and stretch it out */ |
de9cd5ca HS |
1807 | writel(gpio_image & ~S626_GPIO1_HI, dev->mmio + S626_P_GPIO); |
1808 | writel(gpio_image & ~S626_GPIO1_HI, dev->mmio + S626_P_GPIO); | |
25f8fd5e | 1809 | /* Negate ADC Start command */ |
de9cd5ca | 1810 | writel(gpio_image | S626_GPIO1_HI, dev->mmio + S626_P_GPIO); |
11e865c1 | 1811 | |
8ee52611 IA |
1812 | /* |
1813 | * Wait for ADC to complete (GPIO2 is asserted high when | |
1814 | * ADC not busy) and for data from previous conversion to | |
1815 | * shift into FB BUFFER 1 register. | |
1816 | */ | |
11e865c1 | 1817 | |
be008602 | 1818 | /* Wait for ADC done */ |
45b281e4 HS |
1819 | ret = comedi_timeout(dev, s, insn, s626_ai_eoc, 0); |
1820 | if (ret) | |
1821 | return ret; | |
11e865c1 | 1822 | |
be008602 HS |
1823 | /* Fetch ADC data */ |
1824 | if (n != 0) { | |
de9cd5ca | 1825 | tmp = readl(dev->mmio + S626_P_FB_BUFFER1); |
be008602 HS |
1826 | data[n - 1] = s626_ai_reg_to_uint(tmp); |
1827 | } | |
11e865c1 | 1828 | |
8ee52611 IA |
1829 | /* |
1830 | * Allow the ADC to stabilize for 4 microseconds before | |
020c44f3 HS |
1831 | * starting the next (final) conversion. This delay is |
1832 | * necessary to allow sufficient time between last | |
1833 | * conversion finished and the start of the next | |
1834 | * conversion. Without this delay, the last conversion's | |
1835 | * data value is sometimes set to the previous | |
1836 | * conversion's data value. | |
1837 | */ | |
1838 | udelay(4); | |
1839 | } | |
11e865c1 | 1840 | |
8ee52611 IA |
1841 | /* |
1842 | * Start a dummy conversion to cause the data from the | |
1843 | * previous conversion to be shifted in. | |
1844 | */ | |
de9cd5ca | 1845 | gpio_image = readl(dev->mmio + S626_P_GPIO); |
020c44f3 | 1846 | /* Assert ADC Start command */ |
de9cd5ca | 1847 | writel(gpio_image & ~S626_GPIO1_HI, dev->mmio + S626_P_GPIO); |
25f8fd5e | 1848 | /* and stretch it out */ |
de9cd5ca HS |
1849 | writel(gpio_image & ~S626_GPIO1_HI, dev->mmio + S626_P_GPIO); |
1850 | writel(gpio_image & ~S626_GPIO1_HI, dev->mmio + S626_P_GPIO); | |
25f8fd5e | 1851 | /* Negate ADC Start command */ |
de9cd5ca | 1852 | writel(gpio_image | S626_GPIO1_HI, dev->mmio + S626_P_GPIO); |
11e865c1 | 1853 | |
8ee52611 | 1854 | /* Wait for the data to arrive in FB BUFFER 1 register. */ |
11e865c1 | 1855 | |
be008602 | 1856 | /* Wait for ADC done */ |
571845c6 CS |
1857 | ret = comedi_timeout(dev, s, insn, s626_ai_eoc, 0); |
1858 | if (ret) | |
1859 | return ret; | |
11e865c1 | 1860 | |
8ee52611 | 1861 | /* Fetch ADC data from audio interface's input shift register. */ |
11e865c1 | 1862 | |
be008602 HS |
1863 | /* Fetch ADC data */ |
1864 | if (n != 0) { | |
de9cd5ca | 1865 | tmp = readl(dev->mmio + S626_P_FB_BUFFER1); |
be008602 HS |
1866 | data[n - 1] = s626_ai_reg_to_uint(tmp); |
1867 | } | |
11e865c1 | 1868 | |
020c44f3 HS |
1869 | return n; |
1870 | } | |
11e865c1 | 1871 | |
020c44f3 HS |
1872 | static int s626_ai_load_polllist(uint8_t *ppl, struct comedi_cmd *cmd) |
1873 | { | |
020c44f3 | 1874 | int n; |
11e865c1 | 1875 | |
020c44f3 | 1876 | for (n = 0; n < cmd->chanlist_len; n++) { |
8ee52611 | 1877 | if (CR_RANGE(cmd->chanlist[n]) == 0) |
d8515652 | 1878 | ppl[n] = CR_CHAN(cmd->chanlist[n]) | S626_RANGE_5V; |
020c44f3 | 1879 | else |
d8515652 | 1880 | ppl[n] = CR_CHAN(cmd->chanlist[n]) | S626_RANGE_10V; |
020c44f3 HS |
1881 | } |
1882 | if (n != 0) | |
d8515652 | 1883 | ppl[n - 1] |= S626_EOPL; |
11e865c1 | 1884 | |
020c44f3 HS |
1885 | return n; |
1886 | } | |
11e865c1 | 1887 | |
020c44f3 | 1888 | static int s626_ai_inttrig(struct comedi_device *dev, |
478da5c9 HS |
1889 | struct comedi_subdevice *s, |
1890 | unsigned int trig_num) | |
020c44f3 | 1891 | { |
478da5c9 HS |
1892 | struct comedi_cmd *cmd = &s->async->cmd; |
1893 | ||
1894 | if (trig_num != cmd->start_arg) | |
020c44f3 | 1895 | return -EINVAL; |
11e865c1 | 1896 | |
ddd9813e | 1897 | /* Start executing the RPS program */ |
d8515652 | 1898 | s626_mc_enable(dev, S626_MC1_ERPS1, S626_P_MC1); |
11e865c1 | 1899 | |
020c44f3 | 1900 | s->async->inttrig = NULL; |
11e865c1 | 1901 | |
020c44f3 HS |
1902 | return 1; |
1903 | } | |
11e865c1 | 1904 | |
8ee52611 IA |
1905 | /* |
1906 | * This function doesn't require a particular form, this is just what | |
6baffbc2 HS |
1907 | * happens to be used in some of the drivers. It should convert ns |
1908 | * nanoseconds to a counter value suitable for programming the device. | |
1909 | * Also, it should adjust ns so that it cooresponds to the actual time | |
8ee52611 IA |
1910 | * that the device will use. |
1911 | */ | |
a207c12f | 1912 | static int s626_ns_to_timer(unsigned int *nanosec, unsigned int flags) |
6baffbc2 HS |
1913 | { |
1914 | int divider, base; | |
1915 | ||
1916 | base = 500; /* 2MHz internal clock */ | |
1917 | ||
889277b9 IA |
1918 | switch (flags & CMDF_ROUND_MASK) { |
1919 | case CMDF_ROUND_NEAREST: | |
6baffbc2 | 1920 | default: |
d9798aa6 | 1921 | divider = DIV_ROUND_CLOSEST(*nanosec, base); |
6baffbc2 | 1922 | break; |
889277b9 | 1923 | case CMDF_ROUND_DOWN: |
6baffbc2 HS |
1924 | divider = (*nanosec) / base; |
1925 | break; | |
889277b9 | 1926 | case CMDF_ROUND_UP: |
97996da1 | 1927 | divider = DIV_ROUND_UP(*nanosec, base); |
6baffbc2 HS |
1928 | break; |
1929 | } | |
1930 | ||
1931 | *nanosec = base * divider; | |
1932 | return divider - 1; | |
1933 | } | |
1934 | ||
3a305a66 | 1935 | static void s626_timer_load(struct comedi_device *dev, |
0c9a057c | 1936 | unsigned int chan, int tick) |
e3eb08d0 | 1937 | { |
f1f7efce | 1938 | uint16_t setup = |
d8515652 | 1939 | /* Preload upon index. */ |
0830ada5 | 1940 | S626_SET_STD_LOADSRC(S626_LOADSRC_INDX) | |
d8515652 | 1941 | /* Disable hardware index. */ |
0830ada5 | 1942 | S626_SET_STD_INDXSRC(S626_INDXSRC_SOFT) | |
d8515652 | 1943 | /* Operating mode is Timer. */ |
0830ada5 | 1944 | S626_SET_STD_ENCMODE(S626_ENCMODE_TIMER) | |
d8515652 | 1945 | /* Count direction is Down. */ |
0830ada5 | 1946 | S626_SET_STD_CLKPOL(S626_CNTDIR_DOWN) | |
d8515652 | 1947 | /* Clock multiplier is 1x. */ |
0830ada5 IA |
1948 | S626_SET_STD_CLKMULT(S626_CLKMULT_1X) | |
1949 | /* Enabled by index */ | |
1950 | S626_SET_STD_CLKENAB(S626_CLKENAB_INDEX); | |
d8515652 IA |
1951 | uint16_t value_latchsrc = S626_LATCHSRC_A_INDXA; |
1952 | /* uint16_t enab = S626_CLKENAB_ALWAYS; */ | |
e3eb08d0 | 1953 | |
0c9a057c | 1954 | s626_set_mode(dev, chan, setup, false); |
e3eb08d0 | 1955 | |
8ee52611 | 1956 | /* Set the preload register */ |
0c9a057c | 1957 | s626_preload(dev, chan, tick); |
e3eb08d0 | 1958 | |
8ee52611 IA |
1959 | /* |
1960 | * Software index pulse forces the preload register to load | |
1961 | * into the counter | |
1962 | */ | |
0c9a057c HS |
1963 | s626_set_load_trig(dev, chan, 0); |
1964 | s626_pulse_index(dev, chan); | |
e3eb08d0 HS |
1965 | |
1966 | /* set reload on counter overflow */ | |
0c9a057c | 1967 | s626_set_load_trig(dev, chan, 1); |
e3eb08d0 HS |
1968 | |
1969 | /* set interrupt on overflow */ | |
0c9a057c | 1970 | s626_set_int_src(dev, chan, S626_INTSRC_OVER); |
e3eb08d0 | 1971 | |
0c9a057c HS |
1972 | s626_set_latch_source(dev, chan, value_latchsrc); |
1973 | /* s626_set_enable(dev, chan, (uint16_t)(enab != 0)); */ | |
e3eb08d0 HS |
1974 | } |
1975 | ||
8ee52611 | 1976 | /* TO COMPLETE */ |
020c44f3 HS |
1977 | static int s626_ai_cmd(struct comedi_device *dev, struct comedi_subdevice *s) |
1978 | { | |
7f2f7e05 | 1979 | struct s626_private *devpriv = dev->private; |
020c44f3 HS |
1980 | uint8_t ppl[16]; |
1981 | struct comedi_cmd *cmd = &s->async->cmd; | |
020c44f3 | 1982 | int tick; |
11e865c1 | 1983 | |
020c44f3 | 1984 | if (devpriv->ai_cmd_running) { |
730b8e15 IA |
1985 | dev_err(dev->class_dev, |
1986 | "s626_ai_cmd: Another ai_cmd is running\n"); | |
020c44f3 HS |
1987 | return -EBUSY; |
1988 | } | |
1989 | /* disable interrupt */ | |
de9cd5ca | 1990 | writel(0, dev->mmio + S626_P_IER); |
11e865c1 | 1991 | |
020c44f3 | 1992 | /* clear interrupt request */ |
de9cd5ca | 1993 | writel(S626_IRQ_RPS1 | S626_IRQ_GPIO3, dev->mmio + S626_P_ISR); |
11e865c1 | 1994 | |
020c44f3 HS |
1995 | /* clear any pending interrupt */ |
1996 | s626_dio_clear_irq(dev); | |
8ee52611 | 1997 | /* s626_enc_clear_irq(dev); */ |
11e865c1 | 1998 | |
020c44f3 HS |
1999 | /* reset ai_cmd_running flag */ |
2000 | devpriv->ai_cmd_running = 0; | |
11e865c1 | 2001 | |
020c44f3 HS |
2002 | s626_ai_load_polllist(ppl, cmd); |
2003 | devpriv->ai_cmd_running = 1; | |
2004 | devpriv->ai_convert_count = 0; | |
11e865c1 | 2005 | |
020c44f3 HS |
2006 | switch (cmd->scan_begin_src) { |
2007 | case TRIG_FOLLOW: | |
2008 | break; | |
2009 | case TRIG_TIMER: | |
8ee52611 IA |
2010 | /* |
2011 | * set a counter to generate adc trigger at scan_begin_arg | |
2012 | * interval | |
2013 | */ | |
a207c12f | 2014 | tick = s626_ns_to_timer(&cmd->scan_begin_arg, cmd->flags); |
11e865c1 | 2015 | |
020c44f3 | 2016 | /* load timer value and enable interrupt */ |
0c9a057c HS |
2017 | s626_timer_load(dev, 5, tick); |
2018 | s626_set_enable(dev, 5, S626_CLKENAB_ALWAYS); | |
020c44f3 HS |
2019 | break; |
2020 | case TRIG_EXT: | |
8ee52611 | 2021 | /* set the digital line and interrupt for scan trigger */ |
020c44f3 HS |
2022 | if (cmd->start_src != TRIG_EXT) |
2023 | s626_dio_set_irq(dev, cmd->scan_begin_arg); | |
020c44f3 HS |
2024 | break; |
2025 | } | |
11e865c1 | 2026 | |
020c44f3 HS |
2027 | switch (cmd->convert_src) { |
2028 | case TRIG_NOW: | |
2029 | break; | |
2030 | case TRIG_TIMER: | |
8ee52611 IA |
2031 | /* |
2032 | * set a counter to generate adc trigger at convert_arg | |
2033 | * interval | |
2034 | */ | |
a207c12f | 2035 | tick = s626_ns_to_timer(&cmd->convert_arg, cmd->flags); |
11e865c1 | 2036 | |
020c44f3 | 2037 | /* load timer value and enable interrupt */ |
0c9a057c HS |
2038 | s626_timer_load(dev, 4, tick); |
2039 | s626_set_enable(dev, 4, S626_CLKENAB_INDEX); | |
020c44f3 HS |
2040 | break; |
2041 | case TRIG_EXT: | |
8ee52611 IA |
2042 | /* set the digital line and interrupt for convert trigger */ |
2043 | if (cmd->scan_begin_src != TRIG_EXT && | |
2044 | cmd->start_src == TRIG_EXT) | |
020c44f3 | 2045 | s626_dio_set_irq(dev, cmd->convert_arg); |
020c44f3 HS |
2046 | break; |
2047 | } | |
11e865c1 | 2048 | |
31de1948 | 2049 | s626_reset_adc(dev, ppl); |
11e865c1 | 2050 | |
020c44f3 HS |
2051 | switch (cmd->start_src) { |
2052 | case TRIG_NOW: | |
ddd9813e | 2053 | /* Trigger ADC scan loop start */ |
d8515652 | 2054 | /* s626_mc_enable(dev, S626_MC2_ADC_RPS, S626_P_MC2); */ |
11e865c1 | 2055 | |
ddd9813e | 2056 | /* Start executing the RPS program */ |
d8515652 | 2057 | s626_mc_enable(dev, S626_MC1_ERPS1, S626_P_MC1); |
020c44f3 HS |
2058 | s->async->inttrig = NULL; |
2059 | break; | |
2060 | case TRIG_EXT: | |
2061 | /* configure DIO channel for acquisition trigger */ | |
2062 | s626_dio_set_irq(dev, cmd->start_arg); | |
020c44f3 HS |
2063 | s->async->inttrig = NULL; |
2064 | break; | |
2065 | case TRIG_INT: | |
2066 | s->async->inttrig = s626_ai_inttrig; | |
2067 | break; | |
11e865c1 | 2068 | } |
b6c77757 | 2069 | |
020c44f3 | 2070 | /* enable interrupt */ |
de9cd5ca | 2071 | writel(S626_IRQ_GPIO3 | S626_IRQ_RPS1, dev->mmio + S626_P_IER); |
b6c77757 | 2072 | |
020c44f3 HS |
2073 | return 0; |
2074 | } | |
b6c77757 | 2075 | |
020c44f3 HS |
2076 | static int s626_ai_cmdtest(struct comedi_device *dev, |
2077 | struct comedi_subdevice *s, struct comedi_cmd *cmd) | |
2078 | { | |
2079 | int err = 0; | |
c646efe1 | 2080 | unsigned int arg; |
b6c77757 | 2081 | |
27020ffe | 2082 | /* Step 1 : check if triggers are trivially valid */ |
b6c77757 | 2083 | |
d044e28f IA |
2084 | err |= comedi_check_trigger_src(&cmd->start_src, |
2085 | TRIG_NOW | TRIG_INT | TRIG_EXT); | |
2086 | err |= comedi_check_trigger_src(&cmd->scan_begin_src, | |
2087 | TRIG_TIMER | TRIG_EXT | TRIG_FOLLOW); | |
2088 | err |= comedi_check_trigger_src(&cmd->convert_src, | |
2089 | TRIG_TIMER | TRIG_EXT | TRIG_NOW); | |
2090 | err |= comedi_check_trigger_src(&cmd->scan_end_src, TRIG_COUNT); | |
2091 | err |= comedi_check_trigger_src(&cmd->stop_src, TRIG_COUNT | TRIG_NONE); | |
11e865c1 | 2092 | |
020c44f3 HS |
2093 | if (err) |
2094 | return 1; | |
11e865c1 | 2095 | |
27020ffe | 2096 | /* Step 2a : make sure trigger sources are unique */ |
11e865c1 | 2097 | |
d044e28f IA |
2098 | err |= comedi_check_trigger_is_unique(cmd->start_src); |
2099 | err |= comedi_check_trigger_is_unique(cmd->scan_begin_src); | |
2100 | err |= comedi_check_trigger_is_unique(cmd->convert_src); | |
2101 | err |= comedi_check_trigger_is_unique(cmd->stop_src); | |
27020ffe HS |
2102 | |
2103 | /* Step 2b : and mutually compatible */ | |
020c44f3 HS |
2104 | |
2105 | if (err) | |
2106 | return 2; | |
2107 | ||
478da5c9 | 2108 | /* Step 3: check if arguments are trivially valid */ |
020c44f3 | 2109 | |
478da5c9 HS |
2110 | switch (cmd->start_src) { |
2111 | case TRIG_NOW: | |
2112 | case TRIG_INT: | |
d044e28f | 2113 | err |= comedi_check_trigger_arg_is(&cmd->start_arg, 0); |
478da5c9 HS |
2114 | break; |
2115 | case TRIG_EXT: | |
d044e28f | 2116 | err |= comedi_check_trigger_arg_max(&cmd->start_arg, 39); |
478da5c9 HS |
2117 | break; |
2118 | } | |
2119 | ||
53a254b9 | 2120 | if (cmd->scan_begin_src == TRIG_EXT) |
d044e28f | 2121 | err |= comedi_check_trigger_arg_max(&cmd->scan_begin_arg, 39); |
53a254b9 | 2122 | if (cmd->convert_src == TRIG_EXT) |
d044e28f | 2123 | err |= comedi_check_trigger_arg_max(&cmd->convert_arg, 39); |
11e865c1 | 2124 | |
676921c9 IA |
2125 | #define S626_MAX_SPEED 200000 /* in nanoseconds */ |
2126 | #define S626_MIN_SPEED 2000000000 /* in nanoseconds */ | |
11e865c1 | 2127 | |
020c44f3 | 2128 | if (cmd->scan_begin_src == TRIG_TIMER) { |
d044e28f IA |
2129 | err |= comedi_check_trigger_arg_min(&cmd->scan_begin_arg, |
2130 | S626_MAX_SPEED); | |
2131 | err |= comedi_check_trigger_arg_max(&cmd->scan_begin_arg, | |
2132 | S626_MIN_SPEED); | |
020c44f3 | 2133 | } else { |
d044e28f IA |
2134 | /* |
2135 | * external trigger | |
2136 | * should be level/edge, hi/lo specification here | |
2137 | * should specify multiple external triggers | |
2138 | * err |= comedi_check_trigger_arg_max(&cmd->scan_begin_arg, 9); | |
2139 | */ | |
020c44f3 HS |
2140 | } |
2141 | if (cmd->convert_src == TRIG_TIMER) { | |
d044e28f IA |
2142 | err |= comedi_check_trigger_arg_min(&cmd->convert_arg, |
2143 | S626_MAX_SPEED); | |
2144 | err |= comedi_check_trigger_arg_max(&cmd->convert_arg, | |
2145 | S626_MIN_SPEED); | |
020c44f3 | 2146 | } else { |
d044e28f IA |
2147 | /* |
2148 | * external trigger - see above | |
2149 | * err |= comedi_check_trigger_arg_max(&cmd->scan_begin_arg, 9); | |
2150 | */ | |
020c44f3 | 2151 | } |
11e865c1 | 2152 | |
d044e28f IA |
2153 | err |= comedi_check_trigger_arg_is(&cmd->scan_end_arg, |
2154 | cmd->chanlist_len); | |
53a254b9 HS |
2155 | |
2156 | if (cmd->stop_src == TRIG_COUNT) | |
d044e28f | 2157 | err |= comedi_check_trigger_arg_min(&cmd->stop_arg, 1); |
53a254b9 | 2158 | else /* TRIG_NONE */ |
d044e28f | 2159 | err |= comedi_check_trigger_arg_is(&cmd->stop_arg, 0); |
11e865c1 | 2160 | |
020c44f3 HS |
2161 | if (err) |
2162 | return 3; | |
2163 | ||
2164 | /* step 4: fix up any arguments */ | |
2165 | ||
2166 | if (cmd->scan_begin_src == TRIG_TIMER) { | |
c646efe1 | 2167 | arg = cmd->scan_begin_arg; |
a207c12f | 2168 | s626_ns_to_timer(&arg, cmd->flags); |
d044e28f | 2169 | err |= comedi_check_trigger_arg_is(&cmd->scan_begin_arg, arg); |
020c44f3 | 2170 | } |
c646efe1 | 2171 | |
020c44f3 | 2172 | if (cmd->convert_src == TRIG_TIMER) { |
c646efe1 | 2173 | arg = cmd->convert_arg; |
a207c12f | 2174 | s626_ns_to_timer(&arg, cmd->flags); |
d044e28f | 2175 | err |= comedi_check_trigger_arg_is(&cmd->convert_arg, arg); |
c646efe1 HS |
2176 | |
2177 | if (cmd->scan_begin_src == TRIG_TIMER) { | |
2178 | arg = cmd->convert_arg * cmd->scan_end_arg; | |
d044e28f IA |
2179 | err |= comedi_check_trigger_arg_min(&cmd-> |
2180 | scan_begin_arg, | |
2181 | arg); | |
020c44f3 | 2182 | } |
11e865c1 | 2183 | } |
11e865c1 | 2184 | |
020c44f3 HS |
2185 | if (err) |
2186 | return 4; | |
2187 | ||
2188 | return 0; | |
11e865c1 GP |
2189 | } |
2190 | ||
020c44f3 | 2191 | static int s626_ai_cancel(struct comedi_device *dev, struct comedi_subdevice *s) |
11e865c1 | 2192 | { |
7f2f7e05 HS |
2193 | struct s626_private *devpriv = dev->private; |
2194 | ||
c5cf4606 | 2195 | /* Stop RPS program in case it is currently running */ |
d8515652 | 2196 | s626_mc_disable(dev, S626_MC1_ERPS1, S626_P_MC1); |
11e865c1 | 2197 | |
020c44f3 | 2198 | /* disable master interrupt */ |
de9cd5ca | 2199 | writel(0, dev->mmio + S626_P_IER); |
11e865c1 | 2200 | |
020c44f3 | 2201 | devpriv->ai_cmd_running = 0; |
11e865c1 | 2202 | |
020c44f3 HS |
2203 | return 0; |
2204 | } | |
11e865c1 | 2205 | |
18259ffc HS |
2206 | static int s626_ao_insn_write(struct comedi_device *dev, |
2207 | struct comedi_subdevice *s, | |
2208 | struct comedi_insn *insn, | |
2209 | unsigned int *data) | |
11e865c1 | 2210 | { |
18259ffc | 2211 | unsigned int chan = CR_CHAN(insn->chanspec); |
020c44f3 | 2212 | int i; |
11e865c1 | 2213 | |
020c44f3 | 2214 | for (i = 0; i < insn->n; i++) { |
18259ffc HS |
2215 | int16_t dacdata = (int16_t)data[i]; |
2216 | int ret; | |
2217 | ||
020c44f3 | 2218 | dacdata -= (0x1fff); |
11e865c1 | 2219 | |
a7aa94ce CS |
2220 | ret = s626_set_dac(dev, chan, dacdata); |
2221 | if (ret) | |
2222 | return ret; | |
11e865c1 | 2223 | |
18259ffc HS |
2224 | s->readback[chan] = data[i]; |
2225 | } | |
11e865c1 | 2226 | |
18259ffc | 2227 | return insn->n; |
020c44f3 | 2228 | } |
11e865c1 | 2229 | |
8ee52611 IA |
2230 | /* *************** DIGITAL I/O FUNCTIONS *************** */ |
2231 | ||
2232 | /* | |
020c44f3 HS |
2233 | * All DIO functions address a group of DIO channels by means of |
2234 | * "group" argument. group may be 0, 1 or 2, which correspond to DIO | |
2235 | * ports A, B and C, respectively. | |
2236 | */ | |
11e865c1 | 2237 | |
020c44f3 HS |
2238 | static void s626_dio_init(struct comedi_device *dev) |
2239 | { | |
2240 | uint16_t group; | |
11e865c1 | 2241 | |
8ee52611 | 2242 | /* Prepare to treat writes to WRCapSel as capture disables. */ |
d8515652 | 2243 | s626_debi_write(dev, S626_LP_MISC1, S626_MISC1_NOEDCAP); |
11e865c1 | 2244 | |
8ee52611 | 2245 | /* For each group of sixteen channels ... */ |
020c44f3 | 2246 | for (group = 0; group < S626_DIO_BANKS; group++) { |
100b4edc | 2247 | /* Disable all interrupts */ |
d8515652 | 2248 | s626_debi_write(dev, S626_LP_WRINTSEL(group), 0); |
100b4edc | 2249 | /* Disable all event captures */ |
d8515652 | 2250 | s626_debi_write(dev, S626_LP_WRCAPSEL(group), 0xffff); |
100b4edc | 2251 | /* Init all DIOs to default edge polarity */ |
d8515652 | 2252 | s626_debi_write(dev, S626_LP_WREDGSEL(group), 0); |
100b4edc | 2253 | /* Program all outputs to inactive state */ |
d8515652 | 2254 | s626_debi_write(dev, S626_LP_WRDOUT(group), 0); |
11e865c1 | 2255 | } |
020c44f3 | 2256 | } |
11e865c1 | 2257 | |
020c44f3 HS |
2258 | static int s626_dio_insn_bits(struct comedi_device *dev, |
2259 | struct comedi_subdevice *s, | |
1515e522 HS |
2260 | struct comedi_insn *insn, |
2261 | unsigned int *data) | |
020c44f3 | 2262 | { |
100b4edc | 2263 | unsigned long group = (unsigned long)s->private; |
11e865c1 | 2264 | |
6ea79c1d | 2265 | if (comedi_dio_update_state(s, data)) |
d8515652 | 2266 | s626_debi_write(dev, S626_LP_WRDOUT(group), s->state); |
6ea79c1d | 2267 | |
d8515652 | 2268 | data[1] = s626_debi_read(dev, S626_LP_RDDIN(group)); |
11e865c1 | 2269 | |
020c44f3 | 2270 | return insn->n; |
11e865c1 GP |
2271 | } |
2272 | ||
020c44f3 HS |
2273 | static int s626_dio_insn_config(struct comedi_device *dev, |
2274 | struct comedi_subdevice *s, | |
e920fad2 HS |
2275 | struct comedi_insn *insn, |
2276 | unsigned int *data) | |
11e865c1 | 2277 | { |
100b4edc | 2278 | unsigned long group = (unsigned long)s->private; |
ddf62f2c HS |
2279 | int ret; |
2280 | ||
2281 | ret = comedi_dio_insn_config(dev, s, insn, data, 0); | |
2282 | if (ret) | |
2283 | return ret; | |
11e865c1 | 2284 | |
d8515652 | 2285 | s626_debi_write(dev, S626_LP_WRDOUT(group), s->io_bits); |
11e865c1 | 2286 | |
e920fad2 | 2287 | return insn->n; |
11e865c1 GP |
2288 | } |
2289 | ||
8ee52611 IA |
2290 | /* |
2291 | * Now this function initializes the value of the counter (data[0]) | |
2292 | * and set the subdevice. To complete with trigger and interrupt | |
2293 | * configuration. | |
2294 | * | |
2295 | * FIXME: data[0] is supposed to be an INSN_CONFIG_xxx constant indicating | |
affdc230 | 2296 | * what is being configured, but this function appears to be using data[0] |
8ee52611 IA |
2297 | * as a variable. |
2298 | */ | |
020c44f3 HS |
2299 | static int s626_enc_insn_config(struct comedi_device *dev, |
2300 | struct comedi_subdevice *s, | |
2301 | struct comedi_insn *insn, unsigned int *data) | |
2302 | { | |
0c9a057c | 2303 | unsigned int chan = CR_CHAN(insn->chanspec); |
f1f7efce | 2304 | uint16_t setup = |
d8515652 | 2305 | /* Preload upon index. */ |
0830ada5 | 2306 | S626_SET_STD_LOADSRC(S626_LOADSRC_INDX) | |
d8515652 | 2307 | /* Disable hardware index. */ |
0830ada5 | 2308 | S626_SET_STD_INDXSRC(S626_INDXSRC_SOFT) | |
d8515652 | 2309 | /* Operating mode is Counter. */ |
0830ada5 | 2310 | S626_SET_STD_ENCMODE(S626_ENCMODE_COUNTER) | |
d8515652 | 2311 | /* Active high clock. */ |
0830ada5 | 2312 | S626_SET_STD_CLKPOL(S626_CLKPOL_POS) | |
d8515652 | 2313 | /* Clock multiplier is 1x. */ |
0830ada5 IA |
2314 | S626_SET_STD_CLKMULT(S626_CLKMULT_1X) | |
2315 | /* Enabled by index */ | |
2316 | S626_SET_STD_CLKENAB(S626_CLKENAB_INDEX); | |
c3e3a56d | 2317 | /* uint16_t disable_int_src = true; */ |
8ee52611 | 2318 | /* uint32_t Preloadvalue; //Counter initial value */ |
d8515652 IA |
2319 | uint16_t value_latchsrc = S626_LATCHSRC_AB_READ; |
2320 | uint16_t enab = S626_CLKENAB_ALWAYS; | |
11e865c1 | 2321 | |
8ee52611 | 2322 | /* (data==NULL) ? (Preloadvalue=0) : (Preloadvalue=data[0]); */ |
11e865c1 | 2323 | |
0c9a057c HS |
2324 | s626_set_mode(dev, chan, setup, true); |
2325 | s626_preload(dev, chan, data[0]); | |
2326 | s626_pulse_index(dev, chan); | |
2327 | s626_set_latch_source(dev, chan, value_latchsrc); | |
2328 | s626_set_enable(dev, chan, (enab != 0)); | |
11e865c1 | 2329 | |
020c44f3 HS |
2330 | return insn->n; |
2331 | } | |
11e865c1 | 2332 | |
020c44f3 HS |
2333 | static int s626_enc_insn_read(struct comedi_device *dev, |
2334 | struct comedi_subdevice *s, | |
81202ecf HS |
2335 | struct comedi_insn *insn, |
2336 | unsigned int *data) | |
020c44f3 | 2337 | { |
81202ecf HS |
2338 | unsigned int chan = CR_CHAN(insn->chanspec); |
2339 | uint16_t cntr_latch_reg = S626_LP_CNTR(chan); | |
2340 | int i; | |
11e865c1 | 2341 | |
81202ecf HS |
2342 | for (i = 0; i < insn->n; i++) { |
2343 | unsigned int val; | |
11e865c1 | 2344 | |
81202ecf HS |
2345 | /* |
2346 | * Read the counter's output latch LSW/MSW. | |
2347 | * Latches on LSW read. | |
2348 | */ | |
2349 | val = s626_debi_read(dev, cntr_latch_reg); | |
2350 | val |= (s626_debi_read(dev, cntr_latch_reg + 2) << 16); | |
2351 | data[i] = val; | |
2352 | } | |
2353 | ||
2354 | return insn->n; | |
020c44f3 | 2355 | } |
11e865c1 | 2356 | |
020c44f3 HS |
2357 | static int s626_enc_insn_write(struct comedi_device *dev, |
2358 | struct comedi_subdevice *s, | |
2359 | struct comedi_insn *insn, unsigned int *data) | |
2360 | { | |
0c9a057c | 2361 | unsigned int chan = CR_CHAN(insn->chanspec); |
11e865c1 | 2362 | |
8ee52611 | 2363 | /* Set the preload register */ |
0c9a057c | 2364 | s626_preload(dev, chan, data[0]); |
11e865c1 | 2365 | |
8ee52611 IA |
2366 | /* |
2367 | * Software index pulse forces the preload register to load | |
2368 | * into the counter | |
2369 | */ | |
0c9a057c HS |
2370 | s626_set_load_trig(dev, chan, 0); |
2371 | s626_pulse_index(dev, chan); | |
2372 | s626_set_load_trig(dev, chan, 2); | |
11e865c1 | 2373 | |
020c44f3 | 2374 | return 1; |
11e865c1 GP |
2375 | } |
2376 | ||
31de1948 | 2377 | static void s626_write_misc2(struct comedi_device *dev, uint16_t new_image) |
11e865c1 | 2378 | { |
d8515652 IA |
2379 | s626_debi_write(dev, S626_LP_MISC1, S626_MISC1_WENABLE); |
2380 | s626_debi_write(dev, S626_LP_WRMISC2, new_image); | |
2381 | s626_debi_write(dev, S626_LP_MISC1, S626_MISC1_WDISABLE); | |
020c44f3 | 2382 | } |
11e865c1 | 2383 | |
31de1948 | 2384 | static void s626_counters_init(struct comedi_device *dev) |
11e865c1 | 2385 | { |
020c44f3 | 2386 | int chan; |
f1f7efce | 2387 | uint16_t setup = |
d8515652 | 2388 | /* Preload upon index. */ |
0830ada5 | 2389 | S626_SET_STD_LOADSRC(S626_LOADSRC_INDX) | |
d8515652 | 2390 | /* Disable hardware index. */ |
0830ada5 | 2391 | S626_SET_STD_INDXSRC(S626_INDXSRC_SOFT) | |
d8515652 | 2392 | /* Operating mode is counter. */ |
0830ada5 | 2393 | S626_SET_STD_ENCMODE(S626_ENCMODE_COUNTER) | |
d8515652 | 2394 | /* Active high clock. */ |
0830ada5 | 2395 | S626_SET_STD_CLKPOL(S626_CLKPOL_POS) | |
d8515652 | 2396 | /* Clock multiplier is 1x. */ |
0830ada5 | 2397 | S626_SET_STD_CLKMULT(S626_CLKMULT_1X) | |
d8515652 | 2398 | /* Enabled by index */ |
0830ada5 | 2399 | S626_SET_STD_CLKENAB(S626_CLKENAB_INDEX); |
8ee52611 IA |
2400 | |
2401 | /* | |
2402 | * Disable all counter interrupts and clear any captured counter events. | |
2403 | */ | |
020c44f3 | 2404 | for (chan = 0; chan < S626_ENCODER_CHANNELS; chan++) { |
0c9a057c HS |
2405 | s626_set_mode(dev, chan, setup, true); |
2406 | s626_set_int_src(dev, chan, 0); | |
2407 | s626_reset_cap_flags(dev, chan); | |
2408 | s626_set_enable(dev, chan, S626_CLKENAB_ALWAYS); | |
020c44f3 | 2409 | } |
020c44f3 | 2410 | } |
11e865c1 | 2411 | |
b7047895 HS |
2412 | static int s626_allocate_dma_buffers(struct comedi_device *dev) |
2413 | { | |
2414 | struct pci_dev *pcidev = comedi_to_pci_dev(dev); | |
7f2f7e05 | 2415 | struct s626_private *devpriv = dev->private; |
b7047895 HS |
2416 | void *addr; |
2417 | dma_addr_t appdma; | |
2418 | ||
d8515652 | 2419 | addr = pci_alloc_consistent(pcidev, S626_DMABUF_SIZE, &appdma); |
b7047895 HS |
2420 | if (!addr) |
2421 | return -ENOMEM; | |
07a36d66 IA |
2422 | devpriv->ana_buf.logical_base = addr; |
2423 | devpriv->ana_buf.physical_base = appdma; | |
b7047895 | 2424 | |
d8515652 | 2425 | addr = pci_alloc_consistent(pcidev, S626_DMABUF_SIZE, &appdma); |
b7047895 HS |
2426 | if (!addr) |
2427 | return -ENOMEM; | |
07a36d66 IA |
2428 | devpriv->rps_buf.logical_base = addr; |
2429 | devpriv->rps_buf.physical_base = appdma; | |
b7047895 | 2430 | |
b7047895 HS |
2431 | return 0; |
2432 | } | |
2433 | ||
3757e795 HS |
2434 | static void s626_free_dma_buffers(struct comedi_device *dev) |
2435 | { | |
2436 | struct pci_dev *pcidev = comedi_to_pci_dev(dev); | |
2437 | struct s626_private *devpriv = dev->private; | |
2438 | ||
2439 | if (!devpriv) | |
2440 | return; | |
2441 | ||
2442 | if (devpriv->rps_buf.logical_base) | |
2443 | pci_free_consistent(pcidev, S626_DMABUF_SIZE, | |
2444 | devpriv->rps_buf.logical_base, | |
2445 | devpriv->rps_buf.physical_base); | |
2446 | if (devpriv->ana_buf.logical_base) | |
2447 | pci_free_consistent(pcidev, S626_DMABUF_SIZE, | |
2448 | devpriv->ana_buf.logical_base, | |
2449 | devpriv->ana_buf.physical_base); | |
2450 | } | |
2451 | ||
a7aa94ce | 2452 | static int s626_initialize(struct comedi_device *dev) |
020c44f3 | 2453 | { |
7f2f7e05 | 2454 | struct s626_private *devpriv = dev->private; |
f1f7efce | 2455 | dma_addr_t phys_buf; |
68ad0ae0 | 2456 | uint16_t chan; |
020c44f3 | 2457 | int i; |
a7aa94ce | 2458 | int ret; |
11e865c1 | 2459 | |
54a2a02e | 2460 | /* Enable DEBI and audio pins, enable I2C interface */ |
d8515652 IA |
2461 | s626_mc_enable(dev, S626_MC1_DEBI | S626_MC1_AUDIO | S626_MC1_I2C, |
2462 | S626_P_MC1); | |
54a2a02e HS |
2463 | |
2464 | /* | |
8ee52611 | 2465 | * Configure DEBI operating mode |
54a2a02e | 2466 | * |
8ee52611 IA |
2467 | * Local bus is 16 bits wide |
2468 | * Declare DEBI transfer timeout interval | |
2469 | * Set up byte lane steering | |
2470 | * Intel-compatible local bus (DEBI never times out) | |
54a2a02e | 2471 | */ |
d8515652 IA |
2472 | writel(S626_DEBI_CFG_SLAVE16 | |
2473 | (S626_DEBI_TOUT << S626_DEBI_CFG_TOUT_BIT) | S626_DEBI_SWAP | | |
de9cd5ca | 2474 | S626_DEBI_CFG_INTEL, dev->mmio + S626_P_DEBICFG); |
54a2a02e HS |
2475 | |
2476 | /* Disable MMU paging */ | |
de9cd5ca | 2477 | writel(S626_DEBI_PAGE_DISABLE, dev->mmio + S626_P_DEBIPAGE); |
54a2a02e HS |
2478 | |
2479 | /* Init GPIO so that ADC Start* is negated */ | |
de9cd5ca | 2480 | writel(S626_GPIO_BASE | S626_GPIO1_HI, dev->mmio + S626_P_GPIO); |
68ad0ae0 | 2481 | |
17553c88 | 2482 | /* I2C device address for onboard eeprom (revb) */ |
07a36d66 | 2483 | devpriv->i2c_adrs = 0xA0; |
11e865c1 | 2484 | |
54a2a02e HS |
2485 | /* |
2486 | * Issue an I2C ABORT command to halt any I2C | |
2487 | * operation in progress and reset BUSY flag. | |
2488 | */ | |
d8515652 | 2489 | writel(S626_I2C_CLKSEL | S626_I2C_ABORT, |
de9cd5ca | 2490 | dev->mmio + S626_P_I2CSTAT); |
d8515652 | 2491 | s626_mc_enable(dev, S626_MC2_UPLD_IIC, S626_P_MC2); |
571845c6 CS |
2492 | ret = comedi_timeout(dev, NULL, NULL, s626_i2c_handshake_eoc, 0); |
2493 | if (ret) | |
2494 | return ret; | |
68ad0ae0 | 2495 | |
54a2a02e HS |
2496 | /* |
2497 | * Per SAA7146 data sheet, write to STATUS | |
2498 | * reg twice to reset all I2C error flags. | |
2499 | */ | |
68ad0ae0 | 2500 | for (i = 0; i < 2; i++) { |
de9cd5ca | 2501 | writel(S626_I2C_CLKSEL, dev->mmio + S626_P_I2CSTAT); |
d8515652 | 2502 | s626_mc_enable(dev, S626_MC2_UPLD_IIC, S626_P_MC2); |
2061d410 RKM |
2503 | ret = comedi_timeout(dev, NULL, |
2504 | NULL, s626_i2c_handshake_eoc, 0); | |
571845c6 CS |
2505 | if (ret) |
2506 | return ret; | |
68ad0ae0 | 2507 | } |
11e865c1 | 2508 | |
54a2a02e HS |
2509 | /* |
2510 | * Init audio interface functional attributes: set DAC/ADC | |
68ad0ae0 HS |
2511 | * serial clock rates, invert DAC serial clock so that |
2512 | * DAC data setup times are satisfied, enable DAC serial | |
2513 | * clock out. | |
2514 | */ | |
de9cd5ca | 2515 | writel(S626_ACON2_INIT, dev->mmio + S626_P_ACON2); |
11e865c1 | 2516 | |
54a2a02e HS |
2517 | /* |
2518 | * Set up TSL1 slot list, which is used to control the | |
d8515652 IA |
2519 | * accumulation of ADC data: S626_RSD1 = shift data in on SD1. |
2520 | * S626_SIB_A1 = store data uint8_t at next available location | |
54a2a02e HS |
2521 | * in FB BUFFER1 register. |
2522 | */ | |
de9cd5ca | 2523 | writel(S626_RSD1 | S626_SIB_A1, dev->mmio + S626_P_TSL1); |
d8515652 | 2524 | writel(S626_RSD1 | S626_SIB_A1 | S626_EOS, |
de9cd5ca | 2525 | dev->mmio + S626_P_TSL1 + 4); |
11e865c1 | 2526 | |
54a2a02e | 2527 | /* Enable TSL1 slot list so that it executes all the time */ |
de9cd5ca | 2528 | writel(S626_ACON1_ADCSTART, dev->mmio + S626_P_ACON1); |
11e865c1 | 2529 | |
54a2a02e HS |
2530 | /* |
2531 | * Initialize RPS registers used for ADC | |
2532 | */ | |
11e865c1 | 2533 | |
54a2a02e | 2534 | /* Physical start of RPS program */ |
07a36d66 | 2535 | writel((uint32_t)devpriv->rps_buf.physical_base, |
de9cd5ca | 2536 | dev->mmio + S626_P_RPSADDR1); |
54a2a02e | 2537 | /* RPS program performs no explicit mem writes */ |
de9cd5ca | 2538 | writel(0, dev->mmio + S626_P_RPSPAGE1); |
54a2a02e | 2539 | /* Disable RPS timeouts */ |
de9cd5ca | 2540 | writel(0, dev->mmio + S626_P_RPS1_TOUT); |
11e865c1 | 2541 | |
59747847 HS |
2542 | #if 0 |
2543 | /* | |
2544 | * SAA7146 BUG WORKAROUND | |
2545 | * | |
2546 | * Initialize SAA7146 ADC interface to a known state by | |
2547 | * invoking ADCs until FB BUFFER 1 register shows that it | |
2548 | * is correctly receiving ADC data. This is necessary | |
2549 | * because the SAA7146 ADC interface does not start up in | |
2550 | * a defined state after a PCI reset. | |
68ad0ae0 | 2551 | */ |
59747847 | 2552 | { |
9c9ab3c1 | 2553 | struct comedi_subdevice *s = dev->read_subdev; |
f1f7efce IA |
2554 | uint8_t poll_list; |
2555 | uint16_t adc_data; | |
2556 | uint16_t start_val; | |
8ee52611 IA |
2557 | uint16_t index; |
2558 | unsigned int data[16]; | |
59747847 | 2559 | |
8ee52611 | 2560 | /* Create a simple polling list for analog input channel 0 */ |
d8515652 | 2561 | poll_list = S626_EOPL; |
31de1948 | 2562 | s626_reset_adc(dev, &poll_list); |
59747847 | 2563 | |
8ee52611 | 2564 | /* Get initial ADC value */ |
9c9ab3c1 | 2565 | s626_ai_rinsn(dev, s, NULL, data); |
f1f7efce | 2566 | start_val = data[0]; |
59747847 | 2567 | |
8ee52611 IA |
2568 | /* |
2569 | * VERSION 2.01 CHANGE: TIMEOUT ADDED TO PREVENT HANGED | |
2570 | * EXECUTION. | |
2571 | * | |
2572 | * Invoke ADCs until the new ADC value differs from the initial | |
2573 | * value or a timeout occurs. The timeout protects against the | |
2574 | * possibility that the driver is restarting and the ADC data is | |
2575 | * a fixed value resulting from the applied ADC analog input | |
2576 | * being unusually quiet or at the rail. | |
2577 | */ | |
2578 | for (index = 0; index < 500; index++) { | |
9c9ab3c1 | 2579 | s626_ai_rinsn(dev, s, NULL, data); |
f1f7efce IA |
2580 | adc_data = data[0]; |
2581 | if (adc_data != start_val) | |
8ee52611 IA |
2582 | break; |
2583 | } | |
59747847 HS |
2584 | } |
2585 | #endif /* SAA7146 BUG WORKAROUND */ | |
11e865c1 | 2586 | |
54a2a02e HS |
2587 | /* |
2588 | * Initialize the DAC interface | |
2589 | */ | |
11e865c1 | 2590 | |
54a2a02e HS |
2591 | /* |
2592 | * Init Audio2's output DMAC attributes: | |
2593 | * burst length = 1 DWORD | |
2594 | * threshold = 1 DWORD. | |
68ad0ae0 | 2595 | */ |
de9cd5ca | 2596 | writel(0, dev->mmio + S626_P_PCI_BT_A); |
68ad0ae0 | 2597 | |
54a2a02e HS |
2598 | /* |
2599 | * Init Audio2's output DMA physical addresses. The protection | |
68ad0ae0 HS |
2600 | * address is set to 1 DWORD past the base address so that a |
2601 | * single DWORD will be transferred each time a DMA transfer is | |
54a2a02e HS |
2602 | * enabled. |
2603 | */ | |
f1f7efce | 2604 | phys_buf = devpriv->ana_buf.physical_base + |
d8515652 | 2605 | (S626_DAC_WDMABUF_OS * sizeof(uint32_t)); |
de9cd5ca | 2606 | writel((uint32_t)phys_buf, dev->mmio + S626_P_BASEA2_OUT); |
f1f7efce | 2607 | writel((uint32_t)(phys_buf + sizeof(uint32_t)), |
de9cd5ca | 2608 | dev->mmio + S626_P_PROTA2_OUT); |
68ad0ae0 | 2609 | |
54a2a02e HS |
2610 | /* |
2611 | * Cache Audio2's output DMA buffer logical address. This is | |
2612 | * where DAC data is buffered for A2 output DMA transfers. | |
2613 | */ | |
07a36d66 | 2614 | devpriv->dac_wbuf = (uint32_t *)devpriv->ana_buf.logical_base + |
d8515652 | 2615 | S626_DAC_WDMABUF_OS; |
68ad0ae0 | 2616 | |
54a2a02e HS |
2617 | /* |
2618 | * Audio2's output channels does not use paging. The | |
2619 | * protection violation handling bit is set so that the | |
2620 | * DMAC will automatically halt and its PCI address pointer | |
2621 | * will be reset when the protection address is reached. | |
2622 | */ | |
de9cd5ca | 2623 | writel(8, dev->mmio + S626_P_PAGEA2_OUT); |
68ad0ae0 | 2624 | |
54a2a02e HS |
2625 | /* |
2626 | * Initialize time slot list 2 (TSL2), which is used to control | |
68ad0ae0 HS |
2627 | * the clock generation for and serialization of data to be sent |
2628 | * to the DAC devices. Slot 0 is a NOP that is used to trap TSL | |
2629 | * execution; this permits other slots to be safely modified | |
2630 | * without first turning off the TSL sequencer (which is | |
2631 | * apparently impossible to do). Also, SD3 (which is driven by a | |
2632 | * pull-up resistor) is shifted in and stored to the MSB of | |
2633 | * FB_BUFFER2 to be used as evidence that the slot sequence has | |
2634 | * not yet finished executing. | |
2635 | */ | |
11e865c1 | 2636 | |
54a2a02e | 2637 | /* Slot 0: Trap TSL execution, shift 0xFF into FB_BUFFER2 */ |
d8515652 | 2638 | writel(S626_XSD2 | S626_RSD3 | S626_SIB_A2 | S626_EOS, |
de9cd5ca | 2639 | dev->mmio + S626_VECTPORT(0)); |
11e865c1 | 2640 | |
54a2a02e HS |
2641 | /* |
2642 | * Initialize slot 1, which is constant. Slot 1 causes a | |
68ad0ae0 HS |
2643 | * DWORD to be transferred from audio channel 2's output FIFO |
2644 | * to the FIFO's output buffer so that it can be serialized | |
2645 | * and sent to the DAC during subsequent slots. All remaining | |
2646 | * slots are dynamically populated as required by the target | |
2647 | * DAC device. | |
2648 | */ | |
54a2a02e HS |
2649 | |
2650 | /* Slot 1: Fetch DWORD from Audio2's output FIFO */ | |
de9cd5ca | 2651 | writel(S626_LF_A2, dev->mmio + S626_VECTPORT(1)); |
11e865c1 | 2652 | |
54a2a02e | 2653 | /* Start DAC's audio interface (TSL2) running */ |
de9cd5ca | 2654 | writel(S626_ACON1_DACSTART, dev->mmio + S626_P_ACON1); |
11e865c1 | 2655 | |
54a2a02e HS |
2656 | /* |
2657 | * Init Trim DACs to calibrated values. Do it twice because the | |
68ad0ae0 HS |
2658 | * SAA7146 audio channel does not always reset properly and |
2659 | * sometimes causes the first few TrimDAC writes to malfunction. | |
2660 | */ | |
31de1948 | 2661 | s626_load_trim_dacs(dev); |
a7aa94ce CS |
2662 | ret = s626_load_trim_dacs(dev); |
2663 | if (ret) | |
2664 | return ret; | |
11e865c1 | 2665 | |
54a2a02e HS |
2666 | /* |
2667 | * Manually init all gate array hardware in case this is a soft | |
68ad0ae0 HS |
2668 | * reset (we have no way of determining whether this is a warm |
2669 | * or cold start). This is necessary because the gate array will | |
2670 | * reset only in response to a PCI hard reset; there is no soft | |
54a2a02e HS |
2671 | * reset function. |
2672 | */ | |
11e865c1 | 2673 | |
54a2a02e HS |
2674 | /* |
2675 | * Init all DAC outputs to 0V and init all DAC setpoint and | |
68ad0ae0 HS |
2676 | * polarity images. |
2677 | */ | |
a7aa94ce CS |
2678 | for (chan = 0; chan < S626_DAC_CHANNELS; chan++) { |
2679 | ret = s626_set_dac(dev, chan, 0); | |
2680 | if (ret) | |
2681 | return ret; | |
2682 | } | |
11e865c1 | 2683 | |
54a2a02e | 2684 | /* Init counters */ |
31de1948 | 2685 | s626_counters_init(dev); |
11e865c1 | 2686 | |
54a2a02e HS |
2687 | /* |
2688 | * Without modifying the state of the Battery Backup enab, disable | |
68ad0ae0 HS |
2689 | * the watchdog timer, set DIO channels 0-5 to operate in the |
2690 | * standard DIO (vs. counter overflow) mode, disable the battery | |
2691 | * charger, and reset the watchdog interval selector to zero. | |
2692 | */ | |
d8515652 IA |
2693 | s626_write_misc2(dev, (s626_debi_read(dev, S626_LP_RDMISC2) & |
2694 | S626_MISC2_BATT_ENABLE)); | |
11e865c1 | 2695 | |
54a2a02e | 2696 | /* Initialize the digital I/O subsystem */ |
68ad0ae0 | 2697 | s626_dio_init(dev); |
a7aa94ce CS |
2698 | |
2699 | return 0; | |
80ec9510 HS |
2700 | } |
2701 | ||
a690b7e5 | 2702 | static int s626_auto_attach(struct comedi_device *dev, |
6c7d2c8b | 2703 | unsigned long context_unused) |
80ec9510 | 2704 | { |
750af5e5 | 2705 | struct pci_dev *pcidev = comedi_to_pci_dev(dev); |
7f2f7e05 | 2706 | struct s626_private *devpriv; |
80ec9510 HS |
2707 | struct comedi_subdevice *s; |
2708 | int ret; | |
2709 | ||
0bdab509 | 2710 | devpriv = comedi_alloc_devpriv(dev, sizeof(*devpriv)); |
c34fa261 HS |
2711 | if (!devpriv) |
2712 | return -ENOMEM; | |
80ec9510 | 2713 | |
818f569f | 2714 | ret = comedi_pci_enable(dev); |
80ec9510 HS |
2715 | if (ret) |
2716 | return ret; | |
80ec9510 | 2717 | |
de9cd5ca HS |
2718 | dev->mmio = pci_ioremap_bar(pcidev, 0); |
2719 | if (!dev->mmio) | |
80ec9510 HS |
2720 | return -ENOMEM; |
2721 | ||
2722 | /* disable master interrupt */ | |
de9cd5ca | 2723 | writel(0, dev->mmio + S626_P_IER); |
80ec9510 HS |
2724 | |
2725 | /* soft reset */ | |
de9cd5ca | 2726 | writel(S626_MC1_SOFT_RESET, dev->mmio + S626_P_MC1); |
80ec9510 HS |
2727 | |
2728 | /* DMA FIXME DMA// */ | |
2729 | ||
2730 | ret = s626_allocate_dma_buffers(dev); | |
2731 | if (ret) | |
2732 | return ret; | |
2733 | ||
2734 | if (pcidev->irq) { | |
2735 | ret = request_irq(pcidev->irq, s626_irq_handler, IRQF_SHARED, | |
2736 | dev->board_name, dev); | |
2737 | ||
2738 | if (ret == 0) | |
2739 | dev->irq = pcidev->irq; | |
2740 | } | |
2741 | ||
2742 | ret = comedi_alloc_subdevices(dev, 6); | |
2743 | if (ret) | |
2744 | return ret; | |
2745 | ||
f0717f5d | 2746 | s = &dev->subdevices[0]; |
80ec9510 | 2747 | /* analog input subdevice */ |
ca2f1091 | 2748 | s->type = COMEDI_SUBD_AI; |
f95321f3 | 2749 | s->subdev_flags = SDF_READABLE | SDF_DIFF; |
ca2f1091 HS |
2750 | s->n_chan = S626_ADC_CHANNELS; |
2751 | s->maxdata = 0x3fff; | |
2752 | s->range_table = &s626_range_table; | |
2753 | s->len_chanlist = S626_ADC_CHANNELS; | |
ca2f1091 | 2754 | s->insn_read = s626_ai_insn_read; |
2281befd HS |
2755 | if (dev->irq) { |
2756 | dev->read_subdev = s; | |
f95321f3 | 2757 | s->subdev_flags |= SDF_CMD_READ; |
2281befd HS |
2758 | s->do_cmd = s626_ai_cmd; |
2759 | s->do_cmdtest = s626_ai_cmdtest; | |
2760 | s->cancel = s626_ai_cancel; | |
2761 | } | |
80ec9510 | 2762 | |
f0717f5d | 2763 | s = &dev->subdevices[1]; |
80ec9510 | 2764 | /* analog output subdevice */ |
ca2f1091 HS |
2765 | s->type = COMEDI_SUBD_AO; |
2766 | s->subdev_flags = SDF_WRITABLE | SDF_READABLE; | |
2767 | s->n_chan = S626_DAC_CHANNELS; | |
2768 | s->maxdata = 0x3fff; | |
2769 | s->range_table = &range_bipolar10; | |
18259ffc | 2770 | s->insn_write = s626_ao_insn_write; |
18259ffc HS |
2771 | |
2772 | ret = comedi_alloc_subdev_readback(s); | |
2773 | if (ret) | |
2774 | return ret; | |
80ec9510 | 2775 | |
f0717f5d | 2776 | s = &dev->subdevices[2]; |
80ec9510 | 2777 | /* digital I/O subdevice */ |
ca2f1091 HS |
2778 | s->type = COMEDI_SUBD_DIO; |
2779 | s->subdev_flags = SDF_WRITABLE | SDF_READABLE; | |
2780 | s->n_chan = 16; | |
2781 | s->maxdata = 1; | |
2782 | s->io_bits = 0xffff; | |
2783 | s->private = (void *)0; /* DIO group 0 */ | |
2784 | s->range_table = &range_digital; | |
2785 | s->insn_config = s626_dio_insn_config; | |
2786 | s->insn_bits = s626_dio_insn_bits; | |
80ec9510 | 2787 | |
f0717f5d | 2788 | s = &dev->subdevices[3]; |
80ec9510 | 2789 | /* digital I/O subdevice */ |
ca2f1091 HS |
2790 | s->type = COMEDI_SUBD_DIO; |
2791 | s->subdev_flags = SDF_WRITABLE | SDF_READABLE; | |
2792 | s->n_chan = 16; | |
2793 | s->maxdata = 1; | |
2794 | s->io_bits = 0xffff; | |
2795 | s->private = (void *)1; /* DIO group 1 */ | |
2796 | s->range_table = &range_digital; | |
2797 | s->insn_config = s626_dio_insn_config; | |
2798 | s->insn_bits = s626_dio_insn_bits; | |
80ec9510 | 2799 | |
f0717f5d | 2800 | s = &dev->subdevices[4]; |
80ec9510 | 2801 | /* digital I/O subdevice */ |
ca2f1091 HS |
2802 | s->type = COMEDI_SUBD_DIO; |
2803 | s->subdev_flags = SDF_WRITABLE | SDF_READABLE; | |
2804 | s->n_chan = 16; | |
2805 | s->maxdata = 1; | |
2806 | s->io_bits = 0xffff; | |
2807 | s->private = (void *)2; /* DIO group 2 */ | |
2808 | s->range_table = &range_digital; | |
8ee52611 | 2809 | s->insn_config = s626_dio_insn_config; |
ca2f1091 | 2810 | s->insn_bits = s626_dio_insn_bits; |
80ec9510 | 2811 | |
f0717f5d | 2812 | s = &dev->subdevices[5]; |
80ec9510 | 2813 | /* encoder (counter) subdevice */ |
ca2f1091 HS |
2814 | s->type = COMEDI_SUBD_COUNTER; |
2815 | s->subdev_flags = SDF_WRITABLE | SDF_READABLE | SDF_LSAMPL; | |
2816 | s->n_chan = S626_ENCODER_CHANNELS; | |
2817 | s->maxdata = 0xffffff; | |
ca2f1091 HS |
2818 | s->range_table = &range_unknown; |
2819 | s->insn_config = s626_enc_insn_config; | |
2820 | s->insn_read = s626_enc_insn_read; | |
2821 | s->insn_write = s626_enc_insn_write; | |
80ec9510 | 2822 | |
71b9f42e | 2823 | return s626_initialize(dev); |
11e865c1 GP |
2824 | } |
2825 | ||
020c44f3 | 2826 | static void s626_detach(struct comedi_device *dev) |
11e865c1 | 2827 | { |
7f2f7e05 | 2828 | struct s626_private *devpriv = dev->private; |
f574af6d | 2829 | |
020c44f3 HS |
2830 | if (devpriv) { |
2831 | /* stop ai_command */ | |
2832 | devpriv->ai_cmd_running = 0; | |
11e865c1 | 2833 | |
de9cd5ca | 2834 | if (dev->mmio) { |
020c44f3 | 2835 | /* interrupt mask */ |
25f8fd5e | 2836 | /* Disable master interrupt */ |
de9cd5ca | 2837 | writel(0, dev->mmio + S626_P_IER); |
25f8fd5e | 2838 | /* Clear board's IRQ status flag */ |
d8515652 | 2839 | writel(S626_IRQ_GPIO3 | S626_IRQ_RPS1, |
de9cd5ca | 2840 | dev->mmio + S626_P_ISR); |
11e865c1 | 2841 | |
8ee52611 | 2842 | /* Disable the watchdog timer and battery charger. */ |
31de1948 | 2843 | s626_write_misc2(dev, 0); |
11e865c1 | 2844 | |
25f8fd5e | 2845 | /* Close all interfaces on 7146 device */ |
de9cd5ca HS |
2846 | writel(S626_MC1_SHUTDOWN, dev->mmio + S626_P_MC1); |
2847 | writel(S626_ACON1_BASE, dev->mmio + S626_P_ACON1); | |
020c44f3 | 2848 | } |
f574af6d | 2849 | } |
8075bfb6 | 2850 | comedi_pci_detach(dev); |
3757e795 | 2851 | s626_free_dma_buffers(dev); |
11e865c1 | 2852 | } |
7122b76d | 2853 | |
75e6301b | 2854 | static struct comedi_driver s626_driver = { |
7122b76d HS |
2855 | .driver_name = "s626", |
2856 | .module = THIS_MODULE, | |
750af5e5 | 2857 | .auto_attach = s626_auto_attach, |
7122b76d HS |
2858 | .detach = s626_detach, |
2859 | }; | |
2860 | ||
a690b7e5 | 2861 | static int s626_pci_probe(struct pci_dev *dev, |
b8f4ac23 | 2862 | const struct pci_device_id *id) |
7122b76d | 2863 | { |
b8f4ac23 | 2864 | return comedi_pci_auto_config(dev, &s626_driver, id->driver_data); |
7122b76d HS |
2865 | } |
2866 | ||
7122b76d HS |
2867 | /* |
2868 | * For devices with vendor:device id == 0x1131:0x7146 you must specify | |
2869 | * also subvendor:subdevice ids, because otherwise it will conflict with | |
2870 | * Philips SAA7146 media/dvb based cards. | |
2871 | */ | |
41e043fc | 2872 | static const struct pci_device_id s626_pci_table[] = { |
498c5070 IA |
2873 | { PCI_DEVICE_SUB(PCI_VENDOR_ID_PHILIPS, PCI_DEVICE_ID_PHILIPS_SAA7146, |
2874 | 0x6000, 0x0272) }, | |
7122b76d HS |
2875 | { 0 } |
2876 | }; | |
2877 | MODULE_DEVICE_TABLE(pci, s626_pci_table); | |
2878 | ||
75e6301b HS |
2879 | static struct pci_driver s626_pci_driver = { |
2880 | .name = "s626", | |
7122b76d | 2881 | .id_table = s626_pci_table, |
75e6301b | 2882 | .probe = s626_pci_probe, |
9901a4d7 | 2883 | .remove = comedi_pci_auto_unconfig, |
7122b76d | 2884 | }; |
75e6301b | 2885 | module_comedi_pci_driver(s626_driver, s626_pci_driver); |
7122b76d HS |
2886 | |
2887 | MODULE_AUTHOR("Gianluca Palli <gpalli@deis.unibo.it>"); | |
2888 | MODULE_DESCRIPTION("Sensoray 626 Comedi driver module"); | |
2889 | MODULE_LICENSE("GPL"); |