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11e865c1 | 1 | /* |
eb4700ed IA |
2 | * comedi/drivers/s626.h |
3 | * Sensoray s626 Comedi driver, header file | |
4 | * | |
5 | * COMEDI - Linux Control and Measurement Device Interface | |
6 | * Copyright (C) 2000 David A. Schleef <ds@schleef.org> | |
7 | * | |
8 | * Based on Sensoray Model 626 Linux driver Version 0.2 | |
9 | * Copyright (C) 2002-2004 Sensoray Co., Inc. | |
10 | * | |
11 | * This program is free software; you can redistribute it and/or modify | |
12 | * it under the terms of the GNU General Public License as published by | |
13 | * the Free Software Foundation; either version 2 of the License, or | |
14 | * (at your option) any later version. | |
15 | * | |
16 | * This program is distributed in the hope that it will be useful, | |
17 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
18 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
19 | * GNU General Public License for more details. | |
20 | */ | |
21 | ||
22 | #ifndef S626_H_INCLUDED | |
23 | #define S626_H_INCLUDED | |
11e865c1 | 24 | |
d8515652 | 25 | #define S626_DMABUF_SIZE 4096 /* 4k pages */ |
11e865c1 GP |
26 | |
27 | #define S626_ADC_CHANNELS 16 | |
28 | #define S626_DAC_CHANNELS 4 | |
29 | #define S626_ENCODER_CHANNELS 6 | |
30 | #define S626_DIO_CHANNELS 48 | |
eb4700ed | 31 | #define S626_DIO_BANKS 3 /* Number of DIO groups. */ |
805c5f93 RKM |
32 | #define S626_DIO_EXTCHANS 40 /* |
33 | * Number of extended-capability | |
34 | * DIO channels. | |
35 | */ | |
11e865c1 | 36 | |
d8515652 | 37 | #define S626_NUM_TRIMDACS 12 /* Number of valid TrimDAC channels. */ |
11e865c1 | 38 | |
eb4700ed | 39 | /* PCI bus interface types. */ |
d8515652 IA |
40 | #define S626_INTEL 1 /* Intel bus type. */ |
41 | #define S626_MOTOROLA 2 /* Motorola bus type. */ | |
11e865c1 | 42 | |
d8515652 | 43 | #define S626_PLATFORM S626_INTEL /* *** SELECT PLATFORM TYPE *** */ |
11e865c1 | 44 | |
d8515652 IA |
45 | #define S626_RANGE_5V 0x10 /* +/-5V range */ |
46 | #define S626_RANGE_10V 0x00 /* +/-10V range */ | |
11e865c1 | 47 | |
d8515652 IA |
48 | #define S626_EOPL 0x80 /* End of ADC poll list marker. */ |
49 | #define S626_GSEL_BIPOLAR5V 0x00F0 /* S626_LP_GSEL setting 5V bipolar. */ | |
50 | #define S626_GSEL_BIPOLAR10V 0x00A0 /* S626_LP_GSEL setting 10V bipolar. */ | |
11e865c1 | 51 | |
eb4700ed | 52 | /* Error codes that must be visible to this base class. */ |
805c5f93 RKM |
53 | #define S626_ERR_ILLEGAL_PARM 0x00010000 /* |
54 | * Illegal function parameter | |
55 | * value was specified. | |
56 | */ | |
d8515652 | 57 | #define S626_ERR_I2C 0x00020000 /* I2C error. */ |
805c5f93 RKM |
58 | #define S626_ERR_COUNTERSETUP 0x00200000 /* |
59 | * Illegal setup specified for | |
60 | * counter channel. | |
61 | */ | |
d8515652 | 62 | #define S626_ERR_DEBI_TIMEOUT 0x00400000 /* DEBI transfer timed out. */ |
11e865c1 | 63 | |
eb4700ed IA |
64 | /* |
65 | * Organization (physical order) and size (in DWORDs) of logical DMA buffers | |
66 | * contained by ANA_DMABUF. | |
67 | */ | |
805c5f93 RKM |
68 | #define S626_ADC_DMABUF_DWORDS 40 /* |
69 | * ADC DMA buffer must hold 16 samples, | |
70 | * plus pre/post garbage samples. | |
71 | */ | |
72 | #define S626_DAC_WDMABUF_DWORDS 1 /* | |
73 | * DAC output DMA buffer holds a single | |
74 | * sample. | |
75 | */ | |
11e865c1 | 76 | |
eb4700ed | 77 | /* All remaining space in 4KB DMA buffer is available for the RPS1 program. */ |
11e865c1 | 78 | |
eb4700ed | 79 | /* Address offsets, in DWORDS, from base of DMA buffer. */ |
d8515652 | 80 | #define S626_DAC_WDMABUF_OS S626_ADC_DMABUF_DWORDS |
11e865c1 | 81 | |
1c454fab | 82 | /* Interrupt enable bit in ISR and IER. */ |
d8515652 IA |
83 | #define S626_IRQ_GPIO3 0x00000040 /* IRQ enable for GPIO3. */ |
84 | #define S626_IRQ_RPS1 0x10000000 | |
85 | #define S626_ISR_AFOU 0x00000800 | |
b6c77757 BP |
86 | /* Audio fifo under/overflow detected. */ |
87 | ||
d8515652 IA |
88 | #define S626_IRQ_COINT1A 0x0400 /* counter 1A overflow interrupt mask */ |
89 | #define S626_IRQ_COINT1B 0x0800 /* counter 1B overflow interrupt mask */ | |
90 | #define S626_IRQ_COINT2A 0x1000 /* counter 2A overflow interrupt mask */ | |
91 | #define S626_IRQ_COINT2B 0x2000 /* counter 2B overflow interrupt mask */ | |
92 | #define S626_IRQ_COINT3A 0x4000 /* counter 3A overflow interrupt mask */ | |
93 | #define S626_IRQ_COINT3B 0x8000 /* counter 3B overflow interrupt mask */ | |
eb4700ed IA |
94 | |
95 | /* RPS command codes. */ | |
d8515652 IA |
96 | #define S626_RPS_CLRSIGNAL 0x00000000 /* CLEAR SIGNAL */ |
97 | #define S626_RPS_SETSIGNAL 0x10000000 /* SET SIGNAL */ | |
98 | #define S626_RPS_NOP 0x00000000 /* NOP */ | |
99 | #define S626_RPS_PAUSE 0x20000000 /* PAUSE */ | |
100 | #define S626_RPS_UPLOAD 0x40000000 /* UPLOAD */ | |
101 | #define S626_RPS_JUMP 0x80000000 /* JUMP */ | |
102 | #define S626_RPS_LDREG 0x90000100 /* LDREG (1 uint32_t only) */ | |
103 | #define S626_RPS_STREG 0xA0000100 /* STREG (1 uint32_t only) */ | |
104 | #define S626_RPS_STOP 0x50000000 /* STOP */ | |
105 | #define S626_RPS_IRQ 0x60000000 /* IRQ */ | |
106 | ||
107 | #define S626_RPS_LOGICAL_OR 0x08000000 /* Logical OR conditionals. */ | |
805c5f93 RKM |
108 | #define S626_RPS_INVERT 0x04000000 /* |
109 | * Test for negated | |
110 | * semaphores. | |
111 | */ | |
d8515652 | 112 | #define S626_RPS_DEBI 0x00000002 /* DEBI done */ |
eb4700ed | 113 | |
805c5f93 RKM |
114 | #define S626_RPS_SIG0 0x00200000 /* |
115 | * RPS semaphore 0 | |
116 | * (used by ADC). | |
117 | */ | |
118 | #define S626_RPS_SIG1 0x00400000 /* | |
119 | * RPS semaphore 1 | |
120 | * (used by DAC). | |
121 | */ | |
122 | #define S626_RPS_SIG2 0x00800000 /* | |
123 | * RPS semaphore 2 | |
124 | * (not used). | |
125 | */ | |
d8515652 IA |
126 | #define S626_RPS_GPIO2 0x00080000 /* RPS GPIO2 */ |
127 | #define S626_RPS_GPIO3 0x00100000 /* RPS GPIO3 */ | |
eb4700ed | 128 | |
805c5f93 RKM |
129 | #define S626_RPS_SIGADC S626_RPS_SIG0 /* |
130 | * Trigger/status for | |
131 | * ADC's RPS program. | |
132 | */ | |
133 | #define S626_RPS_SIGDAC S626_RPS_SIG1 /* | |
134 | * Trigger/status for | |
135 | * DAC's RPS program. | |
136 | */ | |
eb4700ed IA |
137 | |
138 | /* RPS clock parameters. */ | |
805c5f93 RKM |
139 | #define S626_RPSCLK_SCALAR 8 /* |
140 | * This is apparent ratio of | |
141 | * PCI/RPS clks (undocumented!!). | |
142 | */ | |
d8515652 | 143 | #define S626_RPSCLK_PER_US (33 / S626_RPSCLK_SCALAR) |
805c5f93 RKM |
144 | /* |
145 | * Number of RPS clocks in one | |
146 | * microsecond. | |
147 | */ | |
eb4700ed IA |
148 | |
149 | /* Event counter source addresses. */ | |
d8515652 | 150 | #define S626_SBA_RPS_A0 0x27 /* Time of RPS0 busy, in PCI clocks. */ |
eb4700ed IA |
151 | |
152 | /* GPIO constants. */ | |
805c5f93 RKM |
153 | #define S626_GPIO_BASE 0x10004000 /* |
154 | * GPIO 0,2,3 = inputs, | |
155 | * GPIO3 = IRQ; GPIO1 = out. | |
156 | */ | |
d8515652 IA |
157 | #define S626_GPIO1_LO 0x00000000 /* GPIO1 set to LOW. */ |
158 | #define S626_GPIO1_HI 0x00001000 /* GPIO1 set to HIGH. */ | |
eb4700ed IA |
159 | |
160 | /* Primary Status Register (PSR) constants. */ | |
d8515652 IA |
161 | #define S626_PSR_DEBI_E 0x00040000 /* DEBI event flag. */ |
162 | #define S626_PSR_DEBI_S 0x00080000 /* DEBI status flag. */ | |
805c5f93 RKM |
163 | #define S626_PSR_A2_IN 0x00008000 /* |
164 | * Audio output DMA2 protection | |
165 | * address reached. | |
166 | */ | |
167 | #define S626_PSR_AFOU 0x00000800 /* | |
168 | * Audio FIFO under/overflow | |
169 | * detected. | |
170 | */ | |
171 | #define S626_PSR_GPIO2 0x00000020 /* | |
172 | * GPIO2 input pin: 0=AdcBusy, | |
173 | * 1=AdcIdle. | |
174 | */ | |
175 | #define S626_PSR_EC0S 0x00000001 /* | |
176 | * Event counter 0 threshold | |
177 | * reached. | |
178 | */ | |
eb4700ed IA |
179 | |
180 | /* Secondary Status Register (SSR) constants. */ | |
805c5f93 RKM |
181 | #define S626_SSR_AF2_OUT 0x00000200 /* |
182 | * Audio 2 output FIFO | |
183 | * under/overflow detected. | |
184 | */ | |
eb4700ed IA |
185 | |
186 | /* Master Control Register 1 (MC1) constants. */ | |
d8515652 | 187 | #define S626_MC1_SOFT_RESET 0x80000000 /* Invoke 7146 soft reset. */ |
805c5f93 RKM |
188 | #define S626_MC1_SHUTDOWN 0x3FFF0000 /* |
189 | * Shut down all MC1-controlled | |
190 | * enables. | |
191 | */ | |
eb4700ed | 192 | |
d8515652 IA |
193 | #define S626_MC1_ERPS1 0x2000 /* Enab/disable RPS task 1. */ |
194 | #define S626_MC1_ERPS0 0x1000 /* Enab/disable RPS task 0. */ | |
195 | #define S626_MC1_DEBI 0x0800 /* Enab/disable DEBI pins. */ | |
196 | #define S626_MC1_AUDIO 0x0200 /* Enab/disable audio port pins. */ | |
197 | #define S626_MC1_I2C 0x0100 /* Enab/disable I2C interface. */ | |
198 | #define S626_MC1_A2OUT 0x0008 /* Enab/disable transfer on A2 out. */ | |
199 | #define S626_MC1_A2IN 0x0004 /* Enab/disable transfer on A2 in. */ | |
200 | #define S626_MC1_A1IN 0x0001 /* Enab/disable transfer on A1 in. */ | |
eb4700ed IA |
201 | |
202 | /* Master Control Register 2 (MC2) constants. */ | |
d8515652 IA |
203 | #define S626_MC2_UPLD_DEBI 0x0002 /* Upload DEBI. */ |
204 | #define S626_MC2_UPLD_IIC 0x0001 /* Upload I2C. */ | |
205 | #define S626_MC2_RPSSIG2 0x2000 /* RPS signal 2 (not used). */ | |
206 | #define S626_MC2_RPSSIG1 0x1000 /* RPS signal 1 (DAC RPS busy). */ | |
207 | #define S626_MC2_RPSSIG0 0x0800 /* RPS signal 0 (ADC RPS busy). */ | |
eb4700ed | 208 | |
d8515652 IA |
209 | #define S626_MC2_ADC_RPS S626_MC2_RPSSIG0 /* ADC RPS busy. */ |
210 | #define S626_MC2_DAC_RPS S626_MC2_RPSSIG1 /* DAC RPS busy. */ | |
eb4700ed IA |
211 | |
212 | /* PCI BUS (SAA7146) REGISTER ADDRESS OFFSETS */ | |
d8515652 IA |
213 | #define S626_P_PCI_BT_A 0x004C /* Audio DMA burst/threshold control. */ |
214 | #define S626_P_DEBICFG 0x007C /* DEBI configuration. */ | |
215 | #define S626_P_DEBICMD 0x0080 /* DEBI command. */ | |
216 | #define S626_P_DEBIPAGE 0x0084 /* DEBI page. */ | |
217 | #define S626_P_DEBIAD 0x0088 /* DEBI target address. */ | |
218 | #define S626_P_I2CCTRL 0x008C /* I2C control. */ | |
219 | #define S626_P_I2CSTAT 0x0090 /* I2C status. */ | |
805c5f93 RKM |
220 | #define S626_P_BASEA2_IN 0x00AC /* |
221 | * Audio input 2 base physical DMAbuf | |
222 | * address. | |
223 | */ | |
224 | #define S626_P_PROTA2_IN 0x00B0 /* | |
225 | * Audio input 2 physical DMAbuf | |
226 | * protection address. | |
227 | */ | |
d8515652 | 228 | #define S626_P_PAGEA2_IN 0x00B4 /* Audio input 2 paging attributes. */ |
805c5f93 RKM |
229 | #define S626_P_BASEA2_OUT 0x00B8 /* |
230 | * Audio output 2 base physical DMAbuf | |
231 | * address. | |
232 | */ | |
233 | #define S626_P_PROTA2_OUT 0x00BC /* | |
234 | * Audio output 2 physical DMAbuf | |
235 | * protection address. | |
236 | */ | |
d8515652 IA |
237 | #define S626_P_PAGEA2_OUT 0x00C0 /* Audio output 2 paging attributes. */ |
238 | #define S626_P_RPSPAGE0 0x00C4 /* RPS0 page. */ | |
239 | #define S626_P_RPSPAGE1 0x00C8 /* RPS1 page. */ | |
240 | #define S626_P_RPS0_TOUT 0x00D4 /* RPS0 time-out. */ | |
241 | #define S626_P_RPS1_TOUT 0x00D8 /* RPS1 time-out. */ | |
242 | #define S626_P_IER 0x00DC /* Interrupt enable. */ | |
243 | #define S626_P_GPIO 0x00E0 /* General-purpose I/O. */ | |
244 | #define S626_P_EC1SSR 0x00E4 /* Event counter set 1 source select. */ | |
245 | #define S626_P_ECT1R 0x00EC /* Event counter threshold set 1. */ | |
246 | #define S626_P_ACON1 0x00F4 /* Audio control 1. */ | |
247 | #define S626_P_ACON2 0x00F8 /* Audio control 2. */ | |
248 | #define S626_P_MC1 0x00FC /* Master control 1. */ | |
249 | #define S626_P_MC2 0x0100 /* Master control 2. */ | |
250 | #define S626_P_RPSADDR0 0x0104 /* RPS0 instruction pointer. */ | |
251 | #define S626_P_RPSADDR1 0x0108 /* RPS1 instruction pointer. */ | |
252 | #define S626_P_ISR 0x010C /* Interrupt status. */ | |
253 | #define S626_P_PSR 0x0110 /* Primary status. */ | |
254 | #define S626_P_SSR 0x0114 /* Secondary status. */ | |
255 | #define S626_P_EC1R 0x0118 /* Event counter set 1. */ | |
805c5f93 RKM |
256 | #define S626_P_ADP4 0x0138 /* |
257 | * Logical audio DMA pointer of audio | |
258 | * input FIFO A2_IN. | |
259 | */ | |
d8515652 IA |
260 | #define S626_P_FB_BUFFER1 0x0144 /* Audio feedback buffer 1. */ |
261 | #define S626_P_FB_BUFFER2 0x0148 /* Audio feedback buffer 2. */ | |
262 | #define S626_P_TSL1 0x0180 /* Audio time slot list 1. */ | |
263 | #define S626_P_TSL2 0x01C0 /* Audio time slot list 2. */ | |
b6c77757 | 264 | |
eb4700ed IA |
265 | /* LOCAL BUS (GATE ARRAY) REGISTER ADDRESS OFFSETS */ |
266 | /* Analog I/O registers: */ | |
d8515652 IA |
267 | #define S626_LP_DACPOL 0x0082 /* Write DAC polarity. */ |
268 | #define S626_LP_GSEL 0x0084 /* Write ADC gain. */ | |
269 | #define S626_LP_ISEL 0x0086 /* Write ADC channel select. */ | |
100b4edc HS |
270 | |
271 | /* Digital I/O registers */ | |
d8515652 IA |
272 | #define S626_LP_RDDIN(x) (0x0040 + (x) * 0x10) /* R: digital input */ |
273 | #define S626_LP_WRINTSEL(x) (0x0042 + (x) * 0x10) /* W: int enable */ | |
274 | #define S626_LP_WREDGSEL(x) (0x0044 + (x) * 0x10) /* W: edge selection */ | |
275 | #define S626_LP_WRCAPSEL(x) (0x0046 + (x) * 0x10) /* W: capture enable */ | |
276 | #define S626_LP_RDCAPFLG(x) (0x0048 + (x) * 0x10) /* R: edges captured */ | |
277 | #define S626_LP_WRDOUT(x) (0x0048 + (x) * 0x10) /* W: digital output */ | |
278 | #define S626_LP_RDINTSEL(x) (0x004a + (x) * 0x10) /* R: int enable */ | |
279 | #define S626_LP_RDEDGSEL(x) (0x004c + (x) * 0x10) /* R: edge selection */ | |
280 | #define S626_LP_RDCAPSEL(x) (0x004e + (x) * 0x10) /* R: capture enable */ | |
b6c77757 | 281 | |
f114b45a HS |
282 | /* Counter registers (read/write): 0A 1A 2A 0B 1B 2B */ |
283 | #define S626_LP_CRA(x) (0x0000 + (((x) % 3) * 0x4)) | |
284 | #define S626_LP_CRB(x) (0x0002 + (((x) % 3) * 0x4)) | |
eb4700ed | 285 | |
2ffe88f6 HS |
286 | /* Counter PreLoad (write) and Latch (read) Registers: 0A 1A 2A 0B 1B 2B */ |
287 | #define S626_LP_CNTR(x) (0x000c + (((x) < 3) ? 0x0 : 0x4) + \ | |
288 | (((x) % 3) * 0x8)) | |
eb4700ed IA |
289 | |
290 | /* Miscellaneous Registers (read/write): */ | |
d8515652 IA |
291 | #define S626_LP_MISC1 0x0088 /* Read/write Misc1. */ |
292 | #define S626_LP_WRMISC2 0x0090 /* Write Misc2. */ | |
293 | #define S626_LP_RDMISC2 0x0082 /* Read Misc2. */ | |
eb4700ed IA |
294 | |
295 | /* Bit masks for MISC1 register that are the same for reads and writes. */ | |
805c5f93 RKM |
296 | #define S626_MISC1_WENABLE 0x8000 /* |
297 | * enab writes to MISC2 (except Clear | |
298 | * Watchdog bit). | |
299 | */ | |
d8515652 | 300 | #define S626_MISC1_WDISABLE 0x0000 /* Disable writes to MISC2. */ |
805c5f93 RKM |
301 | #define S626_MISC1_EDCAP 0x1000 /* |
302 | * Enable edge capture on DIO chans | |
303 | * specified by S626_LP_WRCAPSELx. | |
304 | */ | |
305 | #define S626_MISC1_NOEDCAP 0x0000 /* | |
306 | * Disable edge capture on specified | |
307 | * DIO chans. | |
308 | */ | |
b6c77757 | 309 | |
eb4700ed | 310 | /* Bit masks for MISC1 register reads. */ |
d8515652 | 311 | #define S626_RDMISC1_WDTIMEOUT 0x4000 /* Watchdog timer timed out. */ |
b6c77757 | 312 | |
eb4700ed | 313 | /* Bit masks for MISC2 register writes. */ |
d8515652 IA |
314 | #define S626_WRMISC2_WDCLEAR 0x8000 /* Reset watchdog timer to zero. */ |
315 | #define S626_WRMISC2_CHARGE_ENABLE 0x4000 /* Enable battery trickle charging. */ | |
b6c77757 | 316 | |
eb4700ed | 317 | /* Bit masks for MISC2 register that are the same for reads and writes. */ |
d8515652 IA |
318 | #define S626_MISC2_BATT_ENABLE 0x0008 /* Backup battery enable. */ |
319 | #define S626_MISC2_WDENABLE 0x0004 /* Watchdog timer enable. */ | |
320 | #define S626_MISC2_WDPERIOD_MASK 0x0003 /* Watchdog interval select mask. */ | |
b6c77757 | 321 | |
eb4700ed | 322 | /* Bit masks for ACON1 register. */ |
d8515652 IA |
323 | #define S626_A2_RUN 0x40000000 /* Run A2 based on TSL2. */ |
324 | #define S626_A1_RUN 0x20000000 /* Run A1 based on TSL1. */ | |
325 | #define S626_A1_SWAP 0x00200000 /* Use big-endian for A1. */ | |
326 | #define S626_A2_SWAP 0x00100000 /* Use big-endian for A2. */ | |
805c5f93 RKM |
327 | #define S626_WS_MODES 0x00019999 /* |
328 | * WS0 = TSL1 trigger input, | |
329 | * WS1-WS4 = CS* outputs. | |
330 | */ | |
331 | ||
1c454fab | 332 | #if (S626_PLATFORM == S626_INTEL) /* |
805c5f93 RKM |
333 | * Base ACON1 config: always run |
334 | * A1 based on TSL1. | |
335 | */ | |
d8515652 IA |
336 | #define S626_ACON1_BASE (S626_WS_MODES | S626_A1_RUN) |
337 | #elif S626_PLATFORM == S626_MOTOROLA | |
338 | #define S626_ACON1_BASE \ | |
339 | (S626_WS_MODES | S626_A1_RUN | S626_A1_SWAP | S626_A2_SWAP) | |
11e865c1 GP |
340 | #endif |
341 | ||
805c5f93 RKM |
342 | #define S626_ACON1_ADCSTART S626_ACON1_BASE /* |
343 | * Start ADC: run A1 | |
344 | * based on TSL1. | |
345 | */ | |
d8515652 | 346 | #define S626_ACON1_DACSTART (S626_ACON1_BASE | S626_A2_RUN) |
b6c77757 | 347 | /* Start transmit to DAC: run A2 based on TSL2. */ |
d8515652 | 348 | #define S626_ACON1_DACSTOP S626_ACON1_BASE /* Halt A2. */ |
eb4700ed IA |
349 | |
350 | /* Bit masks for ACON2 register. */ | |
d8515652 | 351 | #define S626_A1_CLKSRC_BCLK1 0x00000000 /* A1 bit rate = BCLK1 (ADC). */ |
805c5f93 RKM |
352 | #define S626_A2_CLKSRC_X1 0x00800000 /* |
353 | * A2 bit rate = ACLK/1 | |
354 | * (DACs). | |
355 | */ | |
356 | #define S626_A2_CLKSRC_X2 0x00C00000 /* | |
357 | * A2 bit rate = ACLK/2 | |
358 | * (DACs). | |
359 | */ | |
360 | #define S626_A2_CLKSRC_X4 0x01400000 /* | |
361 | * A2 bit rate = ACLK/4 | |
362 | * (DACs). | |
363 | */ | |
d8515652 IA |
364 | #define S626_INVERT_BCLK2 0x00100000 /* Invert BCLK2 (DACs). */ |
365 | #define S626_BCLK2_OE 0x00040000 /* Enable BCLK2 (DACs). */ | |
805c5f93 RKM |
366 | #define S626_ACON2_XORMASK 0x000C0000 /* |
367 | * XOR mask for ACON2 | |
368 | * active-low bits. | |
369 | */ | |
eb4700ed | 370 | |
d8515652 IA |
371 | #define S626_ACON2_INIT (S626_ACON2_XORMASK ^ \ |
372 | (S626_A1_CLKSRC_BCLK1 | S626_A2_CLKSRC_X2 | \ | |
373 | S626_INVERT_BCLK2 | S626_BCLK2_OE)) | |
eb4700ed IA |
374 | |
375 | /* Bit masks for timeslot records. */ | |
d8515652 IA |
376 | #define S626_WS1 0x40000000 /* WS output to assert. */ |
377 | #define S626_WS2 0x20000000 | |
378 | #define S626_WS3 0x10000000 | |
379 | #define S626_WS4 0x08000000 | |
380 | #define S626_RSD1 0x01000000 /* Shift A1 data in on SD1. */ | |
805c5f93 RKM |
381 | #define S626_SDW_A1 0x00800000 /* |
382 | * Store rcv'd char at next char | |
383 | * slot of DWORD1 buffer. | |
384 | */ | |
385 | #define S626_SIB_A1 0x00400000 /* | |
386 | * Store rcv'd char at next | |
387 | * char slot of FB1 buffer. | |
388 | */ | |
389 | #define S626_SF_A1 0x00200000 /* | |
390 | * Write unsigned long | |
391 | * buffer to input FIFO. | |
392 | */ | |
b6c77757 BP |
393 | |
394 | /* Select parallel-to-serial converter's data source: */ | |
d8515652 IA |
395 | #define S626_XFIFO_0 0x00000000 /* Data fifo byte 0. */ |
396 | #define S626_XFIFO_1 0x00000010 /* Data fifo byte 1. */ | |
397 | #define S626_XFIFO_2 0x00000020 /* Data fifo byte 2. */ | |
398 | #define S626_XFIFO_3 0x00000030 /* Data fifo byte 3. */ | |
399 | #define S626_XFB0 0x00000040 /* FB_BUFFER byte 0. */ | |
400 | #define S626_XFB1 0x00000050 /* FB_BUFFER byte 1. */ | |
401 | #define S626_XFB2 0x00000060 /* FB_BUFFER byte 2. */ | |
402 | #define S626_XFB3 0x00000070 /* FB_BUFFER byte 3. */ | |
805c5f93 RKM |
403 | #define S626_SIB_A2 0x00000200 /* |
404 | * Store next dword from A2's | |
eb4700ed | 405 | * input shifter to FB2 |
805c5f93 RKM |
406 | * buffer. |
407 | */ | |
408 | #define S626_SF_A2 0x00000100 /* | |
409 | * Store next dword from A2's | |
b6c77757 | 410 | * input shifter to its input |
805c5f93 RKM |
411 | * fifo. |
412 | */ | |
413 | #define S626_LF_A2 0x00000080 /* | |
414 | * Load next dword from A2's | |
b6c77757 | 415 | * output fifo into its |
805c5f93 RKM |
416 | * output dword buffer. |
417 | */ | |
d8515652 IA |
418 | #define S626_XSD2 0x00000008 /* Shift data out on SD2. */ |
419 | #define S626_RSD3 0x00001800 /* Shift data in on SD3. */ | |
420 | #define S626_RSD2 0x00001000 /* Shift data in on SD2. */ | |
805c5f93 RKM |
421 | #define S626_LOW_A2 0x00000002 /* |
422 | * Drive last SD low for 7 clks, | |
423 | * then tri-state. | |
424 | */ | |
d8515652 | 425 | #define S626_EOS 0x00000001 /* End of superframe. */ |
eb4700ed IA |
426 | |
427 | /* I2C configuration constants. */ | |
805c5f93 RKM |
428 | #define S626_I2C_CLKSEL 0x0400 /* |
429 | * I2C bit rate = | |
430 | * PCIclk/480 = 68.75 KHz. | |
431 | */ | |
432 | #define S626_I2C_BITRATE 68.75 /* | |
433 | * I2C bus data bit rate | |
d8515652 | 434 | * (determined by |
805c5f93 RKM |
435 | * S626_I2C_CLKSEL) in KHz. |
436 | */ | |
437 | #define S626_I2C_WRTIME 15.0 /* | |
438 | * Worst case time, in msec, | |
eb4700ed | 439 | * for EEPROM internal write |
805c5f93 RKM |
440 | * op. |
441 | */ | |
eb4700ed IA |
442 | |
443 | /* I2C manifest constants. */ | |
444 | ||
445 | /* Max retries to wait for EEPROM write. */ | |
d8515652 IA |
446 | #define S626_I2C_RETRIES (S626_I2C_WRTIME * S626_I2C_BITRATE / 9.0) |
447 | #define S626_I2C_ERR 0x0002 /* I2C control/status flag ERROR. */ | |
448 | #define S626_I2C_BUSY 0x0001 /* I2C control/status flag BUSY. */ | |
449 | #define S626_I2C_ABORT 0x0080 /* I2C status flag ABORT. */ | |
450 | #define S626_I2C_ATTRSTART 0x3 /* I2C attribute START. */ | |
451 | #define S626_I2C_ATTRCONT 0x2 /* I2C attribute CONT. */ | |
452 | #define S626_I2C_ATTRSTOP 0x1 /* I2C attribute STOP. */ | |
453 | #define S626_I2C_ATTRNOP 0x0 /* I2C attribute NOP. */ | |
eb4700ed | 454 | |
eb4700ed | 455 | /* Code macros used for constructing I2C command bytes. */ |
d8515652 IA |
456 | #define S626_I2C_B2(ATTR, VAL) (((ATTR) << 6) | ((VAL) << 24)) |
457 | #define S626_I2C_B1(ATTR, VAL) (((ATTR) << 4) | ((VAL) << 16)) | |
458 | #define S626_I2C_B0(ATTR, VAL) (((ATTR) << 2) | ((VAL) << 8)) | |
11e865c1 | 459 | |
eb4700ed | 460 | /* DEBI command constants. */ |
805c5f93 RKM |
461 | #define S626_DEBI_CMD_SIZE16 (2 << 17) /* |
462 | * Transfer size is always | |
463 | * 2 bytes. | |
464 | */ | |
d8515652 IA |
465 | #define S626_DEBI_CMD_READ 0x00010000 /* Read operation. */ |
466 | #define S626_DEBI_CMD_WRITE 0x00000000 /* Write operation. */ | |
eb4700ed IA |
467 | |
468 | /* Read immediate 2 bytes. */ | |
d8515652 | 469 | #define S626_DEBI_CMD_RDWORD (S626_DEBI_CMD_READ | S626_DEBI_CMD_SIZE16) |
eb4700ed IA |
470 | |
471 | /* Write immediate 2 bytes. */ | |
d8515652 | 472 | #define S626_DEBI_CMD_WRWORD (S626_DEBI_CMD_WRITE | S626_DEBI_CMD_SIZE16) |
11e865c1 | 473 | |
eb4700ed | 474 | /* DEBI configuration constants. */ |
805c5f93 RKM |
475 | #define S626_DEBI_CFG_XIRQ_EN 0x80000000 /* |
476 | * Enable external interrupt | |
477 | * on GPIO3. | |
478 | */ | |
d8515652 | 479 | #define S626_DEBI_CFG_XRESUME 0x40000000 /* Resume block */ |
805c5f93 RKM |
480 | /* |
481 | * Transfer when XIRQ | |
482 | * deasserted. | |
483 | */ | |
d8515652 IA |
484 | #define S626_DEBI_CFG_TOQ 0x03C00000 /* Timeout (15 PCI cycles). */ |
485 | #define S626_DEBI_CFG_FAST 0x10000000 /* Fast mode enable. */ | |
eb4700ed IA |
486 | |
487 | /* 4-bit field that specifies DEBI timeout value in PCI clock cycles: */ | |
805c5f93 RKM |
488 | #define S626_DEBI_CFG_TOUT_BIT 22 /* |
489 | * Finish DEBI cycle after this many | |
490 | * clocks. | |
491 | */ | |
eb4700ed IA |
492 | |
493 | /* 2-bit field that specifies Endian byte lane steering: */ | |
805c5f93 RKM |
494 | #define S626_DEBI_CFG_SWAP_NONE 0x00000000 /* |
495 | * Straight - don't swap any | |
496 | * bytes (Intel). | |
497 | */ | |
d8515652 IA |
498 | #define S626_DEBI_CFG_SWAP_2 0x00100000 /* 2-byte swap (Motorola). */ |
499 | #define S626_DEBI_CFG_SWAP_4 0x00200000 /* 4-byte swap. */ | |
805c5f93 RKM |
500 | #define S626_DEBI_CFG_SLAVE16 0x00080000 /* |
501 | * Slave is able to serve | |
502 | * 16-bit cycles. | |
503 | */ | |
504 | #define S626_DEBI_CFG_INC 0x00040000 /* | |
505 | * Enable address increment | |
506 | * for block transfers. | |
507 | */ | |
d8515652 IA |
508 | #define S626_DEBI_CFG_INTEL 0x00020000 /* Intel style local bus. */ |
509 | #define S626_DEBI_CFG_TIMEROFF 0x00010000 /* Disable timer. */ | |
11e865c1 | 510 | |
d8515652 | 511 | #if S626_PLATFORM == S626_INTEL |
11e865c1 | 512 | |
805c5f93 RKM |
513 | #define S626_DEBI_TOUT 7 /* |
514 | * Wait 7 PCI clocks (212 ns) before | |
515 | * polling RDY. | |
516 | */ | |
11e865c1 | 517 | |
eb4700ed | 518 | /* Intel byte lane steering (pass through all byte lanes). */ |
d8515652 | 519 | #define S626_DEBI_SWAP S626_DEBI_CFG_SWAP_NONE |
11e865c1 | 520 | |
d8515652 | 521 | #elif S626_PLATFORM == S626_MOTOROLA |
11e865c1 | 522 | |
805c5f93 RKM |
523 | #define S626_DEBI_TOUT 15 /* |
524 | * Wait 15 PCI clocks (454 ns) maximum | |
525 | * before timing out. | |
526 | */ | |
eb4700ed IA |
527 | |
528 | /* Motorola byte lane steering. */ | |
d8515652 | 529 | #define S626_DEBI_SWAP S626_DEBI_CFG_SWAP_2 |
11e865c1 GP |
530 | |
531 | #endif | |
532 | ||
eb4700ed | 533 | /* DEBI page table constants. */ |
d8515652 | 534 | #define S626_DEBI_PAGE_DISABLE 0x00000000 /* Paging disable. */ |
eb4700ed IA |
535 | |
536 | /* ******* EXTRA FROM OTHER SENSORAY * .h ******* */ | |
537 | ||
538 | /* LoadSrc values: */ | |
d8515652 | 539 | #define S626_LOADSRC_INDX 0 /* Preload core in response to Index. */ |
805c5f93 RKM |
540 | #define S626_LOADSRC_OVER 1 /* |
541 | * Preload core in response to | |
542 | * Overflow. | |
543 | */ | |
544 | #define S626_LOADSRCB_OVERA 2 /* | |
545 | * Preload B core in response to | |
546 | * A Overflow. | |
547 | */ | |
d8515652 | 548 | #define S626_LOADSRC_NONE 3 /* Never preload core. */ |
eb4700ed IA |
549 | |
550 | /* IntSrc values: */ | |
d8515652 IA |
551 | #define S626_INTSRC_NONE 0 /* Interrupts disabled. */ |
552 | #define S626_INTSRC_OVER 1 /* Interrupt on Overflow. */ | |
553 | #define S626_INTSRC_INDX 2 /* Interrupt on Index. */ | |
554 | #define S626_INTSRC_BOTH 3 /* Interrupt on Index or Overflow. */ | |
eb4700ed IA |
555 | |
556 | /* LatchSrc values: */ | |
d8515652 IA |
557 | #define S626_LATCHSRC_AB_READ 0 /* Latch on read. */ |
558 | #define S626_LATCHSRC_A_INDXA 1 /* Latch A on A Index. */ | |
559 | #define S626_LATCHSRC_B_INDXB 2 /* Latch B on B Index. */ | |
560 | #define S626_LATCHSRC_B_OVERA 3 /* Latch B on A Overflow. */ | |
eb4700ed IA |
561 | |
562 | /* IndxSrc values: */ | |
2cea19fa IA |
563 | #define S626_INDXSRC_ENCODER 0 /* Encoder. */ |
564 | #define S626_INDXSRC_DIGIN 1 /* Digital inputs. */ | |
565 | #define S626_INDXSRC_SOFT 2 /* S/w controlled by IndxPol bit. */ | |
566 | #define S626_INDXSRC_DISABLED 3 /* Index disabled. */ | |
eb4700ed IA |
567 | |
568 | /* IndxPol values: */ | |
d8515652 IA |
569 | #define S626_INDXPOL_POS 0 /* Index input is active high. */ |
570 | #define S626_INDXPOL_NEG 1 /* Index input is active low. */ | |
eb4700ed | 571 | |
622ec01a IA |
572 | /* Logical encoder mode values: */ |
573 | #define S626_ENCMODE_COUNTER 0 /* Counter mode. */ | |
574 | #define S626_ENCMODE_TIMER 2 /* Timer mode. */ | |
575 | #define S626_ENCMODE_EXTENDER 3 /* Extender mode. */ | |
576 | ||
577 | /* Physical CntSrc values (for Counter A source and Counter B source): */ | |
578 | #define S626_CNTSRC_ENCODER 0 /* Encoder */ | |
579 | #define S626_CNTSRC_DIGIN 1 /* Digital inputs */ | |
580 | #define S626_CNTSRC_SYSCLK 2 /* System clock up */ | |
581 | #define S626_CNTSRC_SYSCLK_DOWN 3 /* System clock down */ | |
eb4700ed IA |
582 | |
583 | /* ClkPol values: */ | |
805c5f93 RKM |
584 | #define S626_CLKPOL_POS 0 /* |
585 | * Counter/Extender clock is | |
586 | * active high. | |
587 | */ | |
588 | #define S626_CLKPOL_NEG 1 /* | |
589 | * Counter/Extender clock is | |
590 | * active low. | |
591 | */ | |
d8515652 IA |
592 | #define S626_CNTDIR_UP 0 /* Timer counts up. */ |
593 | #define S626_CNTDIR_DOWN 1 /* Timer counts down. */ | |
eb4700ed IA |
594 | |
595 | /* ClkEnab values: */ | |
d8515652 IA |
596 | #define S626_CLKENAB_ALWAYS 0 /* Clock always enabled. */ |
597 | #define S626_CLKENAB_INDEX 1 /* Clock is enabled by index. */ | |
eb4700ed IA |
598 | |
599 | /* ClkMult values: */ | |
d8515652 IA |
600 | #define S626_CLKMULT_4X 0 /* 4x clock multiplier. */ |
601 | #define S626_CLKMULT_2X 1 /* 2x clock multiplier. */ | |
602 | #define S626_CLKMULT_1X 2 /* 1x clock multiplier. */ | |
7a1046e5 | 603 | #define S626_CLKMULT_SPECIAL 3 /* Special clock multiplier value. */ |
eb4700ed IA |
604 | |
605 | /* Sanity-check limits for parameters. */ | |
606 | ||
805c5f93 RKM |
607 | #define S626_NUM_COUNTERS 6 /* |
608 | * Maximum valid counter | |
609 | * logical channel number. | |
610 | */ | |
d8515652 IA |
611 | #define S626_NUM_INTSOURCES 4 |
612 | #define S626_NUM_LATCHSOURCES 4 | |
613 | #define S626_NUM_CLKMULTS 4 | |
614 | #define S626_NUM_CLKSOURCES 4 | |
615 | #define S626_NUM_CLKPOLS 2 | |
616 | #define S626_NUM_INDEXPOLS 2 | |
617 | #define S626_NUM_INDEXSOURCES 2 | |
618 | #define S626_NUM_LOADTRIGS 4 | |
11e865c1 | 619 | |
03c1a0b8 IA |
620 | /* General macros for manipulating bitfields: */ |
621 | #define S626_MAKE(x, w, p) (((x) & ((1 << (w)) - 1)) << (p)) | |
622 | #define S626_UNMAKE(v, w, p) (((v) >> (p)) & ((1 << (w)) - 1)) | |
eb4700ed IA |
623 | |
624 | /* Bit field positions in CRA: */ | |
d8515652 | 625 | #define S626_CRABIT_INDXSRC_B 14 /* B index source. */ |
622ec01a | 626 | #define S626_CRABIT_CNTSRC_B 12 /* B counter source. */ |
d8515652 IA |
627 | #define S626_CRABIT_INDXPOL_A 11 /* A index polarity. */ |
628 | #define S626_CRABIT_LOADSRC_A 9 /* A preload trigger. */ | |
629 | #define S626_CRABIT_CLKMULT_A 7 /* A clock multiplier. */ | |
630 | #define S626_CRABIT_INTSRC_A 5 /* A interrupt source. */ | |
631 | #define S626_CRABIT_CLKPOL_A 4 /* A clock polarity. */ | |
632 | #define S626_CRABIT_INDXSRC_A 2 /* A index source. */ | |
622ec01a | 633 | #define S626_CRABIT_CNTSRC_A 0 /* A counter source. */ |
eb4700ed | 634 | |
03c1a0b8 IA |
635 | /* Bit field widths in CRA: */ |
636 | #define S626_CRAWID_INDXSRC_B 2 | |
637 | #define S626_CRAWID_CNTSRC_B 2 | |
638 | #define S626_CRAWID_INDXPOL_A 1 | |
639 | #define S626_CRAWID_LOADSRC_A 2 | |
640 | #define S626_CRAWID_CLKMULT_A 2 | |
641 | #define S626_CRAWID_INTSRC_A 2 | |
642 | #define S626_CRAWID_CLKPOL_A 1 | |
643 | #define S626_CRAWID_INDXSRC_A 2 | |
644 | #define S626_CRAWID_CNTSRC_A 2 | |
645 | ||
646 | /* Bit field masks for CRA: */ | |
647 | #define S626_CRAMSK_INDXSRC_B S626_SET_CRA_INDXSRC_B(~0) | |
648 | #define S626_CRAMSK_CNTSRC_B S626_SET_CRA_CNTSRC_B(~0) | |
649 | #define S626_CRAMSK_INDXPOL_A S626_SET_CRA_INDXPOL_A(~0) | |
650 | #define S626_CRAMSK_LOADSRC_A S626_SET_CRA_LOADSRC_A(~0) | |
651 | #define S626_CRAMSK_CLKMULT_A S626_SET_CRA_CLKMULT_A(~0) | |
652 | #define S626_CRAMSK_INTSRC_A S626_SET_CRA_INTSRC_A(~0) | |
653 | #define S626_CRAMSK_CLKPOL_A S626_SET_CRA_CLKPOL_A(~0) | |
654 | #define S626_CRAMSK_INDXSRC_A S626_SET_CRA_INDXSRC_A(~0) | |
655 | #define S626_CRAMSK_CNTSRC_A S626_SET_CRA_CNTSRC_A(~0) | |
656 | ||
657 | /* Construct parts of the CRA value: */ | |
658 | #define S626_SET_CRA_INDXSRC_B(x) \ | |
659 | S626_MAKE((x), S626_CRAWID_INDXSRC_B, S626_CRABIT_INDXSRC_B) | |
660 | #define S626_SET_CRA_CNTSRC_B(x) \ | |
661 | S626_MAKE((x), S626_CRAWID_CNTSRC_B, S626_CRABIT_CNTSRC_B) | |
662 | #define S626_SET_CRA_INDXPOL_A(x) \ | |
663 | S626_MAKE((x), S626_CRAWID_INDXPOL_A, S626_CRABIT_INDXPOL_A) | |
664 | #define S626_SET_CRA_LOADSRC_A(x) \ | |
665 | S626_MAKE((x), S626_CRAWID_LOADSRC_A, S626_CRABIT_LOADSRC_A) | |
666 | #define S626_SET_CRA_CLKMULT_A(x) \ | |
667 | S626_MAKE((x), S626_CRAWID_CLKMULT_A, S626_CRABIT_CLKMULT_A) | |
668 | #define S626_SET_CRA_INTSRC_A(x) \ | |
669 | S626_MAKE((x), S626_CRAWID_INTSRC_A, S626_CRABIT_INTSRC_A) | |
670 | #define S626_SET_CRA_CLKPOL_A(x) \ | |
671 | S626_MAKE((x), S626_CRAWID_CLKPOL_A, S626_CRABIT_CLKPOL_A) | |
672 | #define S626_SET_CRA_INDXSRC_A(x) \ | |
673 | S626_MAKE((x), S626_CRAWID_INDXSRC_A, S626_CRABIT_INDXSRC_A) | |
674 | #define S626_SET_CRA_CNTSRC_A(x) \ | |
675 | S626_MAKE((x), S626_CRAWID_CNTSRC_A, S626_CRABIT_CNTSRC_A) | |
676 | ||
677 | /* Extract parts of the CRA value: */ | |
678 | #define S626_GET_CRA_INDXSRC_B(v) \ | |
679 | S626_UNMAKE((v), S626_CRAWID_INDXSRC_B, S626_CRABIT_INDXSRC_B) | |
680 | #define S626_GET_CRA_CNTSRC_B(v) \ | |
681 | S626_UNMAKE((v), S626_CRAWID_CNTSRC_B, S626_CRABIT_CNTSRC_B) | |
682 | #define S626_GET_CRA_INDXPOL_A(v) \ | |
683 | S626_UNMAKE((v), S626_CRAWID_INDXPOL_A, S626_CRABIT_INDXPOL_A) | |
684 | #define S626_GET_CRA_LOADSRC_A(v) \ | |
685 | S626_UNMAKE((v), S626_CRAWID_LOADSRC_A, S626_CRABIT_LOADSRC_A) | |
686 | #define S626_GET_CRA_CLKMULT_A(v) \ | |
687 | S626_UNMAKE((v), S626_CRAWID_CLKMULT_A, S626_CRABIT_CLKMULT_A) | |
688 | #define S626_GET_CRA_INTSRC_A(v) \ | |
689 | S626_UNMAKE((v), S626_CRAWID_INTSRC_A, S626_CRABIT_INTSRC_A) | |
690 | #define S626_GET_CRA_CLKPOL_A(v) \ | |
691 | S626_UNMAKE((v), S626_CRAWID_CLKPOL_A, S626_CRABIT_CLKPOL_A) | |
692 | #define S626_GET_CRA_INDXSRC_A(v) \ | |
693 | S626_UNMAKE((v), S626_CRAWID_INDXSRC_A, S626_CRABIT_INDXSRC_A) | |
694 | #define S626_GET_CRA_CNTSRC_A(v) \ | |
695 | S626_UNMAKE((v), S626_CRAWID_CNTSRC_A, S626_CRABIT_CNTSRC_A) | |
696 | ||
eb4700ed | 697 | /* Bit field positions in CRB: */ |
e0b07b79 IA |
698 | #define S626_CRBBIT_INTRESETCMD 15 /* (w) Interrupt reset command. */ |
699 | #define S626_CRBBIT_CNTDIR_B 15 /* (r) B counter direction. */ | |
700 | #define S626_CRBBIT_INTRESET_B 14 /* (w) B interrupt reset enable. */ | |
701 | #define S626_CRBBIT_OVERDO_A 14 /* (r) A overflow routed to dig. out. */ | |
702 | #define S626_CRBBIT_INTRESET_A 13 /* (w) A interrupt reset enable. */ | |
703 | #define S626_CRBBIT_OVERDO_B 13 /* (r) B overflow routed to dig. out. */ | |
d8515652 IA |
704 | #define S626_CRBBIT_CLKENAB_A 12 /* A clock enable. */ |
705 | #define S626_CRBBIT_INTSRC_B 10 /* B interrupt source. */ | |
706 | #define S626_CRBBIT_LATCHSRC 8 /* A/B latch source. */ | |
707 | #define S626_CRBBIT_LOADSRC_B 6 /* B preload trigger. */ | |
e0b07b79 | 708 | #define S626_CRBBIT_CLEAR_B 7 /* B cleared when A overflows. */ |
d8515652 IA |
709 | #define S626_CRBBIT_CLKMULT_B 3 /* B clock multiplier. */ |
710 | #define S626_CRBBIT_CLKENAB_B 2 /* B clock enable. */ | |
711 | #define S626_CRBBIT_INDXPOL_B 1 /* B index polarity. */ | |
712 | #define S626_CRBBIT_CLKPOL_B 0 /* B clock polarity. */ | |
eb4700ed | 713 | |
03c1a0b8 IA |
714 | /* Bit field widths in CRB: */ |
715 | #define S626_CRBWID_INTRESETCMD 1 | |
716 | #define S626_CRBWID_CNTDIR_B 1 | |
717 | #define S626_CRBWID_INTRESET_B 1 | |
718 | #define S626_CRBWID_OVERDO_A 1 | |
719 | #define S626_CRBWID_INTRESET_A 1 | |
720 | #define S626_CRBWID_OVERDO_B 1 | |
721 | #define S626_CRBWID_CLKENAB_A 1 | |
722 | #define S626_CRBWID_INTSRC_B 2 | |
723 | #define S626_CRBWID_LATCHSRC 2 | |
724 | #define S626_CRBWID_LOADSRC_B 2 | |
725 | #define S626_CRBWID_CLEAR_B 1 | |
726 | #define S626_CRBWID_CLKMULT_B 2 | |
727 | #define S626_CRBWID_CLKENAB_B 1 | |
728 | #define S626_CRBWID_INDXPOL_B 1 | |
729 | #define S626_CRBWID_CLKPOL_B 1 | |
730 | ||
731 | /* Bit field masks for CRB: */ | |
732 | #define S626_CRBMSK_INTRESETCMD S626_SET_CRB_INTRESETCMD(~0) /* (w) */ | |
733 | #define S626_CRBMSK_CNTDIR_B S626_CRBMSK_INTRESETCMD /* (r) */ | |
734 | #define S626_CRBMSK_INTRESET_B S626_SET_CRB_INTRESET_B(~0) /* (w) */ | |
735 | #define S626_CRBMSK_OVERDO_A S626_CRBMSK_INTRESET_B /* (r) */ | |
736 | #define S626_CRBMSK_INTRESET_A S626_SET_CRB_INTRESET_A(~0) /* (w) */ | |
737 | #define S626_CRBMSK_OVERDO_B S626_CRBMSK_INTRESET_A /* (r) */ | |
738 | #define S626_CRBMSK_CLKENAB_A S626_SET_CRB_CLKENAB_A(~0) | |
739 | #define S626_CRBMSK_INTSRC_B S626_SET_CRB_INTSRC_B(~0) | |
740 | #define S626_CRBMSK_LATCHSRC S626_SET_CRB_LATCHSRC(~0) | |
741 | #define S626_CRBMSK_LOADSRC_B S626_SET_CRB_LOADSRC_B(~0) | |
742 | #define S626_CRBMSK_CLEAR_B S626_SET_CRB_CLEAR_B(~0) | |
743 | #define S626_CRBMSK_CLKMULT_B S626_SET_CRB_CLKMULT_B(~0) | |
744 | #define S626_CRBMSK_CLKENAB_B S626_SET_CRB_CLKENAB_B(~0) | |
745 | #define S626_CRBMSK_INDXPOL_B S626_SET_CRB_INDXPOL_B(~0) | |
746 | #define S626_CRBMSK_CLKPOL_B S626_SET_CRB_CLKPOL_B(~0) | |
6a98d36e | 747 | |
eb4700ed | 748 | /* Interrupt reset control bits. */ |
d8515652 IA |
749 | #define S626_CRBMSK_INTCTRL (S626_CRBMSK_INTRESETCMD | \ |
750 | S626_CRBMSK_INTRESET_A | \ | |
751 | S626_CRBMSK_INTRESET_B) | |
11e865c1 | 752 | |
03c1a0b8 IA |
753 | /* Construct parts of the CRB value: */ |
754 | #define S626_SET_CRB_INTRESETCMD(x) \ | |
755 | S626_MAKE((x), S626_CRBWID_INTRESETCMD, S626_CRBBIT_INTRESETCMD) | |
756 | #define S626_SET_CRB_INTRESET_B(x) \ | |
757 | S626_MAKE((x), S626_CRBWID_INTRESET_B, S626_CRBBIT_INTRESET_B) | |
758 | #define S626_SET_CRB_INTRESET_A(x) \ | |
759 | S626_MAKE((x), S626_CRBWID_INTRESET_A, S626_CRBBIT_INTRESET_A) | |
760 | #define S626_SET_CRB_CLKENAB_A(x) \ | |
761 | S626_MAKE((x), S626_CRBWID_CLKENAB_A, S626_CRBBIT_CLKENAB_A) | |
762 | #define S626_SET_CRB_INTSRC_B(x) \ | |
763 | S626_MAKE((x), S626_CRBWID_INTSRC_B, S626_CRBBIT_INTSRC_B) | |
764 | #define S626_SET_CRB_LATCHSRC(x) \ | |
765 | S626_MAKE((x), S626_CRBWID_LATCHSRC, S626_CRBBIT_LATCHSRC) | |
766 | #define S626_SET_CRB_LOADSRC_B(x) \ | |
767 | S626_MAKE((x), S626_CRBWID_LOADSRC_B, S626_CRBBIT_LOADSRC_B) | |
768 | #define S626_SET_CRB_CLEAR_B(x) \ | |
769 | S626_MAKE((x), S626_CRBWID_CLEAR_B, S626_CRBBIT_CLEAR_B) | |
770 | #define S626_SET_CRB_CLKMULT_B(x) \ | |
771 | S626_MAKE((x), S626_CRBWID_CLKMULT_B, S626_CRBBIT_CLKMULT_B) | |
772 | #define S626_SET_CRB_CLKENAB_B(x) \ | |
773 | S626_MAKE((x), S626_CRBWID_CLKENAB_B, S626_CRBBIT_CLKENAB_B) | |
774 | #define S626_SET_CRB_INDXPOL_B(x) \ | |
775 | S626_MAKE((x), S626_CRBWID_INDXPOL_B, S626_CRBBIT_INDXPOL_B) | |
776 | #define S626_SET_CRB_CLKPOL_B(x) \ | |
777 | S626_MAKE((x), S626_CRBWID_CLKPOL_B, S626_CRBBIT_CLKPOL_B) | |
778 | ||
779 | /* Extract parts of the CRB value: */ | |
780 | #define S626_GET_CRB_CNTDIR_B(v) \ | |
781 | S626_UNMAKE((v), S626_CRBWID_CNTDIR_B, S626_CRBBIT_CNTDIR_B) | |
782 | #define S626_GET_CRB_OVERDO_A(v) \ | |
783 | S626_UNMAKE((v), S626_CRBWID_OVERDO_A, S626_CRBBIT_OVERDO_A) | |
784 | #define S626_GET_CRB_OVERDO_B(v) \ | |
785 | S626_UNMAKE((v), S626_CRBWID_OVERDO_B, S626_CRBBIT_OVERDO_B) | |
786 | #define S626_GET_CRB_CLKENAB_A(v) \ | |
787 | S626_UNMAKE((v), S626_CRBWID_CLKENAB_A, S626_CRBBIT_CLKENAB_A) | |
788 | #define S626_GET_CRB_INTSRC_B(v) \ | |
789 | S626_UNMAKE((v), S626_CRBWID_INTSRC_B, S626_CRBBIT_INTSRC_B) | |
790 | #define S626_GET_CRB_LATCHSRC(v) \ | |
791 | S626_UNMAKE((v), S626_CRBWID_LATCHSRC, S626_CRBBIT_LATCHSRC) | |
792 | #define S626_GET_CRB_LOADSRC_B(v) \ | |
793 | S626_UNMAKE((v), S626_CRBWID_LOADSRC_B, S626_CRBBIT_LOADSRC_B) | |
794 | #define S626_GET_CRB_CLEAR_B(v) \ | |
795 | S626_UNMAKE((v), S626_CRBWID_CLEAR_B, S626_CRBBIT_CLEAR_B) | |
796 | #define S626_GET_CRB_CLKMULT_B(v) \ | |
797 | S626_UNMAKE((v), S626_CRBWID_CLKMULT_B, S626_CRBBIT_CLKMULT_B) | |
798 | #define S626_GET_CRB_CLKENAB_B(v) \ | |
799 | S626_UNMAKE((v), S626_CRBWID_CLKENAB_B, S626_CRBBIT_CLKENAB_B) | |
800 | #define S626_GET_CRB_INDXPOL_B(v) \ | |
801 | S626_UNMAKE((v), S626_CRBWID_INDXPOL_B, S626_CRBBIT_INDXPOL_B) | |
802 | #define S626_GET_CRB_CLKPOL_B(v) \ | |
803 | S626_UNMAKE((v), S626_CRBWID_CLKPOL_B, S626_CRBBIT_CLKPOL_B) | |
804 | ||
805 | /* Bit field positions for standardized SETUP structure: */ | |
d8515652 IA |
806 | #define S626_STDBIT_INTSRC 13 |
807 | #define S626_STDBIT_LATCHSRC 11 | |
808 | #define S626_STDBIT_LOADSRC 9 | |
809 | #define S626_STDBIT_INDXSRC 7 | |
810 | #define S626_STDBIT_INDXPOL 6 | |
622ec01a | 811 | #define S626_STDBIT_ENCMODE 4 |
d8515652 IA |
812 | #define S626_STDBIT_CLKPOL 3 |
813 | #define S626_STDBIT_CLKMULT 1 | |
814 | #define S626_STDBIT_CLKENAB 0 | |
11e865c1 | 815 | |
03c1a0b8 IA |
816 | /* Bit field widths for standardized SETUP structure: */ |
817 | #define S626_STDWID_INTSRC 2 | |
818 | #define S626_STDWID_LATCHSRC 2 | |
819 | #define S626_STDWID_LOADSRC 2 | |
2cea19fa | 820 | #define S626_STDWID_INDXSRC 2 |
03c1a0b8 IA |
821 | #define S626_STDWID_INDXPOL 1 |
822 | #define S626_STDWID_ENCMODE 2 | |
823 | #define S626_STDWID_CLKPOL 1 | |
824 | #define S626_STDWID_CLKMULT 2 | |
825 | #define S626_STDWID_CLKENAB 1 | |
826 | ||
827 | /* Bit field masks for standardized SETUP structure: */ | |
828 | #define S626_STDMSK_INTSRC S626_SET_STD_INTSRC(~0) | |
829 | #define S626_STDMSK_LATCHSRC S626_SET_STD_LATCHSRC(~0) | |
830 | #define S626_STDMSK_LOADSRC S626_SET_STD_LOADSRC(~0) | |
831 | #define S626_STDMSK_INDXSRC S626_SET_STD_INDXSRC(~0) | |
832 | #define S626_STDMSK_INDXPOL S626_SET_STD_INDXPOL(~0) | |
833 | #define S626_STDMSK_ENCMODE S626_SET_STD_ENCMODE(~0) | |
834 | #define S626_STDMSK_CLKPOL S626_SET_STD_CLKPOL(~0) | |
835 | #define S626_STDMSK_CLKMULT S626_SET_STD_CLKMULT(~0) | |
836 | #define S626_STDMSK_CLKENAB S626_SET_STD_CLKENAB(~0) | |
837 | ||
838 | /* Construct parts of standardized SETUP structure: */ | |
839 | #define S626_SET_STD_INTSRC(x) \ | |
840 | S626_MAKE((x), S626_STDWID_INTSRC, S626_STDBIT_INTSRC) | |
841 | #define S626_SET_STD_LATCHSRC(x) \ | |
842 | S626_MAKE((x), S626_STDWID_LATCHSRC, S626_STDBIT_LATCHSRC) | |
843 | #define S626_SET_STD_LOADSRC(x) \ | |
844 | S626_MAKE((x), S626_STDWID_LOADSRC, S626_STDBIT_LOADSRC) | |
845 | #define S626_SET_STD_INDXSRC(x) \ | |
846 | S626_MAKE((x), S626_STDWID_INDXSRC, S626_STDBIT_INDXSRC) | |
847 | #define S626_SET_STD_INDXPOL(x) \ | |
848 | S626_MAKE((x), S626_STDWID_INDXPOL, S626_STDBIT_INDXPOL) | |
849 | #define S626_SET_STD_ENCMODE(x) \ | |
850 | S626_MAKE((x), S626_STDWID_ENCMODE, S626_STDBIT_ENCMODE) | |
851 | #define S626_SET_STD_CLKPOL(x) \ | |
852 | S626_MAKE((x), S626_STDWID_CLKPOL, S626_STDBIT_CLKPOL) | |
853 | #define S626_SET_STD_CLKMULT(x) \ | |
854 | S626_MAKE((x), S626_STDWID_CLKMULT, S626_STDBIT_CLKMULT) | |
855 | #define S626_SET_STD_CLKENAB(x) \ | |
856 | S626_MAKE((x), S626_STDWID_CLKENAB, S626_STDBIT_CLKENAB) | |
857 | ||
858 | /* Extract parts of standardized SETUP structure: */ | |
859 | #define S626_GET_STD_INTSRC(v) \ | |
860 | S626_UNMAKE((v), S626_STDWID_INTSRC, S626_STDBIT_INTSRC) | |
861 | #define S626_GET_STD_LATCHSRC(v) \ | |
862 | S626_UNMAKE((v), S626_STDWID_LATCHSRC, S626_STDBIT_LATCHSRC) | |
863 | #define S626_GET_STD_LOADSRC(v) \ | |
864 | S626_UNMAKE((v), S626_STDWID_LOADSRC, S626_STDBIT_LOADSRC) | |
865 | #define S626_GET_STD_INDXSRC(v) \ | |
866 | S626_UNMAKE((v), S626_STDWID_INDXSRC, S626_STDBIT_INDXSRC) | |
867 | #define S626_GET_STD_INDXPOL(v) \ | |
868 | S626_UNMAKE((v), S626_STDWID_INDXPOL, S626_STDBIT_INDXPOL) | |
869 | #define S626_GET_STD_ENCMODE(v) \ | |
870 | S626_UNMAKE((v), S626_STDWID_ENCMODE, S626_STDBIT_ENCMODE) | |
871 | #define S626_GET_STD_CLKPOL(v) \ | |
872 | S626_UNMAKE((v), S626_STDWID_CLKPOL, S626_STDBIT_CLKPOL) | |
873 | #define S626_GET_STD_CLKMULT(v) \ | |
874 | S626_UNMAKE((v), S626_STDWID_CLKMULT, S626_STDBIT_CLKMULT) | |
875 | #define S626_GET_STD_CLKENAB(v) \ | |
876 | S626_UNMAKE((v), S626_STDWID_CLKENAB, S626_STDBIT_CLKENAB) | |
11e865c1 | 877 | |
eb4700ed | 878 | #endif |