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Merge remote-tracking branch 'staging/staging-next'
[deliverable/linux.git] / drivers / staging / dgnc / dgnc_neo.c
CommitLineData
0b99d589
LL		 1/*
2 * Copyright 2003 Digi International (www.digi.com)
3 * Scott H Kilau <Scott_Kilau at digi dot com>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2, or (at your option)
8 * any later version.
5ba5b89a 9 *
0b99d589 10 * This program is distributed in the hope that it will be useful,
5ba5b89a
LL		 11 * but WITHOUT ANY WARRANTY, EXPRESS OR IMPLIED; without even the
12 * implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
0b99d589 13 * PURPOSE. See the GNU General Public License for more details.
0b99d589
LL		 14 */
15
0b99d589 16#include <linux/kernel.h>
0b99d589
LL		 17#include <linux/sched.h> /* For jiffies, task states */
18#include <linux/interrupt.h> /* For tasklet and interrupt structs/defines */
19#include <linux/delay.h> /* For udelay */
9dfe5670 20#include <linux/io.h> /* For read[bwl]/write[bwl] */
0b99d589
LL		 21#include <linux/serial.h> /* For struct async_serial */
22#include <linux/serial_reg.h> /* For the various UART offsets */
23
24#include "dgnc_driver.h" /* Driver main header file */
25#include "dgnc_neo.h" /* Our header file */
26#include "dgnc_tty.h"
0b99d589 27
03425f55
LL		 28static inline void neo_parse_lsr(struct dgnc_board *brd, uint port);
29static inline void neo_parse_isr(struct dgnc_board *brd, uint port);
0b99d589
LL		 30static void neo_copy_data_from_uart_to_queue(struct channel_t *ch);
31static inline void neo_clear_break(struct channel_t *ch, int force);
32static inline void neo_set_cts_flow_control(struct channel_t *ch);
33static inline void neo_set_rts_flow_control(struct channel_t *ch);
34static inline void neo_set_ixon_flow_control(struct channel_t *ch);
35static inline void neo_set_ixoff_flow_control(struct channel_t *ch);
36static inline void neo_set_no_output_flow_control(struct channel_t *ch);
37static inline void neo_set_no_input_flow_control(struct channel_t *ch);
38static inline void neo_set_new_start_stop_chars(struct channel_t *ch);
446393e9 39static void neo_parse_modem(struct channel_t *ch, unsigned char signals);
0b99d589 40static void neo_tasklet(unsigned long data);
03425f55 41static void neo_vpd(struct dgnc_board *brd);
0b99d589
LL		 42static void neo_uart_init(struct channel_t *ch);
43static void neo_uart_off(struct channel_t *ch);
44static int neo_drain(struct tty_struct *tty, uint seconds);
45static void neo_param(struct tty_struct *tty);
46static void neo_assert_modem_signals(struct channel_t *ch);
47static void neo_flush_uart_write(struct channel_t *ch);
48static void neo_flush_uart_read(struct channel_t *ch);
49static void neo_disable_receiver(struct channel_t *ch);
50static void neo_enable_receiver(struct channel_t *ch);
51static void neo_send_break(struct channel_t *ch, int msecs);
52static void neo_send_start_character(struct channel_t *ch);
53static void neo_send_stop_character(struct channel_t *ch);
54static void neo_copy_data_from_queue_to_uart(struct channel_t *ch);
55static uint neo_get_uart_bytes_left(struct channel_t *ch);
56static void neo_send_immediate_char(struct channel_t *ch, unsigned char c);
57static irqreturn_t neo_intr(int irq, void *voidbrd);
58
0b99d589
LL		 59struct board_ops dgnc_neo_ops = {
60 .tasklet = neo_tasklet,
61 .intr = neo_intr,
62 .uart_init = neo_uart_init,
63 .uart_off = neo_uart_off,
64 .drain = neo_drain,
65 .param = neo_param,
66 .vpd = neo_vpd,
67 .assert_modem_signals = neo_assert_modem_signals,
68 .flush_uart_write = neo_flush_uart_write,
69 .flush_uart_read = neo_flush_uart_read,
70 .disable_receiver = neo_disable_receiver,
71 .enable_receiver = neo_enable_receiver,
72 .send_break = neo_send_break,
73 .send_start_character = neo_send_start_character,
74 .send_stop_character = neo_send_stop_character,
75 .copy_data_from_queue_to_uart = neo_copy_data_from_queue_to_uart,
76 .get_uart_bytes_left = neo_get_uart_bytes_left,
77 .send_immediate_char = neo_send_immediate_char
78};
5ba5b89a 79
0b99d589
LL		 80/*
81 * This function allows calls to ensure that all outstanding
82 * PCI writes have been completed, by doing a PCI read against
83 * a non-destructive, read-only location on the Neo card.
84 *
85 * In this case, we are reading the DVID (Read-only Device Identification)
86 * value of the Neo card.
87 */
03425f55 88static inline void neo_pci_posting_flush(struct dgnc_board *bd)
0b99d589
LL		 89{
90 readb(bd->re_map_membase + 0x8D);
91}
92
93static inline void neo_set_cts_flow_control(struct channel_t *ch)
94{
446393e9
EA		 95 unsigned char ier = readb(&ch->ch_neo_uart->ier);
96 unsigned char efr = readb(&ch->ch_neo_uart->efr);
0b99d589 97
0b99d589
LL		 98 /* Turn on auto CTS flow control */
99#if 1
64e784c4 100 ier |= UART_17158_IER_CTSDSR;
0b99d589
LL		 101#else
102 ier &= ~(UART_17158_IER_CTSDSR);
103#endif
104
105 efr |= (UART_17158_EFR_ECB | UART_17158_EFR_CTSDSR);
106
5ba5b89a 107 /* Turn off auto Xon flow control */
64e784c4 108 efr &= ~UART_17158_EFR_IXON;
0b99d589
LL		 109
110 /* Why? Becuz Exar's spec says we have to zero it out before setting it */
111 writeb(0, &ch->ch_neo_uart->efr);
112
113 /* Turn on UART enhanced bits */
114 writeb(efr, &ch->ch_neo_uart->efr);
115
116 /* Turn on table D, with 8 char hi/low watermarks */
a1115c9f
DY		 117 writeb(UART_17158_FCTR_TRGD | UART_17158_FCTR_RTS_4DELAY,
118 &ch->ch_neo_uart->fctr);
0b99d589
LL		 119
120 /* Feed the UART our trigger levels */
121 writeb(8, &ch->ch_neo_uart->tfifo);
122 ch->ch_t_tlevel = 8;
123
124 writeb(ier, &ch->ch_neo_uart->ier);
125
126 neo_pci_posting_flush(ch->ch_bd);
127}
128
0b99d589
LL		 129static inline void neo_set_rts_flow_control(struct channel_t *ch)
130{
446393e9
EA		 131 unsigned char ier = readb(&ch->ch_neo_uart->ier);
132 unsigned char efr = readb(&ch->ch_neo_uart->efr);
0b99d589 133
0b99d589
LL		 134 /* Turn on auto RTS flow control */
135#if 1
64e784c4 136 ier |= UART_17158_IER_RTSDTR;
0b99d589
LL		 137#else
138 ier &= ~(UART_17158_IER_RTSDTR);
139#endif
140 efr |= (UART_17158_EFR_ECB | UART_17158_EFR_RTSDTR);
141
142 /* Turn off auto Xoff flow control */
64e784c4
SA		 143 ier &= ~UART_17158_IER_XOFF;
144 efr &= ~UART_17158_EFR_IXOFF;
0b99d589
LL		 145
146 /* Why? Becuz Exar's spec says we have to zero it out before setting it */
147 writeb(0, &ch->ch_neo_uart->efr);
148
149 /* Turn on UART enhanced bits */
150 writeb(efr, &ch->ch_neo_uart->efr);
151
a1115c9f
DY		 152 writeb(UART_17158_FCTR_TRGD | UART_17158_FCTR_RTS_4DELAY,
153 &ch->ch_neo_uart->fctr);
0b99d589
LL		 154 ch->ch_r_watermark = 4;
155
156 writeb(32, &ch->ch_neo_uart->rfifo);
157 ch->ch_r_tlevel = 32;
158
159 writeb(ier, &ch->ch_neo_uart->ier);
160
161 /*
162 * From the Neo UART spec sheet:
163 * The auto RTS/DTR function must be started by asserting
164 * RTS/DTR# output pin (MCR bit-0 or 1 to logic 1 after
165 * it is enabled.
166 */
64e784c4 167 ch->ch_mostat |= UART_MCR_RTS;
0b99d589
LL		 168
169 neo_pci_posting_flush(ch->ch_bd);
170}
171
0b99d589
LL		 172static inline void neo_set_ixon_flow_control(struct channel_t *ch)
173{
446393e9
EA		 174 unsigned char ier = readb(&ch->ch_neo_uart->ier);
175 unsigned char efr = readb(&ch->ch_neo_uart->efr);
0b99d589 176
0b99d589 177 /* Turn off auto CTS flow control */
64e784c4
SA		 178 ier &= ~UART_17158_IER_CTSDSR;
179 efr &= ~UART_17158_EFR_CTSDSR;
0b99d589
LL		 180
181 /* Turn on auto Xon flow control */
182 efr |= (UART_17158_EFR_ECB | UART_17158_EFR_IXON);
183
184 /* Why? Becuz Exar's spec says we have to zero it out before setting it */
185 writeb(0, &ch->ch_neo_uart->efr);
186
187 /* Turn on UART enhanced bits */
188 writeb(efr, &ch->ch_neo_uart->efr);
189
a1115c9f 190 writeb(UART_17158_FCTR_TRGD | UART_17158_FCTR_RTS_8DELAY,
6175e73d 191 &ch->ch_neo_uart->fctr);
0b99d589
LL		 192 ch->ch_r_watermark = 4;
193
194 writeb(32, &ch->ch_neo_uart->rfifo);
195 ch->ch_r_tlevel = 32;
196
197 /* Tell UART what start/stop chars it should be looking for */
198 writeb(ch->ch_startc, &ch->ch_neo_uart->xonchar1);
199 writeb(0, &ch->ch_neo_uart->xonchar2);
200
201 writeb(ch->ch_stopc, &ch->ch_neo_uart->xoffchar1);
202 writeb(0, &ch->ch_neo_uart->xoffchar2);
203
204 writeb(ier, &ch->ch_neo_uart->ier);
205
206 neo_pci_posting_flush(ch->ch_bd);
207}
208
0b99d589
LL		 209static inline void neo_set_ixoff_flow_control(struct channel_t *ch)
210{
446393e9
EA		 211 unsigned char ier = readb(&ch->ch_neo_uart->ier);
212 unsigned char efr = readb(&ch->ch_neo_uart->efr);
0b99d589 213
0b99d589 214 /* Turn off auto RTS flow control */
64e784c4
SA		 215 ier &= ~UART_17158_IER_RTSDTR;
216 efr &= ~UART_17158_EFR_RTSDTR;
0b99d589
LL		 217
218 /* Turn on auto Xoff flow control */
64e784c4 219 ier |= UART_17158_IER_XOFF;
0b99d589
LL		 220 efr |= (UART_17158_EFR_ECB | UART_17158_EFR_IXOFF);
221
222 /* Why? Becuz Exar's spec says we have to zero it out before setting it */
223 writeb(0, &ch->ch_neo_uart->efr);
224
225 /* Turn on UART enhanced bits */
226 writeb(efr, &ch->ch_neo_uart->efr);
227
228 /* Turn on table D, with 8 char hi/low watermarks */
a1115c9f
DY		 229 writeb(UART_17158_FCTR_TRGD | UART_17158_FCTR_RTS_8DELAY,
230 &ch->ch_neo_uart->fctr);
0b99d589
LL		 231
232 writeb(8, &ch->ch_neo_uart->tfifo);
00804f77 233 ch->ch_t_tlevel = 8;
0b99d589
LL		 234
235 /* Tell UART what start/stop chars it should be looking for */
236 writeb(ch->ch_startc, &ch->ch_neo_uart->xonchar1);
237 writeb(0, &ch->ch_neo_uart->xonchar2);
238
239 writeb(ch->ch_stopc, &ch->ch_neo_uart->xoffchar1);
240 writeb(0, &ch->ch_neo_uart->xoffchar2);
241
242 writeb(ier, &ch->ch_neo_uart->ier);
243
244 neo_pci_posting_flush(ch->ch_bd);
245}
246
0b99d589
LL		 247static inline void neo_set_no_input_flow_control(struct channel_t *ch)
248{
446393e9
EA		 249 unsigned char ier = readb(&ch->ch_neo_uart->ier);
250 unsigned char efr = readb(&ch->ch_neo_uart->efr);
0b99d589 251
0b99d589 252 /* Turn off auto RTS flow control */
64e784c4
SA		 253 ier &= ~UART_17158_IER_RTSDTR;
254 efr &= ~UART_17158_EFR_RTSDTR;
0b99d589
LL		 255
256 /* Turn off auto Xoff flow control */
64e784c4 257 ier &= ~UART_17158_IER_XOFF;
0b99d589
LL		 258 if (ch->ch_c_iflag & IXON)
259 efr &= ~(UART_17158_EFR_IXOFF);
260 else
261 efr &= ~(UART_17158_EFR_ECB | UART_17158_EFR_IXOFF);
262
0b99d589
LL		 263 /* Why? Becuz Exar's spec says we have to zero it out before setting it */
264 writeb(0, &ch->ch_neo_uart->efr);
265
266 /* Turn on UART enhanced bits */
267 writeb(efr, &ch->ch_neo_uart->efr);
268
269 /* Turn on table D, with 8 char hi/low watermarks */
a1115c9f
DY		 270 writeb(UART_17158_FCTR_TRGD | UART_17158_FCTR_RTS_8DELAY,
271 &ch->ch_neo_uart->fctr);
0b99d589
LL		 272
273 ch->ch_r_watermark = 0;
274
275 writeb(16, &ch->ch_neo_uart->tfifo);
00804f77 276 ch->ch_t_tlevel = 16;
0b99d589
LL		 277
278 writeb(16, &ch->ch_neo_uart->rfifo);
00804f77 279 ch->ch_r_tlevel = 16;
0b99d589
LL		 280
281 writeb(ier, &ch->ch_neo_uart->ier);
282
283 neo_pci_posting_flush(ch->ch_bd);
284}
285
0b99d589
LL		 286static inline void neo_set_no_output_flow_control(struct channel_t *ch)
287{
446393e9
EA		 288 unsigned char ier = readb(&ch->ch_neo_uart->ier);
289 unsigned char efr = readb(&ch->ch_neo_uart->efr);
0b99d589 290
0b99d589 291 /* Turn off auto CTS flow control */
64e784c4
SA		 292 ier &= ~UART_17158_IER_CTSDSR;
293 efr &= ~UART_17158_EFR_CTSDSR;
0b99d589
LL		 294
295 /* Turn off auto Xon flow control */
296 if (ch->ch_c_iflag & IXOFF)
64e784c4 297 efr &= ~UART_17158_EFR_IXON;
0b99d589
LL		 298 else
299 efr &= ~(UART_17158_EFR_ECB | UART_17158_EFR_IXON);
300
301 /* Why? Becuz Exar's spec says we have to zero it out before setting it */
302 writeb(0, &ch->ch_neo_uart->efr);
303
304 /* Turn on UART enhanced bits */
305 writeb(efr, &ch->ch_neo_uart->efr);
306
307 /* Turn on table D, with 8 char hi/low watermarks */
a1115c9f
DY		 308 writeb(UART_17158_FCTR_TRGD | UART_17158_FCTR_RTS_8DELAY,
309 &ch->ch_neo_uart->fctr);
0b99d589
LL		 310
311 ch->ch_r_watermark = 0;
312
313 writeb(16, &ch->ch_neo_uart->tfifo);
00804f77 314 ch->ch_t_tlevel = 16;
0b99d589
LL		 315
316 writeb(16, &ch->ch_neo_uart->rfifo);
00804f77 317 ch->ch_r_tlevel = 16;
0b99d589
LL		 318
319 writeb(ier, &ch->ch_neo_uart->ier);
320
321 neo_pci_posting_flush(ch->ch_bd);
322}
323
0b99d589
LL		 324/* change UARTs start/stop chars */
325static inline void neo_set_new_start_stop_chars(struct channel_t *ch)
326{
0b99d589 327 /* if hardware flow control is set, then skip this whole thing */
6175e73d
DY		 328 if (ch->ch_digi.digi_flags & (CTSPACE | RTSPACE) ||
329 ch->ch_c_cflag & CRTSCTS)
0b99d589
LL		 330 return;
331
0b99d589
LL		 332 /* Tell UART what start/stop chars it should be looking for */
333 writeb(ch->ch_startc, &ch->ch_neo_uart->xonchar1);
334 writeb(0, &ch->ch_neo_uart->xonchar2);
335
336 writeb(ch->ch_stopc, &ch->ch_neo_uart->xoffchar1);
337 writeb(0, &ch->ch_neo_uart->xoffchar2);
338
339 neo_pci_posting_flush(ch->ch_bd);
340}
341
0b99d589
LL		 342/*
343 * No locks are assumed to be held when calling this function.
344 */
345static inline void neo_clear_break(struct channel_t *ch, int force)
346{
7be869b0 347 unsigned long flags;
0b99d589 348
7be869b0 349 spin_lock_irqsave(&ch->ch_lock, flags);
0b99d589
LL		 350
351 /* Bail if we aren't currently sending a break. */
352 if (!ch->ch_stop_sending_break) {
7be869b0 353 spin_unlock_irqrestore(&ch->ch_lock, flags);
0b99d589
LL		 354 return;
355 }
356
357 /* Turn break off, and unset some variables */
358 if (ch->ch_flags & CH_BREAK_SENDING) {
318723e4
DY		 359 if (force ||
360 time_after_eq(jiffies, ch->ch_stop_sending_break)) {
446393e9 361 unsigned char temp = readb(&ch->ch_neo_uart->lcr);
1eba3dba 362
00804f77 363 writeb((temp & ~UART_LCR_SBC), &ch->ch_neo_uart->lcr);
0b99d589
LL		 364 neo_pci_posting_flush(ch->ch_bd);
365 ch->ch_flags &= ~(CH_BREAK_SENDING);
366 ch->ch_stop_sending_break = 0;
00804f77
LL		 367 }
368 }
7be869b0 369 spin_unlock_irqrestore(&ch->ch_lock, flags);
0b99d589
LL		 370}
371
0b99d589
LL		 372/*
373 * Parse the ISR register.
374 */
03425f55 375static inline void neo_parse_isr(struct dgnc_board *brd, uint port)
0b99d589
LL		 376{
377 struct channel_t *ch;
446393e9
EA		 378 unsigned char isr;
379 unsigned char cause;
7be869b0 380 unsigned long flags;
0b99d589 381
0b99d589 382 ch = brd->channels[port];
bddb1531 383 if (!ch || ch->magic != DGNC_CHANNEL_MAGIC)
0b99d589
LL		 384 return;
385
386 /* Here we try to figure out what caused the interrupt to happen */
387 while (1) {
0b99d589
LL		 388 isr = readb(&ch->ch_neo_uart->isr_fcr);
389
390 /* Bail if no pending interrupt */
50667c67 391 if (isr & UART_IIR_NO_INT)
0b99d589 392 break;
0b99d589
LL		 393
394 /*
6175e73d
DY		 395 * Yank off the upper 2 bits,
396 * which just show that the FIFO's are enabled.
0b99d589
LL		 397 */
398 isr &= ~(UART_17158_IIR_FIFO_ENABLED);
399
0b99d589
LL		 400 if (isr & (UART_17158_IIR_RDI_TIMEOUT | UART_IIR_RDI)) {
401 /* Read data from uart -> queue */
0b99d589
LL		 402 neo_copy_data_from_uart_to_queue(ch);
403
404 /* Call our tty layer to enforce queue flow control if needed. */
7be869b0 405 spin_lock_irqsave(&ch->ch_lock, flags);
0b99d589 406 dgnc_check_queue_flow_control(ch);
7be869b0 407 spin_unlock_irqrestore(&ch->ch_lock, flags);
0b99d589
LL		 408 }
409
410 if (isr & UART_IIR_THRI) {
0b99d589 411 /* Transfer data (if any) from Write Queue -> UART. */
7be869b0 412 spin_lock_irqsave(&ch->ch_lock, flags);
0b99d589 413 ch->ch_flags |= (CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM);
7be869b0 414 spin_unlock_irqrestore(&ch->ch_lock, flags);
0b99d589
LL		 415 neo_copy_data_from_queue_to_uart(ch);
416 }
417
418 if (isr & UART_17158_IIR_XONXOFF) {
419 cause = readb(&ch->ch_neo_uart->xoffchar1);
420
0b99d589
LL		 421 /*
422 * Since the UART detected either an XON or
423 * XOFF match, we need to figure out which
424 * one it was, so we can suspend or resume data flow.
425 */
426 if (cause == UART_17158_XON_DETECT) {
427 /* Is output stopped right now, if so, resume it */
428 if (brd->channels[port]->ch_flags & CH_STOP) {
7be869b0
RD		 429 spin_lock_irqsave(&ch->ch_lock,
430 flags);
0b99d589 431 ch->ch_flags &= ~(CH_STOP);
7be869b0
RD		 432 spin_unlock_irqrestore(&ch->ch_lock,
433 flags);
0b99d589 434 }
2000c581 435 } else if (cause == UART_17158_XOFF_DETECT) {
0b99d589 436 if (!(brd->channels[port]->ch_flags & CH_STOP)) {
7be869b0
RD		 437 spin_lock_irqsave(&ch->ch_lock,
438 flags);
0b99d589 439 ch->ch_flags |= CH_STOP;
7be869b0
RD		 440 spin_unlock_irqrestore(&ch->ch_lock,
441 flags);
0b99d589 442 }
0b99d589
LL		 443 }
444 }
445
446 if (isr & UART_17158_IIR_HWFLOW_STATE_CHANGE) {
447 /*
448 * If we get here, this means the hardware is doing auto flow control.
449 * Check to see whether RTS/DTR or CTS/DSR caused this interrupt.
450 */
0b99d589
LL		 451 cause = readb(&ch->ch_neo_uart->mcr);
452 /* Which pin is doing auto flow? RTS or DTR? */
453 if ((cause & 0x4) == 0) {
454 if (cause & UART_MCR_RTS) {
7be869b0
RD		 455 spin_lock_irqsave(&ch->ch_lock,
456 flags);
0b99d589 457 ch->ch_mostat |= UART_MCR_RTS;
7be869b0
RD		 458 spin_unlock_irqrestore(&ch->ch_lock,
459 flags);
2000c581 460 } else {
7be869b0
RD		 461 spin_lock_irqsave(&ch->ch_lock,
462 flags);
0b99d589 463 ch->ch_mostat &= ~(UART_MCR_RTS);
7be869b0
RD		 464 spin_unlock_irqrestore(&ch->ch_lock,
465 flags);
0b99d589
LL		 466 }
467 } else {
468 if (cause & UART_MCR_DTR) {
7be869b0
RD		 469 spin_lock_irqsave(&ch->ch_lock,
470 flags);
0b99d589 471 ch->ch_mostat |= UART_MCR_DTR;
7be869b0
RD		 472 spin_unlock_irqrestore(&ch->ch_lock,
473 flags);
2000c581 474 } else {
7be869b0
RD		 475 spin_lock_irqsave(&ch->ch_lock,
476 flags);
0b99d589 477 ch->ch_mostat &= ~(UART_MCR_DTR);
7be869b0
RD		 478 spin_unlock_irqrestore(&ch->ch_lock,
479 flags);
0b99d589
LL		 480 }
481 }
482 }
483
484 /* Parse any modem signal changes */
0b99d589
LL		 485 neo_parse_modem(ch, readb(&ch->ch_neo_uart->msr));
486 }
487}
488
03425f55 489static inline void neo_parse_lsr(struct dgnc_board *brd, uint port)
0b99d589
LL		 490{
491 struct channel_t *ch;
492 int linestatus;
7be869b0 493 unsigned long flags;
0b99d589 494
1f26adc9
RD		 495 /*
496 * Check to make sure it didn't receive interrupt with a null board
497 * associated or a board pointer that wasn't ours.
498 */
499 if (!brd || brd->magic != DGNC_BOARD_MAGIC)
0b99d589
LL		 500 return;
501
4bef52f3 502 if (port >= brd->maxports)
0b99d589
LL		 503 return;
504
505 ch = brd->channels[port];
506 if (!ch || ch->magic != DGNC_CHANNEL_MAGIC)
507 return;
508
509 linestatus = readb(&ch->ch_neo_uart->lsr);
510
0b99d589
LL		 511 ch->ch_cached_lsr |= linestatus;
512
513 if (ch->ch_cached_lsr & UART_LSR_DR) {
0b99d589
LL		 514 /* Read data from uart -> queue */
515 neo_copy_data_from_uart_to_queue(ch);
7be869b0 516 spin_lock_irqsave(&ch->ch_lock, flags);
0b99d589 517 dgnc_check_queue_flow_control(ch);
7be869b0 518 spin_unlock_irqrestore(&ch->ch_lock, flags);
0b99d589
LL		 519 }
520
0b99d589
LL		 521 /*
522 * The next 3 tests should *NOT* happen, as the above test
523 * should encapsulate all 3... At least, thats what Exar says.
524 */
525
f1e51745 526 if (linestatus & UART_LSR_PE)
0b99d589 527 ch->ch_err_parity++;
0b99d589 528
f1e51745 529 if (linestatus & UART_LSR_FE)
0b99d589 530 ch->ch_err_frame++;
0b99d589 531
f1e51745 532 if (linestatus & UART_LSR_BI)
0b99d589 533 ch->ch_err_break++;
0b99d589
LL		 534
535 if (linestatus & UART_LSR_OE) {
536 /*
537 * Rx Oruns. Exar says that an orun will NOT corrupt
538 * the FIFO. It will just replace the holding register
539 * with this new data byte. So basically just ignore this.
540 * Probably we should eventually have an orun stat in our driver...
541 */
542 ch->ch_err_overrun++;
0b99d589
LL		 543 }
544
545 if (linestatus & UART_LSR_THRE) {
7be869b0 546 spin_lock_irqsave(&ch->ch_lock, flags);
0b99d589 547 ch->ch_flags |= (CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM);
7be869b0 548 spin_unlock_irqrestore(&ch->ch_lock, flags);
0b99d589
LL		 549
550 /* Transfer data (if any) from Write Queue -> UART. */
551 neo_copy_data_from_queue_to_uart(ch);
2000c581 552 } else if (linestatus & UART_17158_TX_AND_FIFO_CLR) {
7be869b0 553 spin_lock_irqsave(&ch->ch_lock, flags);
0b99d589 554 ch->ch_flags |= (CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM);
7be869b0 555 spin_unlock_irqrestore(&ch->ch_lock, flags);
0b99d589
LL		 556
557 /* Transfer data (if any) from Write Queue -> UART. */
558 neo_copy_data_from_queue_to_uart(ch);
559 }
560}
561
0b99d589
LL		 562/*
563 * neo_param()
564 * Send any/all changes to the line to the UART.
565 */
566static void neo_param(struct tty_struct *tty)
567{
446393e9
EA		 568 unsigned char lcr = 0;
569 unsigned char uart_lcr = 0;
570 unsigned char ier = 0;
571 unsigned char uart_ier = 0;
00804f77 572 uint baud = 9600;
0b99d589 573 int quot = 0;
03425f55 574 struct dgnc_board *bd;
0b99d589 575 struct channel_t *ch;
00804f77 576 struct un_t *un;
0b99d589 577
50667c67 578 if (!tty || tty->magic != TTY_MAGIC)
0b99d589 579 return;
0b99d589 580
6f418259 581 un = (struct un_t *)tty->driver_data;
50667c67 582 if (!un || un->magic != DGNC_UNIT_MAGIC)
0b99d589 583 return;
0b99d589 584
5ba5b89a 585 ch = un->un_ch;
50667c67 586 if (!ch || ch->magic != DGNC_CHANNEL_MAGIC)
0b99d589 587 return;
0b99d589
LL		 588
589 bd = ch->ch_bd;
50667c67 590 if (!bd || bd->magic != DGNC_BOARD_MAGIC)
0b99d589 591 return;
0b99d589 592
0b99d589
LL		 593 /*
594 * If baud rate is zero, flush queues, and set mval to drop DTR.
595 */
596 if ((ch->ch_c_cflag & (CBAUD)) == 0) {
587abd7b
SL		 597 ch->ch_r_head = 0;
598 ch->ch_r_tail = 0;
599 ch->ch_e_head = 0;
600 ch->ch_e_tail = 0;
601 ch->ch_w_head = 0;
602 ch->ch_w_tail = 0;
0b99d589
LL		 603
604 neo_flush_uart_write(ch);
605 neo_flush_uart_read(ch);
606
607 /* The baudrate is B0 so all modem lines are to be dropped. */
608 ch->ch_flags |= (CH_BAUD0);
609 ch->ch_mostat &= ~(UART_MCR_RTS | UART_MCR_DTR);
610 neo_assert_modem_signals(ch);
611 ch->ch_old_baud = 0;
612 return;
613
614 } else if (ch->ch_custom_speed) {
0b99d589
LL		 615 baud = ch->ch_custom_speed;
616 /* Handle transition from B0 */
617 if (ch->ch_flags & CH_BAUD0) {
618 ch->ch_flags &= ~(CH_BAUD0);
619
620 /*
621 * Bring back up RTS and DTR...
622 * Also handle RTS or DTR toggle if set.
623 */
624 if (!(ch->ch_digi.digi_flags & DIGI_RTS_TOGGLE))
625 ch->ch_mostat |= (UART_MCR_RTS);
626 if (!(ch->ch_digi.digi_flags & DIGI_DTR_TOGGLE))
627 ch->ch_mostat |= (UART_MCR_DTR);
628 }
629 } else {
630 int iindex = 0;
631 int jindex = 0;
632
633 ulong bauds[4][16] = {
634 { /* slowbaud */
635 0, 50, 75, 110,
636 134, 150, 200, 300,
637 600, 1200, 1800, 2400,
638 4800, 9600, 19200, 38400 },
639 { /* slowbaud & CBAUDEX */
640 0, 57600, 115200, 230400,
641 460800, 150, 200, 921600,
642 600, 1200, 1800, 2400,
643 4800, 9600, 19200, 38400 },
644 { /* fastbaud */
645 0, 57600, 76800, 115200,
646 131657, 153600, 230400, 460800,
647 921600, 1200, 1800, 2400,
648 4800, 9600, 19200, 38400 },
649 { /* fastbaud & CBAUDEX */
650 0, 57600, 115200, 230400,
651 460800, 150, 200, 921600,
652 600, 1200, 1800, 2400,
653 4800, 9600, 19200, 38400 }
654 };
655
656 /* Only use the TXPrint baud rate if the terminal unit is NOT open */
6175e73d
DY		 657 if (!(ch->ch_tun.un_flags & UN_ISOPEN) &&
658 (un->un_type == DGNC_PRINT))
0b99d589
LL		 659 baud = C_BAUD(ch->ch_pun.un_tty) & 0xff;
660 else
661 baud = C_BAUD(ch->ch_tun.un_tty) & 0xff;
662
663 if (ch->ch_c_cflag & CBAUDEX)
664 iindex = 1;
665
666 if (ch->ch_digi.digi_flags & DIGI_FAST)
667 iindex += 2;
668
669 jindex = baud;
670
6175e73d
DY		 671 if ((iindex >= 0) && (iindex < 4) &&
672 (jindex >= 0) && (jindex < 16))
5ba5b89a 673 baud = bauds[iindex][jindex];
f1e51745 674 else
0b99d589 675 baud = 0;
0b99d589
LL		 676
677 if (baud == 0)
678 baud = 9600;
679
680 /* Handle transition from B0 */
681 if (ch->ch_flags & CH_BAUD0) {
682 ch->ch_flags &= ~(CH_BAUD0);
683
684 /*
685 * Bring back up RTS and DTR...
686 * Also handle RTS or DTR toggle if set.
687 */
688 if (!(ch->ch_digi.digi_flags & DIGI_RTS_TOGGLE))
689 ch->ch_mostat |= (UART_MCR_RTS);
690 if (!(ch->ch_digi.digi_flags & DIGI_DTR_TOGGLE))
691 ch->ch_mostat |= (UART_MCR_DTR);
692 }
693 }
694
50667c67 695 if (ch->ch_c_cflag & PARENB)
0b99d589 696 lcr |= UART_LCR_PARITY;
0b99d589 697
50667c67 698 if (!(ch->ch_c_cflag & PARODD))
0b99d589 699 lcr |= UART_LCR_EPAR;
0b99d589 700
5ba5b89a 701 /*
0b99d589
LL		 702 * Not all platforms support mark/space parity,
703 * so this will hide behind an ifdef.
704 */
705#ifdef CMSPAR
5ba5b89a 706 if (ch->ch_c_cflag & CMSPAR)
0b99d589
LL		 707 lcr |= UART_LCR_SPAR;
708#endif
709
710 if (ch->ch_c_cflag & CSTOPB)
711 lcr |= UART_LCR_STOP;
712
713 switch (ch->ch_c_cflag & CSIZE) {
714 case CS5:
715 lcr |= UART_LCR_WLEN5;
716 break;
717 case CS6:
718 lcr |= UART_LCR_WLEN6;
719 break;
720 case CS7:
721 lcr |= UART_LCR_WLEN7;
722 break;
723 case CS8:
724 default:
725 lcr |= UART_LCR_WLEN8;
726 break;
727 }
728
587abd7b
SL		 729 uart_ier = readb(&ch->ch_neo_uart->ier);
730 ier = uart_ier;
731
0b99d589
LL		 732 uart_lcr = readb(&ch->ch_neo_uart->lcr);
733
734 if (baud == 0)
735 baud = 9600;
736
737 quot = ch->ch_bd->bd_dividend / baud;
738
739 if (quot != 0 && ch->ch_old_baud != baud) {
740 ch->ch_old_baud = baud;
741 writeb(UART_LCR_DLAB, &ch->ch_neo_uart->lcr);
742 writeb((quot & 0xff), &ch->ch_neo_uart->txrx);
743 writeb((quot >> 8), &ch->ch_neo_uart->ier);
744 writeb(lcr, &ch->ch_neo_uart->lcr);
00804f77 745 }
0b99d589
LL		 746
747 if (uart_lcr != lcr)
748 writeb(lcr, &ch->ch_neo_uart->lcr);
749
50667c67 750 if (ch->ch_c_cflag & CREAD)
0b99d589 751 ier |= (UART_IER_RDI | UART_IER_RLSI);
50667c67 752 else
0b99d589 753 ier &= ~(UART_IER_RDI | UART_IER_RLSI);
0b99d589
LL		 754
755 /*
756 * Have the UART interrupt on modem signal changes ONLY when
757 * we are in hardware flow control mode, or CLOCAL/FORCEDCD is not set.
758 */
33cfbaf5
MN		 759 if ((ch->ch_digi.digi_flags & CTSPACE) ||
760 (ch->ch_digi.digi_flags & RTSPACE) ||
761 (ch->ch_c_cflag & CRTSCTS) ||
762 !(ch->ch_digi.digi_flags & DIGI_FORCEDCD) ||
763 !(ch->ch_c_cflag & CLOCAL))
0b99d589 764 ier |= UART_IER_MSI;
33cfbaf5 765 else
0b99d589 766 ier &= ~UART_IER_MSI;
0b99d589
LL		 767
768 ier |= UART_IER_THRI;
769
770 if (ier != uart_ier)
771 writeb(ier, &ch->ch_neo_uart->ier);
772
773 /* Set new start/stop chars */
774 neo_set_new_start_stop_chars(ch);
775
776 if (ch->ch_digi.digi_flags & CTSPACE || ch->ch_c_cflag & CRTSCTS) {
777 neo_set_cts_flow_control(ch);
2000c581 778 } else if (ch->ch_c_iflag & IXON) {
0b99d589 779 /* If start/stop is set to disable, then we should disable flow control */
6175e73d
DY		 780 if ((ch->ch_startc == _POSIX_VDISABLE) ||
781 (ch->ch_stopc == _POSIX_VDISABLE))
0b99d589
LL		 782 neo_set_no_output_flow_control(ch);
783 else
784 neo_set_ixon_flow_control(ch);
2000c581 785 } else {
0b99d589
LL		 786 neo_set_no_output_flow_control(ch);
787 }
788
789 if (ch->ch_digi.digi_flags & RTSPACE || ch->ch_c_cflag & CRTSCTS) {
790 neo_set_rts_flow_control(ch);
2000c581 791 } else if (ch->ch_c_iflag & IXOFF) {
0b99d589 792 /* If start/stop is set to disable, then we should disable flow control */
6175e73d
DY		 793 if ((ch->ch_startc == _POSIX_VDISABLE) ||
794 (ch->ch_stopc == _POSIX_VDISABLE))
0b99d589
LL		 795 neo_set_no_input_flow_control(ch);
796 else
797 neo_set_ixoff_flow_control(ch);
2000c581 798 } else {
0b99d589
LL		 799 neo_set_no_input_flow_control(ch);
800 }
801
802 /*
803 * Adjust the RX FIFO Trigger level if baud is less than 9600.
804 * Not exactly elegant, but this is needed because of the Exar chip's
805 * delay on firing off the RX FIFO interrupt on slower baud rates.
806 */
807 if (baud < 9600) {
808 writeb(1, &ch->ch_neo_uart->rfifo);
809 ch->ch_r_tlevel = 1;
810 }
811
812 neo_assert_modem_signals(ch);
813
814 /* Get current status of the modem signals now */
815 neo_parse_modem(ch, readb(&ch->ch_neo_uart->msr));
816}
817
0b99d589
LL		 818/*
819 * Our board poller function.
820 */
821static void neo_tasklet(unsigned long data)
822{
6f418259 823 struct dgnc_board *bd = (struct dgnc_board *)data;
0b99d589 824 struct channel_t *ch;
7be869b0 825 unsigned long flags;
0b99d589
LL		 826 int i;
827 int state = 0;
828 int ports = 0;
829
1f26adc9 830 if (!bd || bd->magic != DGNC_BOARD_MAGIC)
0b99d589 831 return;
0b99d589
LL		 832
833 /* Cache a couple board values */
7be869b0 834 spin_lock_irqsave(&bd->bd_lock, flags);
0b99d589
LL		 835 state = bd->state;
836 ports = bd->nasync;
7be869b0 837 spin_unlock_irqrestore(&bd->bd_lock, flags);
0b99d589
LL		 838
839 /*
840 * Do NOT allow the interrupt routine to read the intr registers
841 * Until we release this lock.
842 */
7be869b0 843 spin_lock_irqsave(&bd->bd_intr_lock, flags);
0b99d589
LL		 844
845 /*
846 * If board is ready, parse deeper to see if there is anything to do.
847 */
848 if ((state == BOARD_READY) && (ports > 0)) {
849 /* Loop on each port */
850 for (i = 0; i < ports; i++) {
851 ch = bd->channels[i];
852
853 /* Just being careful... */
854 if (!ch || ch->magic != DGNC_CHANNEL_MAGIC)
855 continue;
856
857 /*
858 * NOTE: Remember you CANNOT hold any channel
859 * locks when calling the input routine.
860 *
861 * During input processing, its possible we
862 * will call the Linux ld, which might in turn,
863 * do a callback right back into us, resulting
864 * in us trying to grab the channel lock twice!
865 */
866 dgnc_input(ch);
867
868 /*
869 * Channel lock is grabbed and then released
870 * inside both of these routines, but neither
871 * call anything else that could call back into us.
872 */
873 neo_copy_data_from_queue_to_uart(ch);
874 dgnc_wakeup_writes(ch);
875
876 /*
877 * Call carrier carrier function, in case something
878 * has changed.
879 */
880 dgnc_carrier(ch);
881
882 /*
883 * Check to see if we need to turn off a sending break.
884 * The timing check is done inside clear_break()
885 */
886 if (ch->ch_stop_sending_break)
887 neo_clear_break(ch, 0);
888 }
889 }
890
891 /* Allow interrupt routine to access the interrupt register again */
7be869b0 892 spin_unlock_irqrestore(&bd->bd_intr_lock, flags);
0b99d589
LL		 893}
894
0b99d589
LL		 895/*
896 * dgnc_neo_intr()
897 *
898 * Neo specific interrupt handler.
899 */
900static irqreturn_t neo_intr(int irq, void *voidbrd)
901{
fc33bd29 902 struct dgnc_board *brd = voidbrd;
0b99d589
LL		 903 struct channel_t *ch;
904 int port = 0;
d8bf4bee 905 int type;
0b99d589 906 u32 uart_poll;
7be869b0
RD		 907 unsigned long flags;
908 unsigned long flags2;
0b99d589 909
0b99d589 910 /*
1f26adc9
RD		 911 * Check to make sure it didn't receive interrupt with a null board
912 * associated or a board pointer that wasn't ours.
0b99d589 913 */
1f26adc9 914 if (!brd || brd->magic != DGNC_BOARD_MAGIC)
0b99d589 915 return IRQ_NONE;
0b99d589 916
0b99d589 917 /* Lock out the slow poller from running on this board. */
7be869b0 918 spin_lock_irqsave(&brd->bd_intr_lock, flags);
0b99d589
LL		 919
920 /*
921 * Read in "extended" IRQ information from the 32bit Neo register.
922 * Bits 0-7: What port triggered the interrupt.
923 * Bits 8-31: Each 3bits indicate what type of interrupt occurred.
924 */
925 uart_poll = readl(brd->re_map_membase + UART_17158_POLL_ADDR_OFFSET);
926
0b99d589
LL		 927 /*
928 * If 0, no interrupts pending.
929 * This can happen if the IRQ is shared among a couple Neo/Classic boards.
930 */
931 if (!uart_poll) {
7be869b0 932 spin_unlock_irqrestore(&brd->bd_intr_lock, flags);
0b99d589
LL		 933 return IRQ_NONE;
934 }
935
936 /* At this point, we have at least SOMETHING to service, dig further... */
937
0b99d589
LL		 938 /* Loop on each port */
939 while ((uart_poll & 0xff) != 0) {
d8bf4bee
DY		 940 type = uart_poll >> (8 + (port * 3));
941 type &= 0x7;
0b99d589 942
d8bf4bee 943 uart_poll &= ~(0x01 << port);
0b99d589
LL		 944
945 /* Switch on type of interrupt we have */
946 switch (type) {
0b99d589
LL		 947 case UART_17158_RXRDY_TIMEOUT:
948 /*
949 * RXRDY Time-out is cleared by reading data in the
00804f77 950 * RX FIFO until it falls below the trigger level.
0b99d589
LL		 951 */
952
953 /* Verify the port is in range. */
4bef52f3 954 if (port >= brd->nasync)
d8bf4bee 955 break;
0b99d589
LL		 956
957 ch = brd->channels[port];
958 neo_copy_data_from_uart_to_queue(ch);
959
960 /* Call our tty layer to enforce queue flow control if needed. */
7be869b0 961 spin_lock_irqsave(&ch->ch_lock, flags2);
0b99d589 962 dgnc_check_queue_flow_control(ch);
7be869b0 963 spin_unlock_irqrestore(&ch->ch_lock, flags2);
0b99d589 964
d8bf4bee 965 break;
0b99d589
LL		 966
967 case UART_17158_RX_LINE_STATUS:
968 /*
969 * RXRDY and RX LINE Status (logic OR of LSR[4:1])
970 */
971 neo_parse_lsr(brd, port);
d8bf4bee 972 break;
0b99d589
LL		 973
974 case UART_17158_TXRDY:
975 /*
976 * TXRDY interrupt clears after reading ISR register for the UART channel.
977 */
978
979 /*
980 * Yes, this is odd...
981 * Why would I check EVERY possibility of type of
982 * interrupt, when we know its TXRDY???
983 * Becuz for some reason, even tho we got triggered for TXRDY,
79e30af2 984 * it seems to be occasionally wrong. Instead of TX, which
0b99d589
LL		 985 * it should be, I was getting things like RXDY too. Weird.
986 */
987 neo_parse_isr(brd, port);
d8bf4bee 988 break;
0b99d589
LL		 989
990 case UART_17158_MSR:
991 /*
992 * MSR or flow control was seen.
993 */
994 neo_parse_isr(brd, port);
d8bf4bee 995 break;
5ba5b89a 996
0b99d589
LL		 997 default:
998 /*
999 * The UART triggered us with a bogus interrupt type.
1000 * It appears the Exar chip, when REALLY bogged down, will throw
1001 * these once and awhile.
1002 * Its harmless, just ignore it and move on.
1003 */
d8bf4bee 1004 break;
0b99d589 1005 }
d8bf4bee
DY		 1006
1007 port++;
0b99d589
LL		 1008 }
1009
1010 /*
1011 * Schedule tasklet to more in-depth servicing at a better time.
1012 */
1013 tasklet_schedule(&brd->helper_tasklet);
1014
7be869b0 1015 spin_unlock_irqrestore(&brd->bd_intr_lock, flags);
0b99d589 1016
0b99d589
LL		 1017 return IRQ_HANDLED;
1018}
1019
0b99d589
LL		 1020/*
1021 * Neo specific way of turning off the receiver.
1022 * Used as a way to enforce queue flow control when in
1023 * hardware flow control mode.
1024 */
1025static void neo_disable_receiver(struct channel_t *ch)
1026{
446393e9 1027 unsigned char tmp = readb(&ch->ch_neo_uart->ier);
1eba3dba 1028
0b99d589
LL		 1029 tmp &= ~(UART_IER_RDI);
1030 writeb(tmp, &ch->ch_neo_uart->ier);
1031 neo_pci_posting_flush(ch->ch_bd);
1032}
1033
0b99d589
LL		 1034/*
1035 * Neo specific way of turning on the receiver.
1036 * Used as a way to un-enforce queue flow control when in
1037 * hardware flow control mode.
1038 */
1039static void neo_enable_receiver(struct channel_t *ch)
1040{
446393e9 1041 unsigned char tmp = readb(&ch->ch_neo_uart->ier);
1eba3dba 1042
0b99d589
LL		 1043 tmp |= (UART_IER_RDI);
1044 writeb(tmp, &ch->ch_neo_uart->ier);
1045 neo_pci_posting_flush(ch->ch_bd);
1046}
1047
0b99d589
LL		 1048static void neo_copy_data_from_uart_to_queue(struct channel_t *ch)
1049{
00804f77 1050 int qleft = 0;
446393e9
EA		 1051 unsigned char linestatus = 0;
1052 unsigned char error_mask = 0;
00804f77
LL		 1053 int n = 0;
1054 int total = 0;
0b99d589
LL		 1055 ushort head;
1056 ushort tail;
7be869b0 1057 unsigned long flags;
0b99d589
LL		 1058
1059 if (!ch || ch->magic != DGNC_CHANNEL_MAGIC)
1060 return;
1061
7be869b0 1062 spin_lock_irqsave(&ch->ch_lock, flags);
0b99d589
LL		 1063
1064 /* cache head and tail of queue */
1065 head = ch->ch_r_head & RQUEUEMASK;
1066 tail = ch->ch_r_tail & RQUEUEMASK;
1067
1068 /* Get our cached LSR */
1069 linestatus = ch->ch_cached_lsr;
1070 ch->ch_cached_lsr = 0;
1071
1072 /* Store how much space we have left in the queue */
f7c851d4
CP		 1073 qleft = tail - head - 1;
1074 if (qleft < 0)
0b99d589
LL		 1075 qleft += RQUEUEMASK + 1;
1076
1077 /*
1078 * If the UART is not in FIFO mode, force the FIFO copy to
1079 * NOT be run, by setting total to 0.
1080 *
1081 * On the other hand, if the UART IS in FIFO mode, then ask
1082 * the UART to give us an approximation of data it has RX'ed.
1083 */
01351494 1084 if (!(ch->ch_flags & CH_FIFO_ENABLED)) {
0b99d589 1085 total = 0;
01351494 1086 } else {
0b99d589
LL		 1087 total = readb(&ch->ch_neo_uart->rfifo);
1088
1089 /*
1090 * EXAR chip bug - RX FIFO COUNT - Fudge factor.
1091 *
1092 * This resolves a problem/bug with the Exar chip that sometimes
1093 * returns a bogus value in the rfifo register.
1094 * The count can be any where from 0-3 bytes "off".
1095 * Bizarre, but true.
1096 */
50667c67 1097 if ((ch->ch_bd->dvid & 0xf0) >= UART_XR17E158_DVID)
0b99d589 1098 total -= 1;
50667c67 1099 else
0b99d589 1100 total -= 3;
0b99d589
LL		 1101 }
1102
0b99d589
LL		 1103 /*
1104 * Finally, bound the copy to make sure we don't overflow
1105 * our own queue...
1106 * The byte by byte copy loop below this loop this will
1107 * deal with the queue overflow possibility.
1108 */
1109 total = min(total, qleft);
1110
5ba5b89a 1111 while (total > 0) {
0b99d589
LL		 1112 /*
1113 * Grab the linestatus register, we need to check
1114 * to see if there are any errors in the FIFO.
1115 */
1116 linestatus = readb(&ch->ch_neo_uart->lsr);
1117
1118 /*
1119 * Break out if there is a FIFO error somewhere.
1120 * This will allow us to go byte by byte down below,
1121 * finding the exact location of the error.
1122 */
1123 if (linestatus & UART_17158_RX_FIFO_DATA_ERROR)
1124 break;
1125
1126 /* Make sure we don't go over the end of our queue */
6f418259 1127 n = min(((uint)total), (RQUEUESIZE - (uint)head));
0b99d589
LL		 1128
1129 /*
1130 * Cut down n even further if needed, this is to fix
1131 * a problem with memcpy_fromio() with the Neo on the
1132 * IBM pSeries platform.
1133 * 15 bytes max appears to be the magic number.
1134 */
a3d81a37 1135 n = min_t(uint, n, 12);
0b99d589
LL		 1136
1137 /*
1138 * Since we are grabbing the linestatus register, which
1139 * will reset some bits after our read, we need to ensure
1140 * we don't miss our TX FIFO emptys.
1141 */
50667c67 1142 if (linestatus & (UART_LSR_THRE | UART_17158_TX_AND_FIFO_CLR))
0b99d589 1143 ch->ch_flags |= (CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM);
0b99d589
LL		 1144
1145 linestatus = 0;
1146
1147 /* Copy data from uart to the queue */
6175e73d
DY		 1148 memcpy_fromio(ch->ch_rqueue + head,
1149 &ch->ch_neo_uart->txrxburst, n);
0b99d589
LL		 1150
1151 /*
69e98df7 1152 * Since RX_FIFO_DATA_ERROR was 0, we are guaranteed
0b99d589
LL		 1153 * that all the data currently in the FIFO is free of
1154 * breaks and parity/frame/orun errors.
1155 */
1156 memset(ch->ch_equeue + head, 0, n);
1157
1158 /* Add to and flip head if needed */
1159 head = (head + n) & RQUEUEMASK;
1160 total -= n;
1161 qleft -= n;
1162 ch->ch_rxcount += n;
1163 }
1164
1165 /*
1166 * Create a mask to determine whether we should
1167 * insert the character (if any) into our queue.
1168 */
1169 if (ch->ch_c_iflag & IGNBRK)
1170 error_mask |= UART_LSR_BI;
1171
1172 /*
1173 * Now cleanup any leftover bytes still in the UART.
1174 * Also deal with any possible queue overflow here as well.
1175 */
1176 while (1) {
0b99d589
LL		 1177 /*
1178 * Its possible we have a linestatus from the loop above
1179 * this, so we "OR" on any extra bits.
1180 */
1181 linestatus |= readb(&ch->ch_neo_uart->lsr);
1182
1183 /*
1184 * If the chip tells us there is no more data pending to
1185 * be read, we can then leave.
1186 * But before we do, cache the linestatus, just in case.
1187 */
1188 if (!(linestatus & UART_LSR_DR)) {
1189 ch->ch_cached_lsr = linestatus;
1190 break;
1191 }
1192
1193 /* No need to store this bit */
1194 linestatus &= ~UART_LSR_DR;
1195
1196 /*
1197 * Since we are grabbing the linestatus register, which
1198 * will reset some bits after our read, we need to ensure
1199 * we don't miss our TX FIFO emptys.
1200 */
1201 if (linestatus & (UART_LSR_THRE | UART_17158_TX_AND_FIFO_CLR)) {
6175e73d
DY		 1202 linestatus &= ~(UART_LSR_THRE |
1203 UART_17158_TX_AND_FIFO_CLR);
0b99d589
LL		 1204 ch->ch_flags |= (CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM);
1205 }
1206
1207 /*
1208 * Discard character if we are ignoring the error mask.
1209 */
1210 if (linestatus & error_mask) {
446393e9 1211 unsigned char discard;
1eba3dba 1212
0b99d589
LL		 1213 linestatus = 0;
1214 memcpy_fromio(&discard, &ch->ch_neo_uart->txrxburst, 1);
1215 continue;
1216 }
1217
1218 /*
1219 * If our queue is full, we have no choice but to drop some data.
1220 * The assumption is that HWFLOW or SWFLOW should have stopped
1221 * things way way before we got to this point.
1222 *
1223 * I decided that I wanted to ditch the oldest data first,
1224 * I hope thats okay with everyone? Yes? Good.
1225 */
1226 while (qleft < 1) {
587abd7b
SL		 1227 tail = (tail + 1) & RQUEUEMASK;
1228 ch->ch_r_tail = tail;
0b99d589
LL		 1229 ch->ch_err_overrun++;
1230 qleft++;
1231 }
1232
6175e73d
DY		 1233 memcpy_fromio(ch->ch_rqueue + head,
1234 &ch->ch_neo_uart->txrxburst, 1);
6f418259 1235 ch->ch_equeue[head] = (unsigned char)linestatus;
0b99d589 1236
0b99d589
LL		 1237 /* Ditch any remaining linestatus value. */
1238 linestatus = 0;
1239
1240 /* Add to and flip head if needed */
1241 head = (head + 1) & RQUEUEMASK;
1242
1243 qleft--;
1244 ch->ch_rxcount++;
1245 }
1246
1247 /*
1248 * Write new final heads to channel structure.
1249 */
1250 ch->ch_r_head = head & RQUEUEMASK;
1251 ch->ch_e_head = head & EQUEUEMASK;
1252
7be869b0 1253 spin_unlock_irqrestore(&ch->ch_lock, flags);
0b99d589
LL		 1254}
1255
0b99d589
LL		 1256/*
1257 * This function basically goes to sleep for secs, or until
1258 * it gets signalled that the port has fully drained.
1259 */
1260static int neo_drain(struct tty_struct *tty, uint seconds)
1261{
7be869b0 1262 unsigned long flags;
0b99d589 1263 struct channel_t *ch;
00804f77 1264 struct un_t *un;
0b99d589
LL		 1265 int rc = 0;
1266
50667c67 1267 if (!tty || tty->magic != TTY_MAGIC)
8f90ef80 1268 return -ENXIO;
0b99d589 1269
6f418259 1270 un = (struct un_t *)tty->driver_data;
50667c67 1271 if (!un || un->magic != DGNC_UNIT_MAGIC)
8f90ef80 1272 return -ENXIO;
0b99d589 1273
5ba5b89a 1274 ch = un->un_ch;
50667c67 1275 if (!ch || ch->magic != DGNC_CHANNEL_MAGIC)
8f90ef80 1276 return -ENXIO;
0b99d589 1277
7be869b0 1278 spin_lock_irqsave(&ch->ch_lock, flags);
0b99d589 1279 un->un_flags |= UN_EMPTY;
7be869b0 1280 spin_unlock_irqrestore(&ch->ch_lock, flags);
0b99d589
LL		 1281
1282 /*
1283 * Go to sleep waiting for the tty layer to wake me back up when
1284 * the empty flag goes away.
0b99d589 1285 */
127bf166
HPGE		 1286 rc = wait_event_interruptible_timeout(un->un_flags_wait,
1287 ((un->un_flags & UN_EMPTY) == 0),
1288 msecs_to_jiffies(seconds * 1000));
0b99d589
LL		 1289
1290 /* If ret is non-zero, user ctrl-c'ed us */
8f90ef80 1291 return rc;
0b99d589 1292}
5ba5b89a 1293
0b99d589
LL		 1294/*
1295 * Flush the WRITE FIFO on the Neo.
1296 *
1297 * NOTE: Channel lock MUST be held before calling this function!
1298 */
1299static void neo_flush_uart_write(struct channel_t *ch)
1300{
446393e9 1301 unsigned char tmp = 0;
0b99d589
LL		 1302 int i = 0;
1303
50667c67 1304 if (!ch || ch->magic != DGNC_CHANNEL_MAGIC)
0b99d589 1305 return;
0b99d589 1306
6175e73d
DY		 1307 writeb((UART_FCR_ENABLE_FIFO | UART_FCR_CLEAR_XMIT),
1308 &ch->ch_neo_uart->isr_fcr);
0b99d589
LL		 1309 neo_pci_posting_flush(ch->ch_bd);
1310
1311 for (i = 0; i < 10; i++) {
0b99d589
LL		 1312 /* Check to see if the UART feels it completely flushed the FIFO. */
1313 tmp = readb(&ch->ch_neo_uart->isr_fcr);
f1e51745 1314 if (tmp & 4)
0b99d589 1315 udelay(10);
f1e51745 1316 else
0b99d589
LL		 1317 break;
1318 }
1319
1320 ch->ch_flags |= (CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM);
1321}
1322
0b99d589
LL		 1323/*
1324 * Flush the READ FIFO on the Neo.
1325 *
1326 * NOTE: Channel lock MUST be held before calling this function!
1327 */
1328static void neo_flush_uart_read(struct channel_t *ch)
1329{
446393e9 1330 unsigned char tmp = 0;
0b99d589
LL		 1331 int i = 0;
1332
50667c67 1333 if (!ch || ch->magic != DGNC_CHANNEL_MAGIC)
0b99d589 1334 return;
0b99d589 1335
a1115c9f 1336 writeb(UART_FCR_ENABLE_FIFO | UART_FCR_CLEAR_RCVR,
6175e73d 1337 &ch->ch_neo_uart->isr_fcr);
0b99d589
LL		 1338 neo_pci_posting_flush(ch->ch_bd);
1339
1340 for (i = 0; i < 10; i++) {
0b99d589
LL		 1341 /* Check to see if the UART feels it completely flushed the FIFO. */
1342 tmp = readb(&ch->ch_neo_uart->isr_fcr);
f1e51745 1343 if (tmp & 2)
0b99d589 1344 udelay(10);
f1e51745 1345 else
0b99d589
LL		 1346 break;
1347 }
1348}
1349
0b99d589
LL		 1350static void neo_copy_data_from_queue_to_uart(struct channel_t *ch)
1351{
1352 ushort head;
1353 ushort tail;
1354 int n;
1355 int s;
1356 int qlen;
1357 uint len_written = 0;
7be869b0 1358 unsigned long flags;
0b99d589
LL		 1359
1360 if (!ch || ch->magic != DGNC_CHANNEL_MAGIC)
1361 return;
1362
7be869b0 1363 spin_lock_irqsave(&ch->ch_lock, flags);
0b99d589
LL		 1364
1365 /* No data to write to the UART */
f6a14cf0
QL		 1366 if (ch->ch_w_tail == ch->ch_w_head)
1367 goto exit_unlock;
0b99d589
LL		 1368
1369 /* If port is "stopped", don't send any data to the UART */
f6a14cf0 1370 if ((ch->ch_flags & CH_FORCED_STOP) ||
e352d3f1 1371 (ch->ch_flags & CH_BREAK_SENDING))
f6a14cf0 1372 goto exit_unlock;
0b99d589
LL		 1373
1374 /*
1375 * If FIFOs are disabled. Send data directly to txrx register
1376 */
1377 if (!(ch->ch_flags & CH_FIFO_ENABLED)) {
446393e9 1378 unsigned char lsrbits = readb(&ch->ch_neo_uart->lsr);
0b99d589
LL		 1379
1380 /* Cache the LSR bits for later parsing */
1381 ch->ch_cached_lsr |= lsrbits;
1382 if (ch->ch_cached_lsr & UART_LSR_THRE) {
1383 ch->ch_cached_lsr &= ~(UART_LSR_THRE);
1384
1385 /*
1386 * If RTS Toggle mode is on, turn on RTS now if not already set,
1387 * and make sure we get an event when the data transfer has completed.
1388 */
1389 if (ch->ch_digi.digi_flags & DIGI_RTS_TOGGLE) {
1390 if (!(ch->ch_mostat & UART_MCR_RTS)) {
1391 ch->ch_mostat |= (UART_MCR_RTS);
1392 neo_assert_modem_signals(ch);
1393 }
1394 ch->ch_tun.un_flags |= (UN_EMPTY);
1395 }
1396 /*
1397 * If DTR Toggle mode is on, turn on DTR now if not already set,
1398 * and make sure we get an event when the data transfer has completed.
1399 */
1400 if (ch->ch_digi.digi_flags & DIGI_DTR_TOGGLE) {
1401 if (!(ch->ch_mostat & UART_MCR_DTR)) {
1402 ch->ch_mostat |= (UART_MCR_DTR);
1403 neo_assert_modem_signals(ch);
1404 }
1405 ch->ch_tun.un_flags |= (UN_EMPTY);
1406 }
1407
6175e73d
DY		 1408 writeb(ch->ch_wqueue[ch->ch_w_tail],
1409 &ch->ch_neo_uart->txrx);
0b99d589
LL		 1410 ch->ch_w_tail++;
1411 ch->ch_w_tail &= WQUEUEMASK;
1412 ch->ch_txcount++;
1413 }
f6a14cf0
QL		 1414
1415 goto exit_unlock;
0b99d589
LL		 1416 }
1417
1418 /*
1419 * We have to do it this way, because of the EXAR TXFIFO count bug.
1420 */
1421 if ((ch->ch_bd->dvid & 0xf0) < UART_XR17E158_DVID) {
f6a14cf0
QL		 1422 if (!(ch->ch_flags & (CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM)))
1423 goto exit_unlock;
0b99d589
LL		 1424
1425 len_written = 0;
1426
1427 n = readb(&ch->ch_neo_uart->tfifo);
1428
6f418259 1429 if ((unsigned int)n > ch->ch_t_tlevel)
f6a14cf0 1430 goto exit_unlock;
0b99d589
LL		 1431
1432 n = UART_17158_TX_FIFOSIZE - ch->ch_t_tlevel;
2000c581 1433 } else {
0b99d589
LL		 1434 n = UART_17158_TX_FIFOSIZE - readb(&ch->ch_neo_uart->tfifo);
1435 }
1436
1437 /* cache head and tail of queue */
1438 head = ch->ch_w_head & WQUEUEMASK;
1439 tail = ch->ch_w_tail & WQUEUEMASK;
1440 qlen = (head - tail) & WQUEUEMASK;
1441
1442 /* Find minimum of the FIFO space, versus queue length */
1443 n = min(n, qlen);
1444
1445 while (n > 0) {
0b99d589
LL		 1446 s = ((head >= tail) ? head : WQUEUESIZE) - tail;
1447 s = min(s, n);
1448
1449 if (s <= 0)
1450 break;
1451
1452 /*
1453 * If RTS Toggle mode is on, turn on RTS now if not already set,
1454 * and make sure we get an event when the data transfer has completed.
1455 */
1456 if (ch->ch_digi.digi_flags & DIGI_RTS_TOGGLE) {
1457 if (!(ch->ch_mostat & UART_MCR_RTS)) {
1458 ch->ch_mostat |= (UART_MCR_RTS);
1459 neo_assert_modem_signals(ch);
1460 }
1461 ch->ch_tun.un_flags |= (UN_EMPTY);
1462 }
1463
1464 /*
1465 * If DTR Toggle mode is on, turn on DTR now if not already set,
1466 * and make sure we get an event when the data transfer has completed.
1467 */
1468 if (ch->ch_digi.digi_flags & DIGI_DTR_TOGGLE) {
1469 if (!(ch->ch_mostat & UART_MCR_DTR)) {
1470 ch->ch_mostat |= (UART_MCR_DTR);
1471 neo_assert_modem_signals(ch);
1472 }
1473 ch->ch_tun.un_flags |= (UN_EMPTY);
1474 }
1475
6175e73d
DY		 1476 memcpy_toio(&ch->ch_neo_uart->txrxburst,
1477 ch->ch_wqueue + tail, s);
0b99d589
LL		 1478
1479 /* Add and flip queue if needed */
1480 tail = (tail + s) & WQUEUEMASK;
1481 n -= s;
1482 ch->ch_txcount += s;
1483 len_written += s;
1484 }
1485
1486 /* Update the final tail */
1487 ch->ch_w_tail = tail & WQUEUEMASK;
1488
1489 if (len_written > 0) {
1490 neo_pci_posting_flush(ch->ch_bd);
1491 ch->ch_flags &= ~(CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM);
1492 }
1493
f6a14cf0 1494exit_unlock:
7be869b0 1495 spin_unlock_irqrestore(&ch->ch_lock, flags);
0b99d589
LL		 1496}
1497
446393e9 1498static void neo_parse_modem(struct channel_t *ch, unsigned char signals)
0b99d589 1499{
446393e9 1500 unsigned char msignals = signals;
0b99d589
LL		 1501
1502 if (!ch || ch->magic != DGNC_CHANNEL_MAGIC)
1503 return;
1504
0b99d589
LL		 1505 /*
1506 * Do altpin switching. Altpin switches DCD and DSR.
1507 * This prolly breaks DSRPACE, so we should be more clever here.
1508 */
1509 if (ch->ch_digi.digi_flags & DIGI_ALTPIN) {
446393e9 1510 unsigned char mswap = msignals;
0b99d589
LL		 1511
1512 if (mswap & UART_MSR_DDCD) {
1513 msignals &= ~UART_MSR_DDCD;
1514 msignals |= UART_MSR_DDSR;
1515 }
1516 if (mswap & UART_MSR_DDSR) {
1517 msignals &= ~UART_MSR_DDSR;
1518 msignals |= UART_MSR_DDCD;
1519 }
1520 if (mswap & UART_MSR_DCD) {
1521 msignals &= ~UART_MSR_DCD;
1522 msignals |= UART_MSR_DSR;
1523 }
1524 if (mswap & UART_MSR_DSR) {
1525 msignals &= ~UART_MSR_DSR;
1526 msignals |= UART_MSR_DCD;
1527 }
1528 }
1529
1530 /* Scrub off lower bits. They signify delta's, which I don't care about */
1531 msignals &= 0xf0;
1532
1533 if (msignals & UART_MSR_DCD)
1534 ch->ch_mistat |= UART_MSR_DCD;
1535 else
1536 ch->ch_mistat &= ~UART_MSR_DCD;
1537
1538 if (msignals & UART_MSR_DSR)
1539 ch->ch_mistat |= UART_MSR_DSR;
1540 else
1541 ch->ch_mistat &= ~UART_MSR_DSR;
1542
1543 if (msignals & UART_MSR_RI)
1544 ch->ch_mistat |= UART_MSR_RI;
1545 else
1546 ch->ch_mistat &= ~UART_MSR_RI;
1547
1548 if (msignals & UART_MSR_CTS)
1549 ch->ch_mistat |= UART_MSR_CTS;
1550 else
1551 ch->ch_mistat &= ~UART_MSR_CTS;
0b99d589
LL		 1552}
1553
0b99d589
LL		 1554/* Make the UART raise any of the output signals we want up */
1555static void neo_assert_modem_signals(struct channel_t *ch)
1556{
446393e9 1557 unsigned char out;
0b99d589
LL		 1558
1559 if (!ch || ch->magic != DGNC_CHANNEL_MAGIC)
1560 return;
1561
1562 out = ch->ch_mostat;
1563
1564 if (ch->ch_flags & CH_LOOPBACK)
1565 out |= UART_MCR_LOOP;
1566
1567 writeb(out, &ch->ch_neo_uart->mcr);
1568 neo_pci_posting_flush(ch->ch_bd);
1569
1570 /* Give time for the UART to actually raise/drop the signals */
1571 udelay(10);
1572}
1573
0b99d589
LL		 1574static void neo_send_start_character(struct channel_t *ch)
1575{
1576 if (!ch || ch->magic != DGNC_CHANNEL_MAGIC)
1577 return;
1578
1579 if (ch->ch_startc != _POSIX_VDISABLE) {
1580 ch->ch_xon_sends++;
1581 writeb(ch->ch_startc, &ch->ch_neo_uart->txrx);
1582 neo_pci_posting_flush(ch->ch_bd);
1583 udelay(10);
1584 }
1585}
1586
0b99d589
LL		 1587static void neo_send_stop_character(struct channel_t *ch)
1588{
1589 if (!ch || ch->magic != DGNC_CHANNEL_MAGIC)
1590 return;
1591
1592 if (ch->ch_stopc != _POSIX_VDISABLE) {
1593 ch->ch_xoff_sends++;
1594 writeb(ch->ch_stopc, &ch->ch_neo_uart->txrx);
1595 neo_pci_posting_flush(ch->ch_bd);
1596 udelay(10);
1597 }
1598}
1599
0b99d589
LL		 1600/*
1601 * neo_uart_init
1602 */
1603static void neo_uart_init(struct channel_t *ch)
1604{
0b99d589
LL		 1605 writeb(0, &ch->ch_neo_uart->ier);
1606 writeb(0, &ch->ch_neo_uart->efr);
1607 writeb(UART_EFR_ECB, &ch->ch_neo_uart->efr);
5ba5b89a 1608
00804f77 1609 /* Clear out UART and FIFO */
0b99d589 1610 readb(&ch->ch_neo_uart->txrx);
a1115c9f 1611 writeb(UART_FCR_ENABLE_FIFO | UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT,
6175e73d 1612 &ch->ch_neo_uart->isr_fcr);
0b99d589
LL		 1613 readb(&ch->ch_neo_uart->lsr);
1614 readb(&ch->ch_neo_uart->msr);
1615
1616 ch->ch_flags |= CH_FIFO_ENABLED;
1617
1618 /* Assert any signals we want up */
1619 writeb(ch->ch_mostat, &ch->ch_neo_uart->mcr);
1620 neo_pci_posting_flush(ch->ch_bd);
1621}
1622
0b99d589
LL		 1623/*
1624 * Make the UART completely turn off.
1625 */
1626static void neo_uart_off(struct channel_t *ch)
1627{
1628 /* Turn off UART enhanced bits */
1629 writeb(0, &ch->ch_neo_uart->efr);
1630
1631 /* Stop all interrupts from occurring. */
1632 writeb(0, &ch->ch_neo_uart->ier);
1633 neo_pci_posting_flush(ch->ch_bd);
1634}
1635
0b99d589
LL		 1636static uint neo_get_uart_bytes_left(struct channel_t *ch)
1637{
446393e9
EA		 1638 unsigned char left = 0;
1639 unsigned char lsr = readb(&ch->ch_neo_uart->lsr);
0b99d589
LL		 1640
1641 /* We must cache the LSR as some of the bits get reset once read... */
1642 ch->ch_cached_lsr |= lsr;
5ba5b89a 1643
0b99d589
LL		 1644 /* Determine whether the Transmitter is empty or not */
1645 if (!(lsr & UART_LSR_TEMT)) {
13d1773a 1646 if (ch->ch_flags & CH_TX_FIFO_EMPTY)
00804f77 1647 tasklet_schedule(&ch->ch_bd->helper_tasklet);
0b99d589
LL		 1648 left = 1;
1649 } else {
1650 ch->ch_flags |= (CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM);
1651 left = 0;
1652 }
1653
1654 return left;
1655}
1656
0b99d589
LL		 1657/* Channel lock MUST be held by the calling function! */
1658static void neo_send_break(struct channel_t *ch, int msecs)
1659{
1660 /*
1661 * If we receive a time of 0, this means turn off the break.
1662 */
1663 if (msecs == 0) {
1664 if (ch->ch_flags & CH_BREAK_SENDING) {
446393e9 1665 unsigned char temp = readb(&ch->ch_neo_uart->lcr);
1eba3dba 1666
0b99d589
LL		 1667 writeb((temp & ~UART_LCR_SBC), &ch->ch_neo_uart->lcr);
1668 neo_pci_posting_flush(ch->ch_bd);
1669 ch->ch_flags &= ~(CH_BREAK_SENDING);
1670 ch->ch_stop_sending_break = 0;
0b99d589
LL		 1671 }
1672 return;
1673 }
1674
1675 /*
1676 * Set the time we should stop sending the break.
1677 * If we are already sending a break, toss away the existing
1678 * time to stop, and use this new value instead.
1679 */
1680 ch->ch_stop_sending_break = jiffies + dgnc_jiffies_from_ms(msecs);
1681
1682 /* Tell the UART to start sending the break */
1683 if (!(ch->ch_flags & CH_BREAK_SENDING)) {
446393e9 1684 unsigned char temp = readb(&ch->ch_neo_uart->lcr);
5ef33f38 1685
00804f77 1686 writeb((temp | UART_LCR_SBC), &ch->ch_neo_uart->lcr);
0b99d589
LL		 1687 neo_pci_posting_flush(ch->ch_bd);
1688 ch->ch_flags |= (CH_BREAK_SENDING);
00804f77 1689 }
0b99d589
LL		 1690}
1691
0b99d589
LL		 1692/*
1693 * neo_send_immediate_char.
1694 *
5ba5b89a 1695 * Sends a specific character as soon as possible to the UART,
0b99d589
LL		 1696 * jumping over any bytes that might be in the write queue.
1697 *
1698 * The channel lock MUST be held by the calling function.
1699 */
1700static void neo_send_immediate_char(struct channel_t *ch, unsigned char c)
1701{
1702 if (!ch || ch->magic != DGNC_CHANNEL_MAGIC)
1703 return;
1704
1705 writeb(c, &ch->ch_neo_uart->txrx);
1706 neo_pci_posting_flush(ch->ch_bd);
1707}
1708
6175e73d
DY		 1709static unsigned int neo_read_eeprom(unsigned char __iomem *base,
1710 unsigned int address)
0b99d589
LL		 1711{
1712 unsigned int enable;
1713 unsigned int bits;
1714 unsigned int databit;
1715 unsigned int val;
1716
1717 /* enable chip select */
1718 writeb(NEO_EECS, base + NEO_EEREG);
1719 /* READ */
0b7ceaa6 1720 enable = address | 0x180;
0b99d589
LL		 1721
1722 for (bits = 9; bits--; ) {
1723 databit = (enable & (1 << bits)) ? NEO_EEDI : 0;
1724 /* Set read address */
1725 writeb(databit | NEO_EECS, base + NEO_EEREG);
1726 writeb(databit | NEO_EECS | NEO_EECK, base + NEO_EEREG);
1727 }
1728
1729 val = 0;
1730
1731 for (bits = 17; bits--; ) {
1732 /* clock to EEPROM */
1733 writeb(NEO_EECS, base + NEO_EEREG);
1734 writeb(NEO_EECS | NEO_EECK, base + NEO_EEREG);
1735 val <<= 1;
1736 /* read EEPROM */
1737 if (readb(base + NEO_EEREG) & NEO_EEDO)
1738 val |= 1;
1739 }
1740
1741 /* clock falling edge */
1742 writeb(NEO_EECS, base + NEO_EEREG);
1743
1744 /* drop chip select */
1745 writeb(0x00, base + NEO_EEREG);
1746
1747 return val;
1748}
1749
03425f55 1750static void neo_vpd(struct dgnc_board *brd)
0b99d589
LL		 1751{
1752 unsigned int i = 0;
1753 unsigned int a;
1754
1755 if (!brd || brd->magic != DGNC_BOARD_MAGIC)
1756 return;
1757
1758 if (!brd->re_map_membase)
1759 return;
1760
1761 /* Store the VPD into our buffer */
1762 for (i = 0; i < NEO_VPD_IMAGESIZE; i++) {
1763 a = neo_read_eeprom(brd->re_map_membase, i);
5bff5d9f
BS		 1764 brd->vpd[i * 2] = a & 0xff;
1765 brd->vpd[(i * 2) + 1] = (a >> 8) & 0xff;
0b99d589
LL		 1766 }
1767
ffe4f329
DY		 1768 /*
1769 * brd->vpd has different name tags by below index.
1770 * 0x08 : long resource name tag
1771 * 0x10 : long resource name tage (PCI-66 files)
1772 * 0x7F : small resource end tag
1773 */
3996ae34
DY		 1774 if (((brd->vpd[0x08] != 0x82) &&
1775 (brd->vpd[0x10] != 0x82)) ||
1776 (brd->vpd[0x7F] != 0x78)) {
0b99d589 1777 memset(brd->vpd, '\0', NEO_VPD_IMAGESIZE);
2000c581 1778 } else {
0b99d589 1779 /* Search for the serial number */
50667c67
MN		 1780 for (i = 0; i < NEO_VPD_IMAGEBYTES - 3; i++)
1781 if (brd->vpd[i] == 'S' && brd->vpd[i + 1] == 'N')
7df227c4 1782 strncpy(brd->serial_num, &brd->vpd[i + 3], 9);
0b99d589
LL		 1783 }
1784}
Linux kernel - Deliverables
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