projects / deliverable / linux.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
Merge branch 'exynos-drm-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git...
[deliverable/linux.git] / drivers / staging / emxx_udc / emxx_udc.c
CommitLineData
33aa8d45
MD		 1/*
2 * drivers/usb/gadget/emxx_udc.c
3 * EMXX FCD (Function Controller Driver) for USB.
4 *
5 * Copyright (C) 2010 Renesas Electronics Corporation
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2
9 * as published by the Free Software Foundation.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
33aa8d45
MD		 15 */
16
17#include <linux/kernel.h>
0af61e66 18#include <linux/init.h>
33aa8d45
MD		 19#include <linux/platform_device.h>
20#include <linux/delay.h>
21#include <linux/ioport.h>
22#include <linux/slab.h>
23#include <linux/errno.h>
24#include <linux/init.h>
25#include <linux/list.h>
26#include <linux/interrupt.h>
27#include <linux/proc_fs.h>
28#include <linux/clk.h>
29#include <linux/ctype.h>
30#include <linux/string.h>
31#include <linux/dma-mapping.h>
32#include <linux/workqueue.h>
a790ebc1 33#include <linux/device.h>
33aa8d45
MD		 34
35#include <linux/usb/ch9.h>
36#include <linux/usb/gadget.h>
37
38#include <linux/irq.h>
39#include <linux/gpio.h>
40
41#include "emxx_udc.h"
42
33aa8d45
MD		 43#define DMA_ADDR_INVALID (~(dma_addr_t)0)
44
45static const char driver_name[] = "emxx_udc";
33aa8d45
MD		 46
47/*===========================================================================*/
48/* Prototype */
49static void _nbu2ss_ep_dma_abort(struct nbu2ss_udc *, struct nbu2ss_ep *);
50static void _nbu2ss_ep0_enable(struct nbu2ss_udc *);
51/*static void _nbu2ss_ep0_disable(struct nbu2ss_udc *);*/
52static void _nbu2ss_ep_done(struct nbu2ss_ep *, struct nbu2ss_req *, int);
53static void _nbu2ss_set_test_mode(struct nbu2ss_udc *, u32 mode);
54static void _nbu2ss_endpoint_toggle_reset(struct nbu2ss_udc *udc, u8 ep_adrs);
55
56static int _nbu2ss_pullup(struct nbu2ss_udc *, int);
57static void _nbu2ss_fifo_flush(struct nbu2ss_udc *, struct nbu2ss_ep *);
58
59/*===========================================================================*/
60/* Macro */
61#define _nbu2ss_zero_len_pkt(udc, epnum) \
62 _nbu2ss_ep_in_end(udc, epnum, 0, 0)
63
33aa8d45
MD		 64/*===========================================================================*/
65/* Global */
66struct nbu2ss_udc udc_controller;
67
33aa8d45
MD		 68/*-------------------------------------------------------------------------*/
69/* Read */
70static inline u32 _nbu2ss_readl(void *address)
71{
ce1e3eb7 72 return __raw_readl(address);
33aa8d45
MD		 73}
74
75/*-------------------------------------------------------------------------*/
76/* Write */
77static inline void _nbu2ss_writel(void *address, u32 udata)
78{
ce1e3eb7 79 __raw_writel(udata, address);
33aa8d45
MD		 80}
81
82/*-------------------------------------------------------------------------*/
83/* Set Bit */
84static inline void _nbu2ss_bitset(void *address, u32 udata)
85{
86 u32 reg_dt = __raw_readl(address) | (udata);
7f39ae05 87
ce1e3eb7 88 __raw_writel(reg_dt, address);
33aa8d45
MD		 89}
90
91/*-------------------------------------------------------------------------*/
92/* Clear Bit */
93static inline void _nbu2ss_bitclr(void *address, u32 udata)
94{
95 u32 reg_dt = __raw_readl(address) & ~(udata);
7f39ae05 96
ce1e3eb7 97 __raw_writel(reg_dt, address);
33aa8d45
MD		 98}
99
100#ifdef UDC_DEBUG_DUMP
101/*-------------------------------------------------------------------------*/
102static void _nbu2ss_dump_register(struct nbu2ss_udc *udc)
103{
104 int i;
105 u32 reg_data;
106
107 pr_info("=== %s()\n", __func__);
108
706eb8cf 109 if (!udc) {
88689279 110 pr_err("%s udc == NULL\n", __func__);
33aa8d45
MD		 111 return;
112 }
113
114 spin_unlock(&udc->lock);
115
fb71d24b 116 dev_dbg(&udc->dev, "\n-USB REG-\n");
33aa8d45
MD		 117 for (i = 0x0 ; i < USB_BASE_SIZE ; i += 16) {
118 reg_data = _nbu2ss_readl(
119 (u32 *)IO_ADDRESS(USB_BASE_ADDRESS + i));
fb71d24b 120 dev_dbg(&udc->dev, "USB%04x =%08x", i, (int)reg_data);
33aa8d45
MD		 121
122 reg_data = _nbu2ss_readl(
123 (u32 *)IO_ADDRESS(USB_BASE_ADDRESS + i + 4));
fb71d24b 124 dev_dbg(&udc->dev, " %08x", (int)reg_data);
33aa8d45
MD		 125
126 reg_data = _nbu2ss_readl(
127 (u32 *)IO_ADDRESS(USB_BASE_ADDRESS + i + 8));
fb71d24b 128 dev_dbg(&udc->dev, " %08x", (int)reg_data);
33aa8d45
MD		 129
130 reg_data = _nbu2ss_readl(
131 (u32 *)IO_ADDRESS(USB_BASE_ADDRESS + i + 12));
fb71d24b 132 dev_dbg(&udc->dev, " %08x\n", (int)reg_data);
33aa8d45
MD		 133
134 }
135
136 spin_lock(&udc->lock);
137}
138#endif /* UDC_DEBUG_DUMP */
139
140/*-------------------------------------------------------------------------*/
141/* Endpoint 0 Callback (Complete) */
142static void _nbu2ss_ep0_complete(struct usb_ep *_ep, struct usb_request *_req)
143{
144 u8 recipient;
145 u16 selector;
146 u32 test_mode;
147 struct usb_ctrlrequest *p_ctrl;
148 struct nbu2ss_udc *udc;
149
706eb8cf 150 if ((!_ep) || (!_req))
33aa8d45
MD		 151 return;
152
153 udc = (struct nbu2ss_udc *)_req->context;
154 p_ctrl = &udc->ctrl;
155 if ((p_ctrl->bRequestType & USB_TYPE_MASK) == USB_TYPE_STANDARD) {
156
157 if (p_ctrl->bRequest == USB_REQ_SET_FEATURE) {
158 /*-------------------------------------------------*/
159 /* SET_FEATURE */
160 recipient = (u8)(p_ctrl->bRequestType & USB_RECIP_MASK);
161 selector = p_ctrl->wValue;
162 if ((recipient == USB_RECIP_DEVICE) &&
163 (selector == USB_DEVICE_TEST_MODE)) {
164 test_mode = (u32)(p_ctrl->wIndex >> 8);
165 _nbu2ss_set_test_mode(udc, test_mode);
166 }
167 }
168 }
169}
170
171/*-------------------------------------------------------------------------*/
172/* Initialization usb_request */
173static void _nbu2ss_create_ep0_packet(
174 struct nbu2ss_udc *udc,
175 void *p_buf,
176 unsigned length
177)
178{
179 udc->ep0_req.req.buf = p_buf;
180 udc->ep0_req.req.length = length;
181 udc->ep0_req.req.dma = 0;
182 udc->ep0_req.req.zero = TRUE;
183 udc->ep0_req.req.complete = _nbu2ss_ep0_complete;
184 udc->ep0_req.req.status = -EINPROGRESS;
185 udc->ep0_req.req.context = udc;
186 udc->ep0_req.req.actual = 0;
187}
188
189/*-------------------------------------------------------------------------*/
190/* Acquisition of the first address of RAM(FIFO) */
191static u32 _nbu2ss_get_begin_ram_address(struct nbu2ss_udc *udc)
192{
193 u32 num, buf_type;
194 u32 data, last_ram_adr, use_ram_size;
195
f6ef6c09 196 struct ep_regs *p_ep_regs;
33aa8d45
MD		 197
198 last_ram_adr = (D_RAM_SIZE_CTRL / sizeof(u32)) * 2;
199 use_ram_size = 0;
200
201 for (num = 0; num < NUM_ENDPOINTS - 1; num++) {
202 p_ep_regs = &udc->p_regs->EP_REGS[num];
203 data = _nbu2ss_readl(&p_ep_regs->EP_PCKT_ADRS);
204 buf_type = _nbu2ss_readl(&p_ep_regs->EP_CONTROL) & EPn_BUF_TYPE;
205 if (buf_type == 0) {
206 /* Single Buffer */
207 use_ram_size += (data & EPn_MPKT) / sizeof(u32);
208 } else {
209 /* Double Buffer */
210 use_ram_size += ((data & EPn_MPKT) / sizeof(u32)) * 2;
211 }
212
213 if ((data >> 16) > last_ram_adr)
ba57f5fa 214 last_ram_adr = data >> 16;
33aa8d45
MD		 215 }
216
217 return last_ram_adr + use_ram_size;
218}
219
220/*-------------------------------------------------------------------------*/
221/* Construction of Endpoint */
222static int _nbu2ss_ep_init(struct nbu2ss_udc *udc, struct nbu2ss_ep *ep)
223{
224 u32 num;
225 u32 data;
226 u32 begin_adrs;
227
228 if (ep->epnum == 0)
229 return -EINVAL;
230
231 num = ep->epnum - 1;
232
233 /*-------------------------------------------------------------*/
234 /* RAM Transfer Address */
235 begin_adrs = _nbu2ss_get_begin_ram_address(udc);
236 data = (begin_adrs << 16) | ep->ep.maxpacket;
237 _nbu2ss_writel(&udc->p_regs->EP_REGS[num].EP_PCKT_ADRS, data);
238
239 /*-------------------------------------------------------------*/
240 /* Interrupt Enable */
241 data = 1 << (ep->epnum + 8);
242 _nbu2ss_bitset(&udc->p_regs->USB_INT_ENA, data);
243
244 /*-------------------------------------------------------------*/
245 /* Endpoint Type(Mode) */
246 /* Bulk, Interrupt, ISO */
247 switch (ep->ep_type) {
248 case USB_ENDPOINT_XFER_BULK:
249 data = EPn_BULK;
250 break;
251
252 case USB_ENDPOINT_XFER_INT:
253 data = EPn_BUF_SINGLE | EPn_INTERRUPT;
254 break;
255
256 case USB_ENDPOINT_XFER_ISOC:
257 data = EPn_ISO;
258 break;
259
260 default:
261 data = 0;
262 break;
263 }
264
265 _nbu2ss_bitset(&udc->p_regs->EP_REGS[num].EP_CONTROL, data);
266 _nbu2ss_endpoint_toggle_reset(udc, (ep->epnum|ep->direct));
267
268 if (ep->direct == USB_DIR_OUT) {
269 /*---------------------------------------------------------*/
270 /* OUT */
271 data = EPn_EN | EPn_BCLR | EPn_DIR0;
272 _nbu2ss_bitset(&udc->p_regs->EP_REGS[num].EP_CONTROL, data);
273
274 data = (EPn_ONAK | EPn_OSTL_EN | EPn_OSTL);
275 _nbu2ss_bitclr(&udc->p_regs->EP_REGS[num].EP_CONTROL, data);
276
277 data = (EPn_OUT_EN | EPn_OUT_END_EN);
278 _nbu2ss_bitset(&udc->p_regs->EP_REGS[num].EP_INT_ENA, data);
279 } else {
280 /*---------------------------------------------------------*/
281 /* IN */
282 data = (EPn_EN | EPn_BCLR | EPn_AUTO);
283 _nbu2ss_bitset(&udc->p_regs->EP_REGS[num].EP_CONTROL, data);
284
285 data = (EPn_ISTL);
286 _nbu2ss_bitclr(&udc->p_regs->EP_REGS[num].EP_CONTROL, data);
287
288 data = (EPn_IN_EN | EPn_IN_END_EN);
289 _nbu2ss_bitset(&udc->p_regs->EP_REGS[num].EP_INT_ENA, data);
290 }
291
292 return 0;
293}
294
295/*-------------------------------------------------------------------------*/
296/* Release of Endpoint */
297static int _nbu2ss_epn_exit(struct nbu2ss_udc *udc, struct nbu2ss_ep *ep)
298{
299 u32 num;
300 u32 data;
301
302 if ((ep->epnum == 0) || (udc->vbus_active == 0))
303 return -EINVAL;
304
305 num = ep->epnum - 1;
306
307 /*-------------------------------------------------------------*/
308 /* RAM Transfer Address */
309 _nbu2ss_writel(&udc->p_regs->EP_REGS[num].EP_PCKT_ADRS, 0);
310
311 /*-------------------------------------------------------------*/
312 /* Interrupt Disable */
313 data = 1 << (ep->epnum + 8);
314 _nbu2ss_bitclr(&udc->p_regs->USB_INT_ENA, data);
315
316 if (ep->direct == USB_DIR_OUT) {
317 /*---------------------------------------------------------*/
318 /* OUT */
319 data = EPn_ONAK | EPn_BCLR;
320 _nbu2ss_bitset(&udc->p_regs->EP_REGS[num].EP_CONTROL, data);
321
322 data = EPn_EN | EPn_DIR0;
323 _nbu2ss_bitclr(&udc->p_regs->EP_REGS[num].EP_CONTROL, data);
324
325 data = EPn_OUT_EN | EPn_OUT_END_EN;
326 _nbu2ss_bitclr(&udc->p_regs->EP_REGS[num].EP_INT_ENA, data);
327 } else {
328 /*---------------------------------------------------------*/
329 /* IN */
330 data = EPn_BCLR;
331 _nbu2ss_bitset(&udc->p_regs->EP_REGS[num].EP_CONTROL, data);
332
333 data = EPn_EN | EPn_AUTO;
334 _nbu2ss_bitclr(&udc->p_regs->EP_REGS[num].EP_CONTROL, data);
335
336 data = EPn_IN_EN | EPn_IN_END_EN;
337 _nbu2ss_bitclr(&udc->p_regs->EP_REGS[num].EP_INT_ENA, data);
338 }
339
340 return 0;
341}
342
343/*-------------------------------------------------------------------------*/
344/* DMA setting (without Endpoint 0) */
345static void _nbu2ss_ep_dma_init(struct nbu2ss_udc *udc, struct nbu2ss_ep *ep)
346{
347 u32 num;
348 u32 data;
349
350 data = _nbu2ss_readl(&udc->p_regs->USBSSCONF);
351 if (((ep->epnum == 0) || (data & (1 << ep->epnum)) == 0))
352 return; /* Not Support DMA */
353
354 num = ep->epnum - 1;
355
356 if (ep->direct == USB_DIR_OUT) {
357 /*---------------------------------------------------------*/
358 /* OUT */
359 data = ep->ep.maxpacket;
360 _nbu2ss_writel(&udc->p_regs->EP_DCR[num].EP_DCR2, data);
361
362 /*---------------------------------------------------------*/
363 /* Transfer Direct */
364 data = DCR1_EPn_DIR0;
365 _nbu2ss_bitset(&udc->p_regs->EP_DCR[num].EP_DCR1, data);
366
367 /*---------------------------------------------------------*/
368 /* DMA Mode etc. */
369 data = EPn_STOP_MODE | EPn_STOP_SET | EPn_DMAMODE0;
370 _nbu2ss_writel(&udc->p_regs->EP_REGS[num].EP_DMA_CTRL, data);
371 } else {
372 /*---------------------------------------------------------*/
373 /* IN */
374 _nbu2ss_bitset(&udc->p_regs->EP_REGS[num].EP_CONTROL, EPn_AUTO);
375
376 /*---------------------------------------------------------*/
377 /* DMA Mode etc. */
378 data = EPn_BURST_SET | EPn_DMAMODE0;
379 _nbu2ss_writel(&udc->p_regs->EP_REGS[num].EP_DMA_CTRL, data);
380 }
381}
382
383/*-------------------------------------------------------------------------*/
384/* DMA setting release */
385static void _nbu2ss_ep_dma_exit(struct nbu2ss_udc *udc, struct nbu2ss_ep *ep)
386{
387 u32 num;
388 u32 data;
f6ef6c09 389 struct fc_regs *preg = udc->p_regs;
33aa8d45
MD		 390
391 if (udc->vbus_active == 0)
392 return; /* VBUS OFF */
393
394 data = _nbu2ss_readl(&preg->USBSSCONF);
395 if ((ep->epnum == 0) || ((data & (1 << ep->epnum)) == 0))
396 return; /* Not Support DMA */
397
398 num = ep->epnum - 1;
399
400 _nbu2ss_ep_dma_abort(udc, ep);
401
402 if (ep->direct == USB_DIR_OUT) {
403 /*---------------------------------------------------------*/
404 /* OUT */
405 _nbu2ss_writel(&preg->EP_DCR[num].EP_DCR2, 0);
406 _nbu2ss_bitclr(&preg->EP_DCR[num].EP_DCR1, DCR1_EPn_DIR0);
407 _nbu2ss_writel(&preg->EP_REGS[num].EP_DMA_CTRL, 0);
408 } else {
409 /*---------------------------------------------------------*/
410 /* IN */
411 _nbu2ss_bitclr(&preg->EP_REGS[num].EP_CONTROL, EPn_AUTO);
412 _nbu2ss_writel(&preg->EP_REGS[num].EP_DMA_CTRL, 0);
413 }
414}
415
416/*-------------------------------------------------------------------------*/
417/* Abort DMA */
418static void _nbu2ss_ep_dma_abort(struct nbu2ss_udc *udc, struct nbu2ss_ep *ep)
419{
f6ef6c09 420 struct fc_regs *preg = udc->p_regs;
33aa8d45
MD		 421
422 _nbu2ss_bitclr(&preg->EP_DCR[ep->epnum-1].EP_DCR1, DCR1_EPn_REQEN);
423 mdelay(DMA_DISABLE_TIME); /* DCR1_EPn_REQEN Clear */
424 _nbu2ss_bitclr(&preg->EP_REGS[ep->epnum-1].EP_DMA_CTRL, EPn_DMA_EN);
425}
426
427/*-------------------------------------------------------------------------*/
428/* Start IN Transfer */
429static void _nbu2ss_ep_in_end(
430 struct nbu2ss_udc *udc,
431 u32 epnum,
432 u32 data32,
433 u32 length
434)
435{
436 u32 data;
437 u32 num;
f6ef6c09 438 struct fc_regs *preg = udc->p_regs;
33aa8d45
MD		 439
440 if (length >= sizeof(u32))
441 return;
442
443 if (epnum == 0) {
444 _nbu2ss_bitclr(&preg->EP0_CONTROL, EP0_AUTO);
445
446 /* Writing of 1-4 bytes */
447 if (length)
448 _nbu2ss_writel(&preg->EP0_WRITE, data32);
449
450 data = ((length << 5) & EP0_DW) | EP0_DEND;
451 _nbu2ss_writel(&preg->EP0_CONTROL, data);
452
453 _nbu2ss_bitset(&preg->EP0_CONTROL, EP0_AUTO);
454 } else {
455 num = epnum - 1;
456
457 _nbu2ss_bitclr(&preg->EP_REGS[num].EP_CONTROL, EPn_AUTO);
458
459 /* Writing of 1-4 bytes */
460 if (length)
461 _nbu2ss_writel(&preg->EP_REGS[num].EP_WRITE, data32);
462
463 data = (((((u32)length) << 5) & EPn_DW) | EPn_DEND);
464 _nbu2ss_bitset(&preg->EP_REGS[num].EP_CONTROL, data);
465
466 _nbu2ss_bitset(&preg->EP_REGS[num].EP_CONTROL, EPn_AUTO);
467 }
33aa8d45
MD		 468}
469
470#ifdef USE_DMA
471/*-------------------------------------------------------------------------*/
472static void _nbu2ss_dma_map_single(
473 struct nbu2ss_udc *udc,
474 struct nbu2ss_ep *ep,
475 struct nbu2ss_req *req,
476 u8 direct
477)
478{
479 if (req->req.dma == DMA_ADDR_INVALID) {
480 if (req->unaligned)
481 req->req.dma = ep->phys_buf;
482 else {
483 req->req.dma = dma_map_single(
484 udc->gadget.dev.parent,
485 req->req.buf,
486 req->req.length,
487 (direct == USB_DIR_IN)
488 ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
489 }
490 req->mapped = 1;
491 } else {
492 if (!req->unaligned)
493 dma_sync_single_for_device(
494 udc->gadget.dev.parent,
495 req->req.dma,
496 req->req.length,
497 (direct == USB_DIR_IN)
498 ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
499
500 req->mapped = 0;
501 }
502}
503
504/*-------------------------------------------------------------------------*/
505static void _nbu2ss_dma_unmap_single(
506 struct nbu2ss_udc *udc,
507 struct nbu2ss_ep *ep,
508 struct nbu2ss_req *req,
509 u8 direct
510)
511{
512 u8 data[4];
513 u8 *p;
514 u32 count = 0;
515
516 if (direct == USB_DIR_OUT) {
517 count = req->req.actual % 4;
518 if (count) {
519 p = req->req.buf;
520 p += (req->req.actual - count);
521 memcpy(data, p, count);
522 }
523 }
524
525 if (req->mapped) {
526 if (req->unaligned) {
527 if (direct == USB_DIR_OUT)
528 memcpy(req->req.buf, ep->virt_buf,
529 req->req.actual & 0xfffffffc);
530 } else
531 dma_unmap_single(udc->gadget.dev.parent,
532 req->req.dma, req->req.length,
533 (direct == USB_DIR_IN)
534 ? DMA_TO_DEVICE
535 : DMA_FROM_DEVICE);
536 req->req.dma = DMA_ADDR_INVALID;
537 req->mapped = 0;
538 } else {
539 if (!req->unaligned)
540 dma_sync_single_for_cpu(udc->gadget.dev.parent,
541 req->req.dma, req->req.length,
542 (direct == USB_DIR_IN)
543 ? DMA_TO_DEVICE
544 : DMA_FROM_DEVICE);
545 }
546
547 if (count) {
548 p = req->req.buf;
549 p += (req->req.actual - count);
550 memcpy(p, data, count);
551 }
552}
553#endif
554
555/*-------------------------------------------------------------------------*/
556/* Endpoint 0 OUT Transfer (PIO) */
a2c14e97 557static int EP0_out_PIO(struct nbu2ss_udc *udc, u8 *pBuf, u32 length)
33aa8d45
MD		 558{
559 u32 i;
560 int nret = 0;
561 u32 iWordLength = 0;
f6ef6c09 562 union usb_reg_access *pBuf32 = (union usb_reg_access *)pBuf;
33aa8d45
MD		 563
564 /*------------------------------------------------------------*/
565 /* Read Length */
566 iWordLength = length / sizeof(u32);
567
568 /*------------------------------------------------------------*/
569 /* PIO Read */
570 if (iWordLength) {
571 for (i = 0; i < iWordLength; i++) {
572 pBuf32->dw = _nbu2ss_readl(&udc->p_regs->EP0_READ);
573 pBuf32++;
574 }
575 nret = iWordLength * sizeof(u32);
576 }
577
578 return nret;
579}
580
581/*-------------------------------------------------------------------------*/
582/* Endpoint 0 OUT Transfer (PIO, OverBytes) */
a2c14e97 583static int EP0_out_OverBytes(struct nbu2ss_udc *udc, u8 *pBuf, u32 length)
33aa8d45
MD		 584{
585 u32 i;
586 u32 iReadSize = 0;
f6ef6c09
HM		 587 union usb_reg_access Temp32;
588 union usb_reg_access *pBuf32 = (union usb_reg_access *)pBuf;
33aa8d45 589
2866914c 590 if ((length > 0) && (length < sizeof(u32))) {
33aa8d45
MD		 591 Temp32.dw = _nbu2ss_readl(&udc->p_regs->EP0_READ);
592 for (i = 0 ; i < length ; i++)
593 pBuf32->byte.DATA[i] = Temp32.byte.DATA[i];
594 iReadSize += length;
595 }
596
597 return iReadSize;
598}
599
600/*-------------------------------------------------------------------------*/
601/* Endpoint 0 IN Transfer (PIO) */
602static int EP0_in_PIO(struct nbu2ss_udc *udc, u8 *pBuf, u32 length)
603{
604 u32 i;
605 u32 iMaxLength = EP0_PACKETSIZE;
606 u32 iWordLength = 0;
607 u32 iWriteLength = 0;
f6ef6c09 608 union usb_reg_access *pBuf32 = (union usb_reg_access *)pBuf;
33aa8d45
MD		 609
610 /*------------------------------------------------------------*/
611 /* Transfer Length */
612 if (iMaxLength < length)
613 iWordLength = iMaxLength / sizeof(u32);
614 else
615 iWordLength = length / sizeof(u32);
616
617 /*------------------------------------------------------------*/
618 /* PIO */
619 for (i = 0; i < iWordLength; i++) {
620 _nbu2ss_writel(&udc->p_regs->EP0_WRITE, pBuf32->dw);
621 pBuf32++;
622 iWriteLength += sizeof(u32);
623 }
624
625 return iWriteLength;
626}
627
628/*-------------------------------------------------------------------------*/
629/* Endpoint 0 IN Transfer (PIO, OverBytes) */
630static int EP0_in_OverBytes(struct nbu2ss_udc *udc, u8 *pBuf, u32 iRemainSize)
631{
632 u32 i;
f6ef6c09
HM		 633 union usb_reg_access Temp32;
634 union usb_reg_access *pBuf32 = (union usb_reg_access *)pBuf;
33aa8d45 635
2866914c 636 if ((iRemainSize > 0) && (iRemainSize < sizeof(u32))) {
33aa8d45
MD		 637 for (i = 0 ; i < iRemainSize ; i++)
638 Temp32.byte.DATA[i] = pBuf32->byte.DATA[i];
639 _nbu2ss_ep_in_end(udc, 0, Temp32.dw, iRemainSize);
640
641 return iRemainSize;
642 }
643
644 return 0;
645}
646
647/*-------------------------------------------------------------------------*/
648/* Transfer NULL Packet (Epndoint 0) */
649static int EP0_send_NULL(struct nbu2ss_udc *udc, bool pid_flag)
650{
651 u32 data;
652
653 data = _nbu2ss_readl(&udc->p_regs->EP0_CONTROL);
654 data &= ~(u32)EP0_INAK;
655
656 if (pid_flag)
657 data |= (EP0_INAK_EN | EP0_PIDCLR | EP0_DEND);
658 else
659 data |= (EP0_INAK_EN | EP0_DEND);
660
661 _nbu2ss_writel(&udc->p_regs->EP0_CONTROL, data);
662
663 return 0;
664}
665
666/*-------------------------------------------------------------------------*/
667/* Receive NULL Packet (Endpoint 0) */
668static int EP0_receive_NULL(struct nbu2ss_udc *udc, bool pid_flag)
669{
670 u32 data;
671
672 data = _nbu2ss_readl(&udc->p_regs->EP0_CONTROL);
673 data &= ~(u32)EP0_ONAK;
674
675 if (pid_flag)
676 data |= EP0_PIDCLR;
677
678 _nbu2ss_writel(&udc->p_regs->EP0_CONTROL, data);
679
680 return 0;
681}
682
683/*-------------------------------------------------------------------------*/
684static int _nbu2ss_ep0_in_transfer(
685 struct nbu2ss_udc *udc,
33aa8d45
MD		 686 struct nbu2ss_req *req
687)
688{
689 u8 *pBuffer; /* IN Data Buffer */
690 u32 data;
691 u32 iRemainSize = 0;
692 int result = 0;
693
694 /*-------------------------------------------------------------*/
695 /* End confirmation */
696 if (req->req.actual == req->req.length) {
697 if ((req->req.actual % EP0_PACKETSIZE) == 0) {
698 if (req->zero) {
666e9084 699 req->zero = false;
33aa8d45
MD		 700 EP0_send_NULL(udc, FALSE);
701 return 1;
702 }
703 }
704
705 return 0; /* Transfer End */
706 }
707
708 /*-------------------------------------------------------------*/
709 /* NAK release */
710 data = _nbu2ss_readl(&udc->p_regs->EP0_CONTROL);
711 data |= EP0_INAK_EN;
712 data &= ~(u32)EP0_INAK;
713 _nbu2ss_writel(&udc->p_regs->EP0_CONTROL, data);
714
715 iRemainSize = req->req.length - req->req.actual;
716 pBuffer = (u8 *)req->req.buf;
717 pBuffer += req->req.actual;
718
719 /*-------------------------------------------------------------*/
720 /* Data transfer */
721 result = EP0_in_PIO(udc, pBuffer, iRemainSize);
722
723 req->div_len = result;
724 iRemainSize -= result;
725
726 if (iRemainSize == 0) {
727 EP0_send_NULL(udc, FALSE);
728 return result;
729 }
730
731 if ((iRemainSize < sizeof(u32)) && (result != EP0_PACKETSIZE)) {
732 pBuffer += result;
733 result += EP0_in_OverBytes(udc, pBuffer, iRemainSize);
734 req->div_len = result;
735 }
736
737 return result;
738}
739
740/*-------------------------------------------------------------------------*/
741static int _nbu2ss_ep0_out_transfer(
742 struct nbu2ss_udc *udc,
33aa8d45
MD		 743 struct nbu2ss_req *req
744)
745{
746 u8 *pBuffer;
747 u32 iRemainSize;
748 u32 iRecvLength;
749 int result = 0;
750 int fRcvZero;
751
752 /*-------------------------------------------------------------*/
753 /* Receive data confirmation */
754 iRecvLength = _nbu2ss_readl(&udc->p_regs->EP0_LENGTH) & EP0_LDATA;
755 if (iRecvLength != 0) {
756
757 fRcvZero = 0;
758
759 iRemainSize = req->req.length - req->req.actual;
760 pBuffer = (u8 *)req->req.buf;
761 pBuffer += req->req.actual;
762
763 result = EP0_out_PIO(udc, pBuffer
764 , min(iRemainSize, iRecvLength));
765 if (result < 0)
766 return result;
767
768 req->req.actual += result;
769 iRecvLength -= result;
770
2866914c 771 if ((iRecvLength > 0) && (iRecvLength < sizeof(u32))) {
33aa8d45
MD		 772 pBuffer += result;
773 iRemainSize -= result;
774
775 result = EP0_out_OverBytes(udc, pBuffer
776 , min(iRemainSize, iRecvLength));
777 req->req.actual += result;
778 }
779 } else {
780 fRcvZero = 1;
781 }
782
783 /*-------------------------------------------------------------*/
784 /* End confirmation */
785 if (req->req.actual == req->req.length) {
786 if ((req->req.actual % EP0_PACKETSIZE) == 0) {
787 if (req->zero) {
666e9084 788 req->zero = false;
33aa8d45
MD		 789 EP0_receive_NULL(udc, FALSE);
790 return 1;
791 }
792 }
793
794 return 0; /* Transfer End */
795 }
796
797 if ((req->req.actual % EP0_PACKETSIZE) != 0)
798 return 0; /* Short Packet Transfer End */
799
800 if (req->req.actual > req->req.length) {
88689279 801 dev_err(udc->dev, " *** Overrun Error\n");
33aa8d45
MD		 802 return -EOVERFLOW;
803 }
804
805 if (fRcvZero != 0) {
806 iRemainSize = _nbu2ss_readl(&udc->p_regs->EP0_CONTROL);
807 if (iRemainSize & EP0_ONAK) {
808 /*---------------------------------------------------*/
809 /* NACK release */
810 _nbu2ss_bitclr(&udc->p_regs->EP0_CONTROL, EP0_ONAK);
811 }
812 result = 1;
813 }
814
815 return result;
816}
817
818/*-------------------------------------------------------------------------*/
819static int _nbu2ss_out_dma(
820 struct nbu2ss_udc *udc,
821 struct nbu2ss_req *req,
822 u32 num,
823 u32 length
824)
825{
826 u8 *pBuffer;
827 u32 mpkt;
828 u32 lmpkt;
829 u32 dmacnt;
830 u32 burst = 1;
831 u32 data;
832 int result = -EINVAL;
f6ef6c09 833 struct fc_regs *preg = udc->p_regs;
33aa8d45
MD		 834
835 if (req->dma_flag)
836 return 1; /* DMA is forwarded */
837
838 req->dma_flag = TRUE;
839 pBuffer = (u8 *)req->req.dma;
840 pBuffer += req->req.actual;
841
842 /* DMA Address */
843 _nbu2ss_writel(&preg->EP_DCR[num].EP_TADR, (u32)pBuffer);
844
845 /* Number of transfer packets */
846 mpkt = _nbu2ss_readl(&preg->EP_REGS[num].EP_PCKT_ADRS) & EPn_MPKT;
847 dmacnt = (length / mpkt);
848 lmpkt = (length % mpkt) & ~(u32)0x03;
849
2866914c 850 if (dmacnt > DMA_MAX_COUNT) {
33aa8d45
MD		 851 dmacnt = DMA_MAX_COUNT;
852 lmpkt = 0;
2866914c
CM		 853 } else if (lmpkt != 0) {
854 if (dmacnt == 0)
33aa8d45
MD		 855 burst = 0; /* Burst OFF */
856 dmacnt++;
857 }
858
859 data = mpkt | (lmpkt << 16);
860 _nbu2ss_writel(&preg->EP_DCR[num].EP_DCR2, data);
861
862 data = ((dmacnt & 0xff) << 16) | DCR1_EPn_DIR0 | DCR1_EPn_REQEN;
863 _nbu2ss_writel(&preg->EP_DCR[num].EP_DCR1, data);
864
2866914c 865 if (burst == 0) {
33aa8d45
MD		 866 _nbu2ss_writel(&preg->EP_REGS[num].EP_LEN_DCNT, 0);
867 _nbu2ss_bitclr(&preg->EP_REGS[num].EP_DMA_CTRL, EPn_BURST_SET);
868 } else {
869 _nbu2ss_writel(&preg->EP_REGS[num].EP_LEN_DCNT
870 , (dmacnt << 16));
871 _nbu2ss_bitset(&preg->EP_REGS[num].EP_DMA_CTRL, EPn_BURST_SET);
872 }
873 _nbu2ss_bitset(&preg->EP_REGS[num].EP_DMA_CTRL, EPn_DMA_EN);
874
875 result = length & ~(u32)0x03;
876 req->div_len = result;
877
878 return result;
879}
880
881/*-------------------------------------------------------------------------*/
882static int _nbu2ss_epn_out_pio(
883 struct nbu2ss_udc *udc,
884 struct nbu2ss_ep *ep,
885 struct nbu2ss_req *req,
886 u32 length
887)
888{
889 u8 *pBuffer;
890 u32 i;
891 u32 data;
892 u32 iWordLength;
f6ef6c09
HM		 893 union usb_reg_access Temp32;
894 union usb_reg_access *pBuf32;
33aa8d45 895 int result = 0;
f6ef6c09 896 struct fc_regs *preg = udc->p_regs;
33aa8d45
MD		 897
898 if (req->dma_flag)
899 return 1; /* DMA is forwarded */
900
901 if (length == 0)
902 return 0;
903
904 pBuffer = (u8 *)req->req.buf;
f6ef6c09 905 pBuf32 = (union usb_reg_access *)(pBuffer + req->req.actual);
33aa8d45
MD		 906
907 iWordLength = length / sizeof(u32);
908 if (iWordLength > 0) {
909 /*---------------------------------------------------------*/
910 /* Copy of every four bytes */
911 for (i = 0; i < iWordLength; i++) {
912 pBuf32->dw =
913 _nbu2ss_readl(&preg->EP_REGS[ep->epnum-1].EP_READ);
914 pBuf32++;
915 }
916 result = iWordLength * sizeof(u32);
917 }
918
919 data = length - result;
920 if (data > 0) {
921 /*---------------------------------------------------------*/
922 /* Copy of fraction byte */
923 Temp32.dw = _nbu2ss_readl(&preg->EP_REGS[ep->epnum-1].EP_READ);
924 for (i = 0 ; i < data ; i++)
925 pBuf32->byte.DATA[i] = Temp32.byte.DATA[i];
926 result += data;
927 }
928
929 req->req.actual += result;
930
931 if ((req->req.actual == req->req.length)
932 || ((req->req.actual % ep->ep.maxpacket) != 0)) {
933
934 result = 0;
935 }
936
937 return result;
938}
939
940/*-------------------------------------------------------------------------*/
941static int _nbu2ss_epn_out_data(
942 struct nbu2ss_udc *udc,
943 struct nbu2ss_ep *ep,
944 struct nbu2ss_req *req,
945 u32 data_size
946)
947{
948 u32 num;
949 u32 iBufSize;
950 int nret = 1;
951
952 if (ep->epnum == 0)
953 return -EINVAL;
954
955 num = ep->epnum - 1;
956
957 iBufSize = min((req->req.length - req->req.actual), data_size);
958
959 if ((ep->ep_type != USB_ENDPOINT_XFER_INT)
960 && (req->req.dma != 0)
961 && (iBufSize >= sizeof(u32))) {
962 nret = _nbu2ss_out_dma(udc, req, num, iBufSize);
963 } else {
77d966f4 964 iBufSize = min_t(u32, iBufSize, ep->ep.maxpacket);
33aa8d45
MD		 965 nret = _nbu2ss_epn_out_pio(udc, ep, req, iBufSize);
966 }
967
968 return nret;
969}
970
971/*-------------------------------------------------------------------------*/
972static int _nbu2ss_epn_out_transfer(
973 struct nbu2ss_udc *udc,
974 struct nbu2ss_ep *ep,
975 struct nbu2ss_req *req
976)
977{
978 u32 num;
979 u32 iRecvLength;
980 int result = 1;
f6ef6c09 981 struct fc_regs *preg = udc->p_regs;
33aa8d45
MD		 982
983 if (ep->epnum == 0)
984 return -EINVAL;
985
986 num = ep->epnum - 1;
987
988 /*-------------------------------------------------------------*/
989 /* Receive Length */
990 iRecvLength
991 = _nbu2ss_readl(&preg->EP_REGS[num].EP_LEN_DCNT) & EPn_LDATA;
992
993 if (iRecvLength != 0) {
994 result = _nbu2ss_epn_out_data(udc, ep, req, iRecvLength);
995 if (iRecvLength < ep->ep.maxpacket) {
996 if (iRecvLength == result) {
997 req->req.actual += result;
998 result = 0;
999 }
1000 }
1001 } else {
1002 if ((req->req.actual == req->req.length)
1003 || ((req->req.actual % ep->ep.maxpacket) != 0)) {
1004
1005 result = 0;
1006 }
1007 }
1008
1009 if (result == 0) {
1010 if ((req->req.actual % ep->ep.maxpacket) == 0) {
1011 if (req->zero) {
666e9084 1012 req->zero = false;
33aa8d45
MD		 1013 return 1;
1014 }
1015 }
1016 }
1017
1018 if (req->req.actual > req->req.length) {
88689279
HM		 1019 dev_err(udc->dev, " Overrun Error\n");
1020 dev_err(udc->dev, " actual = %d, length = %d\n",
33aa8d45
MD		 1021 req->req.actual, req->req.length);
1022 result = -EOVERFLOW;
1023 }
1024
1025 return result;
1026}
1027
1028/*-------------------------------------------------------------------------*/
1029static int _nbu2ss_in_dma(
1030 struct nbu2ss_udc *udc,
1031 struct nbu2ss_ep *ep,
1032 struct nbu2ss_req *req,
1033 u32 num,
1034 u32 length
1035)
1036{
1037 u8 *pBuffer;
1038 u32 mpkt; /* MaxPacketSize */
1039 u32 lmpkt; /* Last Packet Data Size */
1040 u32 dmacnt; /* IN Data Size */
1041 u32 iWriteLength;
1042 u32 data;
1043 int result = -EINVAL;
f6ef6c09 1044 struct fc_regs *preg = udc->p_regs;
33aa8d45
MD		 1045
1046 if (req->dma_flag)
1047 return 1; /* DMA is forwarded */
1048
1049#ifdef USE_DMA
1050 if (req->req.actual == 0)
1051 _nbu2ss_dma_map_single(udc, ep, req, USB_DIR_IN);
1052#endif
1053 req->dma_flag = TRUE;
1054
1055 /* MAX Packet Size */
1056 mpkt = _nbu2ss_readl(&preg->EP_REGS[num].EP_PCKT_ADRS) & EPn_MPKT;
1057
1058 if ((DMA_MAX_COUNT * mpkt) < length)
1059 iWriteLength = DMA_MAX_COUNT * mpkt;
1060 else
1061 iWriteLength = length;
1062
1063 /*------------------------------------------------------------*/
1064 /* Number of transmission packets */
1065 if (mpkt < iWriteLength) {
1066 dmacnt = iWriteLength / mpkt;
1067 lmpkt = (iWriteLength % mpkt) & ~(u32)0x3;
1068 if (lmpkt != 0)
1069 dmacnt++;
1070 else
1071 lmpkt = mpkt & ~(u32)0x3;
1072
1073 } else {
1074 dmacnt = 1;
1075 lmpkt = iWriteLength & ~(u32)0x3;
1076 }
1077
1078 /* Packet setting */
1079 data = mpkt | (lmpkt << 16);
1080 _nbu2ss_writel(&preg->EP_DCR[num].EP_DCR2, data);
1081
1082 /* Address setting */
1083 pBuffer = (u8 *)req->req.dma;
1084 pBuffer += req->req.actual;
1085 _nbu2ss_writel(&preg->EP_DCR[num].EP_TADR, (u32)pBuffer);
1086
1087 /* Packet and DMA setting */
1088 data = ((dmacnt & 0xff) << 16) | DCR1_EPn_REQEN;
1089 _nbu2ss_writel(&preg->EP_DCR[num].EP_DCR1, data);
1090
1091 /* Packet setting of EPC */
1092 data = dmacnt << 16;
1093 _nbu2ss_writel(&preg->EP_REGS[num].EP_LEN_DCNT, data);
1094
1095 /*DMA setting of EPC */
1096 _nbu2ss_bitset(&preg->EP_REGS[num].EP_DMA_CTRL, EPn_DMA_EN);
1097
1098 result = iWriteLength & ~(u32)0x3;
1099 req->div_len = result;
1100
1101 return result;
1102}
1103
1104/*-------------------------------------------------------------------------*/
1105static int _nbu2ss_epn_in_pio(
1106 struct nbu2ss_udc *udc,
1107 struct nbu2ss_ep *ep,
1108 struct nbu2ss_req *req,
1109 u32 length
1110)
1111{
1112 u8 *pBuffer;
1113 u32 i;
1114 u32 data;
1115 u32 iWordLength;
f6ef6c09
HM		 1116 union usb_reg_access Temp32;
1117 union usb_reg_access *pBuf32 = NULL;
33aa8d45 1118 int result = 0;
f6ef6c09 1119 struct fc_regs *preg = udc->p_regs;
33aa8d45
MD		 1120
1121 if (req->dma_flag)
1122 return 1; /* DMA is forwarded */
1123
1124 if (length > 0) {
1125 pBuffer = (u8 *)req->req.buf;
f6ef6c09 1126 pBuf32 = (union usb_reg_access *)(pBuffer + req->req.actual);
33aa8d45
MD		 1127
1128 iWordLength = length / sizeof(u32);
1129 if (iWordLength > 0) {
1130 for (i = 0; i < iWordLength; i++) {
1131 _nbu2ss_writel(
1132 &preg->EP_REGS[ep->epnum-1].EP_WRITE
1133 , pBuf32->dw
1134 );
1135
1136 pBuf32++;
1137 }
1138 result = iWordLength * sizeof(u32);
1139 }
1140 }
1141
1142 if (result != ep->ep.maxpacket) {
1143 data = length - result;
1144 Temp32.dw = 0;
1145 for (i = 0 ; i < data ; i++)
1146 Temp32.byte.DATA[i] = pBuf32->byte.DATA[i];
1147
1148 _nbu2ss_ep_in_end(udc, ep->epnum, Temp32.dw, data);
1149 result += data;
1150 }
1151
1152 req->div_len = result;
1153
1154 return result;
1155}
1156
1157/*-------------------------------------------------------------------------*/
1158static int _nbu2ss_epn_in_data(
1159 struct nbu2ss_udc *udc,
1160 struct nbu2ss_ep *ep,
1161 struct nbu2ss_req *req,
1162 u32 data_size
1163)
1164{
1165 u32 num;
1166 int nret = 1;
1167
1168 if (ep->epnum == 0)
1169 return -EINVAL;
1170
1171 num = ep->epnum - 1;
1172
1173 if ((ep->ep_type != USB_ENDPOINT_XFER_INT)
1174 && (req->req.dma != 0)
1175 && (data_size >= sizeof(u32))) {
1176 nret = _nbu2ss_in_dma(udc, ep, req, num, data_size);
1177 } else {
77d966f4 1178 data_size = min_t(u32, data_size, ep->ep.maxpacket);
33aa8d45
MD		 1179 nret = _nbu2ss_epn_in_pio(udc, ep, req, data_size);
1180 }
1181
1182 return nret;
1183}
1184
1185/*-------------------------------------------------------------------------*/
1186static int _nbu2ss_epn_in_transfer(
1187 struct nbu2ss_udc *udc,
1188 struct nbu2ss_ep *ep,
1189 struct nbu2ss_req *req
1190)
1191{
1192 u32 num;
1193 u32 iBufSize;
1194 int result = 0;
1195 u32 status;
1196
1197 if (ep->epnum == 0)
1198 return -EINVAL;
1199
1200 num = ep->epnum - 1;
1201
1202 status = _nbu2ss_readl(&udc->p_regs->EP_REGS[num].EP_STATUS);
1203
1204 /*-------------------------------------------------------------*/
1205 /* State confirmation of FIFO */
1206 if (req->req.actual == 0) {
1207 if ((status & EPn_IN_EMPTY) == 0)
1208 return 1; /* Not Empty */
1209
1210 } else {
1211 if ((status & EPn_IN_FULL) != 0)
1212 return 1; /* Not Empty */
1213 }
1214
1215 /*-------------------------------------------------------------*/
69e98df7 1216 /* Start transfer */
33aa8d45
MD		 1217 iBufSize = req->req.length - req->req.actual;
1218 if (iBufSize > 0)
1219 result = _nbu2ss_epn_in_data(udc, ep, req, iBufSize);
1220 else if (req->req.length == 0)
1221 _nbu2ss_zero_len_pkt(udc, ep->epnum);
1222
1223 return result;
1224}
1225
1226/*-------------------------------------------------------------------------*/
1227static int _nbu2ss_start_transfer(
1228 struct nbu2ss_udc *udc,
1229 struct nbu2ss_ep *ep,
1230 struct nbu2ss_req *req,
1231 bool bflag)
1232{
1233 int nret = -EINVAL;
1234
1235 req->dma_flag = FALSE;
1236 req->div_len = 0;
1237
1238 if (req->req.length == 0)
666e9084 1239 req->zero = false;
33aa8d45
MD		 1240 else {
1241 if ((req->req.length % ep->ep.maxpacket) == 0)
1242 req->zero = req->req.zero;
1243 else
666e9084 1244 req->zero = false;
33aa8d45
MD		 1245 }
1246
1247 if (ep->epnum == 0) {
1248 /* EP0 */
1249 switch (udc->ep0state) {
1250 case EP0_IN_DATA_PHASE:
f2b29165 1251 nret = _nbu2ss_ep0_in_transfer(udc, req);
33aa8d45
MD		 1252 break;
1253
1254 case EP0_OUT_DATA_PHASE:
f2b29165 1255 nret = _nbu2ss_ep0_out_transfer(udc, req);
33aa8d45
MD		 1256 break;
1257
1258 case EP0_IN_STATUS_PHASE:
1259 nret = EP0_send_NULL(udc, TRUE);
1260 break;
1261
1262 default:
1263 break;
1264 }
1265
1266 } else {
1267 /* EPn */
1268 if (ep->direct == USB_DIR_OUT) {
1269 /* OUT */
5a602ac4 1270 if (!bflag)
33aa8d45
MD		 1271 nret = _nbu2ss_epn_out_transfer(udc, ep, req);
1272 } else {
1273 /* IN */
1274 nret = _nbu2ss_epn_in_transfer(udc, ep, req);
1275 }
1276 }
1277
1278 return nret;
1279}
1280
1281/*-------------------------------------------------------------------------*/
1282static void _nbu2ss_restert_transfer(struct nbu2ss_ep *ep)
1283{
1284 u32 length;
1285 bool bflag = FALSE;
1286 struct nbu2ss_req *req;
1287
1288 if (list_empty(&ep->queue))
1289 req = NULL;
1290 else
1291 req = list_entry(ep->queue.next, struct nbu2ss_req, queue);
1292
706eb8cf 1293 if (!req)
33aa8d45
MD		 1294 return;
1295
1296 if (ep->epnum > 0) {
1297 length = _nbu2ss_readl(
1298 &ep->udc->p_regs->EP_REGS[ep->epnum-1].EP_LEN_DCNT);
1299
1300 length &= EPn_LDATA;
1301 if (length < ep->ep.maxpacket)
1302 bflag = TRUE;
1303 }
1304
1305 _nbu2ss_start_transfer(ep->udc, ep, req, bflag);
1306}
1307
1308/*-------------------------------------------------------------------------*/
1309/* Endpoint Toggle Reset */
1310static void _nbu2ss_endpoint_toggle_reset(
1311 struct nbu2ss_udc *udc,
1312 u8 ep_adrs)
1313{
1314 u8 num;
1315 u32 data;
1316
1317 if ((ep_adrs == 0) || (ep_adrs == 0x80))
1318 return;
1319
1320 num = (ep_adrs & 0x7F) - 1;
1321
1322 if (ep_adrs & USB_DIR_IN)
1323 data = EPn_IPIDCLR;
1324 else
1325 data = EPn_BCLR | EPn_OPIDCLR;
1326
1327 _nbu2ss_bitset(&udc->p_regs->EP_REGS[num].EP_CONTROL, data);
1328}
1329
1330/*-------------------------------------------------------------------------*/
1331/* Endpoint STALL set */
1332static void _nbu2ss_set_endpoint_stall(
1333 struct nbu2ss_udc *udc,
1334 u8 ep_adrs,
1335 bool bstall)
1336{
1337 u8 num, epnum;
1338 u32 data;
1339 struct nbu2ss_ep *ep;
f6ef6c09 1340 struct fc_regs *preg = udc->p_regs;
33aa8d45
MD		 1341
1342 if ((ep_adrs == 0) || (ep_adrs == 0x80)) {
1343 if (bstall) {
1344 /* Set STALL */
1345 _nbu2ss_bitset(&preg->EP0_CONTROL, EP0_STL);
1346 } else {
1347 /* Clear STALL */
1348 _nbu2ss_bitclr(&preg->EP0_CONTROL, EP0_STL);
1349 }
1350 } else {
1351 epnum = ep_adrs & USB_ENDPOINT_NUMBER_MASK;
1352 num = epnum - 1;
1353 ep = &udc->ep[epnum];
1354
1355 if (bstall) {
1356 /* Set STALL */
1357 ep->halted = TRUE;
1358
1359 if (ep_adrs & USB_DIR_IN)
1360 data = EPn_BCLR | EPn_ISTL;
1361 else
1362 data = EPn_OSTL_EN | EPn_OSTL;
1363
1364 _nbu2ss_bitset(&preg->EP_REGS[num].EP_CONTROL, data);
1365 } else {
1366 /* Clear STALL */
1367 ep->stalled = FALSE;
1368 if (ep_adrs & USB_DIR_IN) {
1369 _nbu2ss_bitclr(&preg->EP_REGS[num].EP_CONTROL
1370 , EPn_ISTL);
1371 } else {
1372 data =
1373 _nbu2ss_readl(&preg->EP_REGS[num].EP_CONTROL);
1374
1375 data &= ~EPn_OSTL;
1376 data |= EPn_OSTL_EN;
1377
1378 _nbu2ss_writel(&preg->EP_REGS[num].EP_CONTROL
1379 , data);
1380 }
1381
1382 ep->stalled = FALSE;
1383 if (ep->halted) {
1384 ep->halted = FALSE;
1385 _nbu2ss_restert_transfer(ep);
1386 }
1387 }
1388 }
33aa8d45
MD		 1389}
1390
33aa8d45
MD		 1391/*-------------------------------------------------------------------------*/
1392/* Device Descriptor */
1393static struct usb_device_descriptor device_desc = {
1394 .bLength = sizeof(device_desc),
1395 .bDescriptorType = USB_DT_DEVICE,
1ff99b31 1396 .bcdUSB = cpu_to_le16(0x0200),
33aa8d45
MD		 1397 .bDeviceClass = USB_CLASS_VENDOR_SPEC,
1398 .bDeviceSubClass = 0x00,
1399 .bDeviceProtocol = 0x00,
1400 .bMaxPacketSize0 = 64,
1ff99b31
RD		 1401 .idVendor = cpu_to_le16(0x0409),
1402 .idProduct = cpu_to_le16(0xfff0),
33aa8d45
MD		 1403 .bcdDevice = 0xffff,
1404 .iManufacturer = 0x00,
1405 .iProduct = 0x00,
1406 .iSerialNumber = 0x00,
1407 .bNumConfigurations = 0x01,
1408};
1409
1410/*-------------------------------------------------------------------------*/
1411static void _nbu2ss_set_test_mode(struct nbu2ss_udc *udc, u32 mode)
1412{
1413 u32 data;
1414
1415 if (mode > MAX_TEST_MODE_NUM)
1416 return;
1417
93275c80 1418 dev_info(udc->dev, "SET FEATURE : test mode = %d\n", mode);
33aa8d45
MD		 1419
1420 data = _nbu2ss_readl(&udc->p_regs->USB_CONTROL);
1421 data &= ~TEST_FORCE_ENABLE;
1422 data |= mode << TEST_MODE_SHIFT;
1423
1424 _nbu2ss_writel(&udc->p_regs->USB_CONTROL, data);
1425 _nbu2ss_bitset(&udc->p_regs->TEST_CONTROL, CS_TESTMODEEN);
1426}
1427
1428/*-------------------------------------------------------------------------*/
1429static int _nbu2ss_set_feature_device(
1430 struct nbu2ss_udc *udc,
1431 u16 selector,
1432 u16 wIndex
1433)
1434{
1435 int result = -EOPNOTSUPP;
1436
1437 switch (selector) {
1438 case USB_DEVICE_REMOTE_WAKEUP:
2866914c 1439 if (wIndex == 0x0000) {
33aa8d45
MD		 1440 udc->remote_wakeup = U2F_ENABLE;
1441 result = 0;
1442 }
1443 break;
1444
1445 case USB_DEVICE_TEST_MODE:
410c944e 1446 wIndex >>= 8;
33aa8d45
MD		 1447 if (wIndex <= MAX_TEST_MODE_NUM)
1448 result = 0;
1449 break;
1450
1451 default:
1452 break;
1453 }
1454
1455 return result;
1456}
1457
1458/*-------------------------------------------------------------------------*/
1459static int _nbu2ss_get_ep_stall(struct nbu2ss_udc *udc, u8 ep_adrs)
1460{
1461 u8 epnum;
1462 u32 data = 0, bit_data;
f6ef6c09 1463 struct fc_regs *preg = udc->p_regs;
33aa8d45
MD		 1464
1465 epnum = ep_adrs & ~USB_ENDPOINT_DIR_MASK;
1466 if (epnum == 0) {
1467 data = _nbu2ss_readl(&preg->EP0_CONTROL);
1468 bit_data = EP0_STL;
1469
1470 } else {
1471 data = _nbu2ss_readl(&preg->EP_REGS[epnum-1].EP_CONTROL);
1472 if ((data & EPn_EN) == 0)
1473 return -1;
1474
1475 if (ep_adrs & USB_ENDPOINT_DIR_MASK)
1476 bit_data = EPn_ISTL;
1477 else
1478 bit_data = EPn_OSTL;
1479 }
1480
1481 if ((data & bit_data) == 0)
1482 return 0;
924c6ee1 1483 return 1;
33aa8d45
MD		 1484}
1485
1486/*-------------------------------------------------------------------------*/
1487static inline int _nbu2ss_req_feature(struct nbu2ss_udc *udc, bool bset)
1488{
1489 u8 recipient = (u8)(udc->ctrl.bRequestType & USB_RECIP_MASK);
1490 u8 direction = (u8)(udc->ctrl.bRequestType & USB_DIR_IN);
1491 u16 selector = udc->ctrl.wValue;
1492 u16 wIndex = udc->ctrl.wIndex;
1493 u8 ep_adrs;
1494 int result = -EOPNOTSUPP;
1495
2866914c
CM		 1496 if ((udc->ctrl.wLength != 0x0000) ||
1497 (direction != USB_DIR_OUT)) {
33aa8d45
MD		 1498 return -EINVAL;
1499 }
1500
1501 switch (recipient) {
1502 case USB_RECIP_DEVICE:
1503 if (bset)
1504 result =
1505 _nbu2ss_set_feature_device(udc, selector, wIndex);
1506 break;
1507
1508 case USB_RECIP_ENDPOINT:
1509 if (0x0000 == (wIndex & 0xFF70)) {
2866914c 1510 if (selector == USB_ENDPOINT_HALT) {
33aa8d45 1511 ep_adrs = wIndex & 0xFF;
5a602ac4 1512 if (!bset) {
33aa8d45
MD		 1513 _nbu2ss_endpoint_toggle_reset(
1514 udc, ep_adrs);
1515 }
1516
1517 _nbu2ss_set_endpoint_stall(
1518 udc, ep_adrs, bset);
1519
1520 result = 0;
1521 }
1522 }
1523 break;
1524
1525 default:
1526 break;
1527 }
1528
1529 if (result >= 0)
1530 _nbu2ss_create_ep0_packet(udc, udc->ep0_buf, 0);
1531
1532 return result;
1533}
1534
1535/*-------------------------------------------------------------------------*/
1536static inline enum usb_device_speed _nbu2ss_get_speed(struct nbu2ss_udc *udc)
1537{
1538 u32 data;
1539 enum usb_device_speed speed = USB_SPEED_FULL;
1540
1541 data = _nbu2ss_readl(&udc->p_regs->USB_STATUS);
1542 if (data & HIGH_SPEED)
1543 speed = USB_SPEED_HIGH;
1544
1545 return speed;
1546}
1547
1548/*-------------------------------------------------------------------------*/
1549static void _nbu2ss_epn_set_stall(
1550 struct nbu2ss_udc *udc,
1551 struct nbu2ss_ep *ep
1552)
1553{
1554 u8 ep_adrs;
1555 u32 regdata;
1556 int limit_cnt = 0;
1557
f6ef6c09 1558 struct fc_regs *preg = udc->p_regs;
33aa8d45
MD		 1559
1560 if (ep->direct == USB_DIR_IN) {
1561 for (limit_cnt = 0
1562 ; limit_cnt < IN_DATA_EMPTY_COUNT
1563 ; limit_cnt++) {
1564
1565 regdata = _nbu2ss_readl(
1566 &preg->EP_REGS[ep->epnum-1].EP_STATUS);
1567
1568 if ((regdata & EPn_IN_DATA) == 0)
1569 break;
1570
1571 mdelay(1);
1572 }
1573 }
1574
1575 ep_adrs = ep->epnum | ep->direct;
1576 _nbu2ss_set_endpoint_stall(udc, ep_adrs, 1);
1577}
1578
1579/*-------------------------------------------------------------------------*/
1580static int std_req_get_status(struct nbu2ss_udc *udc)
1581{
1582 u32 length;
1583 u16 status_data = 0;
1584 u8 recipient = (u8)(udc->ctrl.bRequestType & USB_RECIP_MASK);
1585 u8 direction = (u8)(udc->ctrl.bRequestType & USB_DIR_IN);
1586 u8 ep_adrs;
1587 int result = -EINVAL;
1588
2866914c
CM		 1589 if ((udc->ctrl.wValue != 0x0000)
1590 || (direction != USB_DIR_IN)) {
33aa8d45
MD		 1591
1592 return result;
1593 }
1594
77d966f4 1595 length = min_t(u16, udc->ctrl.wLength, sizeof(status_data));
33aa8d45
MD		 1596
1597 switch (recipient) {
1598 case USB_RECIP_DEVICE:
1599 if (udc->ctrl.wIndex == 0x0000) {
9239d88f 1600 if (udc->gadget.is_selfpowered)
33aa8d45
MD		 1601 status_data |= (1 << USB_DEVICE_SELF_POWERED);
1602
1603 if (udc->remote_wakeup)
1604 status_data |= (1 << USB_DEVICE_REMOTE_WAKEUP);
1605
1606 result = 0;
1607 }
1608 break;
1609
1610 case USB_RECIP_ENDPOINT:
1611 if (0x0000 == (udc->ctrl.wIndex & 0xFF70)) {
1612 ep_adrs = (u8)(udc->ctrl.wIndex & 0xFF);
1613 result = _nbu2ss_get_ep_stall(udc, ep_adrs);
1614
1615 if (result > 0)
1616 status_data |= (1 << USB_ENDPOINT_HALT);
1617 }
1618 break;
1619
1620 default:
1621 break;
1622 }
1623
1624 if (result >= 0) {
1625 memcpy(udc->ep0_buf, &status_data, length);
1626 _nbu2ss_create_ep0_packet(udc, udc->ep0_buf, length);
f2b29165 1627 _nbu2ss_ep0_in_transfer(udc, &udc->ep0_req);
33aa8d45
MD		 1628
1629 } else {
88689279 1630 dev_err(udc->dev, " Error GET_STATUS\n");
33aa8d45
MD		 1631 }
1632
1633 return result;
1634}
1635
1636/*-------------------------------------------------------------------------*/
1637static int std_req_clear_feature(struct nbu2ss_udc *udc)
1638{
1639 return _nbu2ss_req_feature(udc, FALSE);
1640}
1641
1642/*-------------------------------------------------------------------------*/
1643static int std_req_set_feature(struct nbu2ss_udc *udc)
1644{
1645 return _nbu2ss_req_feature(udc, TRUE);
1646}
1647
1648/*-------------------------------------------------------------------------*/
1649static int std_req_set_address(struct nbu2ss_udc *udc)
1650{
1651 int result = 0;
1652 u32 wValue = udc->ctrl.wValue;
1653
2866914c
CM		 1654 if ((udc->ctrl.bRequestType != 0x00) ||
1655 (udc->ctrl.wIndex != 0x0000) ||
1656 (udc->ctrl.wLength != 0x0000)) {
33aa8d45
MD		 1657 return -EINVAL;
1658 }
1659
1660 if (wValue != (wValue & 0x007F))
1661 return -EINVAL;
1662
410c944e 1663 wValue <<= USB_ADRS_SHIFT;
33aa8d45
MD		 1664
1665 _nbu2ss_writel(&udc->p_regs->USB_ADDRESS, wValue);
1666 _nbu2ss_create_ep0_packet(udc, udc->ep0_buf, 0);
1667
1668 return result;
1669}
1670
1671/*-------------------------------------------------------------------------*/
1672static int std_req_set_configuration(struct nbu2ss_udc *udc)
1673{
1674 u32 ConfigValue = (u32)(udc->ctrl.wValue & 0x00ff);
1675
2866914c
CM		 1676 if ((udc->ctrl.wIndex != 0x0000) ||
1677 (udc->ctrl.wLength != 0x0000) ||
1678 (udc->ctrl.bRequestType != 0x00)) {
33aa8d45
MD		 1679 return -EINVAL;
1680 }
1681
1682 udc->curr_config = ConfigValue;
1683
1684 if (ConfigValue > 0) {
1685 _nbu2ss_bitset(&udc->p_regs->USB_CONTROL, CONF);
1686 udc->devstate = USB_STATE_CONFIGURED;
1687
1688 } else {
1689 _nbu2ss_bitclr(&udc->p_regs->USB_CONTROL, CONF);
1690 udc->devstate = USB_STATE_ADDRESS;
1691 }
1692
1693 return 0;
1694}
1695
1696/*-------------------------------------------------------------------------*/
1697static inline void _nbu2ss_read_request_data(struct nbu2ss_udc *udc, u32 *pdata)
1698{
706eb8cf 1699 if ((!udc) && (!pdata))
33aa8d45
MD		 1700 return;
1701
1702 *pdata = _nbu2ss_readl(&udc->p_regs->SETUP_DATA0);
1703 pdata++;
1704 *pdata = _nbu2ss_readl(&udc->p_regs->SETUP_DATA1);
1705}
1706
1707/*-------------------------------------------------------------------------*/
1708static inline int _nbu2ss_decode_request(struct nbu2ss_udc *udc)
1709{
1710 bool bcall_back = TRUE;
1711 int nret = -EINVAL;
1712 struct usb_ctrlrequest *p_ctrl;
1713
1714 p_ctrl = &udc->ctrl;
1715 _nbu2ss_read_request_data(udc, (u32 *)p_ctrl);
1716
1717 /* ep0 state control */
1718 if (p_ctrl->wLength == 0) {
1719 udc->ep0state = EP0_IN_STATUS_PHASE;
1720
1721 } else {
1722 if (p_ctrl->bRequestType & USB_DIR_IN)
1723 udc->ep0state = EP0_IN_DATA_PHASE;
1724 else
1725 udc->ep0state = EP0_OUT_DATA_PHASE;
1726 }
1727
1728 if ((p_ctrl->bRequestType & USB_TYPE_MASK) == USB_TYPE_STANDARD) {
1729 switch (p_ctrl->bRequest) {
1730 case USB_REQ_GET_STATUS:
1731 nret = std_req_get_status(udc);
1732 bcall_back = FALSE;
1733 break;
1734
1735 case USB_REQ_CLEAR_FEATURE:
1736 nret = std_req_clear_feature(udc);
1737 bcall_back = FALSE;
1738 break;
1739
1740 case USB_REQ_SET_FEATURE:
1741 nret = std_req_set_feature(udc);
1742 bcall_back = FALSE;
1743 break;
1744
1745 case USB_REQ_SET_ADDRESS:
1746 nret = std_req_set_address(udc);
1747 bcall_back = FALSE;
1748 break;
1749
1750 case USB_REQ_SET_CONFIGURATION:
1751 nret = std_req_set_configuration(udc);
1752 break;
1753
1754 default:
1755 break;
1756 }
1757 }
1758
5a602ac4 1759 if (!bcall_back) {
33aa8d45
MD		 1760 if (udc->ep0state == EP0_IN_STATUS_PHASE) {
1761 if (nret >= 0) {
1762 /*--------------------------------------*/
1763 /* Status Stage */
1764 nret = EP0_send_NULL(udc, TRUE);
1765 }
1766 }
1767
1768 } else {
1769 spin_unlock(&udc->lock);
1770 nret = udc->driver->setup(&udc->gadget, &udc->ctrl);
1771 spin_lock(&udc->lock);
1772 }
1773
1774 if (nret < 0)
1775 udc->ep0state = EP0_IDLE;
1776
1777 return nret;
1778}
1779
1780/*-------------------------------------------------------------------------*/
1781static inline int _nbu2ss_ep0_in_data_stage(struct nbu2ss_udc *udc)
1782{
1783 int nret;
1784 struct nbu2ss_req *req;
1785 struct nbu2ss_ep *ep = &udc->ep[0];
1786
1787 if (list_empty(&ep->queue))
1788 req = NULL;
1789 else
1790 req = list_entry(ep->queue.next, struct nbu2ss_req, queue);
1791
706eb8cf 1792 if (!req)
33aa8d45
MD		 1793 req = &udc->ep0_req;
1794
1795 req->req.actual += req->div_len;
1796 req->div_len = 0;
1797
f2b29165 1798 nret = _nbu2ss_ep0_in_transfer(udc, req);
33aa8d45
MD		 1799 if (nret == 0) {
1800 udc->ep0state = EP0_OUT_STATUS_PAHSE;
1801 EP0_receive_NULL(udc, TRUE);
1802 }
1803
1804 return 0;
1805}
1806
1807/*-------------------------------------------------------------------------*/
1808static inline int _nbu2ss_ep0_out_data_stage(struct nbu2ss_udc *udc)
1809{
1810 int nret;
1811 struct nbu2ss_req *req;
1812 struct nbu2ss_ep *ep = &udc->ep[0];
1813
1814 if (list_empty(&ep->queue))
1815 req = NULL;
1816 else
1817 req = list_entry(ep->queue.next, struct nbu2ss_req, queue);
1818
706eb8cf 1819 if (!req)
33aa8d45
MD		 1820 req = &udc->ep0_req;
1821
f2b29165 1822 nret = _nbu2ss_ep0_out_transfer(udc, req);
33aa8d45
MD		 1823 if (nret == 0) {
1824 udc->ep0state = EP0_IN_STATUS_PHASE;
1825 EP0_send_NULL(udc, TRUE);
1826
1827 } else if (nret < 0) {
1828 _nbu2ss_bitset(&udc->p_regs->EP0_CONTROL, EP0_BCLR);
1829 req->req.status = nret;
1830 }
1831
1832 return 0;
1833}
1834
1835/*-------------------------------------------------------------------------*/
1836static inline int _nbu2ss_ep0_status_stage(struct nbu2ss_udc *udc)
1837{
1838 struct nbu2ss_req *req;
1839 struct nbu2ss_ep *ep = &udc->ep[0];
1840
1841 if (list_empty(&ep->queue))
1842 req = NULL;
1843 else
1844 req = list_entry(ep->queue.next, struct nbu2ss_req, queue);
1845
706eb8cf 1846 if (!req) {
33aa8d45
MD		 1847 req = &udc->ep0_req;
1848 if (req->req.complete)
1849 req->req.complete(&ep->ep, &req->req);
1850
1851 } else {
1852 if (req->req.complete)
1853 _nbu2ss_ep_done(ep, req, 0);
1854 }
1855
1856 udc->ep0state = EP0_IDLE;
1857
1858 return 0;
1859}
1860
1861/*-------------------------------------------------------------------------*/
1862static inline void _nbu2ss_ep0_int(struct nbu2ss_udc *udc)
1863{
1864 int i;
1865 u32 status;
1866 u32 intr;
1867 int nret = -1;
1868
1869 status = _nbu2ss_readl(&udc->p_regs->EP0_STATUS);
1870 intr = status & EP0_STATUS_RW_BIT;
1871 _nbu2ss_writel(&udc->p_regs->EP0_STATUS, ~(u32)intr);
1872
1873 status &= (SETUP_INT | EP0_IN_INT | EP0_OUT_INT
1874 | STG_END_INT | EP0_OUT_NULL_INT);
1875
1876 if (status == 0) {
93275c80
HM		 1877 dev_info(udc->dev, "%s Not Decode Interrupt\n", __func__);
1878 dev_info(udc->dev, "EP0_STATUS = 0x%08x\n", intr);
33aa8d45
MD		 1879 return;
1880 }
1881
1882 if (udc->gadget.speed == USB_SPEED_UNKNOWN)
1883 udc->gadget.speed = _nbu2ss_get_speed(udc);
1884
1885 for (i = 0; i < EP0_END_XFER; i++) {
1886 switch (udc->ep0state) {
1887 case EP0_IDLE:
1888 if (status & SETUP_INT) {
1889 status = 0;
1890 nret = _nbu2ss_decode_request(udc);
1891 }
1892 break;
1893
1894 case EP0_IN_DATA_PHASE:
1895 if (status & EP0_IN_INT) {
1896 status &= ~EP0_IN_INT;
1897 nret = _nbu2ss_ep0_in_data_stage(udc);
1898 }
1899 break;
1900
1901 case EP0_OUT_DATA_PHASE:
1902 if (status & EP0_OUT_INT) {
1903 status &= ~EP0_OUT_INT;
1904 nret = _nbu2ss_ep0_out_data_stage(udc);
1905 }
1906 break;
1907
1908 case EP0_IN_STATUS_PHASE:
1909 if ((status & STG_END_INT) || (status & SETUP_INT)) {
1910 status &= ~(STG_END_INT | EP0_IN_INT);
1911 nret = _nbu2ss_ep0_status_stage(udc);
1912 }
1913 break;
1914
1915 case EP0_OUT_STATUS_PAHSE:
1916 if ((status & STG_END_INT)
1917 || (status & SETUP_INT)
1918 || (status & EP0_OUT_NULL_INT)) {
1919 status &= ~(STG_END_INT
1920 | EP0_OUT_INT
1921 | EP0_OUT_NULL_INT);
1922
1923 nret = _nbu2ss_ep0_status_stage(udc);
1924 }
1925
1926 break;
1927
1928 default:
1929 status = 0;
1930 break;
1931 }
1932
1933 if (status == 0)
1934 break;
1935 }
1936
1937 if (nret < 0) {
1938 /* Send Stall */
1939 _nbu2ss_set_endpoint_stall(udc, 0, TRUE);
1940 }
1941}
1942
1943/*-------------------------------------------------------------------------*/
1944static void _nbu2ss_ep_done(
1945 struct nbu2ss_ep *ep,
1946 struct nbu2ss_req *req,
1947 int status)
1948{
1949 struct nbu2ss_udc *udc = ep->udc;
1950
1951 list_del_init(&req->queue);
1952
1953 if (status == -ECONNRESET)
1954 _nbu2ss_fifo_flush(udc, ep);
1955
1956 if (likely(req->req.status == -EINPROGRESS))
1957 req->req.status = status;
1958
1959 if (ep->stalled)
1960 _nbu2ss_epn_set_stall(udc, ep);
1961 else {
1962 if (!list_empty(&ep->queue))
1963 _nbu2ss_restert_transfer(ep);
1964 }
1965
1966#ifdef USE_DMA
1967 if ((ep->direct == USB_DIR_OUT) && (ep->epnum > 0) &&
1968 (req->req.dma != 0))
1969 _nbu2ss_dma_unmap_single(udc, ep, req, USB_DIR_OUT);
1970#endif
1971
1972 spin_unlock(&udc->lock);
1973 req->req.complete(&ep->ep, &req->req);
1974 spin_lock(&udc->lock);
1975}
1976
1977/*-------------------------------------------------------------------------*/
1978static inline void _nbu2ss_epn_in_int(
1979 struct nbu2ss_udc *udc,
1980 struct nbu2ss_ep *ep,
1981 struct nbu2ss_req *req)
1982{
1983 int result = 0;
1984 u32 status;
1985
f6ef6c09 1986 struct fc_regs *preg = udc->p_regs;
33aa8d45
MD		 1987
1988 if (req->dma_flag)
1989 return; /* DMA is forwarded */
1990
1991 req->req.actual += req->div_len;
1992 req->div_len = 0;
1993
1994 if (req->req.actual != req->req.length) {
1995 /*---------------------------------------------------------*/
1996 /* remainder of data */
1997 result = _nbu2ss_epn_in_transfer(udc, ep, req);
1998
1999 } else {
5cbca957 2000 if (req->zero && ((req->req.actual % ep->ep.maxpacket) == 0)) {
33aa8d45
MD		 2001
2002 status =
2003 _nbu2ss_readl(&preg->EP_REGS[ep->epnum-1].EP_STATUS);
2004
2005 if ((status & EPn_IN_FULL) == 0) {
2006 /*-----------------------------------------*/
2007 /* 0 Length Packet */
666e9084 2008 req->zero = false;
33aa8d45
MD		 2009 _nbu2ss_zero_len_pkt(udc, ep->epnum);
2010 }
2011 return;
2012 }
2013 }
2014
2015 if (result <= 0) {
2016 /*---------------------------------------------------------*/
2017 /* Complete */
2018 _nbu2ss_ep_done(ep, req, result);
2019 }
2020}
2021
2022/*-------------------------------------------------------------------------*/
2023static inline void _nbu2ss_epn_out_int(
2024 struct nbu2ss_udc *udc,
2025 struct nbu2ss_ep *ep,
2026 struct nbu2ss_req *req)
2027{
2028 int result;
2029
2030 result = _nbu2ss_epn_out_transfer(udc, ep, req);
2031 if (result <= 0)
2032 _nbu2ss_ep_done(ep, req, result);
33aa8d45
MD		 2033}
2034
2035/*-------------------------------------------------------------------------*/
2036static inline void _nbu2ss_epn_in_dma_int(
2037 struct nbu2ss_udc *udc,
2038 struct nbu2ss_ep *ep,
2039 struct nbu2ss_req *req)
2040{
2041 u32 mpkt;
2042 u32 size;
2043 struct usb_request *preq;
2044
2045 preq = &req->req;
2046
5a602ac4 2047 if (!req->dma_flag)
33aa8d45
MD		 2048 return;
2049
2050 preq->actual += req->div_len;
2051 req->div_len = 0;
2052 req->dma_flag = FALSE;
2053
2054#ifdef USE_DMA
2055 _nbu2ss_dma_unmap_single(udc, ep, req, USB_DIR_IN);
2056#endif
2057
2058 if (preq->actual != preq->length) {
2059 _nbu2ss_epn_in_transfer(udc, ep, req);
2060 } else {
2061 mpkt = ep->ep.maxpacket;
2062 size = preq->actual % mpkt;
2063 if (size > 0) {
2064 if (((preq->actual & 0x03) == 0) && (size < mpkt))
2065 _nbu2ss_ep_in_end(udc, ep->epnum, 0, 0);
2066 } else {
2067 _nbu2ss_epn_in_int(udc, ep, req);
2068 }
2069 }
33aa8d45
MD		 2070}
2071
2072/*-------------------------------------------------------------------------*/
2073static inline void _nbu2ss_epn_out_dma_int(
2074 struct nbu2ss_udc *udc,
2075 struct nbu2ss_ep *ep,
2076 struct nbu2ss_req *req)
2077{
2078 int i;
2079 u32 num;
2080 u32 dmacnt, ep_dmacnt;
2081 u32 mpkt;
f6ef6c09 2082 struct fc_regs *preg = udc->p_regs;
33aa8d45
MD		 2083
2084 num = ep->epnum - 1;
2085
2086 if (req->req.actual == req->req.length) {
5cbca957 2087 if ((req->req.length % ep->ep.maxpacket) && !req->zero) {
33aa8d45
MD		 2088 req->div_len = 0;
2089 req->dma_flag = FALSE;
2090 _nbu2ss_ep_done(ep, req, 0);
2091 return;
2092 }
2093 }
2094
2095 ep_dmacnt = _nbu2ss_readl(&preg->EP_REGS[num].EP_LEN_DCNT)
2096 & EPn_DMACNT;
2097 ep_dmacnt >>= 16;
2098
2099 for (i = 0; i < EPC_PLL_LOCK_COUNT; i++) {
2100 dmacnt = _nbu2ss_readl(&preg->EP_DCR[num].EP_DCR1)
2101 & DCR1_EPn_DMACNT;
2102 dmacnt >>= 16;
2103 if (ep_dmacnt == dmacnt)
2104 break;
2105 }
2106
2107 _nbu2ss_bitclr(&preg->EP_DCR[num].EP_DCR1, DCR1_EPn_REQEN);
2108
2109 if (dmacnt != 0) {
2110 mpkt = ep->ep.maxpacket;
2111 if ((req->div_len % mpkt) == 0)
2112 req->div_len -= mpkt * dmacnt;
2113 }
2114
2115 if ((req->req.actual % ep->ep.maxpacket) > 0) {
2116 if (req->req.actual == req->div_len) {
2117 req->div_len = 0;
2118 req->dma_flag = FALSE;
2119 _nbu2ss_ep_done(ep, req, 0);
2120 return;
2121 }
2122 }
2123
2124 req->req.actual += req->div_len;
2125 req->div_len = 0;
2126 req->dma_flag = FALSE;
2127
2128 _nbu2ss_epn_out_int(udc, ep, req);
2129}
2130
2131/*-------------------------------------------------------------------------*/
2132static inline void _nbu2ss_epn_int(struct nbu2ss_udc *udc, u32 epnum)
2133{
2134 u32 num;
2135 u32 status;
2136
2137 struct nbu2ss_req *req;
2138 struct nbu2ss_ep *ep = &udc->ep[epnum];
2139
2140 num = epnum - 1;
2141
2142 /* Interrupt Status */
2143 status = _nbu2ss_readl(&udc->p_regs->EP_REGS[num].EP_STATUS);
2144
2145 /* Interrupt Clear */
2146 _nbu2ss_writel(&udc->p_regs->EP_REGS[num].EP_STATUS, ~(u32)status);
2147
2148 if (list_empty(&ep->queue))
2149 req = NULL;
2150 else
2151 req = list_entry(ep->queue.next, struct nbu2ss_req, queue);
2152
706eb8cf 2153 if (!req) {
f02935c5 2154 /* pr_warn("=== %s(%d) req == NULL\n", __func__, epnum); */
33aa8d45
MD		 2155 return;
2156 }
2157
2158 if (status & EPn_OUT_END_INT) {
2159 status &= ~EPn_OUT_INT;
2160 _nbu2ss_epn_out_dma_int(udc, ep, req);
2161 }
2162
2163 if (status & EPn_OUT_INT)
2164 _nbu2ss_epn_out_int(udc, ep, req);
2165
2166 if (status & EPn_IN_END_INT) {
2167 status &= ~EPn_IN_INT;
2168 _nbu2ss_epn_in_dma_int(udc, ep, req);
2169 }
2170
2171 if (status & EPn_IN_INT)
2172 _nbu2ss_epn_in_int(udc, ep, req);
2173}
2174
2175/*-------------------------------------------------------------------------*/
2176static inline void _nbu2ss_ep_int(struct nbu2ss_udc *udc, u32 epnum)
2177{
2178 if (epnum == 0)
2179 _nbu2ss_ep0_int(udc);
2180 else
2181 _nbu2ss_epn_int(udc, epnum);
2182}
2183
2184/*-------------------------------------------------------------------------*/
2185static void _nbu2ss_ep0_enable(struct nbu2ss_udc *udc)
2186{
2187 _nbu2ss_bitset(&udc->p_regs->EP0_CONTROL, (EP0_AUTO | EP0_BCLR));
2188 _nbu2ss_writel(&udc->p_regs->EP0_INT_ENA, EP0_INT_EN_BIT);
33aa8d45
MD		 2189}
2190
33aa8d45
MD		 2191/*-------------------------------------------------------------------------*/
2192static int _nbu2ss_nuke(struct nbu2ss_udc *udc,
2193 struct nbu2ss_ep *ep,
2194 int status)
2195{
2196 struct nbu2ss_req *req;
2197
2198 /* Endpoint Disable */
2199 _nbu2ss_epn_exit(udc, ep);
2200
2201 /* DMA Disable */
2202 _nbu2ss_ep_dma_exit(udc, ep);
2203
2204 if (list_empty(&ep->queue))
2205 return 0;
2206
2207 /* called with irqs blocked */
ca3d253e 2208 list_for_each_entry(req, &ep->queue, queue) {
33aa8d45
MD		 2209 _nbu2ss_ep_done(ep, req, status);
2210 }
2211
2212 return 0;
2213}
2214
2215/*-------------------------------------------------------------------------*/
2216static void _nbu2ss_quiesce(struct nbu2ss_udc *udc)
2217{
2218 struct nbu2ss_ep *ep;
2219
2220 udc->gadget.speed = USB_SPEED_UNKNOWN;
2221
2222 _nbu2ss_nuke(udc, &udc->ep[0], -ESHUTDOWN);
2223
2224 /* Endpoint n */
2225 list_for_each_entry(ep, &udc->gadget.ep_list, ep.ep_list) {
2226 _nbu2ss_nuke(udc, ep, -ESHUTDOWN);
2227 }
2228}
2229
2230/*-------------------------------------------------------------------------*/
2231static int _nbu2ss_pullup(struct nbu2ss_udc *udc, int is_on)
2232{
2233 u32 reg_dt;
2234
33aa8d45
MD		 2235 if (udc->vbus_active == 0)
2236 return -ESHUTDOWN;
2237
2238 if (is_on) {
2239 /* D+ Pullup */
33aa8d45
MD		 2240 if (udc->driver) {
2241 reg_dt = (_nbu2ss_readl(&udc->p_regs->USB_CONTROL)
2242 | PUE2) & ~(u32)CONNECTB;
2243
2244 _nbu2ss_writel(&udc->p_regs->USB_CONTROL, reg_dt);
2245 }
2246
2247 } else {
2248 /* D+ Pulldown */
33aa8d45
MD		 2249 reg_dt = (_nbu2ss_readl(&udc->p_regs->USB_CONTROL) | CONNECTB)
2250 & ~(u32)PUE2;
2251
2252 _nbu2ss_writel(&udc->p_regs->USB_CONTROL, reg_dt);
2253 udc->gadget.speed = USB_SPEED_UNKNOWN;
2254 }
2255
2256 return 0;
2257}
2258
2259/*-------------------------------------------------------------------------*/
2260static void _nbu2ss_fifo_flush(struct nbu2ss_udc *udc, struct nbu2ss_ep *ep)
2261{
f6ef6c09 2262 struct fc_regs *p = udc->p_regs;
33aa8d45
MD		 2263
2264 if (udc->vbus_active == 0)
2265 return;
2266
2267 if (ep->epnum == 0) {
2268 /* EP0 */
2269 _nbu2ss_bitset(&p->EP0_CONTROL, EP0_BCLR);
2270
2271 } else {
2272 /* EPn */
2273 _nbu2ss_ep_dma_abort(udc, ep);
2274 _nbu2ss_bitset(&p->EP_REGS[ep->epnum - 1].EP_CONTROL, EPn_BCLR);
2275 }
2276}
2277
2278/*-------------------------------------------------------------------------*/
2279static int _nbu2ss_enable_controller(struct nbu2ss_udc *udc)
2280{
2281 int waitcnt = 0;
2282
2283 if (udc->udc_enabled)
2284 return 0;
2285
33aa8d45
MD		 2286 /*
2287 Reset
2288 */
2289 _nbu2ss_bitset(&udc->p_regs->EPCTR, (DIRPD | EPC_RST));
2290 udelay(EPC_RST_DISABLE_TIME); /* 1us wait */
2291
2292 _nbu2ss_bitclr(&udc->p_regs->EPCTR, DIRPD);
2293 mdelay(EPC_DIRPD_DISABLE_TIME); /* 1ms wait */
2294
2295 _nbu2ss_bitclr(&udc->p_regs->EPCTR, EPC_RST);
2296
2297 _nbu2ss_writel(&udc->p_regs->AHBSCTR, WAIT_MODE);
2298
33aa8d45
MD		 2299 _nbu2ss_writel(&udc->p_regs->AHBMCTR,
2300 HBUSREQ_MODE | HTRANS_MODE | WBURST_TYPE);
2301
2302 while (!(_nbu2ss_readl(&udc->p_regs->EPCTR) & PLL_LOCK)) {
2303 waitcnt++;
2304 udelay(1); /* 1us wait */
2305 if (waitcnt == EPC_PLL_LOCK_COUNT) {
88689279 2306 dev_err(udc->dev, "*** Reset Cancel failed\n");
33aa8d45
MD		 2307 return -EINVAL;
2308 }
3e2bb64d 2309 }
33aa8d45 2310
33aa8d45
MD		 2311 _nbu2ss_bitset(&udc->p_regs->UTMI_CHARACTER_1, USB_SQUSET);
2312
2313 _nbu2ss_bitset(&udc->p_regs->USB_CONTROL, (INT_SEL | SOF_RCV));
2314
2315 /* EP0 */
2316 _nbu2ss_ep0_enable(udc);
2317
2318 /* USB Interrupt Enable */
2319 _nbu2ss_bitset(&udc->p_regs->USB_INT_ENA, USB_INT_EN_BIT);
2320
2321 udc->udc_enabled = TRUE;
2322
2323 return 0;
2324}
2325
33aa8d45
MD		 2326/*-------------------------------------------------------------------------*/
2327static void _nbu2ss_reset_controller(struct nbu2ss_udc *udc)
2328{
2329 _nbu2ss_bitset(&udc->p_regs->EPCTR, EPC_RST);
2330 _nbu2ss_bitclr(&udc->p_regs->EPCTR, EPC_RST);
2331}
2332
2333/*-------------------------------------------------------------------------*/
2334static void _nbu2ss_disable_controller(struct nbu2ss_udc *udc)
2335{
2336 if (udc->udc_enabled) {
2337 udc->udc_enabled = FALSE;
2338 _nbu2ss_reset_controller(udc);
2339 _nbu2ss_bitset(&udc->p_regs->EPCTR, (DIRPD | EPC_RST));
2340 }
33aa8d45
MD		 2341}
2342
2343/*-------------------------------------------------------------------------*/
2344static inline void _nbu2ss_check_vbus(struct nbu2ss_udc *udc)
2345{
2346 int nret;
2347 u32 reg_dt;
2348
2349 /* chattering */
2350 mdelay(VBUS_CHATTERING_MDELAY); /* wait (ms) */
2351
2352 /* VBUS ON Check*/
2353 reg_dt = gpio_get_value(VBUS_VALUE);
2354 if (reg_dt == 0) {
2355
2356 udc->linux_suspended = 0;
2357
2358 _nbu2ss_reset_controller(udc);
93275c80 2359 dev_info(udc->dev, " ----- VBUS OFF\n");
33aa8d45
MD		 2360
2361 if (udc->vbus_active == 1) {
2362 /* VBUS OFF */
2363 udc->vbus_active = 0;
2364 if (udc->usb_suspended) {
2365 udc->usb_suspended = 0;
2366 /* _nbu2ss_reset_controller(udc); */
2367 }
2368 udc->devstate = USB_STATE_NOTATTACHED;
2369
2370 _nbu2ss_quiesce(udc);
2371 if (udc->driver) {
2372 spin_unlock(&udc->lock);
2373 udc->driver->disconnect(&udc->gadget);
2374 spin_lock(&udc->lock);
2375 }
2376
2377 _nbu2ss_disable_controller(udc);
2378 }
2379 } else {
2380 mdelay(5); /* wait (5ms) */
2381 reg_dt = gpio_get_value(VBUS_VALUE);
2382 if (reg_dt == 0)
2383 return;
2384
93275c80 2385 dev_info(udc->dev, " ----- VBUS ON\n");
33aa8d45
MD		 2386
2387 if (udc->linux_suspended)
2388 return;
2389
2390 if (udc->vbus_active == 0) {
2391 /* VBUS ON */
2392 udc->vbus_active = 1;
2393 udc->devstate = USB_STATE_POWERED;
2394
2395 nret = _nbu2ss_enable_controller(udc);
2396 if (nret < 0) {
2397 _nbu2ss_disable_controller(udc);
2398 udc->vbus_active = 0;
2399 return;
2400 }
2401
2402 _nbu2ss_pullup(udc, 1);
2403
2404#ifdef UDC_DEBUG_DUMP
2405 _nbu2ss_dump_register(udc);
2406#endif /* UDC_DEBUG_DUMP */
2407
2408 } else {
2409 if (udc->devstate == USB_STATE_POWERED)
2410 _nbu2ss_pullup(udc, 1);
2411 }
2412 }
33aa8d45
MD		 2413}
2414
2415/*-------------------------------------------------------------------------*/
2416static inline void _nbu2ss_int_bus_reset(struct nbu2ss_udc *udc)
2417{
2418 udc->devstate = USB_STATE_DEFAULT;
2419 udc->remote_wakeup = 0;
2420
2421 _nbu2ss_quiesce(udc);
2422
2423 udc->ep0state = EP0_IDLE;
2424}
2425
2426/*-------------------------------------------------------------------------*/
2427static inline void _nbu2ss_int_usb_resume(struct nbu2ss_udc *udc)
2428{
2429 if (udc->usb_suspended == 1) {
2430 udc->usb_suspended = 0;
2431 if (udc->driver && udc->driver->resume) {
2432 spin_unlock(&udc->lock);
2433 udc->driver->resume(&udc->gadget);
2434 spin_lock(&udc->lock);
2435 }
2436 }
2437}
2438
2439/*-------------------------------------------------------------------------*/
2440static inline void _nbu2ss_int_usb_suspend(struct nbu2ss_udc *udc)
2441{
2442 u32 reg_dt;
2443
2444 if (udc->usb_suspended == 0) {
2445 reg_dt = gpio_get_value(VBUS_VALUE);
2446
2447 if (reg_dt == 0)
2448 return;
2449
2450 udc->usb_suspended = 1;
2451 if (udc->driver && udc->driver->suspend) {
2452 spin_unlock(&udc->lock);
2453 udc->driver->suspend(&udc->gadget);
2454 spin_lock(&udc->lock);
2455 }
2456
2457 _nbu2ss_bitset(&udc->p_regs->USB_CONTROL, SUSPEND);
2458 }
2459}
2460
2461/*-------------------------------------------------------------------------*/
2462/* VBUS (GPIO153) Interrupt */
2463static irqreturn_t _nbu2ss_vbus_irq(int irq, void *_udc)
2464{
2465 struct nbu2ss_udc *udc = (struct nbu2ss_udc *)_udc;
2466
2467 spin_lock(&udc->lock);
2468 _nbu2ss_check_vbus(udc);
2469 spin_unlock(&udc->lock);
2470
2471 return IRQ_HANDLED;
2472}
2473
2474/*-------------------------------------------------------------------------*/
2475/* Interrupt (udc) */
2476static irqreturn_t _nbu2ss_udc_irq(int irq, void *_udc)
2477{
2478 u8 suspend_flag = 0;
2479 u32 status;
2480 u32 epnum, int_bit;
2481
2482 struct nbu2ss_udc *udc = (struct nbu2ss_udc *)_udc;
f6ef6c09 2483 struct fc_regs *preg = udc->p_regs;
33aa8d45
MD		 2484
2485 if (gpio_get_value(VBUS_VALUE) == 0) {
2486 _nbu2ss_writel(&preg->USB_INT_STA, ~USB_INT_STA_RW);
2487 _nbu2ss_writel(&preg->USB_INT_ENA, 0);
2488 return IRQ_HANDLED;
2489 }
2490
2491 spin_lock(&udc->lock);
2492
2493 for (;;) {
2494 if (gpio_get_value(VBUS_VALUE) == 0) {
2495 _nbu2ss_writel(&preg->USB_INT_STA, ~USB_INT_STA_RW);
2496 _nbu2ss_writel(&preg->USB_INT_ENA, 0);
2497 status = 0;
2498 } else
2499 status = _nbu2ss_readl(&preg->USB_INT_STA);
2500
2501 if (status == 0)
2502 break;
2503
2504 _nbu2ss_writel(&preg->USB_INT_STA, ~(status & USB_INT_STA_RW));
2505
2506 if (status & USB_RST_INT) {
2507 /* USB Reset */
2508 _nbu2ss_int_bus_reset(udc);
2509 }
2510
2511 if (status & RSUM_INT) {
2512 /* Resume */
2513 _nbu2ss_int_usb_resume(udc);
2514 }
2515
2516 if (status & SPND_INT) {
2517 /* Suspend */
2518 suspend_flag = 1;
2519 }
2520
2521 if (status & EPn_INT) {
2522 /* EP INT */
2523 int_bit = status >> 8;
2524
2525 for (epnum = 0; epnum < NUM_ENDPOINTS; epnum++) {
2526
2527 if (0x01 & int_bit)
2528 _nbu2ss_ep_int(udc, epnum);
2529
2530 int_bit >>= 1;
2531
2532 if (int_bit == 0)
2533 break;
2534 }
2535 }
2536 }
2537
2538 if (suspend_flag)
2539 _nbu2ss_int_usb_suspend(udc);
2540
2541 spin_unlock(&udc->lock);
2542
2543 return IRQ_HANDLED;
2544}
2545
2546/*-------------------------------------------------------------------------*/
2547/* usb_ep_ops */
2548static int nbu2ss_ep_enable(
2549 struct usb_ep *_ep,
2550 const struct usb_endpoint_descriptor *desc)
2551{
2552 u8 ep_type;
2553 unsigned long flags;
2554
2555 struct nbu2ss_ep *ep;
2556 struct nbu2ss_udc *udc;
2557
706eb8cf 2558 if ((!_ep) || (!desc)) {
88689279 2559 pr_err(" *** %s, bad param\n", __func__);
33aa8d45
MD		 2560 return -EINVAL;
2561 }
2562
2563 ep = container_of(_ep, struct nbu2ss_ep, ep);
706eb8cf 2564 if ((!ep) || (!ep->udc)) {
88689279 2565 pr_err(" *** %s, ep == NULL !!\n", __func__);
33aa8d45
MD		 2566 return -EINVAL;
2567 }
2568
3f3efca9 2569 ep_type = usb_endpoint_type(desc);
33aa8d45
MD		 2570 if ((ep_type == USB_ENDPOINT_XFER_CONTROL)
2571 || (ep_type == USB_ENDPOINT_XFER_ISOC)) {
2572
88689279 2573 pr_err(" *** %s, bat bmAttributes\n", __func__);
33aa8d45
MD		 2574 return -EINVAL;
2575 }
2576
2577 udc = ep->udc;
2578 if (udc->vbus_active == 0)
2579 return -ESHUTDOWN;
2580
706eb8cf 2581 if ((!udc->driver)
33aa8d45
MD		 2582 || (udc->gadget.speed == USB_SPEED_UNKNOWN)) {
2583
88689279 2584 dev_err(ep->udc->dev, " *** %s, udc !!\n", __func__);
33aa8d45
MD		 2585 return -ESHUTDOWN;
2586 }
2587
2588 spin_lock_irqsave(&udc->lock, flags);
2589
2590 ep->desc = desc;
3f3efca9 2591 ep->epnum = usb_endpoint_num(desc);
33aa8d45
MD		 2592 ep->direct = desc->bEndpointAddress & USB_ENDPOINT_DIR_MASK;
2593 ep->ep_type = ep_type;
2594 ep->wedged = 0;
2595 ep->halted = FALSE;
2596 ep->stalled = FALSE;
2597
2598 ep->ep.maxpacket = le16_to_cpu(desc->wMaxPacketSize);
2599
2600 /* DMA setting */
2601 _nbu2ss_ep_dma_init(udc, ep);
2602
2603 /* Endpoint setting */
2604 _nbu2ss_ep_init(udc, ep);
2605
2606 spin_unlock_irqrestore(&udc->lock, flags);
2607
2608 return 0;
2609}
2610
2611/*-------------------------------------------------------------------------*/
2612static int nbu2ss_ep_disable(struct usb_ep *_ep)
2613{
2614 struct nbu2ss_ep *ep;
2615 struct nbu2ss_udc *udc;
2616 unsigned long flags;
2617
706eb8cf 2618 if (!_ep) {
88689279 2619 pr_err(" *** %s, bad param\n", __func__);
33aa8d45
MD		 2620 return -EINVAL;
2621 }
2622
2623 ep = container_of(_ep, struct nbu2ss_ep, ep);
706eb8cf 2624 if ((!ep) || (!ep->udc)) {
88689279 2625 pr_err("udc: *** %s, ep == NULL !!\n", __func__);
33aa8d45
MD		 2626 return -EINVAL;
2627 }
2628
2629 udc = ep->udc;
2630 if (udc->vbus_active == 0)
2631 return -ESHUTDOWN;
2632
2633 spin_lock_irqsave(&udc->lock, flags);
2634 _nbu2ss_nuke(udc, ep, -EINPROGRESS); /* dequeue request */
2635 spin_unlock_irqrestore(&udc->lock, flags);
2636
2637 return 0;
2638}
2639
2640/*-------------------------------------------------------------------------*/
2641static struct usb_request *nbu2ss_ep_alloc_request(
2642 struct usb_ep *ep,
2643 gfp_t gfp_flags)
2644{
2645 struct nbu2ss_req *req;
2646
2647 req = kzalloc(sizeof(*req), gfp_flags);
2648 if (!req)
2649 return 0;
2650
2651#ifdef USE_DMA
2652 req->req.dma = DMA_ADDR_INVALID;
2653#endif
2654 INIT_LIST_HEAD(&req->queue);
2655
2656 return &req->req;
2657}
2658
2659/*-------------------------------------------------------------------------*/
2660static void nbu2ss_ep_free_request(
2661 struct usb_ep *_ep,
2662 struct usb_request *_req)
2663{
2664 struct nbu2ss_req *req;
2665
706eb8cf 2666 if (_req) {
33aa8d45
MD		 2667 req = container_of(_req, struct nbu2ss_req, req);
2668
a5a89d7a 2669 kfree(req);
33aa8d45
MD		 2670 }
2671}
2672
2673/*-------------------------------------------------------------------------*/
2674static int nbu2ss_ep_queue(
2675 struct usb_ep *_ep,
2676 struct usb_request *_req,
2677 gfp_t gfp_flags)
2678{
2679 struct nbu2ss_req *req;
2680 struct nbu2ss_ep *ep;
2681 struct nbu2ss_udc *udc;
2682 unsigned long flags;
2683 bool bflag;
2684 int result = -EINVAL;
2685
2686 /* catch various bogus parameters */
706eb8cf
RTD		 2687 if ((!_ep) || (!_req)) {
2688 if (!_ep)
88689279 2689 pr_err("udc: %s --- _ep == NULL\n", __func__);
33aa8d45 2690
706eb8cf 2691 if (!_req)
88689279 2692 pr_err("udc: %s --- _req == NULL\n", __func__);
33aa8d45
MD		 2693
2694 return -EINVAL;
2695 }
2696
2697 req = container_of(_req, struct nbu2ss_req, req);
2698 if (unlikely
2699 (!_req->complete || !_req->buf
2700 || !list_empty(&req->queue))) {
2701
2702 if (!_req->complete)
88689279 2703 pr_err("udc: %s --- !_req->complete\n", __func__);
33aa8d45
MD		 2704
2705 if (!_req->buf)
88689279 2706 pr_err("udc:%s --- !_req->buf\n", __func__);
33aa8d45
MD		 2707
2708 if (!list_empty(&req->queue))
88689279 2709 pr_err("%s --- !list_empty(&req->queue)\n", __func__);
33aa8d45
MD		 2710
2711 return -EINVAL;
2712 }
2713
2714 ep = container_of(_ep, struct nbu2ss_ep, ep);
2715 udc = ep->udc;
2716
33aa8d45 2717 if (udc->vbus_active == 0) {
93275c80 2718 dev_info(udc->dev, "Can't ep_queue (VBUS OFF)\n");
33aa8d45
MD		 2719 return -ESHUTDOWN;
2720 }
2721
2722 if (unlikely(!udc->driver)) {
88689279
HM		 2723 dev_err(udc->dev, "%s, bogus device state %p\n", __func__,
2724 udc->driver);
33aa8d45
MD		 2725 return -ESHUTDOWN;
2726 }
2727
2728 spin_lock_irqsave(&udc->lock, flags);
2729
2730#ifdef USE_DMA
2731 if ((u32)req->req.buf & 0x3)
2732 req->unaligned = TRUE;
2733 else
2734 req->unaligned = FALSE;
2735
2736 if (req->unaligned) {
706eb8cf 2737 if (!ep->virt_buf)
33aa8d45
MD		 2738 ep->virt_buf = (u8 *)dma_alloc_coherent(
2739 NULL, PAGE_SIZE,
4a0721bf 2740 &ep->phys_buf, GFP_ATOMIC | GFP_DMA);
33aa8d45
MD		 2741 if (ep->epnum > 0) {
2742 if (ep->direct == USB_DIR_IN)
2743 memcpy(ep->virt_buf, req->req.buf,
2744 req->req.length);
2745 }
2746 }
2747
2748 if ((ep->epnum > 0) && (ep->direct == USB_DIR_OUT) &&
2749 (req->req.dma != 0))
2750 _nbu2ss_dma_map_single(udc, ep, req, USB_DIR_OUT);
2751#endif
2752
2753 _req->status = -EINPROGRESS;
2754 _req->actual = 0;
2755
2756 bflag = list_empty(&ep->queue);
2757 list_add_tail(&req->queue, &ep->queue);
2758
5a602ac4 2759 if (bflag && !ep->stalled) {
33aa8d45
MD		 2760
2761 result = _nbu2ss_start_transfer(udc, ep, req, FALSE);
2762 if (result < 0) {
88689279
HM		 2763 dev_err(udc->dev, " *** %s, result = %d\n", __func__,
2764 result);
33aa8d45
MD		 2765 list_del(&req->queue);
2766 } else if ((ep->epnum > 0) && (ep->direct == USB_DIR_OUT)) {
2767#ifdef USE_DMA
2768 if (req->req.length < 4 &&
2769 req->req.length == req->req.actual)
2770#else
2771 if (req->req.length == req->req.actual)
2772#endif
2773 _nbu2ss_ep_done(ep, req, result);
2774 }
2775 }
2776
2777 spin_unlock_irqrestore(&udc->lock, flags);
2778
2779 return 0;
2780}
2781
2782/*-------------------------------------------------------------------------*/
2783static int nbu2ss_ep_dequeue(
2784 struct usb_ep *_ep,
2785 struct usb_request *_req)
2786{
2787 struct nbu2ss_req *req;
2788 struct nbu2ss_ep *ep;
2789 struct nbu2ss_udc *udc;
2790 unsigned long flags;
2791
33aa8d45 2792 /* catch various bogus parameters */
706eb8cf 2793 if ((!_ep) || (!_req)) {
88689279 2794 /* pr_err("%s, bad param(1)\n", __func__); */
33aa8d45
MD		 2795 return -EINVAL;
2796 }
2797
2798 ep = container_of(_ep, struct nbu2ss_ep, ep);
2799 if (!ep) {
88689279 2800 pr_err("%s, ep == NULL !!\n", __func__);
33aa8d45
MD		 2801 return -EINVAL;
2802 }
2803
2804 udc = ep->udc;
706eb8cf 2805 if (!udc)
33aa8d45
MD		 2806 return -EINVAL;
2807
2808 spin_lock_irqsave(&udc->lock, flags);
2809
2810 /* make sure it's actually queued on this endpoint */
2811 list_for_each_entry(req, &ep->queue, queue) {
2812 if (&req->req == _req)
2813 break;
2814 }
2815 if (&req->req != _req) {
2816 spin_unlock_irqrestore(&udc->lock, flags);
2817 pr_debug("%s no queue(EINVAL)\n", __func__);
2818 return -EINVAL;
2819 }
2820
2821 _nbu2ss_ep_done(ep, req, -ECONNRESET);
2822
2823 spin_unlock_irqrestore(&udc->lock, flags);
2824
2825 return 0;
2826}
2827
2828/*-------------------------------------------------------------------------*/
2829static int nbu2ss_ep_set_halt(struct usb_ep *_ep, int value)
2830{
2831 u8 ep_adrs;
2832 unsigned long flags;
2833
2834 struct nbu2ss_ep *ep;
2835 struct nbu2ss_udc *udc;
2836
33aa8d45 2837 if (!_ep) {
88689279 2838 pr_err("%s, bad param\n", __func__);
33aa8d45
MD		 2839 return -EINVAL;
2840 }
2841
2842 ep = container_of(_ep, struct nbu2ss_ep, ep);
2843 if (!ep) {
88689279 2844 pr_err("%s, bad ep\n", __func__);
33aa8d45
MD		 2845 return -EINVAL;
2846 }
2847
2848 udc = ep->udc;
2849 if (!udc) {
88689279 2850 dev_err(ep->udc->dev, " *** %s, bad udc\n", __func__);
33aa8d45
MD		 2851 return -EINVAL;
2852 }
2853
2854 spin_lock_irqsave(&udc->lock, flags);
2855
2856 ep_adrs = ep->epnum | ep->direct;
2857 if (value == 0) {
2858 _nbu2ss_set_endpoint_stall(udc, ep_adrs, value);
2859 ep->stalled = FALSE;
2860 } else {
2861 if (list_empty(&ep->queue))
2862 _nbu2ss_epn_set_stall(udc, ep);
2863 else
2864 ep->stalled = TRUE;
2865 }
2866
2867 if (value == 0)
2868 ep->wedged = 0;
2869
2870 spin_unlock_irqrestore(&udc->lock, flags);
2871
2872 return 0;
2873}
2874
2875static int nbu2ss_ep_set_wedge(struct usb_ep *_ep)
2876{
2877 return nbu2ss_ep_set_halt(_ep, 1);
2878}
2879
2880/*-------------------------------------------------------------------------*/
2881static int nbu2ss_ep_fifo_status(struct usb_ep *_ep)
2882{
2883 u32 data;
2884 struct nbu2ss_ep *ep;
2885 struct nbu2ss_udc *udc;
2886 unsigned long flags;
f6ef6c09 2887 struct fc_regs *preg;
33aa8d45 2888
33aa8d45 2889 if (!_ep) {
88689279 2890 pr_err("%s, bad param\n", __func__);
33aa8d45
MD		 2891 return -EINVAL;
2892 }
2893
2894 ep = container_of(_ep, struct nbu2ss_ep, ep);
2895 if (!ep) {
88689279 2896 pr_err("%s, bad ep\n", __func__);
33aa8d45
MD		 2897 return -EINVAL;
2898 }
2899
2900 udc = ep->udc;
2901 if (!udc) {
88689279 2902 dev_err(ep->udc->dev, "%s, bad udc\n", __func__);
33aa8d45
MD		 2903 return -EINVAL;
2904 }
2905
2906 preg = udc->p_regs;
2907
2908 data = gpio_get_value(VBUS_VALUE);
2909 if (data == 0)
2910 return -EINVAL;
2911
2912 spin_lock_irqsave(&udc->lock, flags);
2913
2914 if (ep->epnum == 0) {
2915 data = _nbu2ss_readl(&preg->EP0_LENGTH) & EP0_LDATA;
2916
2917 } else {
2918 data = _nbu2ss_readl(&preg->EP_REGS[ep->epnum-1].EP_LEN_DCNT)
2919 & EPn_LDATA;
2920 }
2921
2922 spin_unlock_irqrestore(&udc->lock, flags);
2923
2924 return 0;
2925}
2926
2927/*-------------------------------------------------------------------------*/
2928static void nbu2ss_ep_fifo_flush(struct usb_ep *_ep)
2929{
2930 u32 data;
2931 struct nbu2ss_ep *ep;
2932 struct nbu2ss_udc *udc;
2933 unsigned long flags;
2934
33aa8d45 2935 if (!_ep) {
88689279 2936 pr_err("udc: %s, bad param\n", __func__);
33aa8d45
MD		 2937 return;
2938 }
2939
2940 ep = container_of(_ep, struct nbu2ss_ep, ep);
bd7de5ce 2941 if (!ep) {
88689279 2942 pr_err("udc: %s, bad ep\n", __func__);
33aa8d45
MD		 2943 return;
2944 }
2945
2946 udc = ep->udc;
2947 if (!udc) {
88689279 2948 dev_err(ep->udc->dev, "%s, bad udc\n", __func__);
33aa8d45
MD		 2949 return;
2950 }
2951
2952 data = gpio_get_value(VBUS_VALUE);
2953 if (data == 0)
2954 return;
2955
2956 spin_lock_irqsave(&udc->lock, flags);
2957 _nbu2ss_fifo_flush(udc, ep);
2958 spin_unlock_irqrestore(&udc->lock, flags);
2959}
2960
2961/*-------------------------------------------------------------------------*/
2962static struct usb_ep_ops nbu2ss_ep_ops = {
2963 .enable = nbu2ss_ep_enable,
2964 .disable = nbu2ss_ep_disable,
2965
2966 .alloc_request = nbu2ss_ep_alloc_request,
2967 .free_request = nbu2ss_ep_free_request,
2968
2969 .queue = nbu2ss_ep_queue,
2970 .dequeue = nbu2ss_ep_dequeue,
2971
2972 .set_halt = nbu2ss_ep_set_halt,
2973 .set_wedge = nbu2ss_ep_set_wedge,
2974
2975 .fifo_status = nbu2ss_ep_fifo_status,
2976 .fifo_flush = nbu2ss_ep_fifo_flush,
2977};
2978
33aa8d45
MD		 2979/*-------------------------------------------------------------------------*/
2980/* usb_gadget_ops */
2981
2982/*-------------------------------------------------------------------------*/
2983static int nbu2ss_gad_get_frame(struct usb_gadget *pgadget)
2984{
2985 u32 data;
2986 struct nbu2ss_udc *udc;
2987
706eb8cf 2988 if (!pgadget) {
88689279 2989 pr_err("udc: %s, bad param\n", __func__);
33aa8d45
MD		 2990 return -EINVAL;
2991 }
2992
2993 udc = container_of(pgadget, struct nbu2ss_udc, gadget);
706eb8cf 2994 if (!udc) {
88689279 2995 dev_err(&pgadget->dev, "%s, udc == NULL\n", __func__);
33aa8d45
MD		 2996 return -EINVAL;
2997 }
2998
2999 data = gpio_get_value(VBUS_VALUE);
3000 if (data == 0)
3001 return -EINVAL;
3002
3003 data = _nbu2ss_readl(&udc->p_regs->USB_ADDRESS) & FRAME;
3004
3005 return data;
3006}
3007
3008/*-------------------------------------------------------------------------*/
3009static int nbu2ss_gad_wakeup(struct usb_gadget *pgadget)
3010{
3011 int i;
3012 u32 data;
3013
3014 struct nbu2ss_udc *udc;
3015
706eb8cf 3016 if (!pgadget) {
88689279 3017 pr_err("%s, bad param\n", __func__);
33aa8d45
MD		 3018 return -EINVAL;
3019 }
3020
3021 udc = container_of(pgadget, struct nbu2ss_udc, gadget);
706eb8cf 3022 if (!udc) {
88689279 3023 dev_err(&pgadget->dev, "%s, udc == NULL\n", __func__);
33aa8d45
MD		 3024 return -EINVAL;
3025 }
3026
3027 data = gpio_get_value(VBUS_VALUE);
3028 if (data == 0) {
93275c80 3029 dev_warn(&pgadget->dev, "VBUS LEVEL = %d\n", data);
33aa8d45
MD		 3030 return -EINVAL;
3031 }
3032
3033 _nbu2ss_bitset(&udc->p_regs->EPCTR, PLL_RESUME);
3034
3035 for (i = 0; i < EPC_PLL_LOCK_COUNT; i++) {
3036 data = _nbu2ss_readl(&udc->p_regs->EPCTR);
3037
3038 if (data & PLL_LOCK)
3039 break;
3040 }
3041
3042 _nbu2ss_bitclr(&udc->p_regs->EPCTR, PLL_RESUME);
3043
3044 return 0;
3045}
3046
3047/*-------------------------------------------------------------------------*/
3048static int nbu2ss_gad_set_selfpowered(struct usb_gadget *pgadget,
3049 int is_selfpowered)
3050{
1fa2df0c 3051 struct nbu2ss_udc *udc;
33aa8d45
MD		 3052 unsigned long flags;
3053
706eb8cf 3054 if (!pgadget) {
88689279 3055 pr_err("%s, bad param\n", __func__);
33aa8d45
MD		 3056 return -EINVAL;
3057 }
3058
1fa2df0c
PC		 3059 udc = container_of(pgadget, struct nbu2ss_udc, gadget);
3060
33aa8d45 3061 spin_lock_irqsave(&udc->lock, flags);
9239d88f 3062 pgadget->is_selfpowered = (is_selfpowered != 0);
33aa8d45
MD		 3063 spin_unlock_irqrestore(&udc->lock, flags);
3064
3065 return 0;
3066}
3067
3068/*-------------------------------------------------------------------------*/
3069static int nbu2ss_gad_vbus_session(struct usb_gadget *pgadget, int is_active)
3070{
33aa8d45
MD		 3071 return 0;
3072}
3073
3074/*-------------------------------------------------------------------------*/
3075static int nbu2ss_gad_vbus_draw(struct usb_gadget *pgadget, unsigned mA)
3076{
3077 struct nbu2ss_udc *udc;
3078 unsigned long flags;
3079
706eb8cf 3080 if (!pgadget) {
88689279 3081 pr_err("%s, bad param\n", __func__);
33aa8d45
MD		 3082 return -EINVAL;
3083 }
3084
3085 udc = container_of(pgadget, struct nbu2ss_udc, gadget);
3086
3087 spin_lock_irqsave(&udc->lock, flags);
3088 udc->mA = mA;
3089 spin_unlock_irqrestore(&udc->lock, flags);
3090
3091 return 0;
3092}
3093
3094/*-------------------------------------------------------------------------*/
3095static int nbu2ss_gad_pullup(struct usb_gadget *pgadget, int is_on)
3096{
3097 struct nbu2ss_udc *udc;
3098 unsigned long flags;
3099
706eb8cf 3100 if (!pgadget) {
88689279 3101 pr_err("%s, bad param\n", __func__);
33aa8d45
MD		 3102 return -EINVAL;
3103 }
3104
3105 udc = container_of(pgadget, struct nbu2ss_udc, gadget);
3106
706eb8cf 3107 if (!udc->driver) {
f02935c5 3108 pr_warn("%s, Not Regist Driver\n", __func__);
33aa8d45
MD		 3109 return -EINVAL;
3110 }
3111
3112 if (udc->vbus_active == 0)
3113 return -ESHUTDOWN;
3114
3115 spin_lock_irqsave(&udc->lock, flags);
3116 _nbu2ss_pullup(udc, is_on);
3117 spin_unlock_irqrestore(&udc->lock, flags);
3118
3119 return 0;
3120}
3121
3122/*-------------------------------------------------------------------------*/
3123static int nbu2ss_gad_ioctl(
3124 struct usb_gadget *pgadget,
3125 unsigned code,
3126 unsigned long param)
3127{
33aa8d45
MD		 3128 return 0;
3129}
3130
33aa8d45
MD		 3131static const struct usb_gadget_ops nbu2ss_gadget_ops = {
3132 .get_frame = nbu2ss_gad_get_frame,
3133 .wakeup = nbu2ss_gad_wakeup,
3134 .set_selfpowered = nbu2ss_gad_set_selfpowered,
3135 .vbus_session = nbu2ss_gad_vbus_session,
3136 .vbus_draw = nbu2ss_gad_vbus_draw,
3137 .pullup = nbu2ss_gad_pullup,
3138 .ioctl = nbu2ss_gad_ioctl,
3139};
3140
68b5c947
RB		 3141static const struct {
3142 const char *name;
3143 const struct usb_ep_caps caps;
3144} ep_info[NUM_ENDPOINTS] = {
3145#define EP_INFO(_name, _caps) \
3146 { \
3147 .name = _name, \
3148 .caps = _caps, \
3149 }
3150
3151 EP_INFO("ep0",
3152 USB_EP_CAPS(USB_EP_CAPS_TYPE_CONTROL, USB_EP_CAPS_DIR_ALL)),
3153 EP_INFO("ep1-bulk",
3154 USB_EP_CAPS(USB_EP_CAPS_TYPE_BULK, USB_EP_CAPS_DIR_ALL)),
3155 EP_INFO("ep2-bulk",
3156 USB_EP_CAPS(USB_EP_CAPS_TYPE_BULK, USB_EP_CAPS_DIR_ALL)),
3157 EP_INFO("ep3in-int",
3158 USB_EP_CAPS(USB_EP_CAPS_TYPE_INT, USB_EP_CAPS_DIR_IN)),
3159 EP_INFO("ep4-iso",
3160 USB_EP_CAPS(USB_EP_CAPS_TYPE_ISO, USB_EP_CAPS_DIR_ALL)),
3161 EP_INFO("ep5-iso",
3162 USB_EP_CAPS(USB_EP_CAPS_TYPE_ISO, USB_EP_CAPS_DIR_ALL)),
3163 EP_INFO("ep6-bulk",
3164 USB_EP_CAPS(USB_EP_CAPS_TYPE_BULK, USB_EP_CAPS_DIR_ALL)),
3165 EP_INFO("ep7-bulk",
3166 USB_EP_CAPS(USB_EP_CAPS_TYPE_BULK, USB_EP_CAPS_DIR_ALL)),
3167 EP_INFO("ep8in-int",
3168 USB_EP_CAPS(USB_EP_CAPS_TYPE_INT, USB_EP_CAPS_DIR_IN)),
3169 EP_INFO("ep9-iso",
3170 USB_EP_CAPS(USB_EP_CAPS_TYPE_ISO, USB_EP_CAPS_DIR_ALL)),
3171 EP_INFO("epa-iso",
3172 USB_EP_CAPS(USB_EP_CAPS_TYPE_ISO, USB_EP_CAPS_DIR_ALL)),
3173 EP_INFO("epb-bulk",
3174 USB_EP_CAPS(USB_EP_CAPS_TYPE_BULK, USB_EP_CAPS_DIR_ALL)),
3175 EP_INFO("epc-bulk",
3176 USB_EP_CAPS(USB_EP_CAPS_TYPE_BULK, USB_EP_CAPS_DIR_ALL)),
3177 EP_INFO("epdin-int",
3178 USB_EP_CAPS(USB_EP_CAPS_TYPE_INT, USB_EP_CAPS_DIR_IN)),
3179
3180#undef EP_INFO
33aa8d45
MD		 3181};
3182
33aa8d45
MD		 3183/*-------------------------------------------------------------------------*/
3184static void __init nbu2ss_drv_ep_init(struct nbu2ss_udc *udc)
3185{
3186 int i;
3187
3188 INIT_LIST_HEAD(&udc->gadget.ep_list);
3189 udc->gadget.ep0 = &udc->ep[0].ep;
3190
737fee1b
CR		 3191 for (i = 0; i < NUM_ENDPOINTS; i++) {
3192 struct nbu2ss_ep *ep = &udc->ep[i];
33aa8d45 3193
737fee1b
CR		 3194 ep->udc = udc;
3195 ep->desc = NULL;
3196
3197 ep->ep.driver_data = NULL;
68b5c947
RB		 3198 ep->ep.name = ep_info[i].name;
3199 ep->ep.caps = ep_info[i].caps;
737fee1b
CR		 3200 ep->ep.ops = &nbu2ss_ep_ops;
3201
cb009d6e
RB		 3202 usb_ep_set_maxpacket_limit(&ep->ep,
3203 i == 0 ? EP0_PACKETSIZE : EP_PACKETSIZE);
737fee1b
CR		 3204
3205 list_add_tail(&ep->ep.ep_list, &udc->gadget.ep_list);
3206 INIT_LIST_HEAD(&ep->queue);
3207 }
33aa8d45
MD		 3208
3209 list_del_init(&udc->ep[0].ep.ep_list);
3210}
3211
3212/*-------------------------------------------------------------------------*/
3213/* platform_driver */
3214static int __init nbu2ss_drv_contest_init(
3215 struct platform_device *pdev,
3216 struct nbu2ss_udc *udc)
3217{
3218 spin_lock_init(&udc->lock);
3219 udc->dev = &pdev->dev;
3220
9239d88f 3221 udc->gadget.is_selfpowered = 1;
33aa8d45
MD		 3222 udc->devstate = USB_STATE_NOTATTACHED;
3223 udc->pdev = pdev;
3224 udc->mA = 0;
3225
3226 udc->pdev->dev.coherent_dma_mask = DMA_BIT_MASK(32);
3227
3228 /* init Endpoint */
3229 nbu2ss_drv_ep_init(udc);
3230
3231 /* init Gadget */
3232 udc->gadget.ops = &nbu2ss_gadget_ops;
3233 udc->gadget.ep0 = &udc->ep[0].ep;
3234 udc->gadget.speed = USB_SPEED_UNKNOWN;
3235 udc->gadget.name = driver_name;
a2c14e97 3236 /* udc->gadget.is_dualspeed = 1; */
33aa8d45
MD		 3237
3238 device_initialize(&udc->gadget.dev);
3239
3240 dev_set_name(&udc->gadget.dev, "gadget");
3241 udc->gadget.dev.parent = &pdev->dev;
3242 udc->gadget.dev.dma_mask = pdev->dev.dma_mask;
3243
3244 return 0;
3245}
3246
3247/*
3248 * probe - binds to the platform device
3249 */
3250static int nbu2ss_drv_probe(struct platform_device *pdev)
3251{
3252 int status = -ENODEV;
3253 struct nbu2ss_udc *udc;
96b29cac
MD		 3254 struct resource *r;
3255 int irq;
3256 void __iomem *mmio_base;
33aa8d45
MD		 3257
3258 udc = &udc_controller;
3259 memset(udc, 0, sizeof(struct nbu2ss_udc));
3260
3261 platform_set_drvdata(pdev, udc);
3262
96b29cac
MD		 3263 /* require I/O memory and IRQ to be provided as resources */
3264 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
a790ebc1
SK		 3265 mmio_base = devm_ioremap_resource(&pdev->dev, r);
3266 if (IS_ERR(mmio_base))
96b29cac 3267 return PTR_ERR(mmio_base);
33aa8d45 3268
96b29cac
MD		 3269 irq = platform_get_irq(pdev, 0);
3270 if (irq < 0) {
3271 dev_err(&pdev->dev, "failed to get IRQ\n");
3272 return irq;
33aa8d45 3273 }
96b29cac
MD		 3274 status = devm_request_irq(&pdev->dev, irq, _nbu2ss_udc_irq,
3275 0, driver_name, udc);
33aa8d45
MD		 3276
3277 /* IO Memory */
f6ef6c09 3278 udc->p_regs = (struct fc_regs *)mmio_base;
33aa8d45
MD		 3279
3280 /* USB Function Controller Interrupt */
33aa8d45 3281 if (status != 0) {
88689279 3282 dev_err(udc->dev, "request_irq(USB_UDC_IRQ_1) failed\n");
c648a57a 3283 return status;
33aa8d45
MD		 3284 }
3285
3286 /* Driver Initialization */
3287 status = nbu2ss_drv_contest_init(pdev, udc);
3288 if (status < 0) {
3289 /* Error */
c648a57a 3290 return status;
33aa8d45
MD		 3291 }
3292
3293 /* VBUS Interrupt */
3294 irq_set_irq_type(INT_VBUS, IRQ_TYPE_EDGE_BOTH);
3295 status = request_irq(INT_VBUS,
3296 _nbu2ss_vbus_irq,
3297 IRQF_SHARED,
3298 driver_name,
3299 udc);
3300
3301 if (status != 0) {
88689279 3302 dev_err(udc->dev, "request_irq(INT_VBUS) failed\n");
c648a57a 3303 return status;
33aa8d45
MD		 3304 }
3305
3306 return status;
33aa8d45
MD		 3307}
3308
3309/*-------------------------------------------------------------------------*/
3310static void nbu2ss_drv_shutdown(struct platform_device *pdev)
3311{
3312 struct nbu2ss_udc *udc;
3313
3314 udc = platform_get_drvdata(pdev);
706eb8cf 3315 if (!udc)
33aa8d45
MD		 3316 return;
3317
3318 _nbu2ss_disable_controller(udc);
3319}
3320
33aa8d45
MD		 3321/*-------------------------------------------------------------------------*/
3322static int nbu2ss_drv_suspend(struct platform_device *pdev, pm_message_t state)
3323{
3324 struct nbu2ss_udc *udc;
3325
3326 udc = platform_get_drvdata(pdev);
706eb8cf 3327 if (!udc)
33aa8d45
MD		 3328 return 0;
3329
3330 if (udc->vbus_active) {
3331 udc->vbus_active = 0;
3332 udc->devstate = USB_STATE_NOTATTACHED;
3333 udc->linux_suspended = 1;
3334
3335 if (udc->usb_suspended) {
3336 udc->usb_suspended = 0;
3337 _nbu2ss_reset_controller(udc);
3338 }
3339
3340 _nbu2ss_quiesce(udc);
3341 }
3342 _nbu2ss_disable_controller(udc);
3343
3344 return 0;
3345}
3346
3347/*-------------------------------------------------------------------------*/
3348static int nbu2ss_drv_resume(struct platform_device *pdev)
3349{
3350 u32 data;
3351 struct nbu2ss_udc *udc;
3352
3353 udc = platform_get_drvdata(pdev);
706eb8cf 3354 if (!udc)
33aa8d45
MD		 3355 return 0;
3356
3357 data = gpio_get_value(VBUS_VALUE);
3358 if (data) {
3359 udc->vbus_active = 1;
3360 udc->devstate = USB_STATE_POWERED;
3361 _nbu2ss_enable_controller(udc);
3362 _nbu2ss_pullup(udc, 1);
3363 }
3364
3365 udc->linux_suspended = 0;
3366
3367 return 0;
3368}
3369
33aa8d45
MD		 3370static struct platform_driver udc_driver = {
3371 .probe = nbu2ss_drv_probe,
3372 .shutdown = nbu2ss_drv_shutdown,
33aa8d45
MD		 3373 .suspend = nbu2ss_drv_suspend,
3374 .resume = nbu2ss_drv_resume,
3375 .driver = {
0af61e66
PG		 3376 .name = driver_name,
3377 .suppress_bind_attrs = true,
33aa8d45
MD		 3378 },
3379};
3380
0af61e66 3381builtin_platform_driver(udc_driver);
Linux kernel - Deliverables
This page took 0.382997 seconds and 5 git commands to generate.