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Merge remote-tracking branch 'staging/staging-next'
[deliverable/linux.git] / drivers / staging / emxx_udc / emxx_udc.c
CommitLineData
33aa8d45
MD		 1/*
2 * drivers/usb/gadget/emxx_udc.c
3 * EMXX FCD (Function Controller Driver) for USB.
4 *
5 * Copyright (C) 2010 Renesas Electronics Corporation
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2
9 * as published by the Free Software Foundation.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
33aa8d45
MD		 15 */
16
17#include <linux/kernel.h>
0bf048ab 18#include <linux/module.h>
33aa8d45
MD		 19#include <linux/platform_device.h>
20#include <linux/delay.h>
21#include <linux/ioport.h>
22#include <linux/slab.h>
23#include <linux/errno.h>
33aa8d45
MD		 24#include <linux/list.h>
25#include <linux/interrupt.h>
26#include <linux/proc_fs.h>
27#include <linux/clk.h>
28#include <linux/ctype.h>
29#include <linux/string.h>
30#include <linux/dma-mapping.h>
31#include <linux/workqueue.h>
a790ebc1 32#include <linux/device.h>
33aa8d45
MD		 33
34#include <linux/usb/ch9.h>
35#include <linux/usb/gadget.h>
36
37#include <linux/irq.h>
38#include <linux/gpio.h>
39
40#include "emxx_udc.h"
41
0bf048ab 42#define DRIVER_DESC "EMXX UDC driver"
33aa8d45
MD		 43#define DMA_ADDR_INVALID (~(dma_addr_t)0)
44
45static const char driver_name[] = "emxx_udc";
0bf048ab 46static const char driver_desc[] = DRIVER_DESC;
33aa8d45
MD		 47
48/*===========================================================================*/
49/* Prototype */
50static void _nbu2ss_ep_dma_abort(struct nbu2ss_udc *, struct nbu2ss_ep *);
51static void _nbu2ss_ep0_enable(struct nbu2ss_udc *);
52/*static void _nbu2ss_ep0_disable(struct nbu2ss_udc *);*/
53static void _nbu2ss_ep_done(struct nbu2ss_ep *, struct nbu2ss_req *, int);
54static void _nbu2ss_set_test_mode(struct nbu2ss_udc *, u32 mode);
55static void _nbu2ss_endpoint_toggle_reset(struct nbu2ss_udc *udc, u8 ep_adrs);
56
57static int _nbu2ss_pullup(struct nbu2ss_udc *, int);
58static void _nbu2ss_fifo_flush(struct nbu2ss_udc *, struct nbu2ss_ep *);
59
60/*===========================================================================*/
61/* Macro */
62#define _nbu2ss_zero_len_pkt(udc, epnum) \
63 _nbu2ss_ep_in_end(udc, epnum, 0, 0)
64
33aa8d45
MD		 65/*===========================================================================*/
66/* Global */
67struct nbu2ss_udc udc_controller;
68
33aa8d45
MD		 69/*-------------------------------------------------------------------------*/
70/* Read */
71static inline u32 _nbu2ss_readl(void *address)
72{
ce1e3eb7 73 return __raw_readl(address);
33aa8d45
MD		 74}
75
76/*-------------------------------------------------------------------------*/
77/* Write */
78static inline void _nbu2ss_writel(void *address, u32 udata)
79{
ce1e3eb7 80 __raw_writel(udata, address);
33aa8d45
MD		 81}
82
83/*-------------------------------------------------------------------------*/
84/* Set Bit */
85static inline void _nbu2ss_bitset(void *address, u32 udata)
86{
87 u32 reg_dt = __raw_readl(address) | (udata);
7f39ae05 88
ce1e3eb7 89 __raw_writel(reg_dt, address);
33aa8d45
MD		 90}
91
92/*-------------------------------------------------------------------------*/
93/* Clear Bit */
94static inline void _nbu2ss_bitclr(void *address, u32 udata)
95{
96 u32 reg_dt = __raw_readl(address) & ~(udata);
7f39ae05 97
ce1e3eb7 98 __raw_writel(reg_dt, address);
33aa8d45
MD		 99}
100
101#ifdef UDC_DEBUG_DUMP
102/*-------------------------------------------------------------------------*/
103static void _nbu2ss_dump_register(struct nbu2ss_udc *udc)
104{
105 int i;
106 u32 reg_data;
107
108 pr_info("=== %s()\n", __func__);
109
706eb8cf 110 if (!udc) {
88689279 111 pr_err("%s udc == NULL\n", __func__);
33aa8d45
MD		 112 return;
113 }
114
115 spin_unlock(&udc->lock);
116
fb71d24b 117 dev_dbg(&udc->dev, "\n-USB REG-\n");
33aa8d45
MD		 118 for (i = 0x0 ; i < USB_BASE_SIZE ; i += 16) {
119 reg_data = _nbu2ss_readl(
120 (u32 *)IO_ADDRESS(USB_BASE_ADDRESS + i));
fb71d24b 121 dev_dbg(&udc->dev, "USB%04x =%08x", i, (int)reg_data);
33aa8d45
MD		 122
123 reg_data = _nbu2ss_readl(
124 (u32 *)IO_ADDRESS(USB_BASE_ADDRESS + i + 4));
fb71d24b 125 dev_dbg(&udc->dev, " %08x", (int)reg_data);
33aa8d45
MD		 126
127 reg_data = _nbu2ss_readl(
128 (u32 *)IO_ADDRESS(USB_BASE_ADDRESS + i + 8));
fb71d24b 129 dev_dbg(&udc->dev, " %08x", (int)reg_data);
33aa8d45
MD		 130
131 reg_data = _nbu2ss_readl(
132 (u32 *)IO_ADDRESS(USB_BASE_ADDRESS + i + 12));
fb71d24b 133 dev_dbg(&udc->dev, " %08x\n", (int)reg_data);
33aa8d45
MD		 134 }
135
136 spin_lock(&udc->lock);
137}
138#endif /* UDC_DEBUG_DUMP */
139
140/*-------------------------------------------------------------------------*/
141/* Endpoint 0 Callback (Complete) */
142static void _nbu2ss_ep0_complete(struct usb_ep *_ep, struct usb_request *_req)
143{
144 u8 recipient;
145 u16 selector;
146 u32 test_mode;
147 struct usb_ctrlrequest *p_ctrl;
148 struct nbu2ss_udc *udc;
149
706eb8cf 150 if ((!_ep) || (!_req))
33aa8d45
MD		 151 return;
152
153 udc = (struct nbu2ss_udc *)_req->context;
154 p_ctrl = &udc->ctrl;
155 if ((p_ctrl->bRequestType & USB_TYPE_MASK) == USB_TYPE_STANDARD) {
156
157 if (p_ctrl->bRequest == USB_REQ_SET_FEATURE) {
158 /*-------------------------------------------------*/
159 /* SET_FEATURE */
160 recipient = (u8)(p_ctrl->bRequestType & USB_RECIP_MASK);
161 selector = p_ctrl->wValue;
162 if ((recipient == USB_RECIP_DEVICE) &&
c75955d1 163 (selector == USB_DEVICE_TEST_MODE)) {
33aa8d45
MD		 164 test_mode = (u32)(p_ctrl->wIndex >> 8);
165 _nbu2ss_set_test_mode(udc, test_mode);
166 }
167 }
168 }
169}
170
171/*-------------------------------------------------------------------------*/
172/* Initialization usb_request */
173static void _nbu2ss_create_ep0_packet(
174 struct nbu2ss_udc *udc,
175 void *p_buf,
176 unsigned length
177)
178{
179 udc->ep0_req.req.buf = p_buf;
180 udc->ep0_req.req.length = length;
181 udc->ep0_req.req.dma = 0;
182 udc->ep0_req.req.zero = TRUE;
183 udc->ep0_req.req.complete = _nbu2ss_ep0_complete;
184 udc->ep0_req.req.status = -EINPROGRESS;
185 udc->ep0_req.req.context = udc;
186 udc->ep0_req.req.actual = 0;
187}
188
189/*-------------------------------------------------------------------------*/
190/* Acquisition of the first address of RAM(FIFO) */
191static u32 _nbu2ss_get_begin_ram_address(struct nbu2ss_udc *udc)
192{
193 u32 num, buf_type;
194 u32 data, last_ram_adr, use_ram_size;
195
f6ef6c09 196 struct ep_regs *p_ep_regs;
33aa8d45
MD		 197
198 last_ram_adr = (D_RAM_SIZE_CTRL / sizeof(u32)) * 2;
199 use_ram_size = 0;
200
201 for (num = 0; num < NUM_ENDPOINTS - 1; num++) {
202 p_ep_regs = &udc->p_regs->EP_REGS[num];
203 data = _nbu2ss_readl(&p_ep_regs->EP_PCKT_ADRS);
204 buf_type = _nbu2ss_readl(&p_ep_regs->EP_CONTROL) & EPn_BUF_TYPE;
205 if (buf_type == 0) {
206 /* Single Buffer */
207 use_ram_size += (data & EPn_MPKT) / sizeof(u32);
208 } else {
209 /* Double Buffer */
210 use_ram_size += ((data & EPn_MPKT) / sizeof(u32)) * 2;
211 }
212
213 if ((data >> 16) > last_ram_adr)
ba57f5fa 214 last_ram_adr = data >> 16;
33aa8d45
MD		 215 }
216
217 return last_ram_adr + use_ram_size;
218}
219
220/*-------------------------------------------------------------------------*/
221/* Construction of Endpoint */
222static int _nbu2ss_ep_init(struct nbu2ss_udc *udc, struct nbu2ss_ep *ep)
223{
224 u32 num;
225 u32 data;
226 u32 begin_adrs;
227
228 if (ep->epnum == 0)
229 return -EINVAL;
230
231 num = ep->epnum - 1;
232
233 /*-------------------------------------------------------------*/
234 /* RAM Transfer Address */
235 begin_adrs = _nbu2ss_get_begin_ram_address(udc);
236 data = (begin_adrs << 16) | ep->ep.maxpacket;
237 _nbu2ss_writel(&udc->p_regs->EP_REGS[num].EP_PCKT_ADRS, data);
238
239 /*-------------------------------------------------------------*/
240 /* Interrupt Enable */
241 data = 1 << (ep->epnum + 8);
242 _nbu2ss_bitset(&udc->p_regs->USB_INT_ENA, data);
243
244 /*-------------------------------------------------------------*/
245 /* Endpoint Type(Mode) */
246 /* Bulk, Interrupt, ISO */
247 switch (ep->ep_type) {
248 case USB_ENDPOINT_XFER_BULK:
249 data = EPn_BULK;
250 break;
251
252 case USB_ENDPOINT_XFER_INT:
253 data = EPn_BUF_SINGLE | EPn_INTERRUPT;
254 break;
255
256 case USB_ENDPOINT_XFER_ISOC:
257 data = EPn_ISO;
258 break;
259
260 default:
261 data = 0;
262 break;
263 }
264
265 _nbu2ss_bitset(&udc->p_regs->EP_REGS[num].EP_CONTROL, data);
266 _nbu2ss_endpoint_toggle_reset(udc, (ep->epnum|ep->direct));
267
268 if (ep->direct == USB_DIR_OUT) {
269 /*---------------------------------------------------------*/
270 /* OUT */
271 data = EPn_EN | EPn_BCLR | EPn_DIR0;
272 _nbu2ss_bitset(&udc->p_regs->EP_REGS[num].EP_CONTROL, data);
273
599b8780 274 data = EPn_ONAK | EPn_OSTL_EN | EPn_OSTL;
33aa8d45
MD		 275 _nbu2ss_bitclr(&udc->p_regs->EP_REGS[num].EP_CONTROL, data);
276
599b8780 277 data = EPn_OUT_EN | EPn_OUT_END_EN;
33aa8d45
MD		 278 _nbu2ss_bitset(&udc->p_regs->EP_REGS[num].EP_INT_ENA, data);
279 } else {
280 /*---------------------------------------------------------*/
281 /* IN */
599b8780 282 data = EPn_EN | EPn_BCLR | EPn_AUTO;
33aa8d45
MD		 283 _nbu2ss_bitset(&udc->p_regs->EP_REGS[num].EP_CONTROL, data);
284
599b8780 285 data = EPn_ISTL;
33aa8d45
MD		 286 _nbu2ss_bitclr(&udc->p_regs->EP_REGS[num].EP_CONTROL, data);
287
599b8780 288 data = EPn_IN_EN | EPn_IN_END_EN;
33aa8d45
MD		 289 _nbu2ss_bitset(&udc->p_regs->EP_REGS[num].EP_INT_ENA, data);
290 }
291
292 return 0;
293}
294
295/*-------------------------------------------------------------------------*/
296/* Release of Endpoint */
297static int _nbu2ss_epn_exit(struct nbu2ss_udc *udc, struct nbu2ss_ep *ep)
298{
299 u32 num;
300 u32 data;
301
302 if ((ep->epnum == 0) || (udc->vbus_active == 0))
303 return -EINVAL;
304
305 num = ep->epnum - 1;
306
307 /*-------------------------------------------------------------*/
308 /* RAM Transfer Address */
309 _nbu2ss_writel(&udc->p_regs->EP_REGS[num].EP_PCKT_ADRS, 0);
310
311 /*-------------------------------------------------------------*/
312 /* Interrupt Disable */
313 data = 1 << (ep->epnum + 8);
314 _nbu2ss_bitclr(&udc->p_regs->USB_INT_ENA, data);
315
316 if (ep->direct == USB_DIR_OUT) {
317 /*---------------------------------------------------------*/
318 /* OUT */
319 data = EPn_ONAK | EPn_BCLR;
320 _nbu2ss_bitset(&udc->p_regs->EP_REGS[num].EP_CONTROL, data);
321
322 data = EPn_EN | EPn_DIR0;
323 _nbu2ss_bitclr(&udc->p_regs->EP_REGS[num].EP_CONTROL, data);
324
325 data = EPn_OUT_EN | EPn_OUT_END_EN;
326 _nbu2ss_bitclr(&udc->p_regs->EP_REGS[num].EP_INT_ENA, data);
327 } else {
328 /*---------------------------------------------------------*/
329 /* IN */
330 data = EPn_BCLR;
331 _nbu2ss_bitset(&udc->p_regs->EP_REGS[num].EP_CONTROL, data);
332
333 data = EPn_EN | EPn_AUTO;
334 _nbu2ss_bitclr(&udc->p_regs->EP_REGS[num].EP_CONTROL, data);
335
336 data = EPn_IN_EN | EPn_IN_END_EN;
337 _nbu2ss_bitclr(&udc->p_regs->EP_REGS[num].EP_INT_ENA, data);
338 }
339
340 return 0;
341}
342
343/*-------------------------------------------------------------------------*/
344/* DMA setting (without Endpoint 0) */
345static void _nbu2ss_ep_dma_init(struct nbu2ss_udc *udc, struct nbu2ss_ep *ep)
346{
347 u32 num;
348 u32 data;
349
350 data = _nbu2ss_readl(&udc->p_regs->USBSSCONF);
351 if (((ep->epnum == 0) || (data & (1 << ep->epnum)) == 0))
352 return; /* Not Support DMA */
353
354 num = ep->epnum - 1;
355
356 if (ep->direct == USB_DIR_OUT) {
357 /*---------------------------------------------------------*/
358 /* OUT */
359 data = ep->ep.maxpacket;
360 _nbu2ss_writel(&udc->p_regs->EP_DCR[num].EP_DCR2, data);
361
362 /*---------------------------------------------------------*/
363 /* Transfer Direct */
364 data = DCR1_EPn_DIR0;
365 _nbu2ss_bitset(&udc->p_regs->EP_DCR[num].EP_DCR1, data);
366
367 /*---------------------------------------------------------*/
368 /* DMA Mode etc. */
369 data = EPn_STOP_MODE | EPn_STOP_SET | EPn_DMAMODE0;
370 _nbu2ss_writel(&udc->p_regs->EP_REGS[num].EP_DMA_CTRL, data);
371 } else {
372 /*---------------------------------------------------------*/
373 /* IN */
374 _nbu2ss_bitset(&udc->p_regs->EP_REGS[num].EP_CONTROL, EPn_AUTO);
375
376 /*---------------------------------------------------------*/
377 /* DMA Mode etc. */
378 data = EPn_BURST_SET | EPn_DMAMODE0;
379 _nbu2ss_writel(&udc->p_regs->EP_REGS[num].EP_DMA_CTRL, data);
380 }
381}
382
383/*-------------------------------------------------------------------------*/
384/* DMA setting release */
385static void _nbu2ss_ep_dma_exit(struct nbu2ss_udc *udc, struct nbu2ss_ep *ep)
386{
387 u32 num;
388 u32 data;
f6ef6c09 389 struct fc_regs *preg = udc->p_regs;
33aa8d45
MD		 390
391 if (udc->vbus_active == 0)
392 return; /* VBUS OFF */
393
394 data = _nbu2ss_readl(&preg->USBSSCONF);
395 if ((ep->epnum == 0) || ((data & (1 << ep->epnum)) == 0))
396 return; /* Not Support DMA */
397
398 num = ep->epnum - 1;
399
400 _nbu2ss_ep_dma_abort(udc, ep);
401
402 if (ep->direct == USB_DIR_OUT) {
403 /*---------------------------------------------------------*/
404 /* OUT */
405 _nbu2ss_writel(&preg->EP_DCR[num].EP_DCR2, 0);
406 _nbu2ss_bitclr(&preg->EP_DCR[num].EP_DCR1, DCR1_EPn_DIR0);
407 _nbu2ss_writel(&preg->EP_REGS[num].EP_DMA_CTRL, 0);
408 } else {
409 /*---------------------------------------------------------*/
410 /* IN */
411 _nbu2ss_bitclr(&preg->EP_REGS[num].EP_CONTROL, EPn_AUTO);
412 _nbu2ss_writel(&preg->EP_REGS[num].EP_DMA_CTRL, 0);
413 }
414}
415
416/*-------------------------------------------------------------------------*/
417/* Abort DMA */
418static void _nbu2ss_ep_dma_abort(struct nbu2ss_udc *udc, struct nbu2ss_ep *ep)
419{
f6ef6c09 420 struct fc_regs *preg = udc->p_regs;
33aa8d45 421
abe34174 422 _nbu2ss_bitclr(&preg->EP_DCR[ep->epnum - 1].EP_DCR1, DCR1_EPn_REQEN);
33aa8d45 423 mdelay(DMA_DISABLE_TIME); /* DCR1_EPn_REQEN Clear */
abe34174 424 _nbu2ss_bitclr(&preg->EP_REGS[ep->epnum - 1].EP_DMA_CTRL, EPn_DMA_EN);
33aa8d45
MD		 425}
426
427/*-------------------------------------------------------------------------*/
428/* Start IN Transfer */
429static void _nbu2ss_ep_in_end(
430 struct nbu2ss_udc *udc,
431 u32 epnum,
432 u32 data32,
433 u32 length
434)
435{
436 u32 data;
437 u32 num;
f6ef6c09 438 struct fc_regs *preg = udc->p_regs;
33aa8d45
MD		 439
440 if (length >= sizeof(u32))
441 return;
442
443 if (epnum == 0) {
444 _nbu2ss_bitclr(&preg->EP0_CONTROL, EP0_AUTO);
445
446 /* Writing of 1-4 bytes */
447 if (length)
448 _nbu2ss_writel(&preg->EP0_WRITE, data32);
449
450 data = ((length << 5) & EP0_DW) | EP0_DEND;
451 _nbu2ss_writel(&preg->EP0_CONTROL, data);
452
453 _nbu2ss_bitset(&preg->EP0_CONTROL, EP0_AUTO);
454 } else {
455 num = epnum - 1;
456
457 _nbu2ss_bitclr(&preg->EP_REGS[num].EP_CONTROL, EPn_AUTO);
458
459 /* Writing of 1-4 bytes */
460 if (length)
461 _nbu2ss_writel(&preg->EP_REGS[num].EP_WRITE, data32);
462
599b8780 463 data = ((((u32)length) << 5) & EPn_DW) | EPn_DEND;
33aa8d45
MD		 464 _nbu2ss_bitset(&preg->EP_REGS[num].EP_CONTROL, data);
465
466 _nbu2ss_bitset(&preg->EP_REGS[num].EP_CONTROL, EPn_AUTO);
467 }
33aa8d45
MD		 468}
469
470#ifdef USE_DMA
471/*-------------------------------------------------------------------------*/
472static void _nbu2ss_dma_map_single(
473 struct nbu2ss_udc *udc,
474 struct nbu2ss_ep *ep,
475 struct nbu2ss_req *req,
476 u8 direct
477)
478{
479 if (req->req.dma == DMA_ADDR_INVALID) {
480 if (req->unaligned)
481 req->req.dma = ep->phys_buf;
482 else {
483 req->req.dma = dma_map_single(
484 udc->gadget.dev.parent,
485 req->req.buf,
486 req->req.length,
487 (direct == USB_DIR_IN)
488 ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
489 }
490 req->mapped = 1;
491 } else {
492 if (!req->unaligned)
493 dma_sync_single_for_device(
494 udc->gadget.dev.parent,
495 req->req.dma,
496 req->req.length,
497 (direct == USB_DIR_IN)
498 ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
499
500 req->mapped = 0;
501 }
502}
503
504/*-------------------------------------------------------------------------*/
505static void _nbu2ss_dma_unmap_single(
506 struct nbu2ss_udc *udc,
507 struct nbu2ss_ep *ep,
508 struct nbu2ss_req *req,
509 u8 direct
510)
511{
512 u8 data[4];
513 u8 *p;
514 u32 count = 0;
515
516 if (direct == USB_DIR_OUT) {
517 count = req->req.actual % 4;
518 if (count) {
519 p = req->req.buf;
520 p += (req->req.actual - count);
521 memcpy(data, p, count);
522 }
523 }
524
525 if (req->mapped) {
526 if (req->unaligned) {
527 if (direct == USB_DIR_OUT)
528 memcpy(req->req.buf, ep->virt_buf,
c75955d1 529 req->req.actual & 0xfffffffc);
33aa8d45
MD		 530 } else
531 dma_unmap_single(udc->gadget.dev.parent,
c75955d1 532 req->req.dma, req->req.length,
33aa8d45
MD		 533 (direct == USB_DIR_IN)
534 ? DMA_TO_DEVICE
535 : DMA_FROM_DEVICE);
536 req->req.dma = DMA_ADDR_INVALID;
537 req->mapped = 0;
538 } else {
539 if (!req->unaligned)
540 dma_sync_single_for_cpu(udc->gadget.dev.parent,
c75955d1 541 req->req.dma, req->req.length,
33aa8d45
MD		 542 (direct == USB_DIR_IN)
543 ? DMA_TO_DEVICE
544 : DMA_FROM_DEVICE);
545 }
546
547 if (count) {
548 p = req->req.buf;
549 p += (req->req.actual - count);
550 memcpy(p, data, count);
551 }
552}
553#endif
554
555/*-------------------------------------------------------------------------*/
556/* Endpoint 0 OUT Transfer (PIO) */
a2c14e97 557static int EP0_out_PIO(struct nbu2ss_udc *udc, u8 *pBuf, u32 length)
33aa8d45
MD		 558{
559 u32 i;
560 int nret = 0;
561 u32 iWordLength = 0;
f6ef6c09 562 union usb_reg_access *pBuf32 = (union usb_reg_access *)pBuf;
33aa8d45
MD		 563
564 /*------------------------------------------------------------*/
565 /* Read Length */
566 iWordLength = length / sizeof(u32);
567
568 /*------------------------------------------------------------*/
569 /* PIO Read */
570 if (iWordLength) {
571 for (i = 0; i < iWordLength; i++) {
572 pBuf32->dw = _nbu2ss_readl(&udc->p_regs->EP0_READ);
573 pBuf32++;
574 }
575 nret = iWordLength * sizeof(u32);
576 }
577
578 return nret;
579}
580
581/*-------------------------------------------------------------------------*/
582/* Endpoint 0 OUT Transfer (PIO, OverBytes) */
a2c14e97 583static int EP0_out_OverBytes(struct nbu2ss_udc *udc, u8 *pBuf, u32 length)
33aa8d45
MD		 584{
585 u32 i;
586 u32 iReadSize = 0;
f6ef6c09
HM		 587 union usb_reg_access Temp32;
588 union usb_reg_access *pBuf32 = (union usb_reg_access *)pBuf;
33aa8d45 589
2866914c 590 if ((length > 0) && (length < sizeof(u32))) {
33aa8d45
MD		 591 Temp32.dw = _nbu2ss_readl(&udc->p_regs->EP0_READ);
592 for (i = 0 ; i < length ; i++)
593 pBuf32->byte.DATA[i] = Temp32.byte.DATA[i];
594 iReadSize += length;
595 }
596
597 return iReadSize;
598}
599
600/*-------------------------------------------------------------------------*/
601/* Endpoint 0 IN Transfer (PIO) */
602static int EP0_in_PIO(struct nbu2ss_udc *udc, u8 *pBuf, u32 length)
603{
604 u32 i;
605 u32 iMaxLength = EP0_PACKETSIZE;
606 u32 iWordLength = 0;
607 u32 iWriteLength = 0;
f6ef6c09 608 union usb_reg_access *pBuf32 = (union usb_reg_access *)pBuf;
33aa8d45
MD		 609
610 /*------------------------------------------------------------*/
611 /* Transfer Length */
612 if (iMaxLength < length)
613 iWordLength = iMaxLength / sizeof(u32);
614 else
615 iWordLength = length / sizeof(u32);
616
617 /*------------------------------------------------------------*/
618 /* PIO */
619 for (i = 0; i < iWordLength; i++) {
620 _nbu2ss_writel(&udc->p_regs->EP0_WRITE, pBuf32->dw);
621 pBuf32++;
622 iWriteLength += sizeof(u32);
623 }
624
625 return iWriteLength;
626}
627
628/*-------------------------------------------------------------------------*/
629/* Endpoint 0 IN Transfer (PIO, OverBytes) */
630static int EP0_in_OverBytes(struct nbu2ss_udc *udc, u8 *pBuf, u32 iRemainSize)
631{
632 u32 i;
f6ef6c09
HM		 633 union usb_reg_access Temp32;
634 union usb_reg_access *pBuf32 = (union usb_reg_access *)pBuf;
33aa8d45 635
2866914c 636 if ((iRemainSize > 0) && (iRemainSize < sizeof(u32))) {
33aa8d45
MD		 637 for (i = 0 ; i < iRemainSize ; i++)
638 Temp32.byte.DATA[i] = pBuf32->byte.DATA[i];
639 _nbu2ss_ep_in_end(udc, 0, Temp32.dw, iRemainSize);
640
641 return iRemainSize;
642 }
643
644 return 0;
645}
646
647/*-------------------------------------------------------------------------*/
648/* Transfer NULL Packet (Epndoint 0) */
649static int EP0_send_NULL(struct nbu2ss_udc *udc, bool pid_flag)
650{
651 u32 data;
652
653 data = _nbu2ss_readl(&udc->p_regs->EP0_CONTROL);
654 data &= ~(u32)EP0_INAK;
655
656 if (pid_flag)
657 data |= (EP0_INAK_EN | EP0_PIDCLR | EP0_DEND);
658 else
659 data |= (EP0_INAK_EN | EP0_DEND);
660
661 _nbu2ss_writel(&udc->p_regs->EP0_CONTROL, data);
662
663 return 0;
664}
665
666/*-------------------------------------------------------------------------*/
667/* Receive NULL Packet (Endpoint 0) */
668static int EP0_receive_NULL(struct nbu2ss_udc *udc, bool pid_flag)
669{
670 u32 data;
671
672 data = _nbu2ss_readl(&udc->p_regs->EP0_CONTROL);
673 data &= ~(u32)EP0_ONAK;
674
675 if (pid_flag)
676 data |= EP0_PIDCLR;
677
678 _nbu2ss_writel(&udc->p_regs->EP0_CONTROL, data);
679
680 return 0;
681}
682
683/*-------------------------------------------------------------------------*/
684static int _nbu2ss_ep0_in_transfer(
685 struct nbu2ss_udc *udc,
33aa8d45
MD		 686 struct nbu2ss_req *req
687)
688{
689 u8 *pBuffer; /* IN Data Buffer */
690 u32 data;
691 u32 iRemainSize = 0;
692 int result = 0;
693
694 /*-------------------------------------------------------------*/
695 /* End confirmation */
696 if (req->req.actual == req->req.length) {
697 if ((req->req.actual % EP0_PACKETSIZE) == 0) {
698 if (req->zero) {
666e9084 699 req->zero = false;
33aa8d45
MD		 700 EP0_send_NULL(udc, FALSE);
701 return 1;
702 }
703 }
704
705 return 0; /* Transfer End */
706 }
707
708 /*-------------------------------------------------------------*/
709 /* NAK release */
710 data = _nbu2ss_readl(&udc->p_regs->EP0_CONTROL);
711 data |= EP0_INAK_EN;
712 data &= ~(u32)EP0_INAK;
713 _nbu2ss_writel(&udc->p_regs->EP0_CONTROL, data);
714
715 iRemainSize = req->req.length - req->req.actual;
716 pBuffer = (u8 *)req->req.buf;
717 pBuffer += req->req.actual;
718
719 /*-------------------------------------------------------------*/
720 /* Data transfer */
721 result = EP0_in_PIO(udc, pBuffer, iRemainSize);
722
723 req->div_len = result;
724 iRemainSize -= result;
725
726 if (iRemainSize == 0) {
727 EP0_send_NULL(udc, FALSE);
728 return result;
729 }
730
731 if ((iRemainSize < sizeof(u32)) && (result != EP0_PACKETSIZE)) {
732 pBuffer += result;
733 result += EP0_in_OverBytes(udc, pBuffer, iRemainSize);
734 req->div_len = result;
735 }
736
737 return result;
738}
739
740/*-------------------------------------------------------------------------*/
741static int _nbu2ss_ep0_out_transfer(
742 struct nbu2ss_udc *udc,
33aa8d45
MD		 743 struct nbu2ss_req *req
744)
745{
746 u8 *pBuffer;
747 u32 iRemainSize;
748 u32 iRecvLength;
749 int result = 0;
750 int fRcvZero;
751
752 /*-------------------------------------------------------------*/
753 /* Receive data confirmation */
754 iRecvLength = _nbu2ss_readl(&udc->p_regs->EP0_LENGTH) & EP0_LDATA;
755 if (iRecvLength != 0) {
756
757 fRcvZero = 0;
758
759 iRemainSize = req->req.length - req->req.actual;
760 pBuffer = (u8 *)req->req.buf;
761 pBuffer += req->req.actual;
762
763 result = EP0_out_PIO(udc, pBuffer
764 , min(iRemainSize, iRecvLength));
765 if (result < 0)
766 return result;
767
768 req->req.actual += result;
769 iRecvLength -= result;
770
2866914c 771 if ((iRecvLength > 0) && (iRecvLength < sizeof(u32))) {
33aa8d45
MD		 772 pBuffer += result;
773 iRemainSize -= result;
774
775 result = EP0_out_OverBytes(udc, pBuffer
776 , min(iRemainSize, iRecvLength));
777 req->req.actual += result;
778 }
779 } else {
780 fRcvZero = 1;
781 }
782
783 /*-------------------------------------------------------------*/
784 /* End confirmation */
785 if (req->req.actual == req->req.length) {
786 if ((req->req.actual % EP0_PACKETSIZE) == 0) {
787 if (req->zero) {
666e9084 788 req->zero = false;
33aa8d45
MD		 789 EP0_receive_NULL(udc, FALSE);
790 return 1;
791 }
792 }
793
794 return 0; /* Transfer End */
795 }
796
797 if ((req->req.actual % EP0_PACKETSIZE) != 0)
798 return 0; /* Short Packet Transfer End */
799
800 if (req->req.actual > req->req.length) {
88689279 801 dev_err(udc->dev, " *** Overrun Error\n");
33aa8d45
MD		 802 return -EOVERFLOW;
803 }
804
805 if (fRcvZero != 0) {
806 iRemainSize = _nbu2ss_readl(&udc->p_regs->EP0_CONTROL);
807 if (iRemainSize & EP0_ONAK) {
808 /*---------------------------------------------------*/
809 /* NACK release */
810 _nbu2ss_bitclr(&udc->p_regs->EP0_CONTROL, EP0_ONAK);
811 }
812 result = 1;
813 }
814
815 return result;
816}
817
818/*-------------------------------------------------------------------------*/
819static int _nbu2ss_out_dma(
820 struct nbu2ss_udc *udc,
821 struct nbu2ss_req *req,
822 u32 num,
823 u32 length
824)
825{
e7cfb390 826 dma_addr_t pBuffer;
33aa8d45
MD		 827 u32 mpkt;
828 u32 lmpkt;
829 u32 dmacnt;
830 u32 burst = 1;
831 u32 data;
832 int result = -EINVAL;
f6ef6c09 833 struct fc_regs *preg = udc->p_regs;
33aa8d45
MD		 834
835 if (req->dma_flag)
836 return 1; /* DMA is forwarded */
837
838 req->dma_flag = TRUE;
e7cfb390 839 pBuffer = req->req.dma;
33aa8d45
MD		 840 pBuffer += req->req.actual;
841
842 /* DMA Address */
843 _nbu2ss_writel(&preg->EP_DCR[num].EP_TADR, (u32)pBuffer);
844
845 /* Number of transfer packets */
846 mpkt = _nbu2ss_readl(&preg->EP_REGS[num].EP_PCKT_ADRS) & EPn_MPKT;
599b8780 847 dmacnt = length / mpkt;
33aa8d45
MD		 848 lmpkt = (length % mpkt) & ~(u32)0x03;
849
2866914c 850 if (dmacnt > DMA_MAX_COUNT) {
33aa8d45
MD		 851 dmacnt = DMA_MAX_COUNT;
852 lmpkt = 0;
2866914c
CM		 853 } else if (lmpkt != 0) {
854 if (dmacnt == 0)
33aa8d45
MD		 855 burst = 0; /* Burst OFF */
856 dmacnt++;
857 }
858
859 data = mpkt | (lmpkt << 16);
860 _nbu2ss_writel(&preg->EP_DCR[num].EP_DCR2, data);
861
862 data = ((dmacnt & 0xff) << 16) | DCR1_EPn_DIR0 | DCR1_EPn_REQEN;
863 _nbu2ss_writel(&preg->EP_DCR[num].EP_DCR1, data);
864
2866914c 865 if (burst == 0) {
33aa8d45
MD		 866 _nbu2ss_writel(&preg->EP_REGS[num].EP_LEN_DCNT, 0);
867 _nbu2ss_bitclr(&preg->EP_REGS[num].EP_DMA_CTRL, EPn_BURST_SET);
868 } else {
869 _nbu2ss_writel(&preg->EP_REGS[num].EP_LEN_DCNT
870 , (dmacnt << 16));
871 _nbu2ss_bitset(&preg->EP_REGS[num].EP_DMA_CTRL, EPn_BURST_SET);
872 }
873 _nbu2ss_bitset(&preg->EP_REGS[num].EP_DMA_CTRL, EPn_DMA_EN);
874
875 result = length & ~(u32)0x03;
876 req->div_len = result;
877
878 return result;
879}
880
881/*-------------------------------------------------------------------------*/
882static int _nbu2ss_epn_out_pio(
883 struct nbu2ss_udc *udc,
884 struct nbu2ss_ep *ep,
885 struct nbu2ss_req *req,
886 u32 length
887)
888{
889 u8 *pBuffer;
890 u32 i;
891 u32 data;
892 u32 iWordLength;
f6ef6c09
HM		 893 union usb_reg_access Temp32;
894 union usb_reg_access *pBuf32;
33aa8d45 895 int result = 0;
f6ef6c09 896 struct fc_regs *preg = udc->p_regs;
33aa8d45
MD		 897
898 if (req->dma_flag)
899 return 1; /* DMA is forwarded */
900
901 if (length == 0)
902 return 0;
903
904 pBuffer = (u8 *)req->req.buf;
f6ef6c09 905 pBuf32 = (union usb_reg_access *)(pBuffer + req->req.actual);
33aa8d45
MD		 906
907 iWordLength = length / sizeof(u32);
908 if (iWordLength > 0) {
909 /*---------------------------------------------------------*/
910 /* Copy of every four bytes */
911 for (i = 0; i < iWordLength; i++) {
912 pBuf32->dw =
abe34174 913 _nbu2ss_readl(&preg->EP_REGS[ep->epnum - 1].EP_READ);
33aa8d45
MD		 914 pBuf32++;
915 }
916 result = iWordLength * sizeof(u32);
917 }
918
919 data = length - result;
920 if (data > 0) {
921 /*---------------------------------------------------------*/
922 /* Copy of fraction byte */
abe34174 923 Temp32.dw = _nbu2ss_readl(&preg->EP_REGS[ep->epnum - 1].EP_READ);
33aa8d45
MD		 924 for (i = 0 ; i < data ; i++)
925 pBuf32->byte.DATA[i] = Temp32.byte.DATA[i];
926 result += data;
927 }
928
929 req->req.actual += result;
930
931 if ((req->req.actual == req->req.length)
932 || ((req->req.actual % ep->ep.maxpacket) != 0)) {
933
934 result = 0;
935 }
936
937 return result;
938}
939
940/*-------------------------------------------------------------------------*/
941static int _nbu2ss_epn_out_data(
942 struct nbu2ss_udc *udc,
943 struct nbu2ss_ep *ep,
944 struct nbu2ss_req *req,
945 u32 data_size
946)
947{
948 u32 num;
949 u32 iBufSize;
950 int nret = 1;
951
952 if (ep->epnum == 0)
953 return -EINVAL;
954
955 num = ep->epnum - 1;
956
957 iBufSize = min((req->req.length - req->req.actual), data_size);
958
959 if ((ep->ep_type != USB_ENDPOINT_XFER_INT)
960 && (req->req.dma != 0)
961 && (iBufSize >= sizeof(u32))) {
962 nret = _nbu2ss_out_dma(udc, req, num, iBufSize);
963 } else {
77d966f4 964 iBufSize = min_t(u32, iBufSize, ep->ep.maxpacket);
33aa8d45
MD		 965 nret = _nbu2ss_epn_out_pio(udc, ep, req, iBufSize);
966 }
967
968 return nret;
969}
970
971/*-------------------------------------------------------------------------*/
972static int _nbu2ss_epn_out_transfer(
973 struct nbu2ss_udc *udc,
974 struct nbu2ss_ep *ep,
975 struct nbu2ss_req *req
976)
977{
978 u32 num;
979 u32 iRecvLength;
980 int result = 1;
f6ef6c09 981 struct fc_regs *preg = udc->p_regs;
33aa8d45
MD		 982
983 if (ep->epnum == 0)
984 return -EINVAL;
985
986 num = ep->epnum - 1;
987
988 /*-------------------------------------------------------------*/
989 /* Receive Length */
990 iRecvLength
991 = _nbu2ss_readl(&preg->EP_REGS[num].EP_LEN_DCNT) & EPn_LDATA;
992
993 if (iRecvLength != 0) {
994 result = _nbu2ss_epn_out_data(udc, ep, req, iRecvLength);
995 if (iRecvLength < ep->ep.maxpacket) {
996 if (iRecvLength == result) {
997 req->req.actual += result;
998 result = 0;
999 }
1000 }
1001 } else {
1002 if ((req->req.actual == req->req.length)
1003 || ((req->req.actual % ep->ep.maxpacket) != 0)) {
1004
1005 result = 0;
1006 }
1007 }
1008
1009 if (result == 0) {
1010 if ((req->req.actual % ep->ep.maxpacket) == 0) {
1011 if (req->zero) {
666e9084 1012 req->zero = false;
33aa8d45
MD		 1013 return 1;
1014 }
1015 }
1016 }
1017
1018 if (req->req.actual > req->req.length) {
88689279
HM		 1019 dev_err(udc->dev, " Overrun Error\n");
1020 dev_err(udc->dev, " actual = %d, length = %d\n",
33aa8d45
MD		 1021 req->req.actual, req->req.length);
1022 result = -EOVERFLOW;
1023 }
1024
1025 return result;
1026}
1027
1028/*-------------------------------------------------------------------------*/
1029static int _nbu2ss_in_dma(
1030 struct nbu2ss_udc *udc,
1031 struct nbu2ss_ep *ep,
1032 struct nbu2ss_req *req,
1033 u32 num,
1034 u32 length
1035)
1036{
e7cfb390 1037 dma_addr_t pBuffer;
33aa8d45
MD		 1038 u32 mpkt; /* MaxPacketSize */
1039 u32 lmpkt; /* Last Packet Data Size */
1040 u32 dmacnt; /* IN Data Size */
1041 u32 iWriteLength;
1042 u32 data;
1043 int result = -EINVAL;
f6ef6c09 1044 struct fc_regs *preg = udc->p_regs;
33aa8d45
MD		 1045
1046 if (req->dma_flag)
1047 return 1; /* DMA is forwarded */
1048
1049#ifdef USE_DMA
1050 if (req->req.actual == 0)
1051 _nbu2ss_dma_map_single(udc, ep, req, USB_DIR_IN);
1052#endif
1053 req->dma_flag = TRUE;
1054
1055 /* MAX Packet Size */
1056 mpkt = _nbu2ss_readl(&preg->EP_REGS[num].EP_PCKT_ADRS) & EPn_MPKT;
1057
1058 if ((DMA_MAX_COUNT * mpkt) < length)
1059 iWriteLength = DMA_MAX_COUNT * mpkt;
1060 else
1061 iWriteLength = length;
1062
1063 /*------------------------------------------------------------*/
1064 /* Number of transmission packets */
1065 if (mpkt < iWriteLength) {
1066 dmacnt = iWriteLength / mpkt;
1067 lmpkt = (iWriteLength % mpkt) & ~(u32)0x3;
1068 if (lmpkt != 0)
1069 dmacnt++;
1070 else
1071 lmpkt = mpkt & ~(u32)0x3;
1072
1073 } else {
1074 dmacnt = 1;
1075 lmpkt = iWriteLength & ~(u32)0x3;
1076 }
1077
1078 /* Packet setting */
1079 data = mpkt | (lmpkt << 16);
1080 _nbu2ss_writel(&preg->EP_DCR[num].EP_DCR2, data);
1081
1082 /* Address setting */
e7cfb390 1083 pBuffer = req->req.dma;
33aa8d45
MD		 1084 pBuffer += req->req.actual;
1085 _nbu2ss_writel(&preg->EP_DCR[num].EP_TADR, (u32)pBuffer);
1086
1087 /* Packet and DMA setting */
1088 data = ((dmacnt & 0xff) << 16) | DCR1_EPn_REQEN;
1089 _nbu2ss_writel(&preg->EP_DCR[num].EP_DCR1, data);
1090
1091 /* Packet setting of EPC */
1092 data = dmacnt << 16;
1093 _nbu2ss_writel(&preg->EP_REGS[num].EP_LEN_DCNT, data);
1094
1095 /*DMA setting of EPC */
1096 _nbu2ss_bitset(&preg->EP_REGS[num].EP_DMA_CTRL, EPn_DMA_EN);
1097
1098 result = iWriteLength & ~(u32)0x3;
1099 req->div_len = result;
1100
1101 return result;
1102}
1103
1104/*-------------------------------------------------------------------------*/
1105static int _nbu2ss_epn_in_pio(
1106 struct nbu2ss_udc *udc,
1107 struct nbu2ss_ep *ep,
1108 struct nbu2ss_req *req,
1109 u32 length
1110)
1111{
1112 u8 *pBuffer;
1113 u32 i;
1114 u32 data;
1115 u32 iWordLength;
f6ef6c09
HM		 1116 union usb_reg_access Temp32;
1117 union usb_reg_access *pBuf32 = NULL;
33aa8d45 1118 int result = 0;
f6ef6c09 1119 struct fc_regs *preg = udc->p_regs;
33aa8d45
MD		 1120
1121 if (req->dma_flag)
1122 return 1; /* DMA is forwarded */
1123
1124 if (length > 0) {
1125 pBuffer = (u8 *)req->req.buf;
f6ef6c09 1126 pBuf32 = (union usb_reg_access *)(pBuffer + req->req.actual);
33aa8d45
MD		 1127
1128 iWordLength = length / sizeof(u32);
1129 if (iWordLength > 0) {
1130 for (i = 0; i < iWordLength; i++) {
1131 _nbu2ss_writel(
abe34174 1132 &preg->EP_REGS[ep->epnum - 1].EP_WRITE
33aa8d45
MD		 1133 , pBuf32->dw
1134 );
1135
1136 pBuf32++;
1137 }
1138 result = iWordLength * sizeof(u32);
1139 }
1140 }
1141
1142 if (result != ep->ep.maxpacket) {
1143 data = length - result;
1144 Temp32.dw = 0;
1145 for (i = 0 ; i < data ; i++)
1146 Temp32.byte.DATA[i] = pBuf32->byte.DATA[i];
1147
1148 _nbu2ss_ep_in_end(udc, ep->epnum, Temp32.dw, data);
1149 result += data;
1150 }
1151
1152 req->div_len = result;
1153
1154 return result;
1155}
1156
1157/*-------------------------------------------------------------------------*/
1158static int _nbu2ss_epn_in_data(
1159 struct nbu2ss_udc *udc,
1160 struct nbu2ss_ep *ep,
1161 struct nbu2ss_req *req,
1162 u32 data_size
1163)
1164{
1165 u32 num;
1166 int nret = 1;
1167
1168 if (ep->epnum == 0)
1169 return -EINVAL;
1170
1171 num = ep->epnum - 1;
1172
1173 if ((ep->ep_type != USB_ENDPOINT_XFER_INT)
1174 && (req->req.dma != 0)
1175 && (data_size >= sizeof(u32))) {
1176 nret = _nbu2ss_in_dma(udc, ep, req, num, data_size);
1177 } else {
77d966f4 1178 data_size = min_t(u32, data_size, ep->ep.maxpacket);
33aa8d45
MD		 1179 nret = _nbu2ss_epn_in_pio(udc, ep, req, data_size);
1180 }
1181
1182 return nret;
1183}
1184
1185/*-------------------------------------------------------------------------*/
1186static int _nbu2ss_epn_in_transfer(
1187 struct nbu2ss_udc *udc,
1188 struct nbu2ss_ep *ep,
1189 struct nbu2ss_req *req
1190)
1191{
1192 u32 num;
1193 u32 iBufSize;
1194 int result = 0;
1195 u32 status;
1196
1197 if (ep->epnum == 0)
1198 return -EINVAL;
1199
1200 num = ep->epnum - 1;
1201
1202 status = _nbu2ss_readl(&udc->p_regs->EP_REGS[num].EP_STATUS);
1203
1204 /*-------------------------------------------------------------*/
1205 /* State confirmation of FIFO */
1206 if (req->req.actual == 0) {
1207 if ((status & EPn_IN_EMPTY) == 0)
1208 return 1; /* Not Empty */
1209
1210 } else {
1211 if ((status & EPn_IN_FULL) != 0)
1212 return 1; /* Not Empty */
1213 }
1214
1215 /*-------------------------------------------------------------*/
69e98df7 1216 /* Start transfer */
33aa8d45
MD		 1217 iBufSize = req->req.length - req->req.actual;
1218 if (iBufSize > 0)
1219 result = _nbu2ss_epn_in_data(udc, ep, req, iBufSize);
1220 else if (req->req.length == 0)
1221 _nbu2ss_zero_len_pkt(udc, ep->epnum);
1222
1223 return result;
1224}
1225
1226/*-------------------------------------------------------------------------*/
1227static int _nbu2ss_start_transfer(
1228 struct nbu2ss_udc *udc,
1229 struct nbu2ss_ep *ep,
1230 struct nbu2ss_req *req,
1231 bool bflag)
1232{
1233 int nret = -EINVAL;
1234
1235 req->dma_flag = FALSE;
1236 req->div_len = 0;
1237
1238 if (req->req.length == 0)
666e9084 1239 req->zero = false;
33aa8d45
MD		 1240 else {
1241 if ((req->req.length % ep->ep.maxpacket) == 0)
1242 req->zero = req->req.zero;
1243 else
666e9084 1244 req->zero = false;
33aa8d45
MD		 1245 }
1246
1247 if (ep->epnum == 0) {
1248 /* EP0 */
1249 switch (udc->ep0state) {
1250 case EP0_IN_DATA_PHASE:
f2b29165 1251 nret = _nbu2ss_ep0_in_transfer(udc, req);
33aa8d45
MD		 1252 break;
1253
1254 case EP0_OUT_DATA_PHASE:
f2b29165 1255 nret = _nbu2ss_ep0_out_transfer(udc, req);
33aa8d45
MD		 1256 break;
1257
1258 case EP0_IN_STATUS_PHASE:
1259 nret = EP0_send_NULL(udc, TRUE);
1260 break;
1261
1262 default:
1263 break;
1264 }
1265
1266 } else {
1267 /* EPn */
1268 if (ep->direct == USB_DIR_OUT) {
1269 /* OUT */
5a602ac4 1270 if (!bflag)
33aa8d45
MD		 1271 nret = _nbu2ss_epn_out_transfer(udc, ep, req);
1272 } else {
1273 /* IN */
1274 nret = _nbu2ss_epn_in_transfer(udc, ep, req);
1275 }
1276 }
1277
1278 return nret;
1279}
1280
1281/*-------------------------------------------------------------------------*/
1282static void _nbu2ss_restert_transfer(struct nbu2ss_ep *ep)
1283{
1284 u32 length;
1285 bool bflag = FALSE;
1286 struct nbu2ss_req *req;
1287
e59ac747 1288 req = list_first_entry_or_null(&ep->queue, struct nbu2ss_req, queue);
706eb8cf 1289 if (!req)
33aa8d45
MD		 1290 return;
1291
1292 if (ep->epnum > 0) {
1293 length = _nbu2ss_readl(
abe34174 1294 &ep->udc->p_regs->EP_REGS[ep->epnum - 1].EP_LEN_DCNT);
33aa8d45
MD		 1295
1296 length &= EPn_LDATA;
1297 if (length < ep->ep.maxpacket)
1298 bflag = TRUE;
1299 }
1300
1301 _nbu2ss_start_transfer(ep->udc, ep, req, bflag);
1302}
1303
1304/*-------------------------------------------------------------------------*/
1305/* Endpoint Toggle Reset */
1306static void _nbu2ss_endpoint_toggle_reset(
1307 struct nbu2ss_udc *udc,
1308 u8 ep_adrs)
1309{
1310 u8 num;
1311 u32 data;
1312
1313 if ((ep_adrs == 0) || (ep_adrs == 0x80))
1314 return;
1315
1316 num = (ep_adrs & 0x7F) - 1;
1317
1318 if (ep_adrs & USB_DIR_IN)
1319 data = EPn_IPIDCLR;
1320 else
1321 data = EPn_BCLR | EPn_OPIDCLR;
1322
1323 _nbu2ss_bitset(&udc->p_regs->EP_REGS[num].EP_CONTROL, data);
1324}
1325
1326/*-------------------------------------------------------------------------*/
1327/* Endpoint STALL set */
1328static void _nbu2ss_set_endpoint_stall(
1329 struct nbu2ss_udc *udc,
1330 u8 ep_adrs,
1331 bool bstall)
1332{
1333 u8 num, epnum;
1334 u32 data;
1335 struct nbu2ss_ep *ep;
f6ef6c09 1336 struct fc_regs *preg = udc->p_regs;
33aa8d45
MD		 1337
1338 if ((ep_adrs == 0) || (ep_adrs == 0x80)) {
1339 if (bstall) {
1340 /* Set STALL */
1341 _nbu2ss_bitset(&preg->EP0_CONTROL, EP0_STL);
1342 } else {
1343 /* Clear STALL */
1344 _nbu2ss_bitclr(&preg->EP0_CONTROL, EP0_STL);
1345 }
1346 } else {
1347 epnum = ep_adrs & USB_ENDPOINT_NUMBER_MASK;
1348 num = epnum - 1;
1349 ep = &udc->ep[epnum];
1350
1351 if (bstall) {
1352 /* Set STALL */
1353 ep->halted = TRUE;
1354
1355 if (ep_adrs & USB_DIR_IN)
1356 data = EPn_BCLR | EPn_ISTL;
1357 else
1358 data = EPn_OSTL_EN | EPn_OSTL;
1359
1360 _nbu2ss_bitset(&preg->EP_REGS[num].EP_CONTROL, data);
1361 } else {
1362 /* Clear STALL */
1363 ep->stalled = FALSE;
1364 if (ep_adrs & USB_DIR_IN) {
1365 _nbu2ss_bitclr(&preg->EP_REGS[num].EP_CONTROL
1366 , EPn_ISTL);
1367 } else {
1368 data =
1369 _nbu2ss_readl(&preg->EP_REGS[num].EP_CONTROL);
1370
1371 data &= ~EPn_OSTL;
1372 data |= EPn_OSTL_EN;
1373
1374 _nbu2ss_writel(&preg->EP_REGS[num].EP_CONTROL
1375 , data);
1376 }
1377
1378 ep->stalled = FALSE;
1379 if (ep->halted) {
1380 ep->halted = FALSE;
1381 _nbu2ss_restert_transfer(ep);
1382 }
1383 }
1384 }
33aa8d45
MD		 1385}
1386
33aa8d45
MD		 1387/*-------------------------------------------------------------------------*/
1388/* Device Descriptor */
1389static struct usb_device_descriptor device_desc = {
1390 .bLength = sizeof(device_desc),
1391 .bDescriptorType = USB_DT_DEVICE,
1ff99b31 1392 .bcdUSB = cpu_to_le16(0x0200),
33aa8d45
MD		 1393 .bDeviceClass = USB_CLASS_VENDOR_SPEC,
1394 .bDeviceSubClass = 0x00,
1395 .bDeviceProtocol = 0x00,
1396 .bMaxPacketSize0 = 64,
1ff99b31
RD		 1397 .idVendor = cpu_to_le16(0x0409),
1398 .idProduct = cpu_to_le16(0xfff0),
33aa8d45
MD		 1399 .bcdDevice = 0xffff,
1400 .iManufacturer = 0x00,
1401 .iProduct = 0x00,
1402 .iSerialNumber = 0x00,
1403 .bNumConfigurations = 0x01,
1404};
1405
1406/*-------------------------------------------------------------------------*/
1407static void _nbu2ss_set_test_mode(struct nbu2ss_udc *udc, u32 mode)
1408{
1409 u32 data;
1410
1411 if (mode > MAX_TEST_MODE_NUM)
1412 return;
1413
93275c80 1414 dev_info(udc->dev, "SET FEATURE : test mode = %d\n", mode);
33aa8d45
MD		 1415
1416 data = _nbu2ss_readl(&udc->p_regs->USB_CONTROL);
1417 data &= ~TEST_FORCE_ENABLE;
1418 data |= mode << TEST_MODE_SHIFT;
1419
1420 _nbu2ss_writel(&udc->p_regs->USB_CONTROL, data);
1421 _nbu2ss_bitset(&udc->p_regs->TEST_CONTROL, CS_TESTMODEEN);
1422}
1423
1424/*-------------------------------------------------------------------------*/
1425static int _nbu2ss_set_feature_device(
1426 struct nbu2ss_udc *udc,
1427 u16 selector,
1428 u16 wIndex
1429)
1430{
1431 int result = -EOPNOTSUPP;
1432
1433 switch (selector) {
1434 case USB_DEVICE_REMOTE_WAKEUP:
2866914c 1435 if (wIndex == 0x0000) {
33aa8d45
MD		 1436 udc->remote_wakeup = U2F_ENABLE;
1437 result = 0;
1438 }
1439 break;
1440
1441 case USB_DEVICE_TEST_MODE:
410c944e 1442 wIndex >>= 8;
33aa8d45
MD		 1443 if (wIndex <= MAX_TEST_MODE_NUM)
1444 result = 0;
1445 break;
1446
1447 default:
1448 break;
1449 }
1450
1451 return result;
1452}
1453
1454/*-------------------------------------------------------------------------*/
1455static int _nbu2ss_get_ep_stall(struct nbu2ss_udc *udc, u8 ep_adrs)
1456{
1457 u8 epnum;
1458 u32 data = 0, bit_data;
f6ef6c09 1459 struct fc_regs *preg = udc->p_regs;
33aa8d45
MD		 1460
1461 epnum = ep_adrs & ~USB_ENDPOINT_DIR_MASK;
1462 if (epnum == 0) {
1463 data = _nbu2ss_readl(&preg->EP0_CONTROL);
1464 bit_data = EP0_STL;
1465
1466 } else {
abe34174 1467 data = _nbu2ss_readl(&preg->EP_REGS[epnum - 1].EP_CONTROL);
33aa8d45
MD		 1468 if ((data & EPn_EN) == 0)
1469 return -1;
1470
1471 if (ep_adrs & USB_ENDPOINT_DIR_MASK)
1472 bit_data = EPn_ISTL;
1473 else
1474 bit_data = EPn_OSTL;
1475 }
1476
1477 if ((data & bit_data) == 0)
1478 return 0;
924c6ee1 1479 return 1;
33aa8d45
MD		 1480}
1481
1482/*-------------------------------------------------------------------------*/
1483static inline int _nbu2ss_req_feature(struct nbu2ss_udc *udc, bool bset)
1484{
1485 u8 recipient = (u8)(udc->ctrl.bRequestType & USB_RECIP_MASK);
1486 u8 direction = (u8)(udc->ctrl.bRequestType & USB_DIR_IN);
1487 u16 selector = udc->ctrl.wValue;
1488 u16 wIndex = udc->ctrl.wIndex;
1489 u8 ep_adrs;
1490 int result = -EOPNOTSUPP;
1491
2866914c 1492 if ((udc->ctrl.wLength != 0x0000) ||
c75955d1 1493 (direction != USB_DIR_OUT)) {
33aa8d45
MD		 1494 return -EINVAL;
1495 }
1496
1497 switch (recipient) {
1498 case USB_RECIP_DEVICE:
1499 if (bset)
1500 result =
1501 _nbu2ss_set_feature_device(udc, selector, wIndex);
1502 break;
1503
1504 case USB_RECIP_ENDPOINT:
1505 if (0x0000 == (wIndex & 0xFF70)) {
2866914c 1506 if (selector == USB_ENDPOINT_HALT) {
33aa8d45 1507 ep_adrs = wIndex & 0xFF;
5a602ac4 1508 if (!bset) {
33aa8d45
MD		 1509 _nbu2ss_endpoint_toggle_reset(
1510 udc, ep_adrs);
1511 }
1512
1513 _nbu2ss_set_endpoint_stall(
1514 udc, ep_adrs, bset);
1515
1516 result = 0;
1517 }
1518 }
1519 break;
1520
1521 default:
1522 break;
1523 }
1524
1525 if (result >= 0)
1526 _nbu2ss_create_ep0_packet(udc, udc->ep0_buf, 0);
1527
1528 return result;
1529}
1530
1531/*-------------------------------------------------------------------------*/
1532static inline enum usb_device_speed _nbu2ss_get_speed(struct nbu2ss_udc *udc)
1533{
1534 u32 data;
1535 enum usb_device_speed speed = USB_SPEED_FULL;
1536
1537 data = _nbu2ss_readl(&udc->p_regs->USB_STATUS);
1538 if (data & HIGH_SPEED)
1539 speed = USB_SPEED_HIGH;
1540
1541 return speed;
1542}
1543
1544/*-------------------------------------------------------------------------*/
1545static void _nbu2ss_epn_set_stall(
1546 struct nbu2ss_udc *udc,
1547 struct nbu2ss_ep *ep
1548)
1549{
1550 u8 ep_adrs;
1551 u32 regdata;
1552 int limit_cnt = 0;
1553
f6ef6c09 1554 struct fc_regs *preg = udc->p_regs;
33aa8d45
MD		 1555
1556 if (ep->direct == USB_DIR_IN) {
1557 for (limit_cnt = 0
1558 ; limit_cnt < IN_DATA_EMPTY_COUNT
1559 ; limit_cnt++) {
1560
1561 regdata = _nbu2ss_readl(
abe34174 1562 &preg->EP_REGS[ep->epnum - 1].EP_STATUS);
33aa8d45
MD		 1563
1564 if ((regdata & EPn_IN_DATA) == 0)
1565 break;
1566
1567 mdelay(1);
1568 }
1569 }
1570
1571 ep_adrs = ep->epnum | ep->direct;
1572 _nbu2ss_set_endpoint_stall(udc, ep_adrs, 1);
1573}
1574
1575/*-------------------------------------------------------------------------*/
1576static int std_req_get_status(struct nbu2ss_udc *udc)
1577{
1578 u32 length;
1579 u16 status_data = 0;
1580 u8 recipient = (u8)(udc->ctrl.bRequestType & USB_RECIP_MASK);
1581 u8 direction = (u8)(udc->ctrl.bRequestType & USB_DIR_IN);
1582 u8 ep_adrs;
1583 int result = -EINVAL;
1584
2866914c
CM		 1585 if ((udc->ctrl.wValue != 0x0000)
1586 || (direction != USB_DIR_IN)) {
33aa8d45
MD		 1587
1588 return result;
1589 }
1590
77d966f4 1591 length = min_t(u16, udc->ctrl.wLength, sizeof(status_data));
33aa8d45
MD		 1592
1593 switch (recipient) {
1594 case USB_RECIP_DEVICE:
1595 if (udc->ctrl.wIndex == 0x0000) {
9239d88f 1596 if (udc->gadget.is_selfpowered)
33aa8d45
MD		 1597 status_data |= (1 << USB_DEVICE_SELF_POWERED);
1598
1599 if (udc->remote_wakeup)
1600 status_data |= (1 << USB_DEVICE_REMOTE_WAKEUP);
1601
1602 result = 0;
1603 }
1604 break;
1605
1606 case USB_RECIP_ENDPOINT:
1607 if (0x0000 == (udc->ctrl.wIndex & 0xFF70)) {
1608 ep_adrs = (u8)(udc->ctrl.wIndex & 0xFF);
1609 result = _nbu2ss_get_ep_stall(udc, ep_adrs);
1610
1611 if (result > 0)
1612 status_data |= (1 << USB_ENDPOINT_HALT);
1613 }
1614 break;
1615
1616 default:
1617 break;
1618 }
1619
1620 if (result >= 0) {
1621 memcpy(udc->ep0_buf, &status_data, length);
1622 _nbu2ss_create_ep0_packet(udc, udc->ep0_buf, length);
f2b29165 1623 _nbu2ss_ep0_in_transfer(udc, &udc->ep0_req);
33aa8d45
MD		 1624
1625 } else {
88689279 1626 dev_err(udc->dev, " Error GET_STATUS\n");
33aa8d45
MD		 1627 }
1628
1629 return result;
1630}
1631
1632/*-------------------------------------------------------------------------*/
1633static int std_req_clear_feature(struct nbu2ss_udc *udc)
1634{
1635 return _nbu2ss_req_feature(udc, FALSE);
1636}
1637
1638/*-------------------------------------------------------------------------*/
1639static int std_req_set_feature(struct nbu2ss_udc *udc)
1640{
1641 return _nbu2ss_req_feature(udc, TRUE);
1642}
1643
1644/*-------------------------------------------------------------------------*/
1645static int std_req_set_address(struct nbu2ss_udc *udc)
1646{
1647 int result = 0;
1648 u32 wValue = udc->ctrl.wValue;
1649
2866914c 1650 if ((udc->ctrl.bRequestType != 0x00) ||
c75955d1 1651 (udc->ctrl.wIndex != 0x0000) ||
2866914c 1652 (udc->ctrl.wLength != 0x0000)) {
33aa8d45
MD		 1653 return -EINVAL;
1654 }
1655
1656 if (wValue != (wValue & 0x007F))
1657 return -EINVAL;
1658
410c944e 1659 wValue <<= USB_ADRS_SHIFT;
33aa8d45
MD		 1660
1661 _nbu2ss_writel(&udc->p_regs->USB_ADDRESS, wValue);
1662 _nbu2ss_create_ep0_packet(udc, udc->ep0_buf, 0);
1663
1664 return result;
1665}
1666
1667/*-------------------------------------------------------------------------*/
1668static int std_req_set_configuration(struct nbu2ss_udc *udc)
1669{
1670 u32 ConfigValue = (u32)(udc->ctrl.wValue & 0x00ff);
1671
2866914c 1672 if ((udc->ctrl.wIndex != 0x0000) ||
c75955d1 1673 (udc->ctrl.wLength != 0x0000) ||
2866914c 1674 (udc->ctrl.bRequestType != 0x00)) {
33aa8d45
MD		 1675 return -EINVAL;
1676 }
1677
1678 udc->curr_config = ConfigValue;
1679
1680 if (ConfigValue > 0) {
1681 _nbu2ss_bitset(&udc->p_regs->USB_CONTROL, CONF);
1682 udc->devstate = USB_STATE_CONFIGURED;
1683
1684 } else {
1685 _nbu2ss_bitclr(&udc->p_regs->USB_CONTROL, CONF);
1686 udc->devstate = USB_STATE_ADDRESS;
1687 }
1688
1689 return 0;
1690}
1691
1692/*-------------------------------------------------------------------------*/
1693static inline void _nbu2ss_read_request_data(struct nbu2ss_udc *udc, u32 *pdata)
1694{
706eb8cf 1695 if ((!udc) && (!pdata))
33aa8d45
MD		 1696 return;
1697
1698 *pdata = _nbu2ss_readl(&udc->p_regs->SETUP_DATA0);
1699 pdata++;
1700 *pdata = _nbu2ss_readl(&udc->p_regs->SETUP_DATA1);
1701}
1702
1703/*-------------------------------------------------------------------------*/
1704static inline int _nbu2ss_decode_request(struct nbu2ss_udc *udc)
1705{
1706 bool bcall_back = TRUE;
1707 int nret = -EINVAL;
1708 struct usb_ctrlrequest *p_ctrl;
1709
1710 p_ctrl = &udc->ctrl;
1711 _nbu2ss_read_request_data(udc, (u32 *)p_ctrl);
1712
1713 /* ep0 state control */
1714 if (p_ctrl->wLength == 0) {
1715 udc->ep0state = EP0_IN_STATUS_PHASE;
1716
1717 } else {
1718 if (p_ctrl->bRequestType & USB_DIR_IN)
1719 udc->ep0state = EP0_IN_DATA_PHASE;
1720 else
1721 udc->ep0state = EP0_OUT_DATA_PHASE;
1722 }
1723
1724 if ((p_ctrl->bRequestType & USB_TYPE_MASK) == USB_TYPE_STANDARD) {
1725 switch (p_ctrl->bRequest) {
1726 case USB_REQ_GET_STATUS:
1727 nret = std_req_get_status(udc);
1728 bcall_back = FALSE;
1729 break;
1730
1731 case USB_REQ_CLEAR_FEATURE:
1732 nret = std_req_clear_feature(udc);
1733 bcall_back = FALSE;
1734 break;
1735
1736 case USB_REQ_SET_FEATURE:
1737 nret = std_req_set_feature(udc);
1738 bcall_back = FALSE;
1739 break;
1740
1741 case USB_REQ_SET_ADDRESS:
1742 nret = std_req_set_address(udc);
1743 bcall_back = FALSE;
1744 break;
1745
1746 case USB_REQ_SET_CONFIGURATION:
1747 nret = std_req_set_configuration(udc);
1748 break;
1749
1750 default:
1751 break;
1752 }
1753 }
1754
5a602ac4 1755 if (!bcall_back) {
33aa8d45
MD		 1756 if (udc->ep0state == EP0_IN_STATUS_PHASE) {
1757 if (nret >= 0) {
1758 /*--------------------------------------*/
1759 /* Status Stage */
1760 nret = EP0_send_NULL(udc, TRUE);
1761 }
1762 }
1763
1764 } else {
1765 spin_unlock(&udc->lock);
1766 nret = udc->driver->setup(&udc->gadget, &udc->ctrl);
1767 spin_lock(&udc->lock);
1768 }
1769
1770 if (nret < 0)
1771 udc->ep0state = EP0_IDLE;
1772
1773 return nret;
1774}
1775
1776/*-------------------------------------------------------------------------*/
1777static inline int _nbu2ss_ep0_in_data_stage(struct nbu2ss_udc *udc)
1778{
1779 int nret;
1780 struct nbu2ss_req *req;
1781 struct nbu2ss_ep *ep = &udc->ep[0];
1782
e59ac747 1783 req = list_first_entry_or_null(&ep->queue, struct nbu2ss_req, queue);
706eb8cf 1784 if (!req)
33aa8d45
MD		 1785 req = &udc->ep0_req;
1786
1787 req->req.actual += req->div_len;
1788 req->div_len = 0;
1789
f2b29165 1790 nret = _nbu2ss_ep0_in_transfer(udc, req);
33aa8d45
MD		 1791 if (nret == 0) {
1792 udc->ep0state = EP0_OUT_STATUS_PAHSE;
1793 EP0_receive_NULL(udc, TRUE);
1794 }
1795
1796 return 0;
1797}
1798
1799/*-------------------------------------------------------------------------*/
1800static inline int _nbu2ss_ep0_out_data_stage(struct nbu2ss_udc *udc)
1801{
1802 int nret;
1803 struct nbu2ss_req *req;
1804 struct nbu2ss_ep *ep = &udc->ep[0];
1805
e59ac747 1806 req = list_first_entry_or_null(&ep->queue, struct nbu2ss_req, queue);
706eb8cf 1807 if (!req)
33aa8d45
MD		 1808 req = &udc->ep0_req;
1809
f2b29165 1810 nret = _nbu2ss_ep0_out_transfer(udc, req);
33aa8d45
MD		 1811 if (nret == 0) {
1812 udc->ep0state = EP0_IN_STATUS_PHASE;
1813 EP0_send_NULL(udc, TRUE);
1814
1815 } else if (nret < 0) {
1816 _nbu2ss_bitset(&udc->p_regs->EP0_CONTROL, EP0_BCLR);
1817 req->req.status = nret;
1818 }
1819
1820 return 0;
1821}
1822
1823/*-------------------------------------------------------------------------*/
1824static inline int _nbu2ss_ep0_status_stage(struct nbu2ss_udc *udc)
1825{
1826 struct nbu2ss_req *req;
1827 struct nbu2ss_ep *ep = &udc->ep[0];
1828
e59ac747 1829 req = list_first_entry_or_null(&ep->queue, struct nbu2ss_req, queue);
706eb8cf 1830 if (!req) {
33aa8d45
MD		 1831 req = &udc->ep0_req;
1832 if (req->req.complete)
1833 req->req.complete(&ep->ep, &req->req);
1834
1835 } else {
1836 if (req->req.complete)
1837 _nbu2ss_ep_done(ep, req, 0);
1838 }
1839
1840 udc->ep0state = EP0_IDLE;
1841
1842 return 0;
1843}
1844
1845/*-------------------------------------------------------------------------*/
1846static inline void _nbu2ss_ep0_int(struct nbu2ss_udc *udc)
1847{
1848 int i;
1849 u32 status;
1850 u32 intr;
1851 int nret = -1;
1852
1853 status = _nbu2ss_readl(&udc->p_regs->EP0_STATUS);
1854 intr = status & EP0_STATUS_RW_BIT;
1855 _nbu2ss_writel(&udc->p_regs->EP0_STATUS, ~(u32)intr);
1856
1857 status &= (SETUP_INT | EP0_IN_INT | EP0_OUT_INT
1858 | STG_END_INT | EP0_OUT_NULL_INT);
1859
1860 if (status == 0) {
93275c80
HM		 1861 dev_info(udc->dev, "%s Not Decode Interrupt\n", __func__);
1862 dev_info(udc->dev, "EP0_STATUS = 0x%08x\n", intr);
33aa8d45
MD		 1863 return;
1864 }
1865
1866 if (udc->gadget.speed == USB_SPEED_UNKNOWN)
1867 udc->gadget.speed = _nbu2ss_get_speed(udc);
1868
1869 for (i = 0; i < EP0_END_XFER; i++) {
1870 switch (udc->ep0state) {
1871 case EP0_IDLE:
1872 if (status & SETUP_INT) {
1873 status = 0;
1874 nret = _nbu2ss_decode_request(udc);
1875 }
1876 break;
1877
1878 case EP0_IN_DATA_PHASE:
1879 if (status & EP0_IN_INT) {
1880 status &= ~EP0_IN_INT;
1881 nret = _nbu2ss_ep0_in_data_stage(udc);
1882 }
1883 break;
1884
1885 case EP0_OUT_DATA_PHASE:
1886 if (status & EP0_OUT_INT) {
1887 status &= ~EP0_OUT_INT;
1888 nret = _nbu2ss_ep0_out_data_stage(udc);
1889 }
1890 break;
1891
1892 case EP0_IN_STATUS_PHASE:
1893 if ((status & STG_END_INT) || (status & SETUP_INT)) {
1894 status &= ~(STG_END_INT | EP0_IN_INT);
1895 nret = _nbu2ss_ep0_status_stage(udc);
1896 }
1897 break;
1898
1899 case EP0_OUT_STATUS_PAHSE:
1900 if ((status & STG_END_INT)
1901 || (status & SETUP_INT)
1902 || (status & EP0_OUT_NULL_INT)) {
1903 status &= ~(STG_END_INT
1904 | EP0_OUT_INT
1905 | EP0_OUT_NULL_INT);
1906
1907 nret = _nbu2ss_ep0_status_stage(udc);
1908 }
1909
1910 break;
1911
1912 default:
1913 status = 0;
1914 break;
1915 }
1916
1917 if (status == 0)
1918 break;
1919 }
1920
1921 if (nret < 0) {
1922 /* Send Stall */
1923 _nbu2ss_set_endpoint_stall(udc, 0, TRUE);
1924 }
1925}
1926
1927/*-------------------------------------------------------------------------*/
1928static void _nbu2ss_ep_done(
1929 struct nbu2ss_ep *ep,
1930 struct nbu2ss_req *req,
1931 int status)
1932{
1933 struct nbu2ss_udc *udc = ep->udc;
1934
1935 list_del_init(&req->queue);
1936
1937 if (status == -ECONNRESET)
1938 _nbu2ss_fifo_flush(udc, ep);
1939
1940 if (likely(req->req.status == -EINPROGRESS))
1941 req->req.status = status;
1942
1943 if (ep->stalled)
1944 _nbu2ss_epn_set_stall(udc, ep);
1945 else {
1946 if (!list_empty(&ep->queue))
1947 _nbu2ss_restert_transfer(ep);
1948 }
1949
1950#ifdef USE_DMA
1951 if ((ep->direct == USB_DIR_OUT) && (ep->epnum > 0) &&
c75955d1 1952 (req->req.dma != 0))
33aa8d45
MD		 1953 _nbu2ss_dma_unmap_single(udc, ep, req, USB_DIR_OUT);
1954#endif
1955
1956 spin_unlock(&udc->lock);
1957 req->req.complete(&ep->ep, &req->req);
1958 spin_lock(&udc->lock);
1959}
1960
1961/*-------------------------------------------------------------------------*/
1962static inline void _nbu2ss_epn_in_int(
1963 struct nbu2ss_udc *udc,
1964 struct nbu2ss_ep *ep,
1965 struct nbu2ss_req *req)
1966{
1967 int result = 0;
1968 u32 status;
1969
f6ef6c09 1970 struct fc_regs *preg = udc->p_regs;
33aa8d45
MD		 1971
1972 if (req->dma_flag)
1973 return; /* DMA is forwarded */
1974
1975 req->req.actual += req->div_len;
1976 req->div_len = 0;
1977
1978 if (req->req.actual != req->req.length) {
1979 /*---------------------------------------------------------*/
1980 /* remainder of data */
1981 result = _nbu2ss_epn_in_transfer(udc, ep, req);
1982
1983 } else {
5cbca957 1984 if (req->zero && ((req->req.actual % ep->ep.maxpacket) == 0)) {
33aa8d45
MD		 1985
1986 status =
abe34174 1987 _nbu2ss_readl(&preg->EP_REGS[ep->epnum - 1].EP_STATUS);
33aa8d45
MD		 1988
1989 if ((status & EPn_IN_FULL) == 0) {
1990 /*-----------------------------------------*/
1991 /* 0 Length Packet */
666e9084 1992 req->zero = false;
33aa8d45
MD		 1993 _nbu2ss_zero_len_pkt(udc, ep->epnum);
1994 }
1995 return;
1996 }
1997 }
1998
1999 if (result <= 0) {
2000 /*---------------------------------------------------------*/
2001 /* Complete */
2002 _nbu2ss_ep_done(ep, req, result);
2003 }
2004}
2005
2006/*-------------------------------------------------------------------------*/
2007static inline void _nbu2ss_epn_out_int(
2008 struct nbu2ss_udc *udc,
2009 struct nbu2ss_ep *ep,
2010 struct nbu2ss_req *req)
2011{
2012 int result;
2013
2014 result = _nbu2ss_epn_out_transfer(udc, ep, req);
2015 if (result <= 0)
2016 _nbu2ss_ep_done(ep, req, result);
33aa8d45
MD		 2017}
2018
2019/*-------------------------------------------------------------------------*/
2020static inline void _nbu2ss_epn_in_dma_int(
2021 struct nbu2ss_udc *udc,
2022 struct nbu2ss_ep *ep,
2023 struct nbu2ss_req *req)
2024{
2025 u32 mpkt;
2026 u32 size;
2027 struct usb_request *preq;
2028
2029 preq = &req->req;
2030
5a602ac4 2031 if (!req->dma_flag)
33aa8d45
MD		 2032 return;
2033
2034 preq->actual += req->div_len;
2035 req->div_len = 0;
2036 req->dma_flag = FALSE;
2037
2038#ifdef USE_DMA
2039 _nbu2ss_dma_unmap_single(udc, ep, req, USB_DIR_IN);
2040#endif
2041
2042 if (preq->actual != preq->length) {
2043 _nbu2ss_epn_in_transfer(udc, ep, req);
2044 } else {
2045 mpkt = ep->ep.maxpacket;
2046 size = preq->actual % mpkt;
2047 if (size > 0) {
2048 if (((preq->actual & 0x03) == 0) && (size < mpkt))
2049 _nbu2ss_ep_in_end(udc, ep->epnum, 0, 0);
2050 } else {
2051 _nbu2ss_epn_in_int(udc, ep, req);
2052 }
2053 }
33aa8d45
MD		 2054}
2055
2056/*-------------------------------------------------------------------------*/
2057static inline void _nbu2ss_epn_out_dma_int(
2058 struct nbu2ss_udc *udc,
2059 struct nbu2ss_ep *ep,
2060 struct nbu2ss_req *req)
2061{
2062 int i;
2063 u32 num;
2064 u32 dmacnt, ep_dmacnt;
2065 u32 mpkt;
f6ef6c09 2066 struct fc_regs *preg = udc->p_regs;
33aa8d45
MD		 2067
2068 num = ep->epnum - 1;
2069
2070 if (req->req.actual == req->req.length) {
5cbca957 2071 if ((req->req.length % ep->ep.maxpacket) && !req->zero) {
33aa8d45
MD		 2072 req->div_len = 0;
2073 req->dma_flag = FALSE;
2074 _nbu2ss_ep_done(ep, req, 0);
2075 return;
2076 }
2077 }
2078
2079 ep_dmacnt = _nbu2ss_readl(&preg->EP_REGS[num].EP_LEN_DCNT)
2080 & EPn_DMACNT;
2081 ep_dmacnt >>= 16;
2082
2083 for (i = 0; i < EPC_PLL_LOCK_COUNT; i++) {
2084 dmacnt = _nbu2ss_readl(&preg->EP_DCR[num].EP_DCR1)
2085 & DCR1_EPn_DMACNT;
2086 dmacnt >>= 16;
2087 if (ep_dmacnt == dmacnt)
2088 break;
2089 }
2090
2091 _nbu2ss_bitclr(&preg->EP_DCR[num].EP_DCR1, DCR1_EPn_REQEN);
2092
2093 if (dmacnt != 0) {
2094 mpkt = ep->ep.maxpacket;
2095 if ((req->div_len % mpkt) == 0)
2096 req->div_len -= mpkt * dmacnt;
2097 }
2098
2099 if ((req->req.actual % ep->ep.maxpacket) > 0) {
2100 if (req->req.actual == req->div_len) {
2101 req->div_len = 0;
2102 req->dma_flag = FALSE;
2103 _nbu2ss_ep_done(ep, req, 0);
2104 return;
2105 }
2106 }
2107
2108 req->req.actual += req->div_len;
2109 req->div_len = 0;
2110 req->dma_flag = FALSE;
2111
2112 _nbu2ss_epn_out_int(udc, ep, req);
2113}
2114
2115/*-------------------------------------------------------------------------*/
2116static inline void _nbu2ss_epn_int(struct nbu2ss_udc *udc, u32 epnum)
2117{
2118 u32 num;
2119 u32 status;
2120
2121 struct nbu2ss_req *req;
2122 struct nbu2ss_ep *ep = &udc->ep[epnum];
2123
2124 num = epnum - 1;
2125
2126 /* Interrupt Status */
2127 status = _nbu2ss_readl(&udc->p_regs->EP_REGS[num].EP_STATUS);
2128
2129 /* Interrupt Clear */
2130 _nbu2ss_writel(&udc->p_regs->EP_REGS[num].EP_STATUS, ~(u32)status);
2131
e59ac747 2132 req = list_first_entry_or_null(&ep->queue, struct nbu2ss_req, queue);
706eb8cf 2133 if (!req) {
f02935c5 2134 /* pr_warn("=== %s(%d) req == NULL\n", __func__, epnum); */
33aa8d45
MD		 2135 return;
2136 }
2137
2138 if (status & EPn_OUT_END_INT) {
2139 status &= ~EPn_OUT_INT;
2140 _nbu2ss_epn_out_dma_int(udc, ep, req);
2141 }
2142
2143 if (status & EPn_OUT_INT)
2144 _nbu2ss_epn_out_int(udc, ep, req);
2145
2146 if (status & EPn_IN_END_INT) {
2147 status &= ~EPn_IN_INT;
2148 _nbu2ss_epn_in_dma_int(udc, ep, req);
2149 }
2150
2151 if (status & EPn_IN_INT)
2152 _nbu2ss_epn_in_int(udc, ep, req);
2153}
2154
2155/*-------------------------------------------------------------------------*/
2156static inline void _nbu2ss_ep_int(struct nbu2ss_udc *udc, u32 epnum)
2157{
2158 if (epnum == 0)
2159 _nbu2ss_ep0_int(udc);
2160 else
2161 _nbu2ss_epn_int(udc, epnum);
2162}
2163
2164/*-------------------------------------------------------------------------*/
2165static void _nbu2ss_ep0_enable(struct nbu2ss_udc *udc)
2166{
2167 _nbu2ss_bitset(&udc->p_regs->EP0_CONTROL, (EP0_AUTO | EP0_BCLR));
2168 _nbu2ss_writel(&udc->p_regs->EP0_INT_ENA, EP0_INT_EN_BIT);
33aa8d45
MD		 2169}
2170
33aa8d45
MD		 2171/*-------------------------------------------------------------------------*/
2172static int _nbu2ss_nuke(struct nbu2ss_udc *udc,
2173 struct nbu2ss_ep *ep,
2174 int status)
2175{
2176 struct nbu2ss_req *req;
2177
2178 /* Endpoint Disable */
2179 _nbu2ss_epn_exit(udc, ep);
2180
2181 /* DMA Disable */
2182 _nbu2ss_ep_dma_exit(udc, ep);
2183
2184 if (list_empty(&ep->queue))
2185 return 0;
2186
2187 /* called with irqs blocked */
ca3d253e 2188 list_for_each_entry(req, &ep->queue, queue) {
33aa8d45
MD		 2189 _nbu2ss_ep_done(ep, req, status);
2190 }
2191
2192 return 0;
2193}
2194
2195/*-------------------------------------------------------------------------*/
2196static void _nbu2ss_quiesce(struct nbu2ss_udc *udc)
2197{
2198 struct nbu2ss_ep *ep;
2199
2200 udc->gadget.speed = USB_SPEED_UNKNOWN;
2201
2202 _nbu2ss_nuke(udc, &udc->ep[0], -ESHUTDOWN);
2203
2204 /* Endpoint n */
2205 list_for_each_entry(ep, &udc->gadget.ep_list, ep.ep_list) {
2206 _nbu2ss_nuke(udc, ep, -ESHUTDOWN);
2207 }
2208}
2209
2210/*-------------------------------------------------------------------------*/
2211static int _nbu2ss_pullup(struct nbu2ss_udc *udc, int is_on)
2212{
2213 u32 reg_dt;
2214
33aa8d45
MD		 2215 if (udc->vbus_active == 0)
2216 return -ESHUTDOWN;
2217
2218 if (is_on) {
2219 /* D+ Pullup */
33aa8d45
MD		 2220 if (udc->driver) {
2221 reg_dt = (_nbu2ss_readl(&udc->p_regs->USB_CONTROL)
2222 | PUE2) & ~(u32)CONNECTB;
2223
2224 _nbu2ss_writel(&udc->p_regs->USB_CONTROL, reg_dt);
2225 }
2226
2227 } else {
2228 /* D+ Pulldown */
33aa8d45
MD		 2229 reg_dt = (_nbu2ss_readl(&udc->p_regs->USB_CONTROL) | CONNECTB)
2230 & ~(u32)PUE2;
2231
2232 _nbu2ss_writel(&udc->p_regs->USB_CONTROL, reg_dt);
2233 udc->gadget.speed = USB_SPEED_UNKNOWN;
2234 }
2235
2236 return 0;
2237}
2238
2239/*-------------------------------------------------------------------------*/
2240static void _nbu2ss_fifo_flush(struct nbu2ss_udc *udc, struct nbu2ss_ep *ep)
2241{
f6ef6c09 2242 struct fc_regs *p = udc->p_regs;
33aa8d45
MD		 2243
2244 if (udc->vbus_active == 0)
2245 return;
2246
2247 if (ep->epnum == 0) {
2248 /* EP0 */
2249 _nbu2ss_bitset(&p->EP0_CONTROL, EP0_BCLR);
2250
2251 } else {
2252 /* EPn */
2253 _nbu2ss_ep_dma_abort(udc, ep);
2254 _nbu2ss_bitset(&p->EP_REGS[ep->epnum - 1].EP_CONTROL, EPn_BCLR);
2255 }
2256}
2257
2258/*-------------------------------------------------------------------------*/
2259static int _nbu2ss_enable_controller(struct nbu2ss_udc *udc)
2260{
2261 int waitcnt = 0;
2262
2263 if (udc->udc_enabled)
2264 return 0;
2265
8e02a3fd 2266 /* Reset */
33aa8d45
MD		 2267 _nbu2ss_bitset(&udc->p_regs->EPCTR, (DIRPD | EPC_RST));
2268 udelay(EPC_RST_DISABLE_TIME); /* 1us wait */
2269
2270 _nbu2ss_bitclr(&udc->p_regs->EPCTR, DIRPD);
2271 mdelay(EPC_DIRPD_DISABLE_TIME); /* 1ms wait */
2272
2273 _nbu2ss_bitclr(&udc->p_regs->EPCTR, EPC_RST);
2274
2275 _nbu2ss_writel(&udc->p_regs->AHBSCTR, WAIT_MODE);
2276
33aa8d45 2277 _nbu2ss_writel(&udc->p_regs->AHBMCTR,
c75955d1 2278 HBUSREQ_MODE | HTRANS_MODE | WBURST_TYPE);
33aa8d45
MD		 2279
2280 while (!(_nbu2ss_readl(&udc->p_regs->EPCTR) & PLL_LOCK)) {
2281 waitcnt++;
2282 udelay(1); /* 1us wait */
2283 if (waitcnt == EPC_PLL_LOCK_COUNT) {
88689279 2284 dev_err(udc->dev, "*** Reset Cancel failed\n");
33aa8d45
MD		 2285 return -EINVAL;
2286 }
3e2bb64d 2287 }
33aa8d45 2288
33aa8d45
MD		 2289 _nbu2ss_bitset(&udc->p_regs->UTMI_CHARACTER_1, USB_SQUSET);
2290
2291 _nbu2ss_bitset(&udc->p_regs->USB_CONTROL, (INT_SEL | SOF_RCV));
2292
2293 /* EP0 */
2294 _nbu2ss_ep0_enable(udc);
2295
2296 /* USB Interrupt Enable */
2297 _nbu2ss_bitset(&udc->p_regs->USB_INT_ENA, USB_INT_EN_BIT);
2298
2299 udc->udc_enabled = TRUE;
2300
2301 return 0;
2302}
2303
33aa8d45
MD		 2304/*-------------------------------------------------------------------------*/
2305static void _nbu2ss_reset_controller(struct nbu2ss_udc *udc)
2306{
2307 _nbu2ss_bitset(&udc->p_regs->EPCTR, EPC_RST);
2308 _nbu2ss_bitclr(&udc->p_regs->EPCTR, EPC_RST);
2309}
2310
2311/*-------------------------------------------------------------------------*/
2312static void _nbu2ss_disable_controller(struct nbu2ss_udc *udc)
2313{
2314 if (udc->udc_enabled) {
2315 udc->udc_enabled = FALSE;
2316 _nbu2ss_reset_controller(udc);
2317 _nbu2ss_bitset(&udc->p_regs->EPCTR, (DIRPD | EPC_RST));
2318 }
33aa8d45
MD		 2319}
2320
2321/*-------------------------------------------------------------------------*/
2322static inline void _nbu2ss_check_vbus(struct nbu2ss_udc *udc)
2323{
2324 int nret;
2325 u32 reg_dt;
2326
2327 /* chattering */
2328 mdelay(VBUS_CHATTERING_MDELAY); /* wait (ms) */
2329
2330 /* VBUS ON Check*/
2331 reg_dt = gpio_get_value(VBUS_VALUE);
2332 if (reg_dt == 0) {
2333
2334 udc->linux_suspended = 0;
2335
2336 _nbu2ss_reset_controller(udc);
93275c80 2337 dev_info(udc->dev, " ----- VBUS OFF\n");
33aa8d45
MD		 2338
2339 if (udc->vbus_active == 1) {
2340 /* VBUS OFF */
2341 udc->vbus_active = 0;
2342 if (udc->usb_suspended) {
2343 udc->usb_suspended = 0;
2344 /* _nbu2ss_reset_controller(udc); */
2345 }
2346 udc->devstate = USB_STATE_NOTATTACHED;
2347
2348 _nbu2ss_quiesce(udc);
2349 if (udc->driver) {
2350 spin_unlock(&udc->lock);
2351 udc->driver->disconnect(&udc->gadget);
2352 spin_lock(&udc->lock);
2353 }
2354
2355 _nbu2ss_disable_controller(udc);
2356 }
2357 } else {
2358 mdelay(5); /* wait (5ms) */
2359 reg_dt = gpio_get_value(VBUS_VALUE);
2360 if (reg_dt == 0)
2361 return;
2362
93275c80 2363 dev_info(udc->dev, " ----- VBUS ON\n");
33aa8d45
MD		 2364
2365 if (udc->linux_suspended)
2366 return;
2367
2368 if (udc->vbus_active == 0) {
2369 /* VBUS ON */
2370 udc->vbus_active = 1;
2371 udc->devstate = USB_STATE_POWERED;
2372
2373 nret = _nbu2ss_enable_controller(udc);
2374 if (nret < 0) {
2375 _nbu2ss_disable_controller(udc);
2376 udc->vbus_active = 0;
2377 return;
2378 }
2379
2380 _nbu2ss_pullup(udc, 1);
2381
2382#ifdef UDC_DEBUG_DUMP
2383 _nbu2ss_dump_register(udc);
2384#endif /* UDC_DEBUG_DUMP */
2385
2386 } else {
2387 if (udc->devstate == USB_STATE_POWERED)
2388 _nbu2ss_pullup(udc, 1);
2389 }
2390 }
33aa8d45
MD		 2391}
2392
2393/*-------------------------------------------------------------------------*/
2394static inline void _nbu2ss_int_bus_reset(struct nbu2ss_udc *udc)
2395{
2396 udc->devstate = USB_STATE_DEFAULT;
2397 udc->remote_wakeup = 0;
2398
2399 _nbu2ss_quiesce(udc);
2400
2401 udc->ep0state = EP0_IDLE;
2402}
2403
2404/*-------------------------------------------------------------------------*/
2405static inline void _nbu2ss_int_usb_resume(struct nbu2ss_udc *udc)
2406{
2407 if (udc->usb_suspended == 1) {
2408 udc->usb_suspended = 0;
2409 if (udc->driver && udc->driver->resume) {
2410 spin_unlock(&udc->lock);
2411 udc->driver->resume(&udc->gadget);
2412 spin_lock(&udc->lock);
2413 }
2414 }
2415}
2416
2417/*-------------------------------------------------------------------------*/
2418static inline void _nbu2ss_int_usb_suspend(struct nbu2ss_udc *udc)
2419{
2420 u32 reg_dt;
2421
2422 if (udc->usb_suspended == 0) {
2423 reg_dt = gpio_get_value(VBUS_VALUE);
2424
2425 if (reg_dt == 0)
2426 return;
2427
2428 udc->usb_suspended = 1;
2429 if (udc->driver && udc->driver->suspend) {
2430 spin_unlock(&udc->lock);
2431 udc->driver->suspend(&udc->gadget);
2432 spin_lock(&udc->lock);
2433 }
2434
2435 _nbu2ss_bitset(&udc->p_regs->USB_CONTROL, SUSPEND);
2436 }
2437}
2438
2439/*-------------------------------------------------------------------------*/
2440/* VBUS (GPIO153) Interrupt */
2441static irqreturn_t _nbu2ss_vbus_irq(int irq, void *_udc)
2442{
2443 struct nbu2ss_udc *udc = (struct nbu2ss_udc *)_udc;
2444
2445 spin_lock(&udc->lock);
2446 _nbu2ss_check_vbus(udc);
2447 spin_unlock(&udc->lock);
2448
2449 return IRQ_HANDLED;
2450}
2451
2452/*-------------------------------------------------------------------------*/
2453/* Interrupt (udc) */
2454static irqreturn_t _nbu2ss_udc_irq(int irq, void *_udc)
2455{
2456 u8 suspend_flag = 0;
2457 u32 status;
2458 u32 epnum, int_bit;
2459
2460 struct nbu2ss_udc *udc = (struct nbu2ss_udc *)_udc;
f6ef6c09 2461 struct fc_regs *preg = udc->p_regs;
33aa8d45
MD		 2462
2463 if (gpio_get_value(VBUS_VALUE) == 0) {
2464 _nbu2ss_writel(&preg->USB_INT_STA, ~USB_INT_STA_RW);
2465 _nbu2ss_writel(&preg->USB_INT_ENA, 0);
2466 return IRQ_HANDLED;
2467 }
2468
2469 spin_lock(&udc->lock);
2470
2471 for (;;) {
2472 if (gpio_get_value(VBUS_VALUE) == 0) {
2473 _nbu2ss_writel(&preg->USB_INT_STA, ~USB_INT_STA_RW);
2474 _nbu2ss_writel(&preg->USB_INT_ENA, 0);
2475 status = 0;
2476 } else
2477 status = _nbu2ss_readl(&preg->USB_INT_STA);
2478
2479 if (status == 0)
2480 break;
2481
2482 _nbu2ss_writel(&preg->USB_INT_STA, ~(status & USB_INT_STA_RW));
2483
2484 if (status & USB_RST_INT) {
2485 /* USB Reset */
2486 _nbu2ss_int_bus_reset(udc);
2487 }
2488
2489 if (status & RSUM_INT) {
2490 /* Resume */
2491 _nbu2ss_int_usb_resume(udc);
2492 }
2493
2494 if (status & SPND_INT) {
2495 /* Suspend */
2496 suspend_flag = 1;
2497 }
2498
2499 if (status & EPn_INT) {
2500 /* EP INT */
2501 int_bit = status >> 8;
2502
2503 for (epnum = 0; epnum < NUM_ENDPOINTS; epnum++) {
2504
2505 if (0x01 & int_bit)
2506 _nbu2ss_ep_int(udc, epnum);
2507
2508 int_bit >>= 1;
2509
2510 if (int_bit == 0)
2511 break;
2512 }
2513 }
2514 }
2515
2516 if (suspend_flag)
2517 _nbu2ss_int_usb_suspend(udc);
2518
2519 spin_unlock(&udc->lock);
2520
2521 return IRQ_HANDLED;
2522}
2523
2524/*-------------------------------------------------------------------------*/
2525/* usb_ep_ops */
2526static int nbu2ss_ep_enable(
2527 struct usb_ep *_ep,
2528 const struct usb_endpoint_descriptor *desc)
2529{
2530 u8 ep_type;
2531 unsigned long flags;
2532
2533 struct nbu2ss_ep *ep;
2534 struct nbu2ss_udc *udc;
2535
706eb8cf 2536 if ((!_ep) || (!desc)) {
88689279 2537 pr_err(" *** %s, bad param\n", __func__);
33aa8d45
MD		 2538 return -EINVAL;
2539 }
2540
2541 ep = container_of(_ep, struct nbu2ss_ep, ep);
706eb8cf 2542 if ((!ep) || (!ep->udc)) {
88689279 2543 pr_err(" *** %s, ep == NULL !!\n", __func__);
33aa8d45
MD		 2544 return -EINVAL;
2545 }
2546
3f3efca9 2547 ep_type = usb_endpoint_type(desc);
33aa8d45
MD		 2548 if ((ep_type == USB_ENDPOINT_XFER_CONTROL)
2549 || (ep_type == USB_ENDPOINT_XFER_ISOC)) {
2550
88689279 2551 pr_err(" *** %s, bat bmAttributes\n", __func__);
33aa8d45
MD		 2552 return -EINVAL;
2553 }
2554
2555 udc = ep->udc;
2556 if (udc->vbus_active == 0)
2557 return -ESHUTDOWN;
2558
706eb8cf 2559 if ((!udc->driver)
33aa8d45
MD		 2560 || (udc->gadget.speed == USB_SPEED_UNKNOWN)) {
2561
88689279 2562 dev_err(ep->udc->dev, " *** %s, udc !!\n", __func__);
33aa8d45
MD		 2563 return -ESHUTDOWN;
2564 }
2565
2566 spin_lock_irqsave(&udc->lock, flags);
2567
2568 ep->desc = desc;
3f3efca9 2569 ep->epnum = usb_endpoint_num(desc);
33aa8d45
MD		 2570 ep->direct = desc->bEndpointAddress & USB_ENDPOINT_DIR_MASK;
2571 ep->ep_type = ep_type;
2572 ep->wedged = 0;
2573 ep->halted = FALSE;
2574 ep->stalled = FALSE;
2575
2576 ep->ep.maxpacket = le16_to_cpu(desc->wMaxPacketSize);
2577
2578 /* DMA setting */
2579 _nbu2ss_ep_dma_init(udc, ep);
2580
2581 /* Endpoint setting */
2582 _nbu2ss_ep_init(udc, ep);
2583
2584 spin_unlock_irqrestore(&udc->lock, flags);
2585
2586 return 0;
2587}
2588
2589/*-------------------------------------------------------------------------*/
2590static int nbu2ss_ep_disable(struct usb_ep *_ep)
2591{
2592 struct nbu2ss_ep *ep;
2593 struct nbu2ss_udc *udc;
2594 unsigned long flags;
2595
706eb8cf 2596 if (!_ep) {
88689279 2597 pr_err(" *** %s, bad param\n", __func__);
33aa8d45
MD		 2598 return -EINVAL;
2599 }
2600
2601 ep = container_of(_ep, struct nbu2ss_ep, ep);
706eb8cf 2602 if ((!ep) || (!ep->udc)) {
88689279 2603 pr_err("udc: *** %s, ep == NULL !!\n", __func__);
33aa8d45
MD		 2604 return -EINVAL;
2605 }
2606
2607 udc = ep->udc;
2608 if (udc->vbus_active == 0)
2609 return -ESHUTDOWN;
2610
2611 spin_lock_irqsave(&udc->lock, flags);
2612 _nbu2ss_nuke(udc, ep, -EINPROGRESS); /* dequeue request */
2613 spin_unlock_irqrestore(&udc->lock, flags);
2614
2615 return 0;
2616}
2617
2618/*-------------------------------------------------------------------------*/
2619static struct usb_request *nbu2ss_ep_alloc_request(
2620 struct usb_ep *ep,
2621 gfp_t gfp_flags)
2622{
2623 struct nbu2ss_req *req;
2624
2625 req = kzalloc(sizeof(*req), gfp_flags);
2626 if (!req)
5a20df72 2627 return NULL;
33aa8d45
MD		 2628
2629#ifdef USE_DMA
2630 req->req.dma = DMA_ADDR_INVALID;
2631#endif
2632 INIT_LIST_HEAD(&req->queue);
2633
2634 return &req->req;
2635}
2636
2637/*-------------------------------------------------------------------------*/
2638static void nbu2ss_ep_free_request(
2639 struct usb_ep *_ep,
2640 struct usb_request *_req)
2641{
2642 struct nbu2ss_req *req;
2643
706eb8cf 2644 if (_req) {
33aa8d45
MD		 2645 req = container_of(_req, struct nbu2ss_req, req);
2646
a5a89d7a 2647 kfree(req);
33aa8d45
MD		 2648 }
2649}
2650
2651/*-------------------------------------------------------------------------*/
2652static int nbu2ss_ep_queue(
2653 struct usb_ep *_ep,
2654 struct usb_request *_req,
2655 gfp_t gfp_flags)
2656{
2657 struct nbu2ss_req *req;
2658 struct nbu2ss_ep *ep;
2659 struct nbu2ss_udc *udc;
2660 unsigned long flags;
2661 bool bflag;
2662 int result = -EINVAL;
2663
2664 /* catch various bogus parameters */
706eb8cf
RTD		 2665 if ((!_ep) || (!_req)) {
2666 if (!_ep)
88689279 2667 pr_err("udc: %s --- _ep == NULL\n", __func__);
33aa8d45 2668
706eb8cf 2669 if (!_req)
88689279 2670 pr_err("udc: %s --- _req == NULL\n", __func__);
33aa8d45
MD		 2671
2672 return -EINVAL;
2673 }
2674
2675 req = container_of(_req, struct nbu2ss_req, req);
2676 if (unlikely
2677 (!_req->complete || !_req->buf
2678 || !list_empty(&req->queue))) {
2679
2680 if (!_req->complete)
88689279 2681 pr_err("udc: %s --- !_req->complete\n", __func__);
33aa8d45
MD		 2682
2683 if (!_req->buf)
88689279 2684 pr_err("udc:%s --- !_req->buf\n", __func__);
33aa8d45
MD		 2685
2686 if (!list_empty(&req->queue))
88689279 2687 pr_err("%s --- !list_empty(&req->queue)\n", __func__);
33aa8d45
MD		 2688
2689 return -EINVAL;
2690 }
2691
2692 ep = container_of(_ep, struct nbu2ss_ep, ep);
2693 udc = ep->udc;
2694
33aa8d45 2695 if (udc->vbus_active == 0) {
93275c80 2696 dev_info(udc->dev, "Can't ep_queue (VBUS OFF)\n");
33aa8d45
MD		 2697 return -ESHUTDOWN;
2698 }
2699
2700 if (unlikely(!udc->driver)) {
88689279 2701 dev_err(udc->dev, "%s, bogus device state %p\n", __func__,
c75955d1 2702 udc->driver);
33aa8d45
MD		 2703 return -ESHUTDOWN;
2704 }
2705
2706 spin_lock_irqsave(&udc->lock, flags);
2707
2708#ifdef USE_DMA
e7cfb390 2709 if ((uintptr_t)req->req.buf & 0x3)
33aa8d45
MD		 2710 req->unaligned = TRUE;
2711 else
2712 req->unaligned = FALSE;
2713
2714 if (req->unaligned) {
706eb8cf 2715 if (!ep->virt_buf)
33aa8d45
MD		 2716 ep->virt_buf = (u8 *)dma_alloc_coherent(
2717 NULL, PAGE_SIZE,
4a0721bf 2718 &ep->phys_buf, GFP_ATOMIC | GFP_DMA);
33aa8d45
MD		 2719 if (ep->epnum > 0) {
2720 if (ep->direct == USB_DIR_IN)
2721 memcpy(ep->virt_buf, req->req.buf,
c75955d1 2722 req->req.length);
33aa8d45
MD		 2723 }
2724 }
2725
2726 if ((ep->epnum > 0) && (ep->direct == USB_DIR_OUT) &&
c75955d1 2727 (req->req.dma != 0))
33aa8d45
MD		 2728 _nbu2ss_dma_map_single(udc, ep, req, USB_DIR_OUT);
2729#endif
2730
2731 _req->status = -EINPROGRESS;
2732 _req->actual = 0;
2733
2734 bflag = list_empty(&ep->queue);
2735 list_add_tail(&req->queue, &ep->queue);
2736
5a602ac4 2737 if (bflag && !ep->stalled) {
33aa8d45
MD		 2738
2739 result = _nbu2ss_start_transfer(udc, ep, req, FALSE);
2740 if (result < 0) {
88689279 2741 dev_err(udc->dev, " *** %s, result = %d\n", __func__,
c75955d1 2742 result);
33aa8d45
MD		 2743 list_del(&req->queue);
2744 } else if ((ep->epnum > 0) && (ep->direct == USB_DIR_OUT)) {
2745#ifdef USE_DMA
2746 if (req->req.length < 4 &&
c75955d1 2747 req->req.length == req->req.actual)
33aa8d45
MD		 2748#else
2749 if (req->req.length == req->req.actual)
2750#endif
2751 _nbu2ss_ep_done(ep, req, result);
2752 }
2753 }
2754
2755 spin_unlock_irqrestore(&udc->lock, flags);
2756
2757 return 0;
2758}
2759
2760/*-------------------------------------------------------------------------*/
2761static int nbu2ss_ep_dequeue(
2762 struct usb_ep *_ep,
2763 struct usb_request *_req)
2764{
2765 struct nbu2ss_req *req;
2766 struct nbu2ss_ep *ep;
2767 struct nbu2ss_udc *udc;
2768 unsigned long flags;
2769
33aa8d45 2770 /* catch various bogus parameters */
706eb8cf 2771 if ((!_ep) || (!_req)) {
88689279 2772 /* pr_err("%s, bad param(1)\n", __func__); */
33aa8d45
MD		 2773 return -EINVAL;
2774 }
2775
2776 ep = container_of(_ep, struct nbu2ss_ep, ep);
2777 if (!ep) {
88689279 2778 pr_err("%s, ep == NULL !!\n", __func__);
33aa8d45
MD		 2779 return -EINVAL;
2780 }
2781
2782 udc = ep->udc;
706eb8cf 2783 if (!udc)
33aa8d45
MD		 2784 return -EINVAL;
2785
2786 spin_lock_irqsave(&udc->lock, flags);
2787
2788 /* make sure it's actually queued on this endpoint */
2789 list_for_each_entry(req, &ep->queue, queue) {
2790 if (&req->req == _req)
2791 break;
2792 }
2793 if (&req->req != _req) {
2794 spin_unlock_irqrestore(&udc->lock, flags);
2795 pr_debug("%s no queue(EINVAL)\n", __func__);
2796 return -EINVAL;
2797 }
2798
2799 _nbu2ss_ep_done(ep, req, -ECONNRESET);
2800
2801 spin_unlock_irqrestore(&udc->lock, flags);
2802
2803 return 0;
2804}
2805
2806/*-------------------------------------------------------------------------*/
2807static int nbu2ss_ep_set_halt(struct usb_ep *_ep, int value)
2808{
2809 u8 ep_adrs;
2810 unsigned long flags;
2811
2812 struct nbu2ss_ep *ep;
2813 struct nbu2ss_udc *udc;
2814
33aa8d45 2815 if (!_ep) {
88689279 2816 pr_err("%s, bad param\n", __func__);
33aa8d45
MD		 2817 return -EINVAL;
2818 }
2819
2820 ep = container_of(_ep, struct nbu2ss_ep, ep);
2821 if (!ep) {
88689279 2822 pr_err("%s, bad ep\n", __func__);
33aa8d45
MD		 2823 return -EINVAL;
2824 }
2825
2826 udc = ep->udc;
2827 if (!udc) {
88689279 2828 dev_err(ep->udc->dev, " *** %s, bad udc\n", __func__);
33aa8d45
MD		 2829 return -EINVAL;
2830 }
2831
2832 spin_lock_irqsave(&udc->lock, flags);
2833
2834 ep_adrs = ep->epnum | ep->direct;
2835 if (value == 0) {
2836 _nbu2ss_set_endpoint_stall(udc, ep_adrs, value);
2837 ep->stalled = FALSE;
2838 } else {
2839 if (list_empty(&ep->queue))
2840 _nbu2ss_epn_set_stall(udc, ep);
2841 else
2842 ep->stalled = TRUE;
2843 }
2844
2845 if (value == 0)
2846 ep->wedged = 0;
2847
2848 spin_unlock_irqrestore(&udc->lock, flags);
2849
2850 return 0;
2851}
2852
2853static int nbu2ss_ep_set_wedge(struct usb_ep *_ep)
2854{
2855 return nbu2ss_ep_set_halt(_ep, 1);
2856}
2857
2858/*-------------------------------------------------------------------------*/
2859static int nbu2ss_ep_fifo_status(struct usb_ep *_ep)
2860{
2861 u32 data;
2862 struct nbu2ss_ep *ep;
2863 struct nbu2ss_udc *udc;
2864 unsigned long flags;
f6ef6c09 2865 struct fc_regs *preg;
33aa8d45 2866
33aa8d45 2867 if (!_ep) {
88689279 2868 pr_err("%s, bad param\n", __func__);
33aa8d45
MD		 2869 return -EINVAL;
2870 }
2871
2872 ep = container_of(_ep, struct nbu2ss_ep, ep);
2873 if (!ep) {
88689279 2874 pr_err("%s, bad ep\n", __func__);
33aa8d45
MD		 2875 return -EINVAL;
2876 }
2877
2878 udc = ep->udc;
2879 if (!udc) {
88689279 2880 dev_err(ep->udc->dev, "%s, bad udc\n", __func__);
33aa8d45
MD		 2881 return -EINVAL;
2882 }
2883
2884 preg = udc->p_regs;
2885
2886 data = gpio_get_value(VBUS_VALUE);
2887 if (data == 0)
2888 return -EINVAL;
2889
2890 spin_lock_irqsave(&udc->lock, flags);
2891
2892 if (ep->epnum == 0) {
2893 data = _nbu2ss_readl(&preg->EP0_LENGTH) & EP0_LDATA;
2894
2895 } else {
abe34174 2896 data = _nbu2ss_readl(&preg->EP_REGS[ep->epnum - 1].EP_LEN_DCNT)
33aa8d45
MD		 2897 & EPn_LDATA;
2898 }
2899
2900 spin_unlock_irqrestore(&udc->lock, flags);
2901
2902 return 0;
2903}
2904
2905/*-------------------------------------------------------------------------*/
2906static void nbu2ss_ep_fifo_flush(struct usb_ep *_ep)
2907{
2908 u32 data;
2909 struct nbu2ss_ep *ep;
2910 struct nbu2ss_udc *udc;
2911 unsigned long flags;
2912
33aa8d45 2913 if (!_ep) {
88689279 2914 pr_err("udc: %s, bad param\n", __func__);
33aa8d45
MD		 2915 return;
2916 }
2917
2918 ep = container_of(_ep, struct nbu2ss_ep, ep);
bd7de5ce 2919 if (!ep) {
88689279 2920 pr_err("udc: %s, bad ep\n", __func__);
33aa8d45
MD		 2921 return;
2922 }
2923
2924 udc = ep->udc;
2925 if (!udc) {
88689279 2926 dev_err(ep->udc->dev, "%s, bad udc\n", __func__);
33aa8d45
MD		 2927 return;
2928 }
2929
2930 data = gpio_get_value(VBUS_VALUE);
2931 if (data == 0)
2932 return;
2933
2934 spin_lock_irqsave(&udc->lock, flags);
2935 _nbu2ss_fifo_flush(udc, ep);
2936 spin_unlock_irqrestore(&udc->lock, flags);
2937}
2938
2939/*-------------------------------------------------------------------------*/
2940static struct usb_ep_ops nbu2ss_ep_ops = {
2941 .enable = nbu2ss_ep_enable,
2942 .disable = nbu2ss_ep_disable,
2943
2944 .alloc_request = nbu2ss_ep_alloc_request,
2945 .free_request = nbu2ss_ep_free_request,
2946
2947 .queue = nbu2ss_ep_queue,
2948 .dequeue = nbu2ss_ep_dequeue,
2949
2950 .set_halt = nbu2ss_ep_set_halt,
2951 .set_wedge = nbu2ss_ep_set_wedge,
2952
2953 .fifo_status = nbu2ss_ep_fifo_status,
2954 .fifo_flush = nbu2ss_ep_fifo_flush,
2955};
2956
33aa8d45
MD		 2957/*-------------------------------------------------------------------------*/
2958/* usb_gadget_ops */
2959
2960/*-------------------------------------------------------------------------*/
2961static int nbu2ss_gad_get_frame(struct usb_gadget *pgadget)
2962{
2963 u32 data;
2964 struct nbu2ss_udc *udc;
2965
706eb8cf 2966 if (!pgadget) {
88689279 2967 pr_err("udc: %s, bad param\n", __func__);
33aa8d45
MD		 2968 return -EINVAL;
2969 }
2970
2971 udc = container_of(pgadget, struct nbu2ss_udc, gadget);
706eb8cf 2972 if (!udc) {
88689279 2973 dev_err(&pgadget->dev, "%s, udc == NULL\n", __func__);
33aa8d45
MD		 2974 return -EINVAL;
2975 }
2976
2977 data = gpio_get_value(VBUS_VALUE);
2978 if (data == 0)
2979 return -EINVAL;
2980
2981 data = _nbu2ss_readl(&udc->p_regs->USB_ADDRESS) & FRAME;
2982
2983 return data;
2984}
2985
2986/*-------------------------------------------------------------------------*/
2987static int nbu2ss_gad_wakeup(struct usb_gadget *pgadget)
2988{
2989 int i;
2990 u32 data;
2991
2992 struct nbu2ss_udc *udc;
2993
706eb8cf 2994 if (!pgadget) {
88689279 2995 pr_err("%s, bad param\n", __func__);
33aa8d45
MD		 2996 return -EINVAL;
2997 }
2998
2999 udc = container_of(pgadget, struct nbu2ss_udc, gadget);
706eb8cf 3000 if (!udc) {
88689279 3001 dev_err(&pgadget->dev, "%s, udc == NULL\n", __func__);
33aa8d45
MD		 3002 return -EINVAL;
3003 }
3004
3005 data = gpio_get_value(VBUS_VALUE);
3006 if (data == 0) {
93275c80 3007 dev_warn(&pgadget->dev, "VBUS LEVEL = %d\n", data);
33aa8d45
MD		 3008 return -EINVAL;
3009 }
3010
3011 _nbu2ss_bitset(&udc->p_regs->EPCTR, PLL_RESUME);
3012
3013 for (i = 0; i < EPC_PLL_LOCK_COUNT; i++) {
3014 data = _nbu2ss_readl(&udc->p_regs->EPCTR);
3015
3016 if (data & PLL_LOCK)
3017 break;
3018 }
3019
3020 _nbu2ss_bitclr(&udc->p_regs->EPCTR, PLL_RESUME);
3021
3022 return 0;
3023}
3024
3025/*-------------------------------------------------------------------------*/
3026static int nbu2ss_gad_set_selfpowered(struct usb_gadget *pgadget,
c75955d1 3027 int is_selfpowered)
33aa8d45 3028{
1fa2df0c 3029 struct nbu2ss_udc *udc;
33aa8d45
MD		 3030 unsigned long flags;
3031
706eb8cf 3032 if (!pgadget) {
88689279 3033 pr_err("%s, bad param\n", __func__);
33aa8d45
MD		 3034 return -EINVAL;
3035 }
3036
1fa2df0c
PC		 3037 udc = container_of(pgadget, struct nbu2ss_udc, gadget);
3038
33aa8d45 3039 spin_lock_irqsave(&udc->lock, flags);
9239d88f 3040 pgadget->is_selfpowered = (is_selfpowered != 0);
33aa8d45
MD		 3041 spin_unlock_irqrestore(&udc->lock, flags);
3042
3043 return 0;
3044}
3045
3046/*-------------------------------------------------------------------------*/
3047static int nbu2ss_gad_vbus_session(struct usb_gadget *pgadget, int is_active)
3048{
33aa8d45
MD		 3049 return 0;
3050}
3051
3052/*-------------------------------------------------------------------------*/
ffc83a79 3053static int nbu2ss_gad_vbus_draw(struct usb_gadget *pgadget, unsigned int mA)
33aa8d45
MD		 3054{
3055 struct nbu2ss_udc *udc;
3056 unsigned long flags;
3057
706eb8cf 3058 if (!pgadget) {
88689279 3059 pr_err("%s, bad param\n", __func__);
33aa8d45
MD		 3060 return -EINVAL;
3061 }
3062
3063 udc = container_of(pgadget, struct nbu2ss_udc, gadget);
3064
3065 spin_lock_irqsave(&udc->lock, flags);
3066 udc->mA = mA;
3067 spin_unlock_irqrestore(&udc->lock, flags);
3068
3069 return 0;
3070}
3071
3072/*-------------------------------------------------------------------------*/
3073static int nbu2ss_gad_pullup(struct usb_gadget *pgadget, int is_on)
3074{
3075 struct nbu2ss_udc *udc;
3076 unsigned long flags;
3077
706eb8cf 3078 if (!pgadget) {
88689279 3079 pr_err("%s, bad param\n", __func__);
33aa8d45
MD		 3080 return -EINVAL;
3081 }
3082
3083 udc = container_of(pgadget, struct nbu2ss_udc, gadget);
3084
706eb8cf 3085 if (!udc->driver) {
f02935c5 3086 pr_warn("%s, Not Regist Driver\n", __func__);
33aa8d45
MD		 3087 return -EINVAL;
3088 }
3089
3090 if (udc->vbus_active == 0)
3091 return -ESHUTDOWN;
3092
3093 spin_lock_irqsave(&udc->lock, flags);
3094 _nbu2ss_pullup(udc, is_on);
3095 spin_unlock_irqrestore(&udc->lock, flags);
3096
3097 return 0;
3098}
3099
3100/*-------------------------------------------------------------------------*/
3101static int nbu2ss_gad_ioctl(
3102 struct usb_gadget *pgadget,
ffc83a79 3103 unsigned int code,
33aa8d45
MD		 3104 unsigned long param)
3105{
33aa8d45
MD		 3106 return 0;
3107}
3108
33aa8d45
MD		 3109static const struct usb_gadget_ops nbu2ss_gadget_ops = {
3110 .get_frame = nbu2ss_gad_get_frame,
3111 .wakeup = nbu2ss_gad_wakeup,
3112 .set_selfpowered = nbu2ss_gad_set_selfpowered,
3113 .vbus_session = nbu2ss_gad_vbus_session,
3114 .vbus_draw = nbu2ss_gad_vbus_draw,
3115 .pullup = nbu2ss_gad_pullup,
3116 .ioctl = nbu2ss_gad_ioctl,
3117};
3118
68b5c947
RB		 3119static const struct {
3120 const char *name;
3121 const struct usb_ep_caps caps;
3122} ep_info[NUM_ENDPOINTS] = {
3123#define EP_INFO(_name, _caps) \
3124 { \
3125 .name = _name, \
3126 .caps = _caps, \
3127 }
3128
3129 EP_INFO("ep0",
3130 USB_EP_CAPS(USB_EP_CAPS_TYPE_CONTROL, USB_EP_CAPS_DIR_ALL)),
3131 EP_INFO("ep1-bulk",
3132 USB_EP_CAPS(USB_EP_CAPS_TYPE_BULK, USB_EP_CAPS_DIR_ALL)),
3133 EP_INFO("ep2-bulk",
3134 USB_EP_CAPS(USB_EP_CAPS_TYPE_BULK, USB_EP_CAPS_DIR_ALL)),
3135 EP_INFO("ep3in-int",
3136 USB_EP_CAPS(USB_EP_CAPS_TYPE_INT, USB_EP_CAPS_DIR_IN)),
3137 EP_INFO("ep4-iso",
3138 USB_EP_CAPS(USB_EP_CAPS_TYPE_ISO, USB_EP_CAPS_DIR_ALL)),
3139 EP_INFO("ep5-iso",
3140 USB_EP_CAPS(USB_EP_CAPS_TYPE_ISO, USB_EP_CAPS_DIR_ALL)),
3141 EP_INFO("ep6-bulk",
3142 USB_EP_CAPS(USB_EP_CAPS_TYPE_BULK, USB_EP_CAPS_DIR_ALL)),
3143 EP_INFO("ep7-bulk",
3144 USB_EP_CAPS(USB_EP_CAPS_TYPE_BULK, USB_EP_CAPS_DIR_ALL)),
3145 EP_INFO("ep8in-int",
3146 USB_EP_CAPS(USB_EP_CAPS_TYPE_INT, USB_EP_CAPS_DIR_IN)),
3147 EP_INFO("ep9-iso",
3148 USB_EP_CAPS(USB_EP_CAPS_TYPE_ISO, USB_EP_CAPS_DIR_ALL)),
3149 EP_INFO("epa-iso",
3150 USB_EP_CAPS(USB_EP_CAPS_TYPE_ISO, USB_EP_CAPS_DIR_ALL)),
3151 EP_INFO("epb-bulk",
3152 USB_EP_CAPS(USB_EP_CAPS_TYPE_BULK, USB_EP_CAPS_DIR_ALL)),
3153 EP_INFO("epc-bulk",
3154 USB_EP_CAPS(USB_EP_CAPS_TYPE_BULK, USB_EP_CAPS_DIR_ALL)),
3155 EP_INFO("epdin-int",
3156 USB_EP_CAPS(USB_EP_CAPS_TYPE_INT, USB_EP_CAPS_DIR_IN)),
3157
3158#undef EP_INFO
33aa8d45
MD		 3159};
3160
33aa8d45
MD		 3161/*-------------------------------------------------------------------------*/
3162static void __init nbu2ss_drv_ep_init(struct nbu2ss_udc *udc)
3163{
3164 int i;
3165
3166 INIT_LIST_HEAD(&udc->gadget.ep_list);
3167 udc->gadget.ep0 = &udc->ep[0].ep;
3168
737fee1b
CR		 3169 for (i = 0; i < NUM_ENDPOINTS; i++) {
3170 struct nbu2ss_ep *ep = &udc->ep[i];
33aa8d45 3171
737fee1b
CR		 3172 ep->udc = udc;
3173 ep->desc = NULL;
3174
3175 ep->ep.driver_data = NULL;
68b5c947
RB		 3176 ep->ep.name = ep_info[i].name;
3177 ep->ep.caps = ep_info[i].caps;
737fee1b
CR		 3178 ep->ep.ops = &nbu2ss_ep_ops;
3179
cb009d6e 3180 usb_ep_set_maxpacket_limit(&ep->ep,
c75955d1
AM		 3181 i == 0 ? EP0_PACKETSIZE
3182 : EP_PACKETSIZE);
737fee1b
CR		 3183
3184 list_add_tail(&ep->ep.ep_list, &udc->gadget.ep_list);
3185 INIT_LIST_HEAD(&ep->queue);
3186 }
33aa8d45
MD		 3187
3188 list_del_init(&udc->ep[0].ep.ep_list);
3189}
3190
3191/*-------------------------------------------------------------------------*/
3192/* platform_driver */
3193static int __init nbu2ss_drv_contest_init(
3194 struct platform_device *pdev,
3195 struct nbu2ss_udc *udc)
3196{
3197 spin_lock_init(&udc->lock);
3198 udc->dev = &pdev->dev;
3199
9239d88f 3200 udc->gadget.is_selfpowered = 1;
33aa8d45
MD		 3201 udc->devstate = USB_STATE_NOTATTACHED;
3202 udc->pdev = pdev;
3203 udc->mA = 0;
3204
3205 udc->pdev->dev.coherent_dma_mask = DMA_BIT_MASK(32);
3206
3207 /* init Endpoint */
3208 nbu2ss_drv_ep_init(udc);
3209
3210 /* init Gadget */
3211 udc->gadget.ops = &nbu2ss_gadget_ops;
3212 udc->gadget.ep0 = &udc->ep[0].ep;
3213 udc->gadget.speed = USB_SPEED_UNKNOWN;
3214 udc->gadget.name = driver_name;
a2c14e97 3215 /* udc->gadget.is_dualspeed = 1; */
33aa8d45
MD		 3216
3217 device_initialize(&udc->gadget.dev);
3218
3219 dev_set_name(&udc->gadget.dev, "gadget");
3220 udc->gadget.dev.parent = &pdev->dev;
3221 udc->gadget.dev.dma_mask = pdev->dev.dma_mask;
3222
3223 return 0;
3224}
3225
3226/*
3227 * probe - binds to the platform device
3228 */
3229static int nbu2ss_drv_probe(struct platform_device *pdev)
3230{
3231 int status = -ENODEV;
3232 struct nbu2ss_udc *udc;
96b29cac
MD		 3233 struct resource *r;
3234 int irq;
3235 void __iomem *mmio_base;
33aa8d45
MD		 3236
3237 udc = &udc_controller;
3238 memset(udc, 0, sizeof(struct nbu2ss_udc));
3239
3240 platform_set_drvdata(pdev, udc);
3241
96b29cac
MD		 3242 /* require I/O memory and IRQ to be provided as resources */
3243 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
a790ebc1
SK		 3244 mmio_base = devm_ioremap_resource(&pdev->dev, r);
3245 if (IS_ERR(mmio_base))
96b29cac 3246 return PTR_ERR(mmio_base);
33aa8d45 3247
96b29cac
MD		 3248 irq = platform_get_irq(pdev, 0);
3249 if (irq < 0) {
3250 dev_err(&pdev->dev, "failed to get IRQ\n");
3251 return irq;
33aa8d45 3252 }
96b29cac
MD		 3253 status = devm_request_irq(&pdev->dev, irq, _nbu2ss_udc_irq,
3254 0, driver_name, udc);
33aa8d45
MD		 3255
3256 /* IO Memory */
f6ef6c09 3257 udc->p_regs = (struct fc_regs *)mmio_base;
33aa8d45
MD		 3258
3259 /* USB Function Controller Interrupt */
33aa8d45 3260 if (status != 0) {
88689279 3261 dev_err(udc->dev, "request_irq(USB_UDC_IRQ_1) failed\n");
c648a57a 3262 return status;
33aa8d45
MD		 3263 }
3264
3265 /* Driver Initialization */
3266 status = nbu2ss_drv_contest_init(pdev, udc);
3267 if (status < 0) {
3268 /* Error */
c648a57a 3269 return status;
33aa8d45
MD		 3270 }
3271
3272 /* VBUS Interrupt */
3273 irq_set_irq_type(INT_VBUS, IRQ_TYPE_EDGE_BOTH);
3274 status = request_irq(INT_VBUS,
c75955d1 3275 _nbu2ss_vbus_irq, IRQF_SHARED, driver_name, udc);
33aa8d45
MD		 3276
3277 if (status != 0) {
88689279 3278 dev_err(udc->dev, "request_irq(INT_VBUS) failed\n");
c648a57a 3279 return status;
33aa8d45
MD		 3280 }
3281
3282 return status;
33aa8d45
MD		 3283}
3284
3285/*-------------------------------------------------------------------------*/
3286static void nbu2ss_drv_shutdown(struct platform_device *pdev)
3287{
3288 struct nbu2ss_udc *udc;
3289
3290 udc = platform_get_drvdata(pdev);
706eb8cf 3291 if (!udc)
33aa8d45
MD		 3292 return;
3293
3294 _nbu2ss_disable_controller(udc);
3295}
3296
0bf048ab
AB		 3297/*-------------------------------------------------------------------------*/
3298static int nbu2ss_drv_remove(struct platform_device *pdev)
3299{
3300 struct nbu2ss_udc *udc;
3301 struct nbu2ss_ep *ep;
3302 int i;
3303
3304 udc = &udc_controller;
3305
3306 for (i = 0; i < NUM_ENDPOINTS; i++) {
3307 ep = &udc->ep[i];
3308 if (ep->virt_buf)
3309 dma_free_coherent(NULL, PAGE_SIZE,
3310 (void *)ep->virt_buf, ep->phys_buf);
3311 }
3312
3313 /* Interrupt Handler - Release */
3314 free_irq(INT_VBUS, udc);
3315
3316 return 0;
3317}
3318
33aa8d45
MD		 3319/*-------------------------------------------------------------------------*/
3320static int nbu2ss_drv_suspend(struct platform_device *pdev, pm_message_t state)
3321{
3322 struct nbu2ss_udc *udc;
3323
3324 udc = platform_get_drvdata(pdev);
706eb8cf 3325 if (!udc)
33aa8d45
MD		 3326 return 0;
3327
3328 if (udc->vbus_active) {
3329 udc->vbus_active = 0;
3330 udc->devstate = USB_STATE_NOTATTACHED;
3331 udc->linux_suspended = 1;
3332
3333 if (udc->usb_suspended) {
3334 udc->usb_suspended = 0;
3335 _nbu2ss_reset_controller(udc);
3336 }
3337
3338 _nbu2ss_quiesce(udc);
3339 }
3340 _nbu2ss_disable_controller(udc);
3341
3342 return 0;
3343}
3344
3345/*-------------------------------------------------------------------------*/
3346static int nbu2ss_drv_resume(struct platform_device *pdev)
3347{
3348 u32 data;
3349 struct nbu2ss_udc *udc;
3350
3351 udc = platform_get_drvdata(pdev);
706eb8cf 3352 if (!udc)
33aa8d45
MD		 3353 return 0;
3354
3355 data = gpio_get_value(VBUS_VALUE);
3356 if (data) {
3357 udc->vbus_active = 1;
3358 udc->devstate = USB_STATE_POWERED;
3359 _nbu2ss_enable_controller(udc);
3360 _nbu2ss_pullup(udc, 1);
3361 }
3362
3363 udc->linux_suspended = 0;
3364
3365 return 0;
3366}
3367
33aa8d45
MD		 3368static struct platform_driver udc_driver = {
3369 .probe = nbu2ss_drv_probe,
3370 .shutdown = nbu2ss_drv_shutdown,
0bf048ab 3371 .remove = nbu2ss_drv_remove,
33aa8d45
MD		 3372 .suspend = nbu2ss_drv_suspend,
3373 .resume = nbu2ss_drv_resume,
3374 .driver = {
0bf048ab 3375 .name = driver_name,
33aa8d45
MD		 3376 },
3377};
3378
0bf048ab
AB		 3379module_platform_driver(udc_driver);
3380
3381MODULE_DESCRIPTION(DRIVER_DESC);
3382MODULE_AUTHOR("Renesas Electronics Corporation");
3383MODULE_LICENSE("GPL");
Linux kernel - Deliverables
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