[deliverable/linux.git] / drivers / staging / fbtft / fb_ili9320.c

/*
 * FB driver for the ILI9320 LCD Controller
 *
 * Copyright (C) 2013 Noralf Tronnes
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 */

#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/gpio.h>
#include <linux/spi/spi.h>
#include <linux/delay.h>

#include "fbtft.h"

#define DRVNAME		"fb_ili9320"
#define WIDTH		240
#define HEIGHT		320
#define DEFAULT_GAMMA	"07 07 6 0 0 0 5 5 4 0\n" \
			"07 08 4 7 5 1 2 0 7 7"

static unsigned int read_devicecode(struct fbtft_par *par)
{
	int ret;
	u8 rxbuf[8] = {0, };

	write_reg(par, 0x0000);
	ret = par->fbtftops.read(par, rxbuf, 4);
	return (rxbuf[2] << 8) | rxbuf[3];
}

static int init_display(struct fbtft_par *par)
{
	unsigned int devcode;

	par->fbtftops.reset(par);

	devcode = read_devicecode(par);
	fbtft_par_dbg(DEBUG_INIT_DISPLAY, par, "Device code: 0x%04X\n",
		      devcode);
	if ((devcode != 0x0000) && (devcode != 0x9320))
		dev_warn(par->info->device,
			 "Unrecognized Device code: 0x%04X (expected 0x9320)\n",
			devcode);

	/* Initialization sequence from ILI9320 Application Notes */

	/* *********** Start Initial Sequence ********* */
	/* Set the Vcore voltage and this setting is must. */
	write_reg(par, 0x00E5, 0x8000);

	/* Start internal OSC. */
	write_reg(par, 0x0000, 0x0001);

	/* set SS and SM bit */
	write_reg(par, 0x0001, 0x0100);

	/* set 1 line inversion */
	write_reg(par, 0x0002, 0x0700);

	/* Resize register */
	write_reg(par, 0x0004, 0x0000);

	/* set the back and front porch */
	write_reg(par, 0x0008, 0x0202);

	/* set non-display area refresh cycle */
	write_reg(par, 0x0009, 0x0000);

	/* FMARK function */
	write_reg(par, 0x000A, 0x0000);

	/* RGB interface setting */
	write_reg(par, 0x000C, 0x0000);

	/* Frame marker Position */
	write_reg(par, 0x000D, 0x0000);

	/* RGB interface polarity */
	write_reg(par, 0x000F, 0x0000);

	/* ***********Power On sequence *************** */
	/* SAP, BT[3:0], AP, DSTB, SLP, STB */
	write_reg(par, 0x0010, 0x0000);

	/* DC1[2:0], DC0[2:0], VC[2:0] */
	write_reg(par, 0x0011, 0x0007);

	/* VREG1OUT voltage */
	write_reg(par, 0x0012, 0x0000);

	/* VDV[4:0] for VCOM amplitude */
	write_reg(par, 0x0013, 0x0000);

	/* Dis-charge capacitor power voltage */
	mdelay(200);

	/* SAP, BT[3:0], AP, DSTB, SLP, STB */
	write_reg(par, 0x0010, 0x17B0);

	/* R11h=0x0031 at VCI=3.3V DC1[2:0], DC0[2:0], VC[2:0] */
	write_reg(par, 0x0011, 0x0031);
	mdelay(50);

	/* R12h=0x0138 at VCI=3.3V VREG1OUT voltage */
	write_reg(par, 0x0012, 0x0138);
	mdelay(50);

	/* R13h=0x1800 at VCI=3.3V VDV[4:0] for VCOM amplitude */
	write_reg(par, 0x0013, 0x1800);

	/* R29h=0x0008 at VCI=3.3V VCM[4:0] for VCOMH */
	write_reg(par, 0x0029, 0x0008);
	mdelay(50);

	/* GRAM horizontal Address */
	write_reg(par, 0x0020, 0x0000);

	/* GRAM Vertical Address */
	write_reg(par, 0x0021, 0x0000);

	/* ------------------ Set GRAM area --------------- */
	/* Horizontal GRAM Start Address */
	write_reg(par, 0x0050, 0x0000);

	/* Horizontal GRAM End Address */
	write_reg(par, 0x0051, 0x00EF);

	/* Vertical GRAM Start Address */
	write_reg(par, 0x0052, 0x0000);

	/* Vertical GRAM End Address */
	write_reg(par, 0x0053, 0x013F);

	/* Gate Scan Line */
	write_reg(par, 0x0060, 0x2700);

	/* NDL,VLE, REV */
	write_reg(par, 0x0061, 0x0001);

	/* set scrolling line */
	write_reg(par, 0x006A, 0x0000);

	/* -------------- Partial Display Control --------- */
	write_reg(par, 0x0080, 0x0000);
	write_reg(par, 0x0081, 0x0000);
	write_reg(par, 0x0082, 0x0000);
	write_reg(par, 0x0083, 0x0000);
	write_reg(par, 0x0084, 0x0000);
	write_reg(par, 0x0085, 0x0000);

	/* -------------- Panel Control ------------------- */
	write_reg(par, 0x0090, 0x0010);
	write_reg(par, 0x0092, 0x0000);
	write_reg(par, 0x0093, 0x0003);
	write_reg(par, 0x0095, 0x0110);
	write_reg(par, 0x0097, 0x0000);
	write_reg(par, 0x0098, 0x0000);
	write_reg(par, 0x0007, 0x0173); /* 262K color and display ON */

	return 0;
}

static void set_addr_win(struct fbtft_par *par, int xs, int ys, int xe, int ye)
{
	switch (par->info->var.rotate) {
	/* R20h = Horizontal GRAM Start Address */
	/* R21h = Vertical GRAM Start Address */
	case 0:
		write_reg(par, 0x0020, xs);
		write_reg(par, 0x0021, ys);
		break;
	case 180:
		write_reg(par, 0x0020, WIDTH - 1 - xs);
		write_reg(par, 0x0021, HEIGHT - 1 - ys);
		break;
	case 270:
		write_reg(par, 0x0020, WIDTH - 1 - ys);
		write_reg(par, 0x0021, xs);
		break;
	case 90:
		write_reg(par, 0x0020, ys);
		write_reg(par, 0x0021, HEIGHT - 1 - xs);
		break;
	}
	write_reg(par, 0x0022); /* Write Data to GRAM */
}

static int set_var(struct fbtft_par *par)
{
	switch (par->info->var.rotate) {
	case 0:
		write_reg(par, 0x3, (par->bgr << 12) | 0x30);
		break;
	case 270:
		write_reg(par, 0x3, (par->bgr << 12) | 0x28);
		break;
	case 180:
		write_reg(par, 0x3, (par->bgr << 12) | 0x00);
		break;
	case 90:
		write_reg(par, 0x3, (par->bgr << 12) | 0x18);
		break;
	}
	return 0;
}

/*
 * Gamma string format:
 *  VRP0 VRP1 RP0 RP1 KP0 KP1 KP2 KP3 KP4 KP5
 *  VRN0 VRN1 RN0 RN1 KN0 KN1 KN2 KN3 KN4 KN5
 */
#define CURVE(num, idx)  curves[num * par->gamma.num_values + idx]
static int set_gamma(struct fbtft_par *par, unsigned long *curves)
{
	unsigned long mask[] = {
		0x1f, 0x1f, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07,
		0x1f, 0x1f, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07,
	};
	int i, j;

	/* apply mask */
	for (i = 0; i < 2; i++)
		for (j = 0; j < 10; j++)
			CURVE(i, j) &= mask[i * par->gamma.num_values + j];

	write_reg(par, 0x0030, CURVE(0, 5) << 8 | CURVE(0, 4));
	write_reg(par, 0x0031, CURVE(0, 7) << 8 | CURVE(0, 6));
	write_reg(par, 0x0032, CURVE(0, 9) << 8 | CURVE(0, 8));
	write_reg(par, 0x0035, CURVE(0, 3) << 8 | CURVE(0, 2));
	write_reg(par, 0x0036, CURVE(0, 1) << 8 | CURVE(0, 0));

	write_reg(par, 0x0037, CURVE(1, 5) << 8 | CURVE(1, 4));
	write_reg(par, 0x0038, CURVE(1, 7) << 8 | CURVE(1, 6));
	write_reg(par, 0x0039, CURVE(1, 9) << 8 | CURVE(1, 8));
	write_reg(par, 0x003C, CURVE(1, 3) << 8 | CURVE(1, 2));
	write_reg(par, 0x003D, CURVE(1, 1) << 8 | CURVE(1, 0));

	return 0;
}

#undef CURVE

static struct fbtft_display display = {
	.regwidth = 16,
	.width = WIDTH,
	.height = HEIGHT,
	.gamma_num = 2,
	.gamma_len = 10,
	.gamma = DEFAULT_GAMMA,
	.fbtftops = {
		.init_display = init_display,
		.set_addr_win = set_addr_win,
		.set_var = set_var,
		.set_gamma = set_gamma,
	},
};

FBTFT_REGISTER_DRIVER(DRVNAME, "ilitek,ili9320", &display);

MODULE_ALIAS("spi:" DRVNAME);
MODULE_ALIAS("platform:" DRVNAME);
MODULE_ALIAS("spi:ili9320");
MODULE_ALIAS("platform:ili9320");

MODULE_DESCRIPTION("FB driver for the ILI9320 LCD Controller");
MODULE_AUTHOR("Noralf Tronnes");
MODULE_LICENSE("GPL");
Commit	Line	Data
69e6089d TP	1	/*
	2	* FB driver for the ILI9320 LCD Controller
	3	*
	4	* Copyright (C) 2013 Noralf Tronnes
	5	*
	6	* This program is free software; you can redistribute it and/or modify
	7	* it under the terms of the GNU General Public License as published by
	8	* the Free Software Foundation; either version 2 of the License, or
	9	* (at your option) any later version.
	10	*
	11	* This program is distributed in the hope that it will be useful,
	12	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	13	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	14	* GNU General Public License for more details.
69e6089d TP	15	*/
	16
	17	#include <linux/module.h>
	18	#include <linux/kernel.h>
	19	#include <linux/init.h>
	20	#include <linux/gpio.h>
	21	#include <linux/spi/spi.h>
	22	#include <linux/delay.h>
	23
	24	#include "fbtft.h"
	25
	26	#define DRVNAME "fb_ili9320"
	27	#define WIDTH 240
	28	#define HEIGHT 320
	29	#define DEFAULT_GAMMA "07 07 6 0 0 0 5 5 4 0\n" \
	30	"07 08 4 7 5 1 2 0 7 7"
	31
1c41494a	32	static unsigned int read_devicecode(struct fbtft_par *par)
69e6089d TP	33	{
	34	int ret;
	35	u8 rxbuf[8] = {0, };
	36
	37	write_reg(par, 0x0000);
	38	ret = par->fbtftops.read(par, rxbuf, 4);
	39	return (rxbuf[2] << 8) \| rxbuf[3];
	40	}
	41
	42	static int init_display(struct fbtft_par *par)
	43	{
1c41494a	44	unsigned int devcode;
9247a2a1	45
69e6089d TP	46	par->fbtftops.reset(par);
	47
	48	devcode = read_devicecode(par);
	49	fbtft_par_dbg(DEBUG_INIT_DISPLAY, par, "Device code: 0x%04X\n",
f07e89ce	50	devcode);
69e6089d TP	51	if ((devcode != 0x0000) && (devcode != 0x9320))
69e6089d TP	52	dev_warn(par->info->device,
f07e89ce	53	"Unrecognized Device code: 0x%04X (expected 0x9320)\n",
69e6089d TP	54	devcode);
	55
	56	/* Initialization sequence from ILI9320 Application Notes */
	57
	58	/* ********* Start Initial Sequence ******* */
9026b5d5 AG	59	/* Set the Vcore voltage and this setting is must. */
	60	write_reg(par, 0x00E5, 0x8000);
	61
	62	/* Start internal OSC. */
	63	write_reg(par, 0x0000, 0x0001);
	64
	65	/* set SS and SM bit */
	66	write_reg(par, 0x0001, 0x0100);
	67
	68	/* set 1 line inversion */
	69	write_reg(par, 0x0002, 0x0700);
	70
	71	/* Resize register */
	72	write_reg(par, 0x0004, 0x0000);
	73
	74	/* set the back and front porch */
	75	write_reg(par, 0x0008, 0x0202);
	76
	77	/* set non-display area refresh cycle */
	78	write_reg(par, 0x0009, 0x0000);
	79
	80	/* FMARK function */
	81	write_reg(par, 0x000A, 0x0000);
	82
	83	/* RGB interface setting */
	84	write_reg(par, 0x000C, 0x0000);
	85
	86	/* Frame marker Position */
	87	write_reg(par, 0x000D, 0x0000);
	88
	89	/* RGB interface polarity */
	90	write_reg(par, 0x000F, 0x0000);
	91
69e6089d	92	/* *********Power On sequence ************* */
9026b5d5 AG	93	/* SAP, BT[3:0], AP, DSTB, SLP, STB */
	94	write_reg(par, 0x0010, 0x0000);
	95
	96	/* DC1[2:0], DC0[2:0], VC[2:0] */
	97	write_reg(par, 0x0011, 0x0007);
	98
	99	/* VREG1OUT voltage */
	100	write_reg(par, 0x0012, 0x0000);
	101
	102	/* VDV[4:0] for VCOM amplitude */
	103	write_reg(par, 0x0013, 0x0000);
	104
	105	/* Dis-charge capacitor power voltage */
	106	mdelay(200);
	107
	108	/* SAP, BT[3:0], AP, DSTB, SLP, STB */
	109	write_reg(par, 0x0010, 0x17B0);
	110
	111	/* R11h=0x0031 at VCI=3.3V DC1[2:0], DC0[2:0], VC[2:0] */
	112	write_reg(par, 0x0011, 0x0031);
69e6089d	113	mdelay(50);
9026b5d5 AG	114
	115	/* R12h=0x0138 at VCI=3.3V VREG1OUT voltage */
	116	write_reg(par, 0x0012, 0x0138);
69e6089d	117	mdelay(50);
9026b5d5 AG	118
	119	/* R13h=0x1800 at VCI=3.3V VDV[4:0] for VCOM amplitude */
	120	write_reg(par, 0x0013, 0x1800);
	121
	122	/* R29h=0x0008 at VCI=3.3V VCM[4:0] for VCOMH */
	123	write_reg(par, 0x0029, 0x0008);
69e6089d	124	mdelay(50);
9026b5d5 AG	125
	126	/* GRAM horizontal Address */
	127	write_reg(par, 0x0020, 0x0000);
	128
	129	/* GRAM Vertical Address */
	130	write_reg(par, 0x0021, 0x0000);
69e6089d TP	131
69e6089d TP	132	/* ------------------ Set GRAM area --------------- */
9026b5d5 AG	133	/* Horizontal GRAM Start Address */
	134	write_reg(par, 0x0050, 0x0000);
	135
	136	/* Horizontal GRAM End Address */
	137	write_reg(par, 0x0051, 0x00EF);
	138
	139	/* Vertical GRAM Start Address */
	140	write_reg(par, 0x0052, 0x0000);
	141
38e12727	142	/* Vertical GRAM End Address */
9026b5d5 AG	143	write_reg(par, 0x0053, 0x013F);
	144
	145	/* Gate Scan Line */
	146	write_reg(par, 0x0060, 0x2700);
	147
	148	/* NDL,VLE, REV */
	149	write_reg(par, 0x0061, 0x0001);
	150
	151	/* set scrolling line */
	152	write_reg(par, 0x006A, 0x0000);
69e6089d TP	153
	154	/* -------------- Partial Display Control --------- */
	155	write_reg(par, 0x0080, 0x0000);
	156	write_reg(par, 0x0081, 0x0000);
	157	write_reg(par, 0x0082, 0x0000);
	158	write_reg(par, 0x0083, 0x0000);
	159	write_reg(par, 0x0084, 0x0000);
	160	write_reg(par, 0x0085, 0x0000);
	161
	162	/* -------------- Panel Control ------------------- */
	163	write_reg(par, 0x0090, 0x0010);
	164	write_reg(par, 0x0092, 0x0000);
	165	write_reg(par, 0x0093, 0x0003);
	166	write_reg(par, 0x0095, 0x0110);
	167	write_reg(par, 0x0097, 0x0000);
	168	write_reg(par, 0x0098, 0x0000);
	169	write_reg(par, 0x0007, 0x0173); /* 262K color and display ON */
	170
	171	return 0;
	172	}
	173
	174	static void set_addr_win(struct fbtft_par *par, int xs, int ys, int xe, int ye)
	175	{
69e6089d TP	176	switch (par->info->var.rotate) {
	177	/* R20h = Horizontal GRAM Start Address */
	178	/* R21h = Vertical GRAM Start Address */
	179	case 0:
	180	write_reg(par, 0x0020, xs);
	181	write_reg(par, 0x0021, ys);
	182	break;
	183	case 180:
	184	write_reg(par, 0x0020, WIDTH - 1 - xs);
	185	write_reg(par, 0x0021, HEIGHT - 1 - ys);
	186	break;
	187	case 270:
	188	write_reg(par, 0x0020, WIDTH - 1 - ys);
	189	write_reg(par, 0x0021, xs);
	190	break;
	191	case 90:
	192	write_reg(par, 0x0020, ys);
	193	write_reg(par, 0x0021, HEIGHT - 1 - xs);
	194	break;
	195	}
	196	write_reg(par, 0x0022); /* Write Data to GRAM */
	197	}
	198
	199	static int set_var(struct fbtft_par *par)
	200	{
69e6089d TP	201	switch (par->info->var.rotate) {
	202	case 0:
	203	write_reg(par, 0x3, (par->bgr << 12) \| 0x30);
	204	break;
	205	case 270:
	206	write_reg(par, 0x3, (par->bgr << 12) \| 0x28);
	207	break;
	208	case 180:
	209	write_reg(par, 0x3, (par->bgr << 12) \| 0x00);
	210	break;
	211	case 90:
	212	write_reg(par, 0x3, (par->bgr << 12) \| 0x18);
	213	break;
	214	}
	215	return 0;
	216	}
	217
	218	/*
3a334ea5 ERR	219	* Gamma string format:
	220	* VRP0 VRP1 RP0 RP1 KP0 KP1 KP2 KP3 KP4 KP5
	221	* VRN0 VRN1 RN0 RN1 KN0 KN1 KN2 KN3 KN4 KN5
	222	*/
94c0a544	223	#define CURVE(num, idx) curves[num * par->gamma.num_values + idx]
69e6089d TP	224	static int set_gamma(struct fbtft_par par, unsigned long curves)
	225	{
	226	unsigned long mask[] = {
153fe946 GU	227	0x1f, 0x1f, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07,
	228	0x1f, 0x1f, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07,
	229	};
69e6089d TP	230	int i, j;
69e6089d TP	231
69e6089d TP	232	/* apply mask */
	233	for (i = 0; i < 2; i++)
	234	for (j = 0; j < 10; j++)
94c0a544	235	CURVE(i, j) &= mask[i * par->gamma.num_values + j];
69e6089d TP	236
	237	write_reg(par, 0x0030, CURVE(0, 5) << 8 \| CURVE(0, 4));
	238	write_reg(par, 0x0031, CURVE(0, 7) << 8 \| CURVE(0, 6));
	239	write_reg(par, 0x0032, CURVE(0, 9) << 8 \| CURVE(0, 8));
	240	write_reg(par, 0x0035, CURVE(0, 3) << 8 \| CURVE(0, 2));
	241	write_reg(par, 0x0036, CURVE(0, 1) << 8 \| CURVE(0, 0));
	242
	243	write_reg(par, 0x0037, CURVE(1, 5) << 8 \| CURVE(1, 4));
	244	write_reg(par, 0x0038, CURVE(1, 7) << 8 \| CURVE(1, 6));
	245	write_reg(par, 0x0039, CURVE(1, 9) << 8 \| CURVE(1, 8));
	246	write_reg(par, 0x003C, CURVE(1, 3) << 8 \| CURVE(1, 2));
	247	write_reg(par, 0x003D, CURVE(1, 1) << 8 \| CURVE(1, 0));
	248
	249	return 0;
	250	}
b4ac6b28	251
69e6089d TP	252	#undef CURVE
69e6089d TP	253
69e6089d TP	254	static struct fbtft_display display = {
	255	.regwidth = 16,
	256	.width = WIDTH,
	257	.height = HEIGHT,
	258	.gamma_num = 2,
	259	.gamma_len = 10,
	260	.gamma = DEFAULT_GAMMA,
	261	.fbtftops = {
	262	.init_display = init_display,
	263	.set_addr_win = set_addr_win,
	264	.set_var = set_var,
	265	.set_gamma = set_gamma,
	266	},
	267	};
1014c2ce	268
69e6089d TP	269	FBTFT_REGISTER_DRIVER(DRVNAME, "ilitek,ili9320", &display);
	270
	271	MODULE_ALIAS("spi:" DRVNAME);
	272	MODULE_ALIAS("platform:" DRVNAME);
	273	MODULE_ALIAS("spi:ili9320");
	274	MODULE_ALIAS("platform:ili9320");
	275
	276	MODULE_DESCRIPTION("FB driver for the ILI9320 LCD Controller");
	277	MODULE_AUTHOR("Noralf Tronnes");
	278	MODULE_LICENSE("GPL");