[deliverable/linux.git] / drivers / staging / iio / dds / ad9832.c

/*
 * AD9832 SPI DDS driver
 *
 * Copyright 2011 Analog Devices Inc.
 *
 * Licensed under the GPL-2.
 */

#include <linux/device.h>
#include <linux/kernel.h>
#include <linux/slab.h>
#include <linux/sysfs.h>
#include <linux/spi/spi.h>
#include <linux/regulator/consumer.h>
#include <linux/err.h>
#include <linux/module.h>
#include <asm/div64.h>

#include "../iio.h"
#include "../sysfs.h"
#include "dds.h"

#include "ad9832.h"

static unsigned long ad9832_calc_freqreg(unsigned long mclk, unsigned long fout)
{
	unsigned long long freqreg = (u64) fout *
				     (u64) ((u64) 1L << AD9832_FREQ_BITS);
	do_div(freqreg, mclk);
	return freqreg;
}

static int ad9832_write_frequency(struct ad9832_state *st,
				  unsigned addr, unsigned long fout)
{
	unsigned long regval;

	if (fout > (st->mclk / 2))
		return -EINVAL;

	regval = ad9832_calc_freqreg(st->mclk, fout);

	st->freq_data[0] = cpu_to_be16((AD9832_CMD_FRE8BITSW << CMD_SHIFT) |
					(addr << ADD_SHIFT) |
					((regval >> 24) & 0xFF));
	st->freq_data[1] = cpu_to_be16((AD9832_CMD_FRE16BITSW << CMD_SHIFT) |
					((addr - 1) << ADD_SHIFT) |
					((regval >> 16) & 0xFF));
	st->freq_data[2] = cpu_to_be16((AD9832_CMD_FRE8BITSW << CMD_SHIFT) |
					((addr - 2) << ADD_SHIFT) |
					((regval >> 8) & 0xFF));
	st->freq_data[3] = cpu_to_be16((AD9832_CMD_FRE16BITSW << CMD_SHIFT) |
					((addr - 3) << ADD_SHIFT) |
					((regval >> 0) & 0xFF));

	return spi_sync(st->spi, &st->freq_msg);;
}

static int ad9832_write_phase(struct ad9832_state *st,
				  unsigned long addr, unsigned long phase)
{
	if (phase > (1 << AD9832_PHASE_BITS))
		return -EINVAL;

	st->phase_data[0] = cpu_to_be16((AD9832_CMD_PHA8BITSW << CMD_SHIFT) |
					(addr << ADD_SHIFT) |
					((phase >> 8) & 0xFF));
	st->phase_data[1] = cpu_to_be16((AD9832_CMD_PHA16BITSW << CMD_SHIFT) |
					((addr - 1) << ADD_SHIFT) |
					(phase & 0xFF));

	return spi_sync(st->spi, &st->phase_msg);
}

static ssize_t ad9832_write(struct device *dev,
		struct device_attribute *attr,
		const char *buf,
		size_t len)
{
	struct iio_dev *indio_dev = dev_get_drvdata(dev);
	struct ad9832_state *st = iio_priv(indio_dev);
	struct iio_dev_attr *this_attr = to_iio_dev_attr(attr);
	int ret;
	long val;

	ret = strict_strtoul(buf, 10, &val);
	if (ret)
		goto error_ret;

	mutex_lock(&indio_dev->mlock);
	switch (this_attr->address) {
	case AD9832_FREQ0HM:
	case AD9832_FREQ1HM:
		ret = ad9832_write_frequency(st, this_attr->address, val);
		break;
	case AD9832_PHASE0H:
	case AD9832_PHASE1H:
	case AD9832_PHASE2H:
	case AD9832_PHASE3H:
		ret = ad9832_write_phase(st, this_attr->address, val);
		break;
	case AD9832_PINCTRL_EN:
		if (val)
			st->ctrl_ss &= ~AD9832_SELSRC;
		else
			st->ctrl_ss |= AD9832_SELSRC;
		st->data = cpu_to_be16((AD9832_CMD_SYNCSELSRC << CMD_SHIFT) |
					st->ctrl_ss);
		ret = spi_sync(st->spi, &st->msg);
		break;
	case AD9832_FREQ_SYM:
		if (val == 1)
			st->ctrl_fp |= AD9832_FREQ;
		else if (val == 0)
			st->ctrl_fp &= ~AD9832_FREQ;
		else {
			ret = -EINVAL;
			break;
		}
		st->data = cpu_to_be16((AD9832_CMD_FPSELECT << CMD_SHIFT) |
					st->ctrl_fp);
		ret = spi_sync(st->spi, &st->msg);
		break;
	case AD9832_PHASE_SYM:
		if (val < 0 || val > 3) {
			ret = -EINVAL;
			break;
		}

		st->ctrl_fp &= ~AD9832_PHASE(3);
		st->ctrl_fp |= AD9832_PHASE(val);

		st->data = cpu_to_be16((AD9832_CMD_FPSELECT << CMD_SHIFT) |
					st->ctrl_fp);
		ret = spi_sync(st->spi, &st->msg);
		break;
	case AD9832_OUTPUT_EN:
		if (val)
			st->ctrl_src &= ~(AD9832_RESET | AD9832_SLEEP |
					AD9832_CLR);
		else
			st->ctrl_src |= AD9832_RESET;

		st->data = cpu_to_be16((AD9832_CMD_SLEEPRESCLR << CMD_SHIFT) |
					st->ctrl_src);
		ret = spi_sync(st->spi, &st->msg);
		break;
	default:
		ret = -ENODEV;
	}
	mutex_unlock(&indio_dev->mlock);

error_ret:
	return ret ? ret : len;
}

/**
 * see dds.h for further information
 */

static IIO_DEV_ATTR_FREQ(0, 0, S_IWUSR, NULL, ad9832_write, AD9832_FREQ0HM);
static IIO_DEV_ATTR_FREQ(0, 1, S_IWUSR, NULL, ad9832_write, AD9832_FREQ1HM);
static IIO_DEV_ATTR_FREQSYMBOL(0, S_IWUSR, NULL, ad9832_write, AD9832_FREQ_SYM);
static IIO_CONST_ATTR_FREQ_SCALE(0, "1"); /* 1Hz */

static IIO_DEV_ATTR_PHASE(0, 0, S_IWUSR, NULL, ad9832_write, AD9832_PHASE0H);
static IIO_DEV_ATTR_PHASE(0, 1, S_IWUSR, NULL, ad9832_write, AD9832_PHASE1H);
static IIO_DEV_ATTR_PHASE(0, 2, S_IWUSR, NULL, ad9832_write, AD9832_PHASE2H);
static IIO_DEV_ATTR_PHASE(0, 3, S_IWUSR, NULL, ad9832_write, AD9832_PHASE3H);
static IIO_DEV_ATTR_PHASESYMBOL(0, S_IWUSR, NULL,
				ad9832_write, AD9832_PHASE_SYM);
static IIO_CONST_ATTR_PHASE_SCALE(0, "0.0015339808"); /* 2PI/2^12 rad*/

static IIO_DEV_ATTR_PINCONTROL_EN(0, S_IWUSR, NULL,
				ad9832_write, AD9832_PINCTRL_EN);
static IIO_DEV_ATTR_OUT_ENABLE(0, S_IWUSR, NULL,
				ad9832_write, AD9832_OUTPUT_EN);

static struct attribute *ad9832_attributes[] = {
	&iio_dev_attr_dds0_freq0.dev_attr.attr,
	&iio_dev_attr_dds0_freq1.dev_attr.attr,
	&iio_const_attr_dds0_freq_scale.dev_attr.attr,
	&iio_dev_attr_dds0_phase0.dev_attr.attr,
	&iio_dev_attr_dds0_phase1.dev_attr.attr,
	&iio_dev_attr_dds0_phase2.dev_attr.attr,
	&iio_dev_attr_dds0_phase3.dev_attr.attr,
	&iio_const_attr_dds0_phase_scale.dev_attr.attr,
	&iio_dev_attr_dds0_pincontrol_en.dev_attr.attr,
	&iio_dev_attr_dds0_freqsymbol.dev_attr.attr,
	&iio_dev_attr_dds0_phasesymbol.dev_attr.attr,
	&iio_dev_attr_dds0_out_enable.dev_attr.attr,
	NULL,
};

static const struct attribute_group ad9832_attribute_group = {
	.attrs = ad9832_attributes,
};

static const struct iio_info ad9832_info = {
	.attrs = &ad9832_attribute_group,
	.driver_module = THIS_MODULE,
};

static int __devinit ad9832_probe(struct spi_device *spi)
{
	struct ad9832_platform_data *pdata = spi->dev.platform_data;
	struct iio_dev *indio_dev;
	struct ad9832_state *st;
	struct regulator *reg;
	int ret;

	if (!pdata) {
		dev_dbg(&spi->dev, "no platform data?\n");
		return -ENODEV;
	}

	reg = regulator_get(&spi->dev, "vcc");
	if (!IS_ERR(reg)) {
		ret = regulator_enable(reg);
		if (ret)
			goto error_put_reg;
	}

	indio_dev = iio_allocate_device(sizeof(*st));
	if (indio_dev == NULL) {
		ret = -ENOMEM;
		goto error_disable_reg;
	}
	spi_set_drvdata(spi, indio_dev);
	st = iio_priv(indio_dev);
	st->reg = reg;
	st->mclk = pdata->mclk;
	st->spi = spi;

	indio_dev->dev.parent = &spi->dev;
	indio_dev->name = spi_get_device_id(spi)->name;
	indio_dev->info = &ad9832_info;
	indio_dev->modes = INDIO_DIRECT_MODE;

	/* Setup default messages */

	st->xfer.tx_buf = &st->data;
	st->xfer.len = 2;

	spi_message_init(&st->msg);
	spi_message_add_tail(&st->xfer, &st->msg);

	st->freq_xfer[0].tx_buf = &st->freq_data[0];
	st->freq_xfer[0].len = 2;
	st->freq_xfer[0].cs_change = 1;
	st->freq_xfer[1].tx_buf = &st->freq_data[1];
	st->freq_xfer[1].len = 2;
	st->freq_xfer[1].cs_change = 1;
	st->freq_xfer[2].tx_buf = &st->freq_data[2];
	st->freq_xfer[2].len = 2;
	st->freq_xfer[2].cs_change = 1;
	st->freq_xfer[3].tx_buf = &st->freq_data[3];
	st->freq_xfer[3].len = 2;

	spi_message_init(&st->freq_msg);
	spi_message_add_tail(&st->freq_xfer[0], &st->freq_msg);
	spi_message_add_tail(&st->freq_xfer[1], &st->freq_msg);
	spi_message_add_tail(&st->freq_xfer[2], &st->freq_msg);
	spi_message_add_tail(&st->freq_xfer[3], &st->freq_msg);

	st->phase_xfer[0].tx_buf = &st->phase_data[0];
	st->phase_xfer[0].len = 2;
	st->phase_xfer[0].cs_change = 1;
	st->phase_xfer[1].tx_buf = &st->phase_data[1];
	st->phase_xfer[1].len = 2;

	spi_message_init(&st->phase_msg);
	spi_message_add_tail(&st->phase_xfer[0], &st->phase_msg);
	spi_message_add_tail(&st->phase_xfer[1], &st->phase_msg);

	st->ctrl_src = AD9832_SLEEP | AD9832_RESET | AD9832_CLR;
	st->data = cpu_to_be16((AD9832_CMD_SLEEPRESCLR << CMD_SHIFT) |
					st->ctrl_src);
	ret = spi_sync(st->spi, &st->msg);
	if (ret) {
		dev_err(&spi->dev, "device init failed\n");
		goto error_free_device;
	}

	ret = ad9832_write_frequency(st, AD9832_FREQ0HM, pdata->freq0);
	if (ret)
		goto error_free_device;

	ret = ad9832_write_frequency(st, AD9832_FREQ1HM, pdata->freq1);
	if (ret)
		goto error_free_device;

	ret = ad9832_write_phase(st, AD9832_PHASE0H, pdata->phase0);
	if (ret)
		goto error_free_device;

	ret = ad9832_write_phase(st, AD9832_PHASE1H, pdata->phase1);
	if (ret)
		goto error_free_device;

	ret = ad9832_write_phase(st, AD9832_PHASE2H, pdata->phase2);
	if (ret)
		goto error_free_device;

	ret = ad9832_write_phase(st, AD9832_PHASE3H, pdata->phase3);
	if (ret)
		goto error_free_device;

	ret = iio_device_register(indio_dev);
	if (ret)
		goto error_free_device;

	return 0;

error_free_device:
	iio_free_device(indio_dev);
error_disable_reg:
	if (!IS_ERR(reg))
		regulator_disable(reg);
error_put_reg:
	if (!IS_ERR(reg))
		regulator_put(reg);

	return ret;
}

static int __devexit ad9832_remove(struct spi_device *spi)
{
	struct iio_dev *indio_dev = spi_get_drvdata(spi);
	struct ad9832_state *st = iio_priv(indio_dev);

	iio_device_unregister(indio_dev);
	if (!IS_ERR(st->reg)) {
		regulator_disable(st->reg);
		regulator_put(st->reg);
	}
	iio_free_device(indio_dev);

	return 0;
}

static const struct spi_device_id ad9832_id[] = {
	{"ad9832", 0},
	{"ad9835", 0},
	{}
};

static struct spi_driver ad9832_driver = {
	.driver = {
		.name	= "ad9832",
		.bus	= &spi_bus_type,
		.owner	= THIS_MODULE,
	},
	.probe		= ad9832_probe,
	.remove		= __devexit_p(ad9832_remove),
	.id_table	= ad9832_id,
};

static int __init ad9832_init(void)
{
	return spi_register_driver(&ad9832_driver);
}
module_init(ad9832_init);

static void __exit ad9832_exit(void)
{
	spi_unregister_driver(&ad9832_driver);
}
module_exit(ad9832_exit);

MODULE_AUTHOR("Michael Hennerich <hennerich@blackfin.uclinux.org>");
MODULE_DESCRIPTION("Analog Devices AD9832/AD9835 DDS");
MODULE_LICENSE("GPL v2");
MODULE_ALIAS("spi:ad9832");
Commit	Line	Data
4a8e6c33	1	/*
ea707584	2	* AD9832 SPI DDS driver
4a8e6c33	3	*
ea707584	4	* Copyright 2011 Analog Devices Inc.
4a8e6c33	5	*
ea707584	6	* Licensed under the GPL-2.
4a8e6c33	7	*/
ea707584	8
4a8e6c33	9	#include <linux/device.h>
ea707584	10	#include <linux/kernel.h>
4a8e6c33 CC	11	#include <linux/slab.h>
4a8e6c33 CC	12	#include <linux/sysfs.h>
ea707584 MH	13	#include <linux/spi/spi.h>
	14	#include <linux/regulator/consumer.h>
	15	#include <linux/err.h>
99c97852	16	#include <linux/module.h>
ea707584	17	#include <asm/div64.h>
4a8e6c33 CC	18
	19	#include "../iio.h"
	20	#include "../sysfs.h"
ea707584	21	#include "dds.h"
4a8e6c33	22
ea707584	23	#include "ad9832.h"
4a8e6c33	24
ea707584	25	static unsigned long ad9832_calc_freqreg(unsigned long mclk, unsigned long fout)
4a8e6c33	26	{
ea707584 MH	27	unsigned long long freqreg = (u64) fout *
	28	(u64) ((u64) 1L << AD9832_FREQ_BITS);
	29	do_div(freqreg, mclk);
	30	return freqreg;
	31	}
4a8e6c33	32
ea707584 MH	33	static int ad9832_write_frequency(struct ad9832_state *st,
	34	unsigned addr, unsigned long fout)
	35	{
	36	unsigned long regval;
	37
	38	if (fout > (st->mclk / 2))
	39	return -EINVAL;
	40
	41	regval = ad9832_calc_freqreg(st->mclk, fout);
	42
	43	st->freq_data[0] = cpu_to_be16((AD9832_CMD_FRE8BITSW << CMD_SHIFT) \|
	44	(addr << ADD_SHIFT) \|
	45	((regval >> 24) & 0xFF));
	46	st->freq_data[1] = cpu_to_be16((AD9832_CMD_FRE16BITSW << CMD_SHIFT) \|
	47	((addr - 1) << ADD_SHIFT) \|
	48	((regval >> 16) & 0xFF));
	49	st->freq_data[2] = cpu_to_be16((AD9832_CMD_FRE8BITSW << CMD_SHIFT) \|
	50	((addr - 2) << ADD_SHIFT) \|
	51	((regval >> 8) & 0xFF));
	52	st->freq_data[3] = cpu_to_be16((AD9832_CMD_FRE16BITSW << CMD_SHIFT) \|
	53	((addr - 3) << ADD_SHIFT) \|
	54	((regval >> 0) & 0xFF));
	55
	56	return spi_sync(st->spi, &st->freq_msg);;
4a8e6c33 CC	57	}
4a8e6c33 CC	58
ea707584 MH	59	static int ad9832_write_phase(struct ad9832_state *st,
	60	unsigned long addr, unsigned long phase)
	61	{
	62	if (phase > (1 << AD9832_PHASE_BITS))
	63	return -EINVAL;
4a8e6c33	64
ea707584 MH	65	st->phase_data[0] = cpu_to_be16((AD9832_CMD_PHA8BITSW << CMD_SHIFT) \|
	66	(addr << ADD_SHIFT) \|
	67	((phase >> 8) & 0xFF));
	68	st->phase_data[1] = cpu_to_be16((AD9832_CMD_PHA16BITSW << CMD_SHIFT) \|
	69	((addr - 1) << ADD_SHIFT) \|
	70	(phase & 0xFF));
4a8e6c33	71
ea707584 MH	72	return spi_sync(st->spi, &st->phase_msg);
ea707584 MH	73	}
4a8e6c33	74
ea707584 MH	75	static ssize_t ad9832_write(struct device *dev,
	76	struct device_attribute *attr,
	77	const char *buf,
	78	size_t len)
4a8e6c33	79	{
638e59fc JC	80	struct iio_dev *indio_dev = dev_get_drvdata(dev);
638e59fc JC	81	struct ad9832_state *st = iio_priv(indio_dev);
ea707584	82	struct iio_dev_attr *this_attr = to_iio_dev_attr(attr);
4a8e6c33	83	int ret;
ea707584	84	long val;
4a8e6c33	85
ea707584	86	ret = strict_strtoul(buf, 10, &val);
4a8e6c33 CC	87	if (ret)
	88	goto error_ret;
	89
638e59fc	90	mutex_lock(&indio_dev->mlock);
ea707584 MH	91	switch (this_attr->address) {
	92	case AD9832_FREQ0HM:
	93	case AD9832_FREQ1HM:
	94	ret = ad9832_write_frequency(st, this_attr->address, val);
	95	break;
	96	case AD9832_PHASE0H:
	97	case AD9832_PHASE1H:
	98	case AD9832_PHASE2H:
	99	case AD9832_PHASE3H:
	100	ret = ad9832_write_phase(st, this_attr->address, val);
	101	break;
	102	case AD9832_PINCTRL_EN:
	103	if (val)
	104	st->ctrl_ss &= ~AD9832_SELSRC;
	105	else
	106	st->ctrl_ss \|= AD9832_SELSRC;
	107	st->data = cpu_to_be16((AD9832_CMD_SYNCSELSRC << CMD_SHIFT) \|
	108	st->ctrl_ss);
	109	ret = spi_sync(st->spi, &st->msg);
	110	break;
	111	case AD9832_FREQ_SYM:
	112	if (val == 1)
	113	st->ctrl_fp \|= AD9832_FREQ;
	114	else if (val == 0)
	115	st->ctrl_fp &= ~AD9832_FREQ;
	116	else {
	117	ret = -EINVAL;
	118	break;
	119	}
	120	st->data = cpu_to_be16((AD9832_CMD_FPSELECT << CMD_SHIFT) \|
	121	st->ctrl_fp);
	122	ret = spi_sync(st->spi, &st->msg);
	123	break;
	124	case AD9832_PHASE_SYM:
	125	if (val < 0 \|\| val > 3) {
	126	ret = -EINVAL;
	127	break;
	128	}
	129
	130	st->ctrl_fp &= ~AD9832_PHASE(3);
	131	st->ctrl_fp \|= AD9832_PHASE(val);
	132
	133	st->data = cpu_to_be16((AD9832_CMD_FPSELECT << CMD_SHIFT) \|
	134	st->ctrl_fp);
	135	ret = spi_sync(st->spi, &st->msg);
	136	break;
	137	case AD9832_OUTPUT_EN:
	138	if (val)
	139	st->ctrl_src &= ~(AD9832_RESET \| AD9832_SLEEP \|
	140	AD9832_CLR);
	141	else
	142	st->ctrl_src \|= AD9832_RESET;
	143
	144	st->data = cpu_to_be16((AD9832_CMD_SLEEPRESCLR << CMD_SHIFT) \|
	145	st->ctrl_src);
	146	ret = spi_sync(st->spi, &st->msg);
	147	break;
	148	default:
	149	ret = -ENODEV;
	150	}
638e59fc	151	mutex_unlock(&indio_dev->mlock);
4a8e6c33	152
ea707584 MH	153	error_ret:
	154	return ret ? ret : len;
	155	}
4a8e6c33	156
ea707584 MH	157	/**
	158	* see dds.h for further information
	159	*/
4a8e6c33	160
ea707584 MH	161	static IIO_DEV_ATTR_FREQ(0, 0, S_IWUSR, NULL, ad9832_write, AD9832_FREQ0HM);
	162	static IIO_DEV_ATTR_FREQ(0, 1, S_IWUSR, NULL, ad9832_write, AD9832_FREQ1HM);
	163	static IIO_DEV_ATTR_FREQSYMBOL(0, S_IWUSR, NULL, ad9832_write, AD9832_FREQ_SYM);
	164	static IIO_CONST_ATTR_FREQ_SCALE(0, "1"); /* 1Hz */
4a8e6c33	165
ea707584 MH	166	static IIO_DEV_ATTR_PHASE(0, 0, S_IWUSR, NULL, ad9832_write, AD9832_PHASE0H);
	167	static IIO_DEV_ATTR_PHASE(0, 1, S_IWUSR, NULL, ad9832_write, AD9832_PHASE1H);
	168	static IIO_DEV_ATTR_PHASE(0, 2, S_IWUSR, NULL, ad9832_write, AD9832_PHASE2H);
	169	static IIO_DEV_ATTR_PHASE(0, 3, S_IWUSR, NULL, ad9832_write, AD9832_PHASE3H);
	170	static IIO_DEV_ATTR_PHASESYMBOL(0, S_IWUSR, NULL,
	171	ad9832_write, AD9832_PHASE_SYM);
	172	static IIO_CONST_ATTR_PHASE_SCALE(0, "0.0015339808"); /* 2PI/2^12 rad*/
4a8e6c33	173
ea707584 MH	174	static IIO_DEV_ATTR_PINCONTROL_EN(0, S_IWUSR, NULL,
	175	ad9832_write, AD9832_PINCTRL_EN);
	176	static IIO_DEV_ATTR_OUT_ENABLE(0, S_IWUSR, NULL,
	177	ad9832_write, AD9832_OUTPUT_EN);
4a8e6c33	178
ea707584 MH	179	static struct attribute *ad9832_attributes[] = {
	180	&iio_dev_attr_dds0_freq0.dev_attr.attr,
	181	&iio_dev_attr_dds0_freq1.dev_attr.attr,
	182	&iio_const_attr_dds0_freq_scale.dev_attr.attr,
	183	&iio_dev_attr_dds0_phase0.dev_attr.attr,
	184	&iio_dev_attr_dds0_phase1.dev_attr.attr,
	185	&iio_dev_attr_dds0_phase2.dev_attr.attr,
	186	&iio_dev_attr_dds0_phase3.dev_attr.attr,
	187	&iio_const_attr_dds0_phase_scale.dev_attr.attr,
	188	&iio_dev_attr_dds0_pincontrol_en.dev_attr.attr,
	189	&iio_dev_attr_dds0_freqsymbol.dev_attr.attr,
	190	&iio_dev_attr_dds0_phasesymbol.dev_attr.attr,
	191	&iio_dev_attr_dds0_out_enable.dev_attr.attr,
ea707584 MH	192	NULL,
ea707584 MH	193	};
4a8e6c33	194
ea707584 MH	195	static const struct attribute_group ad9832_attribute_group = {
	196	.attrs = ad9832_attributes,
	197	};
4a8e6c33	198
6fe8135f JC	199	static const struct iio_info ad9832_info = {
	200	.attrs = &ad9832_attribute_group,
	201	.driver_module = THIS_MODULE,
	202	};
	203
4a8e6c33 CC	204	static int __devinit ad9832_probe(struct spi_device *spi)
4a8e6c33 CC	205	{
ea707584	206	struct ad9832_platform_data *pdata = spi->dev.platform_data;
39f3b32e	207	struct iio_dev *indio_dev;
4a8e6c33	208	struct ad9832_state *st;
39f3b32e	209	struct regulator *reg;
ea707584 MH	210	int ret;
	211
	212	if (!pdata) {
	213	dev_dbg(&spi->dev, "no platform data?\n");
	214	return -ENODEV;
	215	}
4a8e6c33	216
39f3b32e JC	217	reg = regulator_get(&spi->dev, "vcc");
	218	if (!IS_ERR(reg)) {
	219	ret = regulator_enable(reg);
ea707584 MH	220	if (ret)
	221	goto error_put_reg;
	222	}
	223
39f3b32e JC	224	indio_dev = iio_allocate_device(sizeof(*st));
39f3b32e JC	225	if (indio_dev == NULL) {
4a8e6c33	226	ret = -ENOMEM;
ea707584	227	goto error_disable_reg;
4a8e6c33	228	}
39f3b32e JC	229	spi_set_drvdata(spi, indio_dev);
	230	st = iio_priv(indio_dev);
	231	st->reg = reg;
	232	st->mclk = pdata->mclk;
	233	st->spi = spi;
4a8e6c33	234
39f3b32e JC	235	indio_dev->dev.parent = &spi->dev;
	236	indio_dev->name = spi_get_device_id(spi)->name;
	237	indio_dev->info = &ad9832_info;
	238	indio_dev->modes = INDIO_DIRECT_MODE;
ea707584 MH	239
	240	/* Setup default messages */
	241
	242	st->xfer.tx_buf = &st->data;
	243	st->xfer.len = 2;
	244
	245	spi_message_init(&st->msg);
	246	spi_message_add_tail(&st->xfer, &st->msg);
	247
	248	st->freq_xfer[0].tx_buf = &st->freq_data[0];
	249	st->freq_xfer[0].len = 2;
	250	st->freq_xfer[0].cs_change = 1;
	251	st->freq_xfer[1].tx_buf = &st->freq_data[1];
	252	st->freq_xfer[1].len = 2;
	253	st->freq_xfer[1].cs_change = 1;
	254	st->freq_xfer[2].tx_buf = &st->freq_data[2];
	255	st->freq_xfer[2].len = 2;
	256	st->freq_xfer[2].cs_change = 1;
	257	st->freq_xfer[3].tx_buf = &st->freq_data[3];
	258	st->freq_xfer[3].len = 2;
	259
	260	spi_message_init(&st->freq_msg);
	261	spi_message_add_tail(&st->freq_xfer[0], &st->freq_msg);
	262	spi_message_add_tail(&st->freq_xfer[1], &st->freq_msg);
	263	spi_message_add_tail(&st->freq_xfer[2], &st->freq_msg);
	264	spi_message_add_tail(&st->freq_xfer[3], &st->freq_msg);
	265
	266	st->phase_xfer[0].tx_buf = &st->phase_data[0];
	267	st->phase_xfer[0].len = 2;
	268	st->phase_xfer[0].cs_change = 1;
	269	st->phase_xfer[1].tx_buf = &st->phase_data[1];
	270	st->phase_xfer[1].len = 2;
	271
	272	spi_message_init(&st->phase_msg);
	273	spi_message_add_tail(&st->phase_xfer[0], &st->phase_msg);
	274	spi_message_add_tail(&st->phase_xfer[1], &st->phase_msg);
	275
	276	st->ctrl_src = AD9832_SLEEP \| AD9832_RESET \| AD9832_CLR;
	277	st->data = cpu_to_be16((AD9832_CMD_SLEEPRESCLR << CMD_SHIFT) \|
	278	st->ctrl_src);
	279	ret = spi_sync(st->spi, &st->msg);
	280	if (ret) {
	281	dev_err(&spi->dev, "device init failed\n");
	282	goto error_free_device;
	283	}
	284
	285	ret = ad9832_write_frequency(st, AD9832_FREQ0HM, pdata->freq0);
	286	if (ret)
	287	goto error_free_device;
	288
	289	ret = ad9832_write_frequency(st, AD9832_FREQ1HM, pdata->freq1);
	290	if (ret)
	291	goto error_free_device;
	292
	293	ret = ad9832_write_phase(st, AD9832_PHASE0H, pdata->phase0);
	294	if (ret)
	295	goto error_free_device;
	296
	297	ret = ad9832_write_phase(st, AD9832_PHASE1H, pdata->phase1);
	298	if (ret)
	299	goto error_free_device;
4a8e6c33	300
ea707584	301	ret = ad9832_write_phase(st, AD9832_PHASE2H, pdata->phase2);
4a8e6c33	302	if (ret)
ea707584 MH	303	goto error_free_device;
	304
	305	ret = ad9832_write_phase(st, AD9832_PHASE3H, pdata->phase3);
	306	if (ret)
	307	goto error_free_device;
	308
39f3b32e	309	ret = iio_device_register(indio_dev);
ea707584 MH	310	if (ret)
	311	goto error_free_device;
	312
4a8e6c33 CC	313	return 0;
4a8e6c33 CC	314
ea707584	315	error_free_device:
39f3b32e	316	iio_free_device(indio_dev);
ea707584	317	error_disable_reg:
39f3b32e JC	318	if (!IS_ERR(reg))
39f3b32e JC	319	regulator_disable(reg);
ea707584	320	error_put_reg:
39f3b32e JC	321	if (!IS_ERR(reg))
	322	regulator_put(reg);
	323
4a8e6c33 CC	324	return ret;
	325	}
	326
	327	static int __devexit ad9832_remove(struct spi_device *spi)
	328	{
39f3b32e JC	329	struct iio_dev *indio_dev = spi_get_drvdata(spi);
39f3b32e JC	330	struct ad9832_state *st = iio_priv(indio_dev);
39f3b32e JC	331
39f3b32e JC	332	iio_device_unregister(indio_dev);
d2fffd6c JC	333	if (!IS_ERR(st->reg)) {
	334	regulator_disable(st->reg);
	335	regulator_put(st->reg);
ea707584	336	}
d2fffd6c JC	337	iio_free_device(indio_dev);
d2fffd6c JC	338
4a8e6c33 CC	339	return 0;
	340	}
	341
ea707584 MH	342	static const struct spi_device_id ad9832_id[] = {
	343	{"ad9832", 0},
	344	{"ad9835", 0},
	345	{}
	346	};
	347
4a8e6c33 CC	348	static struct spi_driver ad9832_driver = {
4a8e6c33 CC	349	.driver = {
ea707584 MH	350	.name = "ad9832",
	351	.bus = &spi_bus_type,
	352	.owner = THIS_MODULE,
4a8e6c33	353	},
ea707584 MH	354	.probe = ad9832_probe,
	355	.remove = __devexit_p(ad9832_remove),
	356	.id_table = ad9832_id,
4a8e6c33 CC	357	};
4a8e6c33 CC	358
ea707584	359	static int __init ad9832_init(void)
4a8e6c33 CC	360	{
	361	return spi_register_driver(&ad9832_driver);
	362	}
ea707584	363	module_init(ad9832_init);
4a8e6c33	364
ea707584	365	static void __exit ad9832_exit(void)
4a8e6c33 CC	366	{
	367	spi_unregister_driver(&ad9832_driver);
	368	}
ea707584	369	module_exit(ad9832_exit);
4a8e6c33	370
ea707584 MH	371	MODULE_AUTHOR("Michael Hennerich <hennerich@blackfin.uclinux.org>");
ea707584 MH	372	MODULE_DESCRIPTION("Analog Devices AD9832/AD9835 DDS");
4a8e6c33	373	MODULE_LICENSE("GPL v2");
ea707584	374	MODULE_ALIAS("spi:ad9832");