projects / deliverable / linux.git / blame
| Commit | Line | Data |
|---|---|---|
| faa4fd2a | 1 | /* |
| dcae5dac HV |
2 | * Copyright (C) 2010-2013 Bluecherry, LLC <http://www.bluecherrydvr.com> |
| 3 | * | |
| 4 | * Original author: | |
| 5 | * Ben Collins <bcollins@ubuntu.com> | |
| 6 | * | |
| 7 | * Additional work by: | |
| 8 | * John Brooks <john.brooks@bluecherry.net> | |
| faa4fd2a BC |
9 | * |
| 10 | * This program is free software; you can redistribute it and/or modify | |
| 11 | * it under the terms of the GNU General Public License as published by | |
| 12 | * the Free Software Foundation; either version 2 of the License, or | |
| 13 | * (at your option) any later version. | |
| 14 | * | |
| 15 | * This program is distributed in the hope that it will be useful, | |
| 16 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
| 17 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
| 18 | * GNU General Public License for more details. | |
| faa4fd2a BC |
19 | */ |
| 20 | ||
| decebabf KH |
21 | #ifndef __SOLO6X10_REGISTERS_H |
| 22 | #define __SOLO6X10_REGISTERS_H | |
| faa4fd2a | 23 | |
| dad7fab9 | 24 | #include "solo6x10-offsets.h" |
| faa4fd2a | 25 | |
| dcae5dac | 26 | /* Global 6010 system configuration */ |
| faa4fd2a | 27 | #define SOLO_SYS_CFG 0x0000 |
| dcae5dac HV |
28 | #define SOLO_SYS_CFG_FOUT_EN 0x00000001 |
| 29 | #define SOLO_SYS_CFG_PLL_BYPASS 0x00000002 | |
| 30 | #define SOLO_SYS_CFG_PLL_PWDN 0x00000004 | |
| 31 | #define SOLO_SYS_CFG_OUTDIV(__n) (((__n) & 0x003) << 3) | |
| 32 | #define SOLO_SYS_CFG_FEEDBACKDIV(__n) (((__n) & 0x1ff) << 5) | |
| 33 | #define SOLO_SYS_CFG_INPUTDIV(__n) (((__n) & 0x01f) << 14) | |
| faa4fd2a BC |
34 | #define SOLO_SYS_CFG_CLOCK_DIV 0x00080000 |
| 35 | #define SOLO_SYS_CFG_NCLK_DELAY(__n) (((__n) & 0x003) << 24) | |
| 36 | #define SOLO_SYS_CFG_PCLK_DELAY(__n) (((__n) & 0x00f) << 26) | |
| dcae5dac | 37 | #define SOLO_SYS_CFG_SDRAM64BIT 0x40000000 |
| faa4fd2a BC |
38 | #define SOLO_SYS_CFG_RESET 0x80000000 |
| 39 | ||
| 40 | #define SOLO_DMA_CTRL 0x0004 | |
| 41 | #define SOLO_DMA_CTRL_REFRESH_CYCLE(n) ((n)<<8) | |
| 42 | /* 0=16/32MB, 1=32/64MB, 2=64/128MB, 3=128/256MB */ | |
| 43 | #define SOLO_DMA_CTRL_SDRAM_SIZE(n) ((n)<<6) | |
| 44 | #define SOLO_DMA_CTRL_SDRAM_CLK_INVERT (1<<5) | |
| 45 | #define SOLO_DMA_CTRL_STROBE_SELECT (1<<4) | |
| 46 | #define SOLO_DMA_CTRL_READ_DATA_SELECT (1<<3) | |
| 47 | #define SOLO_DMA_CTRL_READ_CLK_SELECT (1<<2) | |
| 48 | #define SOLO_DMA_CTRL_LATENCY(n) ((n)<<0) | |
| dcae5dac HV |
49 | |
| 50 | /* Some things we set in this are undocumented. Why Softlogic?!?! */ | |
| 51 | #define SOLO_DMA_CTRL1 0x0008 | |
| faa4fd2a BC |
52 | |
| 53 | #define SOLO_SYS_VCLK 0x000C | |
| 54 | #define SOLO_VCLK_INVERT (1<<22) | |
| 55 | /* 0=sys_clk/4, 1=sys_clk/2, 2=clk_in/2 of system input */ | |
| 56 | #define SOLO_VCLK_SELECT(n) ((n)<<20) | |
| 57 | #define SOLO_VCLK_VIN1415_DELAY(n) ((n)<<14) | |
| 58 | #define SOLO_VCLK_VIN1213_DELAY(n) ((n)<<12) | |
| 59 | #define SOLO_VCLK_VIN1011_DELAY(n) ((n)<<10) | |
| 60 | #define SOLO_VCLK_VIN0809_DELAY(n) ((n)<<8) | |
| 61 | #define SOLO_VCLK_VIN0607_DELAY(n) ((n)<<6) | |
| 62 | #define SOLO_VCLK_VIN0405_DELAY(n) ((n)<<4) | |
| 63 | #define SOLO_VCLK_VIN0203_DELAY(n) ((n)<<2) | |
| 64 | #define SOLO_VCLK_VIN0001_DELAY(n) ((n)<<0) | |
| 65 | ||
| 66 | #define SOLO_IRQ_STAT 0x0010 | |
| dcae5dac | 67 | #define SOLO_IRQ_MASK 0x0014 |
| faa4fd2a BC |
68 | #define SOLO_IRQ_P2M(n) (1<<((n)+17)) |
| 69 | #define SOLO_IRQ_GPIO (1<<16) | |
| 70 | #define SOLO_IRQ_VIDEO_LOSS (1<<15) | |
| 71 | #define SOLO_IRQ_VIDEO_IN (1<<14) | |
| 72 | #define SOLO_IRQ_MOTION (1<<13) | |
| 73 | #define SOLO_IRQ_ATA_CMD (1<<12) | |
| 74 | #define SOLO_IRQ_ATA_DIR (1<<11) | |
| 75 | #define SOLO_IRQ_PCI_ERR (1<<10) | |
| 76 | #define SOLO_IRQ_PS2_1 (1<<9) | |
| 77 | #define SOLO_IRQ_PS2_0 (1<<8) | |
| 78 | #define SOLO_IRQ_SPI (1<<7) | |
| 79 | #define SOLO_IRQ_IIC (1<<6) | |
| 80 | #define SOLO_IRQ_UART(n) (1<<((n) + 4)) | |
| 81 | #define SOLO_IRQ_G723 (1<<3) | |
| 82 | #define SOLO_IRQ_DECODER (1<<1) | |
| 83 | #define SOLO_IRQ_ENCODER (1<<0) | |
| 84 | ||
| 85 | #define SOLO_CHIP_OPTION 0x001C | |
| 86 | #define SOLO_CHIP_ID_MASK 0x00000007 | |
| 87 | ||
| dcae5dac | 88 | #define SOLO_PLL_CONFIG 0x0020 /* 6110 Only */ |
| 908113d8 | 89 | |
| faa4fd2a BC |
90 | #define SOLO_EEPROM_CTRL 0x0060 |
| 91 | #define SOLO_EEPROM_ACCESS_EN (1<<7) | |
| 92 | #define SOLO_EEPROM_CS (1<<3) | |
| 93 | #define SOLO_EEPROM_CLK (1<<2) | |
| 94 | #define SOLO_EEPROM_DO (1<<1) | |
| 95 | #define SOLO_EEPROM_DI (1<<0) | |
| dcae5dac | 96 | #define SOLO_EEPROM_ENABLE (SOLO_EEPROM_ACCESS_EN | SOLO_EEPROM_CS) |
| faa4fd2a BC |
97 | |
| 98 | #define SOLO_PCI_ERR 0x0070 | |
| 99 | #define SOLO_PCI_ERR_FATAL 0x00000001 | |
| 100 | #define SOLO_PCI_ERR_PARITY 0x00000002 | |
| 101 | #define SOLO_PCI_ERR_TARGET 0x00000004 | |
| 102 | #define SOLO_PCI_ERR_TIMEOUT 0x00000008 | |
| 103 | #define SOLO_PCI_ERR_P2M 0x00000010 | |
| 104 | #define SOLO_PCI_ERR_ATA 0x00000020 | |
| 105 | #define SOLO_PCI_ERR_P2M_DESC 0x00000040 | |
| 106 | #define SOLO_PCI_ERR_FSM0(__s) (((__s) >> 16) & 0x0f) | |
| 107 | #define SOLO_PCI_ERR_FSM1(__s) (((__s) >> 20) & 0x0f) | |
| 108 | #define SOLO_PCI_ERR_FSM2(__s) (((__s) >> 24) & 0x1f) | |
| 109 | ||
| 110 | #define SOLO_P2M_BASE 0x0080 | |
| 111 | ||
| 112 | #define SOLO_P2M_CONFIG(n) (0x0080 + ((n)*0x20)) | |
| 113 | #define SOLO_P2M_DMA_INTERVAL(n) ((n)<<6)/* N*32 clocks */ | |
| 114 | #define SOLO_P2M_CSC_BYTE_REORDER (1<<5) /* BGR -> RGB */ | |
| 115 | /* 0:r=[14:10] g=[9:5] b=[4:0], 1:r=[15:11] g=[10:5] b=[4:0] */ | |
| 116 | #define SOLO_P2M_CSC_16BIT_565 (1<<4) | |
| 117 | #define SOLO_P2M_UV_SWAP (1<<3) | |
| 118 | #define SOLO_P2M_PCI_MASTER_MODE (1<<2) | |
| 119 | #define SOLO_P2M_DESC_INTR_OPT (1<<1) /* 1:Empty, 0:Each */ | |
| 120 | #define SOLO_P2M_DESC_MODE (1<<0) | |
| 121 | ||
| 122 | #define SOLO_P2M_DES_ADR(n) (0x0084 + ((n)*0x20)) | |
| 123 | ||
| 124 | #define SOLO_P2M_DESC_ID(n) (0x0088 + ((n)*0x20)) | |
| 125 | #define SOLO_P2M_UPDATE_ID(n) ((n)<<0) | |
| 126 | ||
| 127 | #define SOLO_P2M_STATUS(n) (0x008C + ((n)*0x20)) | |
| 128 | #define SOLO_P2M_COMMAND_DONE (1<<8) | |
| 129 | #define SOLO_P2M_CURRENT_ID(stat) (0xff & (stat)) | |
| 130 | ||
| 131 | #define SOLO_P2M_CONTROL(n) (0x0090 + ((n)*0x20)) | |
| 132 | #define SOLO_P2M_PCI_INC(n) ((n)<<20) | |
| 133 | #define SOLO_P2M_REPEAT(n) ((n)<<10) | |
| 134 | /* 0:512, 1:256, 2:128, 3:64, 4:32, 5:128(2page) */ | |
| 135 | #define SOLO_P2M_BURST_SIZE(n) ((n)<<7) | |
| 136 | #define SOLO_P2M_BURST_512 0 | |
| 137 | #define SOLO_P2M_BURST_256 1 | |
| 138 | #define SOLO_P2M_BURST_128 2 | |
| 139 | #define SOLO_P2M_BURST_64 3 | |
| 140 | #define SOLO_P2M_BURST_32 4 | |
| 141 | #define SOLO_P2M_CSC_16BIT (1<<6) /* 0:24bit, 1:16bit */ | |
| 142 | /* 0:Y[0]<-0(OFF), 1:Y[0]<-1(ON), 2:Y[0]<-G[0], 3:Y[0]<-Bit[15] */ | |
| 143 | #define SOLO_P2M_ALPHA_MODE(n) ((n)<<4) | |
| 144 | #define SOLO_P2M_CSC_ON (1<<3) | |
| 145 | #define SOLO_P2M_INTERRUPT_REQ (1<<2) | |
| 146 | #define SOLO_P2M_WRITE (1<<1) | |
| 147 | #define SOLO_P2M_TRANS_ON (1<<0) | |
| 148 | ||
| 149 | #define SOLO_P2M_EXT_CFG(n) (0x0094 + ((n)*0x20)) | |
| 150 | #define SOLO_P2M_EXT_INC(n) ((n)<<20) | |
| 151 | #define SOLO_P2M_COPY_SIZE(n) ((n)<<0) | |
| 152 | ||
| 153 | #define SOLO_P2M_TAR_ADR(n) (0x0098 + ((n)*0x20)) | |
| 154 | ||
| 155 | #define SOLO_P2M_EXT_ADR(n) (0x009C + ((n)*0x20)) | |
| 156 | ||
| 157 | #define SOLO_P2M_BUFFER(i) (0x2000 + ((i)*4)) | |
| 158 | ||
| 159 | #define SOLO_VI_CH_SWITCH_0 0x0100 | |
| 160 | #define SOLO_VI_CH_SWITCH_1 0x0104 | |
| 161 | #define SOLO_VI_CH_SWITCH_2 0x0108 | |
| 162 | ||
| 163 | #define SOLO_VI_CH_ENA 0x010C | |
| 164 | #define SOLO_VI_CH_FORMAT 0x0110 | |
| 165 | #define SOLO_VI_FD_SEL_MASK(n) ((n)<<16) | |
| 166 | #define SOLO_VI_PROG_MASK(n) ((n)<<0) | |
| 167 | ||
| 168 | #define SOLO_VI_FMT_CFG 0x0114 | |
| 169 | #define SOLO_VI_FMT_CHECK_VCOUNT (1<<31) | |
| 170 | #define SOLO_VI_FMT_CHECK_HCOUNT (1<<30) | |
| 171 | #define SOLO_VI_FMT_TEST_SIGNAL (1<<28) | |
| 172 | ||
| 173 | #define SOLO_VI_PAGE_SW 0x0118 | |
| 174 | #define SOLO_FI_INV_DISP_LIVE(n) ((n)<<8) | |
| 175 | #define SOLO_FI_INV_DISP_OUT(n) ((n)<<7) | |
| 176 | #define SOLO_DISP_SYNC_FI(n) ((n)<<6) | |
| 177 | #define SOLO_PIP_PAGE_ADD(n) ((n)<<3) | |
| 178 | #define SOLO_NORMAL_PAGE_ADD(n) ((n)<<0) | |
| 179 | ||
| 180 | #define SOLO_VI_ACT_I_P 0x011C | |
| 181 | #define SOLO_VI_ACT_I_S 0x0120 | |
| 182 | #define SOLO_VI_ACT_P 0x0124 | |
| 183 | #define SOLO_VI_FI_INVERT (1<<31) | |
| 184 | #define SOLO_VI_H_START(n) ((n)<<21) | |
| 185 | #define SOLO_VI_V_START(n) ((n)<<11) | |
| 186 | #define SOLO_VI_V_STOP(n) ((n)<<0) | |
| 187 | ||
| 188 | #define SOLO_VI_STATUS0 0x0128 | |
| 189 | #define SOLO_VI_STATUS0_PAGE(__n) ((__n) & 0x07) | |
| 190 | #define SOLO_VI_STATUS1 0x012C | |
| 191 | ||
| 192 | /* XXX: Might be better off in kernel level disp.h */ | |
| 193 | #define DISP_PAGE(stat) ((stat) & 0x07) | |
| 194 | ||
| 195 | #define SOLO_VI_PB_CONFIG 0x0130 | |
| 196 | #define SOLO_VI_PB_USER_MODE (1<<1) | |
| 197 | #define SOLO_VI_PB_PAL (1<<0) | |
| 198 | #define SOLO_VI_PB_RANGE_HV 0x0134 | |
| 199 | #define SOLO_VI_PB_HSIZE(h) ((h)<<12) | |
| 200 | #define SOLO_VI_PB_VSIZE(v) ((v)<<0) | |
| 201 | #define SOLO_VI_PB_ACT_H 0x0138 | |
| 202 | #define SOLO_VI_PB_HSTART(n) ((n)<<12) | |
| 203 | #define SOLO_VI_PB_HSTOP(n) ((n)<<0) | |
| 204 | #define SOLO_VI_PB_ACT_V 0x013C | |
| 205 | #define SOLO_VI_PB_VSTART(n) ((n)<<12) | |
| 206 | #define SOLO_VI_PB_VSTOP(n) ((n)<<0) | |
| 207 | ||
| 208 | #define SOLO_VI_MOSAIC(ch) (0x0140 + ((ch)*4)) | |
| 209 | #define SOLO_VI_MOSAIC_SX(x) ((x)<<24) | |
| 210 | #define SOLO_VI_MOSAIC_EX(x) ((x)<<16) | |
| 211 | #define SOLO_VI_MOSAIC_SY(x) ((x)<<8) | |
| 212 | #define SOLO_VI_MOSAIC_EY(x) ((x)<<0) | |
| 213 | ||
| 214 | #define SOLO_VI_WIN_CTRL0(ch) (0x0180 + ((ch)*4)) | |
| 215 | #define SOLO_VI_WIN_CTRL1(ch) (0x01C0 + ((ch)*4)) | |
| 216 | ||
| 217 | #define SOLO_VI_WIN_CHANNEL(n) ((n)<<28) | |
| 218 | ||
| 219 | #define SOLO_VI_WIN_PIP(n) ((n)<<27) | |
| 220 | #define SOLO_VI_WIN_SCALE(n) ((n)<<24) | |
| 221 | ||
| 222 | #define SOLO_VI_WIN_SX(x) ((x)<<12) | |
| 223 | #define SOLO_VI_WIN_EX(x) ((x)<<0) | |
| 224 | ||
| 225 | #define SOLO_VI_WIN_SY(x) ((x)<<12) | |
| 226 | #define SOLO_VI_WIN_EY(x) ((x)<<0) | |
| 227 | ||
| 228 | #define SOLO_VI_WIN_ON(ch) (0x0200 + ((ch)*4)) | |
| 229 | ||
| 230 | #define SOLO_VI_WIN_SW 0x0240 | |
| 231 | #define SOLO_VI_WIN_LIVE_AUTO_MUTE 0x0244 | |
| 232 | ||
| 233 | #define SOLO_VI_MOT_ADR 0x0260 | |
| 234 | #define SOLO_VI_MOTION_EN(mask) ((mask)<<16) | |
| 235 | #define SOLO_VI_MOT_CTRL 0x0264 | |
| 236 | #define SOLO_VI_MOTION_FRAME_COUNT(n) ((n)<<24) | |
| 237 | #define SOLO_VI_MOTION_SAMPLE_LENGTH(n) ((n)<<16) | |
| 238 | #define SOLO_VI_MOTION_INTR_START_STOP (1<<15) | |
| 239 | #define SOLO_VI_MOTION_FREEZE_DATA (1<<14) | |
| 240 | #define SOLO_VI_MOTION_SAMPLE_COUNT(n) ((n)<<0) | |
| 241 | #define SOLO_VI_MOT_CLEAR 0x0268 | |
| 242 | #define SOLO_VI_MOT_STATUS 0x026C | |
| 243 | #define SOLO_VI_MOTION_CNT(n) ((n)<<0) | |
| 244 | #define SOLO_VI_MOTION_BORDER 0x0270 | |
| 245 | #define SOLO_VI_MOTION_BAR 0x0274 | |
| 246 | #define SOLO_VI_MOTION_Y_SET (1<<29) | |
| 247 | #define SOLO_VI_MOTION_Y_ADD (1<<28) | |
| 248 | #define SOLO_VI_MOTION_CB_SET (1<<27) | |
| 249 | #define SOLO_VI_MOTION_CB_ADD (1<<26) | |
| 250 | #define SOLO_VI_MOTION_CR_SET (1<<25) | |
| 251 | #define SOLO_VI_MOTION_CR_ADD (1<<24) | |
| 252 | #define SOLO_VI_MOTION_Y_VALUE(v) ((v)<<16) | |
| 253 | #define SOLO_VI_MOTION_CB_VALUE(v) ((v)<<8) | |
| 254 | #define SOLO_VI_MOTION_CR_VALUE(v) ((v)<<0) | |
| 255 | ||
| 256 | #define SOLO_VO_FMT_ENC 0x0300 | |
| 257 | #define SOLO_VO_SCAN_MODE_PROGRESSIVE (1<<31) | |
| 258 | #define SOLO_VO_FMT_TYPE_PAL (1<<30) | |
| 259 | #define SOLO_VO_FMT_TYPE_NTSC 0 | |
| 260 | #define SOLO_VO_USER_SET (1<<29) | |
| 261 | ||
| 262 | #define SOLO_VO_FI_CHANGE (1<<20) | |
| 263 | #define SOLO_VO_USER_COLOR_SET_VSYNC (1<<19) | |
| 264 | #define SOLO_VO_USER_COLOR_SET_HSYNC (1<<18) | |
| dcae5dac HV |
265 | #define SOLO_VO_USER_COLOR_SET_NAH (1<<17) |
| 266 | #define SOLO_VO_USER_COLOR_SET_NAV (1<<16) | |
| faa4fd2a BC |
267 | #define SOLO_VO_NA_COLOR_Y(Y) ((Y)<<8) |
| 268 | #define SOLO_VO_NA_COLOR_CB(CB) (((CB)/16)<<4) | |
| 269 | #define SOLO_VO_NA_COLOR_CR(CR) (((CR)/16)<<0) | |
| 270 | ||
| 271 | #define SOLO_VO_ACT_H 0x0304 | |
| 272 | #define SOLO_VO_H_BLANK(n) ((n)<<22) | |
| 273 | #define SOLO_VO_H_START(n) ((n)<<11) | |
| 274 | #define SOLO_VO_H_STOP(n) ((n)<<0) | |
| 275 | ||
| 276 | #define SOLO_VO_ACT_V 0x0308 | |
| 277 | #define SOLO_VO_V_BLANK(n) ((n)<<22) | |
| 278 | #define SOLO_VO_V_START(n) ((n)<<11) | |
| 279 | #define SOLO_VO_V_STOP(n) ((n)<<0) | |
| 280 | ||
| 281 | #define SOLO_VO_RANGE_HV 0x030C | |
| 282 | #define SOLO_VO_SYNC_INVERT (1<<24) | |
| 283 | #define SOLO_VO_HSYNC_INVERT (1<<23) | |
| 284 | #define SOLO_VO_VSYNC_INVERT (1<<22) | |
| 285 | #define SOLO_VO_H_LEN(n) ((n)<<11) | |
| 286 | #define SOLO_VO_V_LEN(n) ((n)<<0) | |
| 287 | ||
| 288 | #define SOLO_VO_DISP_CTRL 0x0310 | |
| 289 | #define SOLO_VO_DISP_ON (1<<31) | |
| 290 | #define SOLO_VO_DISP_ERASE_COUNT(n) ((n&0xf)<<24) | |
| 291 | #define SOLO_VO_DISP_DOUBLE_SCAN (1<<22) | |
| 292 | #define SOLO_VO_DISP_SINGLE_PAGE (1<<21) | |
| 293 | #define SOLO_VO_DISP_BASE(n) (((n)>>16) & 0xffff) | |
| 294 | ||
| 295 | #define SOLO_VO_DISP_ERASE 0x0314 | |
| 296 | #define SOLO_VO_DISP_ERASE_ON (1<<0) | |
| 297 | ||
| 298 | #define SOLO_VO_ZOOM_CTRL 0x0318 | |
| 299 | #define SOLO_VO_ZOOM_VER_ON (1<<24) | |
| 300 | #define SOLO_VO_ZOOM_HOR_ON (1<<23) | |
| 301 | #define SOLO_VO_ZOOM_V_COMP (1<<22) | |
| 302 | #define SOLO_VO_ZOOM_SX(h) (((h)/2)<<11) | |
| 303 | #define SOLO_VO_ZOOM_SY(v) (((v)/2)<<0) | |
| 304 | ||
| 305 | #define SOLO_VO_FREEZE_CTRL 0x031C | |
| 306 | #define SOLO_VO_FREEZE_ON (1<<1) | |
| 307 | #define SOLO_VO_FREEZE_INTERPOLATION (1<<0) | |
| 308 | ||
| 309 | #define SOLO_VO_BKG_COLOR 0x0320 | |
| 310 | #define SOLO_BG_Y(y) ((y)<<16) | |
| 311 | #define SOLO_BG_U(u) ((u)<<8) | |
| 312 | #define SOLO_BG_V(v) ((v)<<0) | |
| 313 | ||
| 314 | #define SOLO_VO_DEINTERLACE 0x0324 | |
| 315 | #define SOLO_VO_DEINTERLACE_THRESHOLD(n) ((n)<<8) | |
| 316 | #define SOLO_VO_DEINTERLACE_EDGE_VALUE(n) ((n)<<0) | |
| 317 | ||
| 318 | #define SOLO_VO_BORDER_LINE_COLOR 0x0330 | |
| 319 | #define SOLO_VO_BORDER_FILL_COLOR 0x0334 | |
| 320 | #define SOLO_VO_BORDER_LINE_MASK 0x0338 | |
| 321 | #define SOLO_VO_BORDER_FILL_MASK 0x033c | |
| 322 | ||
| 323 | #define SOLO_VO_BORDER_X(n) (0x0340+((n)*4)) | |
| 324 | #define SOLO_VO_BORDER_Y(n) (0x0354+((n)*4)) | |
| 325 | ||
| 326 | #define SOLO_VO_CELL_EXT_SET 0x0368 | |
| 327 | #define SOLO_VO_CELL_EXT_START 0x036c | |
| 328 | #define SOLO_VO_CELL_EXT_STOP 0x0370 | |
| 329 | ||
| 330 | #define SOLO_VO_CELL_EXT_SET2 0x0374 | |
| 331 | #define SOLO_VO_CELL_EXT_START2 0x0378 | |
| 332 | #define SOLO_VO_CELL_EXT_STOP2 0x037c | |
| 333 | ||
| 334 | #define SOLO_VO_RECTANGLE_CTRL(n) (0x0368+((n)*12)) | |
| 335 | #define SOLO_VO_RECTANGLE_START(n) (0x036c+((n)*12)) | |
| 336 | #define SOLO_VO_RECTANGLE_STOP(n) (0x0370+((n)*12)) | |
| 337 | ||
| 338 | #define SOLO_VO_CURSOR_POS (0x0380) | |
| 339 | #define SOLO_VO_CURSOR_CLR (0x0384) | |
| 340 | #define SOLO_VO_CURSOR_CLR2 (0x0388) | |
| 341 | #define SOLO_VO_CURSOR_MASK(id) (0x0390+((id)*4)) | |
| 342 | ||
| 343 | #define SOLO_VO_EXPANSION(id) (0x0250+((id)*4)) | |
| 344 | ||
| 345 | #define SOLO_OSG_CONFIG 0x03E0 | |
| 346 | #define SOLO_VO_OSG_ON (1<<31) | |
| 347 | #define SOLO_VO_OSG_COLOR_MUTE (1<<28) | |
| 348 | #define SOLO_VO_OSG_ALPHA_RATE(n) ((n)<<22) | |
| 349 | #define SOLO_VO_OSG_ALPHA_BG_RATE(n) ((n)<<16) | |
| 350 | #define SOLO_VO_OSG_BASE(offset) (((offset)>>16)&0xffff) | |
| 351 | ||
| 352 | #define SOLO_OSG_ERASE 0x03E4 | |
| 353 | #define SOLO_OSG_ERASE_ON (0x80) | |
| 354 | #define SOLO_OSG_ERASE_OFF (0x00) | |
| 355 | ||
| 356 | #define SOLO_VO_OSG_BLINK 0x03E8 | |
| 357 | #define SOLO_VO_OSG_BLINK_ON (1<<1) | |
| 358 | #define SOLO_VO_OSG_BLINK_INTREVAL18 (1<<0) | |
| 359 | ||
| 360 | #define SOLO_CAP_BASE 0x0400 | |
| 361 | #define SOLO_CAP_MAX_PAGE(n) ((n)<<16) | |
| 362 | #define SOLO_CAP_BASE_ADDR(n) ((n)<<0) | |
| 363 | #define SOLO_CAP_BTW 0x0404 | |
| 364 | #define SOLO_CAP_PROG_BANDWIDTH(n) ((n)<<8) | |
| 365 | #define SOLO_CAP_MAX_BANDWIDTH(n) ((n)<<0) | |
| 366 | ||
| 367 | #define SOLO_DIM_SCALE1 0x0408 | |
| 368 | #define SOLO_DIM_SCALE2 0x040C | |
| 369 | #define SOLO_DIM_SCALE3 0x0410 | |
| 370 | #define SOLO_DIM_SCALE4 0x0414 | |
| 371 | #define SOLO_DIM_SCALE5 0x0418 | |
| 372 | #define SOLO_DIM_V_MB_NUM_FRAME(n) ((n)<<16) | |
| 373 | #define SOLO_DIM_V_MB_NUM_FIELD(n) ((n)<<8) | |
| 374 | #define SOLO_DIM_H_MB_NUM(n) ((n)<<0) | |
| 375 | ||
| 376 | #define SOLO_DIM_PROG 0x041C | |
| 377 | #define SOLO_CAP_STATUS 0x0420 | |
| 378 | ||
| 379 | #define SOLO_CAP_CH_SCALE(ch) (0x0440+((ch)*4)) | |
| 380 | #define SOLO_CAP_CH_COMP_ENA_E(ch) (0x0480+((ch)*4)) | |
| 381 | #define SOLO_CAP_CH_INTV(ch) (0x04C0+((ch)*4)) | |
| 382 | #define SOLO_CAP_CH_INTV_E(ch) (0x0500+((ch)*4)) | |
| 383 | ||
| 384 | ||
| 385 | #define SOLO_VE_CFG0 0x0610 | |
| 386 | #define SOLO_VE_TWO_PAGE_MODE (1<<31) | |
| 387 | #define SOLO_VE_INTR_CTRL(n) ((n)<<24) | |
| 388 | #define SOLO_VE_BLOCK_SIZE(n) ((n)<<16) | |
| 389 | #define SOLO_VE_BLOCK_BASE(n) ((n)<<0) | |
| 390 | ||
| 391 | #define SOLO_VE_CFG1 0x0614 | |
| dcae5dac | 392 | #define SOLO_VE_BYTE_ALIGN(n) ((n)<<24) |
| faa4fd2a BC |
393 | #define SOLO_VE_INSERT_INDEX (1<<18) |
| 394 | #define SOLO_VE_MOTION_MODE(n) ((n)<<16) | |
| 395 | #define SOLO_VE_MOTION_BASE(n) ((n)<<0) | |
| dcae5dac HV |
396 | #define SOLO_VE_MPEG_SIZE_H(n) ((n)<<28) /* 6110 Only */ |
| 397 | #define SOLO_VE_JPEG_SIZE_H(n) ((n)<<20) /* 6110 Only */ | |
| 398 | #define SOLO_VE_INSERT_INDEX_JPEG (1<<19) /* 6110 Only */ | |
| faa4fd2a BC |
399 | |
| 400 | #define SOLO_VE_WMRK_POLY 0x061C | |
| 401 | #define SOLO_VE_VMRK_INIT_KEY 0x0620 | |
| 402 | #define SOLO_VE_WMRK_STRL 0x0624 | |
| 403 | #define SOLO_VE_ENCRYP_POLY 0x0628 | |
| 404 | #define SOLO_VE_ENCRYP_INIT 0x062C | |
| 405 | #define SOLO_VE_ATTR 0x0630 | |
| 406 | #define SOLO_VE_LITTLE_ENDIAN (1<<31) | |
| 407 | #define SOLO_COMP_ATTR_RN (1<<30) | |
| 408 | #define SOLO_COMP_ATTR_FCODE(n) ((n)<<27) | |
| 409 | #define SOLO_COMP_TIME_INC(n) ((n)<<25) | |
| 410 | #define SOLO_COMP_TIME_WIDTH(n) ((n)<<21) | |
| 411 | #define SOLO_DCT_INTERVAL(n) ((n)<<16) | |
| dcae5dac | 412 | #define SOLO_VE_COMPT_MOT 0x0634 /* 6110 Only */ |
| faa4fd2a BC |
413 | |
| 414 | #define SOLO_VE_STATE(n) (0x0640+((n)*4)) | |
| faa4fd2a BC |
415 | |
| 416 | #define SOLO_VE_JPEG_QP_TBL 0x0670 | |
| 417 | #define SOLO_VE_JPEG_QP_CH_L 0x0674 | |
| 418 | #define SOLO_VE_JPEG_QP_CH_H 0x0678 | |
| 419 | #define SOLO_VE_JPEG_CFG 0x067C | |
| 420 | #define SOLO_VE_JPEG_CTRL 0x0680 | |
| dcae5dac HV |
421 | #define SOLO_VE_CODE_ENCRYPT 0x0684 /* 6110 Only */ |
| 422 | #define SOLO_VE_JPEG_CFG1 0x0688 /* 6110 Only */ | |
| 423 | #define SOLO_VE_WMRK_ENABLE 0x068C /* 6110 Only */ | |
| faa4fd2a BC |
424 | #define SOLO_VE_OSD_CH 0x0690 |
| 425 | #define SOLO_VE_OSD_BASE 0x0694 | |
| 426 | #define SOLO_VE_OSD_CLR 0x0698 | |
| 427 | #define SOLO_VE_OSD_OPT 0x069C | |
| dcae5dac HV |
428 | #define SOLO_VE_OSD_V_DOUBLE (1<<16) /* 6110 Only */ |
| 429 | #define SOLO_VE_OSD_H_SHADOW (1<<15) | |
| 430 | #define SOLO_VE_OSD_V_SHADOW (1<<14) | |
| 431 | #define SOLO_VE_OSD_H_OFFSET(n) ((n & 0x7f)<<7) | |
| 432 | #define SOLO_VE_OSD_V_OFFSET(n) (n & 0x7f) | |
| faa4fd2a BC |
433 | |
| 434 | #define SOLO_VE_CH_INTL(ch) (0x0700+((ch)*4)) | |
| dcae5dac | 435 | #define SOLO_VE_CH_MOT(ch) (0x0740+((ch)*4)) |
| faa4fd2a BC |
436 | #define SOLO_VE_CH_QP(ch) (0x0780+((ch)*4)) |
| 437 | #define SOLO_VE_CH_QP_E(ch) (0x07C0+((ch)*4)) | |
| 438 | #define SOLO_VE_CH_GOP(ch) (0x0800+((ch)*4)) | |
| 439 | #define SOLO_VE_CH_GOP_E(ch) (0x0840+((ch)*4)) | |
| 440 | #define SOLO_VE_CH_REF_BASE(ch) (0x0880+((ch)*4)) | |
| 441 | #define SOLO_VE_CH_REF_BASE_E(ch) (0x08C0+((ch)*4)) | |
| 442 | ||
| 443 | #define SOLO_VE_MPEG4_QUE(n) (0x0A00+((n)*8)) | |
| 444 | #define SOLO_VE_JPEG_QUE(n) (0x0A04+((n)*8)) | |
| 445 | ||
| 446 | #define SOLO_VD_CFG0 0x0900 | |
| dcae5dac | 447 | #define SOLO_VD_CFG_NO_WRITE_NO_WINDOW (1<<24) |
| faa4fd2a BC |
448 | #define SOLO_VD_CFG_BUSY_WIAT_CODE (1<<23) |
| 449 | #define SOLO_VD_CFG_BUSY_WIAT_REF (1<<22) | |
| 450 | #define SOLO_VD_CFG_BUSY_WIAT_RES (1<<21) | |
| 451 | #define SOLO_VD_CFG_BUSY_WIAT_MS (1<<20) | |
| 452 | #define SOLO_VD_CFG_SINGLE_MODE (1<<18) | |
| 453 | #define SOLO_VD_CFG_SCAL_MANUAL (1<<17) | |
| 454 | #define SOLO_VD_CFG_USER_PAGE_CTRL (1<<16) | |
| 455 | #define SOLO_VD_CFG_LITTLE_ENDIAN (1<<15) | |
| 456 | #define SOLO_VD_CFG_START_FI (1<<14) | |
| 457 | #define SOLO_VD_CFG_ERR_LOCK (1<<13) | |
| 458 | #define SOLO_VD_CFG_ERR_INT_ENA (1<<12) | |
| 459 | #define SOLO_VD_CFG_TIME_WIDTH(n) ((n)<<8) | |
| 460 | #define SOLO_VD_CFG_DCT_INTERVAL(n) ((n)<<0) | |
| 461 | ||
| 462 | #define SOLO_VD_CFG1 0x0904 | |
| 463 | ||
| 464 | #define SOLO_VD_DEINTERLACE 0x0908 | |
| 465 | #define SOLO_VD_DEINTERLACE_THRESHOLD(n) ((n)<<8) | |
| 466 | #define SOLO_VD_DEINTERLACE_EDGE_VALUE(n) ((n)<<0) | |
| 467 | ||
| 468 | #define SOLO_VD_CODE_ADR 0x090C | |
| 469 | ||
| 470 | #define SOLO_VD_CTRL 0x0910 | |
| 471 | #define SOLO_VD_OPER_ON (1<<31) | |
| 472 | #define SOLO_VD_MAX_ITEM(n) ((n)<<0) | |
| 473 | ||
| 474 | #define SOLO_VD_STATUS0 0x0920 | |
| 475 | #define SOLO_VD_STATUS0_INTR_ACK (1<<22) | |
| 476 | #define SOLO_VD_STATUS0_INTR_EMPTY (1<<21) | |
| 477 | #define SOLO_VD_STATUS0_INTR_ERR (1<<20) | |
| 478 | ||
| 479 | #define SOLO_VD_STATUS1 0x0924 | |
| 480 | ||
| 481 | #define SOLO_VD_IDX0 0x0930 | |
| 482 | #define SOLO_VD_IDX_INTERLACE (1<<30) | |
| 483 | #define SOLO_VD_IDX_CHANNEL(n) ((n)<<24) | |
| 484 | #define SOLO_VD_IDX_SIZE(n) ((n)<<0) | |
| 485 | ||
| 486 | #define SOLO_VD_IDX1 0x0934 | |
| 487 | #define SOLO_VD_IDX_SRC_SCALE(n) ((n)<<28) | |
| 488 | #define SOLO_VD_IDX_WINDOW(n) ((n)<<24) | |
| 489 | #define SOLO_VD_IDX_DEINTERLACE (1<<16) | |
| 490 | #define SOLO_VD_IDX_H_BLOCK(n) ((n)<<8) | |
| 491 | #define SOLO_VD_IDX_V_BLOCK(n) ((n)<<0) | |
| 492 | ||
| 493 | #define SOLO_VD_IDX2 0x0938 | |
| 494 | #define SOLO_VD_IDX_REF_BASE_SIDE (1<<31) | |
| 495 | #define SOLO_VD_IDX_REF_BASE(n) (((n)>>16)&0xffff) | |
| 496 | ||
| 497 | #define SOLO_VD_IDX3 0x093C | |
| 498 | #define SOLO_VD_IDX_DISP_SCALE(n) ((n)<<28) | |
| 499 | #define SOLO_VD_IDX_INTERLACE_WR (1<<27) | |
| 500 | #define SOLO_VD_IDX_INTERPOL (1<<26) | |
| 501 | #define SOLO_VD_IDX_HOR2X (1<<25) | |
| 502 | #define SOLO_VD_IDX_OFFSET_X(n) ((n)<<12) | |
| 503 | #define SOLO_VD_IDX_OFFSET_Y(n) ((n)<<0) | |
| 504 | ||
| 505 | #define SOLO_VD_IDX4 0x0940 | |
| 506 | #define SOLO_VD_IDX_DEC_WR_PAGE(n) ((n)<<8) | |
| 507 | #define SOLO_VD_IDX_DISP_RD_PAGE(n) ((n)<<0) | |
| 508 | ||
| 509 | #define SOLO_VD_WR_PAGE(n) (0x03F0 + ((n) * 4)) | |
| 510 | ||
| 511 | ||
| 512 | #define SOLO_GPIO_CONFIG_0 0x0B00 | |
| 513 | #define SOLO_GPIO_CONFIG_1 0x0B04 | |
| 514 | #define SOLO_GPIO_DATA_OUT 0x0B08 | |
| 515 | #define SOLO_GPIO_DATA_IN 0x0B0C | |
| 516 | #define SOLO_GPIO_INT_ACK_STA 0x0B10 | |
| 517 | #define SOLO_GPIO_INT_ENA 0x0B14 | |
| 518 | #define SOLO_GPIO_INT_CFG_0 0x0B18 | |
| 519 | #define SOLO_GPIO_INT_CFG_1 0x0B1C | |
| 520 | ||
| 521 | ||
| 522 | #define SOLO_IIC_CFG 0x0B20 | |
| 523 | #define SOLO_IIC_ENABLE (1<<8) | |
| 524 | #define SOLO_IIC_PRESCALE(n) ((n)<<0) | |
| 525 | ||
| 526 | #define SOLO_IIC_CTRL 0x0B24 | |
| 527 | #define SOLO_IIC_AUTO_CLEAR (1<<20) | |
| 528 | #define SOLO_IIC_STATE_RX_ACK (1<<19) | |
| 529 | #define SOLO_IIC_STATE_BUSY (1<<18) | |
| 530 | #define SOLO_IIC_STATE_SIG_ERR (1<<17) | |
| 531 | #define SOLO_IIC_STATE_TRNS (1<<16) | |
| 532 | #define SOLO_IIC_CH_SET(n) ((n)<<5) | |
| 533 | #define SOLO_IIC_ACK_EN (1<<4) | |
| 534 | #define SOLO_IIC_START (1<<3) | |
| 535 | #define SOLO_IIC_STOP (1<<2) | |
| 536 | #define SOLO_IIC_READ (1<<1) | |
| 537 | #define SOLO_IIC_WRITE (1<<0) | |
| 538 | ||
| 539 | #define SOLO_IIC_TXD 0x0B28 | |
| 540 | #define SOLO_IIC_RXD 0x0B2C | |
| 541 | ||
| 542 | /* | |
| 543 | * UART REGISTER | |
| 544 | */ | |
| 545 | #define SOLO_UART_CONTROL(n) (0x0BA0 + ((n)*0x20)) | |
| 546 | #define SOLO_UART_CLK_DIV(n) ((n)<<24) | |
| 547 | #define SOLO_MODEM_CTRL_EN (1<<20) | |
| 548 | #define SOLO_PARITY_ERROR_DROP (1<<18) | |
| 549 | #define SOLO_IRQ_ERR_EN (1<<17) | |
| 550 | #define SOLO_IRQ_RX_EN (1<<16) | |
| 551 | #define SOLO_IRQ_TX_EN (1<<15) | |
| 552 | #define SOLO_RX_EN (1<<14) | |
| 553 | #define SOLO_TX_EN (1<<13) | |
| 554 | #define SOLO_UART_HALF_DUPLEX (1<<12) | |
| 555 | #define SOLO_UART_LOOPBACK (1<<11) | |
| 556 | ||
| 557 | #define SOLO_BAUDRATE_230400 ((0<<9)|(0<<6)) | |
| 558 | #define SOLO_BAUDRATE_115200 ((0<<9)|(1<<6)) | |
| 559 | #define SOLO_BAUDRATE_57600 ((0<<9)|(2<<6)) | |
| 560 | #define SOLO_BAUDRATE_38400 ((0<<9)|(3<<6)) | |
| 561 | #define SOLO_BAUDRATE_19200 ((0<<9)|(4<<6)) | |
| 562 | #define SOLO_BAUDRATE_9600 ((0<<9)|(5<<6)) | |
| 563 | #define SOLO_BAUDRATE_4800 ((0<<9)|(6<<6)) | |
| 564 | #define SOLO_BAUDRATE_2400 ((1<<9)|(6<<6)) | |
| 565 | #define SOLO_BAUDRATE_1200 ((2<<9)|(6<<6)) | |
| 566 | #define SOLO_BAUDRATE_300 ((3<<9)|(6<<6)) | |
| 567 | ||
| 568 | #define SOLO_UART_DATA_BIT_8 (3<<4) | |
| 569 | #define SOLO_UART_DATA_BIT_7 (2<<4) | |
| 570 | #define SOLO_UART_DATA_BIT_6 (1<<4) | |
| 571 | #define SOLO_UART_DATA_BIT_5 (0<<4) | |
| 572 | ||
| 573 | #define SOLO_UART_STOP_BIT_1 (0<<2) | |
| 574 | #define SOLO_UART_STOP_BIT_2 (1<<2) | |
| 575 | ||
| 576 | #define SOLO_UART_PARITY_NONE (0<<0) | |
| 577 | #define SOLO_UART_PARITY_EVEN (2<<0) | |
| 578 | #define SOLO_UART_PARITY_ODD (3<<0) | |
| 579 | ||
| 580 | #define SOLO_UART_STATUS(n) (0x0BA4 + ((n)*0x20)) | |
| 581 | #define SOLO_UART_CTS (1<<15) | |
| 582 | #define SOLO_UART_RX_BUSY (1<<14) | |
| 583 | #define SOLO_UART_OVERRUN (1<<13) | |
| 584 | #define SOLO_UART_FRAME_ERR (1<<12) | |
| 585 | #define SOLO_UART_PARITY_ERR (1<<11) | |
| 586 | #define SOLO_UART_TX_BUSY (1<<5) | |
| 587 | ||
| 588 | #define SOLO_UART_RX_BUFF_CNT(stat) (((stat)>>6) & 0x1f) | |
| 589 | #define SOLO_UART_RX_BUFF_SIZE 8 | |
| 590 | #define SOLO_UART_TX_BUFF_CNT(stat) (((stat)>>0) & 0x1f) | |
| 591 | #define SOLO_UART_TX_BUFF_SIZE 8 | |
| 592 | ||
| 593 | #define SOLO_UART_TX_DATA(n) (0x0BA8 + ((n)*0x20)) | |
| 594 | #define SOLO_UART_TX_DATA_PUSH (1<<8) | |
| 595 | #define SOLO_UART_RX_DATA(n) (0x0BAC + ((n)*0x20)) | |
| 596 | #define SOLO_UART_RX_DATA_POP (1<<8) | |
| 597 | ||
| 598 | #define SOLO_TIMER_CLOCK_NUM 0x0be0 | |
| faa4fd2a BC |
599 | #define SOLO_TIMER_USEC 0x0be8 |
| 600 | #define SOLO_TIMER_SEC 0x0bec | |
| dcae5dac | 601 | #define SOLO_TIMER_USEC_LSB 0x0d20 /* 6110 Only */ |
| faa4fd2a BC |
602 | |
| 603 | #define SOLO_AUDIO_CONTROL 0x0D00 | |
| 604 | #define SOLO_AUDIO_ENABLE (1<<31) | |
| 605 | #define SOLO_AUDIO_MASTER_MODE (1<<30) | |
| 606 | #define SOLO_AUDIO_I2S_MODE (1<<29) | |
| 607 | #define SOLO_AUDIO_I2S_LR_SWAP (1<<27) | |
| 608 | #define SOLO_AUDIO_I2S_8BIT (1<<26) | |
| 609 | #define SOLO_AUDIO_I2S_MULTI(n) ((n)<<24) | |
| 610 | #define SOLO_AUDIO_MIX_9TO0 (1<<23) | |
| 611 | #define SOLO_AUDIO_DEC_9TO0_VOL(n) ((n)<<20) | |
| 612 | #define SOLO_AUDIO_MIX_19TO10 (1<<19) | |
| 613 | #define SOLO_AUDIO_DEC_19TO10_VOL(n) ((n)<<16) | |
| 614 | #define SOLO_AUDIO_MODE(n) ((n)<<0) | |
| 615 | #define SOLO_AUDIO_SAMPLE 0x0D04 | |
| 616 | #define SOLO_AUDIO_EE_MODE_ON (1<<30) | |
| 617 | #define SOLO_AUDIO_EE_ENC_CH(ch) ((ch)<<25) | |
| 618 | #define SOLO_AUDIO_BITRATE(n) ((n)<<16) | |
| 619 | #define SOLO_AUDIO_CLK_DIV(n) ((n)<<0) | |
| 620 | #define SOLO_AUDIO_FDMA_INTR 0x0D08 | |
| 621 | #define SOLO_AUDIO_FDMA_INTERVAL(n) ((n)<<19) | |
| 622 | #define SOLO_AUDIO_INTR_ORDER(n) ((n)<<16) | |
| 623 | #define SOLO_AUDIO_FDMA_BASE(n) ((n)<<0) | |
| 624 | #define SOLO_AUDIO_EVOL_0 0x0D0C | |
| 625 | #define SOLO_AUDIO_EVOL_1 0x0D10 | |
| 626 | #define SOLO_AUDIO_EVOL(ch, value) ((value)<<((ch)%10)) | |
| 627 | #define SOLO_AUDIO_STA 0x0D14 | |
| 628 | ||
| dcae5dac HV |
629 | /* |
| 630 | * Watchdog configuration | |
| 631 | */ | |
| 632 | #define SOLO_WATCHDOG 0x0be4 | |
| 633 | #define SOLO_WATCHDOG_SET(status, sec) (status << 8 | (sec & 0xff)) | |
| faa4fd2a | 634 | |
| decebabf | 635 | #endif /* __SOLO6X10_REGISTERS_H */ |