Commit | Line | Data |
---|---|---|
ba3d7ddf CG |
1 | /* |
2 | * dim2_hal.c - DIM2 HAL implementation | |
3 | * (MediaLB, Device Interface Macro IP, OS62420) | |
4 | * | |
5 | * Copyright (C) 2015, Microchip Technology Germany II GmbH & Co. KG | |
6 | * | |
7 | * This program is distributed in the hope that it will be useful, | |
8 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
9 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
10 | * GNU General Public License for more details. | |
11 | * | |
12 | * This file is licensed under GPLv2. | |
13 | */ | |
14 | ||
15 | /* Author: Andrey Shvetsov <andrey.shvetsov@k2l.de> */ | |
16 | ||
17 | #include "dim2_hal.h" | |
18 | #include "dim2_errors.h" | |
19 | #include "dim2_reg.h" | |
20 | #include <linux/stddef.h> | |
21 | ||
ba3d7ddf CG |
22 | /* |
23 | * Size factor for isochronous DBR buffer. | |
24 | * Minimal value is 3. | |
25 | */ | |
26 | #define ISOC_DBR_FACTOR 3u | |
27 | ||
28 | /* | |
29 | * Number of 32-bit units for DBR map. | |
30 | * | |
31 | * 1: block size is 512, max allocation is 16K | |
32 | * 2: block size is 256, max allocation is 8K | |
33 | * 4: block size is 128, max allocation is 4K | |
34 | * 8: block size is 64, max allocation is 2K | |
35 | * | |
36 | * Min allocated space is block size. | |
37 | * Max possible allocated space is 32 blocks. | |
38 | */ | |
39 | #define DBR_MAP_SIZE 2 | |
40 | ||
ba3d7ddf CG |
41 | /* -------------------------------------------------------------------------- */ |
42 | /* not configurable area */ | |
43 | ||
44 | #define CDT 0x00 | |
45 | #define ADT 0x40 | |
46 | #define MLB_CAT 0x80 | |
47 | #define AHB_CAT 0x88 | |
48 | ||
16dc3743 | 49 | #define DBR_SIZE (16 * 1024) /* specified by IP */ |
ba3d7ddf CG |
50 | #define DBR_BLOCK_SIZE (DBR_SIZE / 32 / DBR_MAP_SIZE) |
51 | ||
ba3d7ddf CG |
52 | /* -------------------------------------------------------------------------- */ |
53 | /* generic helper functions and macros */ | |
54 | ||
ba3d7ddf CG |
55 | static inline u32 bit_mask(u8 position) |
56 | { | |
57 | return (u32)1 << position; | |
58 | } | |
59 | ||
60 | static inline bool dim_on_error(u8 error_id, const char *error_message) | |
61 | { | |
de668731 | 62 | dimcb_on_error(error_id, error_message); |
ba3d7ddf CG |
63 | return false; |
64 | } | |
65 | ||
ba3d7ddf CG |
66 | /* -------------------------------------------------------------------------- */ |
67 | /* types and local variables */ | |
68 | ||
69 | struct lld_global_vars_t { | |
70 | bool dim_is_initialized; | |
71 | bool mcm_is_initialized; | |
092c78f2 | 72 | struct dim2_regs __iomem *dim2; /* DIM2 core base address */ |
63c87669 | 73 | u32 fcnt; |
ba3d7ddf CG |
74 | u32 dbr_map[DBR_MAP_SIZE]; |
75 | }; | |
76 | ||
77 | static struct lld_global_vars_t g = { false }; | |
78 | ||
ba3d7ddf CG |
79 | /* -------------------------------------------------------------------------- */ |
80 | ||
81 | static int dbr_get_mask_size(u16 size) | |
82 | { | |
83 | int i; | |
84 | ||
85 | for (i = 0; i < 6; i++) | |
86 | if (size <= (DBR_BLOCK_SIZE << i)) | |
87 | return 1 << i; | |
88 | return 0; | |
89 | } | |
90 | ||
91 | /** | |
92 | * Allocates DBR memory. | |
93 | * @param size Allocating memory size. | |
94 | * @return Offset in DBR memory by success or DBR_SIZE if out of memory. | |
95 | */ | |
96 | static int alloc_dbr(u16 size) | |
97 | { | |
98 | int mask_size; | |
99 | int i, block_idx = 0; | |
100 | ||
101 | if (size <= 0) | |
102 | return DBR_SIZE; /* out of memory */ | |
103 | ||
104 | mask_size = dbr_get_mask_size(size); | |
105 | if (mask_size == 0) | |
106 | return DBR_SIZE; /* out of memory */ | |
107 | ||
108 | for (i = 0; i < DBR_MAP_SIZE; i++) { | |
109 | u32 const blocks = (size + DBR_BLOCK_SIZE - 1) / DBR_BLOCK_SIZE; | |
110 | u32 mask = ~((~(u32)0) << blocks); | |
111 | ||
112 | do { | |
113 | if ((g.dbr_map[i] & mask) == 0) { | |
114 | g.dbr_map[i] |= mask; | |
115 | return block_idx * DBR_BLOCK_SIZE; | |
116 | } | |
117 | block_idx += mask_size; | |
9158d33a | 118 | /* do shift left with 2 steps in case mask_size == 32 */ |
ba3d7ddf CG |
119 | mask <<= mask_size - 1; |
120 | } while ((mask <<= 1) != 0); | |
121 | } | |
122 | ||
123 | return DBR_SIZE; /* out of memory */ | |
124 | } | |
125 | ||
126 | static void free_dbr(int offs, int size) | |
127 | { | |
128 | int block_idx = offs / DBR_BLOCK_SIZE; | |
129 | u32 const blocks = (size + DBR_BLOCK_SIZE - 1) / DBR_BLOCK_SIZE; | |
130 | u32 mask = ~((~(u32)0) << blocks); | |
131 | ||
132 | mask <<= block_idx % 32; | |
133 | g.dbr_map[block_idx / 32] &= ~mask; | |
134 | } | |
135 | ||
136 | /* -------------------------------------------------------------------------- */ | |
137 | ||
95a31ef1 CG |
138 | static void dim2_transfer_madr(u32 val) |
139 | { | |
140 | dimcb_io_write(&g.dim2->MADR, val); | |
141 | ||
142 | /* wait for transfer completion */ | |
143 | while ((dimcb_io_read(&g.dim2->MCTL) & 1) != 1) | |
144 | continue; | |
145 | ||
146 | dimcb_io_write(&g.dim2->MCTL, 0); /* clear transfer complete */ | |
147 | } | |
148 | ||
9fe7aeac CG |
149 | static void dim2_clear_dbr(u16 addr, u16 size) |
150 | { | |
151 | enum { MADR_TB_BIT = 30, MADR_WNR_BIT = 31 }; | |
152 | ||
153 | u16 const end_addr = addr + size; | |
154 | u32 const cmd = bit_mask(MADR_WNR_BIT) | bit_mask(MADR_TB_BIT); | |
155 | ||
156 | dimcb_io_write(&g.dim2->MCTL, 0); /* clear transfer complete */ | |
157 | dimcb_io_write(&g.dim2->MDAT0, 0); | |
158 | ||
95a31ef1 CG |
159 | for (; addr < end_addr; addr++) |
160 | dim2_transfer_madr(cmd | addr); | |
9fe7aeac CG |
161 | } |
162 | ||
ba3d7ddf CG |
163 | static u32 dim2_read_ctr(u32 ctr_addr, u16 mdat_idx) |
164 | { | |
95a31ef1 | 165 | dim2_transfer_madr(ctr_addr); |
ba3d7ddf | 166 | |
58889788 | 167 | return dimcb_io_read((&g.dim2->MDAT0) + mdat_idx); |
ba3d7ddf CG |
168 | } |
169 | ||
170 | static void dim2_write_ctr_mask(u32 ctr_addr, const u32 *mask, const u32 *value) | |
171 | { | |
172 | enum { MADR_WNR_BIT = 31 }; | |
173 | ||
1efc4564 | 174 | dimcb_io_write(&g.dim2->MCTL, 0); /* clear transfer complete */ |
ba3d7ddf CG |
175 | |
176 | if (mask[0] != 0) | |
1efc4564 | 177 | dimcb_io_write(&g.dim2->MDAT0, value[0]); |
ba3d7ddf | 178 | if (mask[1] != 0) |
1efc4564 | 179 | dimcb_io_write(&g.dim2->MDAT1, value[1]); |
ba3d7ddf | 180 | if (mask[2] != 0) |
1efc4564 | 181 | dimcb_io_write(&g.dim2->MDAT2, value[2]); |
ba3d7ddf | 182 | if (mask[3] != 0) |
1efc4564 | 183 | dimcb_io_write(&g.dim2->MDAT3, value[3]); |
ba3d7ddf | 184 | |
1efc4564 CL |
185 | dimcb_io_write(&g.dim2->MDWE0, mask[0]); |
186 | dimcb_io_write(&g.dim2->MDWE1, mask[1]); | |
187 | dimcb_io_write(&g.dim2->MDWE2, mask[2]); | |
188 | dimcb_io_write(&g.dim2->MDWE3, mask[3]); | |
ba3d7ddf | 189 | |
95a31ef1 | 190 | dim2_transfer_madr(bit_mask(MADR_WNR_BIT) | ctr_addr); |
ba3d7ddf CG |
191 | } |
192 | ||
193 | static inline void dim2_write_ctr(u32 ctr_addr, const u32 *value) | |
194 | { | |
195 | u32 const mask[4] = { 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF }; | |
196 | ||
197 | dim2_write_ctr_mask(ctr_addr, mask, value); | |
198 | } | |
199 | ||
200 | static inline void dim2_clear_ctr(u32 ctr_addr) | |
201 | { | |
202 | u32 const value[4] = { 0, 0, 0, 0 }; | |
203 | ||
204 | dim2_write_ctr(ctr_addr, value); | |
205 | } | |
206 | ||
207 | static void dim2_configure_cat(u8 cat_base, u8 ch_addr, u8 ch_type, | |
208 | bool read_not_write, bool sync_mfe) | |
209 | { | |
210 | u16 const cat = | |
211 | (read_not_write << CAT_RNW_BIT) | | |
212 | (ch_type << CAT_CT_SHIFT) | | |
213 | (ch_addr << CAT_CL_SHIFT) | | |
214 | (sync_mfe << CAT_MFE_BIT) | | |
215 | (false << CAT_MT_BIT) | | |
216 | (true << CAT_CE_BIT); | |
217 | u8 const ctr_addr = cat_base + ch_addr / 8; | |
218 | u8 const idx = (ch_addr % 8) / 2; | |
219 | u8 const shift = (ch_addr % 2) * 16; | |
220 | u32 mask[4] = { 0, 0, 0, 0 }; | |
221 | u32 value[4] = { 0, 0, 0, 0 }; | |
222 | ||
223 | mask[idx] = (u32)0xFFFF << shift; | |
224 | value[idx] = cat << shift; | |
225 | dim2_write_ctr_mask(ctr_addr, mask, value); | |
226 | } | |
227 | ||
228 | static void dim2_clear_cat(u8 cat_base, u8 ch_addr) | |
229 | { | |
230 | u8 const ctr_addr = cat_base + ch_addr / 8; | |
231 | u8 const idx = (ch_addr % 8) / 2; | |
232 | u8 const shift = (ch_addr % 2) * 16; | |
233 | u32 mask[4] = { 0, 0, 0, 0 }; | |
234 | u32 value[4] = { 0, 0, 0, 0 }; | |
235 | ||
236 | mask[idx] = (u32)0xFFFF << shift; | |
237 | dim2_write_ctr_mask(ctr_addr, mask, value); | |
238 | } | |
239 | ||
240 | static void dim2_configure_cdt(u8 ch_addr, u16 dbr_address, u16 hw_buffer_size, | |
241 | u16 packet_length) | |
242 | { | |
243 | u32 cdt[4] = { 0, 0, 0, 0 }; | |
244 | ||
245 | if (packet_length) | |
246 | cdt[1] = ((packet_length - 1) << CDT1_BS_ISOC_SHIFT); | |
247 | ||
248 | cdt[3] = | |
249 | ((hw_buffer_size - 1) << CDT3_BD_SHIFT) | | |
250 | (dbr_address << CDT3_BA_SHIFT); | |
251 | dim2_write_ctr(CDT + ch_addr, cdt); | |
252 | } | |
253 | ||
254 | static void dim2_clear_cdt(u8 ch_addr) | |
255 | { | |
256 | u32 cdt[4] = { 0, 0, 0, 0 }; | |
257 | ||
258 | dim2_write_ctr(CDT + ch_addr, cdt); | |
259 | } | |
260 | ||
261 | static void dim2_configure_adt(u8 ch_addr) | |
262 | { | |
263 | u32 adt[4] = { 0, 0, 0, 0 }; | |
264 | ||
265 | adt[0] = | |
266 | (true << ADT0_CE_BIT) | | |
267 | (true << ADT0_LE_BIT) | | |
268 | (0 << ADT0_PG_BIT); | |
269 | ||
270 | dim2_write_ctr(ADT + ch_addr, adt); | |
271 | } | |
272 | ||
273 | static void dim2_clear_adt(u8 ch_addr) | |
274 | { | |
275 | u32 adt[4] = { 0, 0, 0, 0 }; | |
276 | ||
277 | dim2_write_ctr(ADT + ch_addr, adt); | |
278 | } | |
279 | ||
280 | static void dim2_start_ctrl_async(u8 ch_addr, u8 idx, u32 buf_addr, | |
281 | u16 buffer_size) | |
282 | { | |
283 | u8 const shift = idx * 16; | |
284 | ||
285 | u32 mask[4] = { 0, 0, 0, 0 }; | |
286 | u32 adt[4] = { 0, 0, 0, 0 }; | |
287 | ||
288 | mask[1] = | |
289 | bit_mask(ADT1_PS_BIT + shift) | | |
290 | bit_mask(ADT1_RDY_BIT + shift) | | |
291 | (ADT1_CTRL_ASYNC_BD_MASK << (ADT1_BD_SHIFT + shift)); | |
292 | adt[1] = | |
293 | (true << (ADT1_PS_BIT + shift)) | | |
294 | (true << (ADT1_RDY_BIT + shift)) | | |
295 | ((buffer_size - 1) << (ADT1_BD_SHIFT + shift)); | |
296 | ||
297 | mask[idx + 2] = 0xFFFFFFFF; | |
298 | adt[idx + 2] = buf_addr; | |
299 | ||
300 | dim2_write_ctr_mask(ADT + ch_addr, mask, adt); | |
301 | } | |
302 | ||
303 | static void dim2_start_isoc_sync(u8 ch_addr, u8 idx, u32 buf_addr, | |
304 | u16 buffer_size) | |
305 | { | |
306 | u8 const shift = idx * 16; | |
307 | ||
308 | u32 mask[4] = { 0, 0, 0, 0 }; | |
309 | u32 adt[4] = { 0, 0, 0, 0 }; | |
310 | ||
311 | mask[1] = | |
312 | bit_mask(ADT1_RDY_BIT + shift) | | |
313 | (ADT1_ISOC_SYNC_BD_MASK << (ADT1_BD_SHIFT + shift)); | |
314 | adt[1] = | |
315 | (true << (ADT1_RDY_BIT + shift)) | | |
316 | ((buffer_size - 1) << (ADT1_BD_SHIFT + shift)); | |
317 | ||
318 | mask[idx + 2] = 0xFFFFFFFF; | |
319 | adt[idx + 2] = buf_addr; | |
320 | ||
321 | dim2_write_ctr_mask(ADT + ch_addr, mask, adt); | |
322 | } | |
323 | ||
ba3d7ddf CG |
324 | static void dim2_clear_ctram(void) |
325 | { | |
326 | u32 ctr_addr; | |
327 | ||
328 | for (ctr_addr = 0; ctr_addr < 0x90; ctr_addr++) | |
329 | dim2_clear_ctr(ctr_addr); | |
330 | } | |
331 | ||
332 | static void dim2_configure_channel( | |
333 | u8 ch_addr, u8 type, u8 is_tx, u16 dbr_address, u16 hw_buffer_size, | |
334 | u16 packet_length, bool sync_mfe) | |
335 | { | |
336 | dim2_configure_cdt(ch_addr, dbr_address, hw_buffer_size, packet_length); | |
337 | dim2_configure_cat(MLB_CAT, ch_addr, type, is_tx ? 1 : 0, sync_mfe); | |
338 | ||
339 | dim2_configure_adt(ch_addr); | |
340 | dim2_configure_cat(AHB_CAT, ch_addr, type, is_tx ? 0 : 1, sync_mfe); | |
341 | ||
342 | /* unmask interrupt for used channel, enable mlb_sys_int[0] interrupt */ | |
1efc4564 | 343 | dimcb_io_write(&g.dim2->ACMR0, |
58889788 | 344 | dimcb_io_read(&g.dim2->ACMR0) | bit_mask(ch_addr)); |
ba3d7ddf CG |
345 | } |
346 | ||
347 | static void dim2_clear_channel(u8 ch_addr) | |
348 | { | |
349 | /* mask interrupt for used channel, disable mlb_sys_int[0] interrupt */ | |
1efc4564 | 350 | dimcb_io_write(&g.dim2->ACMR0, |
58889788 | 351 | dimcb_io_read(&g.dim2->ACMR0) & ~bit_mask(ch_addr)); |
ba3d7ddf CG |
352 | |
353 | dim2_clear_cat(AHB_CAT, ch_addr); | |
354 | dim2_clear_adt(ch_addr); | |
355 | ||
356 | dim2_clear_cat(MLB_CAT, ch_addr); | |
357 | dim2_clear_cdt(ch_addr); | |
1c88f8ff CG |
358 | |
359 | /* clear channel status bit */ | |
360 | dimcb_io_write(&g.dim2->ACSR0, bit_mask(ch_addr)); | |
ba3d7ddf CG |
361 | } |
362 | ||
363 | /* -------------------------------------------------------------------------- */ | |
364 | /* channel state helpers */ | |
365 | ||
366 | static void state_init(struct int_ch_state *state) | |
367 | { | |
368 | state->request_counter = 0; | |
369 | state->service_counter = 0; | |
370 | ||
371 | state->idx1 = 0; | |
372 | state->idx2 = 0; | |
373 | state->level = 0; | |
374 | } | |
375 | ||
376 | /* -------------------------------------------------------------------------- */ | |
377 | /* macro helper functions */ | |
378 | ||
379 | static inline bool check_channel_address(u32 ch_address) | |
380 | { | |
381 | return ch_address > 0 && (ch_address % 2) == 0 && | |
382 | (ch_address / 2) <= (u32)CAT_CL_MASK; | |
383 | } | |
384 | ||
385 | static inline bool check_packet_length(u32 packet_length) | |
386 | { | |
387 | u16 const max_size = ((u16)CDT3_BD_ISOC_MASK + 1u) / ISOC_DBR_FACTOR; | |
388 | ||
389 | if (packet_length <= 0) | |
390 | return false; /* too small */ | |
391 | ||
392 | if (packet_length > max_size) | |
393 | return false; /* too big */ | |
394 | ||
395 | if (packet_length - 1u > (u32)CDT1_BS_ISOC_MASK) | |
396 | return false; /* too big */ | |
397 | ||
398 | return true; | |
399 | } | |
400 | ||
401 | static inline bool check_bytes_per_frame(u32 bytes_per_frame) | |
402 | { | |
63c87669 CG |
403 | u16 const bd_factor = g.fcnt + 2; |
404 | u16 const max_size = ((u16)CDT3_BD_MASK + 1u) >> bd_factor; | |
ba3d7ddf CG |
405 | |
406 | if (bytes_per_frame <= 0) | |
407 | return false; /* too small */ | |
408 | ||
409 | if (bytes_per_frame > max_size) | |
410 | return false; /* too big */ | |
411 | ||
412 | return true; | |
413 | } | |
414 | ||
415 | static inline u16 norm_ctrl_async_buffer_size(u16 buf_size) | |
416 | { | |
417 | u16 const max_size = (u16)ADT1_CTRL_ASYNC_BD_MASK + 1u; | |
418 | ||
419 | if (buf_size > max_size) | |
420 | return max_size; | |
421 | ||
422 | return buf_size; | |
423 | } | |
424 | ||
425 | static inline u16 norm_isoc_buffer_size(u16 buf_size, u16 packet_length) | |
426 | { | |
427 | u16 n; | |
428 | u16 const max_size = (u16)ADT1_ISOC_SYNC_BD_MASK + 1u; | |
429 | ||
430 | if (buf_size > max_size) | |
431 | buf_size = max_size; | |
432 | ||
433 | n = buf_size / packet_length; | |
434 | ||
435 | if (n < 2u) | |
436 | return 0; /* too small buffer for given packet_length */ | |
437 | ||
438 | return packet_length * n; | |
439 | } | |
440 | ||
441 | static inline u16 norm_sync_buffer_size(u16 buf_size, u16 bytes_per_frame) | |
442 | { | |
443 | u16 n; | |
444 | u16 const max_size = (u16)ADT1_ISOC_SYNC_BD_MASK + 1u; | |
63c87669 | 445 | u32 const unit = bytes_per_frame << g.fcnt; |
ba3d7ddf CG |
446 | |
447 | if (buf_size > max_size) | |
448 | buf_size = max_size; | |
449 | ||
450 | n = buf_size / unit; | |
451 | ||
452 | if (n < 1u) | |
453 | return 0; /* too small buffer for given bytes_per_frame */ | |
454 | ||
455 | return unit * n; | |
456 | } | |
457 | ||
458 | static void dim2_cleanup(void) | |
459 | { | |
460 | /* disable MediaLB */ | |
1efc4564 | 461 | dimcb_io_write(&g.dim2->MLBC0, false << MLBC0_MLBEN_BIT); |
ba3d7ddf CG |
462 | |
463 | dim2_clear_ctram(); | |
464 | ||
465 | /* disable mlb_int interrupt */ | |
1efc4564 | 466 | dimcb_io_write(&g.dim2->MIEN, 0); |
ba3d7ddf CG |
467 | |
468 | /* clear status for all dma channels */ | |
1efc4564 CL |
469 | dimcb_io_write(&g.dim2->ACSR0, 0xFFFFFFFF); |
470 | dimcb_io_write(&g.dim2->ACSR1, 0xFFFFFFFF); | |
ba3d7ddf CG |
471 | |
472 | /* mask interrupts for all channels */ | |
1efc4564 CL |
473 | dimcb_io_write(&g.dim2->ACMR0, 0); |
474 | dimcb_io_write(&g.dim2->ACMR1, 0); | |
ba3d7ddf CG |
475 | } |
476 | ||
477 | static void dim2_initialize(bool enable_6pin, u8 mlb_clock) | |
478 | { | |
479 | dim2_cleanup(); | |
480 | ||
481 | /* configure and enable MediaLB */ | |
1efc4564 CL |
482 | dimcb_io_write(&g.dim2->MLBC0, |
483 | enable_6pin << MLBC0_MLBPEN_BIT | | |
484 | mlb_clock << MLBC0_MLBCLK_SHIFT | | |
63c87669 | 485 | g.fcnt << MLBC0_FCNT_SHIFT | |
1efc4564 | 486 | true << MLBC0_MLBEN_BIT); |
ba3d7ddf CG |
487 | |
488 | /* activate all HBI channels */ | |
1efc4564 CL |
489 | dimcb_io_write(&g.dim2->HCMR0, 0xFFFFFFFF); |
490 | dimcb_io_write(&g.dim2->HCMR1, 0xFFFFFFFF); | |
ba3d7ddf CG |
491 | |
492 | /* enable HBI */ | |
1efc4564 | 493 | dimcb_io_write(&g.dim2->HCTL, bit_mask(HCTL_EN_BIT)); |
ba3d7ddf CG |
494 | |
495 | /* configure DMA */ | |
1efc4564 CL |
496 | dimcb_io_write(&g.dim2->ACTL, |
497 | ACTL_DMA_MODE_VAL_DMA_MODE_1 << ACTL_DMA_MODE_BIT | | |
498 | true << ACTL_SCE_BIT); | |
ba3d7ddf CG |
499 | } |
500 | ||
501 | static bool dim2_is_mlb_locked(void) | |
502 | { | |
503 | u32 const mask0 = bit_mask(MLBC0_MLBLK_BIT); | |
504 | u32 const mask1 = bit_mask(MLBC1_CLKMERR_BIT) | | |
505 | bit_mask(MLBC1_LOCKERR_BIT); | |
58889788 | 506 | u32 const c1 = dimcb_io_read(&g.dim2->MLBC1); |
ba3d7ddf CG |
507 | u32 const nda_mask = (u32)MLBC1_NDA_MASK << MLBC1_NDA_SHIFT; |
508 | ||
1efc4564 | 509 | dimcb_io_write(&g.dim2->MLBC1, c1 & nda_mask); |
58889788 CL |
510 | return (dimcb_io_read(&g.dim2->MLBC1) & mask1) == 0 && |
511 | (dimcb_io_read(&g.dim2->MLBC0) & mask0) != 0; | |
ba3d7ddf CG |
512 | } |
513 | ||
ba3d7ddf CG |
514 | /* -------------------------------------------------------------------------- */ |
515 | /* channel help routines */ | |
516 | ||
517 | static inline bool service_channel(u8 ch_addr, u8 idx) | |
518 | { | |
519 | u8 const shift = idx * 16; | |
520 | u32 const adt1 = dim2_read_ctr(ADT + ch_addr, 1); | |
521 | ||
522 | if (((adt1 >> (ADT1_DNE_BIT + shift)) & 1) == 0) | |
523 | return false; | |
524 | ||
525 | { | |
526 | u32 mask[4] = { 0, 0, 0, 0 }; | |
527 | u32 adt_w[4] = { 0, 0, 0, 0 }; | |
528 | ||
529 | mask[1] = | |
530 | bit_mask(ADT1_DNE_BIT + shift) | | |
531 | bit_mask(ADT1_ERR_BIT + shift) | | |
532 | bit_mask(ADT1_RDY_BIT + shift); | |
533 | dim2_write_ctr_mask(ADT + ch_addr, mask, adt_w); | |
534 | } | |
535 | ||
536 | /* clear channel status bit */ | |
1efc4564 | 537 | dimcb_io_write(&g.dim2->ACSR0, bit_mask(ch_addr)); |
ba3d7ddf CG |
538 | |
539 | return true; | |
540 | } | |
541 | ||
ba3d7ddf CG |
542 | /* -------------------------------------------------------------------------- */ |
543 | /* channel init routines */ | |
544 | ||
545 | static void isoc_init(struct dim_channel *ch, u8 ch_addr, u16 packet_length) | |
546 | { | |
547 | state_init(&ch->state); | |
548 | ||
549 | ch->addr = ch_addr; | |
550 | ||
551 | ch->packet_length = packet_length; | |
552 | ch->bytes_per_frame = 0; | |
553 | ch->done_sw_buffers_number = 0; | |
554 | } | |
555 | ||
556 | static void sync_init(struct dim_channel *ch, u8 ch_addr, u16 bytes_per_frame) | |
557 | { | |
558 | state_init(&ch->state); | |
559 | ||
560 | ch->addr = ch_addr; | |
561 | ||
562 | ch->packet_length = 0; | |
563 | ch->bytes_per_frame = bytes_per_frame; | |
564 | ch->done_sw_buffers_number = 0; | |
565 | } | |
566 | ||
567 | static void channel_init(struct dim_channel *ch, u8 ch_addr) | |
568 | { | |
569 | state_init(&ch->state); | |
570 | ||
571 | ch->addr = ch_addr; | |
572 | ||
573 | ch->packet_length = 0; | |
574 | ch->bytes_per_frame = 0; | |
575 | ch->done_sw_buffers_number = 0; | |
576 | } | |
577 | ||
578 | /* returns true if channel interrupt state is cleared */ | |
579 | static bool channel_service_interrupt(struct dim_channel *ch) | |
580 | { | |
581 | struct int_ch_state *const state = &ch->state; | |
582 | ||
583 | if (!service_channel(ch->addr, state->idx2)) | |
584 | return false; | |
585 | ||
586 | state->idx2 ^= 1; | |
587 | state->request_counter++; | |
588 | return true; | |
589 | } | |
590 | ||
591 | static bool channel_start(struct dim_channel *ch, u32 buf_addr, u16 buf_size) | |
592 | { | |
593 | struct int_ch_state *const state = &ch->state; | |
594 | ||
595 | if (buf_size <= 0) | |
596 | return dim_on_error(DIM_ERR_BAD_BUFFER_SIZE, "Bad buffer size"); | |
597 | ||
598 | if (ch->packet_length == 0 && ch->bytes_per_frame == 0 && | |
599 | buf_size != norm_ctrl_async_buffer_size(buf_size)) | |
600 | return dim_on_error(DIM_ERR_BAD_BUFFER_SIZE, | |
601 | "Bad control/async buffer size"); | |
602 | ||
603 | if (ch->packet_length && | |
604 | buf_size != norm_isoc_buffer_size(buf_size, ch->packet_length)) | |
605 | return dim_on_error(DIM_ERR_BAD_BUFFER_SIZE, | |
606 | "Bad isochronous buffer size"); | |
607 | ||
608 | if (ch->bytes_per_frame && | |
609 | buf_size != norm_sync_buffer_size(buf_size, ch->bytes_per_frame)) | |
610 | return dim_on_error(DIM_ERR_BAD_BUFFER_SIZE, | |
611 | "Bad synchronous buffer size"); | |
612 | ||
613 | if (state->level >= 2u) | |
614 | return dim_on_error(DIM_ERR_OVERFLOW, "Channel overflow"); | |
615 | ||
616 | ++state->level; | |
617 | ||
618 | if (ch->packet_length || ch->bytes_per_frame) | |
619 | dim2_start_isoc_sync(ch->addr, state->idx1, buf_addr, buf_size); | |
620 | else | |
9158d33a CG |
621 | dim2_start_ctrl_async(ch->addr, state->idx1, buf_addr, |
622 | buf_size); | |
ba3d7ddf CG |
623 | state->idx1 ^= 1; |
624 | ||
625 | return true; | |
626 | } | |
627 | ||
628 | static u8 channel_service(struct dim_channel *ch) | |
629 | { | |
630 | struct int_ch_state *const state = &ch->state; | |
631 | ||
632 | if (state->service_counter != state->request_counter) { | |
633 | state->service_counter++; | |
634 | if (state->level == 0) | |
635 | return DIM_ERR_UNDERFLOW; | |
636 | ||
637 | --state->level; | |
638 | ch->done_sw_buffers_number++; | |
639 | } | |
640 | ||
641 | return DIM_NO_ERROR; | |
642 | } | |
643 | ||
644 | static bool channel_detach_buffers(struct dim_channel *ch, u16 buffers_number) | |
645 | { | |
646 | if (buffers_number > ch->done_sw_buffers_number) | |
647 | return dim_on_error(DIM_ERR_UNDERFLOW, "Channel underflow"); | |
648 | ||
649 | ch->done_sw_buffers_number -= buffers_number; | |
650 | return true; | |
651 | } | |
652 | ||
ba3d7ddf CG |
653 | /* -------------------------------------------------------------------------- */ |
654 | /* API */ | |
655 | ||
63c87669 CG |
656 | u8 dim_startup(struct dim2_regs __iomem *dim_base_address, u32 mlb_clock, |
657 | u32 fcnt) | |
ba3d7ddf CG |
658 | { |
659 | g.dim_is_initialized = false; | |
660 | ||
661 | if (!dim_base_address) | |
662 | return DIM_INIT_ERR_DIM_ADDR; | |
663 | ||
664 | /* MediaLB clock: 0 - 256 fs, 1 - 512 fs, 2 - 1024 fs, 3 - 2048 fs */ | |
665 | /* MediaLB clock: 4 - 3072 fs, 5 - 4096 fs, 6 - 6144 fs, 7 - 8192 fs */ | |
666 | if (mlb_clock >= 8) | |
667 | return DIM_INIT_ERR_MLB_CLOCK; | |
668 | ||
63c87669 CG |
669 | if (fcnt > MLBC0_FCNT_MAX_VAL) |
670 | return DIM_INIT_ERR_MLB_CLOCK; | |
671 | ||
ba3d7ddf | 672 | g.dim2 = dim_base_address; |
63c87669 | 673 | g.fcnt = fcnt; |
c6c3f345 CG |
674 | g.dbr_map[0] = 0; |
675 | g.dbr_map[1] = 0; | |
ba3d7ddf CG |
676 | |
677 | dim2_initialize(mlb_clock >= 3, mlb_clock); | |
678 | ||
679 | g.dim_is_initialized = true; | |
680 | ||
681 | return DIM_NO_ERROR; | |
682 | } | |
683 | ||
50a45b17 | 684 | void dim_shutdown(void) |
ba3d7ddf CG |
685 | { |
686 | g.dim_is_initialized = false; | |
687 | dim2_cleanup(); | |
688 | } | |
689 | ||
b724207b | 690 | bool dim_get_lock_state(void) |
ba3d7ddf CG |
691 | { |
692 | return dim2_is_mlb_locked(); | |
693 | } | |
694 | ||
695 | static u8 init_ctrl_async(struct dim_channel *ch, u8 type, u8 is_tx, | |
696 | u16 ch_address, u16 hw_buffer_size) | |
697 | { | |
698 | if (!g.dim_is_initialized || !ch) | |
699 | return DIM_ERR_DRIVER_NOT_INITIALIZED; | |
700 | ||
701 | if (!check_channel_address(ch_address)) | |
702 | return DIM_INIT_ERR_CHANNEL_ADDRESS; | |
703 | ||
704 | ch->dbr_size = hw_buffer_size; | |
705 | ch->dbr_addr = alloc_dbr(ch->dbr_size); | |
706 | if (ch->dbr_addr >= DBR_SIZE) | |
707 | return DIM_INIT_ERR_OUT_OF_MEMORY; | |
708 | ||
709 | channel_init(ch, ch_address / 2); | |
710 | ||
711 | dim2_configure_channel(ch->addr, type, is_tx, | |
712 | ch->dbr_addr, ch->dbr_size, 0, false); | |
713 | ||
714 | return DIM_NO_ERROR; | |
715 | } | |
716 | ||
c64c6073 | 717 | u16 dim_norm_ctrl_async_buffer_size(u16 buf_size) |
ba3d7ddf CG |
718 | { |
719 | return norm_ctrl_async_buffer_size(buf_size); | |
720 | } | |
721 | ||
722 | /** | |
723 | * Retrieves maximal possible correct buffer size for isochronous data type | |
724 | * conform to given packet length and not bigger than given buffer size. | |
725 | * | |
726 | * Returns non-zero correct buffer size or zero by error. | |
727 | */ | |
e302ca47 | 728 | u16 dim_norm_isoc_buffer_size(u16 buf_size, u16 packet_length) |
ba3d7ddf CG |
729 | { |
730 | if (!check_packet_length(packet_length)) | |
731 | return 0; | |
732 | ||
733 | return norm_isoc_buffer_size(buf_size, packet_length); | |
734 | } | |
735 | ||
736 | /** | |
737 | * Retrieves maximal possible correct buffer size for synchronous data type | |
738 | * conform to given bytes per frame and not bigger than given buffer size. | |
739 | * | |
740 | * Returns non-zero correct buffer size or zero by error. | |
741 | */ | |
aff19245 | 742 | u16 dim_norm_sync_buffer_size(u16 buf_size, u16 bytes_per_frame) |
ba3d7ddf CG |
743 | { |
744 | if (!check_bytes_per_frame(bytes_per_frame)) | |
745 | return 0; | |
746 | ||
747 | return norm_sync_buffer_size(buf_size, bytes_per_frame); | |
748 | } | |
749 | ||
a3f3e921 CL |
750 | u8 dim_init_control(struct dim_channel *ch, u8 is_tx, u16 ch_address, |
751 | u16 max_buffer_size) | |
ba3d7ddf CG |
752 | { |
753 | return init_ctrl_async(ch, CAT_CT_VAL_CONTROL, is_tx, ch_address, | |
c31d9d12 | 754 | max_buffer_size); |
ba3d7ddf CG |
755 | } |
756 | ||
26303150 CL |
757 | u8 dim_init_async(struct dim_channel *ch, u8 is_tx, u16 ch_address, |
758 | u16 max_buffer_size) | |
ba3d7ddf CG |
759 | { |
760 | return init_ctrl_async(ch, CAT_CT_VAL_ASYNC, is_tx, ch_address, | |
c31d9d12 | 761 | max_buffer_size); |
ba3d7ddf CG |
762 | } |
763 | ||
f1383176 CL |
764 | u8 dim_init_isoc(struct dim_channel *ch, u8 is_tx, u16 ch_address, |
765 | u16 packet_length) | |
ba3d7ddf CG |
766 | { |
767 | if (!g.dim_is_initialized || !ch) | |
768 | return DIM_ERR_DRIVER_NOT_INITIALIZED; | |
769 | ||
770 | if (!check_channel_address(ch_address)) | |
771 | return DIM_INIT_ERR_CHANNEL_ADDRESS; | |
772 | ||
773 | if (!check_packet_length(packet_length)) | |
774 | return DIM_ERR_BAD_CONFIG; | |
775 | ||
776 | ch->dbr_size = packet_length * ISOC_DBR_FACTOR; | |
777 | ch->dbr_addr = alloc_dbr(ch->dbr_size); | |
778 | if (ch->dbr_addr >= DBR_SIZE) | |
779 | return DIM_INIT_ERR_OUT_OF_MEMORY; | |
780 | ||
781 | isoc_init(ch, ch_address / 2, packet_length); | |
782 | ||
783 | dim2_configure_channel(ch->addr, CAT_CT_VAL_ISOC, is_tx, ch->dbr_addr, | |
784 | ch->dbr_size, packet_length, false); | |
785 | ||
786 | return DIM_NO_ERROR; | |
787 | } | |
788 | ||
10e5efb7 CL |
789 | u8 dim_init_sync(struct dim_channel *ch, u8 is_tx, u16 ch_address, |
790 | u16 bytes_per_frame) | |
ba3d7ddf | 791 | { |
63c87669 CG |
792 | u16 bd_factor = g.fcnt + 2; |
793 | ||
ba3d7ddf CG |
794 | if (!g.dim_is_initialized || !ch) |
795 | return DIM_ERR_DRIVER_NOT_INITIALIZED; | |
796 | ||
797 | if (!check_channel_address(ch_address)) | |
798 | return DIM_INIT_ERR_CHANNEL_ADDRESS; | |
799 | ||
800 | if (!check_bytes_per_frame(bytes_per_frame)) | |
801 | return DIM_ERR_BAD_CONFIG; | |
802 | ||
63c87669 | 803 | ch->dbr_size = bytes_per_frame << bd_factor; |
ba3d7ddf CG |
804 | ch->dbr_addr = alloc_dbr(ch->dbr_size); |
805 | if (ch->dbr_addr >= DBR_SIZE) | |
806 | return DIM_INIT_ERR_OUT_OF_MEMORY; | |
807 | ||
808 | sync_init(ch, ch_address / 2, bytes_per_frame); | |
809 | ||
9fe7aeac | 810 | dim2_clear_dbr(ch->dbr_addr, ch->dbr_size); |
ba3d7ddf CG |
811 | dim2_configure_channel(ch->addr, CAT_CT_VAL_SYNC, is_tx, |
812 | ch->dbr_addr, ch->dbr_size, 0, true); | |
813 | ||
814 | return DIM_NO_ERROR; | |
815 | } | |
816 | ||
a5e4d891 | 817 | u8 dim_destroy_channel(struct dim_channel *ch) |
ba3d7ddf CG |
818 | { |
819 | if (!g.dim_is_initialized || !ch) | |
820 | return DIM_ERR_DRIVER_NOT_INITIALIZED; | |
821 | ||
822 | dim2_clear_channel(ch->addr); | |
823 | if (ch->dbr_addr < DBR_SIZE) | |
824 | free_dbr(ch->dbr_addr, ch->dbr_size); | |
825 | ch->dbr_addr = DBR_SIZE; | |
826 | ||
827 | return DIM_NO_ERROR; | |
828 | } | |
829 | ||
e5baa9e9 | 830 | void dim_service_irq(struct dim_channel *const *channels) |
ba3d7ddf CG |
831 | { |
832 | bool state_changed; | |
833 | ||
834 | if (!g.dim_is_initialized) { | |
835 | dim_on_error(DIM_ERR_DRIVER_NOT_INITIALIZED, | |
836 | "DIM is not initialized"); | |
837 | return; | |
838 | } | |
839 | ||
840 | if (!channels) { | |
841 | dim_on_error(DIM_ERR_DRIVER_NOT_INITIALIZED, "Bad channels"); | |
842 | return; | |
843 | } | |
844 | ||
845 | /* | |
9158d33a CG |
846 | * Use while-loop and a flag to make sure the age is changed back at |
847 | * least once, otherwise the interrupt may never come if CPU generates | |
848 | * interrupt on changing age. | |
849 | * This cycle runs not more than number of channels, because | |
850 | * channel_service_interrupt() routine doesn't start the channel again. | |
ba3d7ddf CG |
851 | */ |
852 | do { | |
853 | struct dim_channel *const *ch = channels; | |
854 | ||
855 | state_changed = false; | |
856 | ||
857 | while (*ch) { | |
858 | state_changed |= channel_service_interrupt(*ch); | |
859 | ++ch; | |
860 | } | |
861 | } while (state_changed); | |
862 | ||
863 | /* clear pending Interrupts */ | |
1efc4564 CL |
864 | dimcb_io_write(&g.dim2->MS0, 0); |
865 | dimcb_io_write(&g.dim2->MS1, 0); | |
ba3d7ddf CG |
866 | } |
867 | ||
0d08d54f | 868 | u8 dim_service_channel(struct dim_channel *ch) |
ba3d7ddf CG |
869 | { |
870 | if (!g.dim_is_initialized || !ch) | |
871 | return DIM_ERR_DRIVER_NOT_INITIALIZED; | |
872 | ||
873 | return channel_service(ch); | |
874 | } | |
875 | ||
60d5f66c CL |
876 | struct dim_ch_state_t *dim_get_channel_state(struct dim_channel *ch, |
877 | struct dim_ch_state_t *state_ptr) | |
ba3d7ddf CG |
878 | { |
879 | if (!ch || !state_ptr) | |
910bf1ef | 880 | return NULL; |
ba3d7ddf CG |
881 | |
882 | state_ptr->ready = ch->state.level < 2; | |
883 | state_ptr->done_buffers = ch->done_sw_buffers_number; | |
884 | ||
885 | return state_ptr; | |
886 | } | |
887 | ||
c904ffda CL |
888 | bool dim_enqueue_buffer(struct dim_channel *ch, u32 buffer_addr, |
889 | u16 buffer_size) | |
ba3d7ddf CG |
890 | { |
891 | if (!ch) | |
9158d33a CG |
892 | return dim_on_error(DIM_ERR_DRIVER_NOT_INITIALIZED, |
893 | "Bad channel"); | |
ba3d7ddf CG |
894 | |
895 | return channel_start(ch, buffer_addr, buffer_size); | |
896 | } | |
897 | ||
38c38544 | 898 | bool dim_detach_buffers(struct dim_channel *ch, u16 buffers_number) |
ba3d7ddf CG |
899 | { |
900 | if (!ch) | |
9158d33a CG |
901 | return dim_on_error(DIM_ERR_DRIVER_NOT_INITIALIZED, |
902 | "Bad channel"); | |
ba3d7ddf CG |
903 | |
904 | return channel_detach_buffers(ch, buffers_number); | |
905 | } |