Commit | Line | Data |
---|---|---|
d974ce4f KP |
1 | /* |
2 | * Copyright (c) 2003-2013 Broadcom Corporation | |
3 | * | |
4 | * Copyright (c) 2009-2010 Micron Technology, Inc. | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU General Public License | |
8 | * as published by the Free Software Foundation; either version 2 | |
9 | * of the License, or (at your option) any later version. | |
10 | * | |
11 | * This program is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | * GNU General Public License for more details. | |
15 | */ | |
16 | ||
17 | #include <linux/module.h> | |
18 | #include <linux/delay.h> | |
19 | #include <linux/mtd/mtd.h> | |
20 | #include <linux/mtd/partitions.h> | |
21 | #include <linux/mtd/nand.h> | |
22 | #include <linux/spi/spi.h> | |
23 | ||
24 | #include "mt29f_spinand.h" | |
25 | ||
26 | #define BUFSIZE (10 * 64 * 2048) | |
27 | #define CACHE_BUF 2112 | |
28 | /* | |
29 | * OOB area specification layout: Total 32 available free bytes. | |
30 | */ | |
31 | #ifdef CONFIG_MTD_SPINAND_ONDIEECC | |
32 | static int enable_hw_ecc; | |
33 | static int enable_read_hw_ecc; | |
34 | ||
35 | static inline struct spinand_state *mtd_to_state(struct mtd_info *mtd) | |
36 | { | |
37 | struct nand_chip *chip = (struct nand_chip *)mtd->priv; | |
38 | struct spinand_info *info = (struct spinand_info *)chip->priv; | |
39 | struct spinand_state *state = (struct spinand_state *)info->priv; | |
40 | ||
41 | return state; | |
42 | } | |
43 | ||
44 | static struct nand_ecclayout spinand_oob_64 = { | |
45 | .eccbytes = 24, | |
46 | .eccpos = { | |
47 | 1, 2, 3, 4, 5, 6, | |
48 | 17, 18, 19, 20, 21, 22, | |
49 | 33, 34, 35, 36, 37, 38, | |
50 | 49, 50, 51, 52, 53, 54, }, | |
51 | .oobavail = 32, | |
52 | .oobfree = { | |
53 | {.offset = 8, | |
54 | .length = 8}, | |
55 | {.offset = 24, | |
56 | .length = 8}, | |
57 | {.offset = 40, | |
58 | .length = 8}, | |
59 | {.offset = 56, | |
60 | .length = 8}, | |
61 | } | |
62 | }; | |
63 | #endif | |
64 | ||
65 | /* | |
66 | * spinand_cmd - to process a command to send to the SPI Nand | |
67 | * Description: | |
68 | * Set up the command buffer to send to the SPI controller. | |
69 | * The command buffer has to initialized to 0. | |
70 | */ | |
71 | ||
72 | static int spinand_cmd(struct spi_device *spi, struct spinand_cmd *cmd) | |
73 | { | |
74 | struct spi_message message; | |
75 | struct spi_transfer x[4]; | |
76 | u8 dummy = 0xff; | |
77 | ||
78 | spi_message_init(&message); | |
79 | memset(x, 0, sizeof(x)); | |
80 | ||
81 | x[0].len = 1; | |
82 | x[0].tx_buf = &cmd->cmd; | |
83 | spi_message_add_tail(&x[0], &message); | |
84 | ||
85 | if (cmd->n_addr) { | |
86 | x[1].len = cmd->n_addr; | |
87 | x[1].tx_buf = cmd->addr; | |
88 | spi_message_add_tail(&x[1], &message); | |
89 | } | |
90 | ||
91 | if (cmd->n_dummy) { | |
92 | x[2].len = cmd->n_dummy; | |
93 | x[2].tx_buf = &dummy; | |
94 | spi_message_add_tail(&x[2], &message); | |
95 | } | |
96 | ||
97 | if (cmd->n_tx) { | |
98 | x[3].len = cmd->n_tx; | |
99 | x[3].tx_buf = cmd->tx_buf; | |
100 | spi_message_add_tail(&x[3], &message); | |
101 | } | |
102 | ||
103 | if (cmd->n_rx) { | |
104 | x[3].len = cmd->n_rx; | |
105 | x[3].rx_buf = cmd->rx_buf; | |
106 | spi_message_add_tail(&x[3], &message); | |
107 | } | |
108 | ||
109 | return spi_sync(spi, &message); | |
110 | } | |
111 | ||
112 | /* | |
113 | * spinand_read_id- Read SPI Nand ID | |
114 | * Description: | |
115 | * Read ID: read two ID bytes from the SPI Nand device | |
116 | */ | |
117 | static int spinand_read_id(struct spi_device *spi_nand, u8 *id) | |
118 | { | |
119 | int retval; | |
120 | u8 nand_id[3]; | |
121 | struct spinand_cmd cmd = {0}; | |
122 | ||
123 | cmd.cmd = CMD_READ_ID; | |
124 | cmd.n_rx = 3; | |
125 | cmd.rx_buf = &nand_id[0]; | |
126 | ||
127 | retval = spinand_cmd(spi_nand, &cmd); | |
128 | if (retval < 0) { | |
129 | dev_err(&spi_nand->dev, "error %d reading id\n", retval); | |
130 | return retval; | |
131 | } | |
132 | id[0] = nand_id[1]; | |
133 | id[1] = nand_id[2]; | |
134 | return retval; | |
135 | } | |
136 | ||
137 | /* | |
138 | * spinand_read_status- send command 0xf to the SPI Nand status register | |
139 | * Description: | |
140 | * After read, write, or erase, the Nand device is expected to set the | |
141 | * busy status. | |
142 | * This function is to allow reading the status of the command: read, | |
143 | * write, and erase. | |
144 | * Once the status turns to be ready, the other status bits also are | |
145 | * valid status bits. | |
146 | */ | |
147 | static int spinand_read_status(struct spi_device *spi_nand, uint8_t *status) | |
148 | { | |
149 | struct spinand_cmd cmd = {0}; | |
150 | int ret; | |
151 | ||
152 | cmd.cmd = CMD_READ_REG; | |
153 | cmd.n_addr = 1; | |
154 | cmd.addr[0] = REG_STATUS; | |
155 | cmd.n_rx = 1; | |
156 | cmd.rx_buf = status; | |
157 | ||
158 | ret = spinand_cmd(spi_nand, &cmd); | |
159 | if (ret < 0) | |
160 | dev_err(&spi_nand->dev, "err: %d read status register\n", ret); | |
161 | ||
162 | return ret; | |
163 | } | |
164 | ||
165 | #define MAX_WAIT_JIFFIES (40 * HZ) | |
166 | static int wait_till_ready(struct spi_device *spi_nand) | |
167 | { | |
168 | unsigned long deadline; | |
169 | int retval; | |
170 | u8 stat = 0; | |
171 | ||
172 | deadline = jiffies + MAX_WAIT_JIFFIES; | |
173 | do { | |
174 | retval = spinand_read_status(spi_nand, &stat); | |
175 | if (retval < 0) | |
176 | return -1; | |
177 | else if (!(stat & 0x1)) | |
178 | break; | |
179 | ||
180 | cond_resched(); | |
181 | } while (!time_after_eq(jiffies, deadline)); | |
182 | ||
183 | if ((stat & 0x1) == 0) | |
184 | return 0; | |
185 | ||
186 | return -1; | |
187 | } | |
188 | /** | |
189 | * spinand_get_otp- send command 0xf to read the SPI Nand OTP register | |
190 | * Description: | |
191 | * There is one bit( bit 0x10 ) to set or to clear the internal ECC. | |
192 | * Enable chip internal ECC, set the bit to 1 | |
193 | * Disable chip internal ECC, clear the bit to 0 | |
194 | */ | |
195 | static int spinand_get_otp(struct spi_device *spi_nand, u8 *otp) | |
196 | { | |
197 | struct spinand_cmd cmd = {0}; | |
198 | int retval; | |
199 | ||
200 | cmd.cmd = CMD_READ_REG; | |
201 | cmd.n_addr = 1; | |
202 | cmd.addr[0] = REG_OTP; | |
203 | cmd.n_rx = 1; | |
204 | cmd.rx_buf = otp; | |
205 | ||
206 | retval = spinand_cmd(spi_nand, &cmd); | |
207 | if (retval < 0) | |
208 | dev_err(&spi_nand->dev, "error %d get otp\n", retval); | |
209 | return retval; | |
210 | } | |
211 | ||
212 | /** | |
213 | * spinand_set_otp- send command 0x1f to write the SPI Nand OTP register | |
214 | * Description: | |
215 | * There is one bit( bit 0x10 ) to set or to clear the internal ECC. | |
216 | * Enable chip internal ECC, set the bit to 1 | |
217 | * Disable chip internal ECC, clear the bit to 0 | |
218 | */ | |
219 | static int spinand_set_otp(struct spi_device *spi_nand, u8 *otp) | |
220 | { | |
221 | int retval; | |
222 | struct spinand_cmd cmd = {0}; | |
223 | ||
224 | cmd.cmd = CMD_WRITE_REG, | |
225 | cmd.n_addr = 1, | |
226 | cmd.addr[0] = REG_OTP, | |
227 | cmd.n_tx = 1, | |
228 | cmd.tx_buf = otp, | |
229 | ||
230 | retval = spinand_cmd(spi_nand, &cmd); | |
231 | if (retval < 0) | |
232 | dev_err(&spi_nand->dev, "error %d set otp\n", retval); | |
233 | ||
234 | return retval; | |
235 | } | |
236 | ||
237 | #ifdef CONFIG_MTD_SPINAND_ONDIEECC | |
238 | /** | |
239 | * spinand_enable_ecc- send command 0x1f to write the SPI Nand OTP register | |
240 | * Description: | |
241 | * There is one bit( bit 0x10 ) to set or to clear the internal ECC. | |
242 | * Enable chip internal ECC, set the bit to 1 | |
243 | * Disable chip internal ECC, clear the bit to 0 | |
244 | */ | |
245 | static int spinand_enable_ecc(struct spi_device *spi_nand) | |
246 | { | |
247 | int retval; | |
248 | u8 otp = 0; | |
249 | ||
250 | retval = spinand_get_otp(spi_nand, &otp); | |
251 | if (retval < 0) | |
252 | return retval; | |
253 | ||
254 | if ((otp & OTP_ECC_MASK) == OTP_ECC_MASK) { | |
255 | return 0; | |
256 | } else { | |
257 | otp |= OTP_ECC_MASK; | |
258 | retval = spinand_set_otp(spi_nand, &otp); | |
259 | if (retval < 0) | |
260 | return retval; | |
261 | return spinand_get_otp(spi_nand, &otp); | |
262 | } | |
263 | } | |
264 | #endif | |
265 | ||
266 | static int spinand_disable_ecc(struct spi_device *spi_nand) | |
267 | { | |
268 | int retval; | |
269 | u8 otp = 0; | |
270 | ||
271 | retval = spinand_get_otp(spi_nand, &otp); | |
272 | if (retval < 0) | |
273 | return retval; | |
274 | ||
275 | if ((otp & OTP_ECC_MASK) == OTP_ECC_MASK) { | |
276 | otp &= ~OTP_ECC_MASK; | |
277 | retval = spinand_set_otp(spi_nand, &otp); | |
278 | if (retval < 0) | |
279 | return retval; | |
280 | return spinand_get_otp(spi_nand, &otp); | |
281 | } else | |
282 | return 0; | |
283 | } | |
284 | ||
285 | /** | |
286 | * spinand_write_enable- send command 0x06 to enable write or erase the | |
287 | * Nand cells | |
288 | * Description: | |
289 | * Before write and erase the Nand cells, the write enable has to be set. | |
290 | * After the write or erase, the write enable bit is automatically | |
291 | * cleared (status register bit 2) | |
292 | * Set the bit 2 of the status register has the same effect | |
293 | */ | |
294 | static int spinand_write_enable(struct spi_device *spi_nand) | |
295 | { | |
296 | struct spinand_cmd cmd = {0}; | |
297 | ||
298 | cmd.cmd = CMD_WR_ENABLE; | |
299 | return spinand_cmd(spi_nand, &cmd); | |
300 | } | |
301 | ||
302 | static int spinand_read_page_to_cache(struct spi_device *spi_nand, u16 page_id) | |
303 | { | |
304 | struct spinand_cmd cmd = {0}; | |
305 | u16 row; | |
306 | ||
307 | row = page_id; | |
308 | cmd.cmd = CMD_READ; | |
309 | cmd.n_addr = 3; | |
310 | cmd.addr[1] = (u8)((row & 0xff00) >> 8); | |
311 | cmd.addr[2] = (u8)(row & 0x00ff); | |
312 | ||
313 | return spinand_cmd(spi_nand, &cmd); | |
314 | } | |
315 | ||
316 | /* | |
317 | * spinand_read_from_cache- send command 0x03 to read out the data from the | |
318 | * cache register(2112 bytes max) | |
319 | * Description: | |
320 | * The read can specify 1 to 2112 bytes of data read at the corresponding | |
321 | * locations. | |
322 | * No tRd delay. | |
323 | */ | |
324 | static int spinand_read_from_cache(struct spi_device *spi_nand, u16 page_id, | |
325 | u16 byte_id, u16 len, u8 *rbuf) | |
326 | { | |
327 | struct spinand_cmd cmd = {0}; | |
328 | u16 column; | |
329 | ||
330 | column = byte_id; | |
331 | cmd.cmd = CMD_READ_RDM; | |
332 | cmd.n_addr = 3; | |
333 | cmd.addr[0] = (u8)((column & 0xff00) >> 8); | |
334 | cmd.addr[0] |= (u8)(((page_id >> 6) & 0x1) << 4); | |
335 | cmd.addr[1] = (u8)(column & 0x00ff); | |
336 | cmd.addr[2] = (u8)(0xff); | |
337 | cmd.n_dummy = 0; | |
338 | cmd.n_rx = len; | |
339 | cmd.rx_buf = rbuf; | |
340 | ||
341 | return spinand_cmd(spi_nand, &cmd); | |
342 | } | |
343 | ||
344 | /* | |
345 | * spinand_read_page-to read a page with: | |
346 | * @page_id: the physical page number | |
347 | * @offset: the location from 0 to 2111 | |
348 | * @len: number of bytes to read | |
349 | * @rbuf: read buffer to hold @len bytes | |
350 | * | |
351 | * Description: | |
352 | * The read includes two commands to the Nand: 0x13 and 0x03 commands | |
353 | * Poll to read status to wait for tRD time. | |
354 | */ | |
355 | static int spinand_read_page(struct spi_device *spi_nand, u16 page_id, | |
356 | u16 offset, u16 len, u8 *rbuf) | |
357 | { | |
358 | int ret; | |
359 | u8 status = 0; | |
360 | ||
361 | #ifdef CONFIG_MTD_SPINAND_ONDIEECC | |
362 | if (enable_read_hw_ecc) { | |
363 | if (spinand_enable_ecc(spi_nand) < 0) | |
364 | dev_err(&spi_nand->dev, "enable HW ECC failed!"); | |
365 | } | |
366 | #endif | |
367 | ret = spinand_read_page_to_cache(spi_nand, page_id); | |
368 | if (ret < 0) | |
369 | return ret; | |
370 | ||
371 | if (wait_till_ready(spi_nand)) | |
372 | dev_err(&spi_nand->dev, "WAIT timedout!!!\n"); | |
373 | ||
374 | while (1) { | |
375 | ret = spinand_read_status(spi_nand, &status); | |
376 | if (ret < 0) { | |
377 | dev_err(&spi_nand->dev, | |
378 | "err %d read status register\n", ret); | |
379 | return ret; | |
380 | } | |
381 | ||
382 | if ((status & STATUS_OIP_MASK) == STATUS_READY) { | |
383 | if ((status & STATUS_ECC_MASK) == STATUS_ECC_ERROR) { | |
384 | dev_err(&spi_nand->dev, "ecc error, page=%d\n", | |
385 | page_id); | |
386 | return 0; | |
387 | } | |
388 | break; | |
389 | } | |
390 | } | |
391 | ||
392 | ret = spinand_read_from_cache(spi_nand, page_id, offset, len, rbuf); | |
393 | if (ret < 0) { | |
394 | dev_err(&spi_nand->dev, "read from cache failed!!\n"); | |
395 | return ret; | |
396 | } | |
397 | ||
398 | #ifdef CONFIG_MTD_SPINAND_ONDIEECC | |
399 | if (enable_read_hw_ecc) { | |
400 | ret = spinand_disable_ecc(spi_nand); | |
401 | if (ret < 0) { | |
402 | dev_err(&spi_nand->dev, "disable ecc failed!!\n"); | |
403 | return ret; | |
404 | } | |
405 | enable_read_hw_ecc = 0; | |
406 | } | |
407 | #endif | |
408 | return ret; | |
409 | } | |
410 | ||
411 | /* | |
412 | * spinand_program_data_to_cache--to write a page to cache with: | |
413 | * @byte_id: the location to write to the cache | |
414 | * @len: number of bytes to write | |
415 | * @rbuf: read buffer to hold @len bytes | |
416 | * | |
417 | * Description: | |
418 | * The write command used here is 0x84--indicating that the cache is | |
419 | * not cleared first. | |
420 | * Since it is writing the data to cache, there is no tPROG time. | |
421 | */ | |
422 | static int spinand_program_data_to_cache(struct spi_device *spi_nand, | |
423 | u16 page_id, u16 byte_id, u16 len, u8 *wbuf) | |
424 | { | |
425 | struct spinand_cmd cmd = {0}; | |
426 | u16 column; | |
427 | ||
428 | column = byte_id; | |
429 | cmd.cmd = CMD_PROG_PAGE_CLRCACHE; | |
430 | cmd.n_addr = 2; | |
431 | cmd.addr[0] = (u8)((column & 0xff00) >> 8); | |
432 | cmd.addr[0] |= (u8)(((page_id >> 6) & 0x1) << 4); | |
433 | cmd.addr[1] = (u8)(column & 0x00ff); | |
434 | cmd.n_tx = len; | |
435 | cmd.tx_buf = wbuf; | |
436 | ||
437 | return spinand_cmd(spi_nand, &cmd); | |
438 | } | |
439 | ||
440 | /** | |
441 | * spinand_program_execute--to write a page from cache to the Nand array with | |
442 | * @page_id: the physical page location to write the page. | |
443 | * | |
444 | * Description: | |
445 | * The write command used here is 0x10--indicating the cache is writing to | |
446 | * the Nand array. | |
447 | * Need to wait for tPROG time to finish the transaction. | |
448 | */ | |
449 | static int spinand_program_execute(struct spi_device *spi_nand, u16 page_id) | |
450 | { | |
451 | struct spinand_cmd cmd = {0}; | |
452 | u16 row; | |
453 | ||
454 | row = page_id; | |
455 | cmd.cmd = CMD_PROG_PAGE_EXC; | |
456 | cmd.n_addr = 3; | |
457 | cmd.addr[1] = (u8)((row & 0xff00) >> 8); | |
458 | cmd.addr[2] = (u8)(row & 0x00ff); | |
459 | ||
460 | return spinand_cmd(spi_nand, &cmd); | |
461 | } | |
462 | ||
463 | /** | |
464 | * spinand_program_page--to write a page with: | |
465 | * @page_id: the physical page location to write the page. | |
466 | * @offset: the location from the cache starting from 0 to 2111 | |
467 | * @len: the number of bytes to write | |
468 | * @wbuf: the buffer to hold the number of bytes | |
469 | * | |
470 | * Description: | |
471 | * The commands used here are 0x06, 0x84, and 0x10--indicating that | |
472 | * the write enable is first sent, the write cache command, and the | |
473 | * write execute command. | |
474 | * Poll to wait for the tPROG time to finish the transaction. | |
475 | */ | |
476 | static int spinand_program_page(struct spi_device *spi_nand, | |
477 | u16 page_id, u16 offset, u16 len, u8 *buf) | |
478 | { | |
479 | int retval; | |
480 | u8 status = 0; | |
481 | uint8_t *wbuf; | |
482 | #ifdef CONFIG_MTD_SPINAND_ONDIEECC | |
483 | unsigned int i, j; | |
484 | ||
485 | enable_read_hw_ecc = 0; | |
486 | wbuf = devm_kzalloc(&spi_nand->dev, CACHE_BUF, GFP_KERNEL); | |
487 | spinand_read_page(spi_nand, page_id, 0, CACHE_BUF, wbuf); | |
488 | ||
489 | for (i = offset, j = 0; i < len; i++, j++) | |
490 | wbuf[i] &= buf[j]; | |
491 | ||
492 | if (enable_hw_ecc) { | |
493 | retval = spinand_enable_ecc(spi_nand); | |
494 | if (retval < 0) { | |
495 | dev_err(&spi_nand->dev, "enable ecc failed!!\n"); | |
496 | return retval; | |
497 | } | |
498 | } | |
499 | #else | |
500 | wbuf = buf; | |
501 | #endif | |
502 | retval = spinand_write_enable(spi_nand); | |
503 | if (retval < 0) { | |
504 | dev_err(&spi_nand->dev, "write enable failed!!\n"); | |
505 | return retval; | |
506 | } | |
507 | if (wait_till_ready(spi_nand)) | |
508 | dev_err(&spi_nand->dev, "wait timedout!!!\n"); | |
509 | ||
510 | retval = spinand_program_data_to_cache(spi_nand, page_id, | |
511 | offset, len, wbuf); | |
512 | if (retval < 0) | |
513 | return retval; | |
514 | retval = spinand_program_execute(spi_nand, page_id); | |
515 | if (retval < 0) | |
516 | return retval; | |
517 | while (1) { | |
518 | retval = spinand_read_status(spi_nand, &status); | |
519 | if (retval < 0) { | |
520 | dev_err(&spi_nand->dev, | |
521 | "error %d reading status register\n", | |
522 | retval); | |
523 | return retval; | |
524 | } | |
525 | ||
526 | if ((status & STATUS_OIP_MASK) == STATUS_READY) { | |
527 | if ((status & STATUS_P_FAIL_MASK) == STATUS_P_FAIL) { | |
528 | dev_err(&spi_nand->dev, | |
529 | "program error, page %d\n", page_id); | |
530 | return -1; | |
531 | } else | |
532 | break; | |
533 | } | |
534 | } | |
535 | #ifdef CONFIG_MTD_SPINAND_ONDIEECC | |
536 | if (enable_hw_ecc) { | |
537 | retval = spinand_disable_ecc(spi_nand); | |
538 | if (retval < 0) { | |
539 | dev_err(&spi_nand->dev, "disable ecc failed!!\n"); | |
540 | return retval; | |
541 | } | |
542 | enable_hw_ecc = 0; | |
543 | } | |
544 | #endif | |
545 | ||
546 | return 0; | |
547 | } | |
548 | ||
549 | /** | |
550 | * spinand_erase_block_erase--to erase a page with: | |
551 | * @block_id: the physical block location to erase. | |
552 | * | |
553 | * Description: | |
554 | * The command used here is 0xd8--indicating an erase command to erase | |
555 | * one block--64 pages | |
556 | * Need to wait for tERS. | |
557 | */ | |
558 | static int spinand_erase_block_erase(struct spi_device *spi_nand, u16 block_id) | |
559 | { | |
560 | struct spinand_cmd cmd = {0}; | |
561 | u16 row; | |
562 | ||
563 | row = block_id; | |
564 | cmd.cmd = CMD_ERASE_BLK; | |
565 | cmd.n_addr = 3; | |
566 | cmd.addr[1] = (u8)((row & 0xff00) >> 8); | |
567 | cmd.addr[2] = (u8)(row & 0x00ff); | |
568 | ||
569 | return spinand_cmd(spi_nand, &cmd); | |
570 | } | |
571 | ||
572 | /** | |
573 | * spinand_erase_block--to erase a page with: | |
574 | * @block_id: the physical block location to erase. | |
575 | * | |
576 | * Description: | |
577 | * The commands used here are 0x06 and 0xd8--indicating an erase | |
578 | * command to erase one block--64 pages | |
579 | * It will first to enable the write enable bit (0x06 command), | |
580 | * and then send the 0xd8 erase command | |
581 | * Poll to wait for the tERS time to complete the tranaction. | |
582 | */ | |
583 | static int spinand_erase_block(struct spi_device *spi_nand, u16 block_id) | |
584 | { | |
585 | int retval; | |
586 | u8 status = 0; | |
587 | ||
588 | retval = spinand_write_enable(spi_nand); | |
589 | if (wait_till_ready(spi_nand)) | |
590 | dev_err(&spi_nand->dev, "wait timedout!!!\n"); | |
591 | ||
592 | retval = spinand_erase_block_erase(spi_nand, block_id); | |
593 | while (1) { | |
594 | retval = spinand_read_status(spi_nand, &status); | |
595 | if (retval < 0) { | |
596 | dev_err(&spi_nand->dev, | |
597 | "error %d reading status register\n", | |
598 | (int) retval); | |
599 | return retval; | |
600 | } | |
601 | ||
602 | if ((status & STATUS_OIP_MASK) == STATUS_READY) { | |
603 | if ((status & STATUS_E_FAIL_MASK) == STATUS_E_FAIL) { | |
604 | dev_err(&spi_nand->dev, | |
605 | "erase error, block %d\n", block_id); | |
606 | return -1; | |
607 | } else | |
608 | break; | |
609 | } | |
610 | } | |
611 | return 0; | |
612 | } | |
613 | ||
614 | #ifdef CONFIG_MTD_SPINAND_ONDIEECC | |
615 | static int spinand_write_page_hwecc(struct mtd_info *mtd, | |
616 | struct nand_chip *chip, const uint8_t *buf, int oob_required) | |
617 | { | |
618 | const uint8_t *p = buf; | |
619 | int eccsize = chip->ecc.size; | |
620 | int eccsteps = chip->ecc.steps; | |
621 | ||
622 | enable_hw_ecc = 1; | |
623 | chip->write_buf(mtd, p, eccsize * eccsteps); | |
624 | return 0; | |
625 | } | |
626 | ||
627 | static int spinand_read_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip, | |
628 | uint8_t *buf, int oob_required, int page) | |
629 | { | |
630 | u8 retval, status; | |
631 | uint8_t *p = buf; | |
632 | int eccsize = chip->ecc.size; | |
633 | int eccsteps = chip->ecc.steps; | |
634 | struct spinand_info *info = (struct spinand_info *)chip->priv; | |
635 | ||
636 | enable_read_hw_ecc = 1; | |
637 | ||
638 | chip->read_buf(mtd, p, eccsize * eccsteps); | |
639 | if (oob_required) | |
640 | chip->read_buf(mtd, chip->oob_poi, mtd->oobsize); | |
641 | ||
642 | while (1) { | |
643 | retval = spinand_read_status(info->spi, &status); | |
644 | if ((status & STATUS_OIP_MASK) == STATUS_READY) { | |
645 | if ((status & STATUS_ECC_MASK) == STATUS_ECC_ERROR) { | |
646 | pr_info("spinand: ECC error\n"); | |
647 | mtd->ecc_stats.failed++; | |
648 | } else if ((status & STATUS_ECC_MASK) == | |
649 | STATUS_ECC_1BIT_CORRECTED) | |
650 | mtd->ecc_stats.corrected++; | |
651 | break; | |
652 | } | |
653 | } | |
654 | return 0; | |
655 | ||
656 | } | |
657 | #endif | |
658 | ||
659 | static void spinand_select_chip(struct mtd_info *mtd, int dev) | |
660 | { | |
661 | } | |
662 | ||
663 | static uint8_t spinand_read_byte(struct mtd_info *mtd) | |
664 | { | |
665 | struct spinand_state *state = mtd_to_state(mtd); | |
666 | u8 data; | |
667 | ||
668 | data = state->buf[state->buf_ptr]; | |
669 | state->buf_ptr++; | |
670 | return data; | |
671 | } | |
672 | ||
673 | ||
674 | static int spinand_wait(struct mtd_info *mtd, struct nand_chip *chip) | |
675 | { | |
676 | struct spinand_info *info = (struct spinand_info *)chip->priv; | |
677 | ||
678 | unsigned long timeo = jiffies; | |
679 | int retval, state = chip->state; | |
680 | u8 status; | |
681 | ||
682 | if (state == FL_ERASING) | |
683 | timeo += (HZ * 400) / 1000; | |
684 | else | |
685 | timeo += (HZ * 20) / 1000; | |
686 | ||
687 | while (time_before(jiffies, timeo)) { | |
688 | retval = spinand_read_status(info->spi, &status); | |
689 | if ((status & STATUS_OIP_MASK) == STATUS_READY) | |
690 | return 0; | |
691 | ||
692 | cond_resched(); | |
693 | } | |
694 | return 0; | |
695 | } | |
696 | ||
697 | static void spinand_write_buf(struct mtd_info *mtd, const uint8_t *buf, int len) | |
698 | { | |
699 | ||
700 | struct spinand_state *state = mtd_to_state(mtd); | |
701 | memcpy(state->buf + state->buf_ptr, buf, len); | |
702 | state->buf_ptr += len; | |
703 | } | |
704 | ||
705 | static void spinand_read_buf(struct mtd_info *mtd, uint8_t *buf, int len) | |
706 | { | |
707 | struct spinand_state *state = mtd_to_state(mtd); | |
708 | memcpy(buf, state->buf + state->buf_ptr, len); | |
709 | state->buf_ptr += len; | |
710 | } | |
711 | ||
712 | /* | |
713 | * spinand_reset- send RESET command "0xff" to the Nand device. | |
714 | */ | |
715 | static void spinand_reset(struct spi_device *spi_nand) | |
716 | { | |
717 | struct spinand_cmd cmd = {0}; | |
718 | ||
719 | cmd.cmd = CMD_RESET; | |
720 | ||
721 | if (spinand_cmd(spi_nand, &cmd) < 0) | |
722 | pr_info("spinand reset failed!\n"); | |
723 | ||
724 | /* elapse 1ms before issuing any other command */ | |
725 | udelay(1000); | |
726 | ||
727 | if (wait_till_ready(spi_nand)) | |
728 | dev_err(&spi_nand->dev, "wait timedout!\n"); | |
729 | } | |
730 | ||
731 | static void spinand_cmdfunc(struct mtd_info *mtd, unsigned int command, | |
732 | int column, int page) | |
733 | { | |
734 | struct nand_chip *chip = (struct nand_chip *)mtd->priv; | |
735 | struct spinand_info *info = (struct spinand_info *)chip->priv; | |
736 | struct spinand_state *state = (struct spinand_state *)info->priv; | |
737 | ||
738 | switch (command) { | |
739 | /* | |
740 | * READ0 - read in first 0x800 bytes | |
741 | */ | |
742 | case NAND_CMD_READ1: | |
743 | case NAND_CMD_READ0: | |
744 | state->buf_ptr = 0; | |
745 | spinand_read_page(info->spi, page, 0x0, 0x840, state->buf); | |
746 | break; | |
747 | /* READOOB reads only the OOB because no ECC is performed. */ | |
748 | case NAND_CMD_READOOB: | |
749 | state->buf_ptr = 0; | |
750 | spinand_read_page(info->spi, page, 0x800, 0x40, state->buf); | |
751 | break; | |
752 | case NAND_CMD_RNDOUT: | |
753 | state->buf_ptr = column; | |
754 | break; | |
755 | case NAND_CMD_READID: | |
756 | state->buf_ptr = 0; | |
757 | spinand_read_id(info->spi, (u8 *)state->buf); | |
758 | break; | |
759 | case NAND_CMD_PARAM: | |
760 | state->buf_ptr = 0; | |
761 | break; | |
762 | /* ERASE1 stores the block and page address */ | |
763 | case NAND_CMD_ERASE1: | |
764 | spinand_erase_block(info->spi, page); | |
765 | break; | |
766 | /* ERASE2 uses the block and page address from ERASE1 */ | |
767 | case NAND_CMD_ERASE2: | |
768 | break; | |
769 | /* SEQIN sets up the addr buffer and all registers except the length */ | |
770 | case NAND_CMD_SEQIN: | |
771 | state->col = column; | |
772 | state->row = page; | |
773 | state->buf_ptr = 0; | |
774 | break; | |
775 | /* PAGEPROG reuses all of the setup from SEQIN and adds the length */ | |
776 | case NAND_CMD_PAGEPROG: | |
777 | spinand_program_page(info->spi, state->row, state->col, | |
778 | state->buf_ptr, state->buf); | |
779 | break; | |
780 | case NAND_CMD_STATUS: | |
781 | spinand_get_otp(info->spi, state->buf); | |
782 | if (!(state->buf[0] & 0x80)) | |
783 | state->buf[0] = 0x80; | |
784 | state->buf_ptr = 0; | |
785 | break; | |
786 | /* RESET command */ | |
787 | case NAND_CMD_RESET: | |
788 | if (wait_till_ready(info->spi)) | |
789 | dev_err(&info->spi->dev, "WAIT timedout!!!\n"); | |
790 | /* a minimum of 250us must elapse before issuing RESET cmd*/ | |
791 | udelay(250); | |
792 | spinand_reset(info->spi); | |
793 | break; | |
794 | default: | |
795 | dev_err(&mtd->dev, "Unknown CMD: 0x%x\n", command); | |
796 | } | |
797 | } | |
798 | ||
799 | /** | |
800 | * spinand_lock_block- send write register 0x1f command to the Nand device | |
801 | * | |
802 | * Description: | |
803 | * After power up, all the Nand blocks are locked. This function allows | |
804 | * one to unlock the blocks, and so it can be written or erased. | |
805 | */ | |
806 | static int spinand_lock_block(struct spi_device *spi_nand, u8 lock) | |
807 | { | |
808 | struct spinand_cmd cmd = {0}; | |
809 | int ret; | |
810 | u8 otp = 0; | |
811 | ||
812 | ret = spinand_get_otp(spi_nand, &otp); | |
813 | ||
814 | cmd.cmd = CMD_WRITE_REG; | |
815 | cmd.n_addr = 1; | |
816 | cmd.addr[0] = REG_BLOCK_LOCK; | |
817 | cmd.n_tx = 1; | |
818 | cmd.tx_buf = &lock; | |
819 | ||
820 | ret = spinand_cmd(spi_nand, &cmd); | |
821 | if (ret < 0) | |
822 | dev_err(&spi_nand->dev, "error %d lock block\n", ret); | |
823 | ||
824 | return ret; | |
825 | } | |
826 | /* | |
827 | * spinand_probe - [spinand Interface] | |
828 | * @spi_nand: registered device driver. | |
829 | * | |
830 | * Description: | |
831 | * To set up the device driver parameters to make the device available. | |
832 | */ | |
833 | static int spinand_probe(struct spi_device *spi_nand) | |
834 | { | |
835 | struct mtd_info *mtd; | |
836 | struct nand_chip *chip; | |
837 | struct spinand_info *info; | |
838 | struct spinand_state *state; | |
839 | struct mtd_part_parser_data ppdata; | |
840 | ||
841 | info = devm_kzalloc(&spi_nand->dev, sizeof(struct spinand_info), | |
842 | GFP_KERNEL); | |
843 | if (!info) | |
844 | return -ENOMEM; | |
845 | ||
846 | info->spi = spi_nand; | |
847 | ||
848 | spinand_lock_block(spi_nand, BL_ALL_UNLOCKED); | |
849 | ||
850 | state = devm_kzalloc(&spi_nand->dev, sizeof(struct spinand_state), | |
851 | GFP_KERNEL); | |
852 | if (!state) | |
853 | return -ENOMEM; | |
854 | ||
855 | info->priv = state; | |
856 | state->buf_ptr = 0; | |
857 | state->buf = devm_kzalloc(&spi_nand->dev, BUFSIZE, GFP_KERNEL); | |
858 | if (!state->buf) | |
859 | return -ENOMEM; | |
860 | ||
861 | chip = devm_kzalloc(&spi_nand->dev, sizeof(struct nand_chip), | |
862 | GFP_KERNEL); | |
863 | if (!chip) | |
864 | return -ENOMEM; | |
865 | ||
866 | #ifdef CONFIG_MTD_SPINAND_ONDIEECC | |
867 | chip->ecc.mode = NAND_ECC_HW; | |
868 | chip->ecc.size = 0x200; | |
869 | chip->ecc.bytes = 0x6; | |
870 | chip->ecc.steps = 0x4; | |
871 | ||
872 | chip->ecc.strength = 1; | |
873 | chip->ecc.total = chip->ecc.steps * chip->ecc.bytes; | |
874 | chip->ecc.layout = &spinand_oob_64; | |
875 | chip->ecc.read_page = spinand_read_page_hwecc; | |
876 | chip->ecc.write_page = spinand_write_page_hwecc; | |
877 | #else | |
878 | chip->ecc.mode = NAND_ECC_SOFT; | |
879 | if (spinand_disable_ecc(spi_nand) < 0) | |
880 | pr_info("%s: disable ecc failed!\n", __func__); | |
881 | #endif | |
882 | ||
883 | chip->priv = info; | |
884 | chip->read_buf = spinand_read_buf; | |
885 | chip->write_buf = spinand_write_buf; | |
886 | chip->read_byte = spinand_read_byte; | |
887 | chip->cmdfunc = spinand_cmdfunc; | |
888 | chip->waitfunc = spinand_wait; | |
889 | chip->options |= NAND_CACHEPRG; | |
890 | chip->select_chip = spinand_select_chip; | |
891 | ||
892 | mtd = devm_kzalloc(&spi_nand->dev, sizeof(struct mtd_info), GFP_KERNEL); | |
893 | if (!mtd) | |
894 | return -ENOMEM; | |
895 | ||
896 | dev_set_drvdata(&spi_nand->dev, mtd); | |
897 | ||
898 | mtd->priv = chip; | |
899 | mtd->name = dev_name(&spi_nand->dev); | |
900 | mtd->owner = THIS_MODULE; | |
901 | mtd->oobsize = 64; | |
902 | ||
903 | if (nand_scan(mtd, 1)) | |
904 | return -ENXIO; | |
905 | ||
906 | ppdata.of_node = spi_nand->dev.of_node; | |
907 | return mtd_device_parse_register(mtd, NULL, &ppdata, NULL, 0); | |
908 | } | |
909 | ||
910 | /* | |
911 | * spinand_remove: Remove the device driver | |
912 | * @spi: the spi device. | |
913 | * | |
914 | * Description: | |
915 | * To remove the device driver parameters and free up allocated memories. | |
916 | */ | |
917 | static int spinand_remove(struct spi_device *spi) | |
918 | { | |
919 | mtd_device_unregister(dev_get_drvdata(&spi->dev)); | |
920 | ||
921 | return 0; | |
922 | } | |
923 | ||
924 | static const struct of_device_id spinand_dt[] = { | |
925 | { .compatible = "spinand,mt29f", }, | |
926 | }; | |
927 | ||
928 | /* | |
929 | * Device name structure description | |
930 | */ | |
931 | static struct spi_driver spinand_driver = { | |
932 | .driver = { | |
933 | .name = "mt29f", | |
934 | .bus = &spi_bus_type, | |
935 | .owner = THIS_MODULE, | |
936 | .of_match_table = spinand_dt, | |
937 | }, | |
938 | .probe = spinand_probe, | |
939 | .remove = spinand_remove, | |
940 | }; | |
941 | ||
942 | /* | |
943 | * Device driver registration | |
944 | */ | |
945 | static int __init spinand_init(void) | |
946 | { | |
947 | return spi_register_driver(&spinand_driver); | |
948 | } | |
949 | ||
950 | /* | |
951 | * unregister Device driver. | |
952 | */ | |
953 | static void __exit spinand_exit(void) | |
954 | { | |
955 | spi_unregister_driver(&spinand_driver); | |
956 | } | |
957 | module_init(spinand_init); | |
958 | module_exit(spinand_exit); | |
959 | ||
960 | MODULE_DESCRIPTION("SPI NAND driver for Micron"); | |
961 | MODULE_AUTHOR("Henry Pan <hspan@micron.com>, Kamlakant Patel <kamlakant.patel@broadcom.com>"); | |
962 | MODULE_LICENSE("GPL v2"); |