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net: core: explicitly select a txq before doing l2 forwarding
[deliverable/linux.git] / drivers / staging / netlogic / xlr_net.c
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6f98b1a2
GR		 1/*
2 * Copyright (c) 2003-2012 Broadcom Corporation
3 * All Rights Reserved
4 *
5 * This software is available to you under a choice of one of two
6 * licenses. You may choose to be licensed under the terms of the GNU
7 * General Public License (GPL) Version 2, available from the file
8 * COPYING in the main directory of this source tree, or the Broadcom
9 * license below:
10 *
11 * Redistribution and use in source and binary forms, with or without
12 * modification, are permitted provided that the following conditions
13 * are met:
14 *
15 * 1. Redistributions of source code must retain the above copyright
16 * notice, this list of conditions and the following disclaimer.
17 * 2. Redistributions in binary form must reproduce the above copyright
18 * notice, this list of conditions and the following disclaimer in
19 * the documentation and/or other materials provided with the
20 * distribution.
21 *
22 * THIS SOFTWARE IS PROVIDED BY BROADCOM ``AS IS'' AND ANY EXPRESS OR
23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
24 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
25 * ARE DISCLAIMED. IN NO EVENT SHALL BROADCOM OR CONTRIBUTORS BE LIABLE
26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
29 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
30 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
31 * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
32 * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34#include <linux/phy.h>
35#include <linux/delay.h>
36#include <linux/netdevice.h>
37#include <linux/smp.h>
38#include <linux/ethtool.h>
39#include <linux/module.h>
40#include <linux/etherdevice.h>
41#include <linux/skbuff.h>
42#include <linux/jiffies.h>
43#include <linux/interrupt.h>
44#include <linux/platform_device.h>
45
46#include <asm/mipsregs.h>
2db0083d
A		 47/*
48 * fmn.h - For FMN credit configuration and registering fmn_handler.
6f98b1a2
GR		 49 * FMN is communication mechanism that allows processing agents within
50 * XLR/XLS to communicate each other.
51 */
52#include <asm/netlogic/xlr/fmn.h>
53
54#include "platform_net.h"
55#include "xlr_net.h"
56
57/*
58 * The readl/writel implementation byteswaps on XLR/XLS, so
59 * we need to use __raw_ IO to read the NAE registers
60 * because they are in the big-endian MMIO area on the SoC.
61 */
62static inline void xlr_nae_wreg(u32 __iomem *base, unsigned int reg, u32 val)
63{
64 __raw_writel(val, base + reg);
65}
66
67static inline u32 xlr_nae_rdreg(u32 __iomem *base, unsigned int reg)
68{
69 return __raw_readl(base + reg);
70}
71
72static inline void xlr_reg_update(u32 *base_addr,
73 u32 off, u32 val, u32 mask)
74{
75 u32 tmp;
76
77 tmp = xlr_nae_rdreg(base_addr, off);
78 xlr_nae_wreg(base_addr, off, (tmp & ~mask) | (val & mask));
79}
80
81/*
82 * Table of net_device pointers indexed by port, this will be used to
83 * lookup the net_device corresponding to a port by the message ring handler.
84 *
85 * Maximum ports in XLR/XLS is 8(8 GMAC on XLS, 4 GMAC + 2 XGMAC on XLR)
86 */
87static struct net_device *mac_to_ndev[8];
88
89static inline struct sk_buff *mac_get_skb_back_ptr(void *addr)
90{
91 struct sk_buff **back_ptr;
92
2db0083d
A		 93 /*
94 * this function should be used only for newly allocated packets.
6f98b1a2
GR		 95 * It assumes the first cacheline is for the back pointer related
96 * book keeping info.
97 */
98 back_ptr = (struct sk_buff **)(addr - MAC_SKB_BACK_PTR_SIZE);
99 return *back_ptr;
100}
101
102static inline void mac_put_skb_back_ptr(struct sk_buff *skb)
103{
104 struct sk_buff **back_ptr = (struct sk_buff **)skb->data;
105
2db0083d
A		 106 /*
107 * this function should be used only for newly allocated packets.
6f98b1a2
GR		 108 * It assumes the first cacheline is for the back pointer related
109 * book keeping info.
110 */
111 skb_reserve(skb, MAC_SKB_BACK_PTR_SIZE);
112 *back_ptr = skb;
113}
114
115static int send_to_rfr_fifo(struct xlr_net_priv *priv, void *addr)
116{
117 struct nlm_fmn_msg msg;
118 int ret = 0, num_try = 0, stnid;
119 unsigned long paddr, mflags;
120
121 paddr = virt_to_bus(addr);
122 msg.msg0 = (u64)paddr & 0xffffffffe0ULL;
123 msg.msg1 = 0;
124 msg.msg2 = 0;
125 msg.msg3 = 0;
126 stnid = priv->nd->rfr_station;
127 do {
128 mflags = nlm_cop2_enable();
129 ret = nlm_fmn_send(1, 0, stnid, &msg);
130 nlm_cop2_restore(mflags);
131 if (ret == 0)
132 return 0;
133 } while (++num_try < 10000);
134
135 pr_err("Send to RFR failed in RX path\n");
136 return ret;
137}
138
139static inline struct sk_buff *xlr_alloc_skb(void)
140{
141 struct sk_buff *skb;
142
143 /* skb->data is cache aligned */
144 skb = alloc_skb(XLR_RX_BUF_SIZE, GFP_ATOMIC);
145 if (!skb) {
146 pr_err("SKB allocation failed\n");
147 return NULL;
148 }
149 mac_put_skb_back_ptr(skb);
150 return skb;
151}
152
153static void xlr_net_fmn_handler(int bkt, int src_stnid, int size,
154 int code, struct nlm_fmn_msg *msg, void *arg)
155{
156 struct sk_buff *skb, *skb_new = NULL;
157 struct net_device *ndev;
158 struct xlr_net_priv *priv;
159 u64 length, port;
160 void *addr;
161
162 length = (msg->msg0 >> 40) & 0x3fff;
163 if (length == 0) {
164 addr = bus_to_virt(msg->msg0 & 0xffffffffffULL);
165 dev_kfree_skb_any(addr);
166 } else if (length) {
167 addr = bus_to_virt(msg->msg0 & 0xffffffffe0ULL);
168 length = length - BYTE_OFFSET - MAC_CRC_LEN;
169 port = msg->msg0 & 0x0f;
170 if (src_stnid == FMN_STNID_GMAC1)
171 port = port + 4;
172 skb = mac_get_skb_back_ptr(addr);
173 skb->dev = mac_to_ndev[port];
174 ndev = skb->dev;
175 priv = netdev_priv(ndev);
176
177 /* 16 byte IP header align */
178 skb_reserve(skb, BYTE_OFFSET);
179 skb_put(skb, length);
180 skb->protocol = eth_type_trans(skb, skb->dev);
181 skb->dev->last_rx = jiffies;
182 netif_rx(skb);
183 /* Fill rx ring */
184 skb_new = xlr_alloc_skb();
185 if (skb_new)
186 send_to_rfr_fifo(priv, skb_new->data);
187 }
188 return;
189}
190
191/* Ethtool operation */
192static int xlr_get_settings(struct net_device *ndev, struct ethtool_cmd *ecmd)
193{
194 struct xlr_net_priv *priv = netdev_priv(ndev);
195 struct phy_device *phydev = priv->mii_bus->phy_map[priv->phy_addr];
196
197 if (!phydev)
198 return -ENODEV;
199 return phy_ethtool_gset(phydev, ecmd);
200}
201
202static int xlr_set_settings(struct net_device *ndev, struct ethtool_cmd *ecmd)
203{
204 struct xlr_net_priv *priv = netdev_priv(ndev);
205 struct phy_device *phydev = priv->mii_bus->phy_map[priv->phy_addr];
206
207 if (!phydev)
208 return -ENODEV;
209 return phy_ethtool_sset(phydev, ecmd);
210}
211
212static struct ethtool_ops xlr_ethtool_ops = {
213 .get_settings = xlr_get_settings,
214 .set_settings = xlr_set_settings,
215};
216
217/* Net operations */
218static int xlr_net_fill_rx_ring(struct net_device *ndev)
219{
220 struct sk_buff *skb;
221 struct xlr_net_priv *priv = netdev_priv(ndev);
222 int i;
223
224 for (i = 0; i < MAX_FRIN_SPILL/2; i++) {
225 skb = xlr_alloc_skb();
226 if (!skb)
227 return -ENOMEM;
228 send_to_rfr_fifo(priv, skb->data);
229 }
230 pr_info("Rx ring setup done\n");
231 return 0;
232}
233
234static int xlr_net_open(struct net_device *ndev)
235{
236 u32 err;
237 struct xlr_net_priv *priv = netdev_priv(ndev);
238 struct phy_device *phydev = priv->mii_bus->phy_map[priv->phy_addr];
239
240 /* schedule a link state check */
241 phy_start(phydev);
242
243 err = phy_start_aneg(phydev);
244 if (err) {
245 pr_err("Autoneg failed\n");
246 return err;
247 }
248
249 /* Setup the speed from PHY to internal reg*/
250 xlr_set_gmac_speed(priv);
251 netif_tx_start_all_queues(ndev);
252 return 0;
253}
254
255static int xlr_net_stop(struct net_device *ndev)
256{
257 struct xlr_net_priv *priv = netdev_priv(ndev);
258 struct phy_device *phydev = priv->mii_bus->phy_map[priv->phy_addr];
259
260 phy_stop(phydev);
261 netif_tx_stop_all_queues(ndev);
262 return 0;
263}
264
265static void xlr_make_tx_desc(struct nlm_fmn_msg *msg, unsigned long addr,
266 struct sk_buff *skb)
267{
268 unsigned long physkb = virt_to_phys(skb);
269 int cpu_core = nlm_core_id();
270 int fr_stn_id = cpu_core * 8 + XLR_FB_STN; /* FB to 6th bucket */
271 msg->msg0 = (((u64)1 << 63) | /* End of packet descriptor */
272 ((u64)127 << 54) | /* No Free back */
273 (u64)skb->len << 40 | /* Length of data */
274 ((u64)addr));
275 msg->msg1 = (((u64)1 << 63) |
276 ((u64)fr_stn_id << 54) | /* Free back id */
277 (u64)0 << 40 | /* Set len to 0 */
278 ((u64)physkb & 0xffffffff)); /* 32bit address */
279 msg->msg2 = msg->msg3 = 0;
280}
281
282static void __maybe_unused xlr_wakeup_queue(unsigned long dev)
283{
284 struct net_device *ndev = (struct net_device *) dev;
285 struct xlr_net_priv *priv = netdev_priv(ndev);
286 struct phy_device *phydev = priv->mii_bus->phy_map[priv->phy_addr];
287
288 if (phydev->link)
289 netif_tx_wake_queue(netdev_get_tx_queue(ndev, priv->wakeup_q));
290}
291
292static netdev_tx_t xlr_net_start_xmit(struct sk_buff *skb,
293 struct net_device *ndev)
294{
295 struct nlm_fmn_msg msg;
296 struct xlr_net_priv *priv = netdev_priv(ndev);
297 int ret;
6f98b1a2
GR		 298 u32 flags;
299
6f98b1a2
GR		 300 xlr_make_tx_desc(&msg, virt_to_phys(skb->data), skb);
301 flags = nlm_cop2_enable();
302 ret = nlm_fmn_send(2, 0, priv->nd->tx_stnid, &msg);
303 nlm_cop2_restore(flags);
304 if (ret)
305 dev_kfree_skb_any(skb);
306 return NETDEV_TX_OK;
307}
308
f663dd9a
JW		 309static u16 xlr_net_select_queue(struct net_device *ndev, struct sk_buff *skb,
310 void *accel_priv)
6f98b1a2
GR		 311{
312 return (u16)smp_processor_id();
313}
314
315static void xlr_hw_set_mac_addr(struct net_device *ndev)
316{
317 struct xlr_net_priv *priv = netdev_priv(ndev);
318
319 /* set mac station address */
320 xlr_nae_wreg(priv->base_addr, R_MAC_ADDR0,
321 ((ndev->dev_addr[5] << 24) | (ndev->dev_addr[4] << 16) |
322 (ndev->dev_addr[3] << 8) | (ndev->dev_addr[2])));
323 xlr_nae_wreg(priv->base_addr, R_MAC_ADDR0 + 1,
324 ((ndev->dev_addr[1] << 24) | (ndev->dev_addr[0] << 16)));
325
326 xlr_nae_wreg(priv->base_addr, R_MAC_ADDR_MASK2, 0xffffffff);
327 xlr_nae_wreg(priv->base_addr, R_MAC_ADDR_MASK2 + 1, 0xffffffff);
328 xlr_nae_wreg(priv->base_addr, R_MAC_ADDR_MASK3, 0xffffffff);
329 xlr_nae_wreg(priv->base_addr, R_MAC_ADDR_MASK3 + 1, 0xffffffff);
330
331 xlr_nae_wreg(priv->base_addr, R_MAC_FILTER_CONFIG,
332 (1 << O_MAC_FILTER_CONFIG__BROADCAST_EN) |
333 (1 << O_MAC_FILTER_CONFIG__ALL_MCAST_EN) |
334 (1 << O_MAC_FILTER_CONFIG__MAC_ADDR0_VALID));
335
336 if (priv->nd->phy_interface == PHY_INTERFACE_MODE_RGMII ||
337 priv->nd->phy_interface == PHY_INTERFACE_MODE_SGMII)
338 xlr_reg_update(priv->base_addr, R_IPG_IFG, MAC_B2B_IPG, 0x7f);
339}
340
341static int xlr_net_set_mac_addr(struct net_device *ndev, void *data)
342{
343 int err;
344
345 err = eth_mac_addr(ndev, data);
346 if (err)
347 return err;
348 xlr_hw_set_mac_addr(ndev);
349 return 0;
350}
351
352static void xlr_set_rx_mode(struct net_device *ndev)
353{
354 struct xlr_net_priv *priv = netdev_priv(ndev);
355 u32 regval;
356
357 regval = xlr_nae_rdreg(priv->base_addr, R_MAC_FILTER_CONFIG);
358
359 if (ndev->flags & IFF_PROMISC) {
360 regval |= (1 << O_MAC_FILTER_CONFIG__BROADCAST_EN) |
361 (1 << O_MAC_FILTER_CONFIG__PAUSE_FRAME_EN) |
362 (1 << O_MAC_FILTER_CONFIG__ALL_MCAST_EN) |
363 (1 << O_MAC_FILTER_CONFIG__ALL_UCAST_EN);
364 } else {
365 regval &= ~((1 << O_MAC_FILTER_CONFIG__PAUSE_FRAME_EN) |
366 (1 << O_MAC_FILTER_CONFIG__ALL_UCAST_EN));
367 }
368
369 xlr_nae_wreg(priv->base_addr, R_MAC_FILTER_CONFIG, regval);
370}
371
372static void xlr_stats(struct net_device *ndev, struct rtnl_link_stats64 *stats)
373{
374 struct xlr_net_priv *priv = netdev_priv(ndev);
375
376 stats->rx_packets = xlr_nae_rdreg(priv->base_addr, RX_PACKET_COUNTER);
377 stats->tx_packets = xlr_nae_rdreg(priv->base_addr, TX_PACKET_COUNTER);
378 stats->rx_bytes = xlr_nae_rdreg(priv->base_addr, RX_BYTE_COUNTER);
379 stats->tx_bytes = xlr_nae_rdreg(priv->base_addr, TX_BYTE_COUNTER);
380 stats->tx_errors = xlr_nae_rdreg(priv->base_addr, TX_FCS_ERROR_COUNTER);
381 stats->rx_dropped = xlr_nae_rdreg(priv->base_addr,
382 RX_DROP_PACKET_COUNTER);
383 stats->tx_dropped = xlr_nae_rdreg(priv->base_addr,
384 TX_DROP_FRAME_COUNTER);
385
386 stats->multicast = xlr_nae_rdreg(priv->base_addr,
387 RX_MULTICAST_PACKET_COUNTER);
388 stats->collisions = xlr_nae_rdreg(priv->base_addr,
389 TX_TOTAL_COLLISION_COUNTER);
390
391 stats->rx_length_errors = xlr_nae_rdreg(priv->base_addr,
392 RX_FRAME_LENGTH_ERROR_COUNTER);
393 stats->rx_over_errors = xlr_nae_rdreg(priv->base_addr,
394 RX_DROP_PACKET_COUNTER);
395 stats->rx_crc_errors = xlr_nae_rdreg(priv->base_addr,
396 RX_FCS_ERROR_COUNTER);
397 stats->rx_frame_errors = xlr_nae_rdreg(priv->base_addr,
398 RX_ALIGNMENT_ERROR_COUNTER);
399
400 stats->rx_fifo_errors = xlr_nae_rdreg(priv->base_addr,
401 RX_DROP_PACKET_COUNTER);
402 stats->rx_missed_errors = xlr_nae_rdreg(priv->base_addr,
403 RX_CARRIER_SENSE_ERROR_COUNTER);
404
405 stats->rx_errors = (stats->rx_over_errors + stats->rx_crc_errors +
406 stats->rx_frame_errors + stats->rx_fifo_errors +
407 stats->rx_missed_errors);
408
409 stats->tx_aborted_errors = xlr_nae_rdreg(priv->base_addr,
410 TX_EXCESSIVE_COLLISION_PACKET_COUNTER);
411 stats->tx_carrier_errors = xlr_nae_rdreg(priv->base_addr,
412 TX_DROP_FRAME_COUNTER);
413 stats->tx_fifo_errors = xlr_nae_rdreg(priv->base_addr,
414 TX_DROP_FRAME_COUNTER);
415}
416
417static struct rtnl_link_stats64 *xlr_get_stats64(struct net_device *ndev,
418 struct rtnl_link_stats64 *stats)
419{
420 xlr_stats(ndev, stats);
421 return stats;
422}
423
424static struct net_device_ops xlr_netdev_ops = {
425 .ndo_open = xlr_net_open,
426 .ndo_stop = xlr_net_stop,
427 .ndo_start_xmit = xlr_net_start_xmit,
428 .ndo_select_queue = xlr_net_select_queue,
429 .ndo_set_mac_address = xlr_net_set_mac_addr,
430 .ndo_set_rx_mode = xlr_set_rx_mode,
431 .ndo_get_stats64 = xlr_get_stats64,
432};
433
434/* Gmac init */
435static void *xlr_config_spill(struct xlr_net_priv *priv, int reg_start_0,
436 int reg_start_1, int reg_size, int size)
437{
438 void *spill;
439 u32 *base;
440 unsigned long phys_addr;
441 u32 spill_size;
442
443 base = priv->base_addr;
444 spill_size = size;
445 spill = kmalloc(spill_size + SMP_CACHE_BYTES, GFP_ATOMIC);
446 if (!spill)
447 pr_err("Unable to allocate memory for spill area!\n");
448
449 spill = PTR_ALIGN(spill, SMP_CACHE_BYTES);
450 phys_addr = virt_to_phys(spill);
451 dev_dbg(&priv->ndev->dev, "Allocated spill %d bytes at %lx\n",
452 size, phys_addr);
453 xlr_nae_wreg(base, reg_start_0, (phys_addr >> 5) & 0xffffffff);
454 xlr_nae_wreg(base, reg_start_1, ((u64)phys_addr >> 37) & 0x07);
455 xlr_nae_wreg(base, reg_size, spill_size);
456
457 return spill;
458}
459
460/*
461 * Configure the 6 FIFO's that are used by the network accelarator to
462 * communicate with the rest of the XLx device. 4 of the FIFO's are for
463 * packets from NA --> cpu (called Class FIFO's) and 2 are for feeding
464 * the NA with free descriptors.
465 */
466static void xlr_config_fifo_spill_area(struct xlr_net_priv *priv)
467{
468 priv->frin_spill = xlr_config_spill(priv,
469 R_REG_FRIN_SPILL_MEM_START_0,
470 R_REG_FRIN_SPILL_MEM_START_1,
471 R_REG_FRIN_SPILL_MEM_SIZE,
472 MAX_FRIN_SPILL *
473 sizeof(u64));
474 priv->frout_spill = xlr_config_spill(priv,
475 R_FROUT_SPILL_MEM_START_0,
476 R_FROUT_SPILL_MEM_START_1,
477 R_FROUT_SPILL_MEM_SIZE,
478 MAX_FROUT_SPILL *
479 sizeof(u64));
480 priv->class_0_spill = xlr_config_spill(priv,
481 R_CLASS0_SPILL_MEM_START_0,
482 R_CLASS0_SPILL_MEM_START_1,
483 R_CLASS0_SPILL_MEM_SIZE,
484 MAX_CLASS_0_SPILL *
485 sizeof(u64));
486 priv->class_1_spill = xlr_config_spill(priv,
487 R_CLASS1_SPILL_MEM_START_0,
488 R_CLASS1_SPILL_MEM_START_1,
489 R_CLASS1_SPILL_MEM_SIZE,
490 MAX_CLASS_1_SPILL *
491 sizeof(u64));
492 priv->class_2_spill = xlr_config_spill(priv,
493 R_CLASS2_SPILL_MEM_START_0,
494 R_CLASS2_SPILL_MEM_START_1,
495 R_CLASS2_SPILL_MEM_SIZE,
496 MAX_CLASS_2_SPILL *
497 sizeof(u64));
498 priv->class_3_spill = xlr_config_spill(priv,
499 R_CLASS3_SPILL_MEM_START_0,
500 R_CLASS3_SPILL_MEM_START_1,
501 R_CLASS3_SPILL_MEM_SIZE,
502 MAX_CLASS_3_SPILL *
503 sizeof(u64));
504}
505
2db0083d
A		 506/*
507 * Configure PDE to Round-Robin distribution of packets to the
508 * available cpu
509 */
6f98b1a2
GR		 510static void xlr_config_pde(struct xlr_net_priv *priv)
511{
512 int i = 0;
513 u64 bkt_map = 0;
514
515 /* Each core has 8 buckets(station) */
516 for (i = 0; i < hweight32(priv->nd->cpu_mask); i++)
517 bkt_map |= (0xff << (i * 8));
518
519 xlr_nae_wreg(priv->base_addr, R_PDE_CLASS_0, (bkt_map & 0xffffffff));
520 xlr_nae_wreg(priv->base_addr, R_PDE_CLASS_0 + 1,
521 ((bkt_map >> 32) & 0xffffffff));
522
523 xlr_nae_wreg(priv->base_addr, R_PDE_CLASS_1, (bkt_map & 0xffffffff));
524 xlr_nae_wreg(priv->base_addr, R_PDE_CLASS_1 + 1,
525 ((bkt_map >> 32) & 0xffffffff));
526
527 xlr_nae_wreg(priv->base_addr, R_PDE_CLASS_2, (bkt_map & 0xffffffff));
528 xlr_nae_wreg(priv->base_addr, R_PDE_CLASS_2 + 1,
529 ((bkt_map >> 32) & 0xffffffff));
530
531 xlr_nae_wreg(priv->base_addr, R_PDE_CLASS_3, (bkt_map & 0xffffffff));
532 xlr_nae_wreg(priv->base_addr, R_PDE_CLASS_3 + 1,
533 ((bkt_map >> 32) & 0xffffffff));
534}
535
2db0083d
A		 536/*
537 * Setup the Message ring credits, bucket size and other
538 * common configuration
539 */
6f98b1a2
GR		 540static void xlr_config_common(struct xlr_net_priv *priv)
541{
542 struct xlr_fmn_info *gmac = priv->nd->gmac_fmn_info;
543 int start_stn_id = gmac->start_stn_id;
544 int end_stn_id = gmac->end_stn_id;
545 int *bucket_size = priv->nd->bucket_size;
546 int i, j;
547
548 /* Setting non-core MsgBktSize(0x321 - 0x325) */
549 for (i = start_stn_id; i <= end_stn_id; i++) {
550 xlr_nae_wreg(priv->base_addr,
551 R_GMAC_RFR0_BUCKET_SIZE + i - start_stn_id,
552 bucket_size[i]);
553 }
554
2db0083d
A		 555 /*
556 * Setting non-core Credit counter register
557 * Distributing Gmac's credit to CPU's
558 */
6f98b1a2
GR		 559 for (i = 0; i < 8; i++) {
560 for (j = 0; j < 8; j++)
561 xlr_nae_wreg(priv->base_addr,
562 (R_CC_CPU0_0 + (i * 8)) + j,
563 gmac->credit_config[(i * 8) + j]);
564 }
565
566 xlr_nae_wreg(priv->base_addr, R_MSG_TX_THRESHOLD, 3);
567 xlr_nae_wreg(priv->base_addr, R_DMACR0, 0xffffffff);
568 xlr_nae_wreg(priv->base_addr, R_DMACR1, 0xffffffff);
569 xlr_nae_wreg(priv->base_addr, R_DMACR2, 0xffffffff);
570 xlr_nae_wreg(priv->base_addr, R_DMACR3, 0xffffffff);
571 xlr_nae_wreg(priv->base_addr, R_FREEQCARVE, 0);
572
573 xlr_net_fill_rx_ring(priv->ndev);
574 nlm_register_fmn_handler(start_stn_id, end_stn_id, xlr_net_fmn_handler,
575 NULL);
576}
577
578static void xlr_config_translate_table(struct xlr_net_priv *priv)
579{
580 u32 cpu_mask;
581 u32 val;
582 int bkts[32]; /* one bucket is assumed for each cpu */
583 int b1, b2, c1, c2, i, j, k;
584 int use_bkt;
585
586 use_bkt = 0;
587 cpu_mask = priv->nd->cpu_mask;
588
589 pr_info("Using %s-based distribution\n",
590 (use_bkt) ? "bucket" : "class");
591 j = 0;
592 for (i = 0; i < 32; i++) {
593 if ((1 << i) & cpu_mask) {
594 /* for each cpu, mark the 4+threadid bucket */
595 bkts[j] = ((i / 4) * 8) + (i % 4);
596 j++;
597 }
598 }
599
600 /*configure the 128 * 9 Translation table to send to available buckets*/
601 k = 0;
602 c1 = 3;
603 c2 = 0;
604 for (i = 0; i < 64; i++) {
2db0083d
A		 605 /*
606 * On use_bkt set the b0, b1 are used, else
6f98b1a2
GR		 607 * the 4 classes are used, here implemented
608 * a logic to distribute the packets to the
609 * buckets equally or based on the class
610 */
611 c1 = (c1 + 1) & 3;
612 c2 = (c1 + 1) & 3;
613 b1 = bkts[k];
614 k = (k + 1) % j;
615 b2 = bkts[k];
616 k = (k + 1) % j;
617 val = ((c1 << 23) | (b1 << 17) | (use_bkt << 16) |
618 (c2 << 7) | (b2 << 1) | (use_bkt << 0));
619
620 val = ((c1 << 23) | (b1 << 17) | (use_bkt << 16) |
621 (c2 << 7) | (b2 << 1) | (use_bkt << 0));
622 dev_dbg(&priv->ndev->dev, "Table[%d] b1=%d b2=%d c1=%d c2=%d\n",
623 i, b1, b2, c1, c2);
624 xlr_nae_wreg(priv->base_addr, R_TRANSLATETABLE + i, val);
625 c1 = c2;
626 }
627}
628
629static void xlr_config_parser(struct xlr_net_priv *priv)
630{
631 u32 val;
632
633 /* Mark it as ETHERNET type */
634 xlr_nae_wreg(priv->base_addr, R_L2TYPE_0, 0x01);
635
636 /* Use 7bit CRChash for flow classification with 127 as CRC polynomial*/
637 xlr_nae_wreg(priv->base_addr, R_PARSERCONFIGREG,
638 ((0x7f << 8) | (1 << 1)));
639
640 /* configure the parser : L2 Type is configured in the bootloader */
641 /* extract IP: src, dest protocol */
642 xlr_nae_wreg(priv->base_addr, R_L3CTABLE,
643 (9 << 20) | (1 << 19) | (1 << 18) | (0x01 << 16) |
644 (0x0800 << 0));
645 xlr_nae_wreg(priv->base_addr, R_L3CTABLE + 1,
646 (9 << 25) | (1 << 21) | (12 << 14) | (4 << 10) |
647 (16 << 4) | 4);
648
649 /* Configure to extract SRC port and Dest port for TCP and UDP pkts */
650 xlr_nae_wreg(priv->base_addr, R_L4CTABLE, 6);
651 xlr_nae_wreg(priv->base_addr, R_L4CTABLE + 2, 17);
652 val = ((0 << 21) | (2 << 17) | (2 << 11) | (2 << 7));
653 xlr_nae_wreg(priv->base_addr, R_L4CTABLE + 1, val);
654 xlr_nae_wreg(priv->base_addr, R_L4CTABLE + 3, val);
655
656 xlr_config_translate_table(priv);
657}
658
659static int xlr_phy_write(u32 *base_addr, int phy_addr, int regnum, u16 val)
660{
661 unsigned long timeout, stoptime, checktime;
662 int timedout;
663
664 /* 100ms timeout*/
665 timeout = msecs_to_jiffies(100);
666 stoptime = jiffies + timeout;
667 timedout = 0;
668
669 xlr_nae_wreg(base_addr, R_MII_MGMT_ADDRESS, (phy_addr << 8) | regnum);
670
671 /* Write the data which starts the write cycle */
672 xlr_nae_wreg(base_addr, R_MII_MGMT_WRITE_DATA, (u32) val);
673
674 /* poll for the read cycle to complete */
675 while (!timedout) {
676 checktime = jiffies;
677 if (xlr_nae_rdreg(base_addr, R_MII_MGMT_INDICATORS) == 0)
678 break;
679 timedout = time_after(checktime, stoptime);
680 }
681 if (timedout) {
682 pr_info("Phy device write err: device busy");
683 return -EBUSY;
684 }
685
686 return 0;
687}
688
689static int xlr_phy_read(u32 *base_addr, int phy_addr, int regnum)
690{
691 unsigned long timeout, stoptime, checktime;
692 int timedout;
693
694 /* 100ms timeout*/
695 timeout = msecs_to_jiffies(100);
696 stoptime = jiffies + timeout;
697 timedout = 0;
698
699 /* setup the phy reg to be used */
700 xlr_nae_wreg(base_addr, R_MII_MGMT_ADDRESS,
701 (phy_addr << 8) | (regnum << 0));
702
703 /* Issue the read command */
704 xlr_nae_wreg(base_addr, R_MII_MGMT_COMMAND,
705 (1 << O_MII_MGMT_COMMAND__rstat));
706
707
708 /* poll for the read cycle to complete */
709 while (!timedout) {
710 checktime = jiffies;
711 if (xlr_nae_rdreg(base_addr, R_MII_MGMT_INDICATORS) == 0)
712 break;
713 timedout = time_after(checktime, stoptime);
714 }
715 if (timedout) {
716 pr_info("Phy device read err: device busy");
717 return -EBUSY;
718 }
719
720 /* clear the read cycle */
721 xlr_nae_wreg(base_addr, R_MII_MGMT_COMMAND, 0);
722
723 /* Read the data */
724 return xlr_nae_rdreg(base_addr, R_MII_MGMT_STATUS);
725}
726
727static int xlr_mii_write(struct mii_bus *bus, int phy_addr, int regnum, u16 val)
728{
729 struct xlr_net_priv *priv = bus->priv;
730 int ret;
731
732 ret = xlr_phy_write(priv->mii_addr, phy_addr, regnum, val);
733 dev_dbg(&priv->ndev->dev, "mii_write phy %d : %d <- %x [%x]\n",
734 phy_addr, regnum, val, ret);
735 return ret;
736}
737
738static int xlr_mii_read(struct mii_bus *bus, int phy_addr, int regnum)
739{
740 struct xlr_net_priv *priv = bus->priv;
741 int ret;
742
743 ret = xlr_phy_read(priv->mii_addr, phy_addr, regnum);
744 dev_dbg(&priv->ndev->dev, "mii_read phy %d : %d [%x]\n",
745 phy_addr, regnum, ret);
746 return ret;
747}
748
2db0083d
A		 749/*
750 * XLR ports are RGMII. XLS ports are SGMII mostly except the port0,
6f98b1a2
GR		 751 * which can be configured either SGMII or RGMII, considered SGMII
752 * by default, if board setup to RGMII the port_type need to set
753 * accordingly.Serdes and PCS layer need to configured for SGMII
754 */
755static void xlr_sgmii_init(struct xlr_net_priv *priv)
756{
757 int phy;
758
759 xlr_phy_write(priv->serdes_addr, 26, 0, 0x6DB0);
760 xlr_phy_write(priv->serdes_addr, 26, 1, 0xFFFF);
761 xlr_phy_write(priv->serdes_addr, 26, 2, 0xB6D0);
762 xlr_phy_write(priv->serdes_addr, 26, 3, 0x00FF);
763 xlr_phy_write(priv->serdes_addr, 26, 4, 0x0000);
764 xlr_phy_write(priv->serdes_addr, 26, 5, 0x0000);
765 xlr_phy_write(priv->serdes_addr, 26, 6, 0x0005);
766 xlr_phy_write(priv->serdes_addr, 26, 7, 0x0001);
767 xlr_phy_write(priv->serdes_addr, 26, 8, 0x0000);
768 xlr_phy_write(priv->serdes_addr, 26, 9, 0x0000);
769 xlr_phy_write(priv->serdes_addr, 26, 10, 0x0000);
770
771 /* program GPIO values for serdes init parameters */
772 xlr_nae_wreg(priv->gpio_addr, 0x20, 0x7e6802);
773 xlr_nae_wreg(priv->gpio_addr, 0x10, 0x7104);
774
775 xlr_nae_wreg(priv->gpio_addr, 0x22, 0x7e6802);
776 xlr_nae_wreg(priv->gpio_addr, 0x21, 0x7104);
777
778 /* enable autoneg - more magic */
779 phy = priv->port_id % 4 + 27;
780 xlr_phy_write(priv->pcs_addr, phy, 0, 0x1000);
781 xlr_phy_write(priv->pcs_addr, phy, 0, 0x0200);
782}
783
784void xlr_set_gmac_speed(struct xlr_net_priv *priv)
785{
786 struct phy_device *phydev = priv->mii_bus->phy_map[priv->phy_addr];
787 int speed;
788
789 if (phydev->interface == PHY_INTERFACE_MODE_SGMII)
790 xlr_sgmii_init(priv);
791
792 if (phydev->speed != priv->phy_speed) {
793 pr_info("change %d to %d\n", priv->phy_speed, phydev->speed);
794 speed = phydev->speed;
795 if (speed == SPEED_1000) {
796 /* Set interface to Byte mode */
797 xlr_nae_wreg(priv->base_addr, R_MAC_CONFIG_2, 0x7217);
798 priv->phy_speed = speed;
799 } else if (speed == SPEED_100 || speed == SPEED_10) {
800 /* Set interface to Nibble mode */
801 xlr_nae_wreg(priv->base_addr, R_MAC_CONFIG_2, 0x7117);
802 priv->phy_speed = speed;
803 }
804 /* Set SGMII speed in Interface controll reg */
805 if (phydev->interface == PHY_INTERFACE_MODE_SGMII) {
806 if (speed == SPEED_10)
807 xlr_nae_wreg(priv->base_addr,
808 R_INTERFACE_CONTROL, SGMII_SPEED_10);
809 if (speed == SPEED_100)
810 xlr_nae_wreg(priv->base_addr,
811 R_INTERFACE_CONTROL, SGMII_SPEED_100);
812 if (speed == SPEED_1000)
813 xlr_nae_wreg(priv->base_addr,
814 R_INTERFACE_CONTROL, SGMII_SPEED_1000);
815 }
816 if (speed == SPEED_10)
817 xlr_nae_wreg(priv->base_addr, R_CORECONTROL, 0x2);
818 if (speed == SPEED_100)
819 xlr_nae_wreg(priv->base_addr, R_CORECONTROL, 0x1);
820 if (speed == SPEED_1000)
821 xlr_nae_wreg(priv->base_addr, R_CORECONTROL, 0x0);
822 }
823 pr_info("gmac%d : %dMbps\n", priv->port_id, priv->phy_speed);
824}
825
826static void xlr_gmac_link_adjust(struct net_device *ndev)
827{
828 struct xlr_net_priv *priv = netdev_priv(ndev);
829 struct phy_device *phydev = priv->mii_bus->phy_map[priv->phy_addr];
830 u32 intreg;
831
832 intreg = xlr_nae_rdreg(priv->base_addr, R_INTREG);
833 if (phydev->link) {
834 if (phydev->speed != priv->phy_speed) {
835 pr_info("gmac%d : Link up\n", priv->port_id);
836 xlr_set_gmac_speed(priv);
837 }
838 } else {
839 pr_info("gmac%d : Link down\n", priv->port_id);
840 xlr_set_gmac_speed(priv);
841 }
842}
843
844static int xlr_mii_probe(struct xlr_net_priv *priv)
845{
846 struct phy_device *phydev = priv->mii_bus->phy_map[priv->phy_addr];
847
848 if (!phydev) {
849 pr_err("no PHY found on phy_addr %d\n", priv->phy_addr);
850 return -ENODEV;
851 }
852
853 /* Attach MAC to PHY */
854 phydev = phy_connect(priv->ndev, dev_name(&phydev->dev),
855 &xlr_gmac_link_adjust, priv->nd->phy_interface);
856
857 if (IS_ERR(phydev)) {
858 pr_err("could not attach PHY\n");
859 return PTR_ERR(phydev);
860 }
861 phydev->supported &= (ADVERTISED_10baseT_Full
862 | ADVERTISED_10baseT_Half
863 | ADVERTISED_100baseT_Full
864 | ADVERTISED_100baseT_Half
865 | ADVERTISED_1000baseT_Full
866 | ADVERTISED_Autoneg
867 | ADVERTISED_MII);
868
869 phydev->advertising = phydev->supported;
870 pr_info("attached PHY driver [%s] (mii_bus:phy_addr=%s\n",
871 phydev->drv->name, dev_name(&phydev->dev));
872 return 0;
873}
874
875static int xlr_setup_mdio(struct xlr_net_priv *priv,
876 struct platform_device *pdev)
877{
878 int err;
879
880 priv->phy_addr = priv->nd->phy_addr;
881 priv->mii_bus = mdiobus_alloc();
882 if (!priv->mii_bus) {
883 pr_err("mdiobus alloc failed\n");
884 return -ENOMEM;
885 }
886
887 priv->mii_bus->priv = priv;
888 priv->mii_bus->name = "xlr-mdio";
889 snprintf(priv->mii_bus->id, MII_BUS_ID_SIZE, "%s-%d",
890 priv->mii_bus->name, priv->port_id);
891 priv->mii_bus->read = xlr_mii_read;
892 priv->mii_bus->write = xlr_mii_write;
893 priv->mii_bus->parent = &pdev->dev;
894 priv->mii_bus->irq = kmalloc(sizeof(int)*PHY_MAX_ADDR, GFP_KERNEL);
895 priv->mii_bus->irq[priv->phy_addr] = priv->ndev->irq;
896
897 /* Scan only the enabled address */
898 priv->mii_bus->phy_mask = ~(1 << priv->phy_addr);
899
900 /* setting clock divisor to 54 */
901 xlr_nae_wreg(priv->base_addr, R_MII_MGMT_CONFIG, 0x7);
902
903 err = mdiobus_register(priv->mii_bus);
904 if (err) {
905 mdiobus_free(priv->mii_bus);
906 pr_err("mdio bus registration failed\n");
907 return err;
908 }
909
9d2ea4de 910 pr_info("Registered mdio bus id : %s\n", priv->mii_bus->id);
6f98b1a2
GR		 911 err = xlr_mii_probe(priv);
912 if (err) {
913 mdiobus_free(priv->mii_bus);
914 return err;
915 }
916 return 0;
917}
918
919static void xlr_port_enable(struct xlr_net_priv *priv)
920{
921 u32 prid = (read_c0_prid() & 0xf000);
922
923 /* Setup MAC_CONFIG reg if (xls & rgmii) */
924 if ((prid == 0x8000 || prid == 0x4000 || prid == 0xc000) &&
925 priv->nd->phy_interface == PHY_INTERFACE_MODE_RGMII)
926 xlr_reg_update(priv->base_addr, R_RX_CONTROL,
927 (1 << O_RX_CONTROL__RGMII), (1 << O_RX_CONTROL__RGMII));
928
929 /* Rx Tx enable */
930 xlr_reg_update(priv->base_addr, R_MAC_CONFIG_1,
931 ((1 << O_MAC_CONFIG_1__rxen) | (1 << O_MAC_CONFIG_1__txen) |
932 (1 << O_MAC_CONFIG_1__rxfc) | (1 << O_MAC_CONFIG_1__txfc)),
933 ((1 << O_MAC_CONFIG_1__rxen) | (1 << O_MAC_CONFIG_1__txen) |
934 (1 << O_MAC_CONFIG_1__rxfc) | (1 << O_MAC_CONFIG_1__txfc)));
935
936 /* Setup tx control reg */
937 xlr_reg_update(priv->base_addr, R_TX_CONTROL,
938 ((1 << O_TX_CONTROL__TxEnable) |
939 (512 << O_TX_CONTROL__TxThreshold)), 0x3fff);
940
941 /* Setup rx control reg */
942 xlr_reg_update(priv->base_addr, R_RX_CONTROL,
943 1 << O_RX_CONTROL__RxEnable, 1 << O_RX_CONTROL__RxEnable);
944}
945
946static void xlr_port_disable(struct xlr_net_priv *priv)
947{
948 /* Setup MAC_CONFIG reg */
949 /* Rx Tx disable*/
950 xlr_reg_update(priv->base_addr, R_MAC_CONFIG_1,
951 ((1 << O_MAC_CONFIG_1__rxen) | (1 << O_MAC_CONFIG_1__txen) |
952 (1 << O_MAC_CONFIG_1__rxfc) | (1 << O_MAC_CONFIG_1__txfc)),
953 0x0);
954
955 /* Setup tx control reg */
956 xlr_reg_update(priv->base_addr, R_TX_CONTROL,
957 ((1 << O_TX_CONTROL__TxEnable) |
958 (512 << O_TX_CONTROL__TxThreshold)), 0);
959
960 /* Setup rx control reg */
961 xlr_reg_update(priv->base_addr, R_RX_CONTROL,
962 1 << O_RX_CONTROL__RxEnable, 0);
963}
964
965/* Initialization of gmac */
966static int xlr_gmac_init(struct xlr_net_priv *priv,
967 struct platform_device *pdev)
968{
969 int ret;
970
971 pr_info("Initializing the gmac%d\n", priv->port_id);
972
973 xlr_port_disable(priv);
974 xlr_nae_wreg(priv->base_addr, R_DESC_PACK_CTRL,
975 (1 << O_DESC_PACK_CTRL__MaxEntry)
976 | (BYTE_OFFSET << O_DESC_PACK_CTRL__ByteOffset)
977 | (1600 << O_DESC_PACK_CTRL__RegularSize));
978
979 ret = xlr_setup_mdio(priv, pdev);
980 if (ret)
981 return ret;
982 xlr_port_enable(priv);
983
984 /* Enable Full-duplex/1000Mbps/CRC */
985 xlr_nae_wreg(priv->base_addr, R_MAC_CONFIG_2, 0x7217);
986 /* speed 2.5Mhz */
987 xlr_nae_wreg(priv->base_addr, R_CORECONTROL, 0x02);
988 /* Setup Interrupt mask reg */
989 xlr_nae_wreg(priv->base_addr, R_INTMASK,
990 (1 << O_INTMASK__TxIllegal) |
991 (1 << O_INTMASK__MDInt) |
992 (1 << O_INTMASK__TxFetchError) |
993 (1 << O_INTMASK__P2PSpillEcc) |
994 (1 << O_INTMASK__TagFull) |
995 (1 << O_INTMASK__Underrun) |
996 (1 << O_INTMASK__Abort)
997 );
998
999 /* Clear all stats */
1000 xlr_reg_update(priv->base_addr, R_STATCTRL,
1001 0, 1 << O_STATCTRL__ClrCnt);
1002 xlr_reg_update(priv->base_addr, R_STATCTRL,
1003 1 << O_STATCTRL__ClrCnt, 1 << O_STATCTRL__ClrCnt);
1004 return 0;
1005}
1006
1007static int xlr_net_probe(struct platform_device *pdev)
1008{
1009 struct xlr_net_priv *priv = NULL;
1010 struct net_device *ndev;
1011 struct resource *res;
1012 int mac, err;
1013
1014 mac = pdev->id;
1015 ndev = alloc_etherdev_mq(sizeof(struct xlr_net_priv), 32);
1016 if (!ndev) {
1017 pr_err("Allocation of Ethernet device failed\n");
1018 return -ENOMEM;
1019 }
1020
1021 priv = netdev_priv(ndev);
1022 priv->pdev = pdev;
1023 priv->ndev = ndev;
1024 priv->port_id = mac;
1025 priv->nd = (struct xlr_net_data *)pdev->dev.platform_data;
1026
1027 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1028 if (res == NULL) {
1029 pr_err("No memory resource for MAC %d\n", mac);
1030 err = -ENODEV;
1031 goto err_gmac;
1032 }
1033
803c83fc 1034 ndev->base_addr = (unsigned long) devm_ioremap_resource
6f98b1a2 1035 (&pdev->dev, res);
803c83fc 1036 if (IS_ERR_VALUE(ndev->base_addr)) {
c639b9fb
WY		 1037 err = ndev->base_addr;
1038 goto err_gmac;
6f98b1a2
GR		 1039 }
1040
1041 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
1042 if (res == NULL) {
1043 pr_err("No irq resource for MAC %d\n", mac);
1044 err = -ENODEV;
1045 goto err_gmac;
1046 }
1047 ndev->irq = res->start;
1048
1049 priv->mii_addr = priv->nd->mii_addr;
1050 priv->serdes_addr = priv->nd->serdes_addr;
1051 priv->pcs_addr = priv->nd->pcs_addr;
1052 priv->gpio_addr = priv->nd->gpio_addr;
1053 priv->base_addr = (u32 *) ndev->base_addr;
1054
1055 mac_to_ndev[mac] = ndev;
1056 ndev->netdev_ops = &xlr_netdev_ops;
1057 ndev->watchdog_timeo = HZ;
1058
1059 /* Setup Mac address and Rx mode */
1060 eth_hw_addr_random(ndev);
1061 xlr_hw_set_mac_addr(ndev);
1062 xlr_set_rx_mode(ndev);
1063
1064 priv->num_rx_desc += MAX_NUM_DESC_SPILL;
1065 SET_ETHTOOL_OPS(ndev, &xlr_ethtool_ops);
1066 SET_NETDEV_DEV(ndev, &pdev->dev);
1067
1068 /* Common registers, do one time initialization */
1069 if (mac == 0 || mac == 4) {
1070 xlr_config_fifo_spill_area(priv);
1071 /* Configure PDE to Round-Robin pkt distribution */
1072 xlr_config_pde(priv);
1073 xlr_config_parser(priv);
1074 }
1075 /* Call init with respect to port */
1076 if (strcmp(res->name, "gmac") == 0) {
1077 err = xlr_gmac_init(priv, pdev);
1078 if (err) {
1079 pr_err("gmac%d init failed\n", mac);
1080 goto err_gmac;
1081 }
1082 }
1083
1084 if (mac == 0 || mac == 4)
1085 xlr_config_common(priv);
1086
1087 err = register_netdev(ndev);
1088 if (err)
1089 goto err_netdev;
1090 platform_set_drvdata(pdev, priv);
1091 return 0;
1092
1093err_netdev:
1094 mdiobus_free(priv->mii_bus);
1095err_gmac:
1096 free_netdev(ndev);
1097 return err;
1098}
1099
1100static int xlr_net_remove(struct platform_device *pdev)
1101{
1102 struct xlr_net_priv *priv = platform_get_drvdata(pdev);
1103 unregister_netdev(priv->ndev);
1104 mdiobus_unregister(priv->mii_bus);
1105 mdiobus_free(priv->mii_bus);
1106 free_netdev(priv->ndev);
1107 return 0;
1108}
1109
1110static struct platform_driver xlr_net_driver = {
1111 .probe = xlr_net_probe,
1112 .remove = xlr_net_remove,
1113 .driver = {
1114 .name = "xlr-net",
1115 .owner = THIS_MODULE,
1116 },
1117};
1118
1119module_platform_driver(xlr_net_driver);
1120
1121MODULE_AUTHOR("Ganesan Ramalingam <ganesanr@broadcom.com>");
1122MODULE_DESCRIPTION("Ethernet driver for Netlogic XLR/XLS");
1123MODULE_LICENSE("Dual BSD/GPL");
1124MODULE_ALIAS("platform:xlr-net");
Linux kernel - Deliverables
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