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staging/rdma/hfi1: Remove space after cast
[deliverable/linux.git] / drivers / staging / rdma / hfi1 / chip.c
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77241056
MM		 1/*
2 *
3 * This file is provided under a dual BSD/GPLv2 license. When using or
4 * redistributing this file, you may do so under either license.
5 *
6 * GPL LICENSE SUMMARY
7 *
8 * Copyright(c) 2015 Intel Corporation.
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of version 2 of the GNU General Public License as
12 * published by the Free Software Foundation.
13 *
14 * This program is distributed in the hope that it will be useful, but
15 * WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
17 * General Public License for more details.
18 *
19 * BSD LICENSE
20 *
21 * Copyright(c) 2015 Intel Corporation.
22 *
23 * Redistribution and use in source and binary forms, with or without
24 * modification, are permitted provided that the following conditions
25 * are met:
26 *
27 * - Redistributions of source code must retain the above copyright
28 * notice, this list of conditions and the following disclaimer.
29 * - Redistributions in binary form must reproduce the above copyright
30 * notice, this list of conditions and the following disclaimer in
31 * the documentation and/or other materials provided with the
32 * distribution.
33 * - Neither the name of Intel Corporation nor the names of its
34 * contributors may be used to endorse or promote products derived
35 * from this software without specific prior written permission.
36 *
37 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
38 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
39 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
40 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
41 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
42 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
43 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
44 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
45 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
46 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
47 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
48 *
49 */
50
51/*
52 * This file contains all of the code that is specific to the HFI chip
53 */
54
55#include <linux/pci.h>
56#include <linux/delay.h>
57#include <linux/interrupt.h>
58#include <linux/module.h>
59
60#include "hfi.h"
61#include "trace.h"
62#include "mad.h"
63#include "pio.h"
64#include "sdma.h"
65#include "eprom.h"
5d9157aa 66#include "efivar.h"
8ebd4cf1 67#include "platform.h"
affa48de 68#include "aspm.h"
77241056
MM		 69
70#define NUM_IB_PORTS 1
71
72uint kdeth_qp;
73module_param_named(kdeth_qp, kdeth_qp, uint, S_IRUGO);
74MODULE_PARM_DESC(kdeth_qp, "Set the KDETH queue pair prefix");
75
76uint num_vls = HFI1_MAX_VLS_SUPPORTED;
77module_param(num_vls, uint, S_IRUGO);
78MODULE_PARM_DESC(num_vls, "Set number of Virtual Lanes to use (1-8)");
79
80/*
81 * Default time to aggregate two 10K packets from the idle state
82 * (timer not running). The timer starts at the end of the first packet,
83 * so only the time for one 10K packet and header plus a bit extra is needed.
84 * 10 * 1024 + 64 header byte = 10304 byte
85 * 10304 byte / 12.5 GB/s = 824.32ns
86 */
87uint rcv_intr_timeout = (824 + 16); /* 16 is for coalescing interrupt */
88module_param(rcv_intr_timeout, uint, S_IRUGO);
89MODULE_PARM_DESC(rcv_intr_timeout, "Receive interrupt mitigation timeout in ns");
90
91uint rcv_intr_count = 16; /* same as qib */
92module_param(rcv_intr_count, uint, S_IRUGO);
93MODULE_PARM_DESC(rcv_intr_count, "Receive interrupt mitigation count");
94
95ushort link_crc_mask = SUPPORTED_CRCS;
96module_param(link_crc_mask, ushort, S_IRUGO);
97MODULE_PARM_DESC(link_crc_mask, "CRCs to use on the link");
98
99uint loopback;
100module_param_named(loopback, loopback, uint, S_IRUGO);
101MODULE_PARM_DESC(loopback, "Put into loopback mode (1 = serdes, 3 = external cable");
102
103/* Other driver tunables */
104uint rcv_intr_dynamic = 1; /* enable dynamic mode for rcv int mitigation*/
105static ushort crc_14b_sideband = 1;
106static uint use_flr = 1;
107uint quick_linkup; /* skip LNI */
108
109struct flag_table {
110 u64 flag; /* the flag */
111 char *str; /* description string */
112 u16 extra; /* extra information */
113 u16 unused0;
114 u32 unused1;
115};
116
117/* str must be a string constant */
118#define FLAG_ENTRY(str, extra, flag) {flag, str, extra}
119#define FLAG_ENTRY0(str, flag) {flag, str, 0}
120
121/* Send Error Consequences */
122#define SEC_WRITE_DROPPED 0x1
123#define SEC_PACKET_DROPPED 0x2
124#define SEC_SC_HALTED 0x4 /* per-context only */
125#define SEC_SPC_FREEZE 0x8 /* per-HFI only */
126
77241056 127#define MIN_KERNEL_KCTXTS 2
82c2611d 128#define FIRST_KERNEL_KCTXT 1
77241056
MM		 129#define NUM_MAP_REGS 32
130
131/* Bit offset into the GUID which carries HFI id information */
132#define GUID_HFI_INDEX_SHIFT 39
133
134/* extract the emulation revision */
135#define emulator_rev(dd) ((dd)->irev >> 8)
136/* parallel and serial emulation versions are 3 and 4 respectively */
137#define is_emulator_p(dd) ((((dd)->irev) & 0xf) == 3)
138#define is_emulator_s(dd) ((((dd)->irev) & 0xf) == 4)
139
140/* RSM fields */
141
142/* packet type */
143#define IB_PACKET_TYPE 2ull
144#define QW_SHIFT 6ull
145/* QPN[7..1] */
146#define QPN_WIDTH 7ull
147
148/* LRH.BTH: QW 0, OFFSET 48 - for match */
149#define LRH_BTH_QW 0ull
150#define LRH_BTH_BIT_OFFSET 48ull
151#define LRH_BTH_OFFSET(off) ((LRH_BTH_QW << QW_SHIFT) | (off))
152#define LRH_BTH_MATCH_OFFSET LRH_BTH_OFFSET(LRH_BTH_BIT_OFFSET)
153#define LRH_BTH_SELECT
154#define LRH_BTH_MASK 3ull
155#define LRH_BTH_VALUE 2ull
156
157/* LRH.SC[3..0] QW 0, OFFSET 56 - for match */
158#define LRH_SC_QW 0ull
159#define LRH_SC_BIT_OFFSET 56ull
160#define LRH_SC_OFFSET(off) ((LRH_SC_QW << QW_SHIFT) | (off))
161#define LRH_SC_MATCH_OFFSET LRH_SC_OFFSET(LRH_SC_BIT_OFFSET)
162#define LRH_SC_MASK 128ull
163#define LRH_SC_VALUE 0ull
164
165/* SC[n..0] QW 0, OFFSET 60 - for select */
166#define LRH_SC_SELECT_OFFSET ((LRH_SC_QW << QW_SHIFT) | (60ull))
167
168/* QPN[m+n:1] QW 1, OFFSET 1 */
169#define QPN_SELECT_OFFSET ((1ull << QW_SHIFT) | (1ull))
170
171/* defines to build power on SC2VL table */
172#define SC2VL_VAL( \
173 num, \
174 sc0, sc0val, \
175 sc1, sc1val, \
176 sc2, sc2val, \
177 sc3, sc3val, \
178 sc4, sc4val, \
179 sc5, sc5val, \
180 sc6, sc6val, \
181 sc7, sc7val) \
182( \
183 ((u64)(sc0val) << SEND_SC2VLT##num##_SC##sc0##_SHIFT) | \
184 ((u64)(sc1val) << SEND_SC2VLT##num##_SC##sc1##_SHIFT) | \
185 ((u64)(sc2val) << SEND_SC2VLT##num##_SC##sc2##_SHIFT) | \
186 ((u64)(sc3val) << SEND_SC2VLT##num##_SC##sc3##_SHIFT) | \
187 ((u64)(sc4val) << SEND_SC2VLT##num##_SC##sc4##_SHIFT) | \
188 ((u64)(sc5val) << SEND_SC2VLT##num##_SC##sc5##_SHIFT) | \
189 ((u64)(sc6val) << SEND_SC2VLT##num##_SC##sc6##_SHIFT) | \
190 ((u64)(sc7val) << SEND_SC2VLT##num##_SC##sc7##_SHIFT) \
191)
192
193#define DC_SC_VL_VAL( \
194 range, \
195 e0, e0val, \
196 e1, e1val, \
197 e2, e2val, \
198 e3, e3val, \
199 e4, e4val, \
200 e5, e5val, \
201 e6, e6val, \
202 e7, e7val, \
203 e8, e8val, \
204 e9, e9val, \
205 e10, e10val, \
206 e11, e11val, \
207 e12, e12val, \
208 e13, e13val, \
209 e14, e14val, \
210 e15, e15val) \
211( \
212 ((u64)(e0val) << DCC_CFG_SC_VL_TABLE_##range##_ENTRY##e0##_SHIFT) | \
213 ((u64)(e1val) << DCC_CFG_SC_VL_TABLE_##range##_ENTRY##e1##_SHIFT) | \
214 ((u64)(e2val) << DCC_CFG_SC_VL_TABLE_##range##_ENTRY##e2##_SHIFT) | \
215 ((u64)(e3val) << DCC_CFG_SC_VL_TABLE_##range##_ENTRY##e3##_SHIFT) | \
216 ((u64)(e4val) << DCC_CFG_SC_VL_TABLE_##range##_ENTRY##e4##_SHIFT) | \
217 ((u64)(e5val) << DCC_CFG_SC_VL_TABLE_##range##_ENTRY##e5##_SHIFT) | \
218 ((u64)(e6val) << DCC_CFG_SC_VL_TABLE_##range##_ENTRY##e6##_SHIFT) | \
219 ((u64)(e7val) << DCC_CFG_SC_VL_TABLE_##range##_ENTRY##e7##_SHIFT) | \
220 ((u64)(e8val) << DCC_CFG_SC_VL_TABLE_##range##_ENTRY##e8##_SHIFT) | \
221 ((u64)(e9val) << DCC_CFG_SC_VL_TABLE_##range##_ENTRY##e9##_SHIFT) | \
222 ((u64)(e10val) << DCC_CFG_SC_VL_TABLE_##range##_ENTRY##e10##_SHIFT) | \
223 ((u64)(e11val) << DCC_CFG_SC_VL_TABLE_##range##_ENTRY##e11##_SHIFT) | \
224 ((u64)(e12val) << DCC_CFG_SC_VL_TABLE_##range##_ENTRY##e12##_SHIFT) | \
225 ((u64)(e13val) << DCC_CFG_SC_VL_TABLE_##range##_ENTRY##e13##_SHIFT) | \
226 ((u64)(e14val) << DCC_CFG_SC_VL_TABLE_##range##_ENTRY##e14##_SHIFT) | \
227 ((u64)(e15val) << DCC_CFG_SC_VL_TABLE_##range##_ENTRY##e15##_SHIFT) \
228)
229
230/* all CceStatus sub-block freeze bits */
231#define ALL_FROZE (CCE_STATUS_SDMA_FROZE_SMASK \
232 | CCE_STATUS_RXE_FROZE_SMASK \
233 | CCE_STATUS_TXE_FROZE_SMASK \
234 | CCE_STATUS_TXE_PIO_FROZE_SMASK)
235/* all CceStatus sub-block TXE pause bits */
236#define ALL_TXE_PAUSE (CCE_STATUS_TXE_PIO_PAUSED_SMASK \
237 | CCE_STATUS_TXE_PAUSED_SMASK \
238 | CCE_STATUS_SDMA_PAUSED_SMASK)
239/* all CceStatus sub-block RXE pause bits */
240#define ALL_RXE_PAUSE CCE_STATUS_RXE_PAUSED_SMASK
241
242/*
243 * CCE Error flags.
244 */
245static struct flag_table cce_err_status_flags[] = {
246/* 0*/ FLAG_ENTRY0("CceCsrParityErr",
247 CCE_ERR_STATUS_CCE_CSR_PARITY_ERR_SMASK),
248/* 1*/ FLAG_ENTRY0("CceCsrReadBadAddrErr",
249 CCE_ERR_STATUS_CCE_CSR_READ_BAD_ADDR_ERR_SMASK),
250/* 2*/ FLAG_ENTRY0("CceCsrWriteBadAddrErr",
251 CCE_ERR_STATUS_CCE_CSR_WRITE_BAD_ADDR_ERR_SMASK),
252/* 3*/ FLAG_ENTRY0("CceTrgtAsyncFifoParityErr",
253 CCE_ERR_STATUS_CCE_TRGT_ASYNC_FIFO_PARITY_ERR_SMASK),
254/* 4*/ FLAG_ENTRY0("CceTrgtAccessErr",
255 CCE_ERR_STATUS_CCE_TRGT_ACCESS_ERR_SMASK),
256/* 5*/ FLAG_ENTRY0("CceRspdDataParityErr",
257 CCE_ERR_STATUS_CCE_RSPD_DATA_PARITY_ERR_SMASK),
258/* 6*/ FLAG_ENTRY0("CceCli0AsyncFifoParityErr",
259 CCE_ERR_STATUS_CCE_CLI0_ASYNC_FIFO_PARITY_ERR_SMASK),
260/* 7*/ FLAG_ENTRY0("CceCsrCfgBusParityErr",
261 CCE_ERR_STATUS_CCE_CSR_CFG_BUS_PARITY_ERR_SMASK),
262/* 8*/ FLAG_ENTRY0("CceCli2AsyncFifoParityErr",
263 CCE_ERR_STATUS_CCE_CLI2_ASYNC_FIFO_PARITY_ERR_SMASK),
264/* 9*/ FLAG_ENTRY0("CceCli1AsyncFifoPioCrdtParityErr",
265 CCE_ERR_STATUS_CCE_CLI1_ASYNC_FIFO_PIO_CRDT_PARITY_ERR_SMASK),
266/*10*/ FLAG_ENTRY0("CceCli1AsyncFifoPioCrdtParityErr",
267 CCE_ERR_STATUS_CCE_CLI1_ASYNC_FIFO_SDMA_HD_PARITY_ERR_SMASK),
268/*11*/ FLAG_ENTRY0("CceCli1AsyncFifoRxdmaParityError",
269 CCE_ERR_STATUS_CCE_CLI1_ASYNC_FIFO_RXDMA_PARITY_ERROR_SMASK),
270/*12*/ FLAG_ENTRY0("CceCli1AsyncFifoDbgParityError",
271 CCE_ERR_STATUS_CCE_CLI1_ASYNC_FIFO_DBG_PARITY_ERROR_SMASK),
272/*13*/ FLAG_ENTRY0("PcicRetryMemCorErr",
273 CCE_ERR_STATUS_PCIC_RETRY_MEM_COR_ERR_SMASK),
274/*14*/ FLAG_ENTRY0("PcicRetryMemCorErr",
275 CCE_ERR_STATUS_PCIC_RETRY_SOT_MEM_COR_ERR_SMASK),
276/*15*/ FLAG_ENTRY0("PcicPostHdQCorErr",
277 CCE_ERR_STATUS_PCIC_POST_HD_QCOR_ERR_SMASK),
278/*16*/ FLAG_ENTRY0("PcicPostHdQCorErr",
279 CCE_ERR_STATUS_PCIC_POST_DAT_QCOR_ERR_SMASK),
280/*17*/ FLAG_ENTRY0("PcicPostHdQCorErr",
281 CCE_ERR_STATUS_PCIC_CPL_HD_QCOR_ERR_SMASK),
282/*18*/ FLAG_ENTRY0("PcicCplDatQCorErr",
283 CCE_ERR_STATUS_PCIC_CPL_DAT_QCOR_ERR_SMASK),
284/*19*/ FLAG_ENTRY0("PcicNPostHQParityErr",
285 CCE_ERR_STATUS_PCIC_NPOST_HQ_PARITY_ERR_SMASK),
286/*20*/ FLAG_ENTRY0("PcicNPostDatQParityErr",
287 CCE_ERR_STATUS_PCIC_NPOST_DAT_QPARITY_ERR_SMASK),
288/*21*/ FLAG_ENTRY0("PcicRetryMemUncErr",
289 CCE_ERR_STATUS_PCIC_RETRY_MEM_UNC_ERR_SMASK),
290/*22*/ FLAG_ENTRY0("PcicRetrySotMemUncErr",
291 CCE_ERR_STATUS_PCIC_RETRY_SOT_MEM_UNC_ERR_SMASK),
292/*23*/ FLAG_ENTRY0("PcicPostHdQUncErr",
293 CCE_ERR_STATUS_PCIC_POST_HD_QUNC_ERR_SMASK),
294/*24*/ FLAG_ENTRY0("PcicPostDatQUncErr",
295 CCE_ERR_STATUS_PCIC_POST_DAT_QUNC_ERR_SMASK),
296/*25*/ FLAG_ENTRY0("PcicCplHdQUncErr",
297 CCE_ERR_STATUS_PCIC_CPL_HD_QUNC_ERR_SMASK),
298/*26*/ FLAG_ENTRY0("PcicCplDatQUncErr",
299 CCE_ERR_STATUS_PCIC_CPL_DAT_QUNC_ERR_SMASK),
300/*27*/ FLAG_ENTRY0("PcicTransmitFrontParityErr",
301 CCE_ERR_STATUS_PCIC_TRANSMIT_FRONT_PARITY_ERR_SMASK),
302/*28*/ FLAG_ENTRY0("PcicTransmitBackParityErr",
303 CCE_ERR_STATUS_PCIC_TRANSMIT_BACK_PARITY_ERR_SMASK),
304/*29*/ FLAG_ENTRY0("PcicReceiveParityErr",
305 CCE_ERR_STATUS_PCIC_RECEIVE_PARITY_ERR_SMASK),
306/*30*/ FLAG_ENTRY0("CceTrgtCplTimeoutErr",
307 CCE_ERR_STATUS_CCE_TRGT_CPL_TIMEOUT_ERR_SMASK),
308/*31*/ FLAG_ENTRY0("LATriggered",
309 CCE_ERR_STATUS_LA_TRIGGERED_SMASK),
310/*32*/ FLAG_ENTRY0("CceSegReadBadAddrErr",
311 CCE_ERR_STATUS_CCE_SEG_READ_BAD_ADDR_ERR_SMASK),
312/*33*/ FLAG_ENTRY0("CceSegWriteBadAddrErr",
313 CCE_ERR_STATUS_CCE_SEG_WRITE_BAD_ADDR_ERR_SMASK),
314/*34*/ FLAG_ENTRY0("CceRcplAsyncFifoParityErr",
315 CCE_ERR_STATUS_CCE_RCPL_ASYNC_FIFO_PARITY_ERR_SMASK),
316/*35*/ FLAG_ENTRY0("CceRxdmaConvFifoParityErr",
317 CCE_ERR_STATUS_CCE_RXDMA_CONV_FIFO_PARITY_ERR_SMASK),
318/*36*/ FLAG_ENTRY0("CceMsixTableCorErr",
319 CCE_ERR_STATUS_CCE_MSIX_TABLE_COR_ERR_SMASK),
320/*37*/ FLAG_ENTRY0("CceMsixTableUncErr",
321 CCE_ERR_STATUS_CCE_MSIX_TABLE_UNC_ERR_SMASK),
322/*38*/ FLAG_ENTRY0("CceIntMapCorErr",
323 CCE_ERR_STATUS_CCE_INT_MAP_COR_ERR_SMASK),
324/*39*/ FLAG_ENTRY0("CceIntMapUncErr",
325 CCE_ERR_STATUS_CCE_INT_MAP_UNC_ERR_SMASK),
326/*40*/ FLAG_ENTRY0("CceMsixCsrParityErr",
327 CCE_ERR_STATUS_CCE_MSIX_CSR_PARITY_ERR_SMASK),
328/*41-63 reserved*/
329};
330
331/*
332 * Misc Error flags
333 */
334#define MES(text) MISC_ERR_STATUS_MISC_##text##_ERR_SMASK
335static struct flag_table misc_err_status_flags[] = {
336/* 0*/ FLAG_ENTRY0("CSR_PARITY", MES(CSR_PARITY)),
337/* 1*/ FLAG_ENTRY0("CSR_READ_BAD_ADDR", MES(CSR_READ_BAD_ADDR)),
338/* 2*/ FLAG_ENTRY0("CSR_WRITE_BAD_ADDR", MES(CSR_WRITE_BAD_ADDR)),
339/* 3*/ FLAG_ENTRY0("SBUS_WRITE_FAILED", MES(SBUS_WRITE_FAILED)),
340/* 4*/ FLAG_ENTRY0("KEY_MISMATCH", MES(KEY_MISMATCH)),
341/* 5*/ FLAG_ENTRY0("FW_AUTH_FAILED", MES(FW_AUTH_FAILED)),
342/* 6*/ FLAG_ENTRY0("EFUSE_CSR_PARITY", MES(EFUSE_CSR_PARITY)),
343/* 7*/ FLAG_ENTRY0("EFUSE_READ_BAD_ADDR", MES(EFUSE_READ_BAD_ADDR)),
344/* 8*/ FLAG_ENTRY0("EFUSE_WRITE", MES(EFUSE_WRITE)),
345/* 9*/ FLAG_ENTRY0("EFUSE_DONE_PARITY", MES(EFUSE_DONE_PARITY)),
346/*10*/ FLAG_ENTRY0("INVALID_EEP_CMD", MES(INVALID_EEP_CMD)),
347/*11*/ FLAG_ENTRY0("MBIST_FAIL", MES(MBIST_FAIL)),
348/*12*/ FLAG_ENTRY0("PLL_LOCK_FAIL", MES(PLL_LOCK_FAIL))
349};
350
351/*
352 * TXE PIO Error flags and consequences
353 */
354static struct flag_table pio_err_status_flags[] = {
355/* 0*/ FLAG_ENTRY("PioWriteBadCtxt",
356 SEC_WRITE_DROPPED,
357 SEND_PIO_ERR_STATUS_PIO_WRITE_BAD_CTXT_ERR_SMASK),
358/* 1*/ FLAG_ENTRY("PioWriteAddrParity",
359 SEC_SPC_FREEZE,
360 SEND_PIO_ERR_STATUS_PIO_WRITE_ADDR_PARITY_ERR_SMASK),
361/* 2*/ FLAG_ENTRY("PioCsrParity",
362 SEC_SPC_FREEZE,
363 SEND_PIO_ERR_STATUS_PIO_CSR_PARITY_ERR_SMASK),
364/* 3*/ FLAG_ENTRY("PioSbMemFifo0",
365 SEC_SPC_FREEZE,
366 SEND_PIO_ERR_STATUS_PIO_SB_MEM_FIFO0_ERR_SMASK),
367/* 4*/ FLAG_ENTRY("PioSbMemFifo1",
368 SEC_SPC_FREEZE,
369 SEND_PIO_ERR_STATUS_PIO_SB_MEM_FIFO1_ERR_SMASK),
370/* 5*/ FLAG_ENTRY("PioPccFifoParity",
371 SEC_SPC_FREEZE,
372 SEND_PIO_ERR_STATUS_PIO_PCC_FIFO_PARITY_ERR_SMASK),
373/* 6*/ FLAG_ENTRY("PioPecFifoParity",
374 SEC_SPC_FREEZE,
375 SEND_PIO_ERR_STATUS_PIO_PEC_FIFO_PARITY_ERR_SMASK),
376/* 7*/ FLAG_ENTRY("PioSbrdctlCrrelParity",
377 SEC_SPC_FREEZE,
378 SEND_PIO_ERR_STATUS_PIO_SBRDCTL_CRREL_PARITY_ERR_SMASK),
379/* 8*/ FLAG_ENTRY("PioSbrdctrlCrrelFifoParity",
380 SEC_SPC_FREEZE,
381 SEND_PIO_ERR_STATUS_PIO_SBRDCTRL_CRREL_FIFO_PARITY_ERR_SMASK),
382/* 9*/ FLAG_ENTRY("PioPktEvictFifoParityErr",
383 SEC_SPC_FREEZE,
384 SEND_PIO_ERR_STATUS_PIO_PKT_EVICT_FIFO_PARITY_ERR_SMASK),
385/*10*/ FLAG_ENTRY("PioSmPktResetParity",
386 SEC_SPC_FREEZE,
387 SEND_PIO_ERR_STATUS_PIO_SM_PKT_RESET_PARITY_ERR_SMASK),
388/*11*/ FLAG_ENTRY("PioVlLenMemBank0Unc",
389 SEC_SPC_FREEZE,
390 SEND_PIO_ERR_STATUS_PIO_VL_LEN_MEM_BANK0_UNC_ERR_SMASK),
391/*12*/ FLAG_ENTRY("PioVlLenMemBank1Unc",
392 SEC_SPC_FREEZE,
393 SEND_PIO_ERR_STATUS_PIO_VL_LEN_MEM_BANK1_UNC_ERR_SMASK),
394/*13*/ FLAG_ENTRY("PioVlLenMemBank0Cor",
395 0,
396 SEND_PIO_ERR_STATUS_PIO_VL_LEN_MEM_BANK0_COR_ERR_SMASK),
397/*14*/ FLAG_ENTRY("PioVlLenMemBank1Cor",
398 0,
399 SEND_PIO_ERR_STATUS_PIO_VL_LEN_MEM_BANK1_COR_ERR_SMASK),
400/*15*/ FLAG_ENTRY("PioCreditRetFifoParity",
401 SEC_SPC_FREEZE,
402 SEND_PIO_ERR_STATUS_PIO_CREDIT_RET_FIFO_PARITY_ERR_SMASK),
403/*16*/ FLAG_ENTRY("PioPpmcPblFifo",
404 SEC_SPC_FREEZE,
405 SEND_PIO_ERR_STATUS_PIO_PPMC_PBL_FIFO_ERR_SMASK),
406/*17*/ FLAG_ENTRY("PioInitSmIn",
407 0,
408 SEND_PIO_ERR_STATUS_PIO_INIT_SM_IN_ERR_SMASK),
409/*18*/ FLAG_ENTRY("PioPktEvictSmOrArbSm",
410 SEC_SPC_FREEZE,
411 SEND_PIO_ERR_STATUS_PIO_PKT_EVICT_SM_OR_ARB_SM_ERR_SMASK),
412/*19*/ FLAG_ENTRY("PioHostAddrMemUnc",
413 SEC_SPC_FREEZE,
414 SEND_PIO_ERR_STATUS_PIO_HOST_ADDR_MEM_UNC_ERR_SMASK),
415/*20*/ FLAG_ENTRY("PioHostAddrMemCor",
416 0,
417 SEND_PIO_ERR_STATUS_PIO_HOST_ADDR_MEM_COR_ERR_SMASK),
418/*21*/ FLAG_ENTRY("PioWriteDataParity",
419 SEC_SPC_FREEZE,
420 SEND_PIO_ERR_STATUS_PIO_WRITE_DATA_PARITY_ERR_SMASK),
421/*22*/ FLAG_ENTRY("PioStateMachine",
422 SEC_SPC_FREEZE,
423 SEND_PIO_ERR_STATUS_PIO_STATE_MACHINE_ERR_SMASK),
424/*23*/ FLAG_ENTRY("PioWriteQwValidParity",
8638b77f 425 SEC_WRITE_DROPPED | SEC_SPC_FREEZE,
77241056
MM		 426 SEND_PIO_ERR_STATUS_PIO_WRITE_QW_VALID_PARITY_ERR_SMASK),
427/*24*/ FLAG_ENTRY("PioBlockQwCountParity",
8638b77f 428 SEC_WRITE_DROPPED | SEC_SPC_FREEZE,
77241056
MM		 429 SEND_PIO_ERR_STATUS_PIO_BLOCK_QW_COUNT_PARITY_ERR_SMASK),
430/*25*/ FLAG_ENTRY("PioVlfVlLenParity",
431 SEC_SPC_FREEZE,
432 SEND_PIO_ERR_STATUS_PIO_VLF_VL_LEN_PARITY_ERR_SMASK),
433/*26*/ FLAG_ENTRY("PioVlfSopParity",
434 SEC_SPC_FREEZE,
435 SEND_PIO_ERR_STATUS_PIO_VLF_SOP_PARITY_ERR_SMASK),
436/*27*/ FLAG_ENTRY("PioVlFifoParity",
437 SEC_SPC_FREEZE,
438 SEND_PIO_ERR_STATUS_PIO_VL_FIFO_PARITY_ERR_SMASK),
439/*28*/ FLAG_ENTRY("PioPpmcBqcMemParity",
440 SEC_SPC_FREEZE,
441 SEND_PIO_ERR_STATUS_PIO_PPMC_BQC_MEM_PARITY_ERR_SMASK),
442/*29*/ FLAG_ENTRY("PioPpmcSopLen",
443 SEC_SPC_FREEZE,
444 SEND_PIO_ERR_STATUS_PIO_PPMC_SOP_LEN_ERR_SMASK),
445/*30-31 reserved*/
446/*32*/ FLAG_ENTRY("PioCurrentFreeCntParity",
447 SEC_SPC_FREEZE,
448 SEND_PIO_ERR_STATUS_PIO_CURRENT_FREE_CNT_PARITY_ERR_SMASK),
449/*33*/ FLAG_ENTRY("PioLastReturnedCntParity",
450 SEC_SPC_FREEZE,
451 SEND_PIO_ERR_STATUS_PIO_LAST_RETURNED_CNT_PARITY_ERR_SMASK),
452/*34*/ FLAG_ENTRY("PioPccSopHeadParity",
453 SEC_SPC_FREEZE,
454 SEND_PIO_ERR_STATUS_PIO_PCC_SOP_HEAD_PARITY_ERR_SMASK),
455/*35*/ FLAG_ENTRY("PioPecSopHeadParityErr",
456 SEC_SPC_FREEZE,
457 SEND_PIO_ERR_STATUS_PIO_PEC_SOP_HEAD_PARITY_ERR_SMASK),
458/*36-63 reserved*/
459};
460
461/* TXE PIO errors that cause an SPC freeze */
462#define ALL_PIO_FREEZE_ERR \
463 (SEND_PIO_ERR_STATUS_PIO_WRITE_ADDR_PARITY_ERR_SMASK \
464 | SEND_PIO_ERR_STATUS_PIO_CSR_PARITY_ERR_SMASK \
465 | SEND_PIO_ERR_STATUS_PIO_SB_MEM_FIFO0_ERR_SMASK \
466 | SEND_PIO_ERR_STATUS_PIO_SB_MEM_FIFO1_ERR_SMASK \
467 | SEND_PIO_ERR_STATUS_PIO_PCC_FIFO_PARITY_ERR_SMASK \
468 | SEND_PIO_ERR_STATUS_PIO_PEC_FIFO_PARITY_ERR_SMASK \
469 | SEND_PIO_ERR_STATUS_PIO_SBRDCTL_CRREL_PARITY_ERR_SMASK \
470 | SEND_PIO_ERR_STATUS_PIO_SBRDCTRL_CRREL_FIFO_PARITY_ERR_SMASK \
471 | SEND_PIO_ERR_STATUS_PIO_PKT_EVICT_FIFO_PARITY_ERR_SMASK \
472 | SEND_PIO_ERR_STATUS_PIO_SM_PKT_RESET_PARITY_ERR_SMASK \
473 | SEND_PIO_ERR_STATUS_PIO_VL_LEN_MEM_BANK0_UNC_ERR_SMASK \
474 | SEND_PIO_ERR_STATUS_PIO_VL_LEN_MEM_BANK1_UNC_ERR_SMASK \
475 | SEND_PIO_ERR_STATUS_PIO_CREDIT_RET_FIFO_PARITY_ERR_SMASK \
476 | SEND_PIO_ERR_STATUS_PIO_PPMC_PBL_FIFO_ERR_SMASK \
477 | SEND_PIO_ERR_STATUS_PIO_PKT_EVICT_SM_OR_ARB_SM_ERR_SMASK \
478 | SEND_PIO_ERR_STATUS_PIO_HOST_ADDR_MEM_UNC_ERR_SMASK \
479 | SEND_PIO_ERR_STATUS_PIO_WRITE_DATA_PARITY_ERR_SMASK \
480 | SEND_PIO_ERR_STATUS_PIO_STATE_MACHINE_ERR_SMASK \
481 | SEND_PIO_ERR_STATUS_PIO_WRITE_QW_VALID_PARITY_ERR_SMASK \
482 | SEND_PIO_ERR_STATUS_PIO_BLOCK_QW_COUNT_PARITY_ERR_SMASK \
483 | SEND_PIO_ERR_STATUS_PIO_VLF_VL_LEN_PARITY_ERR_SMASK \
484 | SEND_PIO_ERR_STATUS_PIO_VLF_SOP_PARITY_ERR_SMASK \
485 | SEND_PIO_ERR_STATUS_PIO_VL_FIFO_PARITY_ERR_SMASK \
486 | SEND_PIO_ERR_STATUS_PIO_PPMC_BQC_MEM_PARITY_ERR_SMASK \
487 | SEND_PIO_ERR_STATUS_PIO_PPMC_SOP_LEN_ERR_SMASK \
488 | SEND_PIO_ERR_STATUS_PIO_CURRENT_FREE_CNT_PARITY_ERR_SMASK \
489 | SEND_PIO_ERR_STATUS_PIO_LAST_RETURNED_CNT_PARITY_ERR_SMASK \
490 | SEND_PIO_ERR_STATUS_PIO_PCC_SOP_HEAD_PARITY_ERR_SMASK \
491 | SEND_PIO_ERR_STATUS_PIO_PEC_SOP_HEAD_PARITY_ERR_SMASK)
492
493/*
494 * TXE SDMA Error flags
495 */
496static struct flag_table sdma_err_status_flags[] = {
497/* 0*/ FLAG_ENTRY0("SDmaRpyTagErr",
498 SEND_DMA_ERR_STATUS_SDMA_RPY_TAG_ERR_SMASK),
499/* 1*/ FLAG_ENTRY0("SDmaCsrParityErr",
500 SEND_DMA_ERR_STATUS_SDMA_CSR_PARITY_ERR_SMASK),
501/* 2*/ FLAG_ENTRY0("SDmaPcieReqTrackingUncErr",
502 SEND_DMA_ERR_STATUS_SDMA_PCIE_REQ_TRACKING_UNC_ERR_SMASK),
503/* 3*/ FLAG_ENTRY0("SDmaPcieReqTrackingCorErr",
504 SEND_DMA_ERR_STATUS_SDMA_PCIE_REQ_TRACKING_COR_ERR_SMASK),
505/*04-63 reserved*/
506};
507
508/* TXE SDMA errors that cause an SPC freeze */
509#define ALL_SDMA_FREEZE_ERR \
510 (SEND_DMA_ERR_STATUS_SDMA_RPY_TAG_ERR_SMASK \
511 | SEND_DMA_ERR_STATUS_SDMA_CSR_PARITY_ERR_SMASK \
512 | SEND_DMA_ERR_STATUS_SDMA_PCIE_REQ_TRACKING_UNC_ERR_SMASK)
513
69a00b8e
MM		 514/* SendEgressErrInfo bits that correspond to a PortXmitDiscard counter */
515#define PORT_DISCARD_EGRESS_ERRS \
516 (SEND_EGRESS_ERR_INFO_TOO_LONG_IB_PACKET_ERR_SMASK \
517 | SEND_EGRESS_ERR_INFO_VL_MAPPING_ERR_SMASK \
518 | SEND_EGRESS_ERR_INFO_VL_ERR_SMASK)
519
77241056
MM		 520/*
521 * TXE Egress Error flags
522 */
523#define SEES(text) SEND_EGRESS_ERR_STATUS_##text##_ERR_SMASK
524static struct flag_table egress_err_status_flags[] = {
525/* 0*/ FLAG_ENTRY0("TxPktIntegrityMemCorErr", SEES(TX_PKT_INTEGRITY_MEM_COR)),
526/* 1*/ FLAG_ENTRY0("TxPktIntegrityMemUncErr", SEES(TX_PKT_INTEGRITY_MEM_UNC)),
527/* 2 reserved */
528/* 3*/ FLAG_ENTRY0("TxEgressFifoUnderrunOrParityErr",
529 SEES(TX_EGRESS_FIFO_UNDERRUN_OR_PARITY)),
530/* 4*/ FLAG_ENTRY0("TxLinkdownErr", SEES(TX_LINKDOWN)),
531/* 5*/ FLAG_ENTRY0("TxIncorrectLinkStateErr", SEES(TX_INCORRECT_LINK_STATE)),
532/* 6 reserved */
533/* 7*/ FLAG_ENTRY0("TxPioLaunchIntfParityErr",
534 SEES(TX_PIO_LAUNCH_INTF_PARITY)),
535/* 8*/ FLAG_ENTRY0("TxSdmaLaunchIntfParityErr",
536 SEES(TX_SDMA_LAUNCH_INTF_PARITY)),
537/* 9-10 reserved */
538/*11*/ FLAG_ENTRY0("TxSbrdCtlStateMachineParityErr",
539 SEES(TX_SBRD_CTL_STATE_MACHINE_PARITY)),
540/*12*/ FLAG_ENTRY0("TxIllegalVLErr", SEES(TX_ILLEGAL_VL)),
541/*13*/ FLAG_ENTRY0("TxLaunchCsrParityErr", SEES(TX_LAUNCH_CSR_PARITY)),
542/*14*/ FLAG_ENTRY0("TxSbrdCtlCsrParityErr", SEES(TX_SBRD_CTL_CSR_PARITY)),
543/*15*/ FLAG_ENTRY0("TxConfigParityErr", SEES(TX_CONFIG_PARITY)),
544/*16*/ FLAG_ENTRY0("TxSdma0DisallowedPacketErr",
545 SEES(TX_SDMA0_DISALLOWED_PACKET)),
546/*17*/ FLAG_ENTRY0("TxSdma1DisallowedPacketErr",
547 SEES(TX_SDMA1_DISALLOWED_PACKET)),
548/*18*/ FLAG_ENTRY0("TxSdma2DisallowedPacketErr",
549 SEES(TX_SDMA2_DISALLOWED_PACKET)),
550/*19*/ FLAG_ENTRY0("TxSdma3DisallowedPacketErr",
551 SEES(TX_SDMA3_DISALLOWED_PACKET)),
552/*20*/ FLAG_ENTRY0("TxSdma4DisallowedPacketErr",
553 SEES(TX_SDMA4_DISALLOWED_PACKET)),
554/*21*/ FLAG_ENTRY0("TxSdma5DisallowedPacketErr",
555 SEES(TX_SDMA5_DISALLOWED_PACKET)),
556/*22*/ FLAG_ENTRY0("TxSdma6DisallowedPacketErr",
557 SEES(TX_SDMA6_DISALLOWED_PACKET)),
558/*23*/ FLAG_ENTRY0("TxSdma7DisallowedPacketErr",
559 SEES(TX_SDMA7_DISALLOWED_PACKET)),
560/*24*/ FLAG_ENTRY0("TxSdma8DisallowedPacketErr",
561 SEES(TX_SDMA8_DISALLOWED_PACKET)),
562/*25*/ FLAG_ENTRY0("TxSdma9DisallowedPacketErr",
563 SEES(TX_SDMA9_DISALLOWED_PACKET)),
564/*26*/ FLAG_ENTRY0("TxSdma10DisallowedPacketErr",
565 SEES(TX_SDMA10_DISALLOWED_PACKET)),
566/*27*/ FLAG_ENTRY0("TxSdma11DisallowedPacketErr",
567 SEES(TX_SDMA11_DISALLOWED_PACKET)),
568/*28*/ FLAG_ENTRY0("TxSdma12DisallowedPacketErr",
569 SEES(TX_SDMA12_DISALLOWED_PACKET)),
570/*29*/ FLAG_ENTRY0("TxSdma13DisallowedPacketErr",
571 SEES(TX_SDMA13_DISALLOWED_PACKET)),
572/*30*/ FLAG_ENTRY0("TxSdma14DisallowedPacketErr",
573 SEES(TX_SDMA14_DISALLOWED_PACKET)),
574/*31*/ FLAG_ENTRY0("TxSdma15DisallowedPacketErr",
575 SEES(TX_SDMA15_DISALLOWED_PACKET)),
576/*32*/ FLAG_ENTRY0("TxLaunchFifo0UncOrParityErr",
577 SEES(TX_LAUNCH_FIFO0_UNC_OR_PARITY)),
578/*33*/ FLAG_ENTRY0("TxLaunchFifo1UncOrParityErr",
579 SEES(TX_LAUNCH_FIFO1_UNC_OR_PARITY)),
580/*34*/ FLAG_ENTRY0("TxLaunchFifo2UncOrParityErr",
581 SEES(TX_LAUNCH_FIFO2_UNC_OR_PARITY)),
582/*35*/ FLAG_ENTRY0("TxLaunchFifo3UncOrParityErr",
583 SEES(TX_LAUNCH_FIFO3_UNC_OR_PARITY)),
584/*36*/ FLAG_ENTRY0("TxLaunchFifo4UncOrParityErr",
585 SEES(TX_LAUNCH_FIFO4_UNC_OR_PARITY)),
586/*37*/ FLAG_ENTRY0("TxLaunchFifo5UncOrParityErr",
587 SEES(TX_LAUNCH_FIFO5_UNC_OR_PARITY)),
588/*38*/ FLAG_ENTRY0("TxLaunchFifo6UncOrParityErr",
589 SEES(TX_LAUNCH_FIFO6_UNC_OR_PARITY)),
590/*39*/ FLAG_ENTRY0("TxLaunchFifo7UncOrParityErr",
591 SEES(TX_LAUNCH_FIFO7_UNC_OR_PARITY)),
592/*40*/ FLAG_ENTRY0("TxLaunchFifo8UncOrParityErr",
593 SEES(TX_LAUNCH_FIFO8_UNC_OR_PARITY)),
594/*41*/ FLAG_ENTRY0("TxCreditReturnParityErr", SEES(TX_CREDIT_RETURN_PARITY)),
595/*42*/ FLAG_ENTRY0("TxSbHdrUncErr", SEES(TX_SB_HDR_UNC)),
596/*43*/ FLAG_ENTRY0("TxReadSdmaMemoryUncErr", SEES(TX_READ_SDMA_MEMORY_UNC)),
597/*44*/ FLAG_ENTRY0("TxReadPioMemoryUncErr", SEES(TX_READ_PIO_MEMORY_UNC)),
598/*45*/ FLAG_ENTRY0("TxEgressFifoUncErr", SEES(TX_EGRESS_FIFO_UNC)),
599/*46*/ FLAG_ENTRY0("TxHcrcInsertionErr", SEES(TX_HCRC_INSERTION)),
600/*47*/ FLAG_ENTRY0("TxCreditReturnVLErr", SEES(TX_CREDIT_RETURN_VL)),
601/*48*/ FLAG_ENTRY0("TxLaunchFifo0CorErr", SEES(TX_LAUNCH_FIFO0_COR)),
602/*49*/ FLAG_ENTRY0("TxLaunchFifo1CorErr", SEES(TX_LAUNCH_FIFO1_COR)),
603/*50*/ FLAG_ENTRY0("TxLaunchFifo2CorErr", SEES(TX_LAUNCH_FIFO2_COR)),
604/*51*/ FLAG_ENTRY0("TxLaunchFifo3CorErr", SEES(TX_LAUNCH_FIFO3_COR)),
605/*52*/ FLAG_ENTRY0("TxLaunchFifo4CorErr", SEES(TX_LAUNCH_FIFO4_COR)),
606/*53*/ FLAG_ENTRY0("TxLaunchFifo5CorErr", SEES(TX_LAUNCH_FIFO5_COR)),
607/*54*/ FLAG_ENTRY0("TxLaunchFifo6CorErr", SEES(TX_LAUNCH_FIFO6_COR)),
608/*55*/ FLAG_ENTRY0("TxLaunchFifo7CorErr", SEES(TX_LAUNCH_FIFO7_COR)),
609/*56*/ FLAG_ENTRY0("TxLaunchFifo8CorErr", SEES(TX_LAUNCH_FIFO8_COR)),
610/*57*/ FLAG_ENTRY0("TxCreditOverrunErr", SEES(TX_CREDIT_OVERRUN)),
611/*58*/ FLAG_ENTRY0("TxSbHdrCorErr", SEES(TX_SB_HDR_COR)),
612/*59*/ FLAG_ENTRY0("TxReadSdmaMemoryCorErr", SEES(TX_READ_SDMA_MEMORY_COR)),
613/*60*/ FLAG_ENTRY0("TxReadPioMemoryCorErr", SEES(TX_READ_PIO_MEMORY_COR)),
614/*61*/ FLAG_ENTRY0("TxEgressFifoCorErr", SEES(TX_EGRESS_FIFO_COR)),
615/*62*/ FLAG_ENTRY0("TxReadSdmaMemoryCsrUncErr",
616 SEES(TX_READ_SDMA_MEMORY_CSR_UNC)),
617/*63*/ FLAG_ENTRY0("TxReadPioMemoryCsrUncErr",
618 SEES(TX_READ_PIO_MEMORY_CSR_UNC)),
619};
620
621/*
622 * TXE Egress Error Info flags
623 */
624#define SEEI(text) SEND_EGRESS_ERR_INFO_##text##_ERR_SMASK
625static struct flag_table egress_err_info_flags[] = {
626/* 0*/ FLAG_ENTRY0("Reserved", 0ull),
627/* 1*/ FLAG_ENTRY0("VLErr", SEEI(VL)),
628/* 2*/ FLAG_ENTRY0("JobKeyErr", SEEI(JOB_KEY)),
629/* 3*/ FLAG_ENTRY0("JobKeyErr", SEEI(JOB_KEY)),
630/* 4*/ FLAG_ENTRY0("PartitionKeyErr", SEEI(PARTITION_KEY)),
631/* 5*/ FLAG_ENTRY0("SLIDErr", SEEI(SLID)),
632/* 6*/ FLAG_ENTRY0("OpcodeErr", SEEI(OPCODE)),
633/* 7*/ FLAG_ENTRY0("VLMappingErr", SEEI(VL_MAPPING)),
634/* 8*/ FLAG_ENTRY0("RawErr", SEEI(RAW)),
635/* 9*/ FLAG_ENTRY0("RawIPv6Err", SEEI(RAW_IPV6)),
636/*10*/ FLAG_ENTRY0("GRHErr", SEEI(GRH)),
637/*11*/ FLAG_ENTRY0("BypassErr", SEEI(BYPASS)),
638/*12*/ FLAG_ENTRY0("KDETHPacketsErr", SEEI(KDETH_PACKETS)),
639/*13*/ FLAG_ENTRY0("NonKDETHPacketsErr", SEEI(NON_KDETH_PACKETS)),
640/*14*/ FLAG_ENTRY0("TooSmallIBPacketsErr", SEEI(TOO_SMALL_IB_PACKETS)),
641/*15*/ FLAG_ENTRY0("TooSmallBypassPacketsErr", SEEI(TOO_SMALL_BYPASS_PACKETS)),
642/*16*/ FLAG_ENTRY0("PbcTestErr", SEEI(PBC_TEST)),
643/*17*/ FLAG_ENTRY0("BadPktLenErr", SEEI(BAD_PKT_LEN)),
644/*18*/ FLAG_ENTRY0("TooLongIBPacketErr", SEEI(TOO_LONG_IB_PACKET)),
645/*19*/ FLAG_ENTRY0("TooLongBypassPacketsErr", SEEI(TOO_LONG_BYPASS_PACKETS)),
646/*20*/ FLAG_ENTRY0("PbcStaticRateControlErr", SEEI(PBC_STATIC_RATE_CONTROL)),
647/*21*/ FLAG_ENTRY0("BypassBadPktLenErr", SEEI(BAD_PKT_LEN)),
648};
649
650/* TXE Egress errors that cause an SPC freeze */
651#define ALL_TXE_EGRESS_FREEZE_ERR \
652 (SEES(TX_EGRESS_FIFO_UNDERRUN_OR_PARITY) \
653 | SEES(TX_PIO_LAUNCH_INTF_PARITY) \
654 | SEES(TX_SDMA_LAUNCH_INTF_PARITY) \
655 | SEES(TX_SBRD_CTL_STATE_MACHINE_PARITY) \
656 | SEES(TX_LAUNCH_CSR_PARITY) \
657 | SEES(TX_SBRD_CTL_CSR_PARITY) \
658 | SEES(TX_CONFIG_PARITY) \
659 | SEES(TX_LAUNCH_FIFO0_UNC_OR_PARITY) \
660 | SEES(TX_LAUNCH_FIFO1_UNC_OR_PARITY) \
661 | SEES(TX_LAUNCH_FIFO2_UNC_OR_PARITY) \
662 | SEES(TX_LAUNCH_FIFO3_UNC_OR_PARITY) \
663 | SEES(TX_LAUNCH_FIFO4_UNC_OR_PARITY) \
664 | SEES(TX_LAUNCH_FIFO5_UNC_OR_PARITY) \
665 | SEES(TX_LAUNCH_FIFO6_UNC_OR_PARITY) \
666 | SEES(TX_LAUNCH_FIFO7_UNC_OR_PARITY) \
667 | SEES(TX_LAUNCH_FIFO8_UNC_OR_PARITY) \
668 | SEES(TX_CREDIT_RETURN_PARITY))
669
670/*
671 * TXE Send error flags
672 */
673#define SES(name) SEND_ERR_STATUS_SEND_##name##_ERR_SMASK
674static struct flag_table send_err_status_flags[] = {
2c5b521a 675/* 0*/ FLAG_ENTRY0("SendCsrParityErr", SES(CSR_PARITY)),
77241056
MM		 676/* 1*/ FLAG_ENTRY0("SendCsrReadBadAddrErr", SES(CSR_READ_BAD_ADDR)),
677/* 2*/ FLAG_ENTRY0("SendCsrWriteBadAddrErr", SES(CSR_WRITE_BAD_ADDR))
678};
679
680/*
681 * TXE Send Context Error flags and consequences
682 */
683static struct flag_table sc_err_status_flags[] = {
684/* 0*/ FLAG_ENTRY("InconsistentSop",
685 SEC_PACKET_DROPPED | SEC_SC_HALTED,
686 SEND_CTXT_ERR_STATUS_PIO_INCONSISTENT_SOP_ERR_SMASK),
687/* 1*/ FLAG_ENTRY("DisallowedPacket",
688 SEC_PACKET_DROPPED | SEC_SC_HALTED,
689 SEND_CTXT_ERR_STATUS_PIO_DISALLOWED_PACKET_ERR_SMASK),
690/* 2*/ FLAG_ENTRY("WriteCrossesBoundary",
691 SEC_WRITE_DROPPED | SEC_SC_HALTED,
692 SEND_CTXT_ERR_STATUS_PIO_WRITE_CROSSES_BOUNDARY_ERR_SMASK),
693/* 3*/ FLAG_ENTRY("WriteOverflow",
694 SEC_WRITE_DROPPED | SEC_SC_HALTED,
695 SEND_CTXT_ERR_STATUS_PIO_WRITE_OVERFLOW_ERR_SMASK),
696/* 4*/ FLAG_ENTRY("WriteOutOfBounds",
697 SEC_WRITE_DROPPED | SEC_SC_HALTED,
698 SEND_CTXT_ERR_STATUS_PIO_WRITE_OUT_OF_BOUNDS_ERR_SMASK),
699/* 5-63 reserved*/
700};
701
702/*
703 * RXE Receive Error flags
704 */
705#define RXES(name) RCV_ERR_STATUS_RX_##name##_ERR_SMASK
706static struct flag_table rxe_err_status_flags[] = {
707/* 0*/ FLAG_ENTRY0("RxDmaCsrCorErr", RXES(DMA_CSR_COR)),
708/* 1*/ FLAG_ENTRY0("RxDcIntfParityErr", RXES(DC_INTF_PARITY)),
709/* 2*/ FLAG_ENTRY0("RxRcvHdrUncErr", RXES(RCV_HDR_UNC)),
710/* 3*/ FLAG_ENTRY0("RxRcvHdrCorErr", RXES(RCV_HDR_COR)),
711/* 4*/ FLAG_ENTRY0("RxRcvDataUncErr", RXES(RCV_DATA_UNC)),
712/* 5*/ FLAG_ENTRY0("RxRcvDataCorErr", RXES(RCV_DATA_COR)),
713/* 6*/ FLAG_ENTRY0("RxRcvQpMapTableUncErr", RXES(RCV_QP_MAP_TABLE_UNC)),
714/* 7*/ FLAG_ENTRY0("RxRcvQpMapTableCorErr", RXES(RCV_QP_MAP_TABLE_COR)),
715/* 8*/ FLAG_ENTRY0("RxRcvCsrParityErr", RXES(RCV_CSR_PARITY)),
716/* 9*/ FLAG_ENTRY0("RxDcSopEopParityErr", RXES(DC_SOP_EOP_PARITY)),
717/*10*/ FLAG_ENTRY0("RxDmaFlagUncErr", RXES(DMA_FLAG_UNC)),
718/*11*/ FLAG_ENTRY0("RxDmaFlagCorErr", RXES(DMA_FLAG_COR)),
719/*12*/ FLAG_ENTRY0("RxRcvFsmEncodingErr", RXES(RCV_FSM_ENCODING)),
720/*13*/ FLAG_ENTRY0("RxRbufFreeListUncErr", RXES(RBUF_FREE_LIST_UNC)),
721/*14*/ FLAG_ENTRY0("RxRbufFreeListCorErr", RXES(RBUF_FREE_LIST_COR)),
722/*15*/ FLAG_ENTRY0("RxRbufLookupDesRegUncErr", RXES(RBUF_LOOKUP_DES_REG_UNC)),
723/*16*/ FLAG_ENTRY0("RxRbufLookupDesRegUncCorErr",
724 RXES(RBUF_LOOKUP_DES_REG_UNC_COR)),
725/*17*/ FLAG_ENTRY0("RxRbufLookupDesUncErr", RXES(RBUF_LOOKUP_DES_UNC)),
726/*18*/ FLAG_ENTRY0("RxRbufLookupDesCorErr", RXES(RBUF_LOOKUP_DES_COR)),
727/*19*/ FLAG_ENTRY0("RxRbufBlockListReadUncErr",
728 RXES(RBUF_BLOCK_LIST_READ_UNC)),
729/*20*/ FLAG_ENTRY0("RxRbufBlockListReadCorErr",
730 RXES(RBUF_BLOCK_LIST_READ_COR)),
731/*21*/ FLAG_ENTRY0("RxRbufCsrQHeadBufNumParityErr",
732 RXES(RBUF_CSR_QHEAD_BUF_NUM_PARITY)),
733/*22*/ FLAG_ENTRY0("RxRbufCsrQEntCntParityErr",
734 RXES(RBUF_CSR_QENT_CNT_PARITY)),
735/*23*/ FLAG_ENTRY0("RxRbufCsrQNextBufParityErr",
736 RXES(RBUF_CSR_QNEXT_BUF_PARITY)),
737/*24*/ FLAG_ENTRY0("RxRbufCsrQVldBitParityErr",
738 RXES(RBUF_CSR_QVLD_BIT_PARITY)),
739/*25*/ FLAG_ENTRY0("RxRbufCsrQHdPtrParityErr", RXES(RBUF_CSR_QHD_PTR_PARITY)),
740/*26*/ FLAG_ENTRY0("RxRbufCsrQTlPtrParityErr", RXES(RBUF_CSR_QTL_PTR_PARITY)),
741/*27*/ FLAG_ENTRY0("RxRbufCsrQNumOfPktParityErr",
742 RXES(RBUF_CSR_QNUM_OF_PKT_PARITY)),
743/*28*/ FLAG_ENTRY0("RxRbufCsrQEOPDWParityErr", RXES(RBUF_CSR_QEOPDW_PARITY)),
744/*29*/ FLAG_ENTRY0("RxRbufCtxIdParityErr", RXES(RBUF_CTX_ID_PARITY)),
745/*30*/ FLAG_ENTRY0("RxRBufBadLookupErr", RXES(RBUF_BAD_LOOKUP)),
746/*31*/ FLAG_ENTRY0("RxRbufFullErr", RXES(RBUF_FULL)),
747/*32*/ FLAG_ENTRY0("RxRbufEmptyErr", RXES(RBUF_EMPTY)),
748/*33*/ FLAG_ENTRY0("RxRbufFlRdAddrParityErr", RXES(RBUF_FL_RD_ADDR_PARITY)),
749/*34*/ FLAG_ENTRY0("RxRbufFlWrAddrParityErr", RXES(RBUF_FL_WR_ADDR_PARITY)),
750/*35*/ FLAG_ENTRY0("RxRbufFlInitdoneParityErr",
751 RXES(RBUF_FL_INITDONE_PARITY)),
752/*36*/ FLAG_ENTRY0("RxRbufFlInitWrAddrParityErr",
753 RXES(RBUF_FL_INIT_WR_ADDR_PARITY)),
754/*37*/ FLAG_ENTRY0("RxRbufNextFreeBufUncErr", RXES(RBUF_NEXT_FREE_BUF_UNC)),
755/*38*/ FLAG_ENTRY0("RxRbufNextFreeBufCorErr", RXES(RBUF_NEXT_FREE_BUF_COR)),
756/*39*/ FLAG_ENTRY0("RxLookupDesPart1UncErr", RXES(LOOKUP_DES_PART1_UNC)),
757/*40*/ FLAG_ENTRY0("RxLookupDesPart1UncCorErr",
758 RXES(LOOKUP_DES_PART1_UNC_COR)),
759/*41*/ FLAG_ENTRY0("RxLookupDesPart2ParityErr",
760 RXES(LOOKUP_DES_PART2_PARITY)),
761/*42*/ FLAG_ENTRY0("RxLookupRcvArrayUncErr", RXES(LOOKUP_RCV_ARRAY_UNC)),
762/*43*/ FLAG_ENTRY0("RxLookupRcvArrayCorErr", RXES(LOOKUP_RCV_ARRAY_COR)),
763/*44*/ FLAG_ENTRY0("RxLookupCsrParityErr", RXES(LOOKUP_CSR_PARITY)),
764/*45*/ FLAG_ENTRY0("RxHqIntrCsrParityErr", RXES(HQ_INTR_CSR_PARITY)),
765/*46*/ FLAG_ENTRY0("RxHqIntrFsmErr", RXES(HQ_INTR_FSM)),
766/*47*/ FLAG_ENTRY0("RxRbufDescPart1UncErr", RXES(RBUF_DESC_PART1_UNC)),
767/*48*/ FLAG_ENTRY0("RxRbufDescPart1CorErr", RXES(RBUF_DESC_PART1_COR)),
768/*49*/ FLAG_ENTRY0("RxRbufDescPart2UncErr", RXES(RBUF_DESC_PART2_UNC)),
769/*50*/ FLAG_ENTRY0("RxRbufDescPart2CorErr", RXES(RBUF_DESC_PART2_COR)),
770/*51*/ FLAG_ENTRY0("RxDmaHdrFifoRdUncErr", RXES(DMA_HDR_FIFO_RD_UNC)),
771/*52*/ FLAG_ENTRY0("RxDmaHdrFifoRdCorErr", RXES(DMA_HDR_FIFO_RD_COR)),
772/*53*/ FLAG_ENTRY0("RxDmaDataFifoRdUncErr", RXES(DMA_DATA_FIFO_RD_UNC)),
773/*54*/ FLAG_ENTRY0("RxDmaDataFifoRdCorErr", RXES(DMA_DATA_FIFO_RD_COR)),
774/*55*/ FLAG_ENTRY0("RxRbufDataUncErr", RXES(RBUF_DATA_UNC)),
775/*56*/ FLAG_ENTRY0("RxRbufDataCorErr", RXES(RBUF_DATA_COR)),
776/*57*/ FLAG_ENTRY0("RxDmaCsrParityErr", RXES(DMA_CSR_PARITY)),
777/*58*/ FLAG_ENTRY0("RxDmaEqFsmEncodingErr", RXES(DMA_EQ_FSM_ENCODING)),
778/*59*/ FLAG_ENTRY0("RxDmaDqFsmEncodingErr", RXES(DMA_DQ_FSM_ENCODING)),
779/*60*/ FLAG_ENTRY0("RxDmaCsrUncErr", RXES(DMA_CSR_UNC)),
780/*61*/ FLAG_ENTRY0("RxCsrReadBadAddrErr", RXES(CSR_READ_BAD_ADDR)),
781/*62*/ FLAG_ENTRY0("RxCsrWriteBadAddrErr", RXES(CSR_WRITE_BAD_ADDR)),
782/*63*/ FLAG_ENTRY0("RxCsrParityErr", RXES(CSR_PARITY))
783};
784
785/* RXE errors that will trigger an SPC freeze */
786#define ALL_RXE_FREEZE_ERR \
787 (RCV_ERR_STATUS_RX_RCV_QP_MAP_TABLE_UNC_ERR_SMASK \
788 | RCV_ERR_STATUS_RX_RCV_CSR_PARITY_ERR_SMASK \
789 | RCV_ERR_STATUS_RX_DMA_FLAG_UNC_ERR_SMASK \
790 | RCV_ERR_STATUS_RX_RCV_FSM_ENCODING_ERR_SMASK \
791 | RCV_ERR_STATUS_RX_RBUF_FREE_LIST_UNC_ERR_SMASK \
792 | RCV_ERR_STATUS_RX_RBUF_LOOKUP_DES_REG_UNC_ERR_SMASK \
793 | RCV_ERR_STATUS_RX_RBUF_LOOKUP_DES_REG_UNC_COR_ERR_SMASK \
794 | RCV_ERR_STATUS_RX_RBUF_LOOKUP_DES_UNC_ERR_SMASK \
795 | RCV_ERR_STATUS_RX_RBUF_BLOCK_LIST_READ_UNC_ERR_SMASK \
796 | RCV_ERR_STATUS_RX_RBUF_CSR_QHEAD_BUF_NUM_PARITY_ERR_SMASK \
797 | RCV_ERR_STATUS_RX_RBUF_CSR_QENT_CNT_PARITY_ERR_SMASK \
798 | RCV_ERR_STATUS_RX_RBUF_CSR_QNEXT_BUF_PARITY_ERR_SMASK \
799 | RCV_ERR_STATUS_RX_RBUF_CSR_QVLD_BIT_PARITY_ERR_SMASK \
800 | RCV_ERR_STATUS_RX_RBUF_CSR_QHD_PTR_PARITY_ERR_SMASK \
801 | RCV_ERR_STATUS_RX_RBUF_CSR_QTL_PTR_PARITY_ERR_SMASK \
802 | RCV_ERR_STATUS_RX_RBUF_CSR_QNUM_OF_PKT_PARITY_ERR_SMASK \
803 | RCV_ERR_STATUS_RX_RBUF_CSR_QEOPDW_PARITY_ERR_SMASK \
804 | RCV_ERR_STATUS_RX_RBUF_CTX_ID_PARITY_ERR_SMASK \
805 | RCV_ERR_STATUS_RX_RBUF_BAD_LOOKUP_ERR_SMASK \
806 | RCV_ERR_STATUS_RX_RBUF_FULL_ERR_SMASK \
807 | RCV_ERR_STATUS_RX_RBUF_EMPTY_ERR_SMASK \
808 | RCV_ERR_STATUS_RX_RBUF_FL_RD_ADDR_PARITY_ERR_SMASK \
809 | RCV_ERR_STATUS_RX_RBUF_FL_WR_ADDR_PARITY_ERR_SMASK \
810 | RCV_ERR_STATUS_RX_RBUF_FL_INITDONE_PARITY_ERR_SMASK \
811 | RCV_ERR_STATUS_RX_RBUF_FL_INIT_WR_ADDR_PARITY_ERR_SMASK \
812 | RCV_ERR_STATUS_RX_RBUF_NEXT_FREE_BUF_UNC_ERR_SMASK \
813 | RCV_ERR_STATUS_RX_LOOKUP_DES_PART1_UNC_ERR_SMASK \
814 | RCV_ERR_STATUS_RX_LOOKUP_DES_PART1_UNC_COR_ERR_SMASK \
815 | RCV_ERR_STATUS_RX_LOOKUP_DES_PART2_PARITY_ERR_SMASK \
816 | RCV_ERR_STATUS_RX_LOOKUP_RCV_ARRAY_UNC_ERR_SMASK \
817 | RCV_ERR_STATUS_RX_LOOKUP_CSR_PARITY_ERR_SMASK \
818 | RCV_ERR_STATUS_RX_HQ_INTR_CSR_PARITY_ERR_SMASK \
819 | RCV_ERR_STATUS_RX_HQ_INTR_FSM_ERR_SMASK \
820 | RCV_ERR_STATUS_RX_RBUF_DESC_PART1_UNC_ERR_SMASK \
821 | RCV_ERR_STATUS_RX_RBUF_DESC_PART1_COR_ERR_SMASK \
822 | RCV_ERR_STATUS_RX_RBUF_DESC_PART2_UNC_ERR_SMASK \
823 | RCV_ERR_STATUS_RX_DMA_HDR_FIFO_RD_UNC_ERR_SMASK \
824 | RCV_ERR_STATUS_RX_DMA_DATA_FIFO_RD_UNC_ERR_SMASK \
825 | RCV_ERR_STATUS_RX_RBUF_DATA_UNC_ERR_SMASK \
826 | RCV_ERR_STATUS_RX_DMA_CSR_PARITY_ERR_SMASK \
827 | RCV_ERR_STATUS_RX_DMA_EQ_FSM_ENCODING_ERR_SMASK \
828 | RCV_ERR_STATUS_RX_DMA_DQ_FSM_ENCODING_ERR_SMASK \
829 | RCV_ERR_STATUS_RX_DMA_CSR_UNC_ERR_SMASK \
830 | RCV_ERR_STATUS_RX_CSR_PARITY_ERR_SMASK)
831
832#define RXE_FREEZE_ABORT_MASK \
833 (RCV_ERR_STATUS_RX_DMA_CSR_UNC_ERR_SMASK | \
834 RCV_ERR_STATUS_RX_DMA_HDR_FIFO_RD_UNC_ERR_SMASK | \
835 RCV_ERR_STATUS_RX_DMA_DATA_FIFO_RD_UNC_ERR_SMASK)
836
837/*
838 * DCC Error Flags
839 */
840#define DCCE(name) DCC_ERR_FLG_##name##_SMASK
841static struct flag_table dcc_err_flags[] = {
842 FLAG_ENTRY0("bad_l2_err", DCCE(BAD_L2_ERR)),
843 FLAG_ENTRY0("bad_sc_err", DCCE(BAD_SC_ERR)),
844 FLAG_ENTRY0("bad_mid_tail_err", DCCE(BAD_MID_TAIL_ERR)),
845 FLAG_ENTRY0("bad_preemption_err", DCCE(BAD_PREEMPTION_ERR)),
846 FLAG_ENTRY0("preemption_err", DCCE(PREEMPTION_ERR)),
847 FLAG_ENTRY0("preemptionvl15_err", DCCE(PREEMPTIONVL15_ERR)),
848 FLAG_ENTRY0("bad_vl_marker_err", DCCE(BAD_VL_MARKER_ERR)),
849 FLAG_ENTRY0("bad_dlid_target_err", DCCE(BAD_DLID_TARGET_ERR)),
850 FLAG_ENTRY0("bad_lver_err", DCCE(BAD_LVER_ERR)),
851 FLAG_ENTRY0("uncorrectable_err", DCCE(UNCORRECTABLE_ERR)),
852 FLAG_ENTRY0("bad_crdt_ack_err", DCCE(BAD_CRDT_ACK_ERR)),
853 FLAG_ENTRY0("unsup_pkt_type", DCCE(UNSUP_PKT_TYPE)),
854 FLAG_ENTRY0("bad_ctrl_flit_err", DCCE(BAD_CTRL_FLIT_ERR)),
855 FLAG_ENTRY0("event_cntr_parity_err", DCCE(EVENT_CNTR_PARITY_ERR)),
856 FLAG_ENTRY0("event_cntr_rollover_err", DCCE(EVENT_CNTR_ROLLOVER_ERR)),
857 FLAG_ENTRY0("link_err", DCCE(LINK_ERR)),
858 FLAG_ENTRY0("misc_cntr_rollover_err", DCCE(MISC_CNTR_ROLLOVER_ERR)),
859 FLAG_ENTRY0("bad_ctrl_dist_err", DCCE(BAD_CTRL_DIST_ERR)),
860 FLAG_ENTRY0("bad_tail_dist_err", DCCE(BAD_TAIL_DIST_ERR)),
861 FLAG_ENTRY0("bad_head_dist_err", DCCE(BAD_HEAD_DIST_ERR)),
862 FLAG_ENTRY0("nonvl15_state_err", DCCE(NONVL15_STATE_ERR)),
863 FLAG_ENTRY0("vl15_multi_err", DCCE(VL15_MULTI_ERR)),
864 FLAG_ENTRY0("bad_pkt_length_err", DCCE(BAD_PKT_LENGTH_ERR)),
865 FLAG_ENTRY0("unsup_vl_err", DCCE(UNSUP_VL_ERR)),
866 FLAG_ENTRY0("perm_nvl15_err", DCCE(PERM_NVL15_ERR)),
867 FLAG_ENTRY0("slid_zero_err", DCCE(SLID_ZERO_ERR)),
868 FLAG_ENTRY0("dlid_zero_err", DCCE(DLID_ZERO_ERR)),
869 FLAG_ENTRY0("length_mtu_err", DCCE(LENGTH_MTU_ERR)),
870 FLAG_ENTRY0("rx_early_drop_err", DCCE(RX_EARLY_DROP_ERR)),
871 FLAG_ENTRY0("late_short_err", DCCE(LATE_SHORT_ERR)),
872 FLAG_ENTRY0("late_long_err", DCCE(LATE_LONG_ERR)),
873 FLAG_ENTRY0("late_ebp_err", DCCE(LATE_EBP_ERR)),
874 FLAG_ENTRY0("fpe_tx_fifo_ovflw_err", DCCE(FPE_TX_FIFO_OVFLW_ERR)),
875 FLAG_ENTRY0("fpe_tx_fifo_unflw_err", DCCE(FPE_TX_FIFO_UNFLW_ERR)),
876 FLAG_ENTRY0("csr_access_blocked_host", DCCE(CSR_ACCESS_BLOCKED_HOST)),
877 FLAG_ENTRY0("csr_access_blocked_uc", DCCE(CSR_ACCESS_BLOCKED_UC)),
878 FLAG_ENTRY0("tx_ctrl_parity_err", DCCE(TX_CTRL_PARITY_ERR)),
879 FLAG_ENTRY0("tx_ctrl_parity_mbe_err", DCCE(TX_CTRL_PARITY_MBE_ERR)),
880 FLAG_ENTRY0("tx_sc_parity_err", DCCE(TX_SC_PARITY_ERR)),
881 FLAG_ENTRY0("rx_ctrl_parity_mbe_err", DCCE(RX_CTRL_PARITY_MBE_ERR)),
882 FLAG_ENTRY0("csr_parity_err", DCCE(CSR_PARITY_ERR)),
883 FLAG_ENTRY0("csr_inval_addr", DCCE(CSR_INVAL_ADDR)),
884 FLAG_ENTRY0("tx_byte_shft_parity_err", DCCE(TX_BYTE_SHFT_PARITY_ERR)),
885 FLAG_ENTRY0("rx_byte_shft_parity_err", DCCE(RX_BYTE_SHFT_PARITY_ERR)),
886 FLAG_ENTRY0("fmconfig_err", DCCE(FMCONFIG_ERR)),
887 FLAG_ENTRY0("rcvport_err", DCCE(RCVPORT_ERR)),
888};
889
890/*
891 * LCB error flags
892 */
893#define LCBE(name) DC_LCB_ERR_FLG_##name##_SMASK
894static struct flag_table lcb_err_flags[] = {
895/* 0*/ FLAG_ENTRY0("CSR_PARITY_ERR", LCBE(CSR_PARITY_ERR)),
896/* 1*/ FLAG_ENTRY0("INVALID_CSR_ADDR", LCBE(INVALID_CSR_ADDR)),
897/* 2*/ FLAG_ENTRY0("RST_FOR_FAILED_DESKEW", LCBE(RST_FOR_FAILED_DESKEW)),
898/* 3*/ FLAG_ENTRY0("ALL_LNS_FAILED_REINIT_TEST",
899 LCBE(ALL_LNS_FAILED_REINIT_TEST)),
900/* 4*/ FLAG_ENTRY0("LOST_REINIT_STALL_OR_TOS", LCBE(LOST_REINIT_STALL_OR_TOS)),
901/* 5*/ FLAG_ENTRY0("TX_LESS_THAN_FOUR_LNS", LCBE(TX_LESS_THAN_FOUR_LNS)),
902/* 6*/ FLAG_ENTRY0("RX_LESS_THAN_FOUR_LNS", LCBE(RX_LESS_THAN_FOUR_LNS)),
903/* 7*/ FLAG_ENTRY0("SEQ_CRC_ERR", LCBE(SEQ_CRC_ERR)),
904/* 8*/ FLAG_ENTRY0("REINIT_FROM_PEER", LCBE(REINIT_FROM_PEER)),
905/* 9*/ FLAG_ENTRY0("REINIT_FOR_LN_DEGRADE", LCBE(REINIT_FOR_LN_DEGRADE)),
906/*10*/ FLAG_ENTRY0("CRC_ERR_CNT_HIT_LIMIT", LCBE(CRC_ERR_CNT_HIT_LIMIT)),
907/*11*/ FLAG_ENTRY0("RCLK_STOPPED", LCBE(RCLK_STOPPED)),
908/*12*/ FLAG_ENTRY0("UNEXPECTED_REPLAY_MARKER", LCBE(UNEXPECTED_REPLAY_MARKER)),
909/*13*/ FLAG_ENTRY0("UNEXPECTED_ROUND_TRIP_MARKER",
910 LCBE(UNEXPECTED_ROUND_TRIP_MARKER)),
911/*14*/ FLAG_ENTRY0("ILLEGAL_NULL_LTP", LCBE(ILLEGAL_NULL_LTP)),
912/*15*/ FLAG_ENTRY0("ILLEGAL_FLIT_ENCODING", LCBE(ILLEGAL_FLIT_ENCODING)),
913/*16*/ FLAG_ENTRY0("FLIT_INPUT_BUF_OFLW", LCBE(FLIT_INPUT_BUF_OFLW)),
914/*17*/ FLAG_ENTRY0("VL_ACK_INPUT_BUF_OFLW", LCBE(VL_ACK_INPUT_BUF_OFLW)),
915/*18*/ FLAG_ENTRY0("VL_ACK_INPUT_PARITY_ERR", LCBE(VL_ACK_INPUT_PARITY_ERR)),
916/*19*/ FLAG_ENTRY0("VL_ACK_INPUT_WRONG_CRC_MODE",
917 LCBE(VL_ACK_INPUT_WRONG_CRC_MODE)),
918/*20*/ FLAG_ENTRY0("FLIT_INPUT_BUF_MBE", LCBE(FLIT_INPUT_BUF_MBE)),
919/*21*/ FLAG_ENTRY0("FLIT_INPUT_BUF_SBE", LCBE(FLIT_INPUT_BUF_SBE)),
920/*22*/ FLAG_ENTRY0("REPLAY_BUF_MBE", LCBE(REPLAY_BUF_MBE)),
921/*23*/ FLAG_ENTRY0("REPLAY_BUF_SBE", LCBE(REPLAY_BUF_SBE)),
922/*24*/ FLAG_ENTRY0("CREDIT_RETURN_FLIT_MBE", LCBE(CREDIT_RETURN_FLIT_MBE)),
923/*25*/ FLAG_ENTRY0("RST_FOR_LINK_TIMEOUT", LCBE(RST_FOR_LINK_TIMEOUT)),
924/*26*/ FLAG_ENTRY0("RST_FOR_INCOMPLT_RND_TRIP",
925 LCBE(RST_FOR_INCOMPLT_RND_TRIP)),
926/*27*/ FLAG_ENTRY0("HOLD_REINIT", LCBE(HOLD_REINIT)),
927/*28*/ FLAG_ENTRY0("NEG_EDGE_LINK_TRANSFER_ACTIVE",
928 LCBE(NEG_EDGE_LINK_TRANSFER_ACTIVE)),
929/*29*/ FLAG_ENTRY0("REDUNDANT_FLIT_PARITY_ERR",
930 LCBE(REDUNDANT_FLIT_PARITY_ERR))
931};
932
933/*
934 * DC8051 Error Flags
935 */
936#define D8E(name) DC_DC8051_ERR_FLG_##name##_SMASK
937static struct flag_table dc8051_err_flags[] = {
938 FLAG_ENTRY0("SET_BY_8051", D8E(SET_BY_8051)),
939 FLAG_ENTRY0("LOST_8051_HEART_BEAT", D8E(LOST_8051_HEART_BEAT)),
940 FLAG_ENTRY0("CRAM_MBE", D8E(CRAM_MBE)),
941 FLAG_ENTRY0("CRAM_SBE", D8E(CRAM_SBE)),
942 FLAG_ENTRY0("DRAM_MBE", D8E(DRAM_MBE)),
943 FLAG_ENTRY0("DRAM_SBE", D8E(DRAM_SBE)),
944 FLAG_ENTRY0("IRAM_MBE", D8E(IRAM_MBE)),
945 FLAG_ENTRY0("IRAM_SBE", D8E(IRAM_SBE)),
946 FLAG_ENTRY0("UNMATCHED_SECURE_MSG_ACROSS_BCC_LANES",
947 D8E(UNMATCHED_SECURE_MSG_ACROSS_BCC_LANES)),
948 FLAG_ENTRY0("INVALID_CSR_ADDR", D8E(INVALID_CSR_ADDR)),
949};
950
951/*
952 * DC8051 Information Error flags
953 *
954 * Flags in DC8051_DBG_ERR_INFO_SET_BY_8051.ERROR field.
955 */
956static struct flag_table dc8051_info_err_flags[] = {
957 FLAG_ENTRY0("Spico ROM check failed", SPICO_ROM_FAILED),
958 FLAG_ENTRY0("Unknown frame received", UNKNOWN_FRAME),
959 FLAG_ENTRY0("Target BER not met", TARGET_BER_NOT_MET),
960 FLAG_ENTRY0("Serdes internal loopback failure",
961 FAILED_SERDES_INTERNAL_LOOPBACK),
962 FLAG_ENTRY0("Failed SerDes init", FAILED_SERDES_INIT),
963 FLAG_ENTRY0("Failed LNI(Polling)", FAILED_LNI_POLLING),
964 FLAG_ENTRY0("Failed LNI(Debounce)", FAILED_LNI_DEBOUNCE),
965 FLAG_ENTRY0("Failed LNI(EstbComm)", FAILED_LNI_ESTBCOMM),
966 FLAG_ENTRY0("Failed LNI(OptEq)", FAILED_LNI_OPTEQ),
967 FLAG_ENTRY0("Failed LNI(VerifyCap_1)", FAILED_LNI_VERIFY_CAP1),
968 FLAG_ENTRY0("Failed LNI(VerifyCap_2)", FAILED_LNI_VERIFY_CAP2),
969 FLAG_ENTRY0("Failed LNI(ConfigLT)", FAILED_LNI_CONFIGLT)
970};
971
972/*
973 * DC8051 Information Host Information flags
974 *
975 * Flags in DC8051_DBG_ERR_INFO_SET_BY_8051.HOST_MSG field.
976 */
977static struct flag_table dc8051_info_host_msg_flags[] = {
978 FLAG_ENTRY0("Host request done", 0x0001),
979 FLAG_ENTRY0("BC SMA message", 0x0002),
980 FLAG_ENTRY0("BC PWR_MGM message", 0x0004),
981 FLAG_ENTRY0("BC Unknown message (BCC)", 0x0008),
982 FLAG_ENTRY0("BC Unknown message (LCB)", 0x0010),
983 FLAG_ENTRY0("External device config request", 0x0020),
984 FLAG_ENTRY0("VerifyCap all frames received", 0x0040),
985 FLAG_ENTRY0("LinkUp achieved", 0x0080),
986 FLAG_ENTRY0("Link going down", 0x0100),
987};
988
77241056
MM		 989static u32 encoded_size(u32 size);
990static u32 chip_to_opa_lstate(struct hfi1_devdata *dd, u32 chip_lstate);
991static int set_physical_link_state(struct hfi1_devdata *dd, u64 state);
992static void read_vc_remote_phy(struct hfi1_devdata *dd, u8 *power_management,
993 u8 *continuous);
994static void read_vc_remote_fabric(struct hfi1_devdata *dd, u8 *vau, u8 *z,
995 u8 *vcu, u16 *vl15buf, u8 *crc_sizes);
996static void read_vc_remote_link_width(struct hfi1_devdata *dd,
997 u8 *remote_tx_rate, u16 *link_widths);
998static void read_vc_local_link_width(struct hfi1_devdata *dd, u8 *misc_bits,
999 u8 *flag_bits, u16 *link_widths);
1000static void read_remote_device_id(struct hfi1_devdata *dd, u16 *device_id,
1001 u8 *device_rev);
1002static void read_mgmt_allowed(struct hfi1_devdata *dd, u8 *mgmt_allowed);
1003static void read_local_lni(struct hfi1_devdata *dd, u8 *enable_lane_rx);
1004static int read_tx_settings(struct hfi1_devdata *dd, u8 *enable_lane_tx,
1005 u8 *tx_polarity_inversion,
1006 u8 *rx_polarity_inversion, u8 *max_rate);
1007static void handle_sdma_eng_err(struct hfi1_devdata *dd,
1008 unsigned int context, u64 err_status);
1009static void handle_qsfp_int(struct hfi1_devdata *dd, u32 source, u64 reg);
1010static void handle_dcc_err(struct hfi1_devdata *dd,
1011 unsigned int context, u64 err_status);
1012static void handle_lcb_err(struct hfi1_devdata *dd,
1013 unsigned int context, u64 err_status);
1014static void handle_8051_interrupt(struct hfi1_devdata *dd, u32 unused, u64 reg);
1015static void handle_cce_err(struct hfi1_devdata *dd, u32 unused, u64 reg);
1016static void handle_rxe_err(struct hfi1_devdata *dd, u32 unused, u64 reg);
1017static void handle_misc_err(struct hfi1_devdata *dd, u32 unused, u64 reg);
1018static void handle_pio_err(struct hfi1_devdata *dd, u32 unused, u64 reg);
1019static void handle_sdma_err(struct hfi1_devdata *dd, u32 unused, u64 reg);
1020static void handle_egress_err(struct hfi1_devdata *dd, u32 unused, u64 reg);
1021static void handle_txe_err(struct hfi1_devdata *dd, u32 unused, u64 reg);
1022static void set_partition_keys(struct hfi1_pportdata *);
1023static const char *link_state_name(u32 state);
1024static const char *link_state_reason_name(struct hfi1_pportdata *ppd,
1025 u32 state);
1026static int do_8051_command(struct hfi1_devdata *dd, u32 type, u64 in_data,
1027 u64 *out_data);
1028static int read_idle_sma(struct hfi1_devdata *dd, u64 *data);
1029static int thermal_init(struct hfi1_devdata *dd);
1030
1031static int wait_logical_linkstate(struct hfi1_pportdata *ppd, u32 state,
1032 int msecs);
1033static void read_planned_down_reason_code(struct hfi1_devdata *dd, u8 *pdrrc);
1034static void handle_temp_err(struct hfi1_devdata *);
1035static void dc_shutdown(struct hfi1_devdata *);
1036static void dc_start(struct hfi1_devdata *);
1037
1038/*
1039 * Error interrupt table entry. This is used as input to the interrupt
1040 * "clear down" routine used for all second tier error interrupt register.
1041 * Second tier interrupt registers have a single bit representing them
1042 * in the top-level CceIntStatus.
1043 */
1044struct err_reg_info {
1045 u32 status; /* status CSR offset */
1046 u32 clear; /* clear CSR offset */
1047 u32 mask; /* mask CSR offset */
1048 void (*handler)(struct hfi1_devdata *dd, u32 source, u64 reg);
1049 const char *desc;
1050};
1051
1052#define NUM_MISC_ERRS (IS_GENERAL_ERR_END - IS_GENERAL_ERR_START)
1053#define NUM_DC_ERRS (IS_DC_END - IS_DC_START)
1054#define NUM_VARIOUS (IS_VARIOUS_END - IS_VARIOUS_START)
1055
1056/*
1057 * Helpers for building HFI and DC error interrupt table entries. Different
1058 * helpers are needed because of inconsistent register names.
1059 */
1060#define EE(reg, handler, desc) \
1061 { reg##_STATUS, reg##_CLEAR, reg##_MASK, \
1062 handler, desc }
1063#define DC_EE1(reg, handler, desc) \
1064 { reg##_FLG, reg##_FLG_CLR, reg##_FLG_EN, handler, desc }
1065#define DC_EE2(reg, handler, desc) \
1066 { reg##_FLG, reg##_CLR, reg##_EN, handler, desc }
1067
1068/*
1069 * Table of the "misc" grouping of error interrupts. Each entry refers to
1070 * another register containing more information.
1071 */
1072static const struct err_reg_info misc_errs[NUM_MISC_ERRS] = {
1073/* 0*/ EE(CCE_ERR, handle_cce_err, "CceErr"),
1074/* 1*/ EE(RCV_ERR, handle_rxe_err, "RxeErr"),
1075/* 2*/ EE(MISC_ERR, handle_misc_err, "MiscErr"),
1076/* 3*/ { 0, 0, 0, NULL }, /* reserved */
1077/* 4*/ EE(SEND_PIO_ERR, handle_pio_err, "PioErr"),
1078/* 5*/ EE(SEND_DMA_ERR, handle_sdma_err, "SDmaErr"),
1079/* 6*/ EE(SEND_EGRESS_ERR, handle_egress_err, "EgressErr"),
1080/* 7*/ EE(SEND_ERR, handle_txe_err, "TxeErr")
1081 /* the rest are reserved */
1082};
1083
1084/*
1085 * Index into the Various section of the interrupt sources
1086 * corresponding to the Critical Temperature interrupt.
1087 */
1088#define TCRIT_INT_SOURCE 4
1089
1090/*
1091 * SDMA error interrupt entry - refers to another register containing more
1092 * information.
1093 */
1094static const struct err_reg_info sdma_eng_err =
1095 EE(SEND_DMA_ENG_ERR, handle_sdma_eng_err, "SDmaEngErr");
1096
1097static const struct err_reg_info various_err[NUM_VARIOUS] = {
1098/* 0*/ { 0, 0, 0, NULL }, /* PbcInt */
1099/* 1*/ { 0, 0, 0, NULL }, /* GpioAssertInt */
1100/* 2*/ EE(ASIC_QSFP1, handle_qsfp_int, "QSFP1"),
1101/* 3*/ EE(ASIC_QSFP2, handle_qsfp_int, "QSFP2"),
1102/* 4*/ { 0, 0, 0, NULL }, /* TCritInt */
1103 /* rest are reserved */
1104};
1105
1106/*
1107 * The DC encoding of mtu_cap for 10K MTU in the DCC_CFG_PORT_CONFIG
1108 * register can not be derived from the MTU value because 10K is not
1109 * a power of 2. Therefore, we need a constant. Everything else can
1110 * be calculated.
1111 */
1112#define DCC_CFG_PORT_MTU_CAP_10240 7
1113
1114/*
1115 * Table of the DC grouping of error interrupts. Each entry refers to
1116 * another register containing more information.
1117 */
1118static const struct err_reg_info dc_errs[NUM_DC_ERRS] = {
1119/* 0*/ DC_EE1(DCC_ERR, handle_dcc_err, "DCC Err"),
1120/* 1*/ DC_EE2(DC_LCB_ERR, handle_lcb_err, "LCB Err"),
1121/* 2*/ DC_EE2(DC_DC8051_ERR, handle_8051_interrupt, "DC8051 Interrupt"),
1122/* 3*/ /* dc_lbm_int - special, see is_dc_int() */
1123 /* the rest are reserved */
1124};
1125
1126struct cntr_entry {
1127 /*
1128 * counter name
1129 */
1130 char *name;
1131
1132 /*
1133 * csr to read for name (if applicable)
1134 */
1135 u64 csr;
1136
1137 /*
1138 * offset into dd or ppd to store the counter's value
1139 */
1140 int offset;
1141
1142 /*
1143 * flags
1144 */
1145 u8 flags;
1146
1147 /*
1148 * accessor for stat element, context either dd or ppd
1149 */
1150 u64 (*rw_cntr)(const struct cntr_entry *,
1151 void *context,
1152 int vl,
1153 int mode,
1154 u64 data);
1155};
1156
1157#define C_RCV_HDR_OVF_FIRST C_RCV_HDR_OVF_0
1158#define C_RCV_HDR_OVF_LAST C_RCV_HDR_OVF_159
1159
1160#define CNTR_ELEM(name, csr, offset, flags, accessor) \
1161{ \
1162 name, \
1163 csr, \
1164 offset, \
1165 flags, \
1166 accessor \
1167}
1168
1169/* 32bit RXE */
1170#define RXE32_PORT_CNTR_ELEM(name, counter, flags) \
1171CNTR_ELEM(#name, \
1172 (counter * 8 + RCV_COUNTER_ARRAY32), \
1173 0, flags | CNTR_32BIT, \
1174 port_access_u32_csr)
1175
1176#define RXE32_DEV_CNTR_ELEM(name, counter, flags) \
1177CNTR_ELEM(#name, \
1178 (counter * 8 + RCV_COUNTER_ARRAY32), \
1179 0, flags | CNTR_32BIT, \
1180 dev_access_u32_csr)
1181
1182/* 64bit RXE */
1183#define RXE64_PORT_CNTR_ELEM(name, counter, flags) \
1184CNTR_ELEM(#name, \
1185 (counter * 8 + RCV_COUNTER_ARRAY64), \
1186 0, flags, \
1187 port_access_u64_csr)
1188
1189#define RXE64_DEV_CNTR_ELEM(name, counter, flags) \
1190CNTR_ELEM(#name, \
1191 (counter * 8 + RCV_COUNTER_ARRAY64), \
1192 0, flags, \
1193 dev_access_u64_csr)
1194
1195#define OVR_LBL(ctx) C_RCV_HDR_OVF_ ## ctx
1196#define OVR_ELM(ctx) \
1197CNTR_ELEM("RcvHdrOvr" #ctx, \
8638b77f 1198 (RCV_HDR_OVFL_CNT + ctx * 0x100), \
77241056
MM		 1199 0, CNTR_NORMAL, port_access_u64_csr)
1200
1201/* 32bit TXE */
1202#define TXE32_PORT_CNTR_ELEM(name, counter, flags) \
1203CNTR_ELEM(#name, \
1204 (counter * 8 + SEND_COUNTER_ARRAY32), \
1205 0, flags | CNTR_32BIT, \
1206 port_access_u32_csr)
1207
1208/* 64bit TXE */
1209#define TXE64_PORT_CNTR_ELEM(name, counter, flags) \
1210CNTR_ELEM(#name, \
1211 (counter * 8 + SEND_COUNTER_ARRAY64), \
1212 0, flags, \
1213 port_access_u64_csr)
1214
1215# define TX64_DEV_CNTR_ELEM(name, counter, flags) \
1216CNTR_ELEM(#name,\
1217 counter * 8 + SEND_COUNTER_ARRAY64, \
1218 0, \
1219 flags, \
1220 dev_access_u64_csr)
1221
1222/* CCE */
1223#define CCE_PERF_DEV_CNTR_ELEM(name, counter, flags) \
1224CNTR_ELEM(#name, \
1225 (counter * 8 + CCE_COUNTER_ARRAY32), \
1226 0, flags | CNTR_32BIT, \
1227 dev_access_u32_csr)
1228
1229#define CCE_INT_DEV_CNTR_ELEM(name, counter, flags) \
1230CNTR_ELEM(#name, \
1231 (counter * 8 + CCE_INT_COUNTER_ARRAY32), \
1232 0, flags | CNTR_32BIT, \
1233 dev_access_u32_csr)
1234
1235/* DC */
1236#define DC_PERF_CNTR(name, counter, flags) \
1237CNTR_ELEM(#name, \
1238 counter, \
1239 0, \
1240 flags, \
1241 dev_access_u64_csr)
1242
1243#define DC_PERF_CNTR_LCB(name, counter, flags) \
1244CNTR_ELEM(#name, \
1245 counter, \
1246 0, \
1247 flags, \
1248 dc_access_lcb_cntr)
1249
1250/* ibp counters */
1251#define SW_IBP_CNTR(name, cntr) \
1252CNTR_ELEM(#name, \
1253 0, \
1254 0, \
1255 CNTR_SYNTH, \
1256 access_ibp_##cntr)
1257
1258u64 read_csr(const struct hfi1_devdata *dd, u32 offset)
1259{
1260 u64 val;
1261
1262 if (dd->flags & HFI1_PRESENT) {
1263 val = readq((void __iomem *)dd->kregbase + offset);
1264 return val;
1265 }
1266 return -1;
1267}
1268
1269void write_csr(const struct hfi1_devdata *dd, u32 offset, u64 value)
1270{
1271 if (dd->flags & HFI1_PRESENT)
1272 writeq(value, (void __iomem *)dd->kregbase + offset);
1273}
1274
1275void __iomem *get_csr_addr(
1276 struct hfi1_devdata *dd,
1277 u32 offset)
1278{
1279 return (void __iomem *)dd->kregbase + offset;
1280}
1281
1282static inline u64 read_write_csr(const struct hfi1_devdata *dd, u32 csr,
1283 int mode, u64 value)
1284{
1285 u64 ret;
1286
77241056
MM		 1287 if (mode == CNTR_MODE_R) {
1288 ret = read_csr(dd, csr);
1289 } else if (mode == CNTR_MODE_W) {
1290 write_csr(dd, csr, value);
1291 ret = value;
1292 } else {
1293 dd_dev_err(dd, "Invalid cntr register access mode");
1294 return 0;
1295 }
1296
1297 hfi1_cdbg(CNTR, "csr 0x%x val 0x%llx mode %d", csr, ret, mode);
1298 return ret;
1299}
1300
1301/* Dev Access */
1302static u64 dev_access_u32_csr(const struct cntr_entry *entry,
1303 void *context, int vl, int mode, u64 data)
1304{
a787bde8 1305 struct hfi1_devdata *dd = context;
a699c6c2 1306 u64 csr = entry->csr;
77241056 1307
a699c6c2
VM		 1308 if (entry->flags & CNTR_SDMA) {
1309 if (vl == CNTR_INVALID_VL)
1310 return 0;
1311 csr += 0x100 * vl;
1312 } else {
1313 if (vl != CNTR_INVALID_VL)
1314 return 0;
1315 }
1316 return read_write_csr(dd, csr, mode, data);
1317}
1318
1319static u64 access_sde_err_cnt(const struct cntr_entry *entry,
1320 void *context, int idx, int mode, u64 data)
1321{
1322 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
1323
1324 if (dd->per_sdma && idx < dd->num_sdma)
1325 return dd->per_sdma[idx].err_cnt;
1326 return 0;
1327}
1328
1329static u64 access_sde_int_cnt(const struct cntr_entry *entry,
1330 void *context, int idx, int mode, u64 data)
1331{
1332 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
1333
1334 if (dd->per_sdma && idx < dd->num_sdma)
1335 return dd->per_sdma[idx].sdma_int_cnt;
1336 return 0;
1337}
1338
1339static u64 access_sde_idle_int_cnt(const struct cntr_entry *entry,
1340 void *context, int idx, int mode, u64 data)
1341{
1342 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
1343
1344 if (dd->per_sdma && idx < dd->num_sdma)
1345 return dd->per_sdma[idx].idle_int_cnt;
1346 return 0;
1347}
1348
1349static u64 access_sde_progress_int_cnt(const struct cntr_entry *entry,
1350 void *context, int idx, int mode,
1351 u64 data)
1352{
1353 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
1354
1355 if (dd->per_sdma && idx < dd->num_sdma)
1356 return dd->per_sdma[idx].progress_int_cnt;
1357 return 0;
77241056
MM		 1358}
1359
1360static u64 dev_access_u64_csr(const struct cntr_entry *entry, void *context,
1361 int vl, int mode, u64 data)
1362{
a787bde8 1363 struct hfi1_devdata *dd = context;
77241056
MM		 1364
1365 u64 val = 0;
1366 u64 csr = entry->csr;
1367
1368 if (entry->flags & CNTR_VL) {
1369 if (vl == CNTR_INVALID_VL)
1370 return 0;
1371 csr += 8 * vl;
1372 } else {
1373 if (vl != CNTR_INVALID_VL)
1374 return 0;
1375 }
1376
1377 val = read_write_csr(dd, csr, mode, data);
1378 return val;
1379}
1380
1381static u64 dc_access_lcb_cntr(const struct cntr_entry *entry, void *context,
1382 int vl, int mode, u64 data)
1383{
a787bde8 1384 struct hfi1_devdata *dd = context;
77241056
MM		 1385 u32 csr = entry->csr;
1386 int ret = 0;
1387
1388 if (vl != CNTR_INVALID_VL)
1389 return 0;
1390 if (mode == CNTR_MODE_R)
1391 ret = read_lcb_csr(dd, csr, &data);
1392 else if (mode == CNTR_MODE_W)
1393 ret = write_lcb_csr(dd, csr, data);
1394
1395 if (ret) {
1396 dd_dev_err(dd, "Could not acquire LCB for counter 0x%x", csr);
1397 return 0;
1398 }
1399
1400 hfi1_cdbg(CNTR, "csr 0x%x val 0x%llx mode %d", csr, data, mode);
1401 return data;
1402}
1403
1404/* Port Access */
1405static u64 port_access_u32_csr(const struct cntr_entry *entry, void *context,
1406 int vl, int mode, u64 data)
1407{
a787bde8 1408 struct hfi1_pportdata *ppd = context;
77241056
MM		 1409
1410 if (vl != CNTR_INVALID_VL)
1411 return 0;
1412 return read_write_csr(ppd->dd, entry->csr, mode, data);
1413}
1414
1415static u64 port_access_u64_csr(const struct cntr_entry *entry,
1416 void *context, int vl, int mode, u64 data)
1417{
a787bde8 1418 struct hfi1_pportdata *ppd = context;
77241056
MM		 1419 u64 val;
1420 u64 csr = entry->csr;
1421
1422 if (entry->flags & CNTR_VL) {
1423 if (vl == CNTR_INVALID_VL)
1424 return 0;
1425 csr += 8 * vl;
1426 } else {
1427 if (vl != CNTR_INVALID_VL)
1428 return 0;
1429 }
1430 val = read_write_csr(ppd->dd, csr, mode, data);
1431 return val;
1432}
1433
1434/* Software defined */
1435static inline u64 read_write_sw(struct hfi1_devdata *dd, u64 *cntr, int mode,
1436 u64 data)
1437{
1438 u64 ret;
1439
1440 if (mode == CNTR_MODE_R) {
1441 ret = *cntr;
1442 } else if (mode == CNTR_MODE_W) {
1443 *cntr = data;
1444 ret = data;
1445 } else {
1446 dd_dev_err(dd, "Invalid cntr sw access mode");
1447 return 0;
1448 }
1449
1450 hfi1_cdbg(CNTR, "val 0x%llx mode %d", ret, mode);
1451
1452 return ret;
1453}
1454
1455static u64 access_sw_link_dn_cnt(const struct cntr_entry *entry, void *context,
1456 int vl, int mode, u64 data)
1457{
a787bde8 1458 struct hfi1_pportdata *ppd = context;
77241056
MM		 1459
1460 if (vl != CNTR_INVALID_VL)
1461 return 0;
1462 return read_write_sw(ppd->dd, &ppd->link_downed, mode, data);
1463}
1464
1465static u64 access_sw_link_up_cnt(const struct cntr_entry *entry, void *context,
1466 int vl, int mode, u64 data)
1467{
a787bde8 1468 struct hfi1_pportdata *ppd = context;
77241056
MM		 1469
1470 if (vl != CNTR_INVALID_VL)
1471 return 0;
1472 return read_write_sw(ppd->dd, &ppd->link_up, mode, data);
1473}
1474
6d014530
DL		 1475static u64 access_sw_unknown_frame_cnt(const struct cntr_entry *entry,
1476 void *context, int vl, int mode,
1477 u64 data)
1478{
1479 struct hfi1_pportdata *ppd = (struct hfi1_pportdata *)context;
1480
1481 if (vl != CNTR_INVALID_VL)
1482 return 0;
1483 return read_write_sw(ppd->dd, &ppd->unknown_frame_count, mode, data);
1484}
1485
77241056
MM		 1486static u64 access_sw_xmit_discards(const struct cntr_entry *entry,
1487 void *context, int vl, int mode, u64 data)
1488{
69a00b8e
MM		 1489 struct hfi1_pportdata *ppd = (struct hfi1_pportdata *)context;
1490 u64 zero = 0;
1491 u64 *counter;
77241056 1492
69a00b8e
MM		 1493 if (vl == CNTR_INVALID_VL)
1494 counter = &ppd->port_xmit_discards;
1495 else if (vl >= 0 && vl < C_VL_COUNT)
1496 counter = &ppd->port_xmit_discards_vl[vl];
1497 else
1498 counter = &zero;
77241056 1499
69a00b8e 1500 return read_write_sw(ppd->dd, counter, mode, data);
77241056
MM		 1501}
1502
1503static u64 access_xmit_constraint_errs(const struct cntr_entry *entry,
1504 void *context, int vl, int mode, u64 data)
1505{
a787bde8 1506 struct hfi1_pportdata *ppd = context;
77241056
MM		 1507
1508 if (vl != CNTR_INVALID_VL)
1509 return 0;
1510
1511 return read_write_sw(ppd->dd, &ppd->port_xmit_constraint_errors,
1512 mode, data);
1513}
1514
1515static u64 access_rcv_constraint_errs(const struct cntr_entry *entry,
1516 void *context, int vl, int mode, u64 data)
1517{
a787bde8 1518 struct hfi1_pportdata *ppd = context;
77241056
MM		 1519
1520 if (vl != CNTR_INVALID_VL)
1521 return 0;
1522
1523 return read_write_sw(ppd->dd, &ppd->port_rcv_constraint_errors,
1524 mode, data);
1525}
1526
1527u64 get_all_cpu_total(u64 __percpu *cntr)
1528{
1529 int cpu;
1530 u64 counter = 0;
1531
1532 for_each_possible_cpu(cpu)
1533 counter += *per_cpu_ptr(cntr, cpu);
1534 return counter;
1535}
1536
1537static u64 read_write_cpu(struct hfi1_devdata *dd, u64 *z_val,
1538 u64 __percpu *cntr,
1539 int vl, int mode, u64 data)
1540{
1541
1542 u64 ret = 0;
1543
1544 if (vl != CNTR_INVALID_VL)
1545 return 0;
1546
1547 if (mode == CNTR_MODE_R) {
1548 ret = get_all_cpu_total(cntr) - *z_val;
1549 } else if (mode == CNTR_MODE_W) {
1550 /* A write can only zero the counter */
1551 if (data == 0)
1552 *z_val = get_all_cpu_total(cntr);
1553 else
1554 dd_dev_err(dd, "Per CPU cntrs can only be zeroed");
1555 } else {
1556 dd_dev_err(dd, "Invalid cntr sw cpu access mode");
1557 return 0;
1558 }
1559
1560 return ret;
1561}
1562
1563static u64 access_sw_cpu_intr(const struct cntr_entry *entry,
1564 void *context, int vl, int mode, u64 data)
1565{
a787bde8 1566 struct hfi1_devdata *dd = context;
77241056
MM		 1567
1568 return read_write_cpu(dd, &dd->z_int_counter, dd->int_counter, vl,
1569 mode, data);
1570}
1571
1572static u64 access_sw_cpu_rcv_limit(const struct cntr_entry *entry,
1573 void *context, int vl, int mode, u64 data)
1574{
a787bde8 1575 struct hfi1_devdata *dd = context;
77241056
MM		 1576
1577 return read_write_cpu(dd, &dd->z_rcv_limit, dd->rcv_limit, vl,
1578 mode, data);
1579}
1580
1581static u64 access_sw_pio_wait(const struct cntr_entry *entry,
1582 void *context, int vl, int mode, u64 data)
1583{
a787bde8 1584 struct hfi1_devdata *dd = context;
77241056
MM		 1585
1586 return dd->verbs_dev.n_piowait;
1587}
1588
14553ca1
MM		 1589static u64 access_sw_pio_drain(const struct cntr_entry *entry,
1590 void *context, int vl, int mode, u64 data)
1591{
1592 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
1593
1594 return dd->verbs_dev.n_piodrain;
1595}
1596
77241056
MM		 1597static u64 access_sw_vtx_wait(const struct cntr_entry *entry,
1598 void *context, int vl, int mode, u64 data)
1599{
a787bde8 1600 struct hfi1_devdata *dd = context;
77241056
MM		 1601
1602 return dd->verbs_dev.n_txwait;
1603}
1604
1605static u64 access_sw_kmem_wait(const struct cntr_entry *entry,
1606 void *context, int vl, int mode, u64 data)
1607{
a787bde8 1608 struct hfi1_devdata *dd = context;
77241056
MM		 1609
1610 return dd->verbs_dev.n_kmem_wait;
1611}
1612
b421922e
DL		 1613static u64 access_sw_send_schedule(const struct cntr_entry *entry,
1614 void *context, int vl, int mode, u64 data)
1615{
1616 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
1617
89abfc8d
VM		 1618 return read_write_cpu(dd, &dd->z_send_schedule, dd->send_schedule, vl,
1619 mode, data);
b421922e
DL		 1620}
1621
2c5b521a
JR		 1622/* Software counters for the error status bits within MISC_ERR_STATUS */
1623static u64 access_misc_pll_lock_fail_err_cnt(const struct cntr_entry *entry,
1624 void *context, int vl, int mode,
1625 u64 data)
1626{
1627 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
1628
1629 return dd->misc_err_status_cnt[12];
1630}
1631
1632static u64 access_misc_mbist_fail_err_cnt(const struct cntr_entry *entry,
1633 void *context, int vl, int mode,
1634 u64 data)
1635{
1636 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
1637
1638 return dd->misc_err_status_cnt[11];
1639}
1640
1641static u64 access_misc_invalid_eep_cmd_err_cnt(const struct cntr_entry *entry,
1642 void *context, int vl, int mode,
1643 u64 data)
1644{
1645 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
1646
1647 return dd->misc_err_status_cnt[10];
1648}
1649
1650static u64 access_misc_efuse_done_parity_err_cnt(const struct cntr_entry *entry,
1651 void *context, int vl,
1652 int mode, u64 data)
1653{
1654 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
1655
1656 return dd->misc_err_status_cnt[9];
1657}
1658
1659static u64 access_misc_efuse_write_err_cnt(const struct cntr_entry *entry,
1660 void *context, int vl, int mode,
1661 u64 data)
1662{
1663 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
1664
1665 return dd->misc_err_status_cnt[8];
1666}
1667
1668static u64 access_misc_efuse_read_bad_addr_err_cnt(
1669 const struct cntr_entry *entry,
1670 void *context, int vl, int mode, u64 data)
1671{
1672 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
1673
1674 return dd->misc_err_status_cnt[7];
1675}
1676
1677static u64 access_misc_efuse_csr_parity_err_cnt(const struct cntr_entry *entry,
1678 void *context, int vl,
1679 int mode, u64 data)
1680{
1681 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
1682
1683 return dd->misc_err_status_cnt[6];
1684}
1685
1686static u64 access_misc_fw_auth_failed_err_cnt(const struct cntr_entry *entry,
1687 void *context, int vl, int mode,
1688 u64 data)
1689{
1690 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
1691
1692 return dd->misc_err_status_cnt[5];
1693}
1694
1695static u64 access_misc_key_mismatch_err_cnt(const struct cntr_entry *entry,
1696 void *context, int vl, int mode,
1697 u64 data)
1698{
1699 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
1700
1701 return dd->misc_err_status_cnt[4];
1702}
1703
1704static u64 access_misc_sbus_write_failed_err_cnt(const struct cntr_entry *entry,
1705 void *context, int vl,
1706 int mode, u64 data)
1707{
1708 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
1709
1710 return dd->misc_err_status_cnt[3];
1711}
1712
1713static u64 access_misc_csr_write_bad_addr_err_cnt(
1714 const struct cntr_entry *entry,
1715 void *context, int vl, int mode, u64 data)
1716{
1717 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
1718
1719 return dd->misc_err_status_cnt[2];
1720}
1721
1722static u64 access_misc_csr_read_bad_addr_err_cnt(const struct cntr_entry *entry,
1723 void *context, int vl,
1724 int mode, u64 data)
1725{
1726 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
1727
1728 return dd->misc_err_status_cnt[1];
1729}
1730
1731static u64 access_misc_csr_parity_err_cnt(const struct cntr_entry *entry,
1732 void *context, int vl, int mode,
1733 u64 data)
1734{
1735 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
1736
1737 return dd->misc_err_status_cnt[0];
1738}
1739
1740/*
1741 * Software counter for the aggregate of
1742 * individual CceErrStatus counters
1743 */
1744static u64 access_sw_cce_err_status_aggregated_cnt(
1745 const struct cntr_entry *entry,
1746 void *context, int vl, int mode, u64 data)
1747{
1748 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
1749
1750 return dd->sw_cce_err_status_aggregate;
1751}
1752
1753/*
1754 * Software counters corresponding to each of the
1755 * error status bits within CceErrStatus
1756 */
1757static u64 access_cce_msix_csr_parity_err_cnt(const struct cntr_entry *entry,
1758 void *context, int vl, int mode,
1759 u64 data)
1760{
1761 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
1762
1763 return dd->cce_err_status_cnt[40];
1764}
1765
1766static u64 access_cce_int_map_unc_err_cnt(const struct cntr_entry *entry,
1767 void *context, int vl, int mode,
1768 u64 data)
1769{
1770 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
1771
1772 return dd->cce_err_status_cnt[39];
1773}
1774
1775static u64 access_cce_int_map_cor_err_cnt(const struct cntr_entry *entry,
1776 void *context, int vl, int mode,
1777 u64 data)
1778{
1779 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
1780
1781 return dd->cce_err_status_cnt[38];
1782}
1783
1784static u64 access_cce_msix_table_unc_err_cnt(const struct cntr_entry *entry,
1785 void *context, int vl, int mode,
1786 u64 data)
1787{
1788 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
1789
1790 return dd->cce_err_status_cnt[37];
1791}
1792
1793static u64 access_cce_msix_table_cor_err_cnt(const struct cntr_entry *entry,
1794 void *context, int vl, int mode,
1795 u64 data)
1796{
1797 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
1798
1799 return dd->cce_err_status_cnt[36];
1800}
1801
1802static u64 access_cce_rxdma_conv_fifo_parity_err_cnt(
1803 const struct cntr_entry *entry,
1804 void *context, int vl, int mode, u64 data)
1805{
1806 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
1807
1808 return dd->cce_err_status_cnt[35];
1809}
1810
1811static u64 access_cce_rcpl_async_fifo_parity_err_cnt(
1812 const struct cntr_entry *entry,
1813 void *context, int vl, int mode, u64 data)
1814{
1815 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
1816
1817 return dd->cce_err_status_cnt[34];
1818}
1819
1820static u64 access_cce_seg_write_bad_addr_err_cnt(const struct cntr_entry *entry,
1821 void *context, int vl,
1822 int mode, u64 data)
1823{
1824 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
1825
1826 return dd->cce_err_status_cnt[33];
1827}
1828
1829static u64 access_cce_seg_read_bad_addr_err_cnt(const struct cntr_entry *entry,
1830 void *context, int vl, int mode,
1831 u64 data)
1832{
1833 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
1834
1835 return dd->cce_err_status_cnt[32];
1836}
1837
1838static u64 access_la_triggered_cnt(const struct cntr_entry *entry,
1839 void *context, int vl, int mode, u64 data)
1840{
1841 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
1842
1843 return dd->cce_err_status_cnt[31];
1844}
1845
1846static u64 access_cce_trgt_cpl_timeout_err_cnt(const struct cntr_entry *entry,
1847 void *context, int vl, int mode,
1848 u64 data)
1849{
1850 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
1851
1852 return dd->cce_err_status_cnt[30];
1853}
1854
1855static u64 access_pcic_receive_parity_err_cnt(const struct cntr_entry *entry,
1856 void *context, int vl, int mode,
1857 u64 data)
1858{
1859 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
1860
1861 return dd->cce_err_status_cnt[29];
1862}
1863
1864static u64 access_pcic_transmit_back_parity_err_cnt(
1865 const struct cntr_entry *entry,
1866 void *context, int vl, int mode, u64 data)
1867{
1868 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
1869
1870 return dd->cce_err_status_cnt[28];
1871}
1872
1873static u64 access_pcic_transmit_front_parity_err_cnt(
1874 const struct cntr_entry *entry,
1875 void *context, int vl, int mode, u64 data)
1876{
1877 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
1878
1879 return dd->cce_err_status_cnt[27];
1880}
1881
1882static u64 access_pcic_cpl_dat_q_unc_err_cnt(const struct cntr_entry *entry,
1883 void *context, int vl, int mode,
1884 u64 data)
1885{
1886 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
1887
1888 return dd->cce_err_status_cnt[26];
1889}
1890
1891static u64 access_pcic_cpl_hd_q_unc_err_cnt(const struct cntr_entry *entry,
1892 void *context, int vl, int mode,
1893 u64 data)
1894{
1895 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
1896
1897 return dd->cce_err_status_cnt[25];
1898}
1899
1900static u64 access_pcic_post_dat_q_unc_err_cnt(const struct cntr_entry *entry,
1901 void *context, int vl, int mode,
1902 u64 data)
1903{
1904 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
1905
1906 return dd->cce_err_status_cnt[24];
1907}
1908
1909static u64 access_pcic_post_hd_q_unc_err_cnt(const struct cntr_entry *entry,
1910 void *context, int vl, int mode,
1911 u64 data)
1912{
1913 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
1914
1915 return dd->cce_err_status_cnt[23];
1916}
1917
1918static u64 access_pcic_retry_sot_mem_unc_err_cnt(const struct cntr_entry *entry,
1919 void *context, int vl,
1920 int mode, u64 data)
1921{
1922 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
1923
1924 return dd->cce_err_status_cnt[22];
1925}
1926
1927static u64 access_pcic_retry_mem_unc_err(const struct cntr_entry *entry,
1928 void *context, int vl, int mode,
1929 u64 data)
1930{
1931 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
1932
1933 return dd->cce_err_status_cnt[21];
1934}
1935
1936static u64 access_pcic_n_post_dat_q_parity_err_cnt(
1937 const struct cntr_entry *entry,
1938 void *context, int vl, int mode, u64 data)
1939{
1940 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
1941
1942 return dd->cce_err_status_cnt[20];
1943}
1944
1945static u64 access_pcic_n_post_h_q_parity_err_cnt(const struct cntr_entry *entry,
1946 void *context, int vl,
1947 int mode, u64 data)
1948{
1949 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
1950
1951 return dd->cce_err_status_cnt[19];
1952}
1953
1954static u64 access_pcic_cpl_dat_q_cor_err_cnt(const struct cntr_entry *entry,
1955 void *context, int vl, int mode,
1956 u64 data)
1957{
1958 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
1959
1960 return dd->cce_err_status_cnt[18];
1961}
1962
1963static u64 access_pcic_cpl_hd_q_cor_err_cnt(const struct cntr_entry *entry,
1964 void *context, int vl, int mode,
1965 u64 data)
1966{
1967 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
1968
1969 return dd->cce_err_status_cnt[17];
1970}
1971
1972static u64 access_pcic_post_dat_q_cor_err_cnt(const struct cntr_entry *entry,
1973 void *context, int vl, int mode,
1974 u64 data)
1975{
1976 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
1977
1978 return dd->cce_err_status_cnt[16];
1979}
1980
1981static u64 access_pcic_post_hd_q_cor_err_cnt(const struct cntr_entry *entry,
1982 void *context, int vl, int mode,
1983 u64 data)
1984{
1985 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
1986
1987 return dd->cce_err_status_cnt[15];
1988}
1989
1990static u64 access_pcic_retry_sot_mem_cor_err_cnt(const struct cntr_entry *entry,
1991 void *context, int vl,
1992 int mode, u64 data)
1993{
1994 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
1995
1996 return dd->cce_err_status_cnt[14];
1997}
1998
1999static u64 access_pcic_retry_mem_cor_err_cnt(const struct cntr_entry *entry,
2000 void *context, int vl, int mode,
2001 u64 data)
2002{
2003 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2004
2005 return dd->cce_err_status_cnt[13];
2006}
2007
2008static u64 access_cce_cli1_async_fifo_dbg_parity_err_cnt(
2009 const struct cntr_entry *entry,
2010 void *context, int vl, int mode, u64 data)
2011{
2012 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2013
2014 return dd->cce_err_status_cnt[12];
2015}
2016
2017static u64 access_cce_cli1_async_fifo_rxdma_parity_err_cnt(
2018 const struct cntr_entry *entry,
2019 void *context, int vl, int mode, u64 data)
2020{
2021 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2022
2023 return dd->cce_err_status_cnt[11];
2024}
2025
2026static u64 access_cce_cli1_async_fifo_sdma_hd_parity_err_cnt(
2027 const struct cntr_entry *entry,
2028 void *context, int vl, int mode, u64 data)
2029{
2030 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2031
2032 return dd->cce_err_status_cnt[10];
2033}
2034
2035static u64 access_cce_cl1_async_fifo_pio_crdt_parity_err_cnt(
2036 const struct cntr_entry *entry,
2037 void *context, int vl, int mode, u64 data)
2038{
2039 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2040
2041 return dd->cce_err_status_cnt[9];
2042}
2043
2044static u64 access_cce_cli2_async_fifo_parity_err_cnt(
2045 const struct cntr_entry *entry,
2046 void *context, int vl, int mode, u64 data)
2047{
2048 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2049
2050 return dd->cce_err_status_cnt[8];
2051}
2052
2053static u64 access_cce_csr_cfg_bus_parity_err_cnt(const struct cntr_entry *entry,
2054 void *context, int vl,
2055 int mode, u64 data)
2056{
2057 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2058
2059 return dd->cce_err_status_cnt[7];
2060}
2061
2062static u64 access_cce_cli0_async_fifo_parity_err_cnt(
2063 const struct cntr_entry *entry,
2064 void *context, int vl, int mode, u64 data)
2065{
2066 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2067
2068 return dd->cce_err_status_cnt[6];
2069}
2070
2071static u64 access_cce_rspd_data_parity_err_cnt(const struct cntr_entry *entry,
2072 void *context, int vl, int mode,
2073 u64 data)
2074{
2075 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2076
2077 return dd->cce_err_status_cnt[5];
2078}
2079
2080static u64 access_cce_trgt_access_err_cnt(const struct cntr_entry *entry,
2081 void *context, int vl, int mode,
2082 u64 data)
2083{
2084 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2085
2086 return dd->cce_err_status_cnt[4];
2087}
2088
2089static u64 access_cce_trgt_async_fifo_parity_err_cnt(
2090 const struct cntr_entry *entry,
2091 void *context, int vl, int mode, u64 data)
2092{
2093 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2094
2095 return dd->cce_err_status_cnt[3];
2096}
2097
2098static u64 access_cce_csr_write_bad_addr_err_cnt(const struct cntr_entry *entry,
2099 void *context, int vl,
2100 int mode, u64 data)
2101{
2102 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2103
2104 return dd->cce_err_status_cnt[2];
2105}
2106
2107static u64 access_cce_csr_read_bad_addr_err_cnt(const struct cntr_entry *entry,
2108 void *context, int vl,
2109 int mode, u64 data)
2110{
2111 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2112
2113 return dd->cce_err_status_cnt[1];
2114}
2115
2116static u64 access_ccs_csr_parity_err_cnt(const struct cntr_entry *entry,
2117 void *context, int vl, int mode,
2118 u64 data)
2119{
2120 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2121
2122 return dd->cce_err_status_cnt[0];
2123}
2124
2125/*
2126 * Software counters corresponding to each of the
2127 * error status bits within RcvErrStatus
2128 */
2129static u64 access_rx_csr_parity_err_cnt(const struct cntr_entry *entry,
2130 void *context, int vl, int mode,
2131 u64 data)
2132{
2133 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2134
2135 return dd->rcv_err_status_cnt[63];
2136}
2137
2138static u64 access_rx_csr_write_bad_addr_err_cnt(const struct cntr_entry *entry,
2139 void *context, int vl,
2140 int mode, u64 data)
2141{
2142 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2143
2144 return dd->rcv_err_status_cnt[62];
2145}
2146
2147static u64 access_rx_csr_read_bad_addr_err_cnt(const struct cntr_entry *entry,
2148 void *context, int vl, int mode,
2149 u64 data)
2150{
2151 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2152
2153 return dd->rcv_err_status_cnt[61];
2154}
2155
2156static u64 access_rx_dma_csr_unc_err_cnt(const struct cntr_entry *entry,
2157 void *context, int vl, int mode,
2158 u64 data)
2159{
2160 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2161
2162 return dd->rcv_err_status_cnt[60];
2163}
2164
2165static u64 access_rx_dma_dq_fsm_encoding_err_cnt(const struct cntr_entry *entry,
2166 void *context, int vl,
2167 int mode, u64 data)
2168{
2169 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2170
2171 return dd->rcv_err_status_cnt[59];
2172}
2173
2174static u64 access_rx_dma_eq_fsm_encoding_err_cnt(const struct cntr_entry *entry,
2175 void *context, int vl,
2176 int mode, u64 data)
2177{
2178 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2179
2180 return dd->rcv_err_status_cnt[58];
2181}
2182
2183static u64 access_rx_dma_csr_parity_err_cnt(const struct cntr_entry *entry,
2184 void *context, int vl, int mode,
2185 u64 data)
2186{
2187 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2188
2189 return dd->rcv_err_status_cnt[57];
2190}
2191
2192static u64 access_rx_rbuf_data_cor_err_cnt(const struct cntr_entry *entry,
2193 void *context, int vl, int mode,
2194 u64 data)
2195{
2196 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2197
2198 return dd->rcv_err_status_cnt[56];
2199}
2200
2201static u64 access_rx_rbuf_data_unc_err_cnt(const struct cntr_entry *entry,
2202 void *context, int vl, int mode,
2203 u64 data)
2204{
2205 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2206
2207 return dd->rcv_err_status_cnt[55];
2208}
2209
2210static u64 access_rx_dma_data_fifo_rd_cor_err_cnt(
2211 const struct cntr_entry *entry,
2212 void *context, int vl, int mode, u64 data)
2213{
2214 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2215
2216 return dd->rcv_err_status_cnt[54];
2217}
2218
2219static u64 access_rx_dma_data_fifo_rd_unc_err_cnt(
2220 const struct cntr_entry *entry,
2221 void *context, int vl, int mode, u64 data)
2222{
2223 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2224
2225 return dd->rcv_err_status_cnt[53];
2226}
2227
2228static u64 access_rx_dma_hdr_fifo_rd_cor_err_cnt(const struct cntr_entry *entry,
2229 void *context, int vl,
2230 int mode, u64 data)
2231{
2232 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2233
2234 return dd->rcv_err_status_cnt[52];
2235}
2236
2237static u64 access_rx_dma_hdr_fifo_rd_unc_err_cnt(const struct cntr_entry *entry,
2238 void *context, int vl,
2239 int mode, u64 data)
2240{
2241 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2242
2243 return dd->rcv_err_status_cnt[51];
2244}
2245
2246static u64 access_rx_rbuf_desc_part2_cor_err_cnt(const struct cntr_entry *entry,
2247 void *context, int vl,
2248 int mode, u64 data)
2249{
2250 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2251
2252 return dd->rcv_err_status_cnt[50];
2253}
2254
2255static u64 access_rx_rbuf_desc_part2_unc_err_cnt(const struct cntr_entry *entry,
2256 void *context, int vl,
2257 int mode, u64 data)
2258{
2259 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2260
2261 return dd->rcv_err_status_cnt[49];
2262}
2263
2264static u64 access_rx_rbuf_desc_part1_cor_err_cnt(const struct cntr_entry *entry,
2265 void *context, int vl,
2266 int mode, u64 data)
2267{
2268 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2269
2270 return dd->rcv_err_status_cnt[48];
2271}
2272
2273static u64 access_rx_rbuf_desc_part1_unc_err_cnt(const struct cntr_entry *entry,
2274 void *context, int vl,
2275 int mode, u64 data)
2276{
2277 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2278
2279 return dd->rcv_err_status_cnt[47];
2280}
2281
2282static u64 access_rx_hq_intr_fsm_err_cnt(const struct cntr_entry *entry,
2283 void *context, int vl, int mode,
2284 u64 data)
2285{
2286 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2287
2288 return dd->rcv_err_status_cnt[46];
2289}
2290
2291static u64 access_rx_hq_intr_csr_parity_err_cnt(
2292 const struct cntr_entry *entry,
2293 void *context, int vl, int mode, u64 data)
2294{
2295 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2296
2297 return dd->rcv_err_status_cnt[45];
2298}
2299
2300static u64 access_rx_lookup_csr_parity_err_cnt(
2301 const struct cntr_entry *entry,
2302 void *context, int vl, int mode, u64 data)
2303{
2304 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2305
2306 return dd->rcv_err_status_cnt[44];
2307}
2308
2309static u64 access_rx_lookup_rcv_array_cor_err_cnt(
2310 const struct cntr_entry *entry,
2311 void *context, int vl, int mode, u64 data)
2312{
2313 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2314
2315 return dd->rcv_err_status_cnt[43];
2316}
2317
2318static u64 access_rx_lookup_rcv_array_unc_err_cnt(
2319 const struct cntr_entry *entry,
2320 void *context, int vl, int mode, u64 data)
2321{
2322 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2323
2324 return dd->rcv_err_status_cnt[42];
2325}
2326
2327static u64 access_rx_lookup_des_part2_parity_err_cnt(
2328 const struct cntr_entry *entry,
2329 void *context, int vl, int mode, u64 data)
2330{
2331 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2332
2333 return dd->rcv_err_status_cnt[41];
2334}
2335
2336static u64 access_rx_lookup_des_part1_unc_cor_err_cnt(
2337 const struct cntr_entry *entry,
2338 void *context, int vl, int mode, u64 data)
2339{
2340 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2341
2342 return dd->rcv_err_status_cnt[40];
2343}
2344
2345static u64 access_rx_lookup_des_part1_unc_err_cnt(
2346 const struct cntr_entry *entry,
2347 void *context, int vl, int mode, u64 data)
2348{
2349 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2350
2351 return dd->rcv_err_status_cnt[39];
2352}
2353
2354static u64 access_rx_rbuf_next_free_buf_cor_err_cnt(
2355 const struct cntr_entry *entry,
2356 void *context, int vl, int mode, u64 data)
2357{
2358 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2359
2360 return dd->rcv_err_status_cnt[38];
2361}
2362
2363static u64 access_rx_rbuf_next_free_buf_unc_err_cnt(
2364 const struct cntr_entry *entry,
2365 void *context, int vl, int mode, u64 data)
2366{
2367 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2368
2369 return dd->rcv_err_status_cnt[37];
2370}
2371
2372static u64 access_rbuf_fl_init_wr_addr_parity_err_cnt(
2373 const struct cntr_entry *entry,
2374 void *context, int vl, int mode, u64 data)
2375{
2376 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2377
2378 return dd->rcv_err_status_cnt[36];
2379}
2380
2381static u64 access_rx_rbuf_fl_initdone_parity_err_cnt(
2382 const struct cntr_entry *entry,
2383 void *context, int vl, int mode, u64 data)
2384{
2385 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2386
2387 return dd->rcv_err_status_cnt[35];
2388}
2389
2390static u64 access_rx_rbuf_fl_write_addr_parity_err_cnt(
2391 const struct cntr_entry *entry,
2392 void *context, int vl, int mode, u64 data)
2393{
2394 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2395
2396 return dd->rcv_err_status_cnt[34];
2397}
2398
2399static u64 access_rx_rbuf_fl_rd_addr_parity_err_cnt(
2400 const struct cntr_entry *entry,
2401 void *context, int vl, int mode, u64 data)
2402{
2403 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2404
2405 return dd->rcv_err_status_cnt[33];
2406}
2407
2408static u64 access_rx_rbuf_empty_err_cnt(const struct cntr_entry *entry,
2409 void *context, int vl, int mode,
2410 u64 data)
2411{
2412 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2413
2414 return dd->rcv_err_status_cnt[32];
2415}
2416
2417static u64 access_rx_rbuf_full_err_cnt(const struct cntr_entry *entry,
2418 void *context, int vl, int mode,
2419 u64 data)
2420{
2421 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2422
2423 return dd->rcv_err_status_cnt[31];
2424}
2425
2426static u64 access_rbuf_bad_lookup_err_cnt(const struct cntr_entry *entry,
2427 void *context, int vl, int mode,
2428 u64 data)
2429{
2430 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2431
2432 return dd->rcv_err_status_cnt[30];
2433}
2434
2435static u64 access_rbuf_ctx_id_parity_err_cnt(const struct cntr_entry *entry,
2436 void *context, int vl, int mode,
2437 u64 data)
2438{
2439 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2440
2441 return dd->rcv_err_status_cnt[29];
2442}
2443
2444static u64 access_rbuf_csr_qeopdw_parity_err_cnt(const struct cntr_entry *entry,
2445 void *context, int vl,
2446 int mode, u64 data)
2447{
2448 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2449
2450 return dd->rcv_err_status_cnt[28];
2451}
2452
2453static u64 access_rx_rbuf_csr_q_num_of_pkt_parity_err_cnt(
2454 const struct cntr_entry *entry,
2455 void *context, int vl, int mode, u64 data)
2456{
2457 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2458
2459 return dd->rcv_err_status_cnt[27];
2460}
2461
2462static u64 access_rx_rbuf_csr_q_t1_ptr_parity_err_cnt(
2463 const struct cntr_entry *entry,
2464 void *context, int vl, int mode, u64 data)
2465{
2466 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2467
2468 return dd->rcv_err_status_cnt[26];
2469}
2470
2471static u64 access_rx_rbuf_csr_q_hd_ptr_parity_err_cnt(
2472 const struct cntr_entry *entry,
2473 void *context, int vl, int mode, u64 data)
2474{
2475 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2476
2477 return dd->rcv_err_status_cnt[25];
2478}
2479
2480static u64 access_rx_rbuf_csr_q_vld_bit_parity_err_cnt(
2481 const struct cntr_entry *entry,
2482 void *context, int vl, int mode, u64 data)
2483{
2484 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2485
2486 return dd->rcv_err_status_cnt[24];
2487}
2488
2489static u64 access_rx_rbuf_csr_q_next_buf_parity_err_cnt(
2490 const struct cntr_entry *entry,
2491 void *context, int vl, int mode, u64 data)
2492{
2493 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2494
2495 return dd->rcv_err_status_cnt[23];
2496}
2497
2498static u64 access_rx_rbuf_csr_q_ent_cnt_parity_err_cnt(
2499 const struct cntr_entry *entry,
2500 void *context, int vl, int mode, u64 data)
2501{
2502 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2503
2504 return dd->rcv_err_status_cnt[22];
2505}
2506
2507static u64 access_rx_rbuf_csr_q_head_buf_num_parity_err_cnt(
2508 const struct cntr_entry *entry,
2509 void *context, int vl, int mode, u64 data)
2510{
2511 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2512
2513 return dd->rcv_err_status_cnt[21];
2514}
2515
2516static u64 access_rx_rbuf_block_list_read_cor_err_cnt(
2517 const struct cntr_entry *entry,
2518 void *context, int vl, int mode, u64 data)
2519{
2520 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2521
2522 return dd->rcv_err_status_cnt[20];
2523}
2524
2525static u64 access_rx_rbuf_block_list_read_unc_err_cnt(
2526 const struct cntr_entry *entry,
2527 void *context, int vl, int mode, u64 data)
2528{
2529 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2530
2531 return dd->rcv_err_status_cnt[19];
2532}
2533
2534static u64 access_rx_rbuf_lookup_des_cor_err_cnt(const struct cntr_entry *entry,
2535 void *context, int vl,
2536 int mode, u64 data)
2537{
2538 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2539
2540 return dd->rcv_err_status_cnt[18];
2541}
2542
2543static u64 access_rx_rbuf_lookup_des_unc_err_cnt(const struct cntr_entry *entry,
2544 void *context, int vl,
2545 int mode, u64 data)
2546{
2547 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2548
2549 return dd->rcv_err_status_cnt[17];
2550}
2551
2552static u64 access_rx_rbuf_lookup_des_reg_unc_cor_err_cnt(
2553 const struct cntr_entry *entry,
2554 void *context, int vl, int mode, u64 data)
2555{
2556 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2557
2558 return dd->rcv_err_status_cnt[16];
2559}
2560
2561static u64 access_rx_rbuf_lookup_des_reg_unc_err_cnt(
2562 const struct cntr_entry *entry,
2563 void *context, int vl, int mode, u64 data)
2564{
2565 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2566
2567 return dd->rcv_err_status_cnt[15];
2568}
2569
2570static u64 access_rx_rbuf_free_list_cor_err_cnt(const struct cntr_entry *entry,
2571 void *context, int vl,
2572 int mode, u64 data)
2573{
2574 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2575
2576 return dd->rcv_err_status_cnt[14];
2577}
2578
2579static u64 access_rx_rbuf_free_list_unc_err_cnt(const struct cntr_entry *entry,
2580 void *context, int vl,
2581 int mode, u64 data)
2582{
2583 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2584
2585 return dd->rcv_err_status_cnt[13];
2586}
2587
2588static u64 access_rx_rcv_fsm_encoding_err_cnt(const struct cntr_entry *entry,
2589 void *context, int vl, int mode,
2590 u64 data)
2591{
2592 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2593
2594 return dd->rcv_err_status_cnt[12];
2595}
2596
2597static u64 access_rx_dma_flag_cor_err_cnt(const struct cntr_entry *entry,
2598 void *context, int vl, int mode,
2599 u64 data)
2600{
2601 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2602
2603 return dd->rcv_err_status_cnt[11];
2604}
2605
2606static u64 access_rx_dma_flag_unc_err_cnt(const struct cntr_entry *entry,
2607 void *context, int vl, int mode,
2608 u64 data)
2609{
2610 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2611
2612 return dd->rcv_err_status_cnt[10];
2613}
2614
2615static u64 access_rx_dc_sop_eop_parity_err_cnt(const struct cntr_entry *entry,
2616 void *context, int vl, int mode,
2617 u64 data)
2618{
2619 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2620
2621 return dd->rcv_err_status_cnt[9];
2622}
2623
2624static u64 access_rx_rcv_csr_parity_err_cnt(const struct cntr_entry *entry,
2625 void *context, int vl, int mode,
2626 u64 data)
2627{
2628 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2629
2630 return dd->rcv_err_status_cnt[8];
2631}
2632
2633static u64 access_rx_rcv_qp_map_table_cor_err_cnt(
2634 const struct cntr_entry *entry,
2635 void *context, int vl, int mode, u64 data)
2636{
2637 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2638
2639 return dd->rcv_err_status_cnt[7];
2640}
2641
2642static u64 access_rx_rcv_qp_map_table_unc_err_cnt(
2643 const struct cntr_entry *entry,
2644 void *context, int vl, int mode, u64 data)
2645{
2646 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2647
2648 return dd->rcv_err_status_cnt[6];
2649}
2650
2651static u64 access_rx_rcv_data_cor_err_cnt(const struct cntr_entry *entry,
2652 void *context, int vl, int mode,
2653 u64 data)
2654{
2655 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2656
2657 return dd->rcv_err_status_cnt[5];
2658}
2659
2660static u64 access_rx_rcv_data_unc_err_cnt(const struct cntr_entry *entry,
2661 void *context, int vl, int mode,
2662 u64 data)
2663{
2664 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2665
2666 return dd->rcv_err_status_cnt[4];
2667}
2668
2669static u64 access_rx_rcv_hdr_cor_err_cnt(const struct cntr_entry *entry,
2670 void *context, int vl, int mode,
2671 u64 data)
2672{
2673 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2674
2675 return dd->rcv_err_status_cnt[3];
2676}
2677
2678static u64 access_rx_rcv_hdr_unc_err_cnt(const struct cntr_entry *entry,
2679 void *context, int vl, int mode,
2680 u64 data)
2681{
2682 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2683
2684 return dd->rcv_err_status_cnt[2];
2685}
2686
2687static u64 access_rx_dc_intf_parity_err_cnt(const struct cntr_entry *entry,
2688 void *context, int vl, int mode,
2689 u64 data)
2690{
2691 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2692
2693 return dd->rcv_err_status_cnt[1];
2694}
2695
2696static u64 access_rx_dma_csr_cor_err_cnt(const struct cntr_entry *entry,
2697 void *context, int vl, int mode,
2698 u64 data)
2699{
2700 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2701
2702 return dd->rcv_err_status_cnt[0];
2703}
2704
2705/*
2706 * Software counters corresponding to each of the
2707 * error status bits within SendPioErrStatus
2708 */
2709static u64 access_pio_pec_sop_head_parity_err_cnt(
2710 const struct cntr_entry *entry,
2711 void *context, int vl, int mode, u64 data)
2712{
2713 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2714
2715 return dd->send_pio_err_status_cnt[35];
2716}
2717
2718static u64 access_pio_pcc_sop_head_parity_err_cnt(
2719 const struct cntr_entry *entry,
2720 void *context, int vl, int mode, u64 data)
2721{
2722 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2723
2724 return dd->send_pio_err_status_cnt[34];
2725}
2726
2727static u64 access_pio_last_returned_cnt_parity_err_cnt(
2728 const struct cntr_entry *entry,
2729 void *context, int vl, int mode, u64 data)
2730{
2731 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2732
2733 return dd->send_pio_err_status_cnt[33];
2734}
2735
2736static u64 access_pio_current_free_cnt_parity_err_cnt(
2737 const struct cntr_entry *entry,
2738 void *context, int vl, int mode, u64 data)
2739{
2740 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2741
2742 return dd->send_pio_err_status_cnt[32];
2743}
2744
2745static u64 access_pio_reserved_31_err_cnt(const struct cntr_entry *entry,
2746 void *context, int vl, int mode,
2747 u64 data)
2748{
2749 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2750
2751 return dd->send_pio_err_status_cnt[31];
2752}
2753
2754static u64 access_pio_reserved_30_err_cnt(const struct cntr_entry *entry,
2755 void *context, int vl, int mode,
2756 u64 data)
2757{
2758 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2759
2760 return dd->send_pio_err_status_cnt[30];
2761}
2762
2763static u64 access_pio_ppmc_sop_len_err_cnt(const struct cntr_entry *entry,
2764 void *context, int vl, int mode,
2765 u64 data)
2766{
2767 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2768
2769 return dd->send_pio_err_status_cnt[29];
2770}
2771
2772static u64 access_pio_ppmc_bqc_mem_parity_err_cnt(
2773 const struct cntr_entry *entry,
2774 void *context, int vl, int mode, u64 data)
2775{
2776 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2777
2778 return dd->send_pio_err_status_cnt[28];
2779}
2780
2781static u64 access_pio_vl_fifo_parity_err_cnt(const struct cntr_entry *entry,
2782 void *context, int vl, int mode,
2783 u64 data)
2784{
2785 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2786
2787 return dd->send_pio_err_status_cnt[27];
2788}
2789
2790static u64 access_pio_vlf_sop_parity_err_cnt(const struct cntr_entry *entry,
2791 void *context, int vl, int mode,
2792 u64 data)
2793{
2794 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2795
2796 return dd->send_pio_err_status_cnt[26];
2797}
2798
2799static u64 access_pio_vlf_v1_len_parity_err_cnt(const struct cntr_entry *entry,
2800 void *context, int vl,
2801 int mode, u64 data)
2802{
2803 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2804
2805 return dd->send_pio_err_status_cnt[25];
2806}
2807
2808static u64 access_pio_block_qw_count_parity_err_cnt(
2809 const struct cntr_entry *entry,
2810 void *context, int vl, int mode, u64 data)
2811{
2812 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2813
2814 return dd->send_pio_err_status_cnt[24];
2815}
2816
2817static u64 access_pio_write_qw_valid_parity_err_cnt(
2818 const struct cntr_entry *entry,
2819 void *context, int vl, int mode, u64 data)
2820{
2821 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2822
2823 return dd->send_pio_err_status_cnt[23];
2824}
2825
2826static u64 access_pio_state_machine_err_cnt(const struct cntr_entry *entry,
2827 void *context, int vl, int mode,
2828 u64 data)
2829{
2830 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2831
2832 return dd->send_pio_err_status_cnt[22];
2833}
2834
2835static u64 access_pio_write_data_parity_err_cnt(const struct cntr_entry *entry,
2836 void *context, int vl,
2837 int mode, u64 data)
2838{
2839 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2840
2841 return dd->send_pio_err_status_cnt[21];
2842}
2843
2844static u64 access_pio_host_addr_mem_cor_err_cnt(const struct cntr_entry *entry,
2845 void *context, int vl,
2846 int mode, u64 data)
2847{
2848 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2849
2850 return dd->send_pio_err_status_cnt[20];
2851}
2852
2853static u64 access_pio_host_addr_mem_unc_err_cnt(const struct cntr_entry *entry,
2854 void *context, int vl,
2855 int mode, u64 data)
2856{
2857 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2858
2859 return dd->send_pio_err_status_cnt[19];
2860}
2861
2862static u64 access_pio_pkt_evict_sm_or_arb_sm_err_cnt(
2863 const struct cntr_entry *entry,
2864 void *context, int vl, int mode, u64 data)
2865{
2866 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2867
2868 return dd->send_pio_err_status_cnt[18];
2869}
2870
2871static u64 access_pio_init_sm_in_err_cnt(const struct cntr_entry *entry,
2872 void *context, int vl, int mode,
2873 u64 data)
2874{
2875 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2876
2877 return dd->send_pio_err_status_cnt[17];
2878}
2879
2880static u64 access_pio_ppmc_pbl_fifo_err_cnt(const struct cntr_entry *entry,
2881 void *context, int vl, int mode,
2882 u64 data)
2883{
2884 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2885
2886 return dd->send_pio_err_status_cnt[16];
2887}
2888
2889static u64 access_pio_credit_ret_fifo_parity_err_cnt(
2890 const struct cntr_entry *entry,
2891 void *context, int vl, int mode, u64 data)
2892{
2893 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2894
2895 return dd->send_pio_err_status_cnt[15];
2896}
2897
2898static u64 access_pio_v1_len_mem_bank1_cor_err_cnt(
2899 const struct cntr_entry *entry,
2900 void *context, int vl, int mode, u64 data)
2901{
2902 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2903
2904 return dd->send_pio_err_status_cnt[14];
2905}
2906
2907static u64 access_pio_v1_len_mem_bank0_cor_err_cnt(
2908 const struct cntr_entry *entry,
2909 void *context, int vl, int mode, u64 data)
2910{
2911 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2912
2913 return dd->send_pio_err_status_cnt[13];
2914}
2915
2916static u64 access_pio_v1_len_mem_bank1_unc_err_cnt(
2917 const struct cntr_entry *entry,
2918 void *context, int vl, int mode, u64 data)
2919{
2920 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2921
2922 return dd->send_pio_err_status_cnt[12];
2923}
2924
2925static u64 access_pio_v1_len_mem_bank0_unc_err_cnt(
2926 const struct cntr_entry *entry,
2927 void *context, int vl, int mode, u64 data)
2928{
2929 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2930
2931 return dd->send_pio_err_status_cnt[11];
2932}
2933
2934static u64 access_pio_sm_pkt_reset_parity_err_cnt(
2935 const struct cntr_entry *entry,
2936 void *context, int vl, int mode, u64 data)
2937{
2938 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2939
2940 return dd->send_pio_err_status_cnt[10];
2941}
2942
2943static u64 access_pio_pkt_evict_fifo_parity_err_cnt(
2944 const struct cntr_entry *entry,
2945 void *context, int vl, int mode, u64 data)
2946{
2947 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2948
2949 return dd->send_pio_err_status_cnt[9];
2950}
2951
2952static u64 access_pio_sbrdctrl_crrel_fifo_parity_err_cnt(
2953 const struct cntr_entry *entry,
2954 void *context, int vl, int mode, u64 data)
2955{
2956 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2957
2958 return dd->send_pio_err_status_cnt[8];
2959}
2960
2961static u64 access_pio_sbrdctl_crrel_parity_err_cnt(
2962 const struct cntr_entry *entry,
2963 void *context, int vl, int mode, u64 data)
2964{
2965 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2966
2967 return dd->send_pio_err_status_cnt[7];
2968}
2969
2970static u64 access_pio_pec_fifo_parity_err_cnt(const struct cntr_entry *entry,
2971 void *context, int vl, int mode,
2972 u64 data)
2973{
2974 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2975
2976 return dd->send_pio_err_status_cnt[6];
2977}
2978
2979static u64 access_pio_pcc_fifo_parity_err_cnt(const struct cntr_entry *entry,
2980 void *context, int vl, int mode,
2981 u64 data)
2982{
2983 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2984
2985 return dd->send_pio_err_status_cnt[5];
2986}
2987
2988static u64 access_pio_sb_mem_fifo1_err_cnt(const struct cntr_entry *entry,
2989 void *context, int vl, int mode,
2990 u64 data)
2991{
2992 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2993
2994 return dd->send_pio_err_status_cnt[4];
2995}
2996
2997static u64 access_pio_sb_mem_fifo0_err_cnt(const struct cntr_entry *entry,
2998 void *context, int vl, int mode,
2999 u64 data)
3000{
3001 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3002
3003 return dd->send_pio_err_status_cnt[3];
3004}
3005
3006static u64 access_pio_csr_parity_err_cnt(const struct cntr_entry *entry,
3007 void *context, int vl, int mode,
3008 u64 data)
3009{
3010 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3011
3012 return dd->send_pio_err_status_cnt[2];
3013}
3014
3015static u64 access_pio_write_addr_parity_err_cnt(const struct cntr_entry *entry,
3016 void *context, int vl,
3017 int mode, u64 data)
3018{
3019 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3020
3021 return dd->send_pio_err_status_cnt[1];
3022}
3023
3024static u64 access_pio_write_bad_ctxt_err_cnt(const struct cntr_entry *entry,
3025 void *context, int vl, int mode,
3026 u64 data)
3027{
3028 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3029
3030 return dd->send_pio_err_status_cnt[0];
3031}
3032
3033/*
3034 * Software counters corresponding to each of the
3035 * error status bits within SendDmaErrStatus
3036 */
3037static u64 access_sdma_pcie_req_tracking_cor_err_cnt(
3038 const struct cntr_entry *entry,
3039 void *context, int vl, int mode, u64 data)
3040{
3041 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3042
3043 return dd->send_dma_err_status_cnt[3];
3044}
3045
3046static u64 access_sdma_pcie_req_tracking_unc_err_cnt(
3047 const struct cntr_entry *entry,
3048 void *context, int vl, int mode, u64 data)
3049{
3050 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3051
3052 return dd->send_dma_err_status_cnt[2];
3053}
3054
3055static u64 access_sdma_csr_parity_err_cnt(const struct cntr_entry *entry,
3056 void *context, int vl, int mode,
3057 u64 data)
3058{
3059 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3060
3061 return dd->send_dma_err_status_cnt[1];
3062}
3063
3064static u64 access_sdma_rpy_tag_err_cnt(const struct cntr_entry *entry,
3065 void *context, int vl, int mode,
3066 u64 data)
3067{
3068 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3069
3070 return dd->send_dma_err_status_cnt[0];
3071}
3072
3073/*
3074 * Software counters corresponding to each of the
3075 * error status bits within SendEgressErrStatus
3076 */
3077static u64 access_tx_read_pio_memory_csr_unc_err_cnt(
3078 const struct cntr_entry *entry,
3079 void *context, int vl, int mode, u64 data)
3080{
3081 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3082
3083 return dd->send_egress_err_status_cnt[63];
3084}
3085
3086static u64 access_tx_read_sdma_memory_csr_err_cnt(
3087 const struct cntr_entry *entry,
3088 void *context, int vl, int mode, u64 data)
3089{
3090 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3091
3092 return dd->send_egress_err_status_cnt[62];
3093}
3094
3095static u64 access_tx_egress_fifo_cor_err_cnt(const struct cntr_entry *entry,
3096 void *context, int vl, int mode,
3097 u64 data)
3098{
3099 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3100
3101 return dd->send_egress_err_status_cnt[61];
3102}
3103
3104static u64 access_tx_read_pio_memory_cor_err_cnt(const struct cntr_entry *entry,
3105 void *context, int vl,
3106 int mode, u64 data)
3107{
3108 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3109
3110 return dd->send_egress_err_status_cnt[60];
3111}
3112
3113static u64 access_tx_read_sdma_memory_cor_err_cnt(
3114 const struct cntr_entry *entry,
3115 void *context, int vl, int mode, u64 data)
3116{
3117 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3118
3119 return dd->send_egress_err_status_cnt[59];
3120}
3121
3122static u64 access_tx_sb_hdr_cor_err_cnt(const struct cntr_entry *entry,
3123 void *context, int vl, int mode,
3124 u64 data)
3125{
3126 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3127
3128 return dd->send_egress_err_status_cnt[58];
3129}
3130
3131static u64 access_tx_credit_overrun_err_cnt(const struct cntr_entry *entry,
3132 void *context, int vl, int mode,
3133 u64 data)
3134{
3135 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3136
3137 return dd->send_egress_err_status_cnt[57];
3138}
3139
3140static u64 access_tx_launch_fifo8_cor_err_cnt(const struct cntr_entry *entry,
3141 void *context, int vl, int mode,
3142 u64 data)
3143{
3144 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3145
3146 return dd->send_egress_err_status_cnt[56];
3147}
3148
3149static u64 access_tx_launch_fifo7_cor_err_cnt(const struct cntr_entry *entry,
3150 void *context, int vl, int mode,
3151 u64 data)
3152{
3153 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3154
3155 return dd->send_egress_err_status_cnt[55];
3156}
3157
3158static u64 access_tx_launch_fifo6_cor_err_cnt(const struct cntr_entry *entry,
3159 void *context, int vl, int mode,
3160 u64 data)
3161{
3162 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3163
3164 return dd->send_egress_err_status_cnt[54];
3165}
3166
3167static u64 access_tx_launch_fifo5_cor_err_cnt(const struct cntr_entry *entry,
3168 void *context, int vl, int mode,
3169 u64 data)
3170{
3171 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3172
3173 return dd->send_egress_err_status_cnt[53];
3174}
3175
3176static u64 access_tx_launch_fifo4_cor_err_cnt(const struct cntr_entry *entry,
3177 void *context, int vl, int mode,
3178 u64 data)
3179{
3180 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3181
3182 return dd->send_egress_err_status_cnt[52];
3183}
3184
3185static u64 access_tx_launch_fifo3_cor_err_cnt(const struct cntr_entry *entry,
3186 void *context, int vl, int mode,
3187 u64 data)
3188{
3189 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3190
3191 return dd->send_egress_err_status_cnt[51];
3192}
3193
3194static u64 access_tx_launch_fifo2_cor_err_cnt(const struct cntr_entry *entry,
3195 void *context, int vl, int mode,
3196 u64 data)
3197{
3198 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3199
3200 return dd->send_egress_err_status_cnt[50];
3201}
3202
3203static u64 access_tx_launch_fifo1_cor_err_cnt(const struct cntr_entry *entry,
3204 void *context, int vl, int mode,
3205 u64 data)
3206{
3207 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3208
3209 return dd->send_egress_err_status_cnt[49];
3210}
3211
3212static u64 access_tx_launch_fifo0_cor_err_cnt(const struct cntr_entry *entry,
3213 void *context, int vl, int mode,
3214 u64 data)
3215{
3216 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3217
3218 return dd->send_egress_err_status_cnt[48];
3219}
3220
3221static u64 access_tx_credit_return_vl_err_cnt(const struct cntr_entry *entry,
3222 void *context, int vl, int mode,
3223 u64 data)
3224{
3225 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3226
3227 return dd->send_egress_err_status_cnt[47];
3228}
3229
3230static u64 access_tx_hcrc_insertion_err_cnt(const struct cntr_entry *entry,
3231 void *context, int vl, int mode,
3232 u64 data)
3233{
3234 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3235
3236 return dd->send_egress_err_status_cnt[46];
3237}
3238
3239static u64 access_tx_egress_fifo_unc_err_cnt(const struct cntr_entry *entry,
3240 void *context, int vl, int mode,
3241 u64 data)
3242{
3243 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3244
3245 return dd->send_egress_err_status_cnt[45];
3246}
3247
3248static u64 access_tx_read_pio_memory_unc_err_cnt(const struct cntr_entry *entry,
3249 void *context, int vl,
3250 int mode, u64 data)
3251{
3252 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3253
3254 return dd->send_egress_err_status_cnt[44];
3255}
3256
3257static u64 access_tx_read_sdma_memory_unc_err_cnt(
3258 const struct cntr_entry *entry,
3259 void *context, int vl, int mode, u64 data)
3260{
3261 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3262
3263 return dd->send_egress_err_status_cnt[43];
3264}
3265
3266static u64 access_tx_sb_hdr_unc_err_cnt(const struct cntr_entry *entry,
3267 void *context, int vl, int mode,
3268 u64 data)
3269{
3270 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3271
3272 return dd->send_egress_err_status_cnt[42];
3273}
3274
3275static u64 access_tx_credit_return_partiy_err_cnt(
3276 const struct cntr_entry *entry,
3277 void *context, int vl, int mode, u64 data)
3278{
3279 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3280
3281 return dd->send_egress_err_status_cnt[41];
3282}
3283
3284static u64 access_tx_launch_fifo8_unc_or_parity_err_cnt(
3285 const struct cntr_entry *entry,
3286 void *context, int vl, int mode, u64 data)
3287{
3288 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3289
3290 return dd->send_egress_err_status_cnt[40];
3291}
3292
3293static u64 access_tx_launch_fifo7_unc_or_parity_err_cnt(
3294 const struct cntr_entry *entry,
3295 void *context, int vl, int mode, u64 data)
3296{
3297 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3298
3299 return dd->send_egress_err_status_cnt[39];
3300}
3301
3302static u64 access_tx_launch_fifo6_unc_or_parity_err_cnt(
3303 const struct cntr_entry *entry,
3304 void *context, int vl, int mode, u64 data)
3305{
3306 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3307
3308 return dd->send_egress_err_status_cnt[38];
3309}
3310
3311static u64 access_tx_launch_fifo5_unc_or_parity_err_cnt(
3312 const struct cntr_entry *entry,
3313 void *context, int vl, int mode, u64 data)
3314{
3315 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3316
3317 return dd->send_egress_err_status_cnt[37];
3318}
3319
3320static u64 access_tx_launch_fifo4_unc_or_parity_err_cnt(
3321 const struct cntr_entry *entry,
3322 void *context, int vl, int mode, u64 data)
3323{
3324 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3325
3326 return dd->send_egress_err_status_cnt[36];
3327}
3328
3329static u64 access_tx_launch_fifo3_unc_or_parity_err_cnt(
3330 const struct cntr_entry *entry,
3331 void *context, int vl, int mode, u64 data)
3332{
3333 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3334
3335 return dd->send_egress_err_status_cnt[35];
3336}
3337
3338static u64 access_tx_launch_fifo2_unc_or_parity_err_cnt(
3339 const struct cntr_entry *entry,
3340 void *context, int vl, int mode, u64 data)
3341{
3342 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3343
3344 return dd->send_egress_err_status_cnt[34];
3345}
3346
3347static u64 access_tx_launch_fifo1_unc_or_parity_err_cnt(
3348 const struct cntr_entry *entry,
3349 void *context, int vl, int mode, u64 data)
3350{
3351 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3352
3353 return dd->send_egress_err_status_cnt[33];
3354}
3355
3356static u64 access_tx_launch_fifo0_unc_or_parity_err_cnt(
3357 const struct cntr_entry *entry,
3358 void *context, int vl, int mode, u64 data)
3359{
3360 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3361
3362 return dd->send_egress_err_status_cnt[32];
3363}
3364
3365static u64 access_tx_sdma15_disallowed_packet_err_cnt(
3366 const struct cntr_entry *entry,
3367 void *context, int vl, int mode, u64 data)
3368{
3369 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3370
3371 return dd->send_egress_err_status_cnt[31];
3372}
3373
3374static u64 access_tx_sdma14_disallowed_packet_err_cnt(
3375 const struct cntr_entry *entry,
3376 void *context, int vl, int mode, u64 data)
3377{
3378 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3379
3380 return dd->send_egress_err_status_cnt[30];
3381}
3382
3383static u64 access_tx_sdma13_disallowed_packet_err_cnt(
3384 const struct cntr_entry *entry,
3385 void *context, int vl, int mode, u64 data)
3386{
3387 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3388
3389 return dd->send_egress_err_status_cnt[29];
3390}
3391
3392static u64 access_tx_sdma12_disallowed_packet_err_cnt(
3393 const struct cntr_entry *entry,
3394 void *context, int vl, int mode, u64 data)
3395{
3396 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3397
3398 return dd->send_egress_err_status_cnt[28];
3399}
3400
3401static u64 access_tx_sdma11_disallowed_packet_err_cnt(
3402 const struct cntr_entry *entry,
3403 void *context, int vl, int mode, u64 data)
3404{
3405 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3406
3407 return dd->send_egress_err_status_cnt[27];
3408}
3409
3410static u64 access_tx_sdma10_disallowed_packet_err_cnt(
3411 const struct cntr_entry *entry,
3412 void *context, int vl, int mode, u64 data)
3413{
3414 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3415
3416 return dd->send_egress_err_status_cnt[26];
3417}
3418
3419static u64 access_tx_sdma9_disallowed_packet_err_cnt(
3420 const struct cntr_entry *entry,
3421 void *context, int vl, int mode, u64 data)
3422{
3423 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3424
3425 return dd->send_egress_err_status_cnt[25];
3426}
3427
3428static u64 access_tx_sdma8_disallowed_packet_err_cnt(
3429 const struct cntr_entry *entry,
3430 void *context, int vl, int mode, u64 data)
3431{
3432 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3433
3434 return dd->send_egress_err_status_cnt[24];
3435}
3436
3437static u64 access_tx_sdma7_disallowed_packet_err_cnt(
3438 const struct cntr_entry *entry,
3439 void *context, int vl, int mode, u64 data)
3440{
3441 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3442
3443 return dd->send_egress_err_status_cnt[23];
3444}
3445
3446static u64 access_tx_sdma6_disallowed_packet_err_cnt(
3447 const struct cntr_entry *entry,
3448 void *context, int vl, int mode, u64 data)
3449{
3450 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3451
3452 return dd->send_egress_err_status_cnt[22];
3453}
3454
3455static u64 access_tx_sdma5_disallowed_packet_err_cnt(
3456 const struct cntr_entry *entry,
3457 void *context, int vl, int mode, u64 data)
3458{
3459 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3460
3461 return dd->send_egress_err_status_cnt[21];
3462}
3463
3464static u64 access_tx_sdma4_disallowed_packet_err_cnt(
3465 const struct cntr_entry *entry,
3466 void *context, int vl, int mode, u64 data)
3467{
3468 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3469
3470 return dd->send_egress_err_status_cnt[20];
3471}
3472
3473static u64 access_tx_sdma3_disallowed_packet_err_cnt(
3474 const struct cntr_entry *entry,
3475 void *context, int vl, int mode, u64 data)
3476{
3477 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3478
3479 return dd->send_egress_err_status_cnt[19];
3480}
3481
3482static u64 access_tx_sdma2_disallowed_packet_err_cnt(
3483 const struct cntr_entry *entry,
3484 void *context, int vl, int mode, u64 data)
3485{
3486 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3487
3488 return dd->send_egress_err_status_cnt[18];
3489}
3490
3491static u64 access_tx_sdma1_disallowed_packet_err_cnt(
3492 const struct cntr_entry *entry,
3493 void *context, int vl, int mode, u64 data)
3494{
3495 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3496
3497 return dd->send_egress_err_status_cnt[17];
3498}
3499
3500static u64 access_tx_sdma0_disallowed_packet_err_cnt(
3501 const struct cntr_entry *entry,
3502 void *context, int vl, int mode, u64 data)
3503{
3504 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3505
3506 return dd->send_egress_err_status_cnt[16];
3507}
3508
3509static u64 access_tx_config_parity_err_cnt(const struct cntr_entry *entry,
3510 void *context, int vl, int mode,
3511 u64 data)
3512{
3513 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3514
3515 return dd->send_egress_err_status_cnt[15];
3516}
3517
3518static u64 access_tx_sbrd_ctl_csr_parity_err_cnt(const struct cntr_entry *entry,
3519 void *context, int vl,
3520 int mode, u64 data)
3521{
3522 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3523
3524 return dd->send_egress_err_status_cnt[14];
3525}
3526
3527static u64 access_tx_launch_csr_parity_err_cnt(const struct cntr_entry *entry,
3528 void *context, int vl, int mode,
3529 u64 data)
3530{
3531 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3532
3533 return dd->send_egress_err_status_cnt[13];
3534}
3535
3536static u64 access_tx_illegal_vl_err_cnt(const struct cntr_entry *entry,
3537 void *context, int vl, int mode,
3538 u64 data)
3539{
3540 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3541
3542 return dd->send_egress_err_status_cnt[12];
3543}
3544
3545static u64 access_tx_sbrd_ctl_state_machine_parity_err_cnt(
3546 const struct cntr_entry *entry,
3547 void *context, int vl, int mode, u64 data)
3548{
3549 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3550
3551 return dd->send_egress_err_status_cnt[11];
3552}
3553
3554static u64 access_egress_reserved_10_err_cnt(const struct cntr_entry *entry,
3555 void *context, int vl, int mode,
3556 u64 data)
3557{
3558 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3559
3560 return dd->send_egress_err_status_cnt[10];
3561}
3562
3563static u64 access_egress_reserved_9_err_cnt(const struct cntr_entry *entry,
3564 void *context, int vl, int mode,
3565 u64 data)
3566{
3567 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3568
3569 return dd->send_egress_err_status_cnt[9];
3570}
3571
3572static u64 access_tx_sdma_launch_intf_parity_err_cnt(
3573 const struct cntr_entry *entry,
3574 void *context, int vl, int mode, u64 data)
3575{
3576 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3577
3578 return dd->send_egress_err_status_cnt[8];
3579}
3580
3581static u64 access_tx_pio_launch_intf_parity_err_cnt(
3582 const struct cntr_entry *entry,
3583 void *context, int vl, int mode, u64 data)
3584{
3585 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3586
3587 return dd->send_egress_err_status_cnt[7];
3588}
3589
3590static u64 access_egress_reserved_6_err_cnt(const struct cntr_entry *entry,
3591 void *context, int vl, int mode,
3592 u64 data)
3593{
3594 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3595
3596 return dd->send_egress_err_status_cnt[6];
3597}
3598
3599static u64 access_tx_incorrect_link_state_err_cnt(
3600 const struct cntr_entry *entry,
3601 void *context, int vl, int mode, u64 data)
3602{
3603 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3604
3605 return dd->send_egress_err_status_cnt[5];
3606}
3607
3608static u64 access_tx_linkdown_err_cnt(const struct cntr_entry *entry,
3609 void *context, int vl, int mode,
3610 u64 data)
3611{
3612 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3613
3614 return dd->send_egress_err_status_cnt[4];
3615}
3616
3617static u64 access_tx_egress_fifi_underrun_or_parity_err_cnt(
3618 const struct cntr_entry *entry,
3619 void *context, int vl, int mode, u64 data)
3620{
3621 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3622
3623 return dd->send_egress_err_status_cnt[3];
3624}
3625
3626static u64 access_egress_reserved_2_err_cnt(const struct cntr_entry *entry,
3627 void *context, int vl, int mode,
3628 u64 data)
3629{
3630 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3631
3632 return dd->send_egress_err_status_cnt[2];
3633}
3634
3635static u64 access_tx_pkt_integrity_mem_unc_err_cnt(
3636 const struct cntr_entry *entry,
3637 void *context, int vl, int mode, u64 data)
3638{
3639 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3640
3641 return dd->send_egress_err_status_cnt[1];
3642}
3643
3644static u64 access_tx_pkt_integrity_mem_cor_err_cnt(
3645 const struct cntr_entry *entry,
3646 void *context, int vl, int mode, u64 data)
3647{
3648 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3649
3650 return dd->send_egress_err_status_cnt[0];
3651}
3652
3653/*
3654 * Software counters corresponding to each of the
3655 * error status bits within SendErrStatus
3656 */
3657static u64 access_send_csr_write_bad_addr_err_cnt(
3658 const struct cntr_entry *entry,
3659 void *context, int vl, int mode, u64 data)
3660{
3661 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3662
3663 return dd->send_err_status_cnt[2];
3664}
3665
3666static u64 access_send_csr_read_bad_addr_err_cnt(const struct cntr_entry *entry,
3667 void *context, int vl,
3668 int mode, u64 data)
3669{
3670 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3671
3672 return dd->send_err_status_cnt[1];
3673}
3674
3675static u64 access_send_csr_parity_cnt(const struct cntr_entry *entry,
3676 void *context, int vl, int mode,
3677 u64 data)
3678{
3679 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3680
3681 return dd->send_err_status_cnt[0];
3682}
3683
3684/*
3685 * Software counters corresponding to each of the
3686 * error status bits within SendCtxtErrStatus
3687 */
3688static u64 access_pio_write_out_of_bounds_err_cnt(
3689 const struct cntr_entry *entry,
3690 void *context, int vl, int mode, u64 data)
3691{
3692 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3693
3694 return dd->sw_ctxt_err_status_cnt[4];
3695}
3696
3697static u64 access_pio_write_overflow_err_cnt(const struct cntr_entry *entry,
3698 void *context, int vl, int mode,
3699 u64 data)
3700{
3701 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3702
3703 return dd->sw_ctxt_err_status_cnt[3];
3704}
3705
3706static u64 access_pio_write_crosses_boundary_err_cnt(
3707 const struct cntr_entry *entry,
3708 void *context, int vl, int mode, u64 data)
3709{
3710 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3711
3712 return dd->sw_ctxt_err_status_cnt[2];
3713}
3714
3715static u64 access_pio_disallowed_packet_err_cnt(const struct cntr_entry *entry,
3716 void *context, int vl,
3717 int mode, u64 data)
3718{
3719 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3720
3721 return dd->sw_ctxt_err_status_cnt[1];
3722}
3723
3724static u64 access_pio_inconsistent_sop_err_cnt(const struct cntr_entry *entry,
3725 void *context, int vl, int mode,
3726 u64 data)
3727{
3728 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3729
3730 return dd->sw_ctxt_err_status_cnt[0];
3731}
3732
3733/*
3734 * Software counters corresponding to each of the
3735 * error status bits within SendDmaEngErrStatus
3736 */
3737static u64 access_sdma_header_request_fifo_cor_err_cnt(
3738 const struct cntr_entry *entry,
3739 void *context, int vl, int mode, u64 data)
3740{
3741 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3742
3743 return dd->sw_send_dma_eng_err_status_cnt[23];
3744}
3745
3746static u64 access_sdma_header_storage_cor_err_cnt(
3747 const struct cntr_entry *entry,
3748 void *context, int vl, int mode, u64 data)
3749{
3750 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3751
3752 return dd->sw_send_dma_eng_err_status_cnt[22];
3753}
3754
3755static u64 access_sdma_packet_tracking_cor_err_cnt(
3756 const struct cntr_entry *entry,
3757 void *context, int vl, int mode, u64 data)
3758{
3759 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3760
3761 return dd->sw_send_dma_eng_err_status_cnt[21];
3762}
3763
3764static u64 access_sdma_assembly_cor_err_cnt(const struct cntr_entry *entry,
3765 void *context, int vl, int mode,
3766 u64 data)
3767{
3768 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3769
3770 return dd->sw_send_dma_eng_err_status_cnt[20];
3771}
3772
3773static u64 access_sdma_desc_table_cor_err_cnt(const struct cntr_entry *entry,
3774 void *context, int vl, int mode,
3775 u64 data)
3776{
3777 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3778
3779 return dd->sw_send_dma_eng_err_status_cnt[19];
3780}
3781
3782static u64 access_sdma_header_request_fifo_unc_err_cnt(
3783 const struct cntr_entry *entry,
3784 void *context, int vl, int mode, u64 data)
3785{
3786 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3787
3788 return dd->sw_send_dma_eng_err_status_cnt[18];
3789}
3790
3791static u64 access_sdma_header_storage_unc_err_cnt(
3792 const struct cntr_entry *entry,
3793 void *context, int vl, int mode, u64 data)
3794{
3795 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3796
3797 return dd->sw_send_dma_eng_err_status_cnt[17];
3798}
3799
3800static u64 access_sdma_packet_tracking_unc_err_cnt(
3801 const struct cntr_entry *entry,
3802 void *context, int vl, int mode, u64 data)
3803{
3804 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3805
3806 return dd->sw_send_dma_eng_err_status_cnt[16];
3807}
3808
3809static u64 access_sdma_assembly_unc_err_cnt(const struct cntr_entry *entry,
3810 void *context, int vl, int mode,
3811 u64 data)
3812{
3813 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3814
3815 return dd->sw_send_dma_eng_err_status_cnt[15];
3816}
3817
3818static u64 access_sdma_desc_table_unc_err_cnt(const struct cntr_entry *entry,
3819 void *context, int vl, int mode,
3820 u64 data)
3821{
3822 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3823
3824 return dd->sw_send_dma_eng_err_status_cnt[14];
3825}
3826
3827static u64 access_sdma_timeout_err_cnt(const struct cntr_entry *entry,
3828 void *context, int vl, int mode,
3829 u64 data)
3830{
3831 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3832
3833 return dd->sw_send_dma_eng_err_status_cnt[13];
3834}
3835
3836static u64 access_sdma_header_length_err_cnt(const struct cntr_entry *entry,
3837 void *context, int vl, int mode,
3838 u64 data)
3839{
3840 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3841
3842 return dd->sw_send_dma_eng_err_status_cnt[12];
3843}
3844
3845static u64 access_sdma_header_address_err_cnt(const struct cntr_entry *entry,
3846 void *context, int vl, int mode,
3847 u64 data)
3848{
3849 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3850
3851 return dd->sw_send_dma_eng_err_status_cnt[11];
3852}
3853
3854static u64 access_sdma_header_select_err_cnt(const struct cntr_entry *entry,
3855 void *context, int vl, int mode,
3856 u64 data)
3857{
3858 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3859
3860 return dd->sw_send_dma_eng_err_status_cnt[10];
3861}
3862
3863static u64 access_sdma_reserved_9_err_cnt(const struct cntr_entry *entry,
3864 void *context, int vl, int mode,
3865 u64 data)
3866{
3867 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3868
3869 return dd->sw_send_dma_eng_err_status_cnt[9];
3870}
3871
3872static u64 access_sdma_packet_desc_overflow_err_cnt(
3873 const struct cntr_entry *entry,
3874 void *context, int vl, int mode, u64 data)
3875{
3876 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3877
3878 return dd->sw_send_dma_eng_err_status_cnt[8];
3879}
3880
3881static u64 access_sdma_length_mismatch_err_cnt(const struct cntr_entry *entry,
3882 void *context, int vl,
3883 int mode, u64 data)
3884{
3885 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3886
3887 return dd->sw_send_dma_eng_err_status_cnt[7];
3888}
3889
3890static u64 access_sdma_halt_err_cnt(const struct cntr_entry *entry,
3891 void *context, int vl, int mode, u64 data)
3892{
3893 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3894
3895 return dd->sw_send_dma_eng_err_status_cnt[6];
3896}
3897
3898static u64 access_sdma_mem_read_err_cnt(const struct cntr_entry *entry,
3899 void *context, int vl, int mode,
3900 u64 data)
3901{
3902 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3903
3904 return dd->sw_send_dma_eng_err_status_cnt[5];
3905}
3906
3907static u64 access_sdma_first_desc_err_cnt(const struct cntr_entry *entry,
3908 void *context, int vl, int mode,
3909 u64 data)
3910{
3911 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3912
3913 return dd->sw_send_dma_eng_err_status_cnt[4];
3914}
3915
3916static u64 access_sdma_tail_out_of_bounds_err_cnt(
3917 const struct cntr_entry *entry,
3918 void *context, int vl, int mode, u64 data)
3919{
3920 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3921
3922 return dd->sw_send_dma_eng_err_status_cnt[3];
3923}
3924
3925static u64 access_sdma_too_long_err_cnt(const struct cntr_entry *entry,
3926 void *context, int vl, int mode,
3927 u64 data)
3928{
3929 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3930
3931 return dd->sw_send_dma_eng_err_status_cnt[2];
3932}
3933
3934static u64 access_sdma_gen_mismatch_err_cnt(const struct cntr_entry *entry,
3935 void *context, int vl, int mode,
3936 u64 data)
3937{
3938 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3939
3940 return dd->sw_send_dma_eng_err_status_cnt[1];
3941}
3942
3943static u64 access_sdma_wrong_dw_err_cnt(const struct cntr_entry *entry,
3944 void *context, int vl, int mode,
3945 u64 data)
3946{
3947 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3948
3949 return dd->sw_send_dma_eng_err_status_cnt[0];
3950}
3951
77241056
MM		 3952#define def_access_sw_cpu(cntr) \
3953static u64 access_sw_cpu_##cntr(const struct cntr_entry *entry, \
3954 void *context, int vl, int mode, u64 data) \
3955{ \
3956 struct hfi1_pportdata *ppd = (struct hfi1_pportdata *)context; \
4eb06882
DD		 3957 return read_write_cpu(ppd->dd, &ppd->ibport_data.rvp.z_ ##cntr, \
3958 ppd->ibport_data.rvp.cntr, vl, \
77241056
MM		 3959 mode, data); \
3960}
3961
3962def_access_sw_cpu(rc_acks);
3963def_access_sw_cpu(rc_qacks);
3964def_access_sw_cpu(rc_delayed_comp);
3965
3966#define def_access_ibp_counter(cntr) \
3967static u64 access_ibp_##cntr(const struct cntr_entry *entry, \
3968 void *context, int vl, int mode, u64 data) \
3969{ \
3970 struct hfi1_pportdata *ppd = (struct hfi1_pportdata *)context; \
3971 \
3972 if (vl != CNTR_INVALID_VL) \
3973 return 0; \
3974 \
4eb06882 3975 return read_write_sw(ppd->dd, &ppd->ibport_data.rvp.n_ ##cntr, \
77241056
MM		 3976 mode, data); \
3977}
3978
3979def_access_ibp_counter(loop_pkts);
3980def_access_ibp_counter(rc_resends);
3981def_access_ibp_counter(rnr_naks);
3982def_access_ibp_counter(other_naks);
3983def_access_ibp_counter(rc_timeouts);
3984def_access_ibp_counter(pkt_drops);
3985def_access_ibp_counter(dmawait);
3986def_access_ibp_counter(rc_seqnak);
3987def_access_ibp_counter(rc_dupreq);
3988def_access_ibp_counter(rdma_seq);
3989def_access_ibp_counter(unaligned);
3990def_access_ibp_counter(seq_naks);
3991
3992static struct cntr_entry dev_cntrs[DEV_CNTR_LAST] = {
3993[C_RCV_OVF] = RXE32_DEV_CNTR_ELEM(RcvOverflow, RCV_BUF_OVFL_CNT, CNTR_SYNTH),
3994[C_RX_TID_FULL] = RXE32_DEV_CNTR_ELEM(RxTIDFullEr, RCV_TID_FULL_ERR_CNT,
3995 CNTR_NORMAL),
3996[C_RX_TID_INVALID] = RXE32_DEV_CNTR_ELEM(RxTIDInvalid, RCV_TID_VALID_ERR_CNT,
3997 CNTR_NORMAL),
3998[C_RX_TID_FLGMS] = RXE32_DEV_CNTR_ELEM(RxTidFLGMs,
3999 RCV_TID_FLOW_GEN_MISMATCH_CNT,
4000 CNTR_NORMAL),
77241056
MM		 4001[C_RX_CTX_EGRS] = RXE32_DEV_CNTR_ELEM(RxCtxEgrS, RCV_CONTEXT_EGR_STALL,
4002 CNTR_NORMAL),
4003[C_RCV_TID_FLSMS] = RXE32_DEV_CNTR_ELEM(RxTidFLSMs,
4004 RCV_TID_FLOW_SEQ_MISMATCH_CNT, CNTR_NORMAL),
4005[C_CCE_PCI_CR_ST] = CCE_PERF_DEV_CNTR_ELEM(CcePciCrSt,
4006 CCE_PCIE_POSTED_CRDT_STALL_CNT, CNTR_NORMAL),
4007[C_CCE_PCI_TR_ST] = CCE_PERF_DEV_CNTR_ELEM(CcePciTrSt, CCE_PCIE_TRGT_STALL_CNT,
4008 CNTR_NORMAL),
4009[C_CCE_PIO_WR_ST] = CCE_PERF_DEV_CNTR_ELEM(CcePioWrSt, CCE_PIO_WR_STALL_CNT,
4010 CNTR_NORMAL),
4011[C_CCE_ERR_INT] = CCE_INT_DEV_CNTR_ELEM(CceErrInt, CCE_ERR_INT_CNT,
4012 CNTR_NORMAL),
4013[C_CCE_SDMA_INT] = CCE_INT_DEV_CNTR_ELEM(CceSdmaInt, CCE_SDMA_INT_CNT,
4014 CNTR_NORMAL),
4015[C_CCE_MISC_INT] = CCE_INT_DEV_CNTR_ELEM(CceMiscInt, CCE_MISC_INT_CNT,
4016 CNTR_NORMAL),
4017[C_CCE_RCV_AV_INT] = CCE_INT_DEV_CNTR_ELEM(CceRcvAvInt, CCE_RCV_AVAIL_INT_CNT,
4018 CNTR_NORMAL),
4019[C_CCE_RCV_URG_INT] = CCE_INT_DEV_CNTR_ELEM(CceRcvUrgInt,
4020 CCE_RCV_URGENT_INT_CNT, CNTR_NORMAL),
4021[C_CCE_SEND_CR_INT] = CCE_INT_DEV_CNTR_ELEM(CceSndCrInt,
4022 CCE_SEND_CREDIT_INT_CNT, CNTR_NORMAL),
4023[C_DC_UNC_ERR] = DC_PERF_CNTR(DcUnctblErr, DCC_ERR_UNCORRECTABLE_CNT,
4024 CNTR_SYNTH),
4025[C_DC_RCV_ERR] = DC_PERF_CNTR(DcRecvErr, DCC_ERR_PORTRCV_ERR_CNT, CNTR_SYNTH),
4026[C_DC_FM_CFG_ERR] = DC_PERF_CNTR(DcFmCfgErr, DCC_ERR_FMCONFIG_ERR_CNT,
4027 CNTR_SYNTH),
4028[C_DC_RMT_PHY_ERR] = DC_PERF_CNTR(DcRmtPhyErr, DCC_ERR_RCVREMOTE_PHY_ERR_CNT,
4029 CNTR_SYNTH),
4030[C_DC_DROPPED_PKT] = DC_PERF_CNTR(DcDroppedPkt, DCC_ERR_DROPPED_PKT_CNT,
4031 CNTR_SYNTH),
4032[C_DC_MC_XMIT_PKTS] = DC_PERF_CNTR(DcMcXmitPkts,
4033 DCC_PRF_PORT_XMIT_MULTICAST_CNT, CNTR_SYNTH),
4034[C_DC_MC_RCV_PKTS] = DC_PERF_CNTR(DcMcRcvPkts,
4035 DCC_PRF_PORT_RCV_MULTICAST_PKT_CNT,
4036 CNTR_SYNTH),
4037[C_DC_XMIT_CERR] = DC_PERF_CNTR(DcXmitCorr,
4038 DCC_PRF_PORT_XMIT_CORRECTABLE_CNT, CNTR_SYNTH),
4039[C_DC_RCV_CERR] = DC_PERF_CNTR(DcRcvCorrCnt, DCC_PRF_PORT_RCV_CORRECTABLE_CNT,
4040 CNTR_SYNTH),
4041[C_DC_RCV_FCC] = DC_PERF_CNTR(DcRxFCntl, DCC_PRF_RX_FLOW_CRTL_CNT,
4042 CNTR_SYNTH),
4043[C_DC_XMIT_FCC] = DC_PERF_CNTR(DcXmitFCntl, DCC_PRF_TX_FLOW_CRTL_CNT,
4044 CNTR_SYNTH),
4045[C_DC_XMIT_FLITS] = DC_PERF_CNTR(DcXmitFlits, DCC_PRF_PORT_XMIT_DATA_CNT,
4046 CNTR_SYNTH),
4047[C_DC_RCV_FLITS] = DC_PERF_CNTR(DcRcvFlits, DCC_PRF_PORT_RCV_DATA_CNT,
4048 CNTR_SYNTH),
4049[C_DC_XMIT_PKTS] = DC_PERF_CNTR(DcXmitPkts, DCC_PRF_PORT_XMIT_PKTS_CNT,
4050 CNTR_SYNTH),
4051[C_DC_RCV_PKTS] = DC_PERF_CNTR(DcRcvPkts, DCC_PRF_PORT_RCV_PKTS_CNT,
4052 CNTR_SYNTH),
4053[C_DC_RX_FLIT_VL] = DC_PERF_CNTR(DcRxFlitVl, DCC_PRF_PORT_VL_RCV_DATA_CNT,
4054 CNTR_SYNTH | CNTR_VL),
4055[C_DC_RX_PKT_VL] = DC_PERF_CNTR(DcRxPktVl, DCC_PRF_PORT_VL_RCV_PKTS_CNT,
4056 CNTR_SYNTH | CNTR_VL),
4057[C_DC_RCV_FCN] = DC_PERF_CNTR(DcRcvFcn, DCC_PRF_PORT_RCV_FECN_CNT, CNTR_SYNTH),
4058[C_DC_RCV_FCN_VL] = DC_PERF_CNTR(DcRcvFcnVl, DCC_PRF_PORT_VL_RCV_FECN_CNT,
4059 CNTR_SYNTH | CNTR_VL),
4060[C_DC_RCV_BCN] = DC_PERF_CNTR(DcRcvBcn, DCC_PRF_PORT_RCV_BECN_CNT, CNTR_SYNTH),
4061[C_DC_RCV_BCN_VL] = DC_PERF_CNTR(DcRcvBcnVl, DCC_PRF_PORT_VL_RCV_BECN_CNT,
4062 CNTR_SYNTH | CNTR_VL),
4063[C_DC_RCV_BBL] = DC_PERF_CNTR(DcRcvBbl, DCC_PRF_PORT_RCV_BUBBLE_CNT,
4064 CNTR_SYNTH),
4065[C_DC_RCV_BBL_VL] = DC_PERF_CNTR(DcRcvBblVl, DCC_PRF_PORT_VL_RCV_BUBBLE_CNT,
4066 CNTR_SYNTH | CNTR_VL),
4067[C_DC_MARK_FECN] = DC_PERF_CNTR(DcMarkFcn, DCC_PRF_PORT_MARK_FECN_CNT,
4068 CNTR_SYNTH),
4069[C_DC_MARK_FECN_VL] = DC_PERF_CNTR(DcMarkFcnVl, DCC_PRF_PORT_VL_MARK_FECN_CNT,
4070 CNTR_SYNTH | CNTR_VL),
4071[C_DC_TOTAL_CRC] =
4072 DC_PERF_CNTR_LCB(DcTotCrc, DC_LCB_ERR_INFO_TOTAL_CRC_ERR,
4073 CNTR_SYNTH),
4074[C_DC_CRC_LN0] = DC_PERF_CNTR_LCB(DcCrcLn0, DC_LCB_ERR_INFO_CRC_ERR_LN0,
4075 CNTR_SYNTH),
4076[C_DC_CRC_LN1] = DC_PERF_CNTR_LCB(DcCrcLn1, DC_LCB_ERR_INFO_CRC_ERR_LN1,
4077 CNTR_SYNTH),
4078[C_DC_CRC_LN2] = DC_PERF_CNTR_LCB(DcCrcLn2, DC_LCB_ERR_INFO_CRC_ERR_LN2,
4079 CNTR_SYNTH),
4080[C_DC_CRC_LN3] = DC_PERF_CNTR_LCB(DcCrcLn3, DC_LCB_ERR_INFO_CRC_ERR_LN3,
4081 CNTR_SYNTH),
4082[C_DC_CRC_MULT_LN] =
4083 DC_PERF_CNTR_LCB(DcMultLn, DC_LCB_ERR_INFO_CRC_ERR_MULTI_LN,
4084 CNTR_SYNTH),
4085[C_DC_TX_REPLAY] = DC_PERF_CNTR_LCB(DcTxReplay, DC_LCB_ERR_INFO_TX_REPLAY_CNT,
4086 CNTR_SYNTH),
4087[C_DC_RX_REPLAY] = DC_PERF_CNTR_LCB(DcRxReplay, DC_LCB_ERR_INFO_RX_REPLAY_CNT,
4088 CNTR_SYNTH),
4089[C_DC_SEQ_CRC_CNT] =
4090 DC_PERF_CNTR_LCB(DcLinkSeqCrc, DC_LCB_ERR_INFO_SEQ_CRC_CNT,
4091 CNTR_SYNTH),
4092[C_DC_ESC0_ONLY_CNT] =
4093 DC_PERF_CNTR_LCB(DcEsc0, DC_LCB_ERR_INFO_ESCAPE_0_ONLY_CNT,
4094 CNTR_SYNTH),
4095[C_DC_ESC0_PLUS1_CNT] =
4096 DC_PERF_CNTR_LCB(DcEsc1, DC_LCB_ERR_INFO_ESCAPE_0_PLUS1_CNT,
4097 CNTR_SYNTH),
4098[C_DC_ESC0_PLUS2_CNT] =
4099 DC_PERF_CNTR_LCB(DcEsc0Plus2, DC_LCB_ERR_INFO_ESCAPE_0_PLUS2_CNT,
4100 CNTR_SYNTH),
4101[C_DC_REINIT_FROM_PEER_CNT] =
4102 DC_PERF_CNTR_LCB(DcReinitPeer, DC_LCB_ERR_INFO_REINIT_FROM_PEER_CNT,
4103 CNTR_SYNTH),
4104[C_DC_SBE_CNT] = DC_PERF_CNTR_LCB(DcSbe, DC_LCB_ERR_INFO_SBE_CNT,
4105 CNTR_SYNTH),
4106[C_DC_MISC_FLG_CNT] =
4107 DC_PERF_CNTR_LCB(DcMiscFlg, DC_LCB_ERR_INFO_MISC_FLG_CNT,
4108 CNTR_SYNTH),
4109[C_DC_PRF_GOOD_LTP_CNT] =
4110 DC_PERF_CNTR_LCB(DcGoodLTP, DC_LCB_PRF_GOOD_LTP_CNT, CNTR_SYNTH),
4111[C_DC_PRF_ACCEPTED_LTP_CNT] =
4112 DC_PERF_CNTR_LCB(DcAccLTP, DC_LCB_PRF_ACCEPTED_LTP_CNT,
4113 CNTR_SYNTH),
4114[C_DC_PRF_RX_FLIT_CNT] =
4115 DC_PERF_CNTR_LCB(DcPrfRxFlit, DC_LCB_PRF_RX_FLIT_CNT, CNTR_SYNTH),
4116[C_DC_PRF_TX_FLIT_CNT] =
4117 DC_PERF_CNTR_LCB(DcPrfTxFlit, DC_LCB_PRF_TX_FLIT_CNT, CNTR_SYNTH),
4118[C_DC_PRF_CLK_CNTR] =
4119 DC_PERF_CNTR_LCB(DcPrfClk, DC_LCB_PRF_CLK_CNTR, CNTR_SYNTH),
4120[C_DC_PG_DBG_FLIT_CRDTS_CNT] =
4121 DC_PERF_CNTR_LCB(DcFltCrdts, DC_LCB_PG_DBG_FLIT_CRDTS_CNT, CNTR_SYNTH),
4122[C_DC_PG_STS_PAUSE_COMPLETE_CNT] =
4123 DC_PERF_CNTR_LCB(DcPauseComp, DC_LCB_PG_STS_PAUSE_COMPLETE_CNT,
4124 CNTR_SYNTH),
4125[C_DC_PG_STS_TX_SBE_CNT] =
4126 DC_PERF_CNTR_LCB(DcStsTxSbe, DC_LCB_PG_STS_TX_SBE_CNT, CNTR_SYNTH),
4127[C_DC_PG_STS_TX_MBE_CNT] =
4128 DC_PERF_CNTR_LCB(DcStsTxMbe, DC_LCB_PG_STS_TX_MBE_CNT,
4129 CNTR_SYNTH),
4130[C_SW_CPU_INTR] = CNTR_ELEM("Intr", 0, 0, CNTR_NORMAL,
4131 access_sw_cpu_intr),
4132[C_SW_CPU_RCV_LIM] = CNTR_ELEM("RcvLimit", 0, 0, CNTR_NORMAL,
4133 access_sw_cpu_rcv_limit),
4134[C_SW_VTX_WAIT] = CNTR_ELEM("vTxWait", 0, 0, CNTR_NORMAL,
4135 access_sw_vtx_wait),
4136[C_SW_PIO_WAIT] = CNTR_ELEM("PioWait", 0, 0, CNTR_NORMAL,
4137 access_sw_pio_wait),
14553ca1
MM		 4138[C_SW_PIO_DRAIN] = CNTR_ELEM("PioDrain", 0, 0, CNTR_NORMAL,
4139 access_sw_pio_drain),
77241056
MM		 4140[C_SW_KMEM_WAIT] = CNTR_ELEM("KmemWait", 0, 0, CNTR_NORMAL,
4141 access_sw_kmem_wait),
b421922e
DL		 4142[C_SW_SEND_SCHED] = CNTR_ELEM("SendSched", 0, 0, CNTR_NORMAL,
4143 access_sw_send_schedule),
a699c6c2
VM		 4144[C_SDMA_DESC_FETCHED_CNT] = CNTR_ELEM("SDEDscFdCn",
4145 SEND_DMA_DESC_FETCHED_CNT, 0,
4146 CNTR_NORMAL | CNTR_32BIT | CNTR_SDMA,
4147 dev_access_u32_csr),
4148[C_SDMA_INT_CNT] = CNTR_ELEM("SDMAInt", 0, 0,
4149 CNTR_NORMAL | CNTR_32BIT | CNTR_SDMA,
4150 access_sde_int_cnt),
4151[C_SDMA_ERR_CNT] = CNTR_ELEM("SDMAErrCt", 0, 0,
4152 CNTR_NORMAL | CNTR_32BIT | CNTR_SDMA,
4153 access_sde_err_cnt),
4154[C_SDMA_IDLE_INT_CNT] = CNTR_ELEM("SDMAIdInt", 0, 0,
4155 CNTR_NORMAL | CNTR_32BIT | CNTR_SDMA,
4156 access_sde_idle_int_cnt),
4157[C_SDMA_PROGRESS_INT_CNT] = CNTR_ELEM("SDMAPrIntCn", 0, 0,
4158 CNTR_NORMAL | CNTR_32BIT | CNTR_SDMA,
4159 access_sde_progress_int_cnt),
2c5b521a
JR		 4160/* MISC_ERR_STATUS */
4161[C_MISC_PLL_LOCK_FAIL_ERR] = CNTR_ELEM("MISC_PLL_LOCK_FAIL_ERR", 0, 0,
4162 CNTR_NORMAL,
4163 access_misc_pll_lock_fail_err_cnt),
4164[C_MISC_MBIST_FAIL_ERR] = CNTR_ELEM("MISC_MBIST_FAIL_ERR", 0, 0,
4165 CNTR_NORMAL,
4166 access_misc_mbist_fail_err_cnt),
4167[C_MISC_INVALID_EEP_CMD_ERR] = CNTR_ELEM("MISC_INVALID_EEP_CMD_ERR", 0, 0,
4168 CNTR_NORMAL,
4169 access_misc_invalid_eep_cmd_err_cnt),
4170[C_MISC_EFUSE_DONE_PARITY_ERR] = CNTR_ELEM("MISC_EFUSE_DONE_PARITY_ERR", 0, 0,
4171 CNTR_NORMAL,
4172 access_misc_efuse_done_parity_err_cnt),
4173[C_MISC_EFUSE_WRITE_ERR] = CNTR_ELEM("MISC_EFUSE_WRITE_ERR", 0, 0,
4174 CNTR_NORMAL,
4175 access_misc_efuse_write_err_cnt),
4176[C_MISC_EFUSE_READ_BAD_ADDR_ERR] = CNTR_ELEM("MISC_EFUSE_READ_BAD_ADDR_ERR", 0,
4177 0, CNTR_NORMAL,
4178 access_misc_efuse_read_bad_addr_err_cnt),
4179[C_MISC_EFUSE_CSR_PARITY_ERR] = CNTR_ELEM("MISC_EFUSE_CSR_PARITY_ERR", 0, 0,
4180 CNTR_NORMAL,
4181 access_misc_efuse_csr_parity_err_cnt),
4182[C_MISC_FW_AUTH_FAILED_ERR] = CNTR_ELEM("MISC_FW_AUTH_FAILED_ERR", 0, 0,
4183 CNTR_NORMAL,
4184 access_misc_fw_auth_failed_err_cnt),
4185[C_MISC_KEY_MISMATCH_ERR] = CNTR_ELEM("MISC_KEY_MISMATCH_ERR", 0, 0,
4186 CNTR_NORMAL,
4187 access_misc_key_mismatch_err_cnt),
4188[C_MISC_SBUS_WRITE_FAILED_ERR] = CNTR_ELEM("MISC_SBUS_WRITE_FAILED_ERR", 0, 0,
4189 CNTR_NORMAL,
4190 access_misc_sbus_write_failed_err_cnt),
4191[C_MISC_CSR_WRITE_BAD_ADDR_ERR] = CNTR_ELEM("MISC_CSR_WRITE_BAD_ADDR_ERR", 0, 0,
4192 CNTR_NORMAL,
4193 access_misc_csr_write_bad_addr_err_cnt),
4194[C_MISC_CSR_READ_BAD_ADDR_ERR] = CNTR_ELEM("MISC_CSR_READ_BAD_ADDR_ERR", 0, 0,
4195 CNTR_NORMAL,
4196 access_misc_csr_read_bad_addr_err_cnt),
4197[C_MISC_CSR_PARITY_ERR] = CNTR_ELEM("MISC_CSR_PARITY_ERR", 0, 0,
4198 CNTR_NORMAL,
4199 access_misc_csr_parity_err_cnt),
4200/* CceErrStatus */
4201[C_CCE_ERR_STATUS_AGGREGATED_CNT] = CNTR_ELEM("CceErrStatusAggregatedCnt", 0, 0,
4202 CNTR_NORMAL,
4203 access_sw_cce_err_status_aggregated_cnt),
4204[C_CCE_MSIX_CSR_PARITY_ERR] = CNTR_ELEM("CceMsixCsrParityErr", 0, 0,
4205 CNTR_NORMAL,
4206 access_cce_msix_csr_parity_err_cnt),
4207[C_CCE_INT_MAP_UNC_ERR] = CNTR_ELEM("CceIntMapUncErr", 0, 0,
4208 CNTR_NORMAL,
4209 access_cce_int_map_unc_err_cnt),
4210[C_CCE_INT_MAP_COR_ERR] = CNTR_ELEM("CceIntMapCorErr", 0, 0,
4211 CNTR_NORMAL,
4212 access_cce_int_map_cor_err_cnt),
4213[C_CCE_MSIX_TABLE_UNC_ERR] = CNTR_ELEM("CceMsixTableUncErr", 0, 0,
4214 CNTR_NORMAL,
4215 access_cce_msix_table_unc_err_cnt),
4216[C_CCE_MSIX_TABLE_COR_ERR] = CNTR_ELEM("CceMsixTableCorErr", 0, 0,
4217 CNTR_NORMAL,
4218 access_cce_msix_table_cor_err_cnt),
4219[C_CCE_RXDMA_CONV_FIFO_PARITY_ERR] = CNTR_ELEM("CceRxdmaConvFifoParityErr", 0,
4220 0, CNTR_NORMAL,
4221 access_cce_rxdma_conv_fifo_parity_err_cnt),
4222[C_CCE_RCPL_ASYNC_FIFO_PARITY_ERR] = CNTR_ELEM("CceRcplAsyncFifoParityErr", 0,
4223 0, CNTR_NORMAL,
4224 access_cce_rcpl_async_fifo_parity_err_cnt),
4225[C_CCE_SEG_WRITE_BAD_ADDR_ERR] = CNTR_ELEM("CceSegWriteBadAddrErr", 0, 0,
4226 CNTR_NORMAL,
4227 access_cce_seg_write_bad_addr_err_cnt),
4228[C_CCE_SEG_READ_BAD_ADDR_ERR] = CNTR_ELEM("CceSegReadBadAddrErr", 0, 0,
4229 CNTR_NORMAL,
4230 access_cce_seg_read_bad_addr_err_cnt),
4231[C_LA_TRIGGERED] = CNTR_ELEM("Cce LATriggered", 0, 0,
4232 CNTR_NORMAL,
4233 access_la_triggered_cnt),
4234[C_CCE_TRGT_CPL_TIMEOUT_ERR] = CNTR_ELEM("CceTrgtCplTimeoutErr", 0, 0,
4235 CNTR_NORMAL,
4236 access_cce_trgt_cpl_timeout_err_cnt),
4237[C_PCIC_RECEIVE_PARITY_ERR] = CNTR_ELEM("PcicReceiveParityErr", 0, 0,
4238 CNTR_NORMAL,
4239 access_pcic_receive_parity_err_cnt),
4240[C_PCIC_TRANSMIT_BACK_PARITY_ERR] = CNTR_ELEM("PcicTransmitBackParityErr", 0, 0,
4241 CNTR_NORMAL,
4242 access_pcic_transmit_back_parity_err_cnt),
4243[C_PCIC_TRANSMIT_FRONT_PARITY_ERR] = CNTR_ELEM("PcicTransmitFrontParityErr", 0,
4244 0, CNTR_NORMAL,
4245 access_pcic_transmit_front_parity_err_cnt),
4246[C_PCIC_CPL_DAT_Q_UNC_ERR] = CNTR_ELEM("PcicCplDatQUncErr", 0, 0,
4247 CNTR_NORMAL,
4248 access_pcic_cpl_dat_q_unc_err_cnt),
4249[C_PCIC_CPL_HD_Q_UNC_ERR] = CNTR_ELEM("PcicCplHdQUncErr", 0, 0,
4250 CNTR_NORMAL,
4251 access_pcic_cpl_hd_q_unc_err_cnt),
4252[C_PCIC_POST_DAT_Q_UNC_ERR] = CNTR_ELEM("PcicPostDatQUncErr", 0, 0,
4253 CNTR_NORMAL,
4254 access_pcic_post_dat_q_unc_err_cnt),
4255[C_PCIC_POST_HD_Q_UNC_ERR] = CNTR_ELEM("PcicPostHdQUncErr", 0, 0,
4256 CNTR_NORMAL,
4257 access_pcic_post_hd_q_unc_err_cnt),
4258[C_PCIC_RETRY_SOT_MEM_UNC_ERR] = CNTR_ELEM("PcicRetrySotMemUncErr", 0, 0,
4259 CNTR_NORMAL,
4260 access_pcic_retry_sot_mem_unc_err_cnt),
4261[C_PCIC_RETRY_MEM_UNC_ERR] = CNTR_ELEM("PcicRetryMemUncErr", 0, 0,
4262 CNTR_NORMAL,
4263 access_pcic_retry_mem_unc_err),
4264[C_PCIC_N_POST_DAT_Q_PARITY_ERR] = CNTR_ELEM("PcicNPostDatQParityErr", 0, 0,
4265 CNTR_NORMAL,
4266 access_pcic_n_post_dat_q_parity_err_cnt),
4267[C_PCIC_N_POST_H_Q_PARITY_ERR] = CNTR_ELEM("PcicNPostHQParityErr", 0, 0,
4268 CNTR_NORMAL,
4269 access_pcic_n_post_h_q_parity_err_cnt),
4270[C_PCIC_CPL_DAT_Q_COR_ERR] = CNTR_ELEM("PcicCplDatQCorErr", 0, 0,
4271 CNTR_NORMAL,
4272 access_pcic_cpl_dat_q_cor_err_cnt),
4273[C_PCIC_CPL_HD_Q_COR_ERR] = CNTR_ELEM("PcicCplHdQCorErr", 0, 0,
4274 CNTR_NORMAL,
4275 access_pcic_cpl_hd_q_cor_err_cnt),
4276[C_PCIC_POST_DAT_Q_COR_ERR] = CNTR_ELEM("PcicPostDatQCorErr", 0, 0,
4277 CNTR_NORMAL,
4278 access_pcic_post_dat_q_cor_err_cnt),
4279[C_PCIC_POST_HD_Q_COR_ERR] = CNTR_ELEM("PcicPostHdQCorErr", 0, 0,
4280 CNTR_NORMAL,
4281 access_pcic_post_hd_q_cor_err_cnt),
4282[C_PCIC_RETRY_SOT_MEM_COR_ERR] = CNTR_ELEM("PcicRetrySotMemCorErr", 0, 0,
4283 CNTR_NORMAL,
4284 access_pcic_retry_sot_mem_cor_err_cnt),
4285[C_PCIC_RETRY_MEM_COR_ERR] = CNTR_ELEM("PcicRetryMemCorErr", 0, 0,
4286 CNTR_NORMAL,
4287 access_pcic_retry_mem_cor_err_cnt),
4288[C_CCE_CLI1_ASYNC_FIFO_DBG_PARITY_ERR] = CNTR_ELEM(
4289 "CceCli1AsyncFifoDbgParityError", 0, 0,
4290 CNTR_NORMAL,
4291 access_cce_cli1_async_fifo_dbg_parity_err_cnt),
4292[C_CCE_CLI1_ASYNC_FIFO_RXDMA_PARITY_ERR] = CNTR_ELEM(
4293 "CceCli1AsyncFifoRxdmaParityError", 0, 0,
4294 CNTR_NORMAL,
4295 access_cce_cli1_async_fifo_rxdma_parity_err_cnt
4296 ),
4297[C_CCE_CLI1_ASYNC_FIFO_SDMA_HD_PARITY_ERR] = CNTR_ELEM(
4298 "CceCli1AsyncFifoSdmaHdParityErr", 0, 0,
4299 CNTR_NORMAL,
4300 access_cce_cli1_async_fifo_sdma_hd_parity_err_cnt),
4301[C_CCE_CLI1_ASYNC_FIFO_PIO_CRDT_PARITY_ERR] = CNTR_ELEM(
4302 "CceCli1AsyncFifoPioCrdtParityErr", 0, 0,
4303 CNTR_NORMAL,
4304 access_cce_cl1_async_fifo_pio_crdt_parity_err_cnt),
4305[C_CCE_CLI2_ASYNC_FIFO_PARITY_ERR] = CNTR_ELEM("CceCli2AsyncFifoParityErr", 0,
4306 0, CNTR_NORMAL,
4307 access_cce_cli2_async_fifo_parity_err_cnt),
4308[C_CCE_CSR_CFG_BUS_PARITY_ERR] = CNTR_ELEM("CceCsrCfgBusParityErr", 0, 0,
4309 CNTR_NORMAL,
4310 access_cce_csr_cfg_bus_parity_err_cnt),
4311[C_CCE_CLI0_ASYNC_FIFO_PARTIY_ERR] = CNTR_ELEM("CceCli0AsyncFifoParityErr", 0,
4312 0, CNTR_NORMAL,
4313 access_cce_cli0_async_fifo_parity_err_cnt),
4314[C_CCE_RSPD_DATA_PARITY_ERR] = CNTR_ELEM("CceRspdDataParityErr", 0, 0,
4315 CNTR_NORMAL,
4316 access_cce_rspd_data_parity_err_cnt),
4317[C_CCE_TRGT_ACCESS_ERR] = CNTR_ELEM("CceTrgtAccessErr", 0, 0,
4318 CNTR_NORMAL,
4319 access_cce_trgt_access_err_cnt),
4320[C_CCE_TRGT_ASYNC_FIFO_PARITY_ERR] = CNTR_ELEM("CceTrgtAsyncFifoParityErr", 0,
4321 0, CNTR_NORMAL,
4322 access_cce_trgt_async_fifo_parity_err_cnt),
4323[C_CCE_CSR_WRITE_BAD_ADDR_ERR] = CNTR_ELEM("CceCsrWriteBadAddrErr", 0, 0,
4324 CNTR_NORMAL,
4325 access_cce_csr_write_bad_addr_err_cnt),
4326[C_CCE_CSR_READ_BAD_ADDR_ERR] = CNTR_ELEM("CceCsrReadBadAddrErr", 0, 0,
4327 CNTR_NORMAL,
4328 access_cce_csr_read_bad_addr_err_cnt),
4329[C_CCE_CSR_PARITY_ERR] = CNTR_ELEM("CceCsrParityErr", 0, 0,
4330 CNTR_NORMAL,
4331 access_ccs_csr_parity_err_cnt),
4332
4333/* RcvErrStatus */
4334[C_RX_CSR_PARITY_ERR] = CNTR_ELEM("RxCsrParityErr", 0, 0,
4335 CNTR_NORMAL,
4336 access_rx_csr_parity_err_cnt),
4337[C_RX_CSR_WRITE_BAD_ADDR_ERR] = CNTR_ELEM("RxCsrWriteBadAddrErr", 0, 0,
4338 CNTR_NORMAL,
4339 access_rx_csr_write_bad_addr_err_cnt),
4340[C_RX_CSR_READ_BAD_ADDR_ERR] = CNTR_ELEM("RxCsrReadBadAddrErr", 0, 0,
4341 CNTR_NORMAL,
4342 access_rx_csr_read_bad_addr_err_cnt),
4343[C_RX_DMA_CSR_UNC_ERR] = CNTR_ELEM("RxDmaCsrUncErr", 0, 0,
4344 CNTR_NORMAL,
4345 access_rx_dma_csr_unc_err_cnt),
4346[C_RX_DMA_DQ_FSM_ENCODING_ERR] = CNTR_ELEM("RxDmaDqFsmEncodingErr", 0, 0,
4347 CNTR_NORMAL,
4348 access_rx_dma_dq_fsm_encoding_err_cnt),
4349[C_RX_DMA_EQ_FSM_ENCODING_ERR] = CNTR_ELEM("RxDmaEqFsmEncodingErr", 0, 0,
4350 CNTR_NORMAL,
4351 access_rx_dma_eq_fsm_encoding_err_cnt),
4352[C_RX_DMA_CSR_PARITY_ERR] = CNTR_ELEM("RxDmaCsrParityErr", 0, 0,
4353 CNTR_NORMAL,
4354 access_rx_dma_csr_parity_err_cnt),
4355[C_RX_RBUF_DATA_COR_ERR] = CNTR_ELEM("RxRbufDataCorErr", 0, 0,
4356 CNTR_NORMAL,
4357 access_rx_rbuf_data_cor_err_cnt),
4358[C_RX_RBUF_DATA_UNC_ERR] = CNTR_ELEM("RxRbufDataUncErr", 0, 0,
4359 CNTR_NORMAL,
4360 access_rx_rbuf_data_unc_err_cnt),
4361[C_RX_DMA_DATA_FIFO_RD_COR_ERR] = CNTR_ELEM("RxDmaDataFifoRdCorErr", 0, 0,
4362 CNTR_NORMAL,
4363 access_rx_dma_data_fifo_rd_cor_err_cnt),
4364[C_RX_DMA_DATA_FIFO_RD_UNC_ERR] = CNTR_ELEM("RxDmaDataFifoRdUncErr", 0, 0,
4365 CNTR_NORMAL,
4366 access_rx_dma_data_fifo_rd_unc_err_cnt),
4367[C_RX_DMA_HDR_FIFO_RD_COR_ERR] = CNTR_ELEM("RxDmaHdrFifoRdCorErr", 0, 0,
4368 CNTR_NORMAL,
4369 access_rx_dma_hdr_fifo_rd_cor_err_cnt),
4370[C_RX_DMA_HDR_FIFO_RD_UNC_ERR] = CNTR_ELEM("RxDmaHdrFifoRdUncErr", 0, 0,
4371 CNTR_NORMAL,
4372 access_rx_dma_hdr_fifo_rd_unc_err_cnt),
4373[C_RX_RBUF_DESC_PART2_COR_ERR] = CNTR_ELEM("RxRbufDescPart2CorErr", 0, 0,
4374 CNTR_NORMAL,
4375 access_rx_rbuf_desc_part2_cor_err_cnt),
4376[C_RX_RBUF_DESC_PART2_UNC_ERR] = CNTR_ELEM("RxRbufDescPart2UncErr", 0, 0,
4377 CNTR_NORMAL,
4378 access_rx_rbuf_desc_part2_unc_err_cnt),
4379[C_RX_RBUF_DESC_PART1_COR_ERR] = CNTR_ELEM("RxRbufDescPart1CorErr", 0, 0,
4380 CNTR_NORMAL,
4381 access_rx_rbuf_desc_part1_cor_err_cnt),
4382[C_RX_RBUF_DESC_PART1_UNC_ERR] = CNTR_ELEM("RxRbufDescPart1UncErr", 0, 0,
4383 CNTR_NORMAL,
4384 access_rx_rbuf_desc_part1_unc_err_cnt),
4385[C_RX_HQ_INTR_FSM_ERR] = CNTR_ELEM("RxHqIntrFsmErr", 0, 0,
4386 CNTR_NORMAL,
4387 access_rx_hq_intr_fsm_err_cnt),
4388[C_RX_HQ_INTR_CSR_PARITY_ERR] = CNTR_ELEM("RxHqIntrCsrParityErr", 0, 0,
4389 CNTR_NORMAL,
4390 access_rx_hq_intr_csr_parity_err_cnt),
4391[C_RX_LOOKUP_CSR_PARITY_ERR] = CNTR_ELEM("RxLookupCsrParityErr", 0, 0,
4392 CNTR_NORMAL,
4393 access_rx_lookup_csr_parity_err_cnt),
4394[C_RX_LOOKUP_RCV_ARRAY_COR_ERR] = CNTR_ELEM("RxLookupRcvArrayCorErr", 0, 0,
4395 CNTR_NORMAL,
4396 access_rx_lookup_rcv_array_cor_err_cnt),
4397[C_RX_LOOKUP_RCV_ARRAY_UNC_ERR] = CNTR_ELEM("RxLookupRcvArrayUncErr", 0, 0,
4398 CNTR_NORMAL,
4399 access_rx_lookup_rcv_array_unc_err_cnt),
4400[C_RX_LOOKUP_DES_PART2_PARITY_ERR] = CNTR_ELEM("RxLookupDesPart2ParityErr", 0,
4401 0, CNTR_NORMAL,
4402 access_rx_lookup_des_part2_parity_err_cnt),
4403[C_RX_LOOKUP_DES_PART1_UNC_COR_ERR] = CNTR_ELEM("RxLookupDesPart1UncCorErr", 0,
4404 0, CNTR_NORMAL,
4405 access_rx_lookup_des_part1_unc_cor_err_cnt),
4406[C_RX_LOOKUP_DES_PART1_UNC_ERR] = CNTR_ELEM("RxLookupDesPart1UncErr", 0, 0,
4407 CNTR_NORMAL,
4408 access_rx_lookup_des_part1_unc_err_cnt),
4409[C_RX_RBUF_NEXT_FREE_BUF_COR_ERR] = CNTR_ELEM("RxRbufNextFreeBufCorErr", 0, 0,
4410 CNTR_NORMAL,
4411 access_rx_rbuf_next_free_buf_cor_err_cnt),
4412[C_RX_RBUF_NEXT_FREE_BUF_UNC_ERR] = CNTR_ELEM("RxRbufNextFreeBufUncErr", 0, 0,
4413 CNTR_NORMAL,
4414 access_rx_rbuf_next_free_buf_unc_err_cnt),
4415[C_RX_RBUF_FL_INIT_WR_ADDR_PARITY_ERR] = CNTR_ELEM(
4416 "RxRbufFlInitWrAddrParityErr", 0, 0,
4417 CNTR_NORMAL,
4418 access_rbuf_fl_init_wr_addr_parity_err_cnt),
4419[C_RX_RBUF_FL_INITDONE_PARITY_ERR] = CNTR_ELEM("RxRbufFlInitdoneParityErr", 0,
4420 0, CNTR_NORMAL,
4421 access_rx_rbuf_fl_initdone_parity_err_cnt),
4422[C_RX_RBUF_FL_WRITE_ADDR_PARITY_ERR] = CNTR_ELEM("RxRbufFlWrAddrParityErr", 0,
4423 0, CNTR_NORMAL,
4424 access_rx_rbuf_fl_write_addr_parity_err_cnt),
4425[C_RX_RBUF_FL_RD_ADDR_PARITY_ERR] = CNTR_ELEM("RxRbufFlRdAddrParityErr", 0, 0,
4426 CNTR_NORMAL,
4427 access_rx_rbuf_fl_rd_addr_parity_err_cnt),
4428[C_RX_RBUF_EMPTY_ERR] = CNTR_ELEM("RxRbufEmptyErr", 0, 0,
4429 CNTR_NORMAL,
4430 access_rx_rbuf_empty_err_cnt),
4431[C_RX_RBUF_FULL_ERR] = CNTR_ELEM("RxRbufFullErr", 0, 0,
4432 CNTR_NORMAL,
4433 access_rx_rbuf_full_err_cnt),
4434[C_RX_RBUF_BAD_LOOKUP_ERR] = CNTR_ELEM("RxRBufBadLookupErr", 0, 0,
4435 CNTR_NORMAL,
4436 access_rbuf_bad_lookup_err_cnt),
4437[C_RX_RBUF_CTX_ID_PARITY_ERR] = CNTR_ELEM("RxRbufCtxIdParityErr", 0, 0,
4438 CNTR_NORMAL,
4439 access_rbuf_ctx_id_parity_err_cnt),
4440[C_RX_RBUF_CSR_QEOPDW_PARITY_ERR] = CNTR_ELEM("RxRbufCsrQEOPDWParityErr", 0, 0,
4441 CNTR_NORMAL,
4442 access_rbuf_csr_qeopdw_parity_err_cnt),
4443[C_RX_RBUF_CSR_Q_NUM_OF_PKT_PARITY_ERR] = CNTR_ELEM(
4444 "RxRbufCsrQNumOfPktParityErr", 0, 0,
4445 CNTR_NORMAL,
4446 access_rx_rbuf_csr_q_num_of_pkt_parity_err_cnt),
4447[C_RX_RBUF_CSR_Q_T1_PTR_PARITY_ERR] = CNTR_ELEM(
4448 "RxRbufCsrQTlPtrParityErr", 0, 0,
4449 CNTR_NORMAL,
4450 access_rx_rbuf_csr_q_t1_ptr_parity_err_cnt),
4451[C_RX_RBUF_CSR_Q_HD_PTR_PARITY_ERR] = CNTR_ELEM("RxRbufCsrQHdPtrParityErr", 0,
4452 0, CNTR_NORMAL,
4453 access_rx_rbuf_csr_q_hd_ptr_parity_err_cnt),
4454[C_RX_RBUF_CSR_Q_VLD_BIT_PARITY_ERR] = CNTR_ELEM("RxRbufCsrQVldBitParityErr", 0,
4455 0, CNTR_NORMAL,
4456 access_rx_rbuf_csr_q_vld_bit_parity_err_cnt),
4457[C_RX_RBUF_CSR_Q_NEXT_BUF_PARITY_ERR] = CNTR_ELEM("RxRbufCsrQNextBufParityErr",
4458 0, 0, CNTR_NORMAL,
4459 access_rx_rbuf_csr_q_next_buf_parity_err_cnt),
4460[C_RX_RBUF_CSR_Q_ENT_CNT_PARITY_ERR] = CNTR_ELEM("RxRbufCsrQEntCntParityErr", 0,
4461 0, CNTR_NORMAL,
4462 access_rx_rbuf_csr_q_ent_cnt_parity_err_cnt),
4463[C_RX_RBUF_CSR_Q_HEAD_BUF_NUM_PARITY_ERR] = CNTR_ELEM(
4464 "RxRbufCsrQHeadBufNumParityErr", 0, 0,
4465 CNTR_NORMAL,
4466 access_rx_rbuf_csr_q_head_buf_num_parity_err_cnt),
4467[C_RX_RBUF_BLOCK_LIST_READ_COR_ERR] = CNTR_ELEM("RxRbufBlockListReadCorErr", 0,
4468 0, CNTR_NORMAL,
4469 access_rx_rbuf_block_list_read_cor_err_cnt),
4470[C_RX_RBUF_BLOCK_LIST_READ_UNC_ERR] = CNTR_ELEM("RxRbufBlockListReadUncErr", 0,
4471 0, CNTR_NORMAL,
4472 access_rx_rbuf_block_list_read_unc_err_cnt),
4473[C_RX_RBUF_LOOKUP_DES_COR_ERR] = CNTR_ELEM("RxRbufLookupDesCorErr", 0, 0,
4474 CNTR_NORMAL,
4475 access_rx_rbuf_lookup_des_cor_err_cnt),
4476[C_RX_RBUF_LOOKUP_DES_UNC_ERR] = CNTR_ELEM("RxRbufLookupDesUncErr", 0, 0,
4477 CNTR_NORMAL,
4478 access_rx_rbuf_lookup_des_unc_err_cnt),
4479[C_RX_RBUF_LOOKUP_DES_REG_UNC_COR_ERR] = CNTR_ELEM(
4480 "RxRbufLookupDesRegUncCorErr", 0, 0,
4481 CNTR_NORMAL,
4482 access_rx_rbuf_lookup_des_reg_unc_cor_err_cnt),
4483[C_RX_RBUF_LOOKUP_DES_REG_UNC_ERR] = CNTR_ELEM("RxRbufLookupDesRegUncErr", 0, 0,
4484 CNTR_NORMAL,
4485 access_rx_rbuf_lookup_des_reg_unc_err_cnt),
4486[C_RX_RBUF_FREE_LIST_COR_ERR] = CNTR_ELEM("RxRbufFreeListCorErr", 0, 0,
4487 CNTR_NORMAL,
4488 access_rx_rbuf_free_list_cor_err_cnt),
4489[C_RX_RBUF_FREE_LIST_UNC_ERR] = CNTR_ELEM("RxRbufFreeListUncErr", 0, 0,
4490 CNTR_NORMAL,
4491 access_rx_rbuf_free_list_unc_err_cnt),
4492[C_RX_RCV_FSM_ENCODING_ERR] = CNTR_ELEM("RxRcvFsmEncodingErr", 0, 0,
4493 CNTR_NORMAL,
4494 access_rx_rcv_fsm_encoding_err_cnt),
4495[C_RX_DMA_FLAG_COR_ERR] = CNTR_ELEM("RxDmaFlagCorErr", 0, 0,
4496 CNTR_NORMAL,
4497 access_rx_dma_flag_cor_err_cnt),
4498[C_RX_DMA_FLAG_UNC_ERR] = CNTR_ELEM("RxDmaFlagUncErr", 0, 0,
4499 CNTR_NORMAL,
4500 access_rx_dma_flag_unc_err_cnt),
4501[C_RX_DC_SOP_EOP_PARITY_ERR] = CNTR_ELEM("RxDcSopEopParityErr", 0, 0,
4502 CNTR_NORMAL,
4503 access_rx_dc_sop_eop_parity_err_cnt),
4504[C_RX_RCV_CSR_PARITY_ERR] = CNTR_ELEM("RxRcvCsrParityErr", 0, 0,
4505 CNTR_NORMAL,
4506 access_rx_rcv_csr_parity_err_cnt),
4507[C_RX_RCV_QP_MAP_TABLE_COR_ERR] = CNTR_ELEM("RxRcvQpMapTableCorErr", 0, 0,
4508 CNTR_NORMAL,
4509 access_rx_rcv_qp_map_table_cor_err_cnt),
4510[C_RX_RCV_QP_MAP_TABLE_UNC_ERR] = CNTR_ELEM("RxRcvQpMapTableUncErr", 0, 0,
4511 CNTR_NORMAL,
4512 access_rx_rcv_qp_map_table_unc_err_cnt),
4513[C_RX_RCV_DATA_COR_ERR] = CNTR_ELEM("RxRcvDataCorErr", 0, 0,
4514 CNTR_NORMAL,
4515 access_rx_rcv_data_cor_err_cnt),
4516[C_RX_RCV_DATA_UNC_ERR] = CNTR_ELEM("RxRcvDataUncErr", 0, 0,
4517 CNTR_NORMAL,
4518 access_rx_rcv_data_unc_err_cnt),
4519[C_RX_RCV_HDR_COR_ERR] = CNTR_ELEM("RxRcvHdrCorErr", 0, 0,
4520 CNTR_NORMAL,
4521 access_rx_rcv_hdr_cor_err_cnt),
4522[C_RX_RCV_HDR_UNC_ERR] = CNTR_ELEM("RxRcvHdrUncErr", 0, 0,
4523 CNTR_NORMAL,
4524 access_rx_rcv_hdr_unc_err_cnt),
4525[C_RX_DC_INTF_PARITY_ERR] = CNTR_ELEM("RxDcIntfParityErr", 0, 0,
4526 CNTR_NORMAL,
4527 access_rx_dc_intf_parity_err_cnt),
4528[C_RX_DMA_CSR_COR_ERR] = CNTR_ELEM("RxDmaCsrCorErr", 0, 0,
4529 CNTR_NORMAL,
4530 access_rx_dma_csr_cor_err_cnt),
4531/* SendPioErrStatus */
4532[C_PIO_PEC_SOP_HEAD_PARITY_ERR] = CNTR_ELEM("PioPecSopHeadParityErr", 0, 0,
4533 CNTR_NORMAL,
4534 access_pio_pec_sop_head_parity_err_cnt),
4535[C_PIO_PCC_SOP_HEAD_PARITY_ERR] = CNTR_ELEM("PioPccSopHeadParityErr", 0, 0,
4536 CNTR_NORMAL,
4537 access_pio_pcc_sop_head_parity_err_cnt),
4538[C_PIO_LAST_RETURNED_CNT_PARITY_ERR] = CNTR_ELEM("PioLastReturnedCntParityErr",
4539 0, 0, CNTR_NORMAL,
4540 access_pio_last_returned_cnt_parity_err_cnt),
4541[C_PIO_CURRENT_FREE_CNT_PARITY_ERR] = CNTR_ELEM("PioCurrentFreeCntParityErr", 0,
4542 0, CNTR_NORMAL,
4543 access_pio_current_free_cnt_parity_err_cnt),
4544[C_PIO_RSVD_31_ERR] = CNTR_ELEM("Pio Reserved 31", 0, 0,
4545 CNTR_NORMAL,
4546 access_pio_reserved_31_err_cnt),
4547[C_PIO_RSVD_30_ERR] = CNTR_ELEM("Pio Reserved 30", 0, 0,
4548 CNTR_NORMAL,
4549 access_pio_reserved_30_err_cnt),
4550[C_PIO_PPMC_SOP_LEN_ERR] = CNTR_ELEM("PioPpmcSopLenErr", 0, 0,
4551 CNTR_NORMAL,
4552 access_pio_ppmc_sop_len_err_cnt),
4553[C_PIO_PPMC_BQC_MEM_PARITY_ERR] = CNTR_ELEM("PioPpmcBqcMemParityErr", 0, 0,
4554 CNTR_NORMAL,
4555 access_pio_ppmc_bqc_mem_parity_err_cnt),
4556[C_PIO_VL_FIFO_PARITY_ERR] = CNTR_ELEM("PioVlFifoParityErr", 0, 0,
4557 CNTR_NORMAL,
4558 access_pio_vl_fifo_parity_err_cnt),
4559[C_PIO_VLF_SOP_PARITY_ERR] = CNTR_ELEM("PioVlfSopParityErr", 0, 0,
4560 CNTR_NORMAL,
4561 access_pio_vlf_sop_parity_err_cnt),
4562[C_PIO_VLF_V1_LEN_PARITY_ERR] = CNTR_ELEM("PioVlfVlLenParityErr", 0, 0,
4563 CNTR_NORMAL,
4564 access_pio_vlf_v1_len_parity_err_cnt),
4565[C_PIO_BLOCK_QW_COUNT_PARITY_ERR] = CNTR_ELEM("PioBlockQwCountParityErr", 0, 0,
4566 CNTR_NORMAL,
4567 access_pio_block_qw_count_parity_err_cnt),
4568[C_PIO_WRITE_QW_VALID_PARITY_ERR] = CNTR_ELEM("PioWriteQwValidParityErr", 0, 0,
4569 CNTR_NORMAL,
4570 access_pio_write_qw_valid_parity_err_cnt),
4571[C_PIO_STATE_MACHINE_ERR] = CNTR_ELEM("PioStateMachineErr", 0, 0,
4572 CNTR_NORMAL,
4573 access_pio_state_machine_err_cnt),
4574[C_PIO_WRITE_DATA_PARITY_ERR] = CNTR_ELEM("PioWriteDataParityErr", 0, 0,
4575 CNTR_NORMAL,
4576 access_pio_write_data_parity_err_cnt),
4577[C_PIO_HOST_ADDR_MEM_COR_ERR] = CNTR_ELEM("PioHostAddrMemCorErr", 0, 0,
4578 CNTR_NORMAL,
4579 access_pio_host_addr_mem_cor_err_cnt),
4580[C_PIO_HOST_ADDR_MEM_UNC_ERR] = CNTR_ELEM("PioHostAddrMemUncErr", 0, 0,
4581 CNTR_NORMAL,
4582 access_pio_host_addr_mem_unc_err_cnt),
4583[C_PIO_PKT_EVICT_SM_OR_ARM_SM_ERR] = CNTR_ELEM("PioPktEvictSmOrArbSmErr", 0, 0,
4584 CNTR_NORMAL,
4585 access_pio_pkt_evict_sm_or_arb_sm_err_cnt),
4586[C_PIO_INIT_SM_IN_ERR] = CNTR_ELEM("PioInitSmInErr", 0, 0,
4587 CNTR_NORMAL,
4588 access_pio_init_sm_in_err_cnt),
4589[C_PIO_PPMC_PBL_FIFO_ERR] = CNTR_ELEM("PioPpmcPblFifoErr", 0, 0,
4590 CNTR_NORMAL,
4591 access_pio_ppmc_pbl_fifo_err_cnt),
4592[C_PIO_CREDIT_RET_FIFO_PARITY_ERR] = CNTR_ELEM("PioCreditRetFifoParityErr", 0,
4593 0, CNTR_NORMAL,
4594 access_pio_credit_ret_fifo_parity_err_cnt),
4595[C_PIO_V1_LEN_MEM_BANK1_COR_ERR] = CNTR_ELEM("PioVlLenMemBank1CorErr", 0, 0,
4596 CNTR_NORMAL,
4597 access_pio_v1_len_mem_bank1_cor_err_cnt),
4598[C_PIO_V1_LEN_MEM_BANK0_COR_ERR] = CNTR_ELEM("PioVlLenMemBank0CorErr", 0, 0,
4599 CNTR_NORMAL,
4600 access_pio_v1_len_mem_bank0_cor_err_cnt),
4601[C_PIO_V1_LEN_MEM_BANK1_UNC_ERR] = CNTR_ELEM("PioVlLenMemBank1UncErr", 0, 0,
4602 CNTR_NORMAL,
4603 access_pio_v1_len_mem_bank1_unc_err_cnt),
4604[C_PIO_V1_LEN_MEM_BANK0_UNC_ERR] = CNTR_ELEM("PioVlLenMemBank0UncErr", 0, 0,
4605 CNTR_NORMAL,
4606 access_pio_v1_len_mem_bank0_unc_err_cnt),
4607[C_PIO_SM_PKT_RESET_PARITY_ERR] = CNTR_ELEM("PioSmPktResetParityErr", 0, 0,
4608 CNTR_NORMAL,
4609 access_pio_sm_pkt_reset_parity_err_cnt),
4610[C_PIO_PKT_EVICT_FIFO_PARITY_ERR] = CNTR_ELEM("PioPktEvictFifoParityErr", 0, 0,
4611 CNTR_NORMAL,
4612 access_pio_pkt_evict_fifo_parity_err_cnt),
4613[C_PIO_SBRDCTRL_CRREL_FIFO_PARITY_ERR] = CNTR_ELEM(
4614 "PioSbrdctrlCrrelFifoParityErr", 0, 0,
4615 CNTR_NORMAL,
4616 access_pio_sbrdctrl_crrel_fifo_parity_err_cnt),
4617[C_PIO_SBRDCTL_CRREL_PARITY_ERR] = CNTR_ELEM("PioSbrdctlCrrelParityErr", 0, 0,
4618 CNTR_NORMAL,
4619 access_pio_sbrdctl_crrel_parity_err_cnt),
4620[C_PIO_PEC_FIFO_PARITY_ERR] = CNTR_ELEM("PioPecFifoParityErr", 0, 0,
4621 CNTR_NORMAL,
4622 access_pio_pec_fifo_parity_err_cnt),
4623[C_PIO_PCC_FIFO_PARITY_ERR] = CNTR_ELEM("PioPccFifoParityErr", 0, 0,
4624 CNTR_NORMAL,
4625 access_pio_pcc_fifo_parity_err_cnt),
4626[C_PIO_SB_MEM_FIFO1_ERR] = CNTR_ELEM("PioSbMemFifo1Err", 0, 0,
4627 CNTR_NORMAL,
4628 access_pio_sb_mem_fifo1_err_cnt),
4629[C_PIO_SB_MEM_FIFO0_ERR] = CNTR_ELEM("PioSbMemFifo0Err", 0, 0,
4630 CNTR_NORMAL,
4631 access_pio_sb_mem_fifo0_err_cnt),
4632[C_PIO_CSR_PARITY_ERR] = CNTR_ELEM("PioCsrParityErr", 0, 0,
4633 CNTR_NORMAL,
4634 access_pio_csr_parity_err_cnt),
4635[C_PIO_WRITE_ADDR_PARITY_ERR] = CNTR_ELEM("PioWriteAddrParityErr", 0, 0,
4636 CNTR_NORMAL,
4637 access_pio_write_addr_parity_err_cnt),
4638[C_PIO_WRITE_BAD_CTXT_ERR] = CNTR_ELEM("PioWriteBadCtxtErr", 0, 0,
4639 CNTR_NORMAL,
4640 access_pio_write_bad_ctxt_err_cnt),
4641/* SendDmaErrStatus */
4642[C_SDMA_PCIE_REQ_TRACKING_COR_ERR] = CNTR_ELEM("SDmaPcieReqTrackingCorErr", 0,
4643 0, CNTR_NORMAL,
4644 access_sdma_pcie_req_tracking_cor_err_cnt),
4645[C_SDMA_PCIE_REQ_TRACKING_UNC_ERR] = CNTR_ELEM("SDmaPcieReqTrackingUncErr", 0,
4646 0, CNTR_NORMAL,
4647 access_sdma_pcie_req_tracking_unc_err_cnt),
4648[C_SDMA_CSR_PARITY_ERR] = CNTR_ELEM("SDmaCsrParityErr", 0, 0,
4649 CNTR_NORMAL,
4650 access_sdma_csr_parity_err_cnt),
4651[C_SDMA_RPY_TAG_ERR] = CNTR_ELEM("SDmaRpyTagErr", 0, 0,
4652 CNTR_NORMAL,
4653 access_sdma_rpy_tag_err_cnt),
4654/* SendEgressErrStatus */
4655[C_TX_READ_PIO_MEMORY_CSR_UNC_ERR] = CNTR_ELEM("TxReadPioMemoryCsrUncErr", 0, 0,
4656 CNTR_NORMAL,
4657 access_tx_read_pio_memory_csr_unc_err_cnt),
4658[C_TX_READ_SDMA_MEMORY_CSR_UNC_ERR] = CNTR_ELEM("TxReadSdmaMemoryCsrUncErr", 0,
4659 0, CNTR_NORMAL,
4660 access_tx_read_sdma_memory_csr_err_cnt),
4661[C_TX_EGRESS_FIFO_COR_ERR] = CNTR_ELEM("TxEgressFifoCorErr", 0, 0,
4662 CNTR_NORMAL,
4663 access_tx_egress_fifo_cor_err_cnt),
4664[C_TX_READ_PIO_MEMORY_COR_ERR] = CNTR_ELEM("TxReadPioMemoryCorErr", 0, 0,
4665 CNTR_NORMAL,
4666 access_tx_read_pio_memory_cor_err_cnt),
4667[C_TX_READ_SDMA_MEMORY_COR_ERR] = CNTR_ELEM("TxReadSdmaMemoryCorErr", 0, 0,
4668 CNTR_NORMAL,
4669 access_tx_read_sdma_memory_cor_err_cnt),
4670[C_TX_SB_HDR_COR_ERR] = CNTR_ELEM("TxSbHdrCorErr", 0, 0,
4671 CNTR_NORMAL,
4672 access_tx_sb_hdr_cor_err_cnt),
4673[C_TX_CREDIT_OVERRUN_ERR] = CNTR_ELEM("TxCreditOverrunErr", 0, 0,
4674 CNTR_NORMAL,
4675 access_tx_credit_overrun_err_cnt),
4676[C_TX_LAUNCH_FIFO8_COR_ERR] = CNTR_ELEM("TxLaunchFifo8CorErr", 0, 0,
4677 CNTR_NORMAL,
4678 access_tx_launch_fifo8_cor_err_cnt),
4679[C_TX_LAUNCH_FIFO7_COR_ERR] = CNTR_ELEM("TxLaunchFifo7CorErr", 0, 0,
4680 CNTR_NORMAL,
4681 access_tx_launch_fifo7_cor_err_cnt),
4682[C_TX_LAUNCH_FIFO6_COR_ERR] = CNTR_ELEM("TxLaunchFifo6CorErr", 0, 0,
4683 CNTR_NORMAL,
4684 access_tx_launch_fifo6_cor_err_cnt),
4685[C_TX_LAUNCH_FIFO5_COR_ERR] = CNTR_ELEM("TxLaunchFifo5CorErr", 0, 0,
4686 CNTR_NORMAL,
4687 access_tx_launch_fifo5_cor_err_cnt),
4688[C_TX_LAUNCH_FIFO4_COR_ERR] = CNTR_ELEM("TxLaunchFifo4CorErr", 0, 0,
4689 CNTR_NORMAL,
4690 access_tx_launch_fifo4_cor_err_cnt),
4691[C_TX_LAUNCH_FIFO3_COR_ERR] = CNTR_ELEM("TxLaunchFifo3CorErr", 0, 0,
4692 CNTR_NORMAL,
4693 access_tx_launch_fifo3_cor_err_cnt),
4694[C_TX_LAUNCH_FIFO2_COR_ERR] = CNTR_ELEM("TxLaunchFifo2CorErr", 0, 0,
4695 CNTR_NORMAL,
4696 access_tx_launch_fifo2_cor_err_cnt),
4697[C_TX_LAUNCH_FIFO1_COR_ERR] = CNTR_ELEM("TxLaunchFifo1CorErr", 0, 0,
4698 CNTR_NORMAL,
4699 access_tx_launch_fifo1_cor_err_cnt),
4700[C_TX_LAUNCH_FIFO0_COR_ERR] = CNTR_ELEM("TxLaunchFifo0CorErr", 0, 0,
4701 CNTR_NORMAL,
4702 access_tx_launch_fifo0_cor_err_cnt),
4703[C_TX_CREDIT_RETURN_VL_ERR] = CNTR_ELEM("TxCreditReturnVLErr", 0, 0,
4704 CNTR_NORMAL,
4705 access_tx_credit_return_vl_err_cnt),
4706[C_TX_HCRC_INSERTION_ERR] = CNTR_ELEM("TxHcrcInsertionErr", 0, 0,
4707 CNTR_NORMAL,
4708 access_tx_hcrc_insertion_err_cnt),
4709[C_TX_EGRESS_FIFI_UNC_ERR] = CNTR_ELEM("TxEgressFifoUncErr", 0, 0,
4710 CNTR_NORMAL,
4711 access_tx_egress_fifo_unc_err_cnt),
4712[C_TX_READ_PIO_MEMORY_UNC_ERR] = CNTR_ELEM("TxReadPioMemoryUncErr", 0, 0,
4713 CNTR_NORMAL,
4714 access_tx_read_pio_memory_unc_err_cnt),
4715[C_TX_READ_SDMA_MEMORY_UNC_ERR] = CNTR_ELEM("TxReadSdmaMemoryUncErr", 0, 0,
4716 CNTR_NORMAL,
4717 access_tx_read_sdma_memory_unc_err_cnt),
4718[C_TX_SB_HDR_UNC_ERR] = CNTR_ELEM("TxSbHdrUncErr", 0, 0,
4719 CNTR_NORMAL,
4720 access_tx_sb_hdr_unc_err_cnt),
4721[C_TX_CREDIT_RETURN_PARITY_ERR] = CNTR_ELEM("TxCreditReturnParityErr", 0, 0,
4722 CNTR_NORMAL,
4723 access_tx_credit_return_partiy_err_cnt),
4724[C_TX_LAUNCH_FIFO8_UNC_OR_PARITY_ERR] = CNTR_ELEM("TxLaunchFifo8UncOrParityErr",
4725 0, 0, CNTR_NORMAL,
4726 access_tx_launch_fifo8_unc_or_parity_err_cnt),
4727[C_TX_LAUNCH_FIFO7_UNC_OR_PARITY_ERR] = CNTR_ELEM("TxLaunchFifo7UncOrParityErr",
4728 0, 0, CNTR_NORMAL,
4729 access_tx_launch_fifo7_unc_or_parity_err_cnt),
4730[C_TX_LAUNCH_FIFO6_UNC_OR_PARITY_ERR] = CNTR_ELEM("TxLaunchFifo6UncOrParityErr",
4731 0, 0, CNTR_NORMAL,
4732 access_tx_launch_fifo6_unc_or_parity_err_cnt),
4733[C_TX_LAUNCH_FIFO5_UNC_OR_PARITY_ERR] = CNTR_ELEM("TxLaunchFifo5UncOrParityErr",
4734 0, 0, CNTR_NORMAL,
4735 access_tx_launch_fifo5_unc_or_parity_err_cnt),
4736[C_TX_LAUNCH_FIFO4_UNC_OR_PARITY_ERR] = CNTR_ELEM("TxLaunchFifo4UncOrParityErr",
4737 0, 0, CNTR_NORMAL,
4738 access_tx_launch_fifo4_unc_or_parity_err_cnt),
4739[C_TX_LAUNCH_FIFO3_UNC_OR_PARITY_ERR] = CNTR_ELEM("TxLaunchFifo3UncOrParityErr",
4740 0, 0, CNTR_NORMAL,
4741 access_tx_launch_fifo3_unc_or_parity_err_cnt),
4742[C_TX_LAUNCH_FIFO2_UNC_OR_PARITY_ERR] = CNTR_ELEM("TxLaunchFifo2UncOrParityErr",
4743 0, 0, CNTR_NORMAL,
4744 access_tx_launch_fifo2_unc_or_parity_err_cnt),
4745[C_TX_LAUNCH_FIFO1_UNC_OR_PARITY_ERR] = CNTR_ELEM("TxLaunchFifo1UncOrParityErr",
4746 0, 0, CNTR_NORMAL,
4747 access_tx_launch_fifo1_unc_or_parity_err_cnt),
4748[C_TX_LAUNCH_FIFO0_UNC_OR_PARITY_ERR] = CNTR_ELEM("TxLaunchFifo0UncOrParityErr",
4749 0, 0, CNTR_NORMAL,
4750 access_tx_launch_fifo0_unc_or_parity_err_cnt),
4751[C_TX_SDMA15_DISALLOWED_PACKET_ERR] = CNTR_ELEM("TxSdma15DisallowedPacketErr",
4752 0, 0, CNTR_NORMAL,
4753 access_tx_sdma15_disallowed_packet_err_cnt),
4754[C_TX_SDMA14_DISALLOWED_PACKET_ERR] = CNTR_ELEM("TxSdma14DisallowedPacketErr",
4755 0, 0, CNTR_NORMAL,
4756 access_tx_sdma14_disallowed_packet_err_cnt),
4757[C_TX_SDMA13_DISALLOWED_PACKET_ERR] = CNTR_ELEM("TxSdma13DisallowedPacketErr",
4758 0, 0, CNTR_NORMAL,
4759 access_tx_sdma13_disallowed_packet_err_cnt),
4760[C_TX_SDMA12_DISALLOWED_PACKET_ERR] = CNTR_ELEM("TxSdma12DisallowedPacketErr",
4761 0, 0, CNTR_NORMAL,
4762 access_tx_sdma12_disallowed_packet_err_cnt),
4763[C_TX_SDMA11_DISALLOWED_PACKET_ERR] = CNTR_ELEM("TxSdma11DisallowedPacketErr",
4764 0, 0, CNTR_NORMAL,
4765 access_tx_sdma11_disallowed_packet_err_cnt),
4766[C_TX_SDMA10_DISALLOWED_PACKET_ERR] = CNTR_ELEM("TxSdma10DisallowedPacketErr",
4767 0, 0, CNTR_NORMAL,
4768 access_tx_sdma10_disallowed_packet_err_cnt),
4769[C_TX_SDMA9_DISALLOWED_PACKET_ERR] = CNTR_ELEM("TxSdma9DisallowedPacketErr",
4770 0, 0, CNTR_NORMAL,
4771 access_tx_sdma9_disallowed_packet_err_cnt),
4772[C_TX_SDMA8_DISALLOWED_PACKET_ERR] = CNTR_ELEM("TxSdma8DisallowedPacketErr",
4773 0, 0, CNTR_NORMAL,
4774 access_tx_sdma8_disallowed_packet_err_cnt),
4775[C_TX_SDMA7_DISALLOWED_PACKET_ERR] = CNTR_ELEM("TxSdma7DisallowedPacketErr",
4776 0, 0, CNTR_NORMAL,
4777 access_tx_sdma7_disallowed_packet_err_cnt),
4778[C_TX_SDMA6_DISALLOWED_PACKET_ERR] = CNTR_ELEM("TxSdma6DisallowedPacketErr",
4779 0, 0, CNTR_NORMAL,
4780 access_tx_sdma6_disallowed_packet_err_cnt),
4781[C_TX_SDMA5_DISALLOWED_PACKET_ERR] = CNTR_ELEM("TxSdma5DisallowedPacketErr",
4782 0, 0, CNTR_NORMAL,
4783 access_tx_sdma5_disallowed_packet_err_cnt),
4784[C_TX_SDMA4_DISALLOWED_PACKET_ERR] = CNTR_ELEM("TxSdma4DisallowedPacketErr",
4785 0, 0, CNTR_NORMAL,
4786 access_tx_sdma4_disallowed_packet_err_cnt),
4787[C_TX_SDMA3_DISALLOWED_PACKET_ERR] = CNTR_ELEM("TxSdma3DisallowedPacketErr",
4788 0, 0, CNTR_NORMAL,
4789 access_tx_sdma3_disallowed_packet_err_cnt),
4790[C_TX_SDMA2_DISALLOWED_PACKET_ERR] = CNTR_ELEM("TxSdma2DisallowedPacketErr",
4791 0, 0, CNTR_NORMAL,
4792 access_tx_sdma2_disallowed_packet_err_cnt),
4793[C_TX_SDMA1_DISALLOWED_PACKET_ERR] = CNTR_ELEM("TxSdma1DisallowedPacketErr",
4794 0, 0, CNTR_NORMAL,
4795 access_tx_sdma1_disallowed_packet_err_cnt),
4796[C_TX_SDMA0_DISALLOWED_PACKET_ERR] = CNTR_ELEM("TxSdma0DisallowedPacketErr",
4797 0, 0, CNTR_NORMAL,
4798 access_tx_sdma0_disallowed_packet_err_cnt),
4799[C_TX_CONFIG_PARITY_ERR] = CNTR_ELEM("TxConfigParityErr", 0, 0,
4800 CNTR_NORMAL,
4801 access_tx_config_parity_err_cnt),
4802[C_TX_SBRD_CTL_CSR_PARITY_ERR] = CNTR_ELEM("TxSbrdCtlCsrParityErr", 0, 0,
4803 CNTR_NORMAL,
4804 access_tx_sbrd_ctl_csr_parity_err_cnt),
4805[C_TX_LAUNCH_CSR_PARITY_ERR] = CNTR_ELEM("TxLaunchCsrParityErr", 0, 0,
4806 CNTR_NORMAL,
4807 access_tx_launch_csr_parity_err_cnt),
4808[C_TX_ILLEGAL_CL_ERR] = CNTR_ELEM("TxIllegalVLErr", 0, 0,
4809 CNTR_NORMAL,
4810 access_tx_illegal_vl_err_cnt),
4811[C_TX_SBRD_CTL_STATE_MACHINE_PARITY_ERR] = CNTR_ELEM(
4812 "TxSbrdCtlStateMachineParityErr", 0, 0,
4813 CNTR_NORMAL,
4814 access_tx_sbrd_ctl_state_machine_parity_err_cnt),
4815[C_TX_RESERVED_10] = CNTR_ELEM("Tx Egress Reserved 10", 0, 0,
4816 CNTR_NORMAL,
4817 access_egress_reserved_10_err_cnt),
4818[C_TX_RESERVED_9] = CNTR_ELEM("Tx Egress Reserved 9", 0, 0,
4819 CNTR_NORMAL,
4820 access_egress_reserved_9_err_cnt),
4821[C_TX_SDMA_LAUNCH_INTF_PARITY_ERR] = CNTR_ELEM("TxSdmaLaunchIntfParityErr",
4822 0, 0, CNTR_NORMAL,
4823 access_tx_sdma_launch_intf_parity_err_cnt),
4824[C_TX_PIO_LAUNCH_INTF_PARITY_ERR] = CNTR_ELEM("TxPioLaunchIntfParityErr", 0, 0,
4825 CNTR_NORMAL,
4826 access_tx_pio_launch_intf_parity_err_cnt),
4827[C_TX_RESERVED_6] = CNTR_ELEM("Tx Egress Reserved 6", 0, 0,
4828 CNTR_NORMAL,
4829 access_egress_reserved_6_err_cnt),
4830[C_TX_INCORRECT_LINK_STATE_ERR] = CNTR_ELEM("TxIncorrectLinkStateErr", 0, 0,
4831 CNTR_NORMAL,
4832 access_tx_incorrect_link_state_err_cnt),
4833[C_TX_LINK_DOWN_ERR] = CNTR_ELEM("TxLinkdownErr", 0, 0,
4834 CNTR_NORMAL,
4835 access_tx_linkdown_err_cnt),
4836[C_TX_EGRESS_FIFO_UNDERRUN_OR_PARITY_ERR] = CNTR_ELEM(
4837 "EgressFifoUnderrunOrParityErr", 0, 0,
4838 CNTR_NORMAL,
4839 access_tx_egress_fifi_underrun_or_parity_err_cnt),
4840[C_TX_RESERVED_2] = CNTR_ELEM("Tx Egress Reserved 2", 0, 0,
4841 CNTR_NORMAL,
4842 access_egress_reserved_2_err_cnt),
4843[C_TX_PKT_INTEGRITY_MEM_UNC_ERR] = CNTR_ELEM("TxPktIntegrityMemUncErr", 0, 0,
4844 CNTR_NORMAL,
4845 access_tx_pkt_integrity_mem_unc_err_cnt),
4846[C_TX_PKT_INTEGRITY_MEM_COR_ERR] = CNTR_ELEM("TxPktIntegrityMemCorErr", 0, 0,
4847 CNTR_NORMAL,
4848 access_tx_pkt_integrity_mem_cor_err_cnt),
4849/* SendErrStatus */
4850[C_SEND_CSR_WRITE_BAD_ADDR_ERR] = CNTR_ELEM("SendCsrWriteBadAddrErr", 0, 0,
4851 CNTR_NORMAL,
4852 access_send_csr_write_bad_addr_err_cnt),
4853[C_SEND_CSR_READ_BAD_ADD_ERR] = CNTR_ELEM("SendCsrReadBadAddrErr", 0, 0,
4854 CNTR_NORMAL,
4855 access_send_csr_read_bad_addr_err_cnt),
4856[C_SEND_CSR_PARITY_ERR] = CNTR_ELEM("SendCsrParityErr", 0, 0,
4857 CNTR_NORMAL,
4858 access_send_csr_parity_cnt),
4859/* SendCtxtErrStatus */
4860[C_PIO_WRITE_OUT_OF_BOUNDS_ERR] = CNTR_ELEM("PioWriteOutOfBoundsErr", 0, 0,
4861 CNTR_NORMAL,
4862 access_pio_write_out_of_bounds_err_cnt),
4863[C_PIO_WRITE_OVERFLOW_ERR] = CNTR_ELEM("PioWriteOverflowErr", 0, 0,
4864 CNTR_NORMAL,
4865 access_pio_write_overflow_err_cnt),
4866[C_PIO_WRITE_CROSSES_BOUNDARY_ERR] = CNTR_ELEM("PioWriteCrossesBoundaryErr",
4867 0, 0, CNTR_NORMAL,
4868 access_pio_write_crosses_boundary_err_cnt),
4869[C_PIO_DISALLOWED_PACKET_ERR] = CNTR_ELEM("PioDisallowedPacketErr", 0, 0,
4870 CNTR_NORMAL,
4871 access_pio_disallowed_packet_err_cnt),
4872[C_PIO_INCONSISTENT_SOP_ERR] = CNTR_ELEM("PioInconsistentSopErr", 0, 0,
4873 CNTR_NORMAL,
4874 access_pio_inconsistent_sop_err_cnt),
4875/* SendDmaEngErrStatus */
4876[C_SDMA_HEADER_REQUEST_FIFO_COR_ERR] = CNTR_ELEM("SDmaHeaderRequestFifoCorErr",
4877 0, 0, CNTR_NORMAL,
4878 access_sdma_header_request_fifo_cor_err_cnt),
4879[C_SDMA_HEADER_STORAGE_COR_ERR] = CNTR_ELEM("SDmaHeaderStorageCorErr", 0, 0,
4880 CNTR_NORMAL,
4881 access_sdma_header_storage_cor_err_cnt),
4882[C_SDMA_PACKET_TRACKING_COR_ERR] = CNTR_ELEM("SDmaPacketTrackingCorErr", 0, 0,
4883 CNTR_NORMAL,
4884 access_sdma_packet_tracking_cor_err_cnt),
4885[C_SDMA_ASSEMBLY_COR_ERR] = CNTR_ELEM("SDmaAssemblyCorErr", 0, 0,
4886 CNTR_NORMAL,
4887 access_sdma_assembly_cor_err_cnt),
4888[C_SDMA_DESC_TABLE_COR_ERR] = CNTR_ELEM("SDmaDescTableCorErr", 0, 0,
4889 CNTR_NORMAL,
4890 access_sdma_desc_table_cor_err_cnt),
4891[C_SDMA_HEADER_REQUEST_FIFO_UNC_ERR] = CNTR_ELEM("SDmaHeaderRequestFifoUncErr",
4892 0, 0, CNTR_NORMAL,
4893 access_sdma_header_request_fifo_unc_err_cnt),
4894[C_SDMA_HEADER_STORAGE_UNC_ERR] = CNTR_ELEM("SDmaHeaderStorageUncErr", 0, 0,
4895 CNTR_NORMAL,
4896 access_sdma_header_storage_unc_err_cnt),
4897[C_SDMA_PACKET_TRACKING_UNC_ERR] = CNTR_ELEM("SDmaPacketTrackingUncErr", 0, 0,
4898 CNTR_NORMAL,
4899 access_sdma_packet_tracking_unc_err_cnt),
4900[C_SDMA_ASSEMBLY_UNC_ERR] = CNTR_ELEM("SDmaAssemblyUncErr", 0, 0,
4901 CNTR_NORMAL,
4902 access_sdma_assembly_unc_err_cnt),
4903[C_SDMA_DESC_TABLE_UNC_ERR] = CNTR_ELEM("SDmaDescTableUncErr", 0, 0,
4904 CNTR_NORMAL,
4905 access_sdma_desc_table_unc_err_cnt),
4906[C_SDMA_TIMEOUT_ERR] = CNTR_ELEM("SDmaTimeoutErr", 0, 0,
4907 CNTR_NORMAL,
4908 access_sdma_timeout_err_cnt),
4909[C_SDMA_HEADER_LENGTH_ERR] = CNTR_ELEM("SDmaHeaderLengthErr", 0, 0,
4910 CNTR_NORMAL,
4911 access_sdma_header_length_err_cnt),
4912[C_SDMA_HEADER_ADDRESS_ERR] = CNTR_ELEM("SDmaHeaderAddressErr", 0, 0,
4913 CNTR_NORMAL,
4914 access_sdma_header_address_err_cnt),
4915[C_SDMA_HEADER_SELECT_ERR] = CNTR_ELEM("SDmaHeaderSelectErr", 0, 0,
4916 CNTR_NORMAL,
4917 access_sdma_header_select_err_cnt),
4918[C_SMDA_RESERVED_9] = CNTR_ELEM("SDma Reserved 9", 0, 0,
4919 CNTR_NORMAL,
4920 access_sdma_reserved_9_err_cnt),
4921[C_SDMA_PACKET_DESC_OVERFLOW_ERR] = CNTR_ELEM("SDmaPacketDescOverflowErr", 0, 0,
4922 CNTR_NORMAL,
4923 access_sdma_packet_desc_overflow_err_cnt),
4924[C_SDMA_LENGTH_MISMATCH_ERR] = CNTR_ELEM("SDmaLengthMismatchErr", 0, 0,
4925 CNTR_NORMAL,
4926 access_sdma_length_mismatch_err_cnt),
4927[C_SDMA_HALT_ERR] = CNTR_ELEM("SDmaHaltErr", 0, 0,
4928 CNTR_NORMAL,
4929 access_sdma_halt_err_cnt),
4930[C_SDMA_MEM_READ_ERR] = CNTR_ELEM("SDmaMemReadErr", 0, 0,
4931 CNTR_NORMAL,
4932 access_sdma_mem_read_err_cnt),
4933[C_SDMA_FIRST_DESC_ERR] = CNTR_ELEM("SDmaFirstDescErr", 0, 0,
4934 CNTR_NORMAL,
4935 access_sdma_first_desc_err_cnt),
4936[C_SDMA_TAIL_OUT_OF_BOUNDS_ERR] = CNTR_ELEM("SDmaTailOutOfBoundsErr", 0, 0,
4937 CNTR_NORMAL,
4938 access_sdma_tail_out_of_bounds_err_cnt),
4939[C_SDMA_TOO_LONG_ERR] = CNTR_ELEM("SDmaTooLongErr", 0, 0,
4940 CNTR_NORMAL,
4941 access_sdma_too_long_err_cnt),
4942[C_SDMA_GEN_MISMATCH_ERR] = CNTR_ELEM("SDmaGenMismatchErr", 0, 0,
4943 CNTR_NORMAL,
4944 access_sdma_gen_mismatch_err_cnt),
4945[C_SDMA_WRONG_DW_ERR] = CNTR_ELEM("SDmaWrongDwErr", 0, 0,
4946 CNTR_NORMAL,
4947 access_sdma_wrong_dw_err_cnt),
77241056
MM		 4948};
4949
4950static struct cntr_entry port_cntrs[PORT_CNTR_LAST] = {
4951[C_TX_UNSUP_VL] = TXE32_PORT_CNTR_ELEM(TxUnVLErr, SEND_UNSUP_VL_ERR_CNT,
4952 CNTR_NORMAL),
4953[C_TX_INVAL_LEN] = TXE32_PORT_CNTR_ELEM(TxInvalLen, SEND_LEN_ERR_CNT,
4954 CNTR_NORMAL),
4955[C_TX_MM_LEN_ERR] = TXE32_PORT_CNTR_ELEM(TxMMLenErr, SEND_MAX_MIN_LEN_ERR_CNT,
4956 CNTR_NORMAL),
4957[C_TX_UNDERRUN] = TXE32_PORT_CNTR_ELEM(TxUnderrun, SEND_UNDERRUN_CNT,
4958 CNTR_NORMAL),
4959[C_TX_FLOW_STALL] = TXE32_PORT_CNTR_ELEM(TxFlowStall, SEND_FLOW_STALL_CNT,
4960 CNTR_NORMAL),
4961[C_TX_DROPPED] = TXE32_PORT_CNTR_ELEM(TxDropped, SEND_DROPPED_PKT_CNT,
4962 CNTR_NORMAL),
4963[C_TX_HDR_ERR] = TXE32_PORT_CNTR_ELEM(TxHdrErr, SEND_HEADERS_ERR_CNT,
4964 CNTR_NORMAL),
4965[C_TX_PKT] = TXE64_PORT_CNTR_ELEM(TxPkt, SEND_DATA_PKT_CNT, CNTR_NORMAL),
4966[C_TX_WORDS] = TXE64_PORT_CNTR_ELEM(TxWords, SEND_DWORD_CNT, CNTR_NORMAL),
4967[C_TX_WAIT] = TXE64_PORT_CNTR_ELEM(TxWait, SEND_WAIT_CNT, CNTR_SYNTH),
4968[C_TX_FLIT_VL] = TXE64_PORT_CNTR_ELEM(TxFlitVL, SEND_DATA_VL0_CNT,
4969 CNTR_SYNTH | CNTR_VL),
4970[C_TX_PKT_VL] = TXE64_PORT_CNTR_ELEM(TxPktVL, SEND_DATA_PKT_VL0_CNT,
4971 CNTR_SYNTH | CNTR_VL),
4972[C_TX_WAIT_VL] = TXE64_PORT_CNTR_ELEM(TxWaitVL, SEND_WAIT_VL0_CNT,
4973 CNTR_SYNTH | CNTR_VL),
4974[C_RX_PKT] = RXE64_PORT_CNTR_ELEM(RxPkt, RCV_DATA_PKT_CNT, CNTR_NORMAL),
4975[C_RX_WORDS] = RXE64_PORT_CNTR_ELEM(RxWords, RCV_DWORD_CNT, CNTR_NORMAL),
4976[C_SW_LINK_DOWN] = CNTR_ELEM("SwLinkDown", 0, 0, CNTR_SYNTH | CNTR_32BIT,
4977 access_sw_link_dn_cnt),
4978[C_SW_LINK_UP] = CNTR_ELEM("SwLinkUp", 0, 0, CNTR_SYNTH | CNTR_32BIT,
4979 access_sw_link_up_cnt),
6d014530
DL		 4980[C_SW_UNKNOWN_FRAME] = CNTR_ELEM("UnknownFrame", 0, 0, CNTR_NORMAL,
4981 access_sw_unknown_frame_cnt),
77241056
MM		 4982[C_SW_XMIT_DSCD] = CNTR_ELEM("XmitDscd", 0, 0, CNTR_SYNTH | CNTR_32BIT,
4983 access_sw_xmit_discards),
4984[C_SW_XMIT_DSCD_VL] = CNTR_ELEM("XmitDscdVl", 0, 0,
4985 CNTR_SYNTH | CNTR_32BIT | CNTR_VL,
4986 access_sw_xmit_discards),
4987[C_SW_XMIT_CSTR_ERR] = CNTR_ELEM("XmitCstrErr", 0, 0, CNTR_SYNTH,
4988 access_xmit_constraint_errs),
4989[C_SW_RCV_CSTR_ERR] = CNTR_ELEM("RcvCstrErr", 0, 0, CNTR_SYNTH,
4990 access_rcv_constraint_errs),
4991[C_SW_IBP_LOOP_PKTS] = SW_IBP_CNTR(LoopPkts, loop_pkts),
4992[C_SW_IBP_RC_RESENDS] = SW_IBP_CNTR(RcResend, rc_resends),
4993[C_SW_IBP_RNR_NAKS] = SW_IBP_CNTR(RnrNak, rnr_naks),
4994[C_SW_IBP_OTHER_NAKS] = SW_IBP_CNTR(OtherNak, other_naks),
4995[C_SW_IBP_RC_TIMEOUTS] = SW_IBP_CNTR(RcTimeOut, rc_timeouts),
4996[C_SW_IBP_PKT_DROPS] = SW_IBP_CNTR(PktDrop, pkt_drops),
4997[C_SW_IBP_DMA_WAIT] = SW_IBP_CNTR(DmaWait, dmawait),
4998[C_SW_IBP_RC_SEQNAK] = SW_IBP_CNTR(RcSeqNak, rc_seqnak),
4999[C_SW_IBP_RC_DUPREQ] = SW_IBP_CNTR(RcDupRew, rc_dupreq),
5000[C_SW_IBP_RDMA_SEQ] = SW_IBP_CNTR(RdmaSeq, rdma_seq),
5001[C_SW_IBP_UNALIGNED] = SW_IBP_CNTR(Unaligned, unaligned),
5002[C_SW_IBP_SEQ_NAK] = SW_IBP_CNTR(SeqNak, seq_naks),
5003[C_SW_CPU_RC_ACKS] = CNTR_ELEM("RcAcks", 0, 0, CNTR_NORMAL,
5004 access_sw_cpu_rc_acks),
5005[C_SW_CPU_RC_QACKS] = CNTR_ELEM("RcQacks", 0, 0, CNTR_NORMAL,
5006 access_sw_cpu_rc_qacks),
5007[C_SW_CPU_RC_DELAYED_COMP] = CNTR_ELEM("RcDelayComp", 0, 0, CNTR_NORMAL,
5008 access_sw_cpu_rc_delayed_comp),
5009[OVR_LBL(0)] = OVR_ELM(0), [OVR_LBL(1)] = OVR_ELM(1),
5010[OVR_LBL(2)] = OVR_ELM(2), [OVR_LBL(3)] = OVR_ELM(3),
5011[OVR_LBL(4)] = OVR_ELM(4), [OVR_LBL(5)] = OVR_ELM(5),
5012[OVR_LBL(6)] = OVR_ELM(6), [OVR_LBL(7)] = OVR_ELM(7),
5013[OVR_LBL(8)] = OVR_ELM(8), [OVR_LBL(9)] = OVR_ELM(9),
5014[OVR_LBL(10)] = OVR_ELM(10), [OVR_LBL(11)] = OVR_ELM(11),
5015[OVR_LBL(12)] = OVR_ELM(12), [OVR_LBL(13)] = OVR_ELM(13),
5016[OVR_LBL(14)] = OVR_ELM(14), [OVR_LBL(15)] = OVR_ELM(15),
5017[OVR_LBL(16)] = OVR_ELM(16), [OVR_LBL(17)] = OVR_ELM(17),
5018[OVR_LBL(18)] = OVR_ELM(18), [OVR_LBL(19)] = OVR_ELM(19),
5019[OVR_LBL(20)] = OVR_ELM(20), [OVR_LBL(21)] = OVR_ELM(21),
5020[OVR_LBL(22)] = OVR_ELM(22), [OVR_LBL(23)] = OVR_ELM(23),
5021[OVR_LBL(24)] = OVR_ELM(24), [OVR_LBL(25)] = OVR_ELM(25),
5022[OVR_LBL(26)] = OVR_ELM(26), [OVR_LBL(27)] = OVR_ELM(27),
5023[OVR_LBL(28)] = OVR_ELM(28), [OVR_LBL(29)] = OVR_ELM(29),
5024[OVR_LBL(30)] = OVR_ELM(30), [OVR_LBL(31)] = OVR_ELM(31),
5025[OVR_LBL(32)] = OVR_ELM(32), [OVR_LBL(33)] = OVR_ELM(33),
5026[OVR_LBL(34)] = OVR_ELM(34), [OVR_LBL(35)] = OVR_ELM(35),
5027[OVR_LBL(36)] = OVR_ELM(36), [OVR_LBL(37)] = OVR_ELM(37),
5028[OVR_LBL(38)] = OVR_ELM(38), [OVR_LBL(39)] = OVR_ELM(39),
5029[OVR_LBL(40)] = OVR_ELM(40), [OVR_LBL(41)] = OVR_ELM(41),
5030[OVR_LBL(42)] = OVR_ELM(42), [OVR_LBL(43)] = OVR_ELM(43),
5031[OVR_LBL(44)] = OVR_ELM(44), [OVR_LBL(45)] = OVR_ELM(45),
5032[OVR_LBL(46)] = OVR_ELM(46), [OVR_LBL(47)] = OVR_ELM(47),
5033[OVR_LBL(48)] = OVR_ELM(48), [OVR_LBL(49)] = OVR_ELM(49),
5034[OVR_LBL(50)] = OVR_ELM(50), [OVR_LBL(51)] = OVR_ELM(51),
5035[OVR_LBL(52)] = OVR_ELM(52), [OVR_LBL(53)] = OVR_ELM(53),
5036[OVR_LBL(54)] = OVR_ELM(54), [OVR_LBL(55)] = OVR_ELM(55),
5037[OVR_LBL(56)] = OVR_ELM(56), [OVR_LBL(57)] = OVR_ELM(57),
5038[OVR_LBL(58)] = OVR_ELM(58), [OVR_LBL(59)] = OVR_ELM(59),
5039[OVR_LBL(60)] = OVR_ELM(60), [OVR_LBL(61)] = OVR_ELM(61),
5040[OVR_LBL(62)] = OVR_ELM(62), [OVR_LBL(63)] = OVR_ELM(63),
5041[OVR_LBL(64)] = OVR_ELM(64), [OVR_LBL(65)] = OVR_ELM(65),
5042[OVR_LBL(66)] = OVR_ELM(66), [OVR_LBL(67)] = OVR_ELM(67),
5043[OVR_LBL(68)] = OVR_ELM(68), [OVR_LBL(69)] = OVR_ELM(69),
5044[OVR_LBL(70)] = OVR_ELM(70), [OVR_LBL(71)] = OVR_ELM(71),
5045[OVR_LBL(72)] = OVR_ELM(72), [OVR_LBL(73)] = OVR_ELM(73),
5046[OVR_LBL(74)] = OVR_ELM(74), [OVR_LBL(75)] = OVR_ELM(75),
5047[OVR_LBL(76)] = OVR_ELM(76), [OVR_LBL(77)] = OVR_ELM(77),
5048[OVR_LBL(78)] = OVR_ELM(78), [OVR_LBL(79)] = OVR_ELM(79),
5049[OVR_LBL(80)] = OVR_ELM(80), [OVR_LBL(81)] = OVR_ELM(81),
5050[OVR_LBL(82)] = OVR_ELM(82), [OVR_LBL(83)] = OVR_ELM(83),
5051[OVR_LBL(84)] = OVR_ELM(84), [OVR_LBL(85)] = OVR_ELM(85),
5052[OVR_LBL(86)] = OVR_ELM(86), [OVR_LBL(87)] = OVR_ELM(87),
5053[OVR_LBL(88)] = OVR_ELM(88), [OVR_LBL(89)] = OVR_ELM(89),
5054[OVR_LBL(90)] = OVR_ELM(90), [OVR_LBL(91)] = OVR_ELM(91),
5055[OVR_LBL(92)] = OVR_ELM(92), [OVR_LBL(93)] = OVR_ELM(93),
5056[OVR_LBL(94)] = OVR_ELM(94), [OVR_LBL(95)] = OVR_ELM(95),
5057[OVR_LBL(96)] = OVR_ELM(96), [OVR_LBL(97)] = OVR_ELM(97),
5058[OVR_LBL(98)] = OVR_ELM(98), [OVR_LBL(99)] = OVR_ELM(99),
5059[OVR_LBL(100)] = OVR_ELM(100), [OVR_LBL(101)] = OVR_ELM(101),
5060[OVR_LBL(102)] = OVR_ELM(102), [OVR_LBL(103)] = OVR_ELM(103),
5061[OVR_LBL(104)] = OVR_ELM(104), [OVR_LBL(105)] = OVR_ELM(105),
5062[OVR_LBL(106)] = OVR_ELM(106), [OVR_LBL(107)] = OVR_ELM(107),
5063[OVR_LBL(108)] = OVR_ELM(108), [OVR_LBL(109)] = OVR_ELM(109),
5064[OVR_LBL(110)] = OVR_ELM(110), [OVR_LBL(111)] = OVR_ELM(111),
5065[OVR_LBL(112)] = OVR_ELM(112), [OVR_LBL(113)] = OVR_ELM(113),
5066[OVR_LBL(114)] = OVR_ELM(114), [OVR_LBL(115)] = OVR_ELM(115),
5067[OVR_LBL(116)] = OVR_ELM(116), [OVR_LBL(117)] = OVR_ELM(117),
5068[OVR_LBL(118)] = OVR_ELM(118), [OVR_LBL(119)] = OVR_ELM(119),
5069[OVR_LBL(120)] = OVR_ELM(120), [OVR_LBL(121)] = OVR_ELM(121),
5070[OVR_LBL(122)] = OVR_ELM(122), [OVR_LBL(123)] = OVR_ELM(123),
5071[OVR_LBL(124)] = OVR_ELM(124), [OVR_LBL(125)] = OVR_ELM(125),
5072[OVR_LBL(126)] = OVR_ELM(126), [OVR_LBL(127)] = OVR_ELM(127),
5073[OVR_LBL(128)] = OVR_ELM(128), [OVR_LBL(129)] = OVR_ELM(129),
5074[OVR_LBL(130)] = OVR_ELM(130), [OVR_LBL(131)] = OVR_ELM(131),
5075[OVR_LBL(132)] = OVR_ELM(132), [OVR_LBL(133)] = OVR_ELM(133),
5076[OVR_LBL(134)] = OVR_ELM(134), [OVR_LBL(135)] = OVR_ELM(135),
5077[OVR_LBL(136)] = OVR_ELM(136), [OVR_LBL(137)] = OVR_ELM(137),
5078[OVR_LBL(138)] = OVR_ELM(138), [OVR_LBL(139)] = OVR_ELM(139),
5079[OVR_LBL(140)] = OVR_ELM(140), [OVR_LBL(141)] = OVR_ELM(141),
5080[OVR_LBL(142)] = OVR_ELM(142), [OVR_LBL(143)] = OVR_ELM(143),
5081[OVR_LBL(144)] = OVR_ELM(144), [OVR_LBL(145)] = OVR_ELM(145),
5082[OVR_LBL(146)] = OVR_ELM(146), [OVR_LBL(147)] = OVR_ELM(147),
5083[OVR_LBL(148)] = OVR_ELM(148), [OVR_LBL(149)] = OVR_ELM(149),
5084[OVR_LBL(150)] = OVR_ELM(150), [OVR_LBL(151)] = OVR_ELM(151),
5085[OVR_LBL(152)] = OVR_ELM(152), [OVR_LBL(153)] = OVR_ELM(153),
5086[OVR_LBL(154)] = OVR_ELM(154), [OVR_LBL(155)] = OVR_ELM(155),
5087[OVR_LBL(156)] = OVR_ELM(156), [OVR_LBL(157)] = OVR_ELM(157),
5088[OVR_LBL(158)] = OVR_ELM(158), [OVR_LBL(159)] = OVR_ELM(159),
5089};
5090
5091/* ======================================================================== */
5092
77241056
MM		 5093/* return true if this is chip revision revision a */
5094int is_ax(struct hfi1_devdata *dd)
5095{
5096 u8 chip_rev_minor =
5097 dd->revision >> CCE_REVISION_CHIP_REV_MINOR_SHIFT
5098 & CCE_REVISION_CHIP_REV_MINOR_MASK;
5099 return (chip_rev_minor & 0xf0) == 0;
5100}
5101
5102/* return true if this is chip revision revision b */
5103int is_bx(struct hfi1_devdata *dd)
5104{
5105 u8 chip_rev_minor =
5106 dd->revision >> CCE_REVISION_CHIP_REV_MINOR_SHIFT
5107 & CCE_REVISION_CHIP_REV_MINOR_MASK;
995deafa 5108 return (chip_rev_minor & 0xF0) == 0x10;
77241056
MM		 5109}
5110
5111/*
5112 * Append string s to buffer buf. Arguments curp and len are the current
5113 * position and remaining length, respectively.
5114 *
5115 * return 0 on success, 1 on out of room
5116 */
5117static int append_str(char *buf, char **curp, int *lenp, const char *s)
5118{
5119 char *p = *curp;
5120 int len = *lenp;
5121 int result = 0; /* success */
5122 char c;
5123
5124 /* add a comma, if first in the buffer */
5125 if (p != buf) {
5126 if (len == 0) {
5127 result = 1; /* out of room */
5128 goto done;
5129 }
5130 *p++ = ',';
5131 len--;
5132 }
5133
5134 /* copy the string */
5135 while ((c = *s++) != 0) {
5136 if (len == 0) {
5137 result = 1; /* out of room */
5138 goto done;
5139 }
5140 *p++ = c;
5141 len--;
5142 }
5143
5144done:
5145 /* write return values */
5146 *curp = p;
5147 *lenp = len;
5148
5149 return result;
5150}
5151
5152/*
5153 * Using the given flag table, print a comma separated string into
5154 * the buffer. End in '*' if the buffer is too short.
5155 */
5156static char *flag_string(char *buf, int buf_len, u64 flags,
5157 struct flag_table *table, int table_size)
5158{
5159 char extra[32];
5160 char *p = buf;
5161 int len = buf_len;
5162 int no_room = 0;
5163 int i;
5164
5165 /* make sure there is at least 2 so we can form "*" */
5166 if (len < 2)
5167 return "";
5168
5169 len--; /* leave room for a nul */
5170 for (i = 0; i < table_size; i++) {
5171 if (flags & table[i].flag) {
5172 no_room = append_str(buf, &p, &len, table[i].str);
5173 if (no_room)
5174 break;
5175 flags &= ~table[i].flag;
5176 }
5177 }
5178
5179 /* any undocumented bits left? */
5180 if (!no_room && flags) {
5181 snprintf(extra, sizeof(extra), "bits 0x%llx", flags);
5182 no_room = append_str(buf, &p, &len, extra);
5183 }
5184
5185 /* add * if ran out of room */
5186 if (no_room) {
5187 /* may need to back up to add space for a '*' */
5188 if (len == 0)
5189 --p;
5190 *p++ = '*';
5191 }
5192
5193 /* add final nul - space already allocated above */
5194 *p = 0;
5195 return buf;
5196}
5197
5198/* first 8 CCE error interrupt source names */
5199static const char * const cce_misc_names[] = {
5200 "CceErrInt", /* 0 */
5201 "RxeErrInt", /* 1 */
5202 "MiscErrInt", /* 2 */
5203 "Reserved3", /* 3 */
5204 "PioErrInt", /* 4 */
5205 "SDmaErrInt", /* 5 */
5206 "EgressErrInt", /* 6 */
5207 "TxeErrInt" /* 7 */
5208};
5209
5210/*
5211 * Return the miscellaneous error interrupt name.
5212 */
5213static char *is_misc_err_name(char *buf, size_t bsize, unsigned int source)
5214{
5215 if (source < ARRAY_SIZE(cce_misc_names))
5216 strncpy(buf, cce_misc_names[source], bsize);
5217 else
5218 snprintf(buf,
5219 bsize,
5220 "Reserved%u",
5221 source + IS_GENERAL_ERR_START);
5222
5223 return buf;
5224}
5225
5226/*
5227 * Return the SDMA engine error interrupt name.
5228 */
5229static char *is_sdma_eng_err_name(char *buf, size_t bsize, unsigned int source)
5230{
5231 snprintf(buf, bsize, "SDmaEngErrInt%u", source);
5232 return buf;
5233}
5234
5235/*
5236 * Return the send context error interrupt name.
5237 */
5238static char *is_sendctxt_err_name(char *buf, size_t bsize, unsigned int source)
5239{
5240 snprintf(buf, bsize, "SendCtxtErrInt%u", source);
5241 return buf;
5242}
5243
5244static const char * const various_names[] = {
5245 "PbcInt",
5246 "GpioAssertInt",
5247 "Qsfp1Int",
5248 "Qsfp2Int",
5249 "TCritInt"
5250};
5251
5252/*
5253 * Return the various interrupt name.
5254 */
5255static char *is_various_name(char *buf, size_t bsize, unsigned int source)
5256{
5257 if (source < ARRAY_SIZE(various_names))
5258 strncpy(buf, various_names[source], bsize);
5259 else
8638b77f 5260 snprintf(buf, bsize, "Reserved%u", source + IS_VARIOUS_START);
77241056
MM		 5261 return buf;
5262}
5263
5264/*
5265 * Return the DC interrupt name.
5266 */
5267static char *is_dc_name(char *buf, size_t bsize, unsigned int source)
5268{
5269 static const char * const dc_int_names[] = {
5270 "common",
5271 "lcb",
5272 "8051",
5273 "lbm" /* local block merge */
5274 };
5275
5276 if (source < ARRAY_SIZE(dc_int_names))
5277 snprintf(buf, bsize, "dc_%s_int", dc_int_names[source]);
5278 else
5279 snprintf(buf, bsize, "DCInt%u", source);
5280 return buf;
5281}
5282
5283static const char * const sdma_int_names[] = {
5284 "SDmaInt",
5285 "SdmaIdleInt",
5286 "SdmaProgressInt",
5287};
5288
5289/*
5290 * Return the SDMA engine interrupt name.
5291 */
5292static char *is_sdma_eng_name(char *buf, size_t bsize, unsigned int source)
5293{
5294 /* what interrupt */
5295 unsigned int what = source / TXE_NUM_SDMA_ENGINES;
5296 /* which engine */
5297 unsigned int which = source % TXE_NUM_SDMA_ENGINES;
5298
5299 if (likely(what < 3))
5300 snprintf(buf, bsize, "%s%u", sdma_int_names[what], which);
5301 else
5302 snprintf(buf, bsize, "Invalid SDMA interrupt %u", source);
5303 return buf;
5304}
5305
5306/*
5307 * Return the receive available interrupt name.
5308 */
5309static char *is_rcv_avail_name(char *buf, size_t bsize, unsigned int source)
5310{
5311 snprintf(buf, bsize, "RcvAvailInt%u", source);
5312 return buf;
5313}
5314
5315/*
5316 * Return the receive urgent interrupt name.
5317 */
5318static char *is_rcv_urgent_name(char *buf, size_t bsize, unsigned int source)
5319{
5320 snprintf(buf, bsize, "RcvUrgentInt%u", source);
5321 return buf;
5322}
5323
5324/*
5325 * Return the send credit interrupt name.
5326 */
5327static char *is_send_credit_name(char *buf, size_t bsize, unsigned int source)
5328{
5329 snprintf(buf, bsize, "SendCreditInt%u", source);
5330 return buf;
5331}
5332
5333/*
5334 * Return the reserved interrupt name.
5335 */
5336static char *is_reserved_name(char *buf, size_t bsize, unsigned int source)
5337{
5338 snprintf(buf, bsize, "Reserved%u", source + IS_RESERVED_START);
5339 return buf;
5340}
5341
5342static char *cce_err_status_string(char *buf, int buf_len, u64 flags)
5343{
5344 return flag_string(buf, buf_len, flags,
5345 cce_err_status_flags, ARRAY_SIZE(cce_err_status_flags));
5346}
5347
5348static char *rxe_err_status_string(char *buf, int buf_len, u64 flags)
5349{
5350 return flag_string(buf, buf_len, flags,
5351 rxe_err_status_flags, ARRAY_SIZE(rxe_err_status_flags));
5352}
5353
5354static char *misc_err_status_string(char *buf, int buf_len, u64 flags)
5355{
5356 return flag_string(buf, buf_len, flags, misc_err_status_flags,
5357 ARRAY_SIZE(misc_err_status_flags));
5358}
5359
5360static char *pio_err_status_string(char *buf, int buf_len, u64 flags)
5361{
5362 return flag_string(buf, buf_len, flags,
5363 pio_err_status_flags, ARRAY_SIZE(pio_err_status_flags));
5364}
5365
5366static char *sdma_err_status_string(char *buf, int buf_len, u64 flags)
5367{
5368 return flag_string(buf, buf_len, flags,
5369 sdma_err_status_flags,
5370 ARRAY_SIZE(sdma_err_status_flags));
5371}
5372
5373static char *egress_err_status_string(char *buf, int buf_len, u64 flags)
5374{
5375 return flag_string(buf, buf_len, flags,
5376 egress_err_status_flags, ARRAY_SIZE(egress_err_status_flags));
5377}
5378
5379static char *egress_err_info_string(char *buf, int buf_len, u64 flags)
5380{
5381 return flag_string(buf, buf_len, flags,
5382 egress_err_info_flags, ARRAY_SIZE(egress_err_info_flags));
5383}
5384
5385static char *send_err_status_string(char *buf, int buf_len, u64 flags)
5386{
5387 return flag_string(buf, buf_len, flags,
5388 send_err_status_flags,
5389 ARRAY_SIZE(send_err_status_flags));
5390}
5391
5392static void handle_cce_err(struct hfi1_devdata *dd, u32 unused, u64 reg)
5393{
5394 char buf[96];
2c5b521a 5395 int i = 0;
77241056
MM		 5396
5397 /*
5398 * For most these errors, there is nothing that can be done except
5399 * report or record it.
5400 */
5401 dd_dev_info(dd, "CCE Error: %s\n",
5402 cce_err_status_string(buf, sizeof(buf), reg));
5403
995deafa
MM		 5404 if ((reg & CCE_ERR_STATUS_CCE_CLI2_ASYNC_FIFO_PARITY_ERR_SMASK) &&
5405 is_ax(dd) && (dd->icode != ICODE_FUNCTIONAL_SIMULATOR)) {
77241056
MM		 5406 /* this error requires a manual drop into SPC freeze mode */
5407 /* then a fix up */
5408 start_freeze_handling(dd->pport, FREEZE_SELF);
5409 }
2c5b521a
JR		 5410
5411 for (i = 0; i < NUM_CCE_ERR_STATUS_COUNTERS; i++) {
5412 if (reg & (1ull << i)) {
5413 incr_cntr64(&dd->cce_err_status_cnt[i]);
5414 /* maintain a counter over all cce_err_status errors */
5415 incr_cntr64(&dd->sw_cce_err_status_aggregate);
5416 }
5417 }
77241056
MM		 5418}
5419
5420/*
5421 * Check counters for receive errors that do not have an interrupt
5422 * associated with them.
5423 */
5424#define RCVERR_CHECK_TIME 10
5425static void update_rcverr_timer(unsigned long opaque)
5426{
5427 struct hfi1_devdata *dd = (struct hfi1_devdata *)opaque;
5428 struct hfi1_pportdata *ppd = dd->pport;
5429 u32 cur_ovfl_cnt = read_dev_cntr(dd, C_RCV_OVF, CNTR_INVALID_VL);
5430
5431 if (dd->rcv_ovfl_cnt < cur_ovfl_cnt &&
5432 ppd->port_error_action & OPA_PI_MASK_EX_BUFFER_OVERRUN) {
5433 dd_dev_info(dd, "%s: PortErrorAction bounce\n", __func__);
5434 set_link_down_reason(ppd,
5435 OPA_LINKDOWN_REASON_EXCESSIVE_BUFFER_OVERRUN, 0,
5436 OPA_LINKDOWN_REASON_EXCESSIVE_BUFFER_OVERRUN);
5437 queue_work(ppd->hfi1_wq, &ppd->link_bounce_work);
5438 }
50e5dcbe 5439 dd->rcv_ovfl_cnt = (u32)cur_ovfl_cnt;
77241056
MM		 5440
5441 mod_timer(&dd->rcverr_timer, jiffies + HZ * RCVERR_CHECK_TIME);
5442}
5443
5444static int init_rcverr(struct hfi1_devdata *dd)
5445{
24523a94 5446 setup_timer(&dd->rcverr_timer, update_rcverr_timer, (unsigned long)dd);
77241056
MM		 5447 /* Assume the hardware counter has been reset */
5448 dd->rcv_ovfl_cnt = 0;
5449 return mod_timer(&dd->rcverr_timer, jiffies + HZ * RCVERR_CHECK_TIME);
5450}
5451
5452static void free_rcverr(struct hfi1_devdata *dd)
5453{
5454 if (dd->rcverr_timer.data)
5455 del_timer_sync(&dd->rcverr_timer);
5456 dd->rcverr_timer.data = 0;
5457}
5458
5459static void handle_rxe_err(struct hfi1_devdata *dd, u32 unused, u64 reg)
5460{
5461 char buf[96];
2c5b521a 5462 int i = 0;
77241056
MM		 5463
5464 dd_dev_info(dd, "Receive Error: %s\n",
5465 rxe_err_status_string(buf, sizeof(buf), reg));
5466
5467 if (reg & ALL_RXE_FREEZE_ERR) {
5468 int flags = 0;
5469
5470 /*
5471 * Freeze mode recovery is disabled for the errors
5472 * in RXE_FREEZE_ABORT_MASK
5473 */
995deafa 5474 if (is_ax(dd) && (reg & RXE_FREEZE_ABORT_MASK))
77241056
MM		 5475 flags = FREEZE_ABORT;
5476
5477 start_freeze_handling(dd->pport, flags);
5478 }
2c5b521a
JR		 5479
5480 for (i = 0; i < NUM_RCV_ERR_STATUS_COUNTERS; i++) {
5481 if (reg & (1ull << i))
5482 incr_cntr64(&dd->rcv_err_status_cnt[i]);
5483 }
77241056
MM		 5484}
5485
5486static void handle_misc_err(struct hfi1_devdata *dd, u32 unused, u64 reg)
5487{
5488 char buf[96];
2c5b521a 5489 int i = 0;
77241056
MM		 5490
5491 dd_dev_info(dd, "Misc Error: %s",
5492 misc_err_status_string(buf, sizeof(buf), reg));
2c5b521a
JR		 5493 for (i = 0; i < NUM_MISC_ERR_STATUS_COUNTERS; i++) {
5494 if (reg & (1ull << i))
5495 incr_cntr64(&dd->misc_err_status_cnt[i]);
5496 }
77241056
MM		 5497}
5498
5499static void handle_pio_err(struct hfi1_devdata *dd, u32 unused, u64 reg)
5500{
5501 char buf[96];
2c5b521a 5502 int i = 0;
77241056
MM		 5503
5504 dd_dev_info(dd, "PIO Error: %s\n",
5505 pio_err_status_string(buf, sizeof(buf), reg));
5506
5507 if (reg & ALL_PIO_FREEZE_ERR)
5508 start_freeze_handling(dd->pport, 0);
2c5b521a
JR		 5509
5510 for (i = 0; i < NUM_SEND_PIO_ERR_STATUS_COUNTERS; i++) {
5511 if (reg & (1ull << i))
5512 incr_cntr64(&dd->send_pio_err_status_cnt[i]);
5513 }
77241056
MM		 5514}
5515
5516static void handle_sdma_err(struct hfi1_devdata *dd, u32 unused, u64 reg)
5517{
5518 char buf[96];
2c5b521a 5519 int i = 0;
77241056
MM		 5520
5521 dd_dev_info(dd, "SDMA Error: %s\n",
5522 sdma_err_status_string(buf, sizeof(buf), reg));
5523
5524 if (reg & ALL_SDMA_FREEZE_ERR)
5525 start_freeze_handling(dd->pport, 0);
2c5b521a
JR		 5526
5527 for (i = 0; i < NUM_SEND_DMA_ERR_STATUS_COUNTERS; i++) {
5528 if (reg & (1ull << i))
5529 incr_cntr64(&dd->send_dma_err_status_cnt[i]);
5530 }
77241056
MM		 5531}
5532
69a00b8e 5533static inline void __count_port_discards(struct hfi1_pportdata *ppd)
77241056 5534{
69a00b8e
MM		 5535 incr_cntr64(&ppd->port_xmit_discards);
5536}
77241056 5537
69a00b8e
MM		 5538static void count_port_inactive(struct hfi1_devdata *dd)
5539{
5540 __count_port_discards(dd->pport);
77241056
MM		 5541}
5542
5543/*
5544 * We have had a "disallowed packet" error during egress. Determine the
5545 * integrity check which failed, and update relevant error counter, etc.
5546 *
5547 * Note that the SEND_EGRESS_ERR_INFO register has only a single
5548 * bit of state per integrity check, and so we can miss the reason for an
5549 * egress error if more than one packet fails the same integrity check
5550 * since we cleared the corresponding bit in SEND_EGRESS_ERR_INFO.
5551 */
69a00b8e
MM		 5552static void handle_send_egress_err_info(struct hfi1_devdata *dd,
5553 int vl)
77241056
MM		 5554{
5555 struct hfi1_pportdata *ppd = dd->pport;
5556 u64 src = read_csr(dd, SEND_EGRESS_ERR_SOURCE); /* read first */
5557 u64 info = read_csr(dd, SEND_EGRESS_ERR_INFO);
5558 char buf[96];
5559
5560 /* clear down all observed info as quickly as possible after read */
5561 write_csr(dd, SEND_EGRESS_ERR_INFO, info);
5562
5563 dd_dev_info(dd,
5564 "Egress Error Info: 0x%llx, %s Egress Error Src 0x%llx\n",
5565 info, egress_err_info_string(buf, sizeof(buf), info), src);
5566
5567 /* Eventually add other counters for each bit */
69a00b8e
MM		 5568 if (info & PORT_DISCARD_EGRESS_ERRS) {
5569 int weight, i;
77241056 5570
69a00b8e
MM		 5571 /*
5572 * Count all, in case multiple bits are set. Reminder:
5573 * since there is only one info register for many sources,
5574 * these may be attributed to the wrong VL if they occur
5575 * too close together.
5576 */
5577 weight = hweight64(info);
5578 for (i = 0; i < weight; i++) {
5579 __count_port_discards(ppd);
5580 if (vl >= 0 && vl < TXE_NUM_DATA_VL)
5581 incr_cntr64(&ppd->port_xmit_discards_vl[vl]);
5582 else if (vl == 15)
5583 incr_cntr64(&ppd->port_xmit_discards_vl
5584 [C_VL_15]);
5585 }
77241056
MM		 5586 }
5587}
5588
5589/*
5590 * Input value is a bit position within the SEND_EGRESS_ERR_STATUS
5591 * register. Does it represent a 'port inactive' error?
5592 */
5593static inline int port_inactive_err(u64 posn)
5594{
5595 return (posn >= SEES(TX_LINKDOWN) &&
5596 posn <= SEES(TX_INCORRECT_LINK_STATE));
5597}
5598
5599/*
5600 * Input value is a bit position within the SEND_EGRESS_ERR_STATUS
5601 * register. Does it represent a 'disallowed packet' error?
5602 */
69a00b8e 5603static inline int disallowed_pkt_err(int posn)
77241056
MM		 5604{
5605 return (posn >= SEES(TX_SDMA0_DISALLOWED_PACKET) &&
5606 posn <= SEES(TX_SDMA15_DISALLOWED_PACKET));
5607}
5608
69a00b8e
MM		 5609/*
5610 * Input value is a bit position of one of the SDMA engine disallowed
5611 * packet errors. Return which engine. Use of this must be guarded by
5612 * disallowed_pkt_err().
5613 */
5614static inline int disallowed_pkt_engine(int posn)
5615{
5616 return posn - SEES(TX_SDMA0_DISALLOWED_PACKET);
5617}
5618
5619/*
5620 * Translate an SDMA engine to a VL. Return -1 if the tranlation cannot
5621 * be done.
5622 */
5623static int engine_to_vl(struct hfi1_devdata *dd, int engine)
5624{
5625 struct sdma_vl_map *m;
5626 int vl;
5627
5628 /* range check */
5629 if (engine < 0 || engine >= TXE_NUM_SDMA_ENGINES)
5630 return -1;
5631
5632 rcu_read_lock();
5633 m = rcu_dereference(dd->sdma_map);
5634 vl = m->engine_to_vl[engine];
5635 rcu_read_unlock();
5636
5637 return vl;
5638}
5639
5640/*
5641 * Translate the send context (sofware index) into a VL. Return -1 if the
5642 * translation cannot be done.
5643 */
5644static int sc_to_vl(struct hfi1_devdata *dd, int sw_index)
5645{
5646 struct send_context_info *sci;
5647 struct send_context *sc;
5648 int i;
5649
5650 sci = &dd->send_contexts[sw_index];
5651
5652 /* there is no information for user (PSM) and ack contexts */
5653 if (sci->type != SC_KERNEL)
5654 return -1;
5655
5656 sc = sci->sc;
5657 if (!sc)
5658 return -1;
5659 if (dd->vld[15].sc == sc)
5660 return 15;
5661 for (i = 0; i < num_vls; i++)
5662 if (dd->vld[i].sc == sc)
5663 return i;
5664
5665 return -1;
5666}
5667
77241056
MM		 5668static void handle_egress_err(struct hfi1_devdata *dd, u32 unused, u64 reg)
5669{
5670 u64 reg_copy = reg, handled = 0;
5671 char buf[96];
2c5b521a 5672 int i = 0;
77241056
MM		 5673
5674 if (reg & ALL_TXE_EGRESS_FREEZE_ERR)
5675 start_freeze_handling(dd->pport, 0);
69a00b8e
MM		 5676 else if (is_ax(dd) &&
5677 (reg & SEND_EGRESS_ERR_STATUS_TX_CREDIT_RETURN_VL_ERR_SMASK) &&
5678 (dd->icode != ICODE_FUNCTIONAL_SIMULATOR))
77241056
MM		 5679 start_freeze_handling(dd->pport, 0);
5680
5681 while (reg_copy) {
5682 int posn = fls64(reg_copy);
69a00b8e 5683 /* fls64() returns a 1-based offset, we want it zero based */
77241056 5684 int shift = posn - 1;
69a00b8e 5685 u64 mask = 1ULL << shift;
77241056
MM		 5686
5687 if (port_inactive_err(shift)) {
5688 count_port_inactive(dd);
69a00b8e 5689 handled |= mask;
77241056 5690 } else if (disallowed_pkt_err(shift)) {
69a00b8e
MM		 5691 int vl = engine_to_vl(dd, disallowed_pkt_engine(shift));
5692
5693 handle_send_egress_err_info(dd, vl);
5694 handled |= mask;
77241056 5695 }
69a00b8e 5696 reg_copy &= ~mask;
77241056
MM		 5697 }
5698
5699 reg &= ~handled;
5700
5701 if (reg)
5702 dd_dev_info(dd, "Egress Error: %s\n",
5703 egress_err_status_string(buf, sizeof(buf), reg));
2c5b521a
JR		 5704
5705 for (i = 0; i < NUM_SEND_EGRESS_ERR_STATUS_COUNTERS; i++) {
5706 if (reg & (1ull << i))
5707 incr_cntr64(&dd->send_egress_err_status_cnt[i]);
5708 }
77241056
MM		 5709}
5710
5711static void handle_txe_err(struct hfi1_devdata *dd, u32 unused, u64 reg)
5712{
5713 char buf[96];
2c5b521a 5714 int i = 0;
77241056
MM		 5715
5716 dd_dev_info(dd, "Send Error: %s\n",
5717 send_err_status_string(buf, sizeof(buf), reg));
5718
2c5b521a
JR		 5719 for (i = 0; i < NUM_SEND_ERR_STATUS_COUNTERS; i++) {
5720 if (reg & (1ull << i))
5721 incr_cntr64(&dd->send_err_status_cnt[i]);
5722 }
77241056
MM		 5723}
5724
5725/*
5726 * The maximum number of times the error clear down will loop before
5727 * blocking a repeating error. This value is arbitrary.
5728 */
5729#define MAX_CLEAR_COUNT 20
5730
5731/*
5732 * Clear and handle an error register. All error interrupts are funneled
5733 * through here to have a central location to correctly handle single-
5734 * or multi-shot errors.
5735 *
5736 * For non per-context registers, call this routine with a context value
5737 * of 0 so the per-context offset is zero.
5738 *
5739 * If the handler loops too many times, assume that something is wrong
5740 * and can't be fixed, so mask the error bits.
5741 */
5742static void interrupt_clear_down(struct hfi1_devdata *dd,
5743 u32 context,
5744 const struct err_reg_info *eri)
5745{
5746 u64 reg;
5747 u32 count;
5748
5749 /* read in a loop until no more errors are seen */
5750 count = 0;
5751 while (1) {
5752 reg = read_kctxt_csr(dd, context, eri->status);
5753 if (reg == 0)
5754 break;
5755 write_kctxt_csr(dd, context, eri->clear, reg);
5756 if (likely(eri->handler))
5757 eri->handler(dd, context, reg);
5758 count++;
5759 if (count > MAX_CLEAR_COUNT) {
5760 u64 mask;
5761
5762 dd_dev_err(dd, "Repeating %s bits 0x%llx - masking\n",
5763 eri->desc, reg);
5764 /*
5765 * Read-modify-write so any other masked bits
5766 * remain masked.
5767 */
5768 mask = read_kctxt_csr(dd, context, eri->mask);
5769 mask &= ~reg;
5770 write_kctxt_csr(dd, context, eri->mask, mask);
5771 break;
5772 }
5773 }
5774}
5775
5776/*
5777 * CCE block "misc" interrupt. Source is < 16.
5778 */
5779static void is_misc_err_int(struct hfi1_devdata *dd, unsigned int source)
5780{
5781 const struct err_reg_info *eri = &misc_errs[source];
5782
5783 if (eri->handler) {
5784 interrupt_clear_down(dd, 0, eri);
5785 } else {
5786 dd_dev_err(dd, "Unexpected misc interrupt (%u) - reserved\n",
5787 source);
5788 }
5789}
5790
5791static char *send_context_err_status_string(char *buf, int buf_len, u64 flags)
5792{
5793 return flag_string(buf, buf_len, flags,
5794 sc_err_status_flags, ARRAY_SIZE(sc_err_status_flags));
5795}
5796
5797/*
5798 * Send context error interrupt. Source (hw_context) is < 160.
5799 *
5800 * All send context errors cause the send context to halt. The normal
5801 * clear-down mechanism cannot be used because we cannot clear the
5802 * error bits until several other long-running items are done first.
5803 * This is OK because with the context halted, nothing else is going
5804 * to happen on it anyway.
5805 */
5806static void is_sendctxt_err_int(struct hfi1_devdata *dd,
5807 unsigned int hw_context)
5808{
5809 struct send_context_info *sci;
5810 struct send_context *sc;
5811 char flags[96];
5812 u64 status;
5813 u32 sw_index;
2c5b521a 5814 int i = 0;
77241056
MM		 5815
5816 sw_index = dd->hw_to_sw[hw_context];
5817 if (sw_index >= dd->num_send_contexts) {
5818 dd_dev_err(dd,
5819 "out of range sw index %u for send context %u\n",
5820 sw_index, hw_context);
5821 return;
5822 }
5823 sci = &dd->send_contexts[sw_index];
5824 sc = sci->sc;
5825 if (!sc) {
5826 dd_dev_err(dd, "%s: context %u(%u): no sc?\n", __func__,
5827 sw_index, hw_context);
5828 return;
5829 }
5830
5831 /* tell the software that a halt has begun */
5832 sc_stop(sc, SCF_HALTED);
5833
5834 status = read_kctxt_csr(dd, hw_context, SEND_CTXT_ERR_STATUS);
5835
5836 dd_dev_info(dd, "Send Context %u(%u) Error: %s\n", sw_index, hw_context,
5837 send_context_err_status_string(flags, sizeof(flags), status));
5838
5839 if (status & SEND_CTXT_ERR_STATUS_PIO_DISALLOWED_PACKET_ERR_SMASK)
69a00b8e 5840 handle_send_egress_err_info(dd, sc_to_vl(dd, sw_index));
77241056
MM		 5841
5842 /*
5843 * Automatically restart halted kernel contexts out of interrupt
5844 * context. User contexts must ask the driver to restart the context.
5845 */
5846 if (sc->type != SC_USER)
5847 queue_work(dd->pport->hfi1_wq, &sc->halt_work);
2c5b521a
JR		 5848
5849 /*
5850 * Update the counters for the corresponding status bits.
5851 * Note that these particular counters are aggregated over all
5852 * 160 contexts.
5853 */
5854 for (i = 0; i < NUM_SEND_CTXT_ERR_STATUS_COUNTERS; i++) {
5855 if (status & (1ull << i))
5856 incr_cntr64(&dd->sw_ctxt_err_status_cnt[i]);
5857 }
77241056
MM		 5858}
5859
5860static void handle_sdma_eng_err(struct hfi1_devdata *dd,
5861 unsigned int source, u64 status)
5862{
5863 struct sdma_engine *sde;
2c5b521a 5864 int i = 0;
77241056
MM		 5865
5866 sde = &dd->per_sdma[source];
5867#ifdef CONFIG_SDMA_VERBOSITY
5868 dd_dev_err(sde->dd, "CONFIG SDMA(%u) %s:%d %s()\n", sde->this_idx,
5869 slashstrip(__FILE__), __LINE__, __func__);
5870 dd_dev_err(sde->dd, "CONFIG SDMA(%u) source: %u status 0x%llx\n",
5871 sde->this_idx, source, (unsigned long long)status);
5872#endif
a699c6c2 5873 sde->err_cnt++;
77241056 5874 sdma_engine_error(sde, status);
2c5b521a
JR		 5875
5876 /*
5877 * Update the counters for the corresponding status bits.
5878 * Note that these particular counters are aggregated over
5879 * all 16 DMA engines.
5880 */
5881 for (i = 0; i < NUM_SEND_DMA_ENG_ERR_STATUS_COUNTERS; i++) {
5882 if (status & (1ull << i))
5883 incr_cntr64(&dd->sw_send_dma_eng_err_status_cnt[i]);
5884 }
77241056
MM		 5885}
5886
5887/*
5888 * CCE block SDMA error interrupt. Source is < 16.
5889 */
5890static void is_sdma_eng_err_int(struct hfi1_devdata *dd, unsigned int source)
5891{
5892#ifdef CONFIG_SDMA_VERBOSITY
5893 struct sdma_engine *sde = &dd->per_sdma[source];
5894
5895 dd_dev_err(dd, "CONFIG SDMA(%u) %s:%d %s()\n", sde->this_idx,
5896 slashstrip(__FILE__), __LINE__, __func__);
5897 dd_dev_err(dd, "CONFIG SDMA(%u) source: %u\n", sde->this_idx,
5898 source);
5899 sdma_dumpstate(sde);
5900#endif
5901 interrupt_clear_down(dd, source, &sdma_eng_err);
5902}
5903
5904/*
5905 * CCE block "various" interrupt. Source is < 8.
5906 */
5907static void is_various_int(struct hfi1_devdata *dd, unsigned int source)
5908{
5909 const struct err_reg_info *eri = &various_err[source];
5910
5911 /*
5912 * TCritInt cannot go through interrupt_clear_down()
5913 * because it is not a second tier interrupt. The handler
5914 * should be called directly.
5915 */
5916 if (source == TCRIT_INT_SOURCE)
5917 handle_temp_err(dd);
5918 else if (eri->handler)
5919 interrupt_clear_down(dd, 0, eri);
5920 else
5921 dd_dev_info(dd,
5922 "%s: Unimplemented/reserved interrupt %d\n",
5923 __func__, source);
5924}
5925
5926static void handle_qsfp_int(struct hfi1_devdata *dd, u32 src_ctx, u64 reg)
5927{
8ebd4cf1 5928 /* src_ctx is always zero */
77241056
MM		 5929 struct hfi1_pportdata *ppd = dd->pport;
5930 unsigned long flags;
5931 u64 qsfp_int_mgmt = (u64)(QSFP_HFI0_INT_N | QSFP_HFI0_MODPRST_N);
5932
5933 if (reg & QSFP_HFI0_MODPRST_N) {
5934
5935 dd_dev_info(dd, "%s: ModPresent triggered QSFP interrupt\n",
5936 __func__);
5937
5938 if (!qsfp_mod_present(ppd)) {
5939 ppd->driver_link_ready = 0;
5940 /*
5941 * Cable removed, reset all our information about the
5942 * cache and cable capabilities
5943 */
5944
5945 spin_lock_irqsave(&ppd->qsfp_info.qsfp_lock, flags);
5946 /*
5947 * We don't set cache_refresh_required here as we expect
5948 * an interrupt when a cable is inserted
5949 */
5950 ppd->qsfp_info.cache_valid = 0;
8ebd4cf1
EH		 5951 ppd->qsfp_info.reset_needed = 0;
5952 ppd->qsfp_info.limiting_active = 0;
77241056
MM		 5953 spin_unlock_irqrestore(&ppd->qsfp_info.qsfp_lock,
5954 flags);
8ebd4cf1
EH		 5955 /* Invert the ModPresent pin now to detect plug-in */
5956 write_csr(dd, dd->hfi1_id ? ASIC_QSFP2_INVERT :
5957 ASIC_QSFP1_INVERT, qsfp_int_mgmt);
a9c05e35
BM		 5958
5959 if ((ppd->offline_disabled_reason >
5960 HFI1_ODR_MASK(
e1bf0d5e 5961 OPA_LINKDOWN_REASON_LOCAL_MEDIA_NOT_INSTALLED)) ||
a9c05e35
BM		 5962 (ppd->offline_disabled_reason ==
5963 HFI1_ODR_MASK(OPA_LINKDOWN_REASON_NONE)))
5964 ppd->offline_disabled_reason =
5965 HFI1_ODR_MASK(
e1bf0d5e 5966 OPA_LINKDOWN_REASON_LOCAL_MEDIA_NOT_INSTALLED);
a9c05e35 5967
77241056
MM		 5968 if (ppd->host_link_state == HLS_DN_POLL) {
5969 /*
5970 * The link is still in POLL. This means
5971 * that the normal link down processing
5972 * will not happen. We have to do it here
5973 * before turning the DC off.
5974 */
5975 queue_work(ppd->hfi1_wq, &ppd->link_down_work);
5976 }
5977 } else {
5978 spin_lock_irqsave(&ppd->qsfp_info.qsfp_lock, flags);
5979 ppd->qsfp_info.cache_valid = 0;
5980 ppd->qsfp_info.cache_refresh_required = 1;
5981 spin_unlock_irqrestore(&ppd->qsfp_info.qsfp_lock,
5982 flags);
5983
8ebd4cf1
EH		 5984 /*
5985 * Stop inversion of ModPresent pin to detect
5986 * removal of the cable
5987 */
77241056 5988 qsfp_int_mgmt &= ~(u64)QSFP_HFI0_MODPRST_N;
8ebd4cf1
EH		 5989 write_csr(dd, dd->hfi1_id ? ASIC_QSFP2_INVERT :
5990 ASIC_QSFP1_INVERT, qsfp_int_mgmt);
5991
5992 ppd->offline_disabled_reason =
5993 HFI1_ODR_MASK(OPA_LINKDOWN_REASON_TRANSIENT);
77241056
MM		 5994 }
5995 }
5996
5997 if (reg & QSFP_HFI0_INT_N) {
5998
5999 dd_dev_info(dd, "%s: IntN triggered QSFP interrupt\n",
6000 __func__);
6001 spin_lock_irqsave(&ppd->qsfp_info.qsfp_lock, flags);
6002 ppd->qsfp_info.check_interrupt_flags = 1;
77241056
MM		 6003 spin_unlock_irqrestore(&ppd->qsfp_info.qsfp_lock, flags);
6004 }
6005
6006 /* Schedule the QSFP work only if there is a cable attached. */
6007 if (qsfp_mod_present(ppd))
6008 queue_work(ppd->hfi1_wq, &ppd->qsfp_info.qsfp_work);
6009}
6010
6011static int request_host_lcb_access(struct hfi1_devdata *dd)
6012{
6013 int ret;
6014
6015 ret = do_8051_command(dd, HCMD_MISC,
6016 (u64)HCMD_MISC_REQUEST_LCB_ACCESS << LOAD_DATA_FIELD_ID_SHIFT,
6017 NULL);
6018 if (ret != HCMD_SUCCESS) {
6019 dd_dev_err(dd, "%s: command failed with error %d\n",
6020 __func__, ret);
6021 }
6022 return ret == HCMD_SUCCESS ? 0 : -EBUSY;
6023}
6024
6025static int request_8051_lcb_access(struct hfi1_devdata *dd)
6026{
6027 int ret;
6028
6029 ret = do_8051_command(dd, HCMD_MISC,
6030 (u64)HCMD_MISC_GRANT_LCB_ACCESS << LOAD_DATA_FIELD_ID_SHIFT,
6031 NULL);
6032 if (ret != HCMD_SUCCESS) {
6033 dd_dev_err(dd, "%s: command failed with error %d\n",
6034 __func__, ret);
6035 }
6036 return ret == HCMD_SUCCESS ? 0 : -EBUSY;
6037}
6038
6039/*
6040 * Set the LCB selector - allow host access. The DCC selector always
6041 * points to the host.
6042 */
6043static inline void set_host_lcb_access(struct hfi1_devdata *dd)
6044{
6045 write_csr(dd, DC_DC8051_CFG_CSR_ACCESS_SEL,
6046 DC_DC8051_CFG_CSR_ACCESS_SEL_DCC_SMASK
6047 | DC_DC8051_CFG_CSR_ACCESS_SEL_LCB_SMASK);
6048}
6049
6050/*
6051 * Clear the LCB selector - allow 8051 access. The DCC selector always
6052 * points to the host.
6053 */
6054static inline void set_8051_lcb_access(struct hfi1_devdata *dd)
6055{
6056 write_csr(dd, DC_DC8051_CFG_CSR_ACCESS_SEL,
6057 DC_DC8051_CFG_CSR_ACCESS_SEL_DCC_SMASK);
6058}
6059
6060/*
6061 * Acquire LCB access from the 8051. If the host already has access,
6062 * just increment a counter. Otherwise, inform the 8051 that the
6063 * host is taking access.
6064 *
6065 * Returns:
6066 * 0 on success
6067 * -EBUSY if the 8051 has control and cannot be disturbed
6068 * -errno if unable to acquire access from the 8051
6069 */
6070int acquire_lcb_access(struct hfi1_devdata *dd, int sleep_ok)
6071{
6072 struct hfi1_pportdata *ppd = dd->pport;
6073 int ret = 0;
6074
6075 /*
6076 * Use the host link state lock so the operation of this routine
6077 * { link state check, selector change, count increment } can occur
6078 * as a unit against a link state change. Otherwise there is a
6079 * race between the state change and the count increment.
6080 */
6081 if (sleep_ok) {
6082 mutex_lock(&ppd->hls_lock);
6083 } else {
951842b0 6084 while (!mutex_trylock(&ppd->hls_lock))
77241056
MM		 6085 udelay(1);
6086 }
6087
6088 /* this access is valid only when the link is up */
6089 if ((ppd->host_link_state & HLS_UP) == 0) {
6090 dd_dev_info(dd, "%s: link state %s not up\n",
6091 __func__, link_state_name(ppd->host_link_state));
6092 ret = -EBUSY;
6093 goto done;
6094 }
6095
6096 if (dd->lcb_access_count == 0) {
6097 ret = request_host_lcb_access(dd);
6098 if (ret) {
6099 dd_dev_err(dd,
6100 "%s: unable to acquire LCB access, err %d\n",
6101 __func__, ret);
6102 goto done;
6103 }
6104 set_host_lcb_access(dd);
6105 }
6106 dd->lcb_access_count++;
6107done:
6108 mutex_unlock(&ppd->hls_lock);
6109 return ret;
6110}
6111
6112/*
6113 * Release LCB access by decrementing the use count. If the count is moving
6114 * from 1 to 0, inform 8051 that it has control back.
6115 *
6116 * Returns:
6117 * 0 on success
6118 * -errno if unable to release access to the 8051
6119 */
6120int release_lcb_access(struct hfi1_devdata *dd, int sleep_ok)
6121{
6122 int ret = 0;
6123
6124 /*
6125 * Use the host link state lock because the acquire needed it.
6126 * Here, we only need to keep { selector change, count decrement }
6127 * as a unit.
6128 */
6129 if (sleep_ok) {
6130 mutex_lock(&dd->pport->hls_lock);
6131 } else {
951842b0 6132 while (!mutex_trylock(&dd->pport->hls_lock))
77241056
MM		 6133 udelay(1);
6134 }
6135
6136 if (dd->lcb_access_count == 0) {
6137 dd_dev_err(dd, "%s: LCB access count is zero. Skipping.\n",
6138 __func__);
6139 goto done;
6140 }
6141
6142 if (dd->lcb_access_count == 1) {
6143 set_8051_lcb_access(dd);
6144 ret = request_8051_lcb_access(dd);
6145 if (ret) {
6146 dd_dev_err(dd,
6147 "%s: unable to release LCB access, err %d\n",
6148 __func__, ret);
6149 /* restore host access if the grant didn't work */
6150 set_host_lcb_access(dd);
6151 goto done;
6152 }
6153 }
6154 dd->lcb_access_count--;
6155done:
6156 mutex_unlock(&dd->pport->hls_lock);
6157 return ret;
6158}
6159
6160/*
6161 * Initialize LCB access variables and state. Called during driver load,
6162 * after most of the initialization is finished.
6163 *
6164 * The DC default is LCB access on for the host. The driver defaults to
6165 * leaving access to the 8051. Assign access now - this constrains the call
6166 * to this routine to be after all LCB set-up is done. In particular, after
6167 * hf1_init_dd() -> set_up_interrupts() -> clear_all_interrupts()
6168 */
6169static void init_lcb_access(struct hfi1_devdata *dd)
6170{
6171 dd->lcb_access_count = 0;
6172}
6173
6174/*
6175 * Write a response back to a 8051 request.
6176 */
6177static void hreq_response(struct hfi1_devdata *dd, u8 return_code, u16 rsp_data)
6178{
6179 write_csr(dd, DC_DC8051_CFG_EXT_DEV_0,
6180 DC_DC8051_CFG_EXT_DEV_0_COMPLETED_SMASK
6181 | (u64)return_code << DC_DC8051_CFG_EXT_DEV_0_RETURN_CODE_SHIFT
6182 | (u64)rsp_data << DC_DC8051_CFG_EXT_DEV_0_RSP_DATA_SHIFT);
6183}
6184
6185/*
cbac386a
EH		 6186 * Handle host requests from the 8051.
6187 *
6188 * This is a work-queue function outside of the interrupt.
77241056 6189 */
cbac386a 6190void handle_8051_request(struct work_struct *work)
77241056 6191{
cbac386a
EH		 6192 struct hfi1_pportdata *ppd = container_of(work, struct hfi1_pportdata,
6193 dc_host_req_work);
6194 struct hfi1_devdata *dd = ppd->dd;
77241056 6195 u64 reg;
cbac386a
EH		 6196 u16 data = 0;
6197 u8 type, i, lanes, *cache = ppd->qsfp_info.cache;
6198 u8 cdr_ctrl_byte = cache[QSFP_CDR_CTRL_BYTE_OFFS];
77241056
MM		 6199
6200 reg = read_csr(dd, DC_DC8051_CFG_EXT_DEV_1);
6201 if ((reg & DC_DC8051_CFG_EXT_DEV_1_REQ_NEW_SMASK) == 0)
6202 return; /* no request */
6203
6204 /* zero out COMPLETED so the response is seen */
6205 write_csr(dd, DC_DC8051_CFG_EXT_DEV_0, 0);
6206
6207 /* extract request details */
6208 type = (reg >> DC_DC8051_CFG_EXT_DEV_1_REQ_TYPE_SHIFT)
6209 & DC_DC8051_CFG_EXT_DEV_1_REQ_TYPE_MASK;
6210 data = (reg >> DC_DC8051_CFG_EXT_DEV_1_REQ_DATA_SHIFT)
6211 & DC_DC8051_CFG_EXT_DEV_1_REQ_DATA_MASK;
6212
6213 switch (type) {
6214 case HREQ_LOAD_CONFIG:
6215 case HREQ_SAVE_CONFIG:
6216 case HREQ_READ_CONFIG:
6217 case HREQ_SET_TX_EQ_ABS:
6218 case HREQ_SET_TX_EQ_REL:
77241056
MM		 6219 dd_dev_info(dd, "8051 request: request 0x%x not supported\n",
6220 type);
6221 hreq_response(dd, HREQ_NOT_SUPPORTED, 0);
6222 break;
6223
cbac386a
EH		 6224 case HREQ_ENABLE:
6225 lanes = data & 0xF;
6226 for (i = 0; lanes; lanes >>= 1, i++) {
6227 if (!(lanes & 1))
6228 continue;
6229 if (data & 0x200) {
6230 /* enable TX CDR */
6231 if (cache[QSFP_MOD_PWR_OFFS] & 0x8 &&
6232 cache[QSFP_CDR_INFO_OFFS] & 0x80)
6233 cdr_ctrl_byte |= (1 << (i + 4));
6234 } else {
6235 /* disable TX CDR */
6236 if (cache[QSFP_MOD_PWR_OFFS] & 0x8 &&
6237 cache[QSFP_CDR_INFO_OFFS] & 0x80)
6238 cdr_ctrl_byte &= ~(1 << (i + 4));
6239 }
6240
6241 if (data & 0x800) {
6242 /* enable RX CDR */
6243 if (cache[QSFP_MOD_PWR_OFFS] & 0x4 &&
6244 cache[QSFP_CDR_INFO_OFFS] & 0x40)
6245 cdr_ctrl_byte |= (1 << i);
6246 } else {
6247 /* disable RX CDR */
6248 if (cache[QSFP_MOD_PWR_OFFS] & 0x4 &&
6249 cache[QSFP_CDR_INFO_OFFS] & 0x40)
6250 cdr_ctrl_byte &= ~(1 << i);
6251 }
6252 }
6253 qsfp_write(ppd, ppd->dd->hfi1_id, QSFP_CDR_CTRL_BYTE_OFFS,
6254 &cdr_ctrl_byte, 1);
6255 hreq_response(dd, HREQ_SUCCESS, data);
6256 refresh_qsfp_cache(ppd, &ppd->qsfp_info);
6257 break;
6258
77241056
MM		 6259 case HREQ_CONFIG_DONE:
6260 hreq_response(dd, HREQ_SUCCESS, 0);
6261 break;
6262
6263 case HREQ_INTERFACE_TEST:
6264 hreq_response(dd, HREQ_SUCCESS, data);
6265 break;
6266
6267 default:
6268 dd_dev_err(dd, "8051 request: unknown request 0x%x\n", type);
6269 hreq_response(dd, HREQ_NOT_SUPPORTED, 0);
6270 break;
6271 }
6272}
6273
6274static void write_global_credit(struct hfi1_devdata *dd,
6275 u8 vau, u16 total, u16 shared)
6276{
6277 write_csr(dd, SEND_CM_GLOBAL_CREDIT,
6278 ((u64)total
6279 << SEND_CM_GLOBAL_CREDIT_TOTAL_CREDIT_LIMIT_SHIFT)
6280 | ((u64)shared
6281 << SEND_CM_GLOBAL_CREDIT_SHARED_LIMIT_SHIFT)
6282 | ((u64)vau << SEND_CM_GLOBAL_CREDIT_AU_SHIFT));
6283}
6284
6285/*
6286 * Set up initial VL15 credits of the remote. Assumes the rest of
6287 * the CM credit registers are zero from a previous global or credit reset .
6288 */
6289void set_up_vl15(struct hfi1_devdata *dd, u8 vau, u16 vl15buf)
6290{
6291 /* leave shared count at zero for both global and VL15 */
6292 write_global_credit(dd, vau, vl15buf, 0);
6293
6294 /* We may need some credits for another VL when sending packets
6295 * with the snoop interface. Dividing it down the middle for VL15
6296 * and VL0 should suffice.
6297 */
6298 if (unlikely(dd->hfi1_snoop.mode_flag == HFI1_PORT_SNOOP_MODE)) {
6299 write_csr(dd, SEND_CM_CREDIT_VL15, (u64)(vl15buf >> 1)
6300 << SEND_CM_CREDIT_VL15_DEDICATED_LIMIT_VL_SHIFT);
6301 write_csr(dd, SEND_CM_CREDIT_VL, (u64)(vl15buf >> 1)
6302 << SEND_CM_CREDIT_VL_DEDICATED_LIMIT_VL_SHIFT);
6303 } else {
6304 write_csr(dd, SEND_CM_CREDIT_VL15, (u64)vl15buf
6305 << SEND_CM_CREDIT_VL15_DEDICATED_LIMIT_VL_SHIFT);
6306 }
6307}
6308
6309/*
6310 * Zero all credit details from the previous connection and
6311 * reset the CM manager's internal counters.
6312 */
6313void reset_link_credits(struct hfi1_devdata *dd)
6314{
6315 int i;
6316
6317 /* remove all previous VL credit limits */
6318 for (i = 0; i < TXE_NUM_DATA_VL; i++)
8638b77f 6319 write_csr(dd, SEND_CM_CREDIT_VL + (8 * i), 0);
77241056
MM		 6320 write_csr(dd, SEND_CM_CREDIT_VL15, 0);
6321 write_global_credit(dd, 0, 0, 0);
6322 /* reset the CM block */
6323 pio_send_control(dd, PSC_CM_RESET);
6324}
6325
6326/* convert a vCU to a CU */
6327static u32 vcu_to_cu(u8 vcu)
6328{
6329 return 1 << vcu;
6330}
6331
6332/* convert a CU to a vCU */
6333static u8 cu_to_vcu(u32 cu)
6334{
6335 return ilog2(cu);
6336}
6337
6338/* convert a vAU to an AU */
6339static u32 vau_to_au(u8 vau)
6340{
6341 return 8 * (1 << vau);
6342}
6343
6344static void set_linkup_defaults(struct hfi1_pportdata *ppd)
6345{
6346 ppd->sm_trap_qp = 0x0;
6347 ppd->sa_qp = 0x1;
6348}
6349
6350/*
6351 * Graceful LCB shutdown. This leaves the LCB FIFOs in reset.
6352 */
6353static void lcb_shutdown(struct hfi1_devdata *dd, int abort)
6354{
6355 u64 reg;
6356
6357 /* clear lcb run: LCB_CFG_RUN.EN = 0 */
6358 write_csr(dd, DC_LCB_CFG_RUN, 0);
6359 /* set tx fifo reset: LCB_CFG_TX_FIFOS_RESET.VAL = 1 */
6360 write_csr(dd, DC_LCB_CFG_TX_FIFOS_RESET,
6361 1ull << DC_LCB_CFG_TX_FIFOS_RESET_VAL_SHIFT);
6362 /* set dcc reset csr: DCC_CFG_RESET.{reset_lcb,reset_rx_fpe} = 1 */
6363 dd->lcb_err_en = read_csr(dd, DC_LCB_ERR_EN);
6364 reg = read_csr(dd, DCC_CFG_RESET);
6365 write_csr(dd, DCC_CFG_RESET,
6366 reg
6367 | (1ull << DCC_CFG_RESET_RESET_LCB_SHIFT)
6368 | (1ull << DCC_CFG_RESET_RESET_RX_FPE_SHIFT));
50e5dcbe 6369 (void)read_csr(dd, DCC_CFG_RESET); /* make sure the write completed */
77241056
MM		 6370 if (!abort) {
6371 udelay(1); /* must hold for the longer of 16cclks or 20ns */
6372 write_csr(dd, DCC_CFG_RESET, reg);
6373 write_csr(dd, DC_LCB_ERR_EN, dd->lcb_err_en);
6374 }
6375}
6376
6377/*
6378 * This routine should be called after the link has been transitioned to
6379 * OFFLINE (OFFLINE state has the side effect of putting the SerDes into
6380 * reset).
6381 *
6382 * The expectation is that the caller of this routine would have taken
6383 * care of properly transitioning the link into the correct state.
6384 */
6385static void dc_shutdown(struct hfi1_devdata *dd)
6386{
6387 unsigned long flags;
6388
6389 spin_lock_irqsave(&dd->dc8051_lock, flags);
6390 if (dd->dc_shutdown) {
6391 spin_unlock_irqrestore(&dd->dc8051_lock, flags);
6392 return;
6393 }
6394 dd->dc_shutdown = 1;
6395 spin_unlock_irqrestore(&dd->dc8051_lock, flags);
6396 /* Shutdown the LCB */
6397 lcb_shutdown(dd, 1);
6398 /* Going to OFFLINE would have causes the 8051 to put the
6399 * SerDes into reset already. Just need to shut down the 8051,
6400 * itself. */
6401 write_csr(dd, DC_DC8051_CFG_RST, 0x1);
6402}
6403
6404/* Calling this after the DC has been brought out of reset should not
6405 * do any damage. */
6406static void dc_start(struct hfi1_devdata *dd)
6407{
6408 unsigned long flags;
6409 int ret;
6410
6411 spin_lock_irqsave(&dd->dc8051_lock, flags);
6412 if (!dd->dc_shutdown)
6413 goto done;
6414 spin_unlock_irqrestore(&dd->dc8051_lock, flags);
6415 /* Take the 8051 out of reset */
6416 write_csr(dd, DC_DC8051_CFG_RST, 0ull);
6417 /* Wait until 8051 is ready */
6418 ret = wait_fm_ready(dd, TIMEOUT_8051_START);
6419 if (ret) {
6420 dd_dev_err(dd, "%s: timeout starting 8051 firmware\n",
6421 __func__);
6422 }
6423 /* Take away reset for LCB and RX FPE (set in lcb_shutdown). */
6424 write_csr(dd, DCC_CFG_RESET, 0x10);
6425 /* lcb_shutdown() with abort=1 does not restore these */
6426 write_csr(dd, DC_LCB_ERR_EN, dd->lcb_err_en);
6427 spin_lock_irqsave(&dd->dc8051_lock, flags);
6428 dd->dc_shutdown = 0;
6429done:
6430 spin_unlock_irqrestore(&dd->dc8051_lock, flags);
6431}
6432
6433/*
6434 * These LCB adjustments are for the Aurora SerDes core in the FPGA.
6435 */
6436static void adjust_lcb_for_fpga_serdes(struct hfi1_devdata *dd)
6437{
6438 u64 rx_radr, tx_radr;
6439 u32 version;
6440
6441 if (dd->icode != ICODE_FPGA_EMULATION)
6442 return;
6443
6444 /*
6445 * These LCB defaults on emulator _s are good, nothing to do here:
6446 * LCB_CFG_TX_FIFOS_RADR
6447 * LCB_CFG_RX_FIFOS_RADR
6448 * LCB_CFG_LN_DCLK
6449 * LCB_CFG_IGNORE_LOST_RCLK
6450 */
6451 if (is_emulator_s(dd))
6452 return;
6453 /* else this is _p */
6454
6455 version = emulator_rev(dd);
995deafa 6456 if (!is_ax(dd))
77241056
MM		 6457 version = 0x2d; /* all B0 use 0x2d or higher settings */
6458
6459 if (version <= 0x12) {
6460 /* release 0x12 and below */
6461
6462 /*
6463 * LCB_CFG_RX_FIFOS_RADR.RST_VAL = 0x9
6464 * LCB_CFG_RX_FIFOS_RADR.OK_TO_JUMP_VAL = 0x9
6465 * LCB_CFG_RX_FIFOS_RADR.DO_NOT_JUMP_VAL = 0xa
6466 */
6467 rx_radr =
6468 0xaull << DC_LCB_CFG_RX_FIFOS_RADR_DO_NOT_JUMP_VAL_SHIFT
6469 | 0x9ull << DC_LCB_CFG_RX_FIFOS_RADR_OK_TO_JUMP_VAL_SHIFT
6470 | 0x9ull << DC_LCB_CFG_RX_FIFOS_RADR_RST_VAL_SHIFT;
6471 /*
6472 * LCB_CFG_TX_FIFOS_RADR.ON_REINIT = 0 (default)
6473 * LCB_CFG_TX_FIFOS_RADR.RST_VAL = 6
6474 */
6475 tx_radr = 6ull << DC_LCB_CFG_TX_FIFOS_RADR_RST_VAL_SHIFT;
6476 } else if (version <= 0x18) {
6477 /* release 0x13 up to 0x18 */
6478 /* LCB_CFG_RX_FIFOS_RADR = 0x988 */
6479 rx_radr =
6480 0x9ull << DC_LCB_CFG_RX_FIFOS_RADR_DO_NOT_JUMP_VAL_SHIFT
6481 | 0x8ull << DC_LCB_CFG_RX_FIFOS_RADR_OK_TO_JUMP_VAL_SHIFT
6482 | 0x8ull << DC_LCB_CFG_RX_FIFOS_RADR_RST_VAL_SHIFT;
6483 tx_radr = 7ull << DC_LCB_CFG_TX_FIFOS_RADR_RST_VAL_SHIFT;
6484 } else if (version == 0x19) {
6485 /* release 0x19 */
6486 /* LCB_CFG_RX_FIFOS_RADR = 0xa99 */
6487 rx_radr =
6488 0xAull << DC_LCB_CFG_RX_FIFOS_RADR_DO_NOT_JUMP_VAL_SHIFT
6489 | 0x9ull << DC_LCB_CFG_RX_FIFOS_RADR_OK_TO_JUMP_VAL_SHIFT
6490 | 0x9ull << DC_LCB_CFG_RX_FIFOS_RADR_RST_VAL_SHIFT;
6491 tx_radr = 3ull << DC_LCB_CFG_TX_FIFOS_RADR_RST_VAL_SHIFT;
6492 } else if (version == 0x1a) {
6493 /* release 0x1a */
6494 /* LCB_CFG_RX_FIFOS_RADR = 0x988 */
6495 rx_radr =
6496 0x9ull << DC_LCB_CFG_RX_FIFOS_RADR_DO_NOT_JUMP_VAL_SHIFT
6497 | 0x8ull << DC_LCB_CFG_RX_FIFOS_RADR_OK_TO_JUMP_VAL_SHIFT
6498 | 0x8ull << DC_LCB_CFG_RX_FIFOS_RADR_RST_VAL_SHIFT;
6499 tx_radr = 7ull << DC_LCB_CFG_TX_FIFOS_RADR_RST_VAL_SHIFT;
6500 write_csr(dd, DC_LCB_CFG_LN_DCLK, 1ull);
6501 } else {
6502 /* release 0x1b and higher */
6503 /* LCB_CFG_RX_FIFOS_RADR = 0x877 */
6504 rx_radr =
6505 0x8ull << DC_LCB_CFG_RX_FIFOS_RADR_DO_NOT_JUMP_VAL_SHIFT
6506 | 0x7ull << DC_LCB_CFG_RX_FIFOS_RADR_OK_TO_JUMP_VAL_SHIFT
6507 | 0x7ull << DC_LCB_CFG_RX_FIFOS_RADR_RST_VAL_SHIFT;
6508 tx_radr = 3ull << DC_LCB_CFG_TX_FIFOS_RADR_RST_VAL_SHIFT;
6509 }
6510
6511 write_csr(dd, DC_LCB_CFG_RX_FIFOS_RADR, rx_radr);
6512 /* LCB_CFG_IGNORE_LOST_RCLK.EN = 1 */
6513 write_csr(dd, DC_LCB_CFG_IGNORE_LOST_RCLK,
6514 DC_LCB_CFG_IGNORE_LOST_RCLK_EN_SMASK);
6515 write_csr(dd, DC_LCB_CFG_TX_FIFOS_RADR, tx_radr);
6516}
6517
6518/*
6519 * Handle a SMA idle message
6520 *
6521 * This is a work-queue function outside of the interrupt.
6522 */
6523void handle_sma_message(struct work_struct *work)
6524{
6525 struct hfi1_pportdata *ppd = container_of(work, struct hfi1_pportdata,
6526 sma_message_work);
6527 struct hfi1_devdata *dd = ppd->dd;
6528 u64 msg;
6529 int ret;
6530
6531 /* msg is bytes 1-4 of the 40-bit idle message - the command code
6532 is stripped off */
6533 ret = read_idle_sma(dd, &msg);
6534 if (ret)
6535 return;
6536 dd_dev_info(dd, "%s: SMA message 0x%llx\n", __func__, msg);
6537 /*
6538 * React to the SMA message. Byte[1] (0 for us) is the command.
6539 */
6540 switch (msg & 0xff) {
6541 case SMA_IDLE_ARM:
6542 /*
6543 * See OPAv1 table 9-14 - HFI and External Switch Ports Key
6544 * State Transitions
6545 *
6546 * Only expected in INIT or ARMED, discard otherwise.
6547 */
6548 if (ppd->host_link_state & (HLS_UP_INIT | HLS_UP_ARMED))
6549 ppd->neighbor_normal = 1;
6550 break;
6551 case SMA_IDLE_ACTIVE:
6552 /*
6553 * See OPAv1 table 9-14 - HFI and External Switch Ports Key
6554 * State Transitions
6555 *
6556 * Can activate the node. Discard otherwise.
6557 */
6558 if (ppd->host_link_state == HLS_UP_ARMED
6559 && ppd->is_active_optimize_enabled) {
6560 ppd->neighbor_normal = 1;
6561 ret = set_link_state(ppd, HLS_UP_ACTIVE);
6562 if (ret)
6563 dd_dev_err(
6564 dd,
6565 "%s: received Active SMA idle message, couldn't set link to Active\n",
6566 __func__);
6567 }
6568 break;
6569 default:
6570 dd_dev_err(dd,
6571 "%s: received unexpected SMA idle message 0x%llx\n",
6572 __func__, msg);
6573 break;
6574 }
6575}
6576
6577static void adjust_rcvctrl(struct hfi1_devdata *dd, u64 add, u64 clear)
6578{
6579 u64 rcvctrl;
6580 unsigned long flags;
6581
6582 spin_lock_irqsave(&dd->rcvctrl_lock, flags);
6583 rcvctrl = read_csr(dd, RCV_CTRL);
6584 rcvctrl |= add;
6585 rcvctrl &= ~clear;
6586 write_csr(dd, RCV_CTRL, rcvctrl);
6587 spin_unlock_irqrestore(&dd->rcvctrl_lock, flags);
6588}
6589
6590static inline void add_rcvctrl(struct hfi1_devdata *dd, u64 add)
6591{
6592 adjust_rcvctrl(dd, add, 0);
6593}
6594
6595static inline void clear_rcvctrl(struct hfi1_devdata *dd, u64 clear)
6596{
6597 adjust_rcvctrl(dd, 0, clear);
6598}
6599
6600/*
6601 * Called from all interrupt handlers to start handling an SPC freeze.
6602 */
6603void start_freeze_handling(struct hfi1_pportdata *ppd, int flags)
6604{
6605 struct hfi1_devdata *dd = ppd->dd;
6606 struct send_context *sc;
6607 int i;
6608
6609 if (flags & FREEZE_SELF)
6610 write_csr(dd, CCE_CTRL, CCE_CTRL_SPC_FREEZE_SMASK);
6611
6612 /* enter frozen mode */
6613 dd->flags |= HFI1_FROZEN;
6614
6615 /* notify all SDMA engines that they are going into a freeze */
6616 sdma_freeze_notify(dd, !!(flags & FREEZE_LINK_DOWN));
6617
6618 /* do halt pre-handling on all enabled send contexts */
6619 for (i = 0; i < dd->num_send_contexts; i++) {
6620 sc = dd->send_contexts[i].sc;
6621 if (sc && (sc->flags & SCF_ENABLED))
6622 sc_stop(sc, SCF_FROZEN | SCF_HALTED);
6623 }
6624
6625 /* Send context are frozen. Notify user space */
6626 hfi1_set_uevent_bits(ppd, _HFI1_EVENT_FROZEN_BIT);
6627
6628 if (flags & FREEZE_ABORT) {
6629 dd_dev_err(dd,
6630 "Aborted freeze recovery. Please REBOOT system\n");
6631 return;
6632 }
6633 /* queue non-interrupt handler */
6634 queue_work(ppd->hfi1_wq, &ppd->freeze_work);
6635}
6636
6637/*
6638 * Wait until all 4 sub-blocks indicate that they have frozen or unfrozen,
6639 * depending on the "freeze" parameter.
6640 *
6641 * No need to return an error if it times out, our only option
6642 * is to proceed anyway.
6643 */
6644static void wait_for_freeze_status(struct hfi1_devdata *dd, int freeze)
6645{
6646 unsigned long timeout;
6647 u64 reg;
6648
6649 timeout = jiffies + msecs_to_jiffies(FREEZE_STATUS_TIMEOUT);
6650 while (1) {
6651 reg = read_csr(dd, CCE_STATUS);
6652 if (freeze) {
6653 /* waiting until all indicators are set */
6654 if ((reg & ALL_FROZE) == ALL_FROZE)
6655 return; /* all done */
6656 } else {
6657 /* waiting until all indicators are clear */
6658 if ((reg & ALL_FROZE) == 0)
6659 return; /* all done */
6660 }
6661
6662 if (time_after(jiffies, timeout)) {
6663 dd_dev_err(dd,
6664 "Time out waiting for SPC %sfreeze, bits 0x%llx, expecting 0x%llx, continuing",
6665 freeze ? "" : "un",
6666 reg & ALL_FROZE,
6667 freeze ? ALL_FROZE : 0ull);
6668 return;
6669 }
6670 usleep_range(80, 120);
6671 }
6672}
6673
6674/*
6675 * Do all freeze handling for the RXE block.
6676 */
6677static void rxe_freeze(struct hfi1_devdata *dd)
6678{
6679 int i;
6680
6681 /* disable port */
6682 clear_rcvctrl(dd, RCV_CTRL_RCV_PORT_ENABLE_SMASK);
6683
6684 /* disable all receive contexts */
6685 for (i = 0; i < dd->num_rcv_contexts; i++)
6686 hfi1_rcvctrl(dd, HFI1_RCVCTRL_CTXT_DIS, i);
6687}
6688
6689/*
6690 * Unfreeze handling for the RXE block - kernel contexts only.
6691 * This will also enable the port. User contexts will do unfreeze
6692 * handling on a per-context basis as they call into the driver.
6693 *
6694 */
6695static void rxe_kernel_unfreeze(struct hfi1_devdata *dd)
6696{
566c157c 6697 u32 rcvmask;
77241056
MM		 6698 int i;
6699
6700 /* enable all kernel contexts */
566c157c
MH		 6701 for (i = 0; i < dd->n_krcv_queues; i++) {
6702 rcvmask = HFI1_RCVCTRL_CTXT_ENB;
6703 /* HFI1_RCVCTRL_TAILUPD_[ENB|DIS] needs to be set explicitly */
6704 rcvmask |= HFI1_CAP_KGET_MASK(dd->rcd[i]->flags, DMA_RTAIL) ?
6705 HFI1_RCVCTRL_TAILUPD_ENB : HFI1_RCVCTRL_TAILUPD_DIS;
6706 hfi1_rcvctrl(dd, rcvmask, i);
6707 }
77241056
MM		 6708
6709 /* enable port */
6710 add_rcvctrl(dd, RCV_CTRL_RCV_PORT_ENABLE_SMASK);
6711}
6712
6713/*
6714 * Non-interrupt SPC freeze handling.
6715 *
6716 * This is a work-queue function outside of the triggering interrupt.
6717 */
6718void handle_freeze(struct work_struct *work)
6719{
6720 struct hfi1_pportdata *ppd = container_of(work, struct hfi1_pportdata,
6721 freeze_work);
6722 struct hfi1_devdata *dd = ppd->dd;
6723
6724 /* wait for freeze indicators on all affected blocks */
77241056
MM		 6725 wait_for_freeze_status(dd, 1);
6726
6727 /* SPC is now frozen */
6728
6729 /* do send PIO freeze steps */
6730 pio_freeze(dd);
6731
6732 /* do send DMA freeze steps */
6733 sdma_freeze(dd);
6734
6735 /* do send egress freeze steps - nothing to do */
6736
6737 /* do receive freeze steps */
6738 rxe_freeze(dd);
6739
6740 /*
6741 * Unfreeze the hardware - clear the freeze, wait for each
6742 * block's frozen bit to clear, then clear the frozen flag.
6743 */
6744 write_csr(dd, CCE_CTRL, CCE_CTRL_SPC_UNFREEZE_SMASK);
6745 wait_for_freeze_status(dd, 0);
6746
995deafa 6747 if (is_ax(dd)) {
77241056
MM		 6748 write_csr(dd, CCE_CTRL, CCE_CTRL_SPC_FREEZE_SMASK);
6749 wait_for_freeze_status(dd, 1);
6750 write_csr(dd, CCE_CTRL, CCE_CTRL_SPC_UNFREEZE_SMASK);
6751 wait_for_freeze_status(dd, 0);
6752 }
6753
6754 /* do send PIO unfreeze steps for kernel contexts */
6755 pio_kernel_unfreeze(dd);
6756
6757 /* do send DMA unfreeze steps */
6758 sdma_unfreeze(dd);
6759
6760 /* do send egress unfreeze steps - nothing to do */
6761
6762 /* do receive unfreeze steps for kernel contexts */
6763 rxe_kernel_unfreeze(dd);
6764
6765 /*
6766 * The unfreeze procedure touches global device registers when
6767 * it disables and re-enables RXE. Mark the device unfrozen
6768 * after all that is done so other parts of the driver waiting
6769 * for the device to unfreeze don't do things out of order.
6770 *
6771 * The above implies that the meaning of HFI1_FROZEN flag is
6772 * "Device has gone into freeze mode and freeze mode handling
6773 * is still in progress."
6774 *
6775 * The flag will be removed when freeze mode processing has
6776 * completed.
6777 */
6778 dd->flags &= ~HFI1_FROZEN;
6779 wake_up(&dd->event_queue);
6780
6781 /* no longer frozen */
77241056
MM		 6782}
6783
6784/*
6785 * Handle a link up interrupt from the 8051.
6786 *
6787 * This is a work-queue function outside of the interrupt.
6788 */
6789void handle_link_up(struct work_struct *work)
6790{
6791 struct hfi1_pportdata *ppd = container_of(work, struct hfi1_pportdata,
6792 link_up_work);
6793 set_link_state(ppd, HLS_UP_INIT);
6794
6795 /* cache the read of DC_LCB_STS_ROUND_TRIP_LTP_CNT */
6796 read_ltp_rtt(ppd->dd);
6797 /*
6798 * OPA specifies that certain counters are cleared on a transition
6799 * to link up, so do that.
6800 */
6801 clear_linkup_counters(ppd->dd);
6802 /*
6803 * And (re)set link up default values.
6804 */
6805 set_linkup_defaults(ppd);
6806
6807 /* enforce link speed enabled */
6808 if ((ppd->link_speed_active & ppd->link_speed_enabled) == 0) {
6809 /* oops - current speed is not enabled, bounce */
6810 dd_dev_err(ppd->dd,
6811 "Link speed active 0x%x is outside enabled 0x%x, downing link\n",
6812 ppd->link_speed_active, ppd->link_speed_enabled);
6813 set_link_down_reason(ppd, OPA_LINKDOWN_REASON_SPEED_POLICY, 0,
6814 OPA_LINKDOWN_REASON_SPEED_POLICY);
6815 set_link_state(ppd, HLS_DN_OFFLINE);
8ebd4cf1 6816 tune_serdes(ppd);
77241056
MM		 6817 start_link(ppd);
6818 }
6819}
6820
6821/* Several pieces of LNI information were cached for SMA in ppd.
6822 * Reset these on link down */
6823static void reset_neighbor_info(struct hfi1_pportdata *ppd)
6824{
6825 ppd->neighbor_guid = 0;
6826 ppd->neighbor_port_number = 0;
6827 ppd->neighbor_type = 0;
6828 ppd->neighbor_fm_security = 0;
6829}
6830
6831/*
6832 * Handle a link down interrupt from the 8051.
6833 *
6834 * This is a work-queue function outside of the interrupt.
6835 */
6836void handle_link_down(struct work_struct *work)
6837{
6838 u8 lcl_reason, neigh_reason = 0;
6839 struct hfi1_pportdata *ppd = container_of(work, struct hfi1_pportdata,
6840 link_down_work);
6841
8ebd4cf1
EH		 6842 if ((ppd->host_link_state &
6843 (HLS_DN_POLL | HLS_VERIFY_CAP | HLS_GOING_UP)) &&
6844 ppd->port_type == PORT_TYPE_FIXED)
6845 ppd->offline_disabled_reason =
6846 HFI1_ODR_MASK(OPA_LINKDOWN_REASON_NOT_INSTALLED);
6847
6848 /* Go offline first, then deal with reading/writing through 8051 */
77241056
MM		 6849 set_link_state(ppd, HLS_DN_OFFLINE);
6850
6851 lcl_reason = 0;
6852 read_planned_down_reason_code(ppd->dd, &neigh_reason);
6853
6854 /*
6855 * If no reason, assume peer-initiated but missed
6856 * LinkGoingDown idle flits.
6857 */
6858 if (neigh_reason == 0)
6859 lcl_reason = OPA_LINKDOWN_REASON_NEIGHBOR_UNKNOWN;
6860
6861 set_link_down_reason(ppd, lcl_reason, neigh_reason, 0);
6862
6863 reset_neighbor_info(ppd);
6864
6865 /* disable the port */
6866 clear_rcvctrl(ppd->dd, RCV_CTRL_RCV_PORT_ENABLE_SMASK);
6867
6868 /* If there is no cable attached, turn the DC off. Otherwise,
6869 * start the link bring up. */
8ebd4cf1 6870 if (!qsfp_mod_present(ppd)) {
77241056 6871 dc_shutdown(ppd->dd);
8ebd4cf1
EH		 6872 } else {
6873 tune_serdes(ppd);
77241056 6874 start_link(ppd);
8ebd4cf1 6875 }
77241056
MM		 6876}
6877
6878void handle_link_bounce(struct work_struct *work)
6879{
6880 struct hfi1_pportdata *ppd = container_of(work, struct hfi1_pportdata,
6881 link_bounce_work);
6882
6883 /*
6884 * Only do something if the link is currently up.
6885 */
6886 if (ppd->host_link_state & HLS_UP) {
6887 set_link_state(ppd, HLS_DN_OFFLINE);
8ebd4cf1 6888 tune_serdes(ppd);
77241056
MM		 6889 start_link(ppd);
6890 } else {
6891 dd_dev_info(ppd->dd, "%s: link not up (%s), nothing to do\n",
6892 __func__, link_state_name(ppd->host_link_state));
6893 }
6894}
6895
6896/*
6897 * Mask conversion: Capability exchange to Port LTP. The capability
6898 * exchange has an implicit 16b CRC that is mandatory.
6899 */
6900static int cap_to_port_ltp(int cap)
6901{
6902 int port_ltp = PORT_LTP_CRC_MODE_16; /* this mode is mandatory */
6903
6904 if (cap & CAP_CRC_14B)
6905 port_ltp |= PORT_LTP_CRC_MODE_14;
6906 if (cap & CAP_CRC_48B)
6907 port_ltp |= PORT_LTP_CRC_MODE_48;
6908 if (cap & CAP_CRC_12B_16B_PER_LANE)
6909 port_ltp |= PORT_LTP_CRC_MODE_PER_LANE;
6910
6911 return port_ltp;
6912}
6913
6914/*
6915 * Convert an OPA Port LTP mask to capability mask
6916 */
6917int port_ltp_to_cap(int port_ltp)
6918{
6919 int cap_mask = 0;
6920
6921 if (port_ltp & PORT_LTP_CRC_MODE_14)
6922 cap_mask |= CAP_CRC_14B;
6923 if (port_ltp & PORT_LTP_CRC_MODE_48)
6924 cap_mask |= CAP_CRC_48B;
6925 if (port_ltp & PORT_LTP_CRC_MODE_PER_LANE)
6926 cap_mask |= CAP_CRC_12B_16B_PER_LANE;
6927
6928 return cap_mask;
6929}
6930
6931/*
6932 * Convert a single DC LCB CRC mode to an OPA Port LTP mask.
6933 */
6934static int lcb_to_port_ltp(int lcb_crc)
6935{
6936 int port_ltp = 0;
6937
6938 if (lcb_crc == LCB_CRC_12B_16B_PER_LANE)
6939 port_ltp = PORT_LTP_CRC_MODE_PER_LANE;
6940 else if (lcb_crc == LCB_CRC_48B)
6941 port_ltp = PORT_LTP_CRC_MODE_48;
6942 else if (lcb_crc == LCB_CRC_14B)
6943 port_ltp = PORT_LTP_CRC_MODE_14;
6944 else
6945 port_ltp = PORT_LTP_CRC_MODE_16;
6946
6947 return port_ltp;
6948}
6949
6950/*
6951 * Our neighbor has indicated that we are allowed to act as a fabric
6952 * manager, so place the full management partition key in the second
6953 * (0-based) pkey array position (see OPAv1, section 20.2.2.6.8). Note
6954 * that we should already have the limited management partition key in
6955 * array element 1, and also that the port is not yet up when
6956 * add_full_mgmt_pkey() is invoked.
6957 */
6958static void add_full_mgmt_pkey(struct hfi1_pportdata *ppd)
6959{
6960 struct hfi1_devdata *dd = ppd->dd;
6961
8764522e
DL		 6962 /* Sanity check - ppd->pkeys[2] should be 0, or already initalized */
6963 if (!((ppd->pkeys[2] == 0) || (ppd->pkeys[2] == FULL_MGMT_P_KEY)))
6964 dd_dev_warn(dd, "%s pkey[2] already set to 0x%x, resetting it to 0x%x\n",
6965 __func__, ppd->pkeys[2], FULL_MGMT_P_KEY);
77241056
MM		 6966 ppd->pkeys[2] = FULL_MGMT_P_KEY;
6967 (void)hfi1_set_ib_cfg(ppd, HFI1_IB_CFG_PKEYS, 0);
6968}
6969
6970/*
6971 * Convert the given link width to the OPA link width bitmask.
6972 */
6973static u16 link_width_to_bits(struct hfi1_devdata *dd, u16 width)
6974{
6975 switch (width) {
6976 case 0:
6977 /*
6978 * Simulator and quick linkup do not set the width.
6979 * Just set it to 4x without complaint.
6980 */
6981 if (dd->icode == ICODE_FUNCTIONAL_SIMULATOR || quick_linkup)
6982 return OPA_LINK_WIDTH_4X;
6983 return 0; /* no lanes up */
6984 case 1: return OPA_LINK_WIDTH_1X;
6985 case 2: return OPA_LINK_WIDTH_2X;
6986 case 3: return OPA_LINK_WIDTH_3X;
6987 default:
6988 dd_dev_info(dd, "%s: invalid width %d, using 4\n",
6989 __func__, width);
6990 /* fall through */
6991 case 4: return OPA_LINK_WIDTH_4X;
6992 }
6993}
6994
6995/*
6996 * Do a population count on the bottom nibble.
6997 */
6998static const u8 bit_counts[16] = {
6999 0, 1, 1, 2, 1, 2, 2, 3, 1, 2, 2, 3, 2, 3, 3, 4
7000};
7001static inline u8 nibble_to_count(u8 nibble)
7002{
7003 return bit_counts[nibble & 0xf];
7004}
7005
7006/*
7007 * Read the active lane information from the 8051 registers and return
7008 * their widths.
7009 *
7010 * Active lane information is found in these 8051 registers:
7011 * enable_lane_tx
7012 * enable_lane_rx
7013 */
7014static void get_link_widths(struct hfi1_devdata *dd, u16 *tx_width,
7015 u16 *rx_width)
7016{
7017 u16 tx, rx;
7018 u8 enable_lane_rx;
7019 u8 enable_lane_tx;
7020 u8 tx_polarity_inversion;
7021 u8 rx_polarity_inversion;
7022 u8 max_rate;
7023
7024 /* read the active lanes */
7025 read_tx_settings(dd, &enable_lane_tx, &tx_polarity_inversion,
7026 &rx_polarity_inversion, &max_rate);
7027 read_local_lni(dd, &enable_lane_rx);
7028
7029 /* convert to counts */
7030 tx = nibble_to_count(enable_lane_tx);
7031 rx = nibble_to_count(enable_lane_rx);
7032
7033 /*
7034 * Set link_speed_active here, overriding what was set in
7035 * handle_verify_cap(). The ASIC 8051 firmware does not correctly
7036 * set the max_rate field in handle_verify_cap until v0.19.
7037 */
7038 if ((dd->icode == ICODE_RTL_SILICON)
7039 && (dd->dc8051_ver < dc8051_ver(0, 19))) {
7040 /* max_rate: 0 = 12.5G, 1 = 25G */
7041 switch (max_rate) {
7042 case 0:
7043 dd->pport[0].link_speed_active = OPA_LINK_SPEED_12_5G;
7044 break;
7045 default:
7046 dd_dev_err(dd,
7047 "%s: unexpected max rate %d, using 25Gb\n",
7048 __func__, (int)max_rate);
7049 /* fall through */
7050 case 1:
7051 dd->pport[0].link_speed_active = OPA_LINK_SPEED_25G;
7052 break;
7053 }
7054 }
7055
7056 dd_dev_info(dd,
7057 "Fabric active lanes (width): tx 0x%x (%d), rx 0x%x (%d)\n",
7058 enable_lane_tx, tx, enable_lane_rx, rx);
7059 *tx_width = link_width_to_bits(dd, tx);
7060 *rx_width = link_width_to_bits(dd, rx);
7061}
7062
7063/*
7064 * Read verify_cap_local_fm_link_width[1] to obtain the link widths.
7065 * Valid after the end of VerifyCap and during LinkUp. Does not change
7066 * after link up. I.e. look elsewhere for downgrade information.
7067 *
7068 * Bits are:
7069 * + bits [7:4] contain the number of active transmitters
7070 * + bits [3:0] contain the number of active receivers
7071 * These are numbers 1 through 4 and can be different values if the
7072 * link is asymmetric.
7073 *
7074 * verify_cap_local_fm_link_width[0] retains its original value.
7075 */
7076static void get_linkup_widths(struct hfi1_devdata *dd, u16 *tx_width,
7077 u16 *rx_width)
7078{
7079 u16 widths, tx, rx;
7080 u8 misc_bits, local_flags;
7081 u16 active_tx, active_rx;
7082
7083 read_vc_local_link_width(dd, &misc_bits, &local_flags, &widths);
7084 tx = widths >> 12;
7085 rx = (widths >> 8) & 0xf;
7086
7087 *tx_width = link_width_to_bits(dd, tx);
7088 *rx_width = link_width_to_bits(dd, rx);
7089
7090 /* print the active widths */
7091 get_link_widths(dd, &active_tx, &active_rx);
7092}
7093
7094/*
7095 * Set ppd->link_width_active and ppd->link_width_downgrade_active using
7096 * hardware information when the link first comes up.
7097 *
7098 * The link width is not available until after VerifyCap.AllFramesReceived
7099 * (the trigger for handle_verify_cap), so this is outside that routine
7100 * and should be called when the 8051 signals linkup.
7101 */
7102void get_linkup_link_widths(struct hfi1_pportdata *ppd)
7103{
7104 u16 tx_width, rx_width;
7105
7106 /* get end-of-LNI link widths */
7107 get_linkup_widths(ppd->dd, &tx_width, &rx_width);
7108
7109 /* use tx_width as the link is supposed to be symmetric on link up */
7110 ppd->link_width_active = tx_width;
7111 /* link width downgrade active (LWD.A) starts out matching LW.A */
7112 ppd->link_width_downgrade_tx_active = ppd->link_width_active;
7113 ppd->link_width_downgrade_rx_active = ppd->link_width_active;
7114 /* per OPA spec, on link up LWD.E resets to LWD.S */
7115 ppd->link_width_downgrade_enabled = ppd->link_width_downgrade_supported;
7116 /* cache the active egress rate (units {10^6 bits/sec]) */
7117 ppd->current_egress_rate = active_egress_rate(ppd);
7118}
7119
7120/*
7121 * Handle a verify capabilities interrupt from the 8051.
7122 *
7123 * This is a work-queue function outside of the interrupt.
7124 */
7125void handle_verify_cap(struct work_struct *work)
7126{
7127 struct hfi1_pportdata *ppd = container_of(work, struct hfi1_pportdata,
7128 link_vc_work);
7129 struct hfi1_devdata *dd = ppd->dd;
7130 u64 reg;
7131 u8 power_management;
7132 u8 continious;
7133 u8 vcu;
7134 u8 vau;
7135 u8 z;
7136 u16 vl15buf;
7137 u16 link_widths;
7138 u16 crc_mask;
7139 u16 crc_val;
7140 u16 device_id;
7141 u16 active_tx, active_rx;
7142 u8 partner_supported_crc;
7143 u8 remote_tx_rate;
7144 u8 device_rev;
7145
7146 set_link_state(ppd, HLS_VERIFY_CAP);
7147
7148 lcb_shutdown(dd, 0);
7149 adjust_lcb_for_fpga_serdes(dd);
7150
7151 /*
7152 * These are now valid:
7153 * remote VerifyCap fields in the general LNI config
7154 * CSR DC8051_STS_REMOTE_GUID
7155 * CSR DC8051_STS_REMOTE_NODE_TYPE
7156 * CSR DC8051_STS_REMOTE_FM_SECURITY
7157 * CSR DC8051_STS_REMOTE_PORT_NO
7158 */
7159
7160 read_vc_remote_phy(dd, &power_management, &continious);
7161 read_vc_remote_fabric(
7162 dd,
7163 &vau,
7164 &z,
7165 &vcu,
7166 &vl15buf,
7167 &partner_supported_crc);
7168 read_vc_remote_link_width(dd, &remote_tx_rate, &link_widths);
7169 read_remote_device_id(dd, &device_id, &device_rev);
7170 /*
7171 * And the 'MgmtAllowed' information, which is exchanged during
7172 * LNI, is also be available at this point.
7173 */
7174 read_mgmt_allowed(dd, &ppd->mgmt_allowed);
7175 /* print the active widths */
7176 get_link_widths(dd, &active_tx, &active_rx);
7177 dd_dev_info(dd,
7178 "Peer PHY: power management 0x%x, continuous updates 0x%x\n",
7179 (int)power_management, (int)continious);
7180 dd_dev_info(dd,
7181 "Peer Fabric: vAU %d, Z %d, vCU %d, vl15 credits 0x%x, CRC sizes 0x%x\n",
7182 (int)vau,
7183 (int)z,
7184 (int)vcu,
7185 (int)vl15buf,
7186 (int)partner_supported_crc);
7187 dd_dev_info(dd, "Peer Link Width: tx rate 0x%x, widths 0x%x\n",
7188 (u32)remote_tx_rate, (u32)link_widths);
7189 dd_dev_info(dd, "Peer Device ID: 0x%04x, Revision 0x%02x\n",
7190 (u32)device_id, (u32)device_rev);
7191 /*
7192 * The peer vAU value just read is the peer receiver value. HFI does
7193 * not support a transmit vAU of 0 (AU == 8). We advertised that
7194 * with Z=1 in the fabric capabilities sent to the peer. The peer
7195 * will see our Z=1, and, if it advertised a vAU of 0, will move its
7196 * receive to vAU of 1 (AU == 16). Do the same here. We do not care
7197 * about the peer Z value - our sent vAU is 3 (hardwired) and is not
7198 * subject to the Z value exception.
7199 */
7200 if (vau == 0)
7201 vau = 1;
7202 set_up_vl15(dd, vau, vl15buf);
7203
7204 /* set up the LCB CRC mode */
7205 crc_mask = ppd->port_crc_mode_enabled & partner_supported_crc;
7206
7207 /* order is important: use the lowest bit in common */
7208 if (crc_mask & CAP_CRC_14B)
7209 crc_val = LCB_CRC_14B;
7210 else if (crc_mask & CAP_CRC_48B)
7211 crc_val = LCB_CRC_48B;
7212 else if (crc_mask & CAP_CRC_12B_16B_PER_LANE)
7213 crc_val = LCB_CRC_12B_16B_PER_LANE;
7214 else
7215 crc_val = LCB_CRC_16B;
7216
7217 dd_dev_info(dd, "Final LCB CRC mode: %d\n", (int)crc_val);
7218 write_csr(dd, DC_LCB_CFG_CRC_MODE,
7219 (u64)crc_val << DC_LCB_CFG_CRC_MODE_TX_VAL_SHIFT);
7220
7221 /* set (14b only) or clear sideband credit */
7222 reg = read_csr(dd, SEND_CM_CTRL);
7223 if (crc_val == LCB_CRC_14B && crc_14b_sideband) {
7224 write_csr(dd, SEND_CM_CTRL,
7225 reg | SEND_CM_CTRL_FORCE_CREDIT_MODE_SMASK);
7226 } else {
7227 write_csr(dd, SEND_CM_CTRL,
7228 reg & ~SEND_CM_CTRL_FORCE_CREDIT_MODE_SMASK);
7229 }
7230
7231 ppd->link_speed_active = 0; /* invalid value */
7232 if (dd->dc8051_ver < dc8051_ver(0, 20)) {
7233 /* remote_tx_rate: 0 = 12.5G, 1 = 25G */
7234 switch (remote_tx_rate) {
7235 case 0:
7236 ppd->link_speed_active = OPA_LINK_SPEED_12_5G;
7237 break;
7238 case 1:
7239 ppd->link_speed_active = OPA_LINK_SPEED_25G;
7240 break;
7241 }
7242 } else {
7243 /* actual rate is highest bit of the ANDed rates */
7244 u8 rate = remote_tx_rate & ppd->local_tx_rate;
7245
7246 if (rate & 2)
7247 ppd->link_speed_active = OPA_LINK_SPEED_25G;
7248 else if (rate & 1)
7249 ppd->link_speed_active = OPA_LINK_SPEED_12_5G;
7250 }
7251 if (ppd->link_speed_active == 0) {
7252 dd_dev_err(dd, "%s: unexpected remote tx rate %d, using 25Gb\n",
7253 __func__, (int)remote_tx_rate);
7254 ppd->link_speed_active = OPA_LINK_SPEED_25G;
7255 }
7256
7257 /*
7258 * Cache the values of the supported, enabled, and active
7259 * LTP CRC modes to return in 'portinfo' queries. But the bit
7260 * flags that are returned in the portinfo query differ from
7261 * what's in the link_crc_mask, crc_sizes, and crc_val
7262 * variables. Convert these here.
7263 */
7264 ppd->port_ltp_crc_mode = cap_to_port_ltp(link_crc_mask) << 8;
7265 /* supported crc modes */
7266 ppd->port_ltp_crc_mode |=
7267 cap_to_port_ltp(ppd->port_crc_mode_enabled) << 4;
7268 /* enabled crc modes */
7269 ppd->port_ltp_crc_mode |= lcb_to_port_ltp(crc_val);
7270 /* active crc mode */
7271
7272 /* set up the remote credit return table */
7273 assign_remote_cm_au_table(dd, vcu);
7274
7275 /*
7276 * The LCB is reset on entry to handle_verify_cap(), so this must
7277 * be applied on every link up.
7278 *
7279 * Adjust LCB error kill enable to kill the link if
7280 * these RBUF errors are seen:
7281 * REPLAY_BUF_MBE_SMASK
7282 * FLIT_INPUT_BUF_MBE_SMASK
7283 */
995deafa 7284 if (is_ax(dd)) { /* fixed in B0 */
77241056
MM		 7285 reg = read_csr(dd, DC_LCB_CFG_LINK_KILL_EN);
7286 reg |= DC_LCB_CFG_LINK_KILL_EN_REPLAY_BUF_MBE_SMASK
7287 | DC_LCB_CFG_LINK_KILL_EN_FLIT_INPUT_BUF_MBE_SMASK;
7288 write_csr(dd, DC_LCB_CFG_LINK_KILL_EN, reg);
7289 }
7290
7291 /* pull LCB fifos out of reset - all fifo clocks must be stable */
7292 write_csr(dd, DC_LCB_CFG_TX_FIFOS_RESET, 0);
7293
7294 /* give 8051 access to the LCB CSRs */
7295 write_csr(dd, DC_LCB_ERR_EN, 0); /* mask LCB errors */
7296 set_8051_lcb_access(dd);
7297
7298 ppd->neighbor_guid =
7299 read_csr(dd, DC_DC8051_STS_REMOTE_GUID);
7300 ppd->neighbor_port_number = read_csr(dd, DC_DC8051_STS_REMOTE_PORT_NO) &
7301 DC_DC8051_STS_REMOTE_PORT_NO_VAL_SMASK;
7302 ppd->neighbor_type =
7303 read_csr(dd, DC_DC8051_STS_REMOTE_NODE_TYPE) &
7304 DC_DC8051_STS_REMOTE_NODE_TYPE_VAL_MASK;
7305 ppd->neighbor_fm_security =
7306 read_csr(dd, DC_DC8051_STS_REMOTE_FM_SECURITY) &
7307 DC_DC8051_STS_LOCAL_FM_SECURITY_DISABLED_MASK;
7308 dd_dev_info(dd,
7309 "Neighbor Guid: %llx Neighbor type %d MgmtAllowed %d FM security bypass %d\n",
7310 ppd->neighbor_guid, ppd->neighbor_type,
7311 ppd->mgmt_allowed, ppd->neighbor_fm_security);
7312 if (ppd->mgmt_allowed)
7313 add_full_mgmt_pkey(ppd);
7314
7315 /* tell the 8051 to go to LinkUp */
7316 set_link_state(ppd, HLS_GOING_UP);
7317}
7318
7319/*
7320 * Apply the link width downgrade enabled policy against the current active
7321 * link widths.
7322 *
7323 * Called when the enabled policy changes or the active link widths change.
7324 */
7325void apply_link_downgrade_policy(struct hfi1_pportdata *ppd, int refresh_widths)
7326{
77241056 7327 int do_bounce = 0;
323fd785
DL		 7328 int tries;
7329 u16 lwde;
77241056
MM		 7330 u16 tx, rx;
7331
323fd785
DL		 7332 /* use the hls lock to avoid a race with actual link up */
7333 tries = 0;
7334retry:
77241056
MM		 7335 mutex_lock(&ppd->hls_lock);
7336 /* only apply if the link is up */
323fd785
DL		 7337 if (!(ppd->host_link_state & HLS_UP)) {
7338 /* still going up..wait and retry */
7339 if (ppd->host_link_state & HLS_GOING_UP) {
7340 if (++tries < 1000) {
7341 mutex_unlock(&ppd->hls_lock);
7342 usleep_range(100, 120); /* arbitrary */
7343 goto retry;
7344 }
7345 dd_dev_err(ppd->dd,
7346 "%s: giving up waiting for link state change\n",
7347 __func__);
7348 }
7349 goto done;
7350 }
7351
7352 lwde = ppd->link_width_downgrade_enabled;
77241056
MM		 7353
7354 if (refresh_widths) {
7355 get_link_widths(ppd->dd, &tx, &rx);
7356 ppd->link_width_downgrade_tx_active = tx;
7357 ppd->link_width_downgrade_rx_active = rx;
7358 }
7359
7360 if (lwde == 0) {
7361 /* downgrade is disabled */
7362
7363 /* bounce if not at starting active width */
7364 if ((ppd->link_width_active !=
7365 ppd->link_width_downgrade_tx_active)
7366 || (ppd->link_width_active !=
7367 ppd->link_width_downgrade_rx_active)) {
7368 dd_dev_err(ppd->dd,
7369 "Link downgrade is disabled and link has downgraded, downing link\n");
7370 dd_dev_err(ppd->dd,
7371 " original 0x%x, tx active 0x%x, rx active 0x%x\n",
7372 ppd->link_width_active,
7373 ppd->link_width_downgrade_tx_active,
7374 ppd->link_width_downgrade_rx_active);
7375 do_bounce = 1;
7376 }
7377 } else if ((lwde & ppd->link_width_downgrade_tx_active) == 0
7378 || (lwde & ppd->link_width_downgrade_rx_active) == 0) {
7379 /* Tx or Rx is outside the enabled policy */
7380 dd_dev_err(ppd->dd,
7381 "Link is outside of downgrade allowed, downing link\n");
7382 dd_dev_err(ppd->dd,
7383 " enabled 0x%x, tx active 0x%x, rx active 0x%x\n",
7384 lwde,
7385 ppd->link_width_downgrade_tx_active,
7386 ppd->link_width_downgrade_rx_active);
7387 do_bounce = 1;
7388 }
7389
323fd785
DL		 7390done:
7391 mutex_unlock(&ppd->hls_lock);
7392
77241056
MM		 7393 if (do_bounce) {
7394 set_link_down_reason(ppd, OPA_LINKDOWN_REASON_WIDTH_POLICY, 0,
7395 OPA_LINKDOWN_REASON_WIDTH_POLICY);
7396 set_link_state(ppd, HLS_DN_OFFLINE);
8ebd4cf1 7397 tune_serdes(ppd);
77241056
MM		 7398 start_link(ppd);
7399 }
7400}
7401
7402/*
7403 * Handle a link downgrade interrupt from the 8051.
7404 *
7405 * This is a work-queue function outside of the interrupt.
7406 */
7407void handle_link_downgrade(struct work_struct *work)
7408{
7409 struct hfi1_pportdata *ppd = container_of(work, struct hfi1_pportdata,
7410 link_downgrade_work);
7411
7412 dd_dev_info(ppd->dd, "8051: Link width downgrade\n");
7413 apply_link_downgrade_policy(ppd, 1);
7414}
7415
7416static char *dcc_err_string(char *buf, int buf_len, u64 flags)
7417{
7418 return flag_string(buf, buf_len, flags, dcc_err_flags,
7419 ARRAY_SIZE(dcc_err_flags));
7420}
7421
7422static char *lcb_err_string(char *buf, int buf_len, u64 flags)
7423{
7424 return flag_string(buf, buf_len, flags, lcb_err_flags,
7425 ARRAY_SIZE(lcb_err_flags));
7426}
7427
7428static char *dc8051_err_string(char *buf, int buf_len, u64 flags)
7429{
7430 return flag_string(buf, buf_len, flags, dc8051_err_flags,
7431 ARRAY_SIZE(dc8051_err_flags));
7432}
7433
7434static char *dc8051_info_err_string(char *buf, int buf_len, u64 flags)
7435{
7436 return flag_string(buf, buf_len, flags, dc8051_info_err_flags,
7437 ARRAY_SIZE(dc8051_info_err_flags));
7438}
7439
7440static char *dc8051_info_host_msg_string(char *buf, int buf_len, u64 flags)
7441{
7442 return flag_string(buf, buf_len, flags, dc8051_info_host_msg_flags,
7443 ARRAY_SIZE(dc8051_info_host_msg_flags));
7444}
7445
7446static void handle_8051_interrupt(struct hfi1_devdata *dd, u32 unused, u64 reg)
7447{
7448 struct hfi1_pportdata *ppd = dd->pport;
7449 u64 info, err, host_msg;
7450 int queue_link_down = 0;
7451 char buf[96];
7452
7453 /* look at the flags */
7454 if (reg & DC_DC8051_ERR_FLG_SET_BY_8051_SMASK) {
7455 /* 8051 information set by firmware */
7456 /* read DC8051_DBG_ERR_INFO_SET_BY_8051 for details */
7457 info = read_csr(dd, DC_DC8051_DBG_ERR_INFO_SET_BY_8051);
7458 err = (info >> DC_DC8051_DBG_ERR_INFO_SET_BY_8051_ERROR_SHIFT)
7459 & DC_DC8051_DBG_ERR_INFO_SET_BY_8051_ERROR_MASK;
7460 host_msg = (info >>
7461 DC_DC8051_DBG_ERR_INFO_SET_BY_8051_HOST_MSG_SHIFT)
7462 & DC_DC8051_DBG_ERR_INFO_SET_BY_8051_HOST_MSG_MASK;
7463
7464 /*
7465 * Handle error flags.
7466 */
7467 if (err & FAILED_LNI) {
7468 /*
7469 * LNI error indications are cleared by the 8051
7470 * only when starting polling. Only pay attention
7471 * to them when in the states that occur during
7472 * LNI.
7473 */
7474 if (ppd->host_link_state
7475 & (HLS_DN_POLL | HLS_VERIFY_CAP | HLS_GOING_UP)) {
7476 queue_link_down = 1;
7477 dd_dev_info(dd, "Link error: %s\n",
7478 dc8051_info_err_string(buf,
7479 sizeof(buf),
7480 err & FAILED_LNI));
7481 }
7482 err &= ~(u64)FAILED_LNI;
7483 }
6d014530
DL		 7484 /* unknown frames can happen durning LNI, just count */
7485 if (err & UNKNOWN_FRAME) {
7486 ppd->unknown_frame_count++;
7487 err &= ~(u64)UNKNOWN_FRAME;
7488 }
77241056
MM		 7489 if (err) {
7490 /* report remaining errors, but do not do anything */
7491 dd_dev_err(dd, "8051 info error: %s\n",
7492 dc8051_info_err_string(buf, sizeof(buf), err));
7493 }
7494
7495 /*
7496 * Handle host message flags.
7497 */
7498 if (host_msg & HOST_REQ_DONE) {
7499 /*
7500 * Presently, the driver does a busy wait for
7501 * host requests to complete. This is only an
7502 * informational message.
7503 * NOTE: The 8051 clears the host message
7504 * information *on the next 8051 command*.
7505 * Therefore, when linkup is achieved,
7506 * this flag will still be set.
7507 */
7508 host_msg &= ~(u64)HOST_REQ_DONE;
7509 }
7510 if (host_msg & BC_SMA_MSG) {
7511 queue_work(ppd->hfi1_wq, &ppd->sma_message_work);
7512 host_msg &= ~(u64)BC_SMA_MSG;
7513 }
7514 if (host_msg & LINKUP_ACHIEVED) {
7515 dd_dev_info(dd, "8051: Link up\n");
7516 queue_work(ppd->hfi1_wq, &ppd->link_up_work);
7517 host_msg &= ~(u64)LINKUP_ACHIEVED;
7518 }
7519 if (host_msg & EXT_DEVICE_CFG_REQ) {
cbac386a 7520 queue_work(ppd->hfi1_wq, &ppd->dc_host_req_work);
77241056
MM		 7521 host_msg &= ~(u64)EXT_DEVICE_CFG_REQ;
7522 }
7523 if (host_msg & VERIFY_CAP_FRAME) {
7524 queue_work(ppd->hfi1_wq, &ppd->link_vc_work);
7525 host_msg &= ~(u64)VERIFY_CAP_FRAME;
7526 }
7527 if (host_msg & LINK_GOING_DOWN) {
7528 const char *extra = "";
7529 /* no downgrade action needed if going down */
7530 if (host_msg & LINK_WIDTH_DOWNGRADED) {
7531 host_msg &= ~(u64)LINK_WIDTH_DOWNGRADED;
7532 extra = " (ignoring downgrade)";
7533 }
7534 dd_dev_info(dd, "8051: Link down%s\n", extra);
7535 queue_link_down = 1;
7536 host_msg &= ~(u64)LINK_GOING_DOWN;
7537 }
7538 if (host_msg & LINK_WIDTH_DOWNGRADED) {
7539 queue_work(ppd->hfi1_wq, &ppd->link_downgrade_work);
7540 host_msg &= ~(u64)LINK_WIDTH_DOWNGRADED;
7541 }
7542 if (host_msg) {
7543 /* report remaining messages, but do not do anything */
7544 dd_dev_info(dd, "8051 info host message: %s\n",
7545 dc8051_info_host_msg_string(buf, sizeof(buf),
7546 host_msg));
7547 }
7548
7549 reg &= ~DC_DC8051_ERR_FLG_SET_BY_8051_SMASK;
7550 }
7551 if (reg & DC_DC8051_ERR_FLG_LOST_8051_HEART_BEAT_SMASK) {
7552 /*
7553 * Lost the 8051 heartbeat. If this happens, we
7554 * receive constant interrupts about it. Disable
7555 * the interrupt after the first.
7556 */
7557 dd_dev_err(dd, "Lost 8051 heartbeat\n");
7558 write_csr(dd, DC_DC8051_ERR_EN,
7559 read_csr(dd, DC_DC8051_ERR_EN)
7560 & ~DC_DC8051_ERR_EN_LOST_8051_HEART_BEAT_SMASK);
7561
7562 reg &= ~DC_DC8051_ERR_FLG_LOST_8051_HEART_BEAT_SMASK;
7563 }
7564 if (reg) {
7565 /* report the error, but do not do anything */
7566 dd_dev_err(dd, "8051 error: %s\n",
7567 dc8051_err_string(buf, sizeof(buf), reg));
7568 }
7569
7570 if (queue_link_down) {
7571 /* if the link is already going down or disabled, do not
7572 * queue another */
7573 if ((ppd->host_link_state
8638b77f 7574 & (HLS_GOING_OFFLINE | HLS_LINK_COOLDOWN))
77241056
MM		 7575 || ppd->link_enabled == 0) {
7576 dd_dev_info(dd, "%s: not queuing link down\n",
7577 __func__);
7578 } else {
7579 queue_work(ppd->hfi1_wq, &ppd->link_down_work);
7580 }
7581 }
7582}
7583
7584static const char * const fm_config_txt[] = {
7585[0] =
7586 "BadHeadDist: Distance violation between two head flits",
7587[1] =
7588 "BadTailDist: Distance violation between two tail flits",
7589[2] =
7590 "BadCtrlDist: Distance violation between two credit control flits",
7591[3] =
7592 "BadCrdAck: Credits return for unsupported VL",
7593[4] =
7594 "UnsupportedVLMarker: Received VL Marker",
7595[5] =
7596 "BadPreempt: Exceeded the preemption nesting level",
7597[6] =
7598 "BadControlFlit: Received unsupported control flit",
7599/* no 7 */
7600[8] =
7601 "UnsupportedVLMarker: Received VL Marker for unconfigured or disabled VL",
7602};
7603
7604static const char * const port_rcv_txt[] = {
7605[1] =
7606 "BadPktLen: Illegal PktLen",
7607[2] =
7608 "PktLenTooLong: Packet longer than PktLen",
7609[3] =
7610 "PktLenTooShort: Packet shorter than PktLen",
7611[4] =
7612 "BadSLID: Illegal SLID (0, using multicast as SLID, does not include security validation of SLID)",
7613[5] =
7614 "BadDLID: Illegal DLID (0, doesn't match HFI)",
7615[6] =
7616 "BadL2: Illegal L2 opcode",
7617[7] =
7618 "BadSC: Unsupported SC",
7619[9] =
7620 "BadRC: Illegal RC",
7621[11] =
7622 "PreemptError: Preempting with same VL",
7623[12] =
7624 "PreemptVL15: Preempting a VL15 packet",
7625};
7626
7627#define OPA_LDR_FMCONFIG_OFFSET 16
7628#define OPA_LDR_PORTRCV_OFFSET 0
7629static void handle_dcc_err(struct hfi1_devdata *dd, u32 unused, u64 reg)
7630{
7631 u64 info, hdr0, hdr1;
7632 const char *extra;
7633 char buf[96];
7634 struct hfi1_pportdata *ppd = dd->pport;
7635 u8 lcl_reason = 0;
7636 int do_bounce = 0;
7637
7638 if (reg & DCC_ERR_FLG_UNCORRECTABLE_ERR_SMASK) {
7639 if (!(dd->err_info_uncorrectable & OPA_EI_STATUS_SMASK)) {
7640 info = read_csr(dd, DCC_ERR_INFO_UNCORRECTABLE);
7641 dd->err_info_uncorrectable = info & OPA_EI_CODE_SMASK;
7642 /* set status bit */
7643 dd->err_info_uncorrectable |= OPA_EI_STATUS_SMASK;
7644 }
7645 reg &= ~DCC_ERR_FLG_UNCORRECTABLE_ERR_SMASK;
7646 }
7647
7648 if (reg & DCC_ERR_FLG_LINK_ERR_SMASK) {
7649 struct hfi1_pportdata *ppd = dd->pport;
7650 /* this counter saturates at (2^32) - 1 */
7651 if (ppd->link_downed < (u32)UINT_MAX)
7652 ppd->link_downed++;
7653 reg &= ~DCC_ERR_FLG_LINK_ERR_SMASK;
7654 }
7655
7656 if (reg & DCC_ERR_FLG_FMCONFIG_ERR_SMASK) {
7657 u8 reason_valid = 1;
7658
7659 info = read_csr(dd, DCC_ERR_INFO_FMCONFIG);
7660 if (!(dd->err_info_fmconfig & OPA_EI_STATUS_SMASK)) {
7661 dd->err_info_fmconfig = info & OPA_EI_CODE_SMASK;
7662 /* set status bit */
7663 dd->err_info_fmconfig |= OPA_EI_STATUS_SMASK;
7664 }
7665 switch (info) {
7666 case 0:
7667 case 1:
7668 case 2:
7669 case 3:
7670 case 4:
7671 case 5:
7672 case 6:
7673 extra = fm_config_txt[info];
7674 break;
7675 case 8:
7676 extra = fm_config_txt[info];
7677 if (ppd->port_error_action &
7678 OPA_PI_MASK_FM_CFG_UNSUPPORTED_VL_MARKER) {
7679 do_bounce = 1;
7680 /*
7681 * lcl_reason cannot be derived from info
7682 * for this error
7683 */
7684 lcl_reason =
7685 OPA_LINKDOWN_REASON_UNSUPPORTED_VL_MARKER;
7686 }
7687 break;
7688 default:
7689 reason_valid = 0;
7690 snprintf(buf, sizeof(buf), "reserved%lld", info);
7691 extra = buf;
7692 break;
7693 }
7694
7695 if (reason_valid && !do_bounce) {
7696 do_bounce = ppd->port_error_action &
7697 (1 << (OPA_LDR_FMCONFIG_OFFSET + info));
7698 lcl_reason = info + OPA_LINKDOWN_REASON_BAD_HEAD_DIST;
7699 }
7700
7701 /* just report this */
7702 dd_dev_info(dd, "DCC Error: fmconfig error: %s\n", extra);
7703 reg &= ~DCC_ERR_FLG_FMCONFIG_ERR_SMASK;
7704 }
7705
7706 if (reg & DCC_ERR_FLG_RCVPORT_ERR_SMASK) {
7707 u8 reason_valid = 1;
7708
7709 info = read_csr(dd, DCC_ERR_INFO_PORTRCV);
7710 hdr0 = read_csr(dd, DCC_ERR_INFO_PORTRCV_HDR0);
7711 hdr1 = read_csr(dd, DCC_ERR_INFO_PORTRCV_HDR1);
7712 if (!(dd->err_info_rcvport.status_and_code &
7713 OPA_EI_STATUS_SMASK)) {
7714 dd->err_info_rcvport.status_and_code =
7715 info & OPA_EI_CODE_SMASK;
7716 /* set status bit */
7717 dd->err_info_rcvport.status_and_code |=
7718 OPA_EI_STATUS_SMASK;
7719 /* save first 2 flits in the packet that caused
7720 * the error */
7721 dd->err_info_rcvport.packet_flit1 = hdr0;
7722 dd->err_info_rcvport.packet_flit2 = hdr1;
7723 }
7724 switch (info) {
7725 case 1:
7726 case 2:
7727 case 3:
7728 case 4:
7729 case 5:
7730 case 6:
7731 case 7:
7732 case 9:
7733 case 11:
7734 case 12:
7735 extra = port_rcv_txt[info];
7736 break;
7737 default:
7738 reason_valid = 0;
7739 snprintf(buf, sizeof(buf), "reserved%lld", info);
7740 extra = buf;
7741 break;
7742 }
7743
7744 if (reason_valid && !do_bounce) {
7745 do_bounce = ppd->port_error_action &
7746 (1 << (OPA_LDR_PORTRCV_OFFSET + info));
7747 lcl_reason = info + OPA_LINKDOWN_REASON_RCV_ERROR_0;
7748 }
7749
7750 /* just report this */
7751 dd_dev_info(dd, "DCC Error: PortRcv error: %s\n", extra);
7752 dd_dev_info(dd, " hdr0 0x%llx, hdr1 0x%llx\n",
7753 hdr0, hdr1);
7754
7755 reg &= ~DCC_ERR_FLG_RCVPORT_ERR_SMASK;
7756 }
7757
7758 if (reg & DCC_ERR_FLG_EN_CSR_ACCESS_BLOCKED_UC_SMASK) {
7759 /* informative only */
7760 dd_dev_info(dd, "8051 access to LCB blocked\n");
7761 reg &= ~DCC_ERR_FLG_EN_CSR_ACCESS_BLOCKED_UC_SMASK;
7762 }
7763 if (reg & DCC_ERR_FLG_EN_CSR_ACCESS_BLOCKED_HOST_SMASK) {
7764 /* informative only */
7765 dd_dev_info(dd, "host access to LCB blocked\n");
7766 reg &= ~DCC_ERR_FLG_EN_CSR_ACCESS_BLOCKED_HOST_SMASK;
7767 }
7768
7769 /* report any remaining errors */
7770 if (reg)
7771 dd_dev_info(dd, "DCC Error: %s\n",
7772 dcc_err_string(buf, sizeof(buf), reg));
7773
7774 if (lcl_reason == 0)
7775 lcl_reason = OPA_LINKDOWN_REASON_UNKNOWN;
7776
7777 if (do_bounce) {
7778 dd_dev_info(dd, "%s: PortErrorAction bounce\n", __func__);
7779 set_link_down_reason(ppd, lcl_reason, 0, lcl_reason);
7780 queue_work(ppd->hfi1_wq, &ppd->link_bounce_work);
7781 }
7782}
7783
7784static void handle_lcb_err(struct hfi1_devdata *dd, u32 unused, u64 reg)
7785{
7786 char buf[96];
7787
7788 dd_dev_info(dd, "LCB Error: %s\n",
7789 lcb_err_string(buf, sizeof(buf), reg));
7790}
7791
7792/*
7793 * CCE block DC interrupt. Source is < 8.
7794 */
7795static void is_dc_int(struct hfi1_devdata *dd, unsigned int source)
7796{
7797 const struct err_reg_info *eri = &dc_errs[source];
7798
7799 if (eri->handler) {
7800 interrupt_clear_down(dd, 0, eri);
7801 } else if (source == 3 /* dc_lbm_int */) {
7802 /*
7803 * This indicates that a parity error has occurred on the
7804 * address/control lines presented to the LBM. The error
7805 * is a single pulse, there is no associated error flag,
7806 * and it is non-maskable. This is because if a parity
7807 * error occurs on the request the request is dropped.
7808 * This should never occur, but it is nice to know if it
7809 * ever does.
7810 */
7811 dd_dev_err(dd, "Parity error in DC LBM block\n");
7812 } else {
7813 dd_dev_err(dd, "Invalid DC interrupt %u\n", source);
7814 }
7815}
7816
7817/*
7818 * TX block send credit interrupt. Source is < 160.
7819 */
7820static void is_send_credit_int(struct hfi1_devdata *dd, unsigned int source)
7821{
7822 sc_group_release_update(dd, source);
7823}
7824
7825/*
7826 * TX block SDMA interrupt. Source is < 48.
7827 *
7828 * SDMA interrupts are grouped by type:
7829 *
7830 * 0 - N-1 = SDma
7831 * N - 2N-1 = SDmaProgress
7832 * 2N - 3N-1 = SDmaIdle
7833 */
7834static void is_sdma_eng_int(struct hfi1_devdata *dd, unsigned int source)
7835{
7836 /* what interrupt */
7837 unsigned int what = source / TXE_NUM_SDMA_ENGINES;
7838 /* which engine */
7839 unsigned int which = source % TXE_NUM_SDMA_ENGINES;
7840
7841#ifdef CONFIG_SDMA_VERBOSITY
7842 dd_dev_err(dd, "CONFIG SDMA(%u) %s:%d %s()\n", which,
7843 slashstrip(__FILE__), __LINE__, __func__);
7844 sdma_dumpstate(&dd->per_sdma[which]);
7845#endif
7846
7847 if (likely(what < 3 && which < dd->num_sdma)) {
7848 sdma_engine_interrupt(&dd->per_sdma[which], 1ull << source);
7849 } else {
7850 /* should not happen */
7851 dd_dev_err(dd, "Invalid SDMA interrupt 0x%x\n", source);
7852 }
7853}
7854
7855/*
7856 * RX block receive available interrupt. Source is < 160.
7857 */
7858static void is_rcv_avail_int(struct hfi1_devdata *dd, unsigned int source)
7859{
7860 struct hfi1_ctxtdata *rcd;
7861 char *err_detail;
7862
7863 if (likely(source < dd->num_rcv_contexts)) {
7864 rcd = dd->rcd[source];
7865 if (rcd) {
7866 if (source < dd->first_user_ctxt)
f4f30031 7867 rcd->do_interrupt(rcd, 0);
77241056
MM		 7868 else
7869 handle_user_interrupt(rcd);
7870 return; /* OK */
7871 }
7872 /* received an interrupt, but no rcd */
7873 err_detail = "dataless";
7874 } else {
7875 /* received an interrupt, but are not using that context */
7876 err_detail = "out of range";
7877 }
7878 dd_dev_err(dd, "unexpected %s receive available context interrupt %u\n",
7879 err_detail, source);
7880}
7881
7882/*
7883 * RX block receive urgent interrupt. Source is < 160.
7884 */
7885static void is_rcv_urgent_int(struct hfi1_devdata *dd, unsigned int source)
7886{
7887 struct hfi1_ctxtdata *rcd;
7888 char *err_detail;
7889
7890 if (likely(source < dd->num_rcv_contexts)) {
7891 rcd = dd->rcd[source];
7892 if (rcd) {
7893 /* only pay attention to user urgent interrupts */
7894 if (source >= dd->first_user_ctxt)
7895 handle_user_interrupt(rcd);
7896 return; /* OK */
7897 }
7898 /* received an interrupt, but no rcd */
7899 err_detail = "dataless";
7900 } else {
7901 /* received an interrupt, but are not using that context */
7902 err_detail = "out of range";
7903 }
7904 dd_dev_err(dd, "unexpected %s receive urgent context interrupt %u\n",
7905 err_detail, source);
7906}
7907
7908/*
7909 * Reserved range interrupt. Should not be called in normal operation.
7910 */
7911static void is_reserved_int(struct hfi1_devdata *dd, unsigned int source)
7912{
7913 char name[64];
7914
7915 dd_dev_err(dd, "unexpected %s interrupt\n",
7916 is_reserved_name(name, sizeof(name), source));
7917}
7918
7919static const struct is_table is_table[] = {
7920/* start end
7921 name func interrupt func */
7922{ IS_GENERAL_ERR_START, IS_GENERAL_ERR_END,
7923 is_misc_err_name, is_misc_err_int },
7924{ IS_SDMAENG_ERR_START, IS_SDMAENG_ERR_END,
7925 is_sdma_eng_err_name, is_sdma_eng_err_int },
7926{ IS_SENDCTXT_ERR_START, IS_SENDCTXT_ERR_END,
7927 is_sendctxt_err_name, is_sendctxt_err_int },
7928{ IS_SDMA_START, IS_SDMA_END,
7929 is_sdma_eng_name, is_sdma_eng_int },
7930{ IS_VARIOUS_START, IS_VARIOUS_END,
7931 is_various_name, is_various_int },
7932{ IS_DC_START, IS_DC_END,
7933 is_dc_name, is_dc_int },
7934{ IS_RCVAVAIL_START, IS_RCVAVAIL_END,
7935 is_rcv_avail_name, is_rcv_avail_int },
7936{ IS_RCVURGENT_START, IS_RCVURGENT_END,
7937 is_rcv_urgent_name, is_rcv_urgent_int },
7938{ IS_SENDCREDIT_START, IS_SENDCREDIT_END,
7939 is_send_credit_name, is_send_credit_int},
7940{ IS_RESERVED_START, IS_RESERVED_END,
7941 is_reserved_name, is_reserved_int},
7942};
7943
7944/*
7945 * Interrupt source interrupt - called when the given source has an interrupt.
7946 * Source is a bit index into an array of 64-bit integers.
7947 */
7948static void is_interrupt(struct hfi1_devdata *dd, unsigned int source)
7949{
7950 const struct is_table *entry;
7951
7952 /* avoids a double compare by walking the table in-order */
7953 for (entry = &is_table[0]; entry->is_name; entry++) {
7954 if (source < entry->end) {
7955 trace_hfi1_interrupt(dd, entry, source);
7956 entry->is_int(dd, source - entry->start);
7957 return;
7958 }
7959 }
7960 /* fell off the end */
7961 dd_dev_err(dd, "invalid interrupt source %u\n", source);
7962}
7963
7964/*
7965 * General interrupt handler. This is able to correctly handle
7966 * all interrupts in case INTx is used.
7967 */
7968static irqreturn_t general_interrupt(int irq, void *data)
7969{
7970 struct hfi1_devdata *dd = data;
7971 u64 regs[CCE_NUM_INT_CSRS];
7972 u32 bit;
7973 int i;
7974
7975 this_cpu_inc(*dd->int_counter);
7976
7977 /* phase 1: scan and clear all handled interrupts */
7978 for (i = 0; i < CCE_NUM_INT_CSRS; i++) {
7979 if (dd->gi_mask[i] == 0) {
7980 regs[i] = 0; /* used later */
7981 continue;
7982 }
7983 regs[i] = read_csr(dd, CCE_INT_STATUS + (8 * i)) &
7984 dd->gi_mask[i];
7985 /* only clear if anything is set */
7986 if (regs[i])
7987 write_csr(dd, CCE_INT_CLEAR + (8 * i), regs[i]);
7988 }
7989
7990 /* phase 2: call the appropriate handler */
7991 for_each_set_bit(bit, (unsigned long *)&regs[0],
8638b77f 7992 CCE_NUM_INT_CSRS * 64) {
77241056
MM		 7993 is_interrupt(dd, bit);
7994 }
7995
7996 return IRQ_HANDLED;
7997}
7998
7999static irqreturn_t sdma_interrupt(int irq, void *data)
8000{
8001 struct sdma_engine *sde = data;
8002 struct hfi1_devdata *dd = sde->dd;
8003 u64 status;
8004
8005#ifdef CONFIG_SDMA_VERBOSITY
8006 dd_dev_err(dd, "CONFIG SDMA(%u) %s:%d %s()\n", sde->this_idx,
8007 slashstrip(__FILE__), __LINE__, __func__);
8008 sdma_dumpstate(sde);
8009#endif
8010
8011 this_cpu_inc(*dd->int_counter);
8012
8013 /* This read_csr is really bad in the hot path */
8014 status = read_csr(dd,
8638b77f 8015 CCE_INT_STATUS + (8 * (IS_SDMA_START / 64)))
77241056
MM		 8016 & sde->imask;
8017 if (likely(status)) {
8018 /* clear the interrupt(s) */
8019 write_csr(dd,
8638b77f 8020 CCE_INT_CLEAR + (8 * (IS_SDMA_START / 64)),
77241056
MM		 8021 status);
8022
8023 /* handle the interrupt(s) */
8024 sdma_engine_interrupt(sde, status);
8025 } else
8026 dd_dev_err(dd, "SDMA engine %u interrupt, but no status bits set\n",
8027 sde->this_idx);
8028
8029 return IRQ_HANDLED;
8030}
8031
8032/*
ecd42f8d
DL		 8033 * Clear the receive interrupt. Use a read of the interrupt clear CSR
8034 * to insure that the write completed. This does NOT guarantee that
8035 * queued DMA writes to memory from the chip are pushed.
f4f30031
DL		 8036 */
8037static inline void clear_recv_intr(struct hfi1_ctxtdata *rcd)
8038{
8039 struct hfi1_devdata *dd = rcd->dd;
8040 u32 addr = CCE_INT_CLEAR + (8 * rcd->ireg);
8041
8042 mmiowb(); /* make sure everything before is written */
8043 write_csr(dd, addr, rcd->imask);
8044 /* force the above write on the chip and get a value back */
8045 (void)read_csr(dd, addr);
8046}
8047
8048/* force the receive interrupt */
fb9036dd 8049void force_recv_intr(struct hfi1_ctxtdata *rcd)
f4f30031
DL		 8050{
8051 write_csr(rcd->dd, CCE_INT_FORCE + (8 * rcd->ireg), rcd->imask);
8052}
8053
ecd42f8d
DL		 8054/*
8055 * Return non-zero if a packet is present.
8056 *
8057 * This routine is called when rechecking for packets after the RcvAvail
8058 * interrupt has been cleared down. First, do a quick check of memory for
8059 * a packet present. If not found, use an expensive CSR read of the context
8060 * tail to determine the actual tail. The CSR read is necessary because there
8061 * is no method to push pending DMAs to memory other than an interrupt and we
8062 * are trying to determine if we need to force an interrupt.
8063 */
f4f30031
DL		 8064static inline int check_packet_present(struct hfi1_ctxtdata *rcd)
8065{
ecd42f8d
DL		 8066 u32 tail;
8067 int present;
8068
f4f30031 8069 if (!HFI1_CAP_IS_KSET(DMA_RTAIL))
ecd42f8d 8070 present = (rcd->seq_cnt ==
f4f30031 8071 rhf_rcv_seq(rhf_to_cpu(get_rhf_addr(rcd))));
ecd42f8d
DL		 8072 else /* is RDMA rtail */
8073 present = (rcd->head != get_rcvhdrtail(rcd));
8074
8075 if (present)
8076 return 1;
f4f30031 8077
ecd42f8d
DL		 8078 /* fall back to a CSR read, correct indpendent of DMA_RTAIL */
8079 tail = (u32)read_uctxt_csr(rcd->dd, rcd->ctxt, RCV_HDR_TAIL);
8080 return rcd->head != tail;
f4f30031
DL		 8081}
8082
8083/*
8084 * Receive packet IRQ handler. This routine expects to be on its own IRQ.
8085 * This routine will try to handle packets immediately (latency), but if
8086 * it finds too many, it will invoke the thread handler (bandwitdh). The
8087 * chip receive interupt is *not* cleared down until this or the thread (if
8088 * invoked) is finished. The intent is to avoid extra interrupts while we
8089 * are processing packets anyway.
77241056
MM		 8090 */
8091static irqreturn_t receive_context_interrupt(int irq, void *data)
8092{
8093 struct hfi1_ctxtdata *rcd = data;
8094 struct hfi1_devdata *dd = rcd->dd;
f4f30031
DL		 8095 int disposition;
8096 int present;
77241056
MM		 8097
8098 trace_hfi1_receive_interrupt(dd, rcd->ctxt);
8099 this_cpu_inc(*dd->int_counter);
affa48de 8100 aspm_ctx_disable(rcd);
77241056 8101
f4f30031
DL		 8102 /* receive interrupt remains blocked while processing packets */
8103 disposition = rcd->do_interrupt(rcd, 0);
77241056 8104
f4f30031
DL		 8105 /*
8106 * Too many packets were seen while processing packets in this
8107 * IRQ handler. Invoke the handler thread. The receive interrupt
8108 * remains blocked.
8109 */
8110 if (disposition == RCV_PKT_LIMIT)
8111 return IRQ_WAKE_THREAD;
8112
8113 /*
8114 * The packet processor detected no more packets. Clear the receive
8115 * interrupt and recheck for a packet packet that may have arrived
8116 * after the previous check and interrupt clear. If a packet arrived,
8117 * force another interrupt.
8118 */
8119 clear_recv_intr(rcd);
8120 present = check_packet_present(rcd);
8121 if (present)
8122 force_recv_intr(rcd);
8123
8124 return IRQ_HANDLED;
8125}
8126
8127/*
8128 * Receive packet thread handler. This expects to be invoked with the
8129 * receive interrupt still blocked.
8130 */
8131static irqreturn_t receive_context_thread(int irq, void *data)
8132{
8133 struct hfi1_ctxtdata *rcd = data;
8134 int present;
8135
8136 /* receive interrupt is still blocked from the IRQ handler */
8137 (void)rcd->do_interrupt(rcd, 1);
8138
8139 /*
8140 * The packet processor will only return if it detected no more
8141 * packets. Hold IRQs here so we can safely clear the interrupt and
8142 * recheck for a packet that may have arrived after the previous
8143 * check and the interrupt clear. If a packet arrived, force another
8144 * interrupt.
8145 */
8146 local_irq_disable();
8147 clear_recv_intr(rcd);
8148 present = check_packet_present(rcd);
8149 if (present)
8150 force_recv_intr(rcd);
8151 local_irq_enable();
77241056
MM		 8152
8153 return IRQ_HANDLED;
8154}
8155
8156/* ========================================================================= */
8157
8158u32 read_physical_state(struct hfi1_devdata *dd)
8159{
8160 u64 reg;
8161
8162 reg = read_csr(dd, DC_DC8051_STS_CUR_STATE);
8163 return (reg >> DC_DC8051_STS_CUR_STATE_PORT_SHIFT)
8164 & DC_DC8051_STS_CUR_STATE_PORT_MASK;
8165}
8166
fb9036dd 8167u32 read_logical_state(struct hfi1_devdata *dd)
77241056
MM		 8168{
8169 u64 reg;
8170
8171 reg = read_csr(dd, DCC_CFG_PORT_CONFIG);
8172 return (reg >> DCC_CFG_PORT_CONFIG_LINK_STATE_SHIFT)
8173 & DCC_CFG_PORT_CONFIG_LINK_STATE_MASK;
8174}
8175
8176static void set_logical_state(struct hfi1_devdata *dd, u32 chip_lstate)
8177{
8178 u64 reg;
8179
8180 reg = read_csr(dd, DCC_CFG_PORT_CONFIG);
8181 /* clear current state, set new state */
8182 reg &= ~DCC_CFG_PORT_CONFIG_LINK_STATE_SMASK;
8183 reg |= (u64)chip_lstate << DCC_CFG_PORT_CONFIG_LINK_STATE_SHIFT;
8184 write_csr(dd, DCC_CFG_PORT_CONFIG, reg);
8185}
8186
8187/*
8188 * Use the 8051 to read a LCB CSR.
8189 */
8190static int read_lcb_via_8051(struct hfi1_devdata *dd, u32 addr, u64 *data)
8191{
8192 u32 regno;
8193 int ret;
8194
8195 if (dd->icode == ICODE_FUNCTIONAL_SIMULATOR) {
8196 if (acquire_lcb_access(dd, 0) == 0) {
8197 *data = read_csr(dd, addr);
8198 release_lcb_access(dd, 0);
8199 return 0;
8200 }
8201 return -EBUSY;
8202 }
8203
8204 /* register is an index of LCB registers: (offset - base) / 8 */
8205 regno = (addr - DC_LCB_CFG_RUN) >> 3;
8206 ret = do_8051_command(dd, HCMD_READ_LCB_CSR, regno, data);
8207 if (ret != HCMD_SUCCESS)
8208 return -EBUSY;
8209 return 0;
8210}
8211
8212/*
8213 * Read an LCB CSR. Access may not be in host control, so check.
8214 * Return 0 on success, -EBUSY on failure.
8215 */
8216int read_lcb_csr(struct hfi1_devdata *dd, u32 addr, u64 *data)
8217{
8218 struct hfi1_pportdata *ppd = dd->pport;
8219
8220 /* if up, go through the 8051 for the value */
8221 if (ppd->host_link_state & HLS_UP)
8222 return read_lcb_via_8051(dd, addr, data);
8223 /* if going up or down, no access */
8224 if (ppd->host_link_state & (HLS_GOING_UP | HLS_GOING_OFFLINE))
8225 return -EBUSY;
8226 /* otherwise, host has access */
8227 *data = read_csr(dd, addr);
8228 return 0;
8229}
8230
8231/*
8232 * Use the 8051 to write a LCB CSR.
8233 */
8234static int write_lcb_via_8051(struct hfi1_devdata *dd, u32 addr, u64 data)
8235{
3bf40d65
DL		 8236 u32 regno;
8237 int ret;
77241056 8238
3bf40d65
DL		 8239 if (dd->icode == ICODE_FUNCTIONAL_SIMULATOR ||
8240 (dd->dc8051_ver < dc8051_ver(0, 20))) {
8241 if (acquire_lcb_access(dd, 0) == 0) {
8242 write_csr(dd, addr, data);
8243 release_lcb_access(dd, 0);
8244 return 0;
8245 }
8246 return -EBUSY;
77241056 8247 }
3bf40d65
DL		 8248
8249 /* register is an index of LCB registers: (offset - base) / 8 */
8250 regno = (addr - DC_LCB_CFG_RUN) >> 3;
8251 ret = do_8051_command(dd, HCMD_WRITE_LCB_CSR, regno, &data);
8252 if (ret != HCMD_SUCCESS)
8253 return -EBUSY;
8254 return 0;
77241056
MM		 8255}
8256
8257/*
8258 * Write an LCB CSR. Access may not be in host control, so check.
8259 * Return 0 on success, -EBUSY on failure.
8260 */
8261int write_lcb_csr(struct hfi1_devdata *dd, u32 addr, u64 data)
8262{
8263 struct hfi1_pportdata *ppd = dd->pport;
8264
8265 /* if up, go through the 8051 for the value */
8266 if (ppd->host_link_state & HLS_UP)
8267 return write_lcb_via_8051(dd, addr, data);
8268 /* if going up or down, no access */
8269 if (ppd->host_link_state & (HLS_GOING_UP | HLS_GOING_OFFLINE))
8270 return -EBUSY;
8271 /* otherwise, host has access */
8272 write_csr(dd, addr, data);
8273 return 0;
8274}
8275
8276/*
8277 * Returns:
8278 * < 0 = Linux error, not able to get access
8279 * > 0 = 8051 command RETURN_CODE
8280 */
8281static int do_8051_command(
8282 struct hfi1_devdata *dd,
8283 u32 type,
8284 u64 in_data,
8285 u64 *out_data)
8286{
8287 u64 reg, completed;
8288 int return_code;
8289 unsigned long flags;
8290 unsigned long timeout;
8291
8292 hfi1_cdbg(DC8051, "type %d, data 0x%012llx", type, in_data);
8293
8294 /*
8295 * Alternative to holding the lock for a long time:
8296 * - keep busy wait - have other users bounce off
8297 */
8298 spin_lock_irqsave(&dd->dc8051_lock, flags);
8299
8300 /* We can't send any commands to the 8051 if it's in reset */
8301 if (dd->dc_shutdown) {
8302 return_code = -ENODEV;
8303 goto fail;
8304 }
8305
8306 /*
8307 * If an 8051 host command timed out previously, then the 8051 is
8308 * stuck.
8309 *
8310 * On first timeout, attempt to reset and restart the entire DC
8311 * block (including 8051). (Is this too big of a hammer?)
8312 *
8313 * If the 8051 times out a second time, the reset did not bring it
8314 * back to healthy life. In that case, fail any subsequent commands.
8315 */
8316 if (dd->dc8051_timed_out) {
8317 if (dd->dc8051_timed_out > 1) {
8318 dd_dev_err(dd,
8319 "Previous 8051 host command timed out, skipping command %u\n",
8320 type);
8321 return_code = -ENXIO;
8322 goto fail;
8323 }
8324 spin_unlock_irqrestore(&dd->dc8051_lock, flags);
8325 dc_shutdown(dd);
8326 dc_start(dd);
8327 spin_lock_irqsave(&dd->dc8051_lock, flags);
8328 }
8329
8330 /*
8331 * If there is no timeout, then the 8051 command interface is
8332 * waiting for a command.
8333 */
8334
3bf40d65
DL		 8335 /*
8336 * When writing a LCB CSR, out_data contains the full value to
8337 * to be written, while in_data contains the relative LCB
8338 * address in 7:0. Do the work here, rather than the caller,
8339 * of distrubting the write data to where it needs to go:
8340 *
8341 * Write data
8342 * 39:00 -> in_data[47:8]
8343 * 47:40 -> DC8051_CFG_EXT_DEV_0.RETURN_CODE
8344 * 63:48 -> DC8051_CFG_EXT_DEV_0.RSP_DATA
8345 */
8346 if (type == HCMD_WRITE_LCB_CSR) {
8347 in_data |= ((*out_data) & 0xffffffffffull) << 8;
8348 reg = ((((*out_data) >> 40) & 0xff) <<
8349 DC_DC8051_CFG_EXT_DEV_0_RETURN_CODE_SHIFT)
8350 | ((((*out_data) >> 48) & 0xffff) <<
8351 DC_DC8051_CFG_EXT_DEV_0_RSP_DATA_SHIFT);
8352 write_csr(dd, DC_DC8051_CFG_EXT_DEV_0, reg);
8353 }
8354
77241056
MM		 8355 /*
8356 * Do two writes: the first to stabilize the type and req_data, the
8357 * second to activate.
8358 */
8359 reg = ((u64)type & DC_DC8051_CFG_HOST_CMD_0_REQ_TYPE_MASK)
8360 << DC_DC8051_CFG_HOST_CMD_0_REQ_TYPE_SHIFT
8361 | (in_data & DC_DC8051_CFG_HOST_CMD_0_REQ_DATA_MASK)
8362 << DC_DC8051_CFG_HOST_CMD_0_REQ_DATA_SHIFT;
8363 write_csr(dd, DC_DC8051_CFG_HOST_CMD_0, reg);
8364 reg |= DC_DC8051_CFG_HOST_CMD_0_REQ_NEW_SMASK;
8365 write_csr(dd, DC_DC8051_CFG_HOST_CMD_0, reg);
8366
8367 /* wait for completion, alternate: interrupt */
8368 timeout = jiffies + msecs_to_jiffies(DC8051_COMMAND_TIMEOUT);
8369 while (1) {
8370 reg = read_csr(dd, DC_DC8051_CFG_HOST_CMD_1);
8371 completed = reg & DC_DC8051_CFG_HOST_CMD_1_COMPLETED_SMASK;
8372 if (completed)
8373 break;
8374 if (time_after(jiffies, timeout)) {
8375 dd->dc8051_timed_out++;
8376 dd_dev_err(dd, "8051 host command %u timeout\n", type);
8377 if (out_data)
8378 *out_data = 0;
8379 return_code = -ETIMEDOUT;
8380 goto fail;
8381 }
8382 udelay(2);
8383 }
8384
8385 if (out_data) {
8386 *out_data = (reg >> DC_DC8051_CFG_HOST_CMD_1_RSP_DATA_SHIFT)
8387 & DC_DC8051_CFG_HOST_CMD_1_RSP_DATA_MASK;
8388 if (type == HCMD_READ_LCB_CSR) {
8389 /* top 16 bits are in a different register */
8390 *out_data |= (read_csr(dd, DC_DC8051_CFG_EXT_DEV_1)
8391 & DC_DC8051_CFG_EXT_DEV_1_REQ_DATA_SMASK)
8392 << (48
8393 - DC_DC8051_CFG_EXT_DEV_1_REQ_DATA_SHIFT);
8394 }
8395 }
8396 return_code = (reg >> DC_DC8051_CFG_HOST_CMD_1_RETURN_CODE_SHIFT)
8397 & DC_DC8051_CFG_HOST_CMD_1_RETURN_CODE_MASK;
8398 dd->dc8051_timed_out = 0;
8399 /*
8400 * Clear command for next user.
8401 */
8402 write_csr(dd, DC_DC8051_CFG_HOST_CMD_0, 0);
8403
8404fail:
8405 spin_unlock_irqrestore(&dd->dc8051_lock, flags);
8406
8407 return return_code;
8408}
8409
8410static int set_physical_link_state(struct hfi1_devdata *dd, u64 state)
8411{
8412 return do_8051_command(dd, HCMD_CHANGE_PHY_STATE, state, NULL);
8413}
8414
8ebd4cf1
EH		 8415int load_8051_config(struct hfi1_devdata *dd, u8 field_id,
8416 u8 lane_id, u32 config_data)
77241056
MM		 8417{
8418 u64 data;
8419 int ret;
8420
8421 data = (u64)field_id << LOAD_DATA_FIELD_ID_SHIFT
8422 | (u64)lane_id << LOAD_DATA_LANE_ID_SHIFT
8423 | (u64)config_data << LOAD_DATA_DATA_SHIFT;
8424 ret = do_8051_command(dd, HCMD_LOAD_CONFIG_DATA, data, NULL);
8425 if (ret != HCMD_SUCCESS) {
8426 dd_dev_err(dd,
8427 "load 8051 config: field id %d, lane %d, err %d\n",
8428 (int)field_id, (int)lane_id, ret);
8429 }
8430 return ret;
8431}
8432
8433/*
8434 * Read the 8051 firmware "registers". Use the RAM directly. Always
8435 * set the result, even on error.
8436 * Return 0 on success, -errno on failure
8437 */
8ebd4cf1
EH		 8438int read_8051_config(struct hfi1_devdata *dd, u8 field_id, u8 lane_id,
8439 u32 *result)
77241056
MM		 8440{
8441 u64 big_data;
8442 u32 addr;
8443 int ret;
8444
8445 /* address start depends on the lane_id */
8446 if (lane_id < 4)
8447 addr = (4 * NUM_GENERAL_FIELDS)
8448 + (lane_id * 4 * NUM_LANE_FIELDS);
8449 else
8450 addr = 0;
8451 addr += field_id * 4;
8452
8453 /* read is in 8-byte chunks, hardware will truncate the address down */
8454 ret = read_8051_data(dd, addr, 8, &big_data);
8455
8456 if (ret == 0) {
8457 /* extract the 4 bytes we want */
8458 if (addr & 0x4)
8459 *result = (u32)(big_data >> 32);
8460 else
8461 *result = (u32)big_data;
8462 } else {
8463 *result = 0;
8464 dd_dev_err(dd, "%s: direct read failed, lane %d, field %d!\n",
8465 __func__, lane_id, field_id);
8466 }
8467
8468 return ret;
8469}
8470
8471static int write_vc_local_phy(struct hfi1_devdata *dd, u8 power_management,
8472 u8 continuous)
8473{
8474 u32 frame;
8475
8476 frame = continuous << CONTINIOUS_REMOTE_UPDATE_SUPPORT_SHIFT
8477 | power_management << POWER_MANAGEMENT_SHIFT;
8478 return load_8051_config(dd, VERIFY_CAP_LOCAL_PHY,
8479 GENERAL_CONFIG, frame);
8480}
8481
8482static int write_vc_local_fabric(struct hfi1_devdata *dd, u8 vau, u8 z, u8 vcu,
8483 u16 vl15buf, u8 crc_sizes)
8484{
8485 u32 frame;
8486
8487 frame = (u32)vau << VAU_SHIFT
8488 | (u32)z << Z_SHIFT
8489 | (u32)vcu << VCU_SHIFT
8490 | (u32)vl15buf << VL15BUF_SHIFT
8491 | (u32)crc_sizes << CRC_SIZES_SHIFT;
8492 return load_8051_config(dd, VERIFY_CAP_LOCAL_FABRIC,
8493 GENERAL_CONFIG, frame);
8494}
8495
8496static void read_vc_local_link_width(struct hfi1_devdata *dd, u8 *misc_bits,
8497 u8 *flag_bits, u16 *link_widths)
8498{
8499 u32 frame;
8500
8501 read_8051_config(dd, VERIFY_CAP_LOCAL_LINK_WIDTH, GENERAL_CONFIG,
8502 &frame);
8503 *misc_bits = (frame >> MISC_CONFIG_BITS_SHIFT) & MISC_CONFIG_BITS_MASK;
8504 *flag_bits = (frame >> LOCAL_FLAG_BITS_SHIFT) & LOCAL_FLAG_BITS_MASK;
8505 *link_widths = (frame >> LINK_WIDTH_SHIFT) & LINK_WIDTH_MASK;
8506}
8507
8508static int write_vc_local_link_width(struct hfi1_devdata *dd,
8509 u8 misc_bits,
8510 u8 flag_bits,
8511 u16 link_widths)
8512{
8513 u32 frame;
8514
8515 frame = (u32)misc_bits << MISC_CONFIG_BITS_SHIFT
8516 | (u32)flag_bits << LOCAL_FLAG_BITS_SHIFT
8517 | (u32)link_widths << LINK_WIDTH_SHIFT;
8518 return load_8051_config(dd, VERIFY_CAP_LOCAL_LINK_WIDTH, GENERAL_CONFIG,
8519 frame);
8520}
8521
8522static int write_local_device_id(struct hfi1_devdata *dd, u16 device_id,
8523 u8 device_rev)
8524{
8525 u32 frame;
8526
8527 frame = ((u32)device_id << LOCAL_DEVICE_ID_SHIFT)
8528 | ((u32)device_rev << LOCAL_DEVICE_REV_SHIFT);
8529 return load_8051_config(dd, LOCAL_DEVICE_ID, GENERAL_CONFIG, frame);
8530}
8531
8532static void read_remote_device_id(struct hfi1_devdata *dd, u16 *device_id,
8533 u8 *device_rev)
8534{
8535 u32 frame;
8536
8537 read_8051_config(dd, REMOTE_DEVICE_ID, GENERAL_CONFIG, &frame);
8538 *device_id = (frame >> REMOTE_DEVICE_ID_SHIFT) & REMOTE_DEVICE_ID_MASK;
8539 *device_rev = (frame >> REMOTE_DEVICE_REV_SHIFT)
8540 & REMOTE_DEVICE_REV_MASK;
8541}
8542
8543void read_misc_status(struct hfi1_devdata *dd, u8 *ver_a, u8 *ver_b)
8544{
8545 u32 frame;
8546
8547 read_8051_config(dd, MISC_STATUS, GENERAL_CONFIG, &frame);
8548 *ver_a = (frame >> STS_FM_VERSION_A_SHIFT) & STS_FM_VERSION_A_MASK;
8549 *ver_b = (frame >> STS_FM_VERSION_B_SHIFT) & STS_FM_VERSION_B_MASK;
8550}
8551
8552static void read_vc_remote_phy(struct hfi1_devdata *dd, u8 *power_management,
8553 u8 *continuous)
8554{
8555 u32 frame;
8556
8557 read_8051_config(dd, VERIFY_CAP_REMOTE_PHY, GENERAL_CONFIG, &frame);
8558 *power_management = (frame >> POWER_MANAGEMENT_SHIFT)
8559 & POWER_MANAGEMENT_MASK;
8560 *continuous = (frame >> CONTINIOUS_REMOTE_UPDATE_SUPPORT_SHIFT)
8561 & CONTINIOUS_REMOTE_UPDATE_SUPPORT_MASK;
8562}
8563
8564static void read_vc_remote_fabric(struct hfi1_devdata *dd, u8 *vau, u8 *z,
8565 u8 *vcu, u16 *vl15buf, u8 *crc_sizes)
8566{
8567 u32 frame;
8568
8569 read_8051_config(dd, VERIFY_CAP_REMOTE_FABRIC, GENERAL_CONFIG, &frame);
8570 *vau = (frame >> VAU_SHIFT) & VAU_MASK;
8571 *z = (frame >> Z_SHIFT) & Z_MASK;
8572 *vcu = (frame >> VCU_SHIFT) & VCU_MASK;
8573 *vl15buf = (frame >> VL15BUF_SHIFT) & VL15BUF_MASK;
8574 *crc_sizes = (frame >> CRC_SIZES_SHIFT) & CRC_SIZES_MASK;
8575}
8576
8577static void read_vc_remote_link_width(struct hfi1_devdata *dd,
8578 u8 *remote_tx_rate,
8579 u16 *link_widths)
8580{
8581 u32 frame;
8582
8583 read_8051_config(dd, VERIFY_CAP_REMOTE_LINK_WIDTH, GENERAL_CONFIG,
8584 &frame);
8585 *remote_tx_rate = (frame >> REMOTE_TX_RATE_SHIFT)
8586 & REMOTE_TX_RATE_MASK;
8587 *link_widths = (frame >> LINK_WIDTH_SHIFT) & LINK_WIDTH_MASK;
8588}
8589
8590static void read_local_lni(struct hfi1_devdata *dd, u8 *enable_lane_rx)
8591{
8592 u32 frame;
8593
8594 read_8051_config(dd, LOCAL_LNI_INFO, GENERAL_CONFIG, &frame);
8595 *enable_lane_rx = (frame >> ENABLE_LANE_RX_SHIFT) & ENABLE_LANE_RX_MASK;
8596}
8597
8598static void read_mgmt_allowed(struct hfi1_devdata *dd, u8 *mgmt_allowed)
8599{
8600 u32 frame;
8601
8602 read_8051_config(dd, REMOTE_LNI_INFO, GENERAL_CONFIG, &frame);
8603 *mgmt_allowed = (frame >> MGMT_ALLOWED_SHIFT) & MGMT_ALLOWED_MASK;
8604}
8605
8606static void read_last_local_state(struct hfi1_devdata *dd, u32 *lls)
8607{
8608 read_8051_config(dd, LAST_LOCAL_STATE_COMPLETE, GENERAL_CONFIG, lls);
8609}
8610
8611static void read_last_remote_state(struct hfi1_devdata *dd, u32 *lrs)
8612{
8613 read_8051_config(dd, LAST_REMOTE_STATE_COMPLETE, GENERAL_CONFIG, lrs);
8614}
8615
8616void hfi1_read_link_quality(struct hfi1_devdata *dd, u8 *link_quality)
8617{
8618 u32 frame;
8619 int ret;
8620
8621 *link_quality = 0;
8622 if (dd->pport->host_link_state & HLS_UP) {
8623 ret = read_8051_config(dd, LINK_QUALITY_INFO, GENERAL_CONFIG,
8624 &frame);
8625 if (ret == 0)
8626 *link_quality = (frame >> LINK_QUALITY_SHIFT)
8627 & LINK_QUALITY_MASK;
8628 }
8629}
8630
8631static void read_planned_down_reason_code(struct hfi1_devdata *dd, u8 *pdrrc)
8632{
8633 u32 frame;
8634
8635 read_8051_config(dd, LINK_QUALITY_INFO, GENERAL_CONFIG, &frame);
8636 *pdrrc = (frame >> DOWN_REMOTE_REASON_SHIFT) & DOWN_REMOTE_REASON_MASK;
8637}
8638
8639static int read_tx_settings(struct hfi1_devdata *dd,
8640 u8 *enable_lane_tx,
8641 u8 *tx_polarity_inversion,
8642 u8 *rx_polarity_inversion,
8643 u8 *max_rate)
8644{
8645 u32 frame;
8646 int ret;
8647
8648 ret = read_8051_config(dd, TX_SETTINGS, GENERAL_CONFIG, &frame);
8649 *enable_lane_tx = (frame >> ENABLE_LANE_TX_SHIFT)
8650 & ENABLE_LANE_TX_MASK;
8651 *tx_polarity_inversion = (frame >> TX_POLARITY_INVERSION_SHIFT)
8652 & TX_POLARITY_INVERSION_MASK;
8653 *rx_polarity_inversion = (frame >> RX_POLARITY_INVERSION_SHIFT)
8654 & RX_POLARITY_INVERSION_MASK;
8655 *max_rate = (frame >> MAX_RATE_SHIFT) & MAX_RATE_MASK;
8656 return ret;
8657}
8658
8659static int write_tx_settings(struct hfi1_devdata *dd,
8660 u8 enable_lane_tx,
8661 u8 tx_polarity_inversion,
8662 u8 rx_polarity_inversion,
8663 u8 max_rate)
8664{
8665 u32 frame;
8666
8667 /* no need to mask, all variable sizes match field widths */
8668 frame = enable_lane_tx << ENABLE_LANE_TX_SHIFT
8669 | tx_polarity_inversion << TX_POLARITY_INVERSION_SHIFT
8670 | rx_polarity_inversion << RX_POLARITY_INVERSION_SHIFT
8671 | max_rate << MAX_RATE_SHIFT;
8672 return load_8051_config(dd, TX_SETTINGS, GENERAL_CONFIG, frame);
8673}
8674
8675static void check_fabric_firmware_versions(struct hfi1_devdata *dd)
8676{
8677 u32 frame, version, prod_id;
8678 int ret, lane;
8679
8680 /* 4 lanes */
8681 for (lane = 0; lane < 4; lane++) {
8682 ret = read_8051_config(dd, SPICO_FW_VERSION, lane, &frame);
8683 if (ret) {
8684 dd_dev_err(
8685 dd,
8686 "Unable to read lane %d firmware details\n",
8687 lane);
8688 continue;
8689 }
8690 version = (frame >> SPICO_ROM_VERSION_SHIFT)
8691 & SPICO_ROM_VERSION_MASK;
8692 prod_id = (frame >> SPICO_ROM_PROD_ID_SHIFT)
8693 & SPICO_ROM_PROD_ID_MASK;
8694 dd_dev_info(dd,
8695 "Lane %d firmware: version 0x%04x, prod_id 0x%04x\n",
8696 lane, version, prod_id);
8697 }
8698}
8699
8700/*
8701 * Read an idle LCB message.
8702 *
8703 * Returns 0 on success, -EINVAL on error
8704 */
8705static int read_idle_message(struct hfi1_devdata *dd, u64 type, u64 *data_out)
8706{
8707 int ret;
8708
8709 ret = do_8051_command(dd, HCMD_READ_LCB_IDLE_MSG,
8710 type, data_out);
8711 if (ret != HCMD_SUCCESS) {
8712 dd_dev_err(dd, "read idle message: type %d, err %d\n",
8713 (u32)type, ret);
8714 return -EINVAL;
8715 }
8716 dd_dev_info(dd, "%s: read idle message 0x%llx\n", __func__, *data_out);
8717 /* return only the payload as we already know the type */
8718 *data_out >>= IDLE_PAYLOAD_SHIFT;
8719 return 0;
8720}
8721
8722/*
8723 * Read an idle SMA message. To be done in response to a notification from
8724 * the 8051.
8725 *
8726 * Returns 0 on success, -EINVAL on error
8727 */
8728static int read_idle_sma(struct hfi1_devdata *dd, u64 *data)
8729{
8730 return read_idle_message(dd,
8731 (u64)IDLE_SMA << IDLE_MSG_TYPE_SHIFT, data);
8732}
8733
8734/*
8735 * Send an idle LCB message.
8736 *
8737 * Returns 0 on success, -EINVAL on error
8738 */
8739static int send_idle_message(struct hfi1_devdata *dd, u64 data)
8740{
8741 int ret;
8742
8743 dd_dev_info(dd, "%s: sending idle message 0x%llx\n", __func__, data);
8744 ret = do_8051_command(dd, HCMD_SEND_LCB_IDLE_MSG, data, NULL);
8745 if (ret != HCMD_SUCCESS) {
8746 dd_dev_err(dd, "send idle message: data 0x%llx, err %d\n",
8747 data, ret);
8748 return -EINVAL;
8749 }
8750 return 0;
8751}
8752
8753/*
8754 * Send an idle SMA message.
8755 *
8756 * Returns 0 on success, -EINVAL on error
8757 */
8758int send_idle_sma(struct hfi1_devdata *dd, u64 message)
8759{
8760 u64 data;
8761
8762 data = ((message & IDLE_PAYLOAD_MASK) << IDLE_PAYLOAD_SHIFT)
8763 | ((u64)IDLE_SMA << IDLE_MSG_TYPE_SHIFT);
8764 return send_idle_message(dd, data);
8765}
8766
8767/*
8768 * Initialize the LCB then do a quick link up. This may or may not be
8769 * in loopback.
8770 *
8771 * return 0 on success, -errno on error
8772 */
8773static int do_quick_linkup(struct hfi1_devdata *dd)
8774{
8775 u64 reg;
8776 unsigned long timeout;
8777 int ret;
8778
8779 lcb_shutdown(dd, 0);
8780
8781 if (loopback) {
8782 /* LCB_CFG_LOOPBACK.VAL = 2 */
8783 /* LCB_CFG_LANE_WIDTH.VAL = 0 */
8784 write_csr(dd, DC_LCB_CFG_LOOPBACK,
8785 IB_PACKET_TYPE << DC_LCB_CFG_LOOPBACK_VAL_SHIFT);
8786 write_csr(dd, DC_LCB_CFG_LANE_WIDTH, 0);
8787 }
8788
8789 /* start the LCBs */
8790 /* LCB_CFG_TX_FIFOS_RESET.VAL = 0 */
8791 write_csr(dd, DC_LCB_CFG_TX_FIFOS_RESET, 0);
8792
8793 /* simulator only loopback steps */
8794 if (loopback && dd->icode == ICODE_FUNCTIONAL_SIMULATOR) {
8795 /* LCB_CFG_RUN.EN = 1 */
8796 write_csr(dd, DC_LCB_CFG_RUN,
8797 1ull << DC_LCB_CFG_RUN_EN_SHIFT);
8798
8799 /* watch LCB_STS_LINK_TRANSFER_ACTIVE */
8800 timeout = jiffies + msecs_to_jiffies(10);
8801 while (1) {
8802 reg = read_csr(dd,
8803 DC_LCB_STS_LINK_TRANSFER_ACTIVE);
8804 if (reg)
8805 break;
8806 if (time_after(jiffies, timeout)) {
8807 dd_dev_err(dd,
8808 "timeout waiting for LINK_TRANSFER_ACTIVE\n");
8809 return -ETIMEDOUT;
8810 }
8811 udelay(2);
8812 }
8813
8814 write_csr(dd, DC_LCB_CFG_ALLOW_LINK_UP,
8815 1ull << DC_LCB_CFG_ALLOW_LINK_UP_VAL_SHIFT);
8816 }
8817
8818 if (!loopback) {
8819 /*
8820 * When doing quick linkup and not in loopback, both
8821 * sides must be done with LCB set-up before either
8822 * starts the quick linkup. Put a delay here so that
8823 * both sides can be started and have a chance to be
8824 * done with LCB set up before resuming.
8825 */
8826 dd_dev_err(dd,
8827 "Pausing for peer to be finished with LCB set up\n");
8828 msleep(5000);
8829 dd_dev_err(dd,
8830 "Continuing with quick linkup\n");
8831 }
8832
8833 write_csr(dd, DC_LCB_ERR_EN, 0); /* mask LCB errors */
8834 set_8051_lcb_access(dd);
8835
8836 /*
8837 * State "quick" LinkUp request sets the physical link state to
8838 * LinkUp without a verify capability sequence.
8839 * This state is in simulator v37 and later.
8840 */
8841 ret = set_physical_link_state(dd, PLS_QUICK_LINKUP);
8842 if (ret != HCMD_SUCCESS) {
8843 dd_dev_err(dd,
8844 "%s: set physical link state to quick LinkUp failed with return %d\n",
8845 __func__, ret);
8846
8847 set_host_lcb_access(dd);
8848 write_csr(dd, DC_LCB_ERR_EN, ~0ull); /* watch LCB errors */
8849
8850 if (ret >= 0)
8851 ret = -EINVAL;
8852 return ret;
8853 }
8854
8855 return 0; /* success */
8856}
8857
8858/*
8859 * Set the SerDes to internal loopback mode.
8860 * Returns 0 on success, -errno on error.
8861 */
8862static int set_serdes_loopback_mode(struct hfi1_devdata *dd)
8863{
8864 int ret;
8865
8866 ret = set_physical_link_state(dd, PLS_INTERNAL_SERDES_LOOPBACK);
8867 if (ret == HCMD_SUCCESS)
8868 return 0;
8869 dd_dev_err(dd,
8870 "Set physical link state to SerDes Loopback failed with return %d\n",
8871 ret);
8872 if (ret >= 0)
8873 ret = -EINVAL;
8874 return ret;
8875}
8876
8877/*
8878 * Do all special steps to set up loopback.
8879 */
8880static int init_loopback(struct hfi1_devdata *dd)
8881{
8882 dd_dev_info(dd, "Entering loopback mode\n");
8883
8884 /* all loopbacks should disable self GUID check */
8885 write_csr(dd, DC_DC8051_CFG_MODE,
8886 (read_csr(dd, DC_DC8051_CFG_MODE) | DISABLE_SELF_GUID_CHECK));
8887
8888 /*
8889 * The simulator has only one loopback option - LCB. Switch
8890 * to that option, which includes quick link up.
8891 *
8892 * Accept all valid loopback values.
8893 */
8894 if ((dd->icode == ICODE_FUNCTIONAL_SIMULATOR)
8895 && (loopback == LOOPBACK_SERDES
8896 || loopback == LOOPBACK_LCB
8897 || loopback == LOOPBACK_CABLE)) {
8898 loopback = LOOPBACK_LCB;
8899 quick_linkup = 1;
8900 return 0;
8901 }
8902
8903 /* handle serdes loopback */
8904 if (loopback == LOOPBACK_SERDES) {
8905 /* internal serdes loopack needs quick linkup on RTL */
8906 if (dd->icode == ICODE_RTL_SILICON)
8907 quick_linkup = 1;
8908 return set_serdes_loopback_mode(dd);
8909 }
8910
8911 /* LCB loopback - handled at poll time */
8912 if (loopback == LOOPBACK_LCB) {
8913 quick_linkup = 1; /* LCB is always quick linkup */
8914
8915 /* not supported in emulation due to emulation RTL changes */
8916 if (dd->icode == ICODE_FPGA_EMULATION) {
8917 dd_dev_err(dd,
8918 "LCB loopback not supported in emulation\n");
8919 return -EINVAL;
8920 }
8921 return 0;
8922 }
8923
8924 /* external cable loopback requires no extra steps */
8925 if (loopback == LOOPBACK_CABLE)
8926 return 0;
8927
8928 dd_dev_err(dd, "Invalid loopback mode %d\n", loopback);
8929 return -EINVAL;
8930}
8931
8932/*
8933 * Translate from the OPA_LINK_WIDTH handed to us by the FM to bits
8934 * used in the Verify Capability link width attribute.
8935 */
8936static u16 opa_to_vc_link_widths(u16 opa_widths)
8937{
8938 int i;
8939 u16 result = 0;
8940
8941 static const struct link_bits {
8942 u16 from;
8943 u16 to;
8944 } opa_link_xlate[] = {
8638b77f
JJ		 8945 { OPA_LINK_WIDTH_1X, 1 << (1 - 1) },
8946 { OPA_LINK_WIDTH_2X, 1 << (2 - 1) },
8947 { OPA_LINK_WIDTH_3X, 1 << (3 - 1) },
8948 { OPA_LINK_WIDTH_4X, 1 << (4 - 1) },
77241056
MM		 8949 };
8950
8951 for (i = 0; i < ARRAY_SIZE(opa_link_xlate); i++) {
8952 if (opa_widths & opa_link_xlate[i].from)
8953 result |= opa_link_xlate[i].to;
8954 }
8955 return result;
8956}
8957
8958/*
8959 * Set link attributes before moving to polling.
8960 */
8961static int set_local_link_attributes(struct hfi1_pportdata *ppd)
8962{
8963 struct hfi1_devdata *dd = ppd->dd;
8964 u8 enable_lane_tx;
8965 u8 tx_polarity_inversion;
8966 u8 rx_polarity_inversion;
8967 int ret;
8968
8969 /* reset our fabric serdes to clear any lingering problems */
8970 fabric_serdes_reset(dd);
8971
8972 /* set the local tx rate - need to read-modify-write */
8973 ret = read_tx_settings(dd, &enable_lane_tx, &tx_polarity_inversion,
8974 &rx_polarity_inversion, &ppd->local_tx_rate);
8975 if (ret)
8976 goto set_local_link_attributes_fail;
8977
8978 if (dd->dc8051_ver < dc8051_ver(0, 20)) {
8979 /* set the tx rate to the fastest enabled */
8980 if (ppd->link_speed_enabled & OPA_LINK_SPEED_25G)
8981 ppd->local_tx_rate = 1;
8982 else
8983 ppd->local_tx_rate = 0;
8984 } else {
8985 /* set the tx rate to all enabled */
8986 ppd->local_tx_rate = 0;
8987 if (ppd->link_speed_enabled & OPA_LINK_SPEED_25G)
8988 ppd->local_tx_rate |= 2;
8989 if (ppd->link_speed_enabled & OPA_LINK_SPEED_12_5G)
8990 ppd->local_tx_rate |= 1;
8991 }
febffe2c
EH		 8992
8993 enable_lane_tx = 0xF; /* enable all four lanes */
77241056
MM		 8994 ret = write_tx_settings(dd, enable_lane_tx, tx_polarity_inversion,
8995 rx_polarity_inversion, ppd->local_tx_rate);
8996 if (ret != HCMD_SUCCESS)
8997 goto set_local_link_attributes_fail;
8998
8999 /*
9000 * DC supports continuous updates.
9001 */
9002 ret = write_vc_local_phy(dd, 0 /* no power management */,
9003 1 /* continuous updates */);
9004 if (ret != HCMD_SUCCESS)
9005 goto set_local_link_attributes_fail;
9006
9007 /* z=1 in the next call: AU of 0 is not supported by the hardware */
9008 ret = write_vc_local_fabric(dd, dd->vau, 1, dd->vcu, dd->vl15_init,
9009 ppd->port_crc_mode_enabled);
9010 if (ret != HCMD_SUCCESS)
9011 goto set_local_link_attributes_fail;
9012
9013 ret = write_vc_local_link_width(dd, 0, 0,
9014 opa_to_vc_link_widths(ppd->link_width_enabled));
9015 if (ret != HCMD_SUCCESS)
9016 goto set_local_link_attributes_fail;
9017
9018 /* let peer know who we are */
9019 ret = write_local_device_id(dd, dd->pcidev->device, dd->minrev);
9020 if (ret == HCMD_SUCCESS)
9021 return 0;
9022
9023set_local_link_attributes_fail:
9024 dd_dev_err(dd,
9025 "Failed to set local link attributes, return 0x%x\n",
9026 ret);
9027 return ret;
9028}
9029
9030/*
9031 * Call this to start the link. Schedule a retry if the cable is not
9032 * present or if unable to start polling. Do not do anything if the
9033 * link is disabled. Returns 0 if link is disabled or moved to polling
9034 */
9035int start_link(struct hfi1_pportdata *ppd)
9036{
9037 if (!ppd->link_enabled) {
9038 dd_dev_info(ppd->dd,
9039 "%s: stopping link start because link is disabled\n",
9040 __func__);
9041 return 0;
9042 }
9043 if (!ppd->driver_link_ready) {
9044 dd_dev_info(ppd->dd,
9045 "%s: stopping link start because driver is not ready\n",
9046 __func__);
9047 return 0;
9048 }
9049
9050 if (qsfp_mod_present(ppd) || loopback == LOOPBACK_SERDES ||
9051 loopback == LOOPBACK_LCB ||
9052 ppd->dd->icode == ICODE_FUNCTIONAL_SIMULATOR)
9053 return set_link_state(ppd, HLS_DN_POLL);
9054
9055 dd_dev_info(ppd->dd,
9056 "%s: stopping link start because no cable is present\n",
9057 __func__);
9058 return -EAGAIN;
9059}
9060
8ebd4cf1
EH		 9061static void wait_for_qsfp_init(struct hfi1_pportdata *ppd)
9062{
9063 struct hfi1_devdata *dd = ppd->dd;
9064 u64 mask;
9065 unsigned long timeout;
9066
9067 /*
9068 * Check for QSFP interrupt for t_init (SFF 8679)
9069 */
9070 timeout = jiffies + msecs_to_jiffies(2000);
9071 while (1) {
9072 mask = read_csr(dd, dd->hfi1_id ?
9073 ASIC_QSFP2_IN : ASIC_QSFP1_IN);
9074 if (!(mask & QSFP_HFI0_INT_N)) {
9075 write_csr(dd, dd->hfi1_id ? ASIC_QSFP2_CLEAR :
9076 ASIC_QSFP1_CLEAR, QSFP_HFI0_INT_N);
9077 break;
9078 }
9079 if (time_after(jiffies, timeout)) {
9080 dd_dev_info(dd, "%s: No IntN detected, reset complete\n",
9081 __func__);
9082 break;
9083 }
9084 udelay(2);
9085 }
9086}
9087
9088static void set_qsfp_int_n(struct hfi1_pportdata *ppd, u8 enable)
9089{
9090 struct hfi1_devdata *dd = ppd->dd;
9091 u64 mask;
9092
9093 mask = read_csr(dd, dd->hfi1_id ? ASIC_QSFP2_MASK : ASIC_QSFP1_MASK);
9094 if (enable)
9095 mask |= (u64)QSFP_HFI0_INT_N;
9096 else
9097 mask &= ~(u64)QSFP_HFI0_INT_N;
9098 write_csr(dd, dd->hfi1_id ? ASIC_QSFP2_MASK : ASIC_QSFP1_MASK, mask);
9099}
9100
9101void reset_qsfp(struct hfi1_pportdata *ppd)
77241056
MM		 9102{
9103 struct hfi1_devdata *dd = ppd->dd;
9104 u64 mask, qsfp_mask;
9105
8ebd4cf1
EH		 9106 /* Disable INT_N from triggering QSFP interrupts */
9107 set_qsfp_int_n(ppd, 0);
9108
9109 /* Reset the QSFP */
77241056 9110 mask = (u64)QSFP_HFI0_RESET_N;
8ebd4cf1 9111 qsfp_mask = read_csr(dd, dd->hfi1_id ? ASIC_QSFP2_OE : ASIC_QSFP1_OE);
77241056
MM		 9112 qsfp_mask |= mask;
9113 write_csr(dd,
8ebd4cf1 9114 dd->hfi1_id ? ASIC_QSFP2_OE : ASIC_QSFP1_OE, qsfp_mask);
77241056 9115
8ebd4cf1
EH		 9116 qsfp_mask = read_csr(dd, dd->hfi1_id ?
9117 ASIC_QSFP2_OUT : ASIC_QSFP1_OUT);
77241056
MM		 9118 qsfp_mask &= ~mask;
9119 write_csr(dd,
8ebd4cf1 9120 dd->hfi1_id ? ASIC_QSFP2_OUT : ASIC_QSFP1_OUT, qsfp_mask);
77241056
MM		 9121
9122 udelay(10);
9123
9124 qsfp_mask |= mask;
9125 write_csr(dd,
8ebd4cf1
EH		 9126 dd->hfi1_id ? ASIC_QSFP2_OUT : ASIC_QSFP1_OUT, qsfp_mask);
9127
9128 wait_for_qsfp_init(ppd);
9129
9130 /*
9131 * Allow INT_N to trigger the QSFP interrupt to watch
9132 * for alarms and warnings
9133 */
9134 set_qsfp_int_n(ppd, 1);
77241056
MM		 9135}
9136
9137static int handle_qsfp_error_conditions(struct hfi1_pportdata *ppd,
9138 u8 *qsfp_interrupt_status)
9139{
9140 struct hfi1_devdata *dd = ppd->dd;
9141
9142 if ((qsfp_interrupt_status[0] & QSFP_HIGH_TEMP_ALARM) ||
9143 (qsfp_interrupt_status[0] & QSFP_HIGH_TEMP_WARNING))
9144 dd_dev_info(dd,
9145 "%s: QSFP cable on fire\n",
9146 __func__);
9147
9148 if ((qsfp_interrupt_status[0] & QSFP_LOW_TEMP_ALARM) ||
9149 (qsfp_interrupt_status[0] & QSFP_LOW_TEMP_WARNING))
9150 dd_dev_info(dd,
9151 "%s: QSFP cable temperature too low\n",
9152 __func__);
9153
9154 if ((qsfp_interrupt_status[1] & QSFP_HIGH_VCC_ALARM) ||
9155 (qsfp_interrupt_status[1] & QSFP_HIGH_VCC_WARNING))
9156 dd_dev_info(dd,
9157 "%s: QSFP supply voltage too high\n",
9158 __func__);
9159
9160 if ((qsfp_interrupt_status[1] & QSFP_LOW_VCC_ALARM) ||
9161 (qsfp_interrupt_status[1] & QSFP_LOW_VCC_WARNING))
9162 dd_dev_info(dd,
9163 "%s: QSFP supply voltage too low\n",
9164 __func__);
9165
9166 /* Byte 2 is vendor specific */
9167
9168 if ((qsfp_interrupt_status[3] & QSFP_HIGH_POWER_ALARM) ||
9169 (qsfp_interrupt_status[3] & QSFP_HIGH_POWER_WARNING))
9170 dd_dev_info(dd,
9171 "%s: Cable RX channel 1/2 power too high\n",
9172 __func__);
9173
9174 if ((qsfp_interrupt_status[3] & QSFP_LOW_POWER_ALARM) ||
9175 (qsfp_interrupt_status[3] & QSFP_LOW_POWER_WARNING))
9176 dd_dev_info(dd,
9177 "%s: Cable RX channel 1/2 power too low\n",
9178 __func__);
9179
9180 if ((qsfp_interrupt_status[4] & QSFP_HIGH_POWER_ALARM) ||
9181 (qsfp_interrupt_status[4] & QSFP_HIGH_POWER_WARNING))
9182 dd_dev_info(dd,
9183 "%s: Cable RX channel 3/4 power too high\n",
9184 __func__);
9185
9186 if ((qsfp_interrupt_status[4] & QSFP_LOW_POWER_ALARM) ||
9187 (qsfp_interrupt_status[4] & QSFP_LOW_POWER_WARNING))
9188 dd_dev_info(dd,
9189 "%s: Cable RX channel 3/4 power too low\n",
9190 __func__);
9191
9192 if ((qsfp_interrupt_status[5] & QSFP_HIGH_BIAS_ALARM) ||
9193 (qsfp_interrupt_status[5] & QSFP_HIGH_BIAS_WARNING))
9194 dd_dev_info(dd,
9195 "%s: Cable TX channel 1/2 bias too high\n",
9196 __func__);
9197
9198 if ((qsfp_interrupt_status[5] & QSFP_LOW_BIAS_ALARM) ||
9199 (qsfp_interrupt_status[5] & QSFP_LOW_BIAS_WARNING))
9200 dd_dev_info(dd,
9201 "%s: Cable TX channel 1/2 bias too low\n",
9202 __func__);
9203
9204 if ((qsfp_interrupt_status[6] & QSFP_HIGH_BIAS_ALARM) ||
9205 (qsfp_interrupt_status[6] & QSFP_HIGH_BIAS_WARNING))
9206 dd_dev_info(dd,
9207 "%s: Cable TX channel 3/4 bias too high\n",
9208 __func__);
9209
9210 if ((qsfp_interrupt_status[6] & QSFP_LOW_BIAS_ALARM) ||
9211 (qsfp_interrupt_status[6] & QSFP_LOW_BIAS_WARNING))
9212 dd_dev_info(dd,
9213 "%s: Cable TX channel 3/4 bias too low\n",
9214 __func__);
9215
9216 if ((qsfp_interrupt_status[7] & QSFP_HIGH_POWER_ALARM) ||
9217 (qsfp_interrupt_status[7] & QSFP_HIGH_POWER_WARNING))
9218 dd_dev_info(dd,
9219 "%s: Cable TX channel 1/2 power too high\n",
9220 __func__);
9221
9222 if ((qsfp_interrupt_status[7] & QSFP_LOW_POWER_ALARM) ||
9223 (qsfp_interrupt_status[7] & QSFP_LOW_POWER_WARNING))
9224 dd_dev_info(dd,
9225 "%s: Cable TX channel 1/2 power too low\n",
9226 __func__);
9227
9228 if ((qsfp_interrupt_status[8] & QSFP_HIGH_POWER_ALARM) ||
9229 (qsfp_interrupt_status[8] & QSFP_HIGH_POWER_WARNING))
9230 dd_dev_info(dd,
9231 "%s: Cable TX channel 3/4 power too high\n",
9232 __func__);
9233
9234 if ((qsfp_interrupt_status[8] & QSFP_LOW_POWER_ALARM) ||
9235 (qsfp_interrupt_status[8] & QSFP_LOW_POWER_WARNING))
9236 dd_dev_info(dd,
9237 "%s: Cable TX channel 3/4 power too low\n",
9238 __func__);
9239
9240 /* Bytes 9-10 and 11-12 are reserved */
9241 /* Bytes 13-15 are vendor specific */
9242
9243 return 0;
9244}
9245
77241056 9246/* This routine will only be scheduled if the QSFP module is present */
8ebd4cf1 9247void qsfp_event(struct work_struct *work)
77241056
MM		 9248{
9249 struct qsfp_data *qd;
9250 struct hfi1_pportdata *ppd;
9251 struct hfi1_devdata *dd;
9252
9253 qd = container_of(work, struct qsfp_data, qsfp_work);
9254 ppd = qd->ppd;
9255 dd = ppd->dd;
9256
9257 /* Sanity check */
9258 if (!qsfp_mod_present(ppd))
9259 return;
9260
9261 /*
9262 * Turn DC back on after cables has been
9263 * re-inserted. Up until now, the DC has been in
9264 * reset to save power.
9265 */
9266 dc_start(dd);
9267
9268 if (qd->cache_refresh_required) {
77241056 9269
8ebd4cf1
EH		 9270 set_qsfp_int_n(ppd, 0);
9271
9272 wait_for_qsfp_init(ppd);
9273
9274 /*
9275 * Allow INT_N to trigger the QSFP interrupt to watch
9276 * for alarms and warnings
77241056 9277 */
8ebd4cf1
EH		 9278 set_qsfp_int_n(ppd, 1);
9279
9280 tune_serdes(ppd);
9281
9282 start_link(ppd);
77241056
MM		 9283 }
9284
9285 if (qd->check_interrupt_flags) {
9286 u8 qsfp_interrupt_status[16] = {0,};
9287
9288 if (qsfp_read(ppd, dd->hfi1_id, 6,
9289 &qsfp_interrupt_status[0], 16) != 16) {
9290 dd_dev_info(dd,
9291 "%s: Failed to read status of QSFP module\n",
9292 __func__);
9293 } else {
9294 unsigned long flags;
77241056 9295
8ebd4cf1
EH		 9296 handle_qsfp_error_conditions(
9297 ppd, qsfp_interrupt_status);
77241056
MM		 9298 spin_lock_irqsave(&ppd->qsfp_info.qsfp_lock, flags);
9299 ppd->qsfp_info.check_interrupt_flags = 0;
9300 spin_unlock_irqrestore(&ppd->qsfp_info.qsfp_lock,
9301 flags);
77241056
MM		 9302 }
9303 }
9304}
9305
8ebd4cf1 9306static void init_qsfp_int(struct hfi1_devdata *dd)
77241056 9307{
8ebd4cf1
EH		 9308 struct hfi1_pportdata *ppd = dd->pport;
9309 u64 qsfp_mask, cce_int_mask;
9310 const int qsfp1_int_smask = QSFP1_INT % 64;
9311 const int qsfp2_int_smask = QSFP2_INT % 64;
77241056 9312
8ebd4cf1
EH		 9313 /*
9314 * disable QSFP1 interrupts for HFI1, QSFP2 interrupts for HFI0
9315 * Qsfp1Int and Qsfp2Int are adjacent bits in the same CSR,
9316 * therefore just one of QSFP1_INT/QSFP2_INT can be used to find
9317 * the index of the appropriate CSR in the CCEIntMask CSR array
9318 */
9319 cce_int_mask = read_csr(dd, CCE_INT_MASK +
9320 (8 * (QSFP1_INT / 64)));
9321 if (dd->hfi1_id) {
9322 cce_int_mask &= ~((u64)1 << qsfp1_int_smask);
9323 write_csr(dd, CCE_INT_MASK + (8 * (QSFP1_INT / 64)),
9324 cce_int_mask);
9325 } else {
9326 cce_int_mask &= ~((u64)1 << qsfp2_int_smask);
9327 write_csr(dd, CCE_INT_MASK + (8 * (QSFP2_INT / 64)),
9328 cce_int_mask);
77241056
MM		 9329 }
9330
77241056
MM		 9331 qsfp_mask = (u64)(QSFP_HFI0_INT_N | QSFP_HFI0_MODPRST_N);
9332 /* Clear current status to avoid spurious interrupts */
8ebd4cf1
EH		 9333 write_csr(dd, dd->hfi1_id ? ASIC_QSFP2_CLEAR : ASIC_QSFP1_CLEAR,
9334 qsfp_mask);
9335 write_csr(dd, dd->hfi1_id ? ASIC_QSFP2_MASK : ASIC_QSFP1_MASK,
9336 qsfp_mask);
9337
9338 set_qsfp_int_n(ppd, 0);
77241056
MM		 9339
9340 /* Handle active low nature of INT_N and MODPRST_N pins */
9341 if (qsfp_mod_present(ppd))
9342 qsfp_mask &= ~(u64)QSFP_HFI0_MODPRST_N;
9343 write_csr(dd,
9344 dd->hfi1_id ? ASIC_QSFP2_INVERT : ASIC_QSFP1_INVERT,
9345 qsfp_mask);
77241056
MM		 9346}
9347
bbdeb33d
DL		 9348/*
9349 * Do a one-time initialize of the LCB block.
9350 */
9351static void init_lcb(struct hfi1_devdata *dd)
9352{
a59329d5
DL		 9353 /* simulator does not correctly handle LCB cclk loopback, skip */
9354 if (dd->icode == ICODE_FUNCTIONAL_SIMULATOR)
9355 return;
9356
bbdeb33d
DL		 9357 /* the DC has been reset earlier in the driver load */
9358
9359 /* set LCB for cclk loopback on the port */
9360 write_csr(dd, DC_LCB_CFG_TX_FIFOS_RESET, 0x01);
9361 write_csr(dd, DC_LCB_CFG_LANE_WIDTH, 0x00);
9362 write_csr(dd, DC_LCB_CFG_REINIT_AS_SLAVE, 0x00);
9363 write_csr(dd, DC_LCB_CFG_CNT_FOR_SKIP_STALL, 0x110);
9364 write_csr(dd, DC_LCB_CFG_CLK_CNTR, 0x08);
9365 write_csr(dd, DC_LCB_CFG_LOOPBACK, 0x02);
9366 write_csr(dd, DC_LCB_CFG_TX_FIFOS_RESET, 0x00);
9367}
9368
77241056
MM		 9369int bringup_serdes(struct hfi1_pportdata *ppd)
9370{
9371 struct hfi1_devdata *dd = ppd->dd;
9372 u64 guid;
9373 int ret;
9374
9375 if (HFI1_CAP_IS_KSET(EXTENDED_PSN))
9376 add_rcvctrl(dd, RCV_CTRL_RCV_EXTENDED_PSN_ENABLE_SMASK);
9377
9378 guid = ppd->guid;
9379 if (!guid) {
9380 if (dd->base_guid)
9381 guid = dd->base_guid + ppd->port - 1;
9382 ppd->guid = guid;
9383 }
9384
77241056
MM		 9385 /* Set linkinit_reason on power up per OPA spec */
9386 ppd->linkinit_reason = OPA_LINKINIT_REASON_LINKUP;
9387
bbdeb33d
DL		 9388 /* one-time init of the LCB */
9389 init_lcb(dd);
9390
77241056
MM		 9391 if (loopback) {
9392 ret = init_loopback(dd);
9393 if (ret < 0)
9394 return ret;
9395 }
9396
8ebd4cf1
EH		 9397 /* tune the SERDES to a ballpark setting for
9398 * optimal signal and bit error rate
9399 * Needs to be done before starting the link
9400 */
9401 tune_serdes(ppd);
9402
77241056
MM		 9403 return start_link(ppd);
9404}
9405
9406void hfi1_quiet_serdes(struct hfi1_pportdata *ppd)
9407{
9408 struct hfi1_devdata *dd = ppd->dd;
9409
9410 /*
9411 * Shut down the link and keep it down. First turn off that the
9412 * driver wants to allow the link to be up (driver_link_ready).
9413 * Then make sure the link is not automatically restarted
9414 * (link_enabled). Cancel any pending restart. And finally
9415 * go offline.
9416 */
9417 ppd->driver_link_ready = 0;
9418 ppd->link_enabled = 0;
9419
8ebd4cf1
EH		 9420 ppd->offline_disabled_reason =
9421 HFI1_ODR_MASK(OPA_LINKDOWN_REASON_SMA_DISABLED);
77241056
MM		 9422 set_link_down_reason(ppd, OPA_LINKDOWN_REASON_SMA_DISABLED, 0,
9423 OPA_LINKDOWN_REASON_SMA_DISABLED);
9424 set_link_state(ppd, HLS_DN_OFFLINE);
9425
9426 /* disable the port */
9427 clear_rcvctrl(dd, RCV_CTRL_RCV_PORT_ENABLE_SMASK);
9428}
9429
9430static inline int init_cpu_counters(struct hfi1_devdata *dd)
9431{
9432 struct hfi1_pportdata *ppd;
9433 int i;
9434
9435 ppd = (struct hfi1_pportdata *)(dd + 1);
9436 for (i = 0; i < dd->num_pports; i++, ppd++) {
4eb06882
DD		 9437 ppd->ibport_data.rvp.rc_acks = NULL;
9438 ppd->ibport_data.rvp.rc_qacks = NULL;
9439 ppd->ibport_data.rvp.rc_acks = alloc_percpu(u64);
9440 ppd->ibport_data.rvp.rc_qacks = alloc_percpu(u64);
9441 ppd->ibport_data.rvp.rc_delayed_comp = alloc_percpu(u64);
9442 if (!ppd->ibport_data.rvp.rc_acks ||
9443 !ppd->ibport_data.rvp.rc_delayed_comp ||
9444 !ppd->ibport_data.rvp.rc_qacks)
77241056
MM		 9445 return -ENOMEM;
9446 }
9447
9448 return 0;
9449}
9450
9451static const char * const pt_names[] = {
9452 "expected",
9453 "eager",
9454 "invalid"
9455};
9456
9457static const char *pt_name(u32 type)
9458{
9459 return type >= ARRAY_SIZE(pt_names) ? "unknown" : pt_names[type];
9460}
9461
9462/*
9463 * index is the index into the receive array
9464 */
9465void hfi1_put_tid(struct hfi1_devdata *dd, u32 index,
9466 u32 type, unsigned long pa, u16 order)
9467{
9468 u64 reg;
9469 void __iomem *base = (dd->rcvarray_wc ? dd->rcvarray_wc :
9470 (dd->kregbase + RCV_ARRAY));
9471
9472 if (!(dd->flags & HFI1_PRESENT))
9473 goto done;
9474
9475 if (type == PT_INVALID) {
9476 pa = 0;
9477 } else if (type > PT_INVALID) {
9478 dd_dev_err(dd,
9479 "unexpected receive array type %u for index %u, not handled\n",
9480 type, index);
9481 goto done;
9482 }
9483
9484 hfi1_cdbg(TID, "type %s, index 0x%x, pa 0x%lx, bsize 0x%lx",
9485 pt_name(type), index, pa, (unsigned long)order);
9486
9487#define RT_ADDR_SHIFT 12 /* 4KB kernel address boundary */
9488 reg = RCV_ARRAY_RT_WRITE_ENABLE_SMASK
9489 | (u64)order << RCV_ARRAY_RT_BUF_SIZE_SHIFT
9490 | ((pa >> RT_ADDR_SHIFT) & RCV_ARRAY_RT_ADDR_MASK)
9491 << RCV_ARRAY_RT_ADDR_SHIFT;
9492 writeq(reg, base + (index * 8));
9493
9494 if (type == PT_EAGER)
9495 /*
9496 * Eager entries are written one-by-one so we have to push them
9497 * after we write the entry.
9498 */
9499 flush_wc();
9500done:
9501 return;
9502}
9503
9504void hfi1_clear_tids(struct hfi1_ctxtdata *rcd)
9505{
9506 struct hfi1_devdata *dd = rcd->dd;
9507 u32 i;
9508
9509 /* this could be optimized */
9510 for (i = rcd->eager_base; i < rcd->eager_base +
9511 rcd->egrbufs.alloced; i++)
9512 hfi1_put_tid(dd, i, PT_INVALID, 0, 0);
9513
9514 for (i = rcd->expected_base;
9515 i < rcd->expected_base + rcd->expected_count; i++)
9516 hfi1_put_tid(dd, i, PT_INVALID, 0, 0);
9517}
9518
9519int hfi1_get_base_kinfo(struct hfi1_ctxtdata *rcd,
9520 struct hfi1_ctxt_info *kinfo)
9521{
9522 kinfo->runtime_flags = (HFI1_MISC_GET() << HFI1_CAP_USER_SHIFT) |
9523 HFI1_CAP_UGET(MASK) | HFI1_CAP_KGET(K2U);
9524 return 0;
9525}
9526
9527struct hfi1_message_header *hfi1_get_msgheader(
9528 struct hfi1_devdata *dd, __le32 *rhf_addr)
9529{
9530 u32 offset = rhf_hdrq_offset(rhf_to_cpu(rhf_addr));
9531
9532 return (struct hfi1_message_header *)
9533 (rhf_addr - dd->rhf_offset + offset);
9534}
9535
9536static const char * const ib_cfg_name_strings[] = {
9537 "HFI1_IB_CFG_LIDLMC",
9538 "HFI1_IB_CFG_LWID_DG_ENB",
9539 "HFI1_IB_CFG_LWID_ENB",
9540 "HFI1_IB_CFG_LWID",
9541 "HFI1_IB_CFG_SPD_ENB",
9542 "HFI1_IB_CFG_SPD",
9543 "HFI1_IB_CFG_RXPOL_ENB",
9544 "HFI1_IB_CFG_LREV_ENB",
9545 "HFI1_IB_CFG_LINKLATENCY",
9546 "HFI1_IB_CFG_HRTBT",
9547 "HFI1_IB_CFG_OP_VLS",
9548 "HFI1_IB_CFG_VL_HIGH_CAP",
9549 "HFI1_IB_CFG_VL_LOW_CAP",
9550 "HFI1_IB_CFG_OVERRUN_THRESH",
9551 "HFI1_IB_CFG_PHYERR_THRESH",
9552 "HFI1_IB_CFG_LINKDEFAULT",
9553 "HFI1_IB_CFG_PKEYS",
9554 "HFI1_IB_CFG_MTU",
9555 "HFI1_IB_CFG_LSTATE",
9556 "HFI1_IB_CFG_VL_HIGH_LIMIT",
9557 "HFI1_IB_CFG_PMA_TICKS",
9558 "HFI1_IB_CFG_PORT"
9559};
9560
9561static const char *ib_cfg_name(int which)
9562{
9563 if (which < 0 || which >= ARRAY_SIZE(ib_cfg_name_strings))
9564 return "invalid";
9565 return ib_cfg_name_strings[which];
9566}
9567
9568int hfi1_get_ib_cfg(struct hfi1_pportdata *ppd, int which)
9569{
9570 struct hfi1_devdata *dd = ppd->dd;
9571 int val = 0;
9572
9573 switch (which) {
9574 case HFI1_IB_CFG_LWID_ENB: /* allowed Link-width */
9575 val = ppd->link_width_enabled;
9576 break;
9577 case HFI1_IB_CFG_LWID: /* currently active Link-width */
9578 val = ppd->link_width_active;
9579 break;
9580 case HFI1_IB_CFG_SPD_ENB: /* allowed Link speeds */
9581 val = ppd->link_speed_enabled;
9582 break;
9583 case HFI1_IB_CFG_SPD: /* current Link speed */
9584 val = ppd->link_speed_active;
9585 break;
9586
9587 case HFI1_IB_CFG_RXPOL_ENB: /* Auto-RX-polarity enable */
9588 case HFI1_IB_CFG_LREV_ENB: /* Auto-Lane-reversal enable */
9589 case HFI1_IB_CFG_LINKLATENCY:
9590 goto unimplemented;
9591
9592 case HFI1_IB_CFG_OP_VLS:
9593 val = ppd->vls_operational;
9594 break;
9595 case HFI1_IB_CFG_VL_HIGH_CAP: /* VL arb high priority table size */
9596 val = VL_ARB_HIGH_PRIO_TABLE_SIZE;
9597 break;
9598 case HFI1_IB_CFG_VL_LOW_CAP: /* VL arb low priority table size */
9599 val = VL_ARB_LOW_PRIO_TABLE_SIZE;
9600 break;
9601 case HFI1_IB_CFG_OVERRUN_THRESH: /* IB overrun threshold */
9602 val = ppd->overrun_threshold;
9603 break;
9604 case HFI1_IB_CFG_PHYERR_THRESH: /* IB PHY error threshold */
9605 val = ppd->phy_error_threshold;
9606 break;
9607 case HFI1_IB_CFG_LINKDEFAULT: /* IB link default (sleep/poll) */
9608 val = dd->link_default;
9609 break;
9610
9611 case HFI1_IB_CFG_HRTBT: /* Heartbeat off/enable/auto */
9612 case HFI1_IB_CFG_PMA_TICKS:
9613 default:
9614unimplemented:
9615 if (HFI1_CAP_IS_KSET(PRINT_UNIMPL))
9616 dd_dev_info(
9617 dd,
9618 "%s: which %s: not implemented\n",
9619 __func__,
9620 ib_cfg_name(which));
9621 break;
9622 }
9623
9624 return val;
9625}
9626
9627/*
9628 * The largest MAD packet size.
9629 */
9630#define MAX_MAD_PACKET 2048
9631
9632/*
9633 * Return the maximum header bytes that can go on the _wire_
9634 * for this device. This count includes the ICRC which is
9635 * not part of the packet held in memory but it is appended
9636 * by the HW.
9637 * This is dependent on the device's receive header entry size.
9638 * HFI allows this to be set per-receive context, but the
9639 * driver presently enforces a global value.
9640 */
9641u32 lrh_max_header_bytes(struct hfi1_devdata *dd)
9642{
9643 /*
9644 * The maximum non-payload (MTU) bytes in LRH.PktLen are
9645 * the Receive Header Entry Size minus the PBC (or RHF) size
9646 * plus one DW for the ICRC appended by HW.
9647 *
9648 * dd->rcd[0].rcvhdrqentsize is in DW.
9649 * We use rcd[0] as all context will have the same value. Also,
9650 * the first kernel context would have been allocated by now so
9651 * we are guaranteed a valid value.
9652 */
9653 return (dd->rcd[0]->rcvhdrqentsize - 2/*PBC/RHF*/ + 1/*ICRC*/) << 2;
9654}
9655
9656/*
9657 * Set Send Length
9658 * @ppd - per port data
9659 *
9660 * Set the MTU by limiting how many DWs may be sent. The SendLenCheck*
9661 * registers compare against LRH.PktLen, so use the max bytes included
9662 * in the LRH.
9663 *
9664 * This routine changes all VL values except VL15, which it maintains at
9665 * the same value.
9666 */
9667static void set_send_length(struct hfi1_pportdata *ppd)
9668{
9669 struct hfi1_devdata *dd = ppd->dd;
6cc6ad2e
HC		 9670 u32 max_hb = lrh_max_header_bytes(dd), dcmtu;
9671 u32 maxvlmtu = dd->vld[15].mtu;
77241056
MM		 9672 u64 len1 = 0, len2 = (((dd->vld[15].mtu + max_hb) >> 2)
9673 & SEND_LEN_CHECK1_LEN_VL15_MASK) <<
9674 SEND_LEN_CHECK1_LEN_VL15_SHIFT;
9675 int i;
9676
9677 for (i = 0; i < ppd->vls_supported; i++) {
9678 if (dd->vld[i].mtu > maxvlmtu)
9679 maxvlmtu = dd->vld[i].mtu;
9680 if (i <= 3)
9681 len1 |= (((dd->vld[i].mtu + max_hb) >> 2)
9682 & SEND_LEN_CHECK0_LEN_VL0_MASK) <<
9683 ((i % 4) * SEND_LEN_CHECK0_LEN_VL1_SHIFT);
9684 else
9685 len2 |= (((dd->vld[i].mtu + max_hb) >> 2)
9686 & SEND_LEN_CHECK1_LEN_VL4_MASK) <<
9687 ((i % 4) * SEND_LEN_CHECK1_LEN_VL5_SHIFT);
9688 }
9689 write_csr(dd, SEND_LEN_CHECK0, len1);
9690 write_csr(dd, SEND_LEN_CHECK1, len2);
9691 /* adjust kernel credit return thresholds based on new MTUs */
9692 /* all kernel receive contexts have the same hdrqentsize */
9693 for (i = 0; i < ppd->vls_supported; i++) {
9694 sc_set_cr_threshold(dd->vld[i].sc,
9695 sc_mtu_to_threshold(dd->vld[i].sc, dd->vld[i].mtu,
9696 dd->rcd[0]->rcvhdrqentsize));
9697 }
9698 sc_set_cr_threshold(dd->vld[15].sc,
9699 sc_mtu_to_threshold(dd->vld[15].sc, dd->vld[15].mtu,
9700 dd->rcd[0]->rcvhdrqentsize));
9701
9702 /* Adjust maximum MTU for the port in DC */
9703 dcmtu = maxvlmtu == 10240 ? DCC_CFG_PORT_MTU_CAP_10240 :
9704 (ilog2(maxvlmtu >> 8) + 1);
9705 len1 = read_csr(ppd->dd, DCC_CFG_PORT_CONFIG);
9706 len1 &= ~DCC_CFG_PORT_CONFIG_MTU_CAP_SMASK;
9707 len1 |= ((u64)dcmtu & DCC_CFG_PORT_CONFIG_MTU_CAP_MASK) <<
9708 DCC_CFG_PORT_CONFIG_MTU_CAP_SHIFT;
9709 write_csr(ppd->dd, DCC_CFG_PORT_CONFIG, len1);
9710}
9711
9712static void set_lidlmc(struct hfi1_pportdata *ppd)
9713{
9714 int i;
9715 u64 sreg = 0;
9716 struct hfi1_devdata *dd = ppd->dd;
9717 u32 mask = ~((1U << ppd->lmc) - 1);
9718 u64 c1 = read_csr(ppd->dd, DCC_CFG_PORT_CONFIG1);
9719
9720 if (dd->hfi1_snoop.mode_flag)
9721 dd_dev_info(dd, "Set lid/lmc while snooping");
9722
9723 c1 &= ~(DCC_CFG_PORT_CONFIG1_TARGET_DLID_SMASK
9724 | DCC_CFG_PORT_CONFIG1_DLID_MASK_SMASK);
9725 c1 |= ((ppd->lid & DCC_CFG_PORT_CONFIG1_TARGET_DLID_MASK)
8638b77f 9726 << DCC_CFG_PORT_CONFIG1_TARGET_DLID_SHIFT) |
77241056
MM		 9727 ((mask & DCC_CFG_PORT_CONFIG1_DLID_MASK_MASK)
9728 << DCC_CFG_PORT_CONFIG1_DLID_MASK_SHIFT);
9729 write_csr(ppd->dd, DCC_CFG_PORT_CONFIG1, c1);
9730
9731 /*
9732 * Iterate over all the send contexts and set their SLID check
9733 */
9734 sreg = ((mask & SEND_CTXT_CHECK_SLID_MASK_MASK) <<
9735 SEND_CTXT_CHECK_SLID_MASK_SHIFT) |
9736 (((ppd->lid & mask) & SEND_CTXT_CHECK_SLID_VALUE_MASK) <<
9737 SEND_CTXT_CHECK_SLID_VALUE_SHIFT);
9738
9739 for (i = 0; i < dd->chip_send_contexts; i++) {
9740 hfi1_cdbg(LINKVERB, "SendContext[%d].SLID_CHECK = 0x%x",
9741 i, (u32)sreg);
9742 write_kctxt_csr(dd, i, SEND_CTXT_CHECK_SLID, sreg);
9743 }
9744
9745 /* Now we have to do the same thing for the sdma engines */
9746 sdma_update_lmc(dd, mask, ppd->lid);
9747}
9748
9749static int wait_phy_linkstate(struct hfi1_devdata *dd, u32 state, u32 msecs)
9750{
9751 unsigned long timeout;
9752 u32 curr_state;
9753
9754 timeout = jiffies + msecs_to_jiffies(msecs);
9755 while (1) {
9756 curr_state = read_physical_state(dd);
9757 if (curr_state == state)
9758 break;
9759 if (time_after(jiffies, timeout)) {
9760 dd_dev_err(dd,
9761 "timeout waiting for phy link state 0x%x, current state is 0x%x\n",
9762 state, curr_state);
9763 return -ETIMEDOUT;
9764 }
9765 usleep_range(1950, 2050); /* sleep 2ms-ish */
9766 }
9767
9768 return 0;
9769}
9770
9771/*
9772 * Helper for set_link_state(). Do not call except from that routine.
9773 * Expects ppd->hls_mutex to be held.
9774 *
9775 * @rem_reason value to be sent to the neighbor
9776 *
9777 * LinkDownReasons only set if transition succeeds.
9778 */
9779static int goto_offline(struct hfi1_pportdata *ppd, u8 rem_reason)
9780{
9781 struct hfi1_devdata *dd = ppd->dd;
9782 u32 pstate, previous_state;
9783 u32 last_local_state;
9784 u32 last_remote_state;
9785 int ret;
9786 int do_transition;
9787 int do_wait;
9788
9789 previous_state = ppd->host_link_state;
9790 ppd->host_link_state = HLS_GOING_OFFLINE;
9791 pstate = read_physical_state(dd);
9792 if (pstate == PLS_OFFLINE) {
9793 do_transition = 0; /* in right state */
9794 do_wait = 0; /* ...no need to wait */
9795 } else if ((pstate & 0xff) == PLS_OFFLINE) {
9796 do_transition = 0; /* in an offline transient state */
9797 do_wait = 1; /* ...wait for it to settle */
9798 } else {
9799 do_transition = 1; /* need to move to offline */
9800 do_wait = 1; /* ...will need to wait */
9801 }
9802
9803 if (do_transition) {
9804 ret = set_physical_link_state(dd,
9805 PLS_OFFLINE | (rem_reason << 8));
9806
9807 if (ret != HCMD_SUCCESS) {
9808 dd_dev_err(dd,
9809 "Failed to transition to Offline link state, return %d\n",
9810 ret);
9811 return -EINVAL;
9812 }
a9c05e35
BM		 9813 if (ppd->offline_disabled_reason ==
9814 HFI1_ODR_MASK(OPA_LINKDOWN_REASON_NONE))
77241056 9815 ppd->offline_disabled_reason =
a9c05e35 9816 HFI1_ODR_MASK(OPA_LINKDOWN_REASON_TRANSIENT);
77241056
MM		 9817 }
9818
9819 if (do_wait) {
9820 /* it can take a while for the link to go down */
dc060245 9821 ret = wait_phy_linkstate(dd, PLS_OFFLINE, 10000);
77241056
MM		 9822 if (ret < 0)
9823 return ret;
9824 }
9825
9826 /* make sure the logical state is also down */
9827 wait_logical_linkstate(ppd, IB_PORT_DOWN, 1000);
9828
9829 /*
9830 * Now in charge of LCB - must be after the physical state is
9831 * offline.quiet and before host_link_state is changed.
9832 */
9833 set_host_lcb_access(dd);
9834 write_csr(dd, DC_LCB_ERR_EN, ~0ull); /* watch LCB errors */
9835 ppd->host_link_state = HLS_LINK_COOLDOWN; /* LCB access allowed */
9836
8ebd4cf1
EH		 9837 if (ppd->port_type == PORT_TYPE_QSFP &&
9838 ppd->qsfp_info.limiting_active &&
9839 qsfp_mod_present(ppd)) {
9840 set_qsfp_tx(ppd, 0);
9841 }
9842
77241056
MM		 9843 /*
9844 * The LNI has a mandatory wait time after the physical state
9845 * moves to Offline.Quiet. The wait time may be different
9846 * depending on how the link went down. The 8051 firmware
9847 * will observe the needed wait time and only move to ready
9848 * when that is completed. The largest of the quiet timeouts
05087f3b
DL		 9849 * is 6s, so wait that long and then at least 0.5s more for
9850 * other transitions, and another 0.5s for a buffer.
77241056 9851 */
05087f3b 9852 ret = wait_fm_ready(dd, 7000);
77241056
MM		 9853 if (ret) {
9854 dd_dev_err(dd,
9855 "After going offline, timed out waiting for the 8051 to become ready to accept host requests\n");
9856 /* state is really offline, so make it so */
9857 ppd->host_link_state = HLS_DN_OFFLINE;
9858 return ret;
9859 }
9860
9861 /*
9862 * The state is now offline and the 8051 is ready to accept host
9863 * requests.
9864 * - change our state
9865 * - notify others if we were previously in a linkup state
9866 */
9867 ppd->host_link_state = HLS_DN_OFFLINE;
9868 if (previous_state & HLS_UP) {
9869 /* went down while link was up */
9870 handle_linkup_change(dd, 0);
9871 } else if (previous_state
9872 & (HLS_DN_POLL | HLS_VERIFY_CAP | HLS_GOING_UP)) {
9873 /* went down while attempting link up */
9874 /* byte 1 of last_*_state is the failure reason */
9875 read_last_local_state(dd, &last_local_state);
9876 read_last_remote_state(dd, &last_remote_state);
9877 dd_dev_err(dd,
9878 "LNI failure last states: local 0x%08x, remote 0x%08x\n",
9879 last_local_state, last_remote_state);
9880 }
9881
9882 /* the active link width (downgrade) is 0 on link down */
9883 ppd->link_width_active = 0;
9884 ppd->link_width_downgrade_tx_active = 0;
9885 ppd->link_width_downgrade_rx_active = 0;
9886 ppd->current_egress_rate = 0;
9887 return 0;
9888}
9889
9890/* return the link state name */
9891static const char *link_state_name(u32 state)
9892{
9893 const char *name;
9894 int n = ilog2(state);
9895 static const char * const names[] = {
9896 [__HLS_UP_INIT_BP] = "INIT",
9897 [__HLS_UP_ARMED_BP] = "ARMED",
9898 [__HLS_UP_ACTIVE_BP] = "ACTIVE",
9899 [__HLS_DN_DOWNDEF_BP] = "DOWNDEF",
9900 [__HLS_DN_POLL_BP] = "POLL",
9901 [__HLS_DN_DISABLE_BP] = "DISABLE",
9902 [__HLS_DN_OFFLINE_BP] = "OFFLINE",
9903 [__HLS_VERIFY_CAP_BP] = "VERIFY_CAP",
9904 [__HLS_GOING_UP_BP] = "GOING_UP",
9905 [__HLS_GOING_OFFLINE_BP] = "GOING_OFFLINE",
9906 [__HLS_LINK_COOLDOWN_BP] = "LINK_COOLDOWN"
9907 };
9908
9909 name = n < ARRAY_SIZE(names) ? names[n] : NULL;
9910 return name ? name : "unknown";
9911}
9912
9913/* return the link state reason name */
9914static const char *link_state_reason_name(struct hfi1_pportdata *ppd, u32 state)
9915{
9916 if (state == HLS_UP_INIT) {
9917 switch (ppd->linkinit_reason) {
9918 case OPA_LINKINIT_REASON_LINKUP:
9919 return "(LINKUP)";
9920 case OPA_LINKINIT_REASON_FLAPPING:
9921 return "(FLAPPING)";
9922 case OPA_LINKINIT_OUTSIDE_POLICY:
9923 return "(OUTSIDE_POLICY)";
9924 case OPA_LINKINIT_QUARANTINED:
9925 return "(QUARANTINED)";
9926 case OPA_LINKINIT_INSUFIC_CAPABILITY:
9927 return "(INSUFIC_CAPABILITY)";
9928 default:
9929 break;
9930 }
9931 }
9932 return "";
9933}
9934
9935/*
9936 * driver_physical_state - convert the driver's notion of a port's
9937 * state (an HLS_*) into a physical state (a {IB,OPA}_PORTPHYSSTATE_*).
9938 * Return -1 (converted to a u32) to indicate error.
9939 */
9940u32 driver_physical_state(struct hfi1_pportdata *ppd)
9941{
9942 switch (ppd->host_link_state) {
9943 case HLS_UP_INIT:
9944 case HLS_UP_ARMED:
9945 case HLS_UP_ACTIVE:
9946 return IB_PORTPHYSSTATE_LINKUP;
9947 case HLS_DN_POLL:
9948 return IB_PORTPHYSSTATE_POLLING;
9949 case HLS_DN_DISABLE:
9950 return IB_PORTPHYSSTATE_DISABLED;
9951 case HLS_DN_OFFLINE:
9952 return OPA_PORTPHYSSTATE_OFFLINE;
9953 case HLS_VERIFY_CAP:
9954 return IB_PORTPHYSSTATE_POLLING;
9955 case HLS_GOING_UP:
9956 return IB_PORTPHYSSTATE_POLLING;
9957 case HLS_GOING_OFFLINE:
9958 return OPA_PORTPHYSSTATE_OFFLINE;
9959 case HLS_LINK_COOLDOWN:
9960 return OPA_PORTPHYSSTATE_OFFLINE;
9961 case HLS_DN_DOWNDEF:
9962 default:
9963 dd_dev_err(ppd->dd, "invalid host_link_state 0x%x\n",
9964 ppd->host_link_state);
9965 return -1;
9966 }
9967}
9968
9969/*
9970 * driver_logical_state - convert the driver's notion of a port's
9971 * state (an HLS_*) into a logical state (a IB_PORT_*). Return -1
9972 * (converted to a u32) to indicate error.
9973 */
9974u32 driver_logical_state(struct hfi1_pportdata *ppd)
9975{
9976 if (ppd->host_link_state && !(ppd->host_link_state & HLS_UP))
9977 return IB_PORT_DOWN;
9978
9979 switch (ppd->host_link_state & HLS_UP) {
9980 case HLS_UP_INIT:
9981 return IB_PORT_INIT;
9982 case HLS_UP_ARMED:
9983 return IB_PORT_ARMED;
9984 case HLS_UP_ACTIVE:
9985 return IB_PORT_ACTIVE;
9986 default:
9987 dd_dev_err(ppd->dd, "invalid host_link_state 0x%x\n",
9988 ppd->host_link_state);
9989 return -1;
9990 }
9991}
9992
9993void set_link_down_reason(struct hfi1_pportdata *ppd, u8 lcl_reason,
9994 u8 neigh_reason, u8 rem_reason)
9995{
9996 if (ppd->local_link_down_reason.latest == 0 &&
9997 ppd->neigh_link_down_reason.latest == 0) {
9998 ppd->local_link_down_reason.latest = lcl_reason;
9999 ppd->neigh_link_down_reason.latest = neigh_reason;
10000 ppd->remote_link_down_reason = rem_reason;
10001 }
10002}
10003
10004/*
10005 * Change the physical and/or logical link state.
10006 *
10007 * Do not call this routine while inside an interrupt. It contains
10008 * calls to routines that can take multiple seconds to finish.
10009 *
10010 * Returns 0 on success, -errno on failure.
10011 */
10012int set_link_state(struct hfi1_pportdata *ppd, u32 state)
10013{
10014 struct hfi1_devdata *dd = ppd->dd;
10015 struct ib_event event = {.device = NULL};
10016 int ret1, ret = 0;
10017 int was_up, is_down;
10018 int orig_new_state, poll_bounce;
10019
10020 mutex_lock(&ppd->hls_lock);
10021
10022 orig_new_state = state;
10023 if (state == HLS_DN_DOWNDEF)
10024 state = dd->link_default;
10025
10026 /* interpret poll -> poll as a link bounce */
10027 poll_bounce = ppd->host_link_state == HLS_DN_POLL
10028 && state == HLS_DN_POLL;
10029
10030 dd_dev_info(dd, "%s: current %s, new %s %s%s\n", __func__,
10031 link_state_name(ppd->host_link_state),
10032 link_state_name(orig_new_state),
10033 poll_bounce ? "(bounce) " : "",
10034 link_state_reason_name(ppd, state));
10035
10036 was_up = !!(ppd->host_link_state & HLS_UP);
10037
10038 /*
10039 * If we're going to a (HLS_*) link state that implies the logical
10040 * link state is neither of (IB_PORT_ARMED, IB_PORT_ACTIVE), then
10041 * reset is_sm_config_started to 0.
10042 */
10043 if (!(state & (HLS_UP_ARMED | HLS_UP_ACTIVE)))
10044 ppd->is_sm_config_started = 0;
10045
10046 /*
10047 * Do nothing if the states match. Let a poll to poll link bounce
10048 * go through.
10049 */
10050 if (ppd->host_link_state == state && !poll_bounce)
10051 goto done;
10052
10053 switch (state) {
10054 case HLS_UP_INIT:
10055 if (ppd->host_link_state == HLS_DN_POLL && (quick_linkup
10056 || dd->icode == ICODE_FUNCTIONAL_SIMULATOR)) {
10057 /*
10058 * Quick link up jumps from polling to here.
10059 *
10060 * Whether in normal or loopback mode, the
10061 * simulator jumps from polling to link up.
10062 * Accept that here.
10063 */
10064 /* OK */;
10065 } else if (ppd->host_link_state != HLS_GOING_UP) {
10066 goto unexpected;
10067 }
10068
10069 ppd->host_link_state = HLS_UP_INIT;
10070 ret = wait_logical_linkstate(ppd, IB_PORT_INIT, 1000);
10071 if (ret) {
10072 /* logical state didn't change, stay at going_up */
10073 ppd->host_link_state = HLS_GOING_UP;
10074 dd_dev_err(dd,
10075 "%s: logical state did not change to INIT\n",
10076 __func__);
10077 } else {
10078 /* clear old transient LINKINIT_REASON code */
10079 if (ppd->linkinit_reason >= OPA_LINKINIT_REASON_CLEAR)
10080 ppd->linkinit_reason =
10081 OPA_LINKINIT_REASON_LINKUP;
10082
10083 /* enable the port */
10084 add_rcvctrl(dd, RCV_CTRL_RCV_PORT_ENABLE_SMASK);
10085
10086 handle_linkup_change(dd, 1);
10087 }
10088 break;
10089 case HLS_UP_ARMED:
10090 if (ppd->host_link_state != HLS_UP_INIT)
10091 goto unexpected;
10092
10093 ppd->host_link_state = HLS_UP_ARMED;
10094 set_logical_state(dd, LSTATE_ARMED);
10095 ret = wait_logical_linkstate(ppd, IB_PORT_ARMED, 1000);
10096 if (ret) {
10097 /* logical state didn't change, stay at init */
10098 ppd->host_link_state = HLS_UP_INIT;
10099 dd_dev_err(dd,
10100 "%s: logical state did not change to ARMED\n",
10101 __func__);
10102 }
10103 /*
10104 * The simulator does not currently implement SMA messages,
10105 * so neighbor_normal is not set. Set it here when we first
10106 * move to Armed.
10107 */
10108 if (dd->icode == ICODE_FUNCTIONAL_SIMULATOR)
10109 ppd->neighbor_normal = 1;
10110 break;
10111 case HLS_UP_ACTIVE:
10112 if (ppd->host_link_state != HLS_UP_ARMED)
10113 goto unexpected;
10114
10115 ppd->host_link_state = HLS_UP_ACTIVE;
10116 set_logical_state(dd, LSTATE_ACTIVE);
10117 ret = wait_logical_linkstate(ppd, IB_PORT_ACTIVE, 1000);
10118 if (ret) {
10119 /* logical state didn't change, stay at armed */
10120 ppd->host_link_state = HLS_UP_ARMED;
10121 dd_dev_err(dd,
10122 "%s: logical state did not change to ACTIVE\n",
10123 __func__);
10124 } else {
10125
10126 /* tell all engines to go running */
10127 sdma_all_running(dd);
10128
10129 /* Signal the IB layer that the port has went active */
ec3f2c12 10130 event.device = &dd->verbs_dev.rdi.ibdev;
77241056
MM		 10131 event.element.port_num = ppd->port;
10132 event.event = IB_EVENT_PORT_ACTIVE;
10133 }
10134 break;
10135 case HLS_DN_POLL:
10136 if ((ppd->host_link_state == HLS_DN_DISABLE ||
10137 ppd->host_link_state == HLS_DN_OFFLINE) &&
10138 dd->dc_shutdown)
10139 dc_start(dd);
10140 /* Hand LED control to the DC */
10141 write_csr(dd, DCC_CFG_LED_CNTRL, 0);
10142
10143 if (ppd->host_link_state != HLS_DN_OFFLINE) {
10144 u8 tmp = ppd->link_enabled;
10145
10146 ret = goto_offline(ppd, ppd->remote_link_down_reason);
10147 if (ret) {
10148 ppd->link_enabled = tmp;
10149 break;
10150 }
10151 ppd->remote_link_down_reason = 0;
10152
10153 if (ppd->driver_link_ready)
10154 ppd->link_enabled = 1;
10155 }
10156
fb9036dd 10157 set_all_slowpath(ppd->dd);
77241056
MM		 10158 ret = set_local_link_attributes(ppd);
10159 if (ret)
10160 break;
10161
10162 ppd->port_error_action = 0;
10163 ppd->host_link_state = HLS_DN_POLL;
10164
10165 if (quick_linkup) {
10166 /* quick linkup does not go into polling */
10167 ret = do_quick_linkup(dd);
10168 } else {
10169 ret1 = set_physical_link_state(dd, PLS_POLLING);
10170 if (ret1 != HCMD_SUCCESS) {
10171 dd_dev_err(dd,
10172 "Failed to transition to Polling link state, return 0x%x\n",
10173 ret1);
10174 ret = -EINVAL;
10175 }
10176 }
a9c05e35
BM		 10177 ppd->offline_disabled_reason =
10178 HFI1_ODR_MASK(OPA_LINKDOWN_REASON_NONE);
77241056
MM		 10179 /*
10180 * If an error occurred above, go back to offline. The
10181 * caller may reschedule another attempt.
10182 */
10183 if (ret)
10184 goto_offline(ppd, 0);
10185 break;
10186 case HLS_DN_DISABLE:
10187 /* link is disabled */
10188 ppd->link_enabled = 0;
10189
10190 /* allow any state to transition to disabled */
10191
10192 /* must transition to offline first */
10193 if (ppd->host_link_state != HLS_DN_OFFLINE) {
10194 ret = goto_offline(ppd, ppd->remote_link_down_reason);
10195 if (ret)
10196 break;
10197 ppd->remote_link_down_reason = 0;
10198 }
10199
10200 ret1 = set_physical_link_state(dd, PLS_DISABLED);
10201 if (ret1 != HCMD_SUCCESS) {
10202 dd_dev_err(dd,
10203 "Failed to transition to Disabled link state, return 0x%x\n",
10204 ret1);
10205 ret = -EINVAL;
10206 break;
10207 }
10208 ppd->host_link_state = HLS_DN_DISABLE;
10209 dc_shutdown(dd);
10210 break;
10211 case HLS_DN_OFFLINE:
10212 if (ppd->host_link_state == HLS_DN_DISABLE)
10213 dc_start(dd);
10214
10215 /* allow any state to transition to offline */
10216 ret = goto_offline(ppd, ppd->remote_link_down_reason);
10217 if (!ret)
10218 ppd->remote_link_down_reason = 0;
10219 break;
10220 case HLS_VERIFY_CAP:
10221 if (ppd->host_link_state != HLS_DN_POLL)
10222 goto unexpected;
10223 ppd->host_link_state = HLS_VERIFY_CAP;
10224 break;
10225 case HLS_GOING_UP:
10226 if (ppd->host_link_state != HLS_VERIFY_CAP)
10227 goto unexpected;
10228
10229 ret1 = set_physical_link_state(dd, PLS_LINKUP);
10230 if (ret1 != HCMD_SUCCESS) {
10231 dd_dev_err(dd,
10232 "Failed to transition to link up state, return 0x%x\n",
10233 ret1);
10234 ret = -EINVAL;
10235 break;
10236 }
10237 ppd->host_link_state = HLS_GOING_UP;
10238 break;
10239
10240 case HLS_GOING_OFFLINE: /* transient within goto_offline() */
10241 case HLS_LINK_COOLDOWN: /* transient within goto_offline() */
10242 default:
10243 dd_dev_info(dd, "%s: state 0x%x: not supported\n",
10244 __func__, state);
10245 ret = -EINVAL;
10246 break;
10247 }
10248
10249 is_down = !!(ppd->host_link_state & (HLS_DN_POLL |
10250 HLS_DN_DISABLE | HLS_DN_OFFLINE));
10251
10252 if (was_up && is_down && ppd->local_link_down_reason.sma == 0 &&
10253 ppd->neigh_link_down_reason.sma == 0) {
10254 ppd->local_link_down_reason.sma =
10255 ppd->local_link_down_reason.latest;
10256 ppd->neigh_link_down_reason.sma =
10257 ppd->neigh_link_down_reason.latest;
10258 }
10259
10260 goto done;
10261
10262unexpected:
10263 dd_dev_err(dd, "%s: unexpected state transition from %s to %s\n",
10264 __func__, link_state_name(ppd->host_link_state),
10265 link_state_name(state));
10266 ret = -EINVAL;
10267
10268done:
10269 mutex_unlock(&ppd->hls_lock);
10270
10271 if (event.device)
10272 ib_dispatch_event(&event);
10273
10274 return ret;
10275}
10276
10277int hfi1_set_ib_cfg(struct hfi1_pportdata *ppd, int which, u32 val)
10278{
10279 u64 reg;
10280 int ret = 0;
10281
10282 switch (which) {
10283 case HFI1_IB_CFG_LIDLMC:
10284 set_lidlmc(ppd);
10285 break;
10286 case HFI1_IB_CFG_VL_HIGH_LIMIT:
10287 /*
10288 * The VL Arbitrator high limit is sent in units of 4k
10289 * bytes, while HFI stores it in units of 64 bytes.
10290 */
8638b77f 10291 val *= 4096 / 64;
77241056
MM		 10292 reg = ((u64)val & SEND_HIGH_PRIORITY_LIMIT_LIMIT_MASK)
10293 << SEND_HIGH_PRIORITY_LIMIT_LIMIT_SHIFT;
10294 write_csr(ppd->dd, SEND_HIGH_PRIORITY_LIMIT, reg);
10295 break;
10296 case HFI1_IB_CFG_LINKDEFAULT: /* IB link default (sleep/poll) */
10297 /* HFI only supports POLL as the default link down state */
10298 if (val != HLS_DN_POLL)
10299 ret = -EINVAL;
10300 break;
10301 case HFI1_IB_CFG_OP_VLS:
10302 if (ppd->vls_operational != val) {
10303 ppd->vls_operational = val;
10304 if (!ppd->port)
10305 ret = -EINVAL;
77241056
MM		 10306 }
10307 break;
10308 /*
10309 * For link width, link width downgrade, and speed enable, always AND
10310 * the setting with what is actually supported. This has two benefits.
10311 * First, enabled can't have unsupported values, no matter what the
10312 * SM or FM might want. Second, the ALL_SUPPORTED wildcards that mean
10313 * "fill in with your supported value" have all the bits in the
10314 * field set, so simply ANDing with supported has the desired result.
10315 */
10316 case HFI1_IB_CFG_LWID_ENB: /* set allowed Link-width */
10317 ppd->link_width_enabled = val & ppd->link_width_supported;
10318 break;
10319 case HFI1_IB_CFG_LWID_DG_ENB: /* set allowed link width downgrade */
10320 ppd->link_width_downgrade_enabled =
10321 val & ppd->link_width_downgrade_supported;
10322 break;
10323 case HFI1_IB_CFG_SPD_ENB: /* allowed Link speeds */
10324 ppd->link_speed_enabled = val & ppd->link_speed_supported;
10325 break;
10326 case HFI1_IB_CFG_OVERRUN_THRESH: /* IB overrun threshold */
10327 /*
10328 * HFI does not follow IB specs, save this value
10329 * so we can report it, if asked.
10330 */
10331 ppd->overrun_threshold = val;
10332 break;
10333 case HFI1_IB_CFG_PHYERR_THRESH: /* IB PHY error threshold */
10334 /*
10335 * HFI does not follow IB specs, save this value
10336 * so we can report it, if asked.
10337 */
10338 ppd->phy_error_threshold = val;
10339 break;
10340
10341 case HFI1_IB_CFG_MTU:
10342 set_send_length(ppd);
10343 break;
10344
10345 case HFI1_IB_CFG_PKEYS:
10346 if (HFI1_CAP_IS_KSET(PKEY_CHECK))
10347 set_partition_keys(ppd);
10348 break;
10349
10350 default:
10351 if (HFI1_CAP_IS_KSET(PRINT_UNIMPL))
10352 dd_dev_info(ppd->dd,
10353 "%s: which %s, val 0x%x: not implemented\n",
10354 __func__, ib_cfg_name(which), val);
10355 break;
10356 }
10357 return ret;
10358}
10359
10360/* begin functions related to vl arbitration table caching */
10361static void init_vl_arb_caches(struct hfi1_pportdata *ppd)
10362{
10363 int i;
10364
10365 BUILD_BUG_ON(VL_ARB_TABLE_SIZE !=
10366 VL_ARB_LOW_PRIO_TABLE_SIZE);
10367 BUILD_BUG_ON(VL_ARB_TABLE_SIZE !=
10368 VL_ARB_HIGH_PRIO_TABLE_SIZE);
10369
10370 /*
10371 * Note that we always return values directly from the
10372 * 'vl_arb_cache' (and do no CSR reads) in response to a
10373 * 'Get(VLArbTable)'. This is obviously correct after a
10374 * 'Set(VLArbTable)', since the cache will then be up to
10375 * date. But it's also correct prior to any 'Set(VLArbTable)'
10376 * since then both the cache, and the relevant h/w registers
10377 * will be zeroed.
10378 */
10379
10380 for (i = 0; i < MAX_PRIO_TABLE; i++)
10381 spin_lock_init(&ppd->vl_arb_cache[i].lock);
10382}
10383
10384/*
10385 * vl_arb_lock_cache
10386 *
10387 * All other vl_arb_* functions should be called only after locking
10388 * the cache.
10389 */
10390static inline struct vl_arb_cache *
10391vl_arb_lock_cache(struct hfi1_pportdata *ppd, int idx)
10392{
10393 if (idx != LO_PRIO_TABLE && idx != HI_PRIO_TABLE)
10394 return NULL;
10395 spin_lock(&ppd->vl_arb_cache[idx].lock);
10396 return &ppd->vl_arb_cache[idx];
10397}
10398
10399static inline void vl_arb_unlock_cache(struct hfi1_pportdata *ppd, int idx)
10400{
10401 spin_unlock(&ppd->vl_arb_cache[idx].lock);
10402}
10403
10404static void vl_arb_get_cache(struct vl_arb_cache *cache,
10405 struct ib_vl_weight_elem *vl)
10406{
10407 memcpy(vl, cache->table, VL_ARB_TABLE_SIZE * sizeof(*vl));
10408}
10409
10410static void vl_arb_set_cache(struct vl_arb_cache *cache,
10411 struct ib_vl_weight_elem *vl)
10412{
10413 memcpy(cache->table, vl, VL_ARB_TABLE_SIZE * sizeof(*vl));
10414}
10415
10416static int vl_arb_match_cache(struct vl_arb_cache *cache,
10417 struct ib_vl_weight_elem *vl)
10418{
10419 return !memcmp(cache->table, vl, VL_ARB_TABLE_SIZE * sizeof(*vl));
10420}
10421/* end functions related to vl arbitration table caching */
10422
10423static int set_vl_weights(struct hfi1_pportdata *ppd, u32 target,
10424 u32 size, struct ib_vl_weight_elem *vl)
10425{
10426 struct hfi1_devdata *dd = ppd->dd;
10427 u64 reg;
10428 unsigned int i, is_up = 0;
10429 int drain, ret = 0;
10430
10431 mutex_lock(&ppd->hls_lock);
10432
10433 if (ppd->host_link_state & HLS_UP)
10434 is_up = 1;
10435
10436 drain = !is_ax(dd) && is_up;
10437
10438 if (drain)
10439 /*
10440 * Before adjusting VL arbitration weights, empty per-VL
10441 * FIFOs, otherwise a packet whose VL weight is being
10442 * set to 0 could get stuck in a FIFO with no chance to
10443 * egress.
10444 */
10445 ret = stop_drain_data_vls(dd);
10446
10447 if (ret) {
10448 dd_dev_err(
10449 dd,
10450 "%s: cannot stop/drain VLs - refusing to change VL arbitration weights\n",
10451 __func__);
10452 goto err;
10453 }
10454
10455 for (i = 0; i < size; i++, vl++) {
10456 /*
10457 * NOTE: The low priority shift and mask are used here, but
10458 * they are the same for both the low and high registers.
10459 */
10460 reg = (((u64)vl->vl & SEND_LOW_PRIORITY_LIST_VL_MASK)
10461 << SEND_LOW_PRIORITY_LIST_VL_SHIFT)
10462 | (((u64)vl->weight
10463 & SEND_LOW_PRIORITY_LIST_WEIGHT_MASK)
10464 << SEND_LOW_PRIORITY_LIST_WEIGHT_SHIFT);
10465 write_csr(dd, target + (i * 8), reg);
10466 }
10467 pio_send_control(dd, PSC_GLOBAL_VLARB_ENABLE);
10468
10469 if (drain)
10470 open_fill_data_vls(dd); /* reopen all VLs */
10471
10472err:
10473 mutex_unlock(&ppd->hls_lock);
10474
10475 return ret;
10476}
10477
10478/*
10479 * Read one credit merge VL register.
10480 */
10481static void read_one_cm_vl(struct hfi1_devdata *dd, u32 csr,
10482 struct vl_limit *vll)
10483{
10484 u64 reg = read_csr(dd, csr);
10485
10486 vll->dedicated = cpu_to_be16(
10487 (reg >> SEND_CM_CREDIT_VL_DEDICATED_LIMIT_VL_SHIFT)
10488 & SEND_CM_CREDIT_VL_DEDICATED_LIMIT_VL_MASK);
10489 vll->shared = cpu_to_be16(
10490 (reg >> SEND_CM_CREDIT_VL_SHARED_LIMIT_VL_SHIFT)
10491 & SEND_CM_CREDIT_VL_SHARED_LIMIT_VL_MASK);
10492}
10493
10494/*
10495 * Read the current credit merge limits.
10496 */
10497static int get_buffer_control(struct hfi1_devdata *dd,
10498 struct buffer_control *bc, u16 *overall_limit)
10499{
10500 u64 reg;
10501 int i;
10502
10503 /* not all entries are filled in */
10504 memset(bc, 0, sizeof(*bc));
10505
10506 /* OPA and HFI have a 1-1 mapping */
10507 for (i = 0; i < TXE_NUM_DATA_VL; i++)
8638b77f 10508 read_one_cm_vl(dd, SEND_CM_CREDIT_VL + (8 * i), &bc->vl[i]);
77241056
MM		 10509
10510 /* NOTE: assumes that VL* and VL15 CSRs are bit-wise identical */
10511 read_one_cm_vl(dd, SEND_CM_CREDIT_VL15, &bc->vl[15]);
10512
10513 reg = read_csr(dd, SEND_CM_GLOBAL_CREDIT);
10514 bc->overall_shared_limit = cpu_to_be16(
10515 (reg >> SEND_CM_GLOBAL_CREDIT_SHARED_LIMIT_SHIFT)
10516 & SEND_CM_GLOBAL_CREDIT_SHARED_LIMIT_MASK);
10517 if (overall_limit)
10518 *overall_limit = (reg
10519 >> SEND_CM_GLOBAL_CREDIT_TOTAL_CREDIT_LIMIT_SHIFT)
10520 & SEND_CM_GLOBAL_CREDIT_TOTAL_CREDIT_LIMIT_MASK;
10521 return sizeof(struct buffer_control);
10522}
10523
10524static int get_sc2vlnt(struct hfi1_devdata *dd, struct sc2vlnt *dp)
10525{
10526 u64 reg;
10527 int i;
10528
10529 /* each register contains 16 SC->VLnt mappings, 4 bits each */
10530 reg = read_csr(dd, DCC_CFG_SC_VL_TABLE_15_0);
10531 for (i = 0; i < sizeof(u64); i++) {
10532 u8 byte = *(((u8 *)&reg) + i);
10533
10534 dp->vlnt[2 * i] = byte & 0xf;
10535 dp->vlnt[(2 * i) + 1] = (byte & 0xf0) >> 4;
10536 }
10537
10538 reg = read_csr(dd, DCC_CFG_SC_VL_TABLE_31_16);
10539 for (i = 0; i < sizeof(u64); i++) {
10540 u8 byte = *(((u8 *)&reg) + i);
10541
10542 dp->vlnt[16 + (2 * i)] = byte & 0xf;
10543 dp->vlnt[16 + (2 * i) + 1] = (byte & 0xf0) >> 4;
10544 }
10545 return sizeof(struct sc2vlnt);
10546}
10547
10548static void get_vlarb_preempt(struct hfi1_devdata *dd, u32 nelems,
10549 struct ib_vl_weight_elem *vl)
10550{
10551 unsigned int i;
10552
10553 for (i = 0; i < nelems; i++, vl++) {
10554 vl->vl = 0xf;
10555 vl->weight = 0;
10556 }
10557}
10558
10559static void set_sc2vlnt(struct hfi1_devdata *dd, struct sc2vlnt *dp)
10560{
10561 write_csr(dd, DCC_CFG_SC_VL_TABLE_15_0,
10562 DC_SC_VL_VAL(15_0,
10563 0, dp->vlnt[0] & 0xf,
10564 1, dp->vlnt[1] & 0xf,
10565 2, dp->vlnt[2] & 0xf,
10566 3, dp->vlnt[3] & 0xf,
10567 4, dp->vlnt[4] & 0xf,
10568 5, dp->vlnt[5] & 0xf,
10569 6, dp->vlnt[6] & 0xf,
10570 7, dp->vlnt[7] & 0xf,
10571 8, dp->vlnt[8] & 0xf,
10572 9, dp->vlnt[9] & 0xf,
10573 10, dp->vlnt[10] & 0xf,
10574 11, dp->vlnt[11] & 0xf,
10575 12, dp->vlnt[12] & 0xf,
10576 13, dp->vlnt[13] & 0xf,
10577 14, dp->vlnt[14] & 0xf,
10578 15, dp->vlnt[15] & 0xf));
10579 write_csr(dd, DCC_CFG_SC_VL_TABLE_31_16,
10580 DC_SC_VL_VAL(31_16,
10581 16, dp->vlnt[16] & 0xf,
10582 17, dp->vlnt[17] & 0xf,
10583 18, dp->vlnt[18] & 0xf,
10584 19, dp->vlnt[19] & 0xf,
10585 20, dp->vlnt[20] & 0xf,
10586 21, dp->vlnt[21] & 0xf,
10587 22, dp->vlnt[22] & 0xf,
10588 23, dp->vlnt[23] & 0xf,
10589 24, dp->vlnt[24] & 0xf,
10590 25, dp->vlnt[25] & 0xf,
10591 26, dp->vlnt[26] & 0xf,
10592 27, dp->vlnt[27] & 0xf,
10593 28, dp->vlnt[28] & 0xf,
10594 29, dp->vlnt[29] & 0xf,
10595 30, dp->vlnt[30] & 0xf,
10596 31, dp->vlnt[31] & 0xf));
10597}
10598
10599static void nonzero_msg(struct hfi1_devdata *dd, int idx, const char *what,
10600 u16 limit)
10601{
10602 if (limit != 0)
10603 dd_dev_info(dd, "Invalid %s limit %d on VL %d, ignoring\n",
10604 what, (int)limit, idx);
10605}
10606
10607/* change only the shared limit portion of SendCmGLobalCredit */
10608static void set_global_shared(struct hfi1_devdata *dd, u16 limit)
10609{
10610 u64 reg;
10611
10612 reg = read_csr(dd, SEND_CM_GLOBAL_CREDIT);
10613 reg &= ~SEND_CM_GLOBAL_CREDIT_SHARED_LIMIT_SMASK;
10614 reg |= (u64)limit << SEND_CM_GLOBAL_CREDIT_SHARED_LIMIT_SHIFT;
10615 write_csr(dd, SEND_CM_GLOBAL_CREDIT, reg);
10616}
10617
10618/* change only the total credit limit portion of SendCmGLobalCredit */
10619static void set_global_limit(struct hfi1_devdata *dd, u16 limit)
10620{
10621 u64 reg;
10622
10623 reg = read_csr(dd, SEND_CM_GLOBAL_CREDIT);
10624 reg &= ~SEND_CM_GLOBAL_CREDIT_TOTAL_CREDIT_LIMIT_SMASK;
10625 reg |= (u64)limit << SEND_CM_GLOBAL_CREDIT_TOTAL_CREDIT_LIMIT_SHIFT;
10626 write_csr(dd, SEND_CM_GLOBAL_CREDIT, reg);
10627}
10628
10629/* set the given per-VL shared limit */
10630static void set_vl_shared(struct hfi1_devdata *dd, int vl, u16 limit)
10631{
10632 u64 reg;
10633 u32 addr;
10634
10635 if (vl < TXE_NUM_DATA_VL)
10636 addr = SEND_CM_CREDIT_VL + (8 * vl);
10637 else
10638 addr = SEND_CM_CREDIT_VL15;
10639
10640 reg = read_csr(dd, addr);
10641 reg &= ~SEND_CM_CREDIT_VL_SHARED_LIMIT_VL_SMASK;
10642 reg |= (u64)limit << SEND_CM_CREDIT_VL_SHARED_LIMIT_VL_SHIFT;
10643 write_csr(dd, addr, reg);
10644}
10645
10646/* set the given per-VL dedicated limit */
10647static void set_vl_dedicated(struct hfi1_devdata *dd, int vl, u16 limit)
10648{
10649 u64 reg;
10650 u32 addr;
10651
10652 if (vl < TXE_NUM_DATA_VL)
10653 addr = SEND_CM_CREDIT_VL + (8 * vl);
10654 else
10655 addr = SEND_CM_CREDIT_VL15;
10656
10657 reg = read_csr(dd, addr);
10658 reg &= ~SEND_CM_CREDIT_VL_DEDICATED_LIMIT_VL_SMASK;
10659 reg |= (u64)limit << SEND_CM_CREDIT_VL_DEDICATED_LIMIT_VL_SHIFT;
10660 write_csr(dd, addr, reg);
10661}
10662
10663/* spin until the given per-VL status mask bits clear */
10664static void wait_for_vl_status_clear(struct hfi1_devdata *dd, u64 mask,
10665 const char *which)
10666{
10667 unsigned long timeout;
10668 u64 reg;
10669
10670 timeout = jiffies + msecs_to_jiffies(VL_STATUS_CLEAR_TIMEOUT);
10671 while (1) {
10672 reg = read_csr(dd, SEND_CM_CREDIT_USED_STATUS) & mask;
10673
10674 if (reg == 0)
10675 return; /* success */
10676 if (time_after(jiffies, timeout))
10677 break; /* timed out */
10678 udelay(1);
10679 }
10680
10681 dd_dev_err(dd,
10682 "%s credit change status not clearing after %dms, mask 0x%llx, not clear 0x%llx\n",
10683 which, VL_STATUS_CLEAR_TIMEOUT, mask, reg);
10684 /*
10685 * If this occurs, it is likely there was a credit loss on the link.
10686 * The only recovery from that is a link bounce.
10687 */
10688 dd_dev_err(dd,
10689 "Continuing anyway. A credit loss may occur. Suggest a link bounce\n");
10690}
10691
10692/*
10693 * The number of credits on the VLs may be changed while everything
10694 * is "live", but the following algorithm must be followed due to
10695 * how the hardware is actually implemented. In particular,
10696 * Return_Credit_Status[] is the only correct status check.
10697 *
10698 * if (reducing Global_Shared_Credit_Limit or any shared limit changing)
10699 * set Global_Shared_Credit_Limit = 0
10700 * use_all_vl = 1
10701 * mask0 = all VLs that are changing either dedicated or shared limits
10702 * set Shared_Limit[mask0] = 0
10703 * spin until Return_Credit_Status[use_all_vl ? all VL : mask0] == 0
10704 * if (changing any dedicated limit)
10705 * mask1 = all VLs that are lowering dedicated limits
10706 * lower Dedicated_Limit[mask1]
10707 * spin until Return_Credit_Status[mask1] == 0
10708 * raise Dedicated_Limits
10709 * raise Shared_Limits
10710 * raise Global_Shared_Credit_Limit
10711 *
10712 * lower = if the new limit is lower, set the limit to the new value
10713 * raise = if the new limit is higher than the current value (may be changed
10714 * earlier in the algorithm), set the new limit to the new value
10715 */
8a4d3444
MM		 10716int set_buffer_control(struct hfi1_pportdata *ppd,
10717 struct buffer_control *new_bc)
77241056 10718{
8a4d3444 10719 struct hfi1_devdata *dd = ppd->dd;
77241056
MM		 10720 u64 changing_mask, ld_mask, stat_mask;
10721 int change_count;
10722 int i, use_all_mask;
10723 int this_shared_changing;
8a4d3444 10724 int vl_count = 0, ret;
77241056
MM		 10725 /*
10726 * A0: add the variable any_shared_limit_changing below and in the
10727 * algorithm above. If removing A0 support, it can be removed.
10728 */
10729 int any_shared_limit_changing;
10730 struct buffer_control cur_bc;
10731 u8 changing[OPA_MAX_VLS];
10732 u8 lowering_dedicated[OPA_MAX_VLS];
10733 u16 cur_total;
10734 u32 new_total = 0;
10735 const u64 all_mask =
10736 SEND_CM_CREDIT_USED_STATUS_VL0_RETURN_CREDIT_STATUS_SMASK
10737 | SEND_CM_CREDIT_USED_STATUS_VL1_RETURN_CREDIT_STATUS_SMASK
10738 | SEND_CM_CREDIT_USED_STATUS_VL2_RETURN_CREDIT_STATUS_SMASK
10739 | SEND_CM_CREDIT_USED_STATUS_VL3_RETURN_CREDIT_STATUS_SMASK
10740 | SEND_CM_CREDIT_USED_STATUS_VL4_RETURN_CREDIT_STATUS_SMASK
10741 | SEND_CM_CREDIT_USED_STATUS_VL5_RETURN_CREDIT_STATUS_SMASK
10742 | SEND_CM_CREDIT_USED_STATUS_VL6_RETURN_CREDIT_STATUS_SMASK
10743 | SEND_CM_CREDIT_USED_STATUS_VL7_RETURN_CREDIT_STATUS_SMASK
10744 | SEND_CM_CREDIT_USED_STATUS_VL15_RETURN_CREDIT_STATUS_SMASK;
10745
10746#define valid_vl(idx) ((idx) < TXE_NUM_DATA_VL || (idx) == 15)
10747#define NUM_USABLE_VLS 16 /* look at VL15 and less */
10748
77241056
MM		 10749 /* find the new total credits, do sanity check on unused VLs */
10750 for (i = 0; i < OPA_MAX_VLS; i++) {
10751 if (valid_vl(i)) {
10752 new_total += be16_to_cpu(new_bc->vl[i].dedicated);
10753 continue;
10754 }
10755 nonzero_msg(dd, i, "dedicated",
10756 be16_to_cpu(new_bc->vl[i].dedicated));
10757 nonzero_msg(dd, i, "shared",
10758 be16_to_cpu(new_bc->vl[i].shared));
10759 new_bc->vl[i].dedicated = 0;
10760 new_bc->vl[i].shared = 0;
10761 }
10762 new_total += be16_to_cpu(new_bc->overall_shared_limit);
bff14bb6 10763
77241056
MM		 10764 /* fetch the current values */
10765 get_buffer_control(dd, &cur_bc, &cur_total);
10766
10767 /*
10768 * Create the masks we will use.
10769 */
10770 memset(changing, 0, sizeof(changing));
10771 memset(lowering_dedicated, 0, sizeof(lowering_dedicated));
10772 /* NOTE: Assumes that the individual VL bits are adjacent and in
10773 increasing order */
10774 stat_mask =
10775 SEND_CM_CREDIT_USED_STATUS_VL0_RETURN_CREDIT_STATUS_SMASK;
10776 changing_mask = 0;
10777 ld_mask = 0;
10778 change_count = 0;
10779 any_shared_limit_changing = 0;
10780 for (i = 0; i < NUM_USABLE_VLS; i++, stat_mask <<= 1) {
10781 if (!valid_vl(i))
10782 continue;
10783 this_shared_changing = new_bc->vl[i].shared
10784 != cur_bc.vl[i].shared;
10785 if (this_shared_changing)
10786 any_shared_limit_changing = 1;
10787 if (new_bc->vl[i].dedicated != cur_bc.vl[i].dedicated
10788 || this_shared_changing) {
10789 changing[i] = 1;
10790 changing_mask |= stat_mask;
10791 change_count++;
10792 }
10793 if (be16_to_cpu(new_bc->vl[i].dedicated) <
10794 be16_to_cpu(cur_bc.vl[i].dedicated)) {
10795 lowering_dedicated[i] = 1;
10796 ld_mask |= stat_mask;
10797 }
10798 }
10799
10800 /* bracket the credit change with a total adjustment */
10801 if (new_total > cur_total)
10802 set_global_limit(dd, new_total);
10803
10804 /*
10805 * Start the credit change algorithm.
10806 */
10807 use_all_mask = 0;
10808 if ((be16_to_cpu(new_bc->overall_shared_limit) <
995deafa
MM		 10809 be16_to_cpu(cur_bc.overall_shared_limit)) ||
10810 (is_ax(dd) && any_shared_limit_changing)) {
77241056
MM		 10811 set_global_shared(dd, 0);
10812 cur_bc.overall_shared_limit = 0;
10813 use_all_mask = 1;
10814 }
10815
10816 for (i = 0; i < NUM_USABLE_VLS; i++) {
10817 if (!valid_vl(i))
10818 continue;
10819
10820 if (changing[i]) {
10821 set_vl_shared(dd, i, 0);
10822 cur_bc.vl[i].shared = 0;
10823 }
10824 }
10825
10826 wait_for_vl_status_clear(dd, use_all_mask ? all_mask : changing_mask,
10827 "shared");
10828
10829 if (change_count > 0) {
10830 for (i = 0; i < NUM_USABLE_VLS; i++) {
10831 if (!valid_vl(i))
10832 continue;
10833
10834 if (lowering_dedicated[i]) {
10835 set_vl_dedicated(dd, i,
10836 be16_to_cpu(new_bc->vl[i].dedicated));
10837 cur_bc.vl[i].dedicated =
10838 new_bc->vl[i].dedicated;
10839 }
10840 }
10841
10842 wait_for_vl_status_clear(dd, ld_mask, "dedicated");
10843
10844 /* now raise all dedicated that are going up */
10845 for (i = 0; i < NUM_USABLE_VLS; i++) {
10846 if (!valid_vl(i))
10847 continue;
10848
10849 if (be16_to_cpu(new_bc->vl[i].dedicated) >
10850 be16_to_cpu(cur_bc.vl[i].dedicated))
10851 set_vl_dedicated(dd, i,
10852 be16_to_cpu(new_bc->vl[i].dedicated));
10853 }
10854 }
10855
10856 /* next raise all shared that are going up */
10857 for (i = 0; i < NUM_USABLE_VLS; i++) {
10858 if (!valid_vl(i))
10859 continue;
10860
10861 if (be16_to_cpu(new_bc->vl[i].shared) >
10862 be16_to_cpu(cur_bc.vl[i].shared))
10863 set_vl_shared(dd, i, be16_to_cpu(new_bc->vl[i].shared));
10864 }
10865
10866 /* finally raise the global shared */
10867 if (be16_to_cpu(new_bc->overall_shared_limit) >
10868 be16_to_cpu(cur_bc.overall_shared_limit))
10869 set_global_shared(dd,
10870 be16_to_cpu(new_bc->overall_shared_limit));
10871
10872 /* bracket the credit change with a total adjustment */
10873 if (new_total < cur_total)
10874 set_global_limit(dd, new_total);
8a4d3444
MM		 10875
10876 /*
10877 * Determine the actual number of operational VLS using the number of
10878 * dedicated and shared credits for each VL.
10879 */
10880 if (change_count > 0) {
10881 for (i = 0; i < TXE_NUM_DATA_VL; i++)
10882 if (be16_to_cpu(new_bc->vl[i].dedicated) > 0 ||
10883 be16_to_cpu(new_bc->vl[i].shared) > 0)
10884 vl_count++;
10885 ppd->actual_vls_operational = vl_count;
10886 ret = sdma_map_init(dd, ppd->port - 1, vl_count ?
10887 ppd->actual_vls_operational :
10888 ppd->vls_operational,
10889 NULL);
10890 if (ret == 0)
10891 ret = pio_map_init(dd, ppd->port - 1, vl_count ?
10892 ppd->actual_vls_operational :
10893 ppd->vls_operational, NULL);
10894 if (ret)
10895 return ret;
10896 }
77241056
MM		 10897 return 0;
10898}
10899
10900/*
10901 * Read the given fabric manager table. Return the size of the
10902 * table (in bytes) on success, and a negative error code on
10903 * failure.
10904 */
10905int fm_get_table(struct hfi1_pportdata *ppd, int which, void *t)
10906
10907{
10908 int size;
10909 struct vl_arb_cache *vlc;
10910
10911 switch (which) {
10912 case FM_TBL_VL_HIGH_ARB:
10913 size = 256;
10914 /*
10915 * OPA specifies 128 elements (of 2 bytes each), though
10916 * HFI supports only 16 elements in h/w.
10917 */
10918 vlc = vl_arb_lock_cache(ppd, HI_PRIO_TABLE);
10919 vl_arb_get_cache(vlc, t);
10920 vl_arb_unlock_cache(ppd, HI_PRIO_TABLE);
10921 break;
10922 case FM_TBL_VL_LOW_ARB:
10923 size = 256;
10924 /*
10925 * OPA specifies 128 elements (of 2 bytes each), though
10926 * HFI supports only 16 elements in h/w.
10927 */
10928 vlc = vl_arb_lock_cache(ppd, LO_PRIO_TABLE);
10929 vl_arb_get_cache(vlc, t);
10930 vl_arb_unlock_cache(ppd, LO_PRIO_TABLE);
10931 break;
10932 case FM_TBL_BUFFER_CONTROL:
10933 size = get_buffer_control(ppd->dd, t, NULL);
10934 break;
10935 case FM_TBL_SC2VLNT:
10936 size = get_sc2vlnt(ppd->dd, t);
10937 break;
10938 case FM_TBL_VL_PREEMPT_ELEMS:
10939 size = 256;
10940 /* OPA specifies 128 elements, of 2 bytes each */
10941 get_vlarb_preempt(ppd->dd, OPA_MAX_VLS, t);
10942 break;
10943 case FM_TBL_VL_PREEMPT_MATRIX:
10944 size = 256;
10945 /*
10946 * OPA specifies that this is the same size as the VL
10947 * arbitration tables (i.e., 256 bytes).
10948 */
10949 break;
10950 default:
10951 return -EINVAL;
10952 }
10953 return size;
10954}
10955
10956/*
10957 * Write the given fabric manager table.
10958 */
10959int fm_set_table(struct hfi1_pportdata *ppd, int which, void *t)
10960{
10961 int ret = 0;
10962 struct vl_arb_cache *vlc;
10963
10964 switch (which) {
10965 case FM_TBL_VL_HIGH_ARB:
10966 vlc = vl_arb_lock_cache(ppd, HI_PRIO_TABLE);
10967 if (vl_arb_match_cache(vlc, t)) {
10968 vl_arb_unlock_cache(ppd, HI_PRIO_TABLE);
10969 break;
10970 }
10971 vl_arb_set_cache(vlc, t);
10972 vl_arb_unlock_cache(ppd, HI_PRIO_TABLE);
10973 ret = set_vl_weights(ppd, SEND_HIGH_PRIORITY_LIST,
10974 VL_ARB_HIGH_PRIO_TABLE_SIZE, t);
10975 break;
10976 case FM_TBL_VL_LOW_ARB:
10977 vlc = vl_arb_lock_cache(ppd, LO_PRIO_TABLE);
10978 if (vl_arb_match_cache(vlc, t)) {
10979 vl_arb_unlock_cache(ppd, LO_PRIO_TABLE);
10980 break;
10981 }
10982 vl_arb_set_cache(vlc, t);
10983 vl_arb_unlock_cache(ppd, LO_PRIO_TABLE);
10984 ret = set_vl_weights(ppd, SEND_LOW_PRIORITY_LIST,
10985 VL_ARB_LOW_PRIO_TABLE_SIZE, t);
10986 break;
10987 case FM_TBL_BUFFER_CONTROL:
8a4d3444 10988 ret = set_buffer_control(ppd, t);
77241056
MM		 10989 break;
10990 case FM_TBL_SC2VLNT:
10991 set_sc2vlnt(ppd->dd, t);
10992 break;
10993 default:
10994 ret = -EINVAL;
10995 }
10996 return ret;
10997}
10998
10999/*
11000 * Disable all data VLs.
11001 *
11002 * Return 0 if disabled, non-zero if the VLs cannot be disabled.
11003 */
11004static int disable_data_vls(struct hfi1_devdata *dd)
11005{
995deafa 11006 if (is_ax(dd))
77241056
MM		 11007 return 1;
11008
11009 pio_send_control(dd, PSC_DATA_VL_DISABLE);
11010
11011 return 0;
11012}
11013
11014/*
11015 * open_fill_data_vls() - the counterpart to stop_drain_data_vls().
11016 * Just re-enables all data VLs (the "fill" part happens
11017 * automatically - the name was chosen for symmetry with
11018 * stop_drain_data_vls()).
11019 *
11020 * Return 0 if successful, non-zero if the VLs cannot be enabled.
11021 */
11022int open_fill_data_vls(struct hfi1_devdata *dd)
11023{
995deafa 11024 if (is_ax(dd))
77241056
MM		 11025 return 1;
11026
11027 pio_send_control(dd, PSC_DATA_VL_ENABLE);
11028
11029 return 0;
11030}
11031
11032/*
11033 * drain_data_vls() - assumes that disable_data_vls() has been called,
11034 * wait for occupancy (of per-VL FIFOs) for all contexts, and SDMA
11035 * engines to drop to 0.
11036 */
11037static void drain_data_vls(struct hfi1_devdata *dd)
11038{
11039 sc_wait(dd);
11040 sdma_wait(dd);
11041 pause_for_credit_return(dd);
11042}
11043
11044/*
11045 * stop_drain_data_vls() - disable, then drain all per-VL fifos.
11046 *
11047 * Use open_fill_data_vls() to resume using data VLs. This pair is
11048 * meant to be used like this:
11049 *
11050 * stop_drain_data_vls(dd);
11051 * // do things with per-VL resources
11052 * open_fill_data_vls(dd);
11053 */
11054int stop_drain_data_vls(struct hfi1_devdata *dd)
11055{
11056 int ret;
11057
11058 ret = disable_data_vls(dd);
11059 if (ret == 0)
11060 drain_data_vls(dd);
11061
11062 return ret;
11063}
11064
11065/*
11066 * Convert a nanosecond time to a cclock count. No matter how slow
11067 * the cclock, a non-zero ns will always have a non-zero result.
11068 */
11069u32 ns_to_cclock(struct hfi1_devdata *dd, u32 ns)
11070{
11071 u32 cclocks;
11072
11073 if (dd->icode == ICODE_FPGA_EMULATION)
11074 cclocks = (ns * 1000) / FPGA_CCLOCK_PS;
11075 else /* simulation pretends to be ASIC */
11076 cclocks = (ns * 1000) / ASIC_CCLOCK_PS;
11077 if (ns && !cclocks) /* if ns nonzero, must be at least 1 */
11078 cclocks = 1;
11079 return cclocks;
11080}
11081
11082/*
11083 * Convert a cclock count to nanoseconds. Not matter how slow
11084 * the cclock, a non-zero cclocks will always have a non-zero result.
11085 */
11086u32 cclock_to_ns(struct hfi1_devdata *dd, u32 cclocks)
11087{
11088 u32 ns;
11089
11090 if (dd->icode == ICODE_FPGA_EMULATION)
11091 ns = (cclocks * FPGA_CCLOCK_PS) / 1000;
11092 else /* simulation pretends to be ASIC */
11093 ns = (cclocks * ASIC_CCLOCK_PS) / 1000;
11094 if (cclocks && !ns)
11095 ns = 1;
11096 return ns;
11097}
11098
11099/*
11100 * Dynamically adjust the receive interrupt timeout for a context based on
11101 * incoming packet rate.
11102 *
11103 * NOTE: Dynamic adjustment does not allow rcv_intr_count to be zero.
11104 */
11105static void adjust_rcv_timeout(struct hfi1_ctxtdata *rcd, u32 npkts)
11106{
11107 struct hfi1_devdata *dd = rcd->dd;
11108 u32 timeout = rcd->rcvavail_timeout;
11109
11110 /*
11111 * This algorithm doubles or halves the timeout depending on whether
11112 * the number of packets received in this interrupt were less than or
11113 * greater equal the interrupt count.
11114 *
11115 * The calculations below do not allow a steady state to be achieved.
11116 * Only at the endpoints it is possible to have an unchanging
11117 * timeout.
11118 */
11119 if (npkts < rcv_intr_count) {
11120 /*
11121 * Not enough packets arrived before the timeout, adjust
11122 * timeout downward.
11123 */
11124 if (timeout < 2) /* already at minimum? */
11125 return;
11126 timeout >>= 1;
11127 } else {
11128 /*
11129 * More than enough packets arrived before the timeout, adjust
11130 * timeout upward.
11131 */
11132 if (timeout >= dd->rcv_intr_timeout_csr) /* already at max? */
11133 return;
11134 timeout = min(timeout << 1, dd->rcv_intr_timeout_csr);
11135 }
11136
11137 rcd->rcvavail_timeout = timeout;
11138 /* timeout cannot be larger than rcv_intr_timeout_csr which has already
11139 been verified to be in range */
11140 write_kctxt_csr(dd, rcd->ctxt, RCV_AVAIL_TIME_OUT,
11141 (u64)timeout << RCV_AVAIL_TIME_OUT_TIME_OUT_RELOAD_SHIFT);
11142}
11143
11144void update_usrhead(struct hfi1_ctxtdata *rcd, u32 hd, u32 updegr, u32 egrhd,
11145 u32 intr_adjust, u32 npkts)
11146{
11147 struct hfi1_devdata *dd = rcd->dd;
11148 u64 reg;
11149 u32 ctxt = rcd->ctxt;
11150
11151 /*
11152 * Need to write timeout register before updating RcvHdrHead to ensure
11153 * that a new value is used when the HW decides to restart counting.
11154 */
11155 if (intr_adjust)
11156 adjust_rcv_timeout(rcd, npkts);
11157 if (updegr) {
11158 reg = (egrhd & RCV_EGR_INDEX_HEAD_HEAD_MASK)
11159 << RCV_EGR_INDEX_HEAD_HEAD_SHIFT;
11160 write_uctxt_csr(dd, ctxt, RCV_EGR_INDEX_HEAD, reg);
11161 }
11162 mmiowb();
11163 reg = ((u64)rcv_intr_count << RCV_HDR_HEAD_COUNTER_SHIFT) |
11164 (((u64)hd & RCV_HDR_HEAD_HEAD_MASK)
11165 << RCV_HDR_HEAD_HEAD_SHIFT);
11166 write_uctxt_csr(dd, ctxt, RCV_HDR_HEAD, reg);
11167 mmiowb();
11168}
11169
11170u32 hdrqempty(struct hfi1_ctxtdata *rcd)
11171{
11172 u32 head, tail;
11173
11174 head = (read_uctxt_csr(rcd->dd, rcd->ctxt, RCV_HDR_HEAD)
11175 & RCV_HDR_HEAD_HEAD_SMASK) >> RCV_HDR_HEAD_HEAD_SHIFT;
11176
11177 if (rcd->rcvhdrtail_kvaddr)
11178 tail = get_rcvhdrtail(rcd);
11179 else
11180 tail = read_uctxt_csr(rcd->dd, rcd->ctxt, RCV_HDR_TAIL);
11181
11182 return head == tail;
11183}
11184
11185/*
11186 * Context Control and Receive Array encoding for buffer size:
11187 * 0x0 invalid
11188 * 0x1 4 KB
11189 * 0x2 8 KB
11190 * 0x3 16 KB
11191 * 0x4 32 KB
11192 * 0x5 64 KB
11193 * 0x6 128 KB
11194 * 0x7 256 KB
11195 * 0x8 512 KB (Receive Array only)
11196 * 0x9 1 MB (Receive Array only)
11197 * 0xa 2 MB (Receive Array only)
11198 *
11199 * 0xB-0xF - reserved (Receive Array only)
11200 *
11201 *
11202 * This routine assumes that the value has already been sanity checked.
11203 */
11204static u32 encoded_size(u32 size)
11205{
11206 switch (size) {
8638b77f
JJ		 11207 case 4 * 1024: return 0x1;
11208 case 8 * 1024: return 0x2;
11209 case 16 * 1024: return 0x3;
11210 case 32 * 1024: return 0x4;
11211 case 64 * 1024: return 0x5;
11212 case 128 * 1024: return 0x6;
11213 case 256 * 1024: return 0x7;
11214 case 512 * 1024: return 0x8;
11215 case 1 * 1024 * 1024: return 0x9;
11216 case 2 * 1024 * 1024: return 0xa;
77241056
MM		 11217 }
11218 return 0x1; /* if invalid, go with the minimum size */
11219}
11220
11221void hfi1_rcvctrl(struct hfi1_devdata *dd, unsigned int op, int ctxt)
11222{
11223 struct hfi1_ctxtdata *rcd;
11224 u64 rcvctrl, reg;
11225 int did_enable = 0;
11226
11227 rcd = dd->rcd[ctxt];
11228 if (!rcd)
11229 return;
11230
11231 hfi1_cdbg(RCVCTRL, "ctxt %d op 0x%x", ctxt, op);
11232
11233 rcvctrl = read_kctxt_csr(dd, ctxt, RCV_CTXT_CTRL);
11234 /* if the context already enabled, don't do the extra steps */
11235 if ((op & HFI1_RCVCTRL_CTXT_ENB)
11236 && !(rcvctrl & RCV_CTXT_CTRL_ENABLE_SMASK)) {
11237 /* reset the tail and hdr addresses, and sequence count */
11238 write_kctxt_csr(dd, ctxt, RCV_HDR_ADDR,
11239 rcd->rcvhdrq_phys);
11240 if (HFI1_CAP_KGET_MASK(rcd->flags, DMA_RTAIL))
11241 write_kctxt_csr(dd, ctxt, RCV_HDR_TAIL_ADDR,
11242 rcd->rcvhdrqtailaddr_phys);
11243 rcd->seq_cnt = 1;
11244
11245 /* reset the cached receive header queue head value */
11246 rcd->head = 0;
11247
11248 /*
11249 * Zero the receive header queue so we don't get false
11250 * positives when checking the sequence number. The
11251 * sequence numbers could land exactly on the same spot.
11252 * E.g. a rcd restart before the receive header wrapped.
11253 */
11254 memset(rcd->rcvhdrq, 0, rcd->rcvhdrq_size);
11255
11256 /* starting timeout */
11257 rcd->rcvavail_timeout = dd->rcv_intr_timeout_csr;
11258
11259 /* enable the context */
11260 rcvctrl |= RCV_CTXT_CTRL_ENABLE_SMASK;
11261
11262 /* clean the egr buffer size first */
11263 rcvctrl &= ~RCV_CTXT_CTRL_EGR_BUF_SIZE_SMASK;
11264 rcvctrl |= ((u64)encoded_size(rcd->egrbufs.rcvtid_size)
11265 & RCV_CTXT_CTRL_EGR_BUF_SIZE_MASK)
11266 << RCV_CTXT_CTRL_EGR_BUF_SIZE_SHIFT;
11267
11268 /* zero RcvHdrHead - set RcvHdrHead.Counter after enable */
11269 write_uctxt_csr(dd, ctxt, RCV_HDR_HEAD, 0);
11270 did_enable = 1;
11271
11272 /* zero RcvEgrIndexHead */
11273 write_uctxt_csr(dd, ctxt, RCV_EGR_INDEX_HEAD, 0);
11274
11275 /* set eager count and base index */
11276 reg = (((u64)(rcd->egrbufs.alloced >> RCV_SHIFT)
11277 & RCV_EGR_CTRL_EGR_CNT_MASK)
11278 << RCV_EGR_CTRL_EGR_CNT_SHIFT) |
11279 (((rcd->eager_base >> RCV_SHIFT)
11280 & RCV_EGR_CTRL_EGR_BASE_INDEX_MASK)
11281 << RCV_EGR_CTRL_EGR_BASE_INDEX_SHIFT);
11282 write_kctxt_csr(dd, ctxt, RCV_EGR_CTRL, reg);
11283
11284 /*
11285 * Set TID (expected) count and base index.
11286 * rcd->expected_count is set to individual RcvArray entries,
11287 * not pairs, and the CSR takes a pair-count in groups of
11288 * four, so divide by 8.
11289 */
11290 reg = (((rcd->expected_count >> RCV_SHIFT)
11291 & RCV_TID_CTRL_TID_PAIR_CNT_MASK)
11292 << RCV_TID_CTRL_TID_PAIR_CNT_SHIFT) |
11293 (((rcd->expected_base >> RCV_SHIFT)
11294 & RCV_TID_CTRL_TID_BASE_INDEX_MASK)
11295 << RCV_TID_CTRL_TID_BASE_INDEX_SHIFT);
11296 write_kctxt_csr(dd, ctxt, RCV_TID_CTRL, reg);
82c2611d
NV		 11297 if (ctxt == HFI1_CTRL_CTXT)
11298 write_csr(dd, RCV_VL15, HFI1_CTRL_CTXT);
77241056
MM		 11299 }
11300 if (op & HFI1_RCVCTRL_CTXT_DIS) {
11301 write_csr(dd, RCV_VL15, 0);
46b010d3
MB		 11302 /*
11303 * When receive context is being disabled turn on tail
11304 * update with a dummy tail address and then disable
11305 * receive context.
11306 */
11307 if (dd->rcvhdrtail_dummy_physaddr) {
11308 write_kctxt_csr(dd, ctxt, RCV_HDR_TAIL_ADDR,
11309 dd->rcvhdrtail_dummy_physaddr);
566c157c 11310 /* Enabling RcvCtxtCtrl.TailUpd is intentional. */
46b010d3
MB		 11311 rcvctrl |= RCV_CTXT_CTRL_TAIL_UPD_SMASK;
11312 }
11313
77241056
MM		 11314 rcvctrl &= ~RCV_CTXT_CTRL_ENABLE_SMASK;
11315 }
11316 if (op & HFI1_RCVCTRL_INTRAVAIL_ENB)
11317 rcvctrl |= RCV_CTXT_CTRL_INTR_AVAIL_SMASK;
11318 if (op & HFI1_RCVCTRL_INTRAVAIL_DIS)
11319 rcvctrl &= ~RCV_CTXT_CTRL_INTR_AVAIL_SMASK;
11320 if (op & HFI1_RCVCTRL_TAILUPD_ENB && rcd->rcvhdrqtailaddr_phys)
11321 rcvctrl |= RCV_CTXT_CTRL_TAIL_UPD_SMASK;
566c157c
MH		 11322 if (op & HFI1_RCVCTRL_TAILUPD_DIS) {
11323 /* See comment on RcvCtxtCtrl.TailUpd above */
11324 if (!(op & HFI1_RCVCTRL_CTXT_DIS))
11325 rcvctrl &= ~RCV_CTXT_CTRL_TAIL_UPD_SMASK;
11326 }
77241056
MM		 11327 if (op & HFI1_RCVCTRL_TIDFLOW_ENB)
11328 rcvctrl |= RCV_CTXT_CTRL_TID_FLOW_ENABLE_SMASK;
11329 if (op & HFI1_RCVCTRL_TIDFLOW_DIS)
11330 rcvctrl &= ~RCV_CTXT_CTRL_TID_FLOW_ENABLE_SMASK;
11331 if (op & HFI1_RCVCTRL_ONE_PKT_EGR_ENB) {
11332 /* In one-packet-per-eager mode, the size comes from
11333 the RcvArray entry. */
11334 rcvctrl &= ~RCV_CTXT_CTRL_EGR_BUF_SIZE_SMASK;
11335 rcvctrl |= RCV_CTXT_CTRL_ONE_PACKET_PER_EGR_BUFFER_SMASK;
11336 }
11337 if (op & HFI1_RCVCTRL_ONE_PKT_EGR_DIS)
11338 rcvctrl &= ~RCV_CTXT_CTRL_ONE_PACKET_PER_EGR_BUFFER_SMASK;
11339 if (op & HFI1_RCVCTRL_NO_RHQ_DROP_ENB)
11340 rcvctrl |= RCV_CTXT_CTRL_DONT_DROP_RHQ_FULL_SMASK;
11341 if (op & HFI1_RCVCTRL_NO_RHQ_DROP_DIS)
11342 rcvctrl &= ~RCV_CTXT_CTRL_DONT_DROP_RHQ_FULL_SMASK;
11343 if (op & HFI1_RCVCTRL_NO_EGR_DROP_ENB)
11344 rcvctrl |= RCV_CTXT_CTRL_DONT_DROP_EGR_FULL_SMASK;
11345 if (op & HFI1_RCVCTRL_NO_EGR_DROP_DIS)
11346 rcvctrl &= ~RCV_CTXT_CTRL_DONT_DROP_EGR_FULL_SMASK;
11347 rcd->rcvctrl = rcvctrl;
11348 hfi1_cdbg(RCVCTRL, "ctxt %d rcvctrl 0x%llx\n", ctxt, rcvctrl);
11349 write_kctxt_csr(dd, ctxt, RCV_CTXT_CTRL, rcd->rcvctrl);
11350
11351 /* work around sticky RcvCtxtStatus.BlockedRHQFull */
11352 if (did_enable
11353 && (rcvctrl & RCV_CTXT_CTRL_DONT_DROP_RHQ_FULL_SMASK)) {
11354 reg = read_kctxt_csr(dd, ctxt, RCV_CTXT_STATUS);
11355 if (reg != 0) {
11356 dd_dev_info(dd, "ctxt %d status %lld (blocked)\n",
11357 ctxt, reg);
11358 read_uctxt_csr(dd, ctxt, RCV_HDR_HEAD);
11359 write_uctxt_csr(dd, ctxt, RCV_HDR_HEAD, 0x10);
11360 write_uctxt_csr(dd, ctxt, RCV_HDR_HEAD, 0x00);
11361 read_uctxt_csr(dd, ctxt, RCV_HDR_HEAD);
11362 reg = read_kctxt_csr(dd, ctxt, RCV_CTXT_STATUS);
11363 dd_dev_info(dd, "ctxt %d status %lld (%s blocked)\n",
11364 ctxt, reg, reg == 0 ? "not" : "still");
11365 }
11366 }
11367
11368 if (did_enable) {
11369 /*
11370 * The interrupt timeout and count must be set after
11371 * the context is enabled to take effect.
11372 */
11373 /* set interrupt timeout */
11374 write_kctxt_csr(dd, ctxt, RCV_AVAIL_TIME_OUT,
11375 (u64)rcd->rcvavail_timeout <<
11376 RCV_AVAIL_TIME_OUT_TIME_OUT_RELOAD_SHIFT);
11377
11378 /* set RcvHdrHead.Counter, zero RcvHdrHead.Head (again) */
11379 reg = (u64)rcv_intr_count << RCV_HDR_HEAD_COUNTER_SHIFT;
11380 write_uctxt_csr(dd, ctxt, RCV_HDR_HEAD, reg);
11381 }
11382
11383 if (op & (HFI1_RCVCTRL_TAILUPD_DIS | HFI1_RCVCTRL_CTXT_DIS))
11384 /*
11385 * If the context has been disabled and the Tail Update has
46b010d3
MB		 11386 * been cleared, set the RCV_HDR_TAIL_ADDR CSR to dummy address
11387 * so it doesn't contain an address that is invalid.
77241056 11388 */
46b010d3
MB		 11389 write_kctxt_csr(dd, ctxt, RCV_HDR_TAIL_ADDR,
11390 dd->rcvhdrtail_dummy_physaddr);
77241056
MM		 11391}
11392
11393u32 hfi1_read_cntrs(struct hfi1_devdata *dd, loff_t pos, char **namep,
11394 u64 **cntrp)
11395{
11396 int ret;
11397 u64 val = 0;
11398
11399 if (namep) {
11400 ret = dd->cntrnameslen;
11401 if (pos != 0) {
11402 dd_dev_err(dd, "read_cntrs does not support indexing");
11403 return 0;
11404 }
11405 *namep = dd->cntrnames;
11406 } else {
11407 const struct cntr_entry *entry;
11408 int i, j;
11409
11410 ret = (dd->ndevcntrs) * sizeof(u64);
11411 if (pos != 0) {
11412 dd_dev_err(dd, "read_cntrs does not support indexing");
11413 return 0;
11414 }
11415
11416 /* Get the start of the block of counters */
11417 *cntrp = dd->cntrs;
11418
11419 /*
11420 * Now go and fill in each counter in the block.
11421 */
11422 for (i = 0; i < DEV_CNTR_LAST; i++) {
11423 entry = &dev_cntrs[i];
11424 hfi1_cdbg(CNTR, "reading %s", entry->name);
11425 if (entry->flags & CNTR_DISABLED) {
11426 /* Nothing */
11427 hfi1_cdbg(CNTR, "\tDisabled\n");
11428 } else {
11429 if (entry->flags & CNTR_VL) {
11430 hfi1_cdbg(CNTR, "\tPer VL\n");
11431 for (j = 0; j < C_VL_COUNT; j++) {
11432 val = entry->rw_cntr(entry,
11433 dd, j,
11434 CNTR_MODE_R,
11435 0);
11436 hfi1_cdbg(
11437 CNTR,
11438 "\t\tRead 0x%llx for %d\n",
11439 val, j);
11440 dd->cntrs[entry->offset + j] =
11441 val;
11442 }
a699c6c2
VM		 11443 } else if (entry->flags & CNTR_SDMA) {
11444 hfi1_cdbg(CNTR,
11445 "\t Per SDMA Engine\n");
11446 for (j = 0; j < dd->chip_sdma_engines;
11447 j++) {
11448 val =
11449 entry->rw_cntr(entry, dd, j,
11450 CNTR_MODE_R, 0);
11451 hfi1_cdbg(CNTR,
11452 "\t\tRead 0x%llx for %d\n",
11453 val, j);
11454 dd->cntrs[entry->offset + j] =
11455 val;
11456 }
77241056
MM		 11457 } else {
11458 val = entry->rw_cntr(entry, dd,
11459 CNTR_INVALID_VL,
11460 CNTR_MODE_R, 0);
11461 dd->cntrs[entry->offset] = val;
11462 hfi1_cdbg(CNTR, "\tRead 0x%llx", val);
11463 }
11464 }
11465 }
11466 }
11467 return ret;
11468}
11469
11470/*
11471 * Used by sysfs to create files for hfi stats to read
11472 */
11473u32 hfi1_read_portcntrs(struct hfi1_devdata *dd, loff_t pos, u32 port,
11474 char **namep, u64 **cntrp)
11475{
11476 int ret;
11477 u64 val = 0;
11478
11479 if (namep) {
11480 ret = dd->portcntrnameslen;
11481 if (pos != 0) {
11482 dd_dev_err(dd, "index not supported");
11483 return 0;
11484 }
11485 *namep = dd->portcntrnames;
11486 } else {
11487 const struct cntr_entry *entry;
11488 struct hfi1_pportdata *ppd;
11489 int i, j;
11490
11491 ret = (dd->nportcntrs) * sizeof(u64);
11492 if (pos != 0) {
11493 dd_dev_err(dd, "indexing not supported");
11494 return 0;
11495 }
11496 ppd = (struct hfi1_pportdata *)(dd + 1 + port);
11497 *cntrp = ppd->cntrs;
11498
11499 for (i = 0; i < PORT_CNTR_LAST; i++) {
11500 entry = &port_cntrs[i];
11501 hfi1_cdbg(CNTR, "reading %s", entry->name);
11502 if (entry->flags & CNTR_DISABLED) {
11503 /* Nothing */
11504 hfi1_cdbg(CNTR, "\tDisabled\n");
11505 continue;
11506 }
11507
11508 if (entry->flags & CNTR_VL) {
11509 hfi1_cdbg(CNTR, "\tPer VL");
11510 for (j = 0; j < C_VL_COUNT; j++) {
11511 val = entry->rw_cntr(entry, ppd, j,
11512 CNTR_MODE_R,
11513 0);
11514 hfi1_cdbg(
11515 CNTR,
11516 "\t\tRead 0x%llx for %d",
11517 val, j);
11518 ppd->cntrs[entry->offset + j] = val;
11519 }
11520 } else {
11521 val = entry->rw_cntr(entry, ppd,
11522 CNTR_INVALID_VL,
11523 CNTR_MODE_R,
11524 0);
11525 ppd->cntrs[entry->offset] = val;
11526 hfi1_cdbg(CNTR, "\tRead 0x%llx", val);
11527 }
11528 }
11529 }
11530 return ret;
11531}
11532
11533static void free_cntrs(struct hfi1_devdata *dd)
11534{
11535 struct hfi1_pportdata *ppd;
11536 int i;
11537
11538 if (dd->synth_stats_timer.data)
11539 del_timer_sync(&dd->synth_stats_timer);
11540 dd->synth_stats_timer.data = 0;
11541 ppd = (struct hfi1_pportdata *)(dd + 1);
11542 for (i = 0; i < dd->num_pports; i++, ppd++) {
11543 kfree(ppd->cntrs);
11544 kfree(ppd->scntrs);
4eb06882
DD		 11545 free_percpu(ppd->ibport_data.rvp.rc_acks);
11546 free_percpu(ppd->ibport_data.rvp.rc_qacks);
11547 free_percpu(ppd->ibport_data.rvp.rc_delayed_comp);
77241056
MM		 11548 ppd->cntrs = NULL;
11549 ppd->scntrs = NULL;
4eb06882
DD		 11550 ppd->ibport_data.rvp.rc_acks = NULL;
11551 ppd->ibport_data.rvp.rc_qacks = NULL;
11552 ppd->ibport_data.rvp.rc_delayed_comp = NULL;
77241056
MM		 11553 }
11554 kfree(dd->portcntrnames);
11555 dd->portcntrnames = NULL;
11556 kfree(dd->cntrs);
11557 dd->cntrs = NULL;
11558 kfree(dd->scntrs);
11559 dd->scntrs = NULL;
11560 kfree(dd->cntrnames);
11561 dd->cntrnames = NULL;
11562}
11563
11564#define CNTR_MAX 0xFFFFFFFFFFFFFFFFULL
11565#define CNTR_32BIT_MAX 0x00000000FFFFFFFF
11566
11567static u64 read_dev_port_cntr(struct hfi1_devdata *dd, struct cntr_entry *entry,
11568 u64 *psval, void *context, int vl)
11569{
11570 u64 val;
11571 u64 sval = *psval;
11572
11573 if (entry->flags & CNTR_DISABLED) {
11574 dd_dev_err(dd, "Counter %s not enabled", entry->name);
11575 return 0;
11576 }
11577
11578 hfi1_cdbg(CNTR, "cntr: %s vl %d psval 0x%llx", entry->name, vl, *psval);
11579
11580 val = entry->rw_cntr(entry, context, vl, CNTR_MODE_R, 0);
11581
11582 /* If its a synthetic counter there is more work we need to do */
11583 if (entry->flags & CNTR_SYNTH) {
11584 if (sval == CNTR_MAX) {
11585 /* No need to read already saturated */
11586 return CNTR_MAX;
11587 }
11588
11589 if (entry->flags & CNTR_32BIT) {
11590 /* 32bit counters can wrap multiple times */
11591 u64 upper = sval >> 32;
11592 u64 lower = (sval << 32) >> 32;
11593
11594 if (lower > val) { /* hw wrapped */
11595 if (upper == CNTR_32BIT_MAX)
11596 val = CNTR_MAX;
11597 else
11598 upper++;
11599 }
11600
11601 if (val != CNTR_MAX)
11602 val = (upper << 32) | val;
11603
11604 } else {
11605 /* If we rolled we are saturated */
11606 if ((val < sval) || (val > CNTR_MAX))
11607 val = CNTR_MAX;
11608 }
11609 }
11610
11611 *psval = val;
11612
11613 hfi1_cdbg(CNTR, "\tNew val=0x%llx", val);
11614
11615 return val;
11616}
11617
11618static u64 write_dev_port_cntr(struct hfi1_devdata *dd,
11619 struct cntr_entry *entry,
11620 u64 *psval, void *context, int vl, u64 data)
11621{
11622 u64 val;
11623
11624 if (entry->flags & CNTR_DISABLED) {
11625 dd_dev_err(dd, "Counter %s not enabled", entry->name);
11626 return 0;
11627 }
11628
11629 hfi1_cdbg(CNTR, "cntr: %s vl %d psval 0x%llx", entry->name, vl, *psval);
11630
11631 if (entry->flags & CNTR_SYNTH) {
11632 *psval = data;
11633 if (entry->flags & CNTR_32BIT) {
11634 val = entry->rw_cntr(entry, context, vl, CNTR_MODE_W,
11635 (data << 32) >> 32);
11636 val = data; /* return the full 64bit value */
11637 } else {
11638 val = entry->rw_cntr(entry, context, vl, CNTR_MODE_W,
11639 data);
11640 }
11641 } else {
11642 val = entry->rw_cntr(entry, context, vl, CNTR_MODE_W, data);
11643 }
11644
11645 *psval = val;
11646
11647 hfi1_cdbg(CNTR, "\tNew val=0x%llx", val);
11648
11649 return val;
11650}
11651
11652u64 read_dev_cntr(struct hfi1_devdata *dd, int index, int vl)
11653{
11654 struct cntr_entry *entry;
11655 u64 *sval;
11656
11657 entry = &dev_cntrs[index];
11658 sval = dd->scntrs + entry->offset;
11659
11660 if (vl != CNTR_INVALID_VL)
11661 sval += vl;
11662
11663 return read_dev_port_cntr(dd, entry, sval, dd, vl);
11664}
11665
11666u64 write_dev_cntr(struct hfi1_devdata *dd, int index, int vl, u64 data)
11667{
11668 struct cntr_entry *entry;
11669 u64 *sval;
11670
11671 entry = &dev_cntrs[index];
11672 sval = dd->scntrs + entry->offset;
11673
11674 if (vl != CNTR_INVALID_VL)
11675 sval += vl;
11676
11677 return write_dev_port_cntr(dd, entry, sval, dd, vl, data);
11678}
11679
11680u64 read_port_cntr(struct hfi1_pportdata *ppd, int index, int vl)
11681{
11682 struct cntr_entry *entry;
11683 u64 *sval;
11684
11685 entry = &port_cntrs[index];
11686 sval = ppd->scntrs + entry->offset;
11687
11688 if (vl != CNTR_INVALID_VL)
11689 sval += vl;
11690
11691 if ((index >= C_RCV_HDR_OVF_FIRST + ppd->dd->num_rcv_contexts) &&
11692 (index <= C_RCV_HDR_OVF_LAST)) {
11693 /* We do not want to bother for disabled contexts */
11694 return 0;
11695 }
11696
11697 return read_dev_port_cntr(ppd->dd, entry, sval, ppd, vl);
11698}
11699
11700u64 write_port_cntr(struct hfi1_pportdata *ppd, int index, int vl, u64 data)
11701{
11702 struct cntr_entry *entry;
11703 u64 *sval;
11704
11705 entry = &port_cntrs[index];
11706 sval = ppd->scntrs + entry->offset;
11707
11708 if (vl != CNTR_INVALID_VL)
11709 sval += vl;
11710
11711 if ((index >= C_RCV_HDR_OVF_FIRST + ppd->dd->num_rcv_contexts) &&
11712 (index <= C_RCV_HDR_OVF_LAST)) {
11713 /* We do not want to bother for disabled contexts */
11714 return 0;
11715 }
11716
11717 return write_dev_port_cntr(ppd->dd, entry, sval, ppd, vl, data);
11718}
11719
11720static void update_synth_timer(unsigned long opaque)
11721{
11722 u64 cur_tx;
11723 u64 cur_rx;
11724 u64 total_flits;
11725 u8 update = 0;
11726 int i, j, vl;
11727 struct hfi1_pportdata *ppd;
11728 struct cntr_entry *entry;
11729
11730 struct hfi1_devdata *dd = (struct hfi1_devdata *)opaque;
11731
11732 /*
11733 * Rather than keep beating on the CSRs pick a minimal set that we can
11734 * check to watch for potential roll over. We can do this by looking at
11735 * the number of flits sent/recv. If the total flits exceeds 32bits then
11736 * we have to iterate all the counters and update.
11737 */
11738 entry = &dev_cntrs[C_DC_RCV_FLITS];
11739 cur_rx = entry->rw_cntr(entry, dd, CNTR_INVALID_VL, CNTR_MODE_R, 0);
11740
11741 entry = &dev_cntrs[C_DC_XMIT_FLITS];
11742 cur_tx = entry->rw_cntr(entry, dd, CNTR_INVALID_VL, CNTR_MODE_R, 0);
11743
11744 hfi1_cdbg(
11745 CNTR,
11746 "[%d] curr tx=0x%llx rx=0x%llx :: last tx=0x%llx rx=0x%llx\n",
11747 dd->unit, cur_tx, cur_rx, dd->last_tx, dd->last_rx);
11748
11749 if ((cur_tx < dd->last_tx) || (cur_rx < dd->last_rx)) {
11750 /*
11751 * May not be strictly necessary to update but it won't hurt and
11752 * simplifies the logic here.
11753 */
11754 update = 1;
11755 hfi1_cdbg(CNTR, "[%d] Tripwire counter rolled, updating",
11756 dd->unit);
11757 } else {
11758 total_flits = (cur_tx - dd->last_tx) + (cur_rx - dd->last_rx);
11759 hfi1_cdbg(CNTR,
11760 "[%d] total flits 0x%llx limit 0x%llx\n", dd->unit,
11761 total_flits, (u64)CNTR_32BIT_MAX);
11762 if (total_flits >= CNTR_32BIT_MAX) {
11763 hfi1_cdbg(CNTR, "[%d] 32bit limit hit, updating",
11764 dd->unit);
11765 update = 1;
11766 }
11767 }
11768
11769 if (update) {
11770 hfi1_cdbg(CNTR, "[%d] Updating dd and ppd counters", dd->unit);
11771 for (i = 0; i < DEV_CNTR_LAST; i++) {
11772 entry = &dev_cntrs[i];
11773 if (entry->flags & CNTR_VL) {
11774 for (vl = 0; vl < C_VL_COUNT; vl++)
11775 read_dev_cntr(dd, i, vl);
11776 } else {
11777 read_dev_cntr(dd, i, CNTR_INVALID_VL);
11778 }
11779 }
11780 ppd = (struct hfi1_pportdata *)(dd + 1);
11781 for (i = 0; i < dd->num_pports; i++, ppd++) {
11782 for (j = 0; j < PORT_CNTR_LAST; j++) {
11783 entry = &port_cntrs[j];
11784 if (entry->flags & CNTR_VL) {
11785 for (vl = 0; vl < C_VL_COUNT; vl++)
11786 read_port_cntr(ppd, j, vl);
11787 } else {
11788 read_port_cntr(ppd, j, CNTR_INVALID_VL);
11789 }
11790 }
11791 }
11792
11793 /*
11794 * We want the value in the register. The goal is to keep track
11795 * of the number of "ticks" not the counter value. In other
11796 * words if the register rolls we want to notice it and go ahead
11797 * and force an update.
11798 */
11799 entry = &dev_cntrs[C_DC_XMIT_FLITS];
11800 dd->last_tx = entry->rw_cntr(entry, dd, CNTR_INVALID_VL,
11801 CNTR_MODE_R, 0);
11802
11803 entry = &dev_cntrs[C_DC_RCV_FLITS];
11804 dd->last_rx = entry->rw_cntr(entry, dd, CNTR_INVALID_VL,
11805 CNTR_MODE_R, 0);
11806
11807 hfi1_cdbg(CNTR, "[%d] setting last tx/rx to 0x%llx 0x%llx",
11808 dd->unit, dd->last_tx, dd->last_rx);
11809
11810 } else {
11811 hfi1_cdbg(CNTR, "[%d] No update necessary", dd->unit);
11812 }
11813
11814mod_timer(&dd->synth_stats_timer, jiffies + HZ * SYNTH_CNT_TIME);
11815}
11816
11817#define C_MAX_NAME 13 /* 12 chars + one for /0 */
11818static int init_cntrs(struct hfi1_devdata *dd)
11819{
c024c554 11820 int i, rcv_ctxts, j;
77241056
MM		 11821 size_t sz;
11822 char *p;
11823 char name[C_MAX_NAME];
11824 struct hfi1_pportdata *ppd;
11d2b114
SS		 11825 const char *bit_type_32 = ",32";
11826 const int bit_type_32_sz = strlen(bit_type_32);
77241056
MM		 11827
11828 /* set up the stats timer; the add_timer is done at the end */
24523a94
MFW		 11829 setup_timer(&dd->synth_stats_timer, update_synth_timer,
11830 (unsigned long)dd);
77241056
MM		 11831
11832 /***********************/
11833 /* per device counters */
11834 /***********************/
11835
11836 /* size names and determine how many we have*/
11837 dd->ndevcntrs = 0;
11838 sz = 0;
77241056
MM		 11839
11840 for (i = 0; i < DEV_CNTR_LAST; i++) {
77241056
MM		 11841 if (dev_cntrs[i].flags & CNTR_DISABLED) {
11842 hfi1_dbg_early("\tSkipping %s\n", dev_cntrs[i].name);
11843 continue;
11844 }
11845
11846 if (dev_cntrs[i].flags & CNTR_VL) {
c024c554 11847 dev_cntrs[i].offset = dd->ndevcntrs;
77241056 11848 for (j = 0; j < C_VL_COUNT; j++) {
77241056
MM		 11849 snprintf(name, C_MAX_NAME, "%s%d",
11850 dev_cntrs[i].name,
11851 vl_from_idx(j));
11852 sz += strlen(name);
11d2b114
SS		 11853 /* Add ",32" for 32-bit counters */
11854 if (dev_cntrs[i].flags & CNTR_32BIT)
11855 sz += bit_type_32_sz;
77241056 11856 sz++;
77241056 11857 dd->ndevcntrs++;
77241056 11858 }
a699c6c2 11859 } else if (dev_cntrs[i].flags & CNTR_SDMA) {
c024c554 11860 dev_cntrs[i].offset = dd->ndevcntrs;
a699c6c2 11861 for (j = 0; j < dd->chip_sdma_engines; j++) {
a699c6c2
VM		 11862 snprintf(name, C_MAX_NAME, "%s%d",
11863 dev_cntrs[i].name, j);
11864 sz += strlen(name);
11d2b114
SS		 11865 /* Add ",32" for 32-bit counters */
11866 if (dev_cntrs[i].flags & CNTR_32BIT)
11867 sz += bit_type_32_sz;
a699c6c2 11868 sz++;
a699c6c2 11869 dd->ndevcntrs++;
a699c6c2 11870 }
77241056 11871 } else {
11d2b114 11872 /* +1 for newline. */
77241056 11873 sz += strlen(dev_cntrs[i].name) + 1;
11d2b114
SS		 11874 /* Add ",32" for 32-bit counters */
11875 if (dev_cntrs[i].flags & CNTR_32BIT)
11876 sz += bit_type_32_sz;
c024c554 11877 dev_cntrs[i].offset = dd->ndevcntrs;
77241056 11878 dd->ndevcntrs++;
77241056
MM		 11879 }
11880 }
11881
11882 /* allocate space for the counter values */
c024c554 11883 dd->cntrs = kcalloc(dd->ndevcntrs, sizeof(u64), GFP_KERNEL);
77241056
MM		 11884 if (!dd->cntrs)
11885 goto bail;
11886
c024c554 11887 dd->scntrs = kcalloc(dd->ndevcntrs, sizeof(u64), GFP_KERNEL);
77241056
MM		 11888 if (!dd->scntrs)
11889 goto bail;
11890
77241056
MM		 11891 /* allocate space for the counter names */
11892 dd->cntrnameslen = sz;
11893 dd->cntrnames = kmalloc(sz, GFP_KERNEL);
11894 if (!dd->cntrnames)
11895 goto bail;
11896
11897 /* fill in the names */
c024c554 11898 for (p = dd->cntrnames, i = 0; i < DEV_CNTR_LAST; i++) {
77241056
MM		 11899 if (dev_cntrs[i].flags & CNTR_DISABLED) {
11900 /* Nothing */
11d2b114
SS		 11901 } else if (dev_cntrs[i].flags & CNTR_VL) {
11902 for (j = 0; j < C_VL_COUNT; j++) {
11d2b114
SS		 11903 snprintf(name, C_MAX_NAME, "%s%d",
11904 dev_cntrs[i].name,
11905 vl_from_idx(j));
11906 memcpy(p, name, strlen(name));
11907 p += strlen(name);
11908
11909 /* Counter is 32 bits */
11910 if (dev_cntrs[i].flags & CNTR_32BIT) {
11911 memcpy(p, bit_type_32, bit_type_32_sz);
11912 p += bit_type_32_sz;
77241056 11913 }
11d2b114
SS		 11914
11915 *p++ = '\n';
11916 }
11917 } else if (dev_cntrs[i].flags & CNTR_SDMA) {
11918 for (j = 0; j < dd->chip_sdma_engines; j++) {
11d2b114
SS		 11919 snprintf(name, C_MAX_NAME, "%s%d",
11920 dev_cntrs[i].name, j);
11921 memcpy(p, name, strlen(name));
11922 p += strlen(name);
11923
11924 /* Counter is 32 bits */
11925 if (dev_cntrs[i].flags & CNTR_32BIT) {
11926 memcpy(p, bit_type_32, bit_type_32_sz);
11927 p += bit_type_32_sz;
a699c6c2 11928 }
11d2b114 11929
77241056
MM		 11930 *p++ = '\n';
11931 }
11d2b114
SS		 11932 } else {
11933 memcpy(p, dev_cntrs[i].name, strlen(dev_cntrs[i].name));
11934 p += strlen(dev_cntrs[i].name);
11935
11936 /* Counter is 32 bits */
11937 if (dev_cntrs[i].flags & CNTR_32BIT) {
11938 memcpy(p, bit_type_32, bit_type_32_sz);
11939 p += bit_type_32_sz;
11940 }
11941
11942 *p++ = '\n';
77241056
MM		 11943 }
11944 }
11945
11946 /*********************/
11947 /* per port counters */
11948 /*********************/
11949
11950 /*
11951 * Go through the counters for the overflows and disable the ones we
11952 * don't need. This varies based on platform so we need to do it
11953 * dynamically here.
11954 */
11955 rcv_ctxts = dd->num_rcv_contexts;
11956 for (i = C_RCV_HDR_OVF_FIRST + rcv_ctxts;
11957 i <= C_RCV_HDR_OVF_LAST; i++) {
11958 port_cntrs[i].flags |= CNTR_DISABLED;
11959 }
11960
11961 /* size port counter names and determine how many we have*/
11962 sz = 0;
11963 dd->nportcntrs = 0;
11964 for (i = 0; i < PORT_CNTR_LAST; i++) {
77241056
MM		 11965 if (port_cntrs[i].flags & CNTR_DISABLED) {
11966 hfi1_dbg_early("\tSkipping %s\n", port_cntrs[i].name);
11967 continue;
11968 }
11969
11970 if (port_cntrs[i].flags & CNTR_VL) {
77241056
MM		 11971 port_cntrs[i].offset = dd->nportcntrs;
11972 for (j = 0; j < C_VL_COUNT; j++) {
77241056
MM		 11973 snprintf(name, C_MAX_NAME, "%s%d",
11974 port_cntrs[i].name,
11975 vl_from_idx(j));
11976 sz += strlen(name);
11d2b114
SS		 11977 /* Add ",32" for 32-bit counters */
11978 if (port_cntrs[i].flags & CNTR_32BIT)
11979 sz += bit_type_32_sz;
77241056 11980 sz++;
77241056
MM		 11981 dd->nportcntrs++;
11982 }
11983 } else {
11d2b114 11984 /* +1 for newline */
77241056 11985 sz += strlen(port_cntrs[i].name) + 1;
11d2b114
SS		 11986 /* Add ",32" for 32-bit counters */
11987 if (port_cntrs[i].flags & CNTR_32BIT)
11988 sz += bit_type_32_sz;
77241056
MM		 11989 port_cntrs[i].offset = dd->nportcntrs;
11990 dd->nportcntrs++;
77241056
MM		 11991 }
11992 }
11993
11994 /* allocate space for the counter names */
11995 dd->portcntrnameslen = sz;
11996 dd->portcntrnames = kmalloc(sz, GFP_KERNEL);
11997 if (!dd->portcntrnames)
11998 goto bail;
11999
12000 /* fill in port cntr names */
12001 for (p = dd->portcntrnames, i = 0; i < PORT_CNTR_LAST; i++) {
12002 if (port_cntrs[i].flags & CNTR_DISABLED)
12003 continue;
12004
12005 if (port_cntrs[i].flags & CNTR_VL) {
12006 for (j = 0; j < C_VL_COUNT; j++) {
77241056
MM		 12007 snprintf(name, C_MAX_NAME, "%s%d",
12008 port_cntrs[i].name,
12009 vl_from_idx(j));
12010 memcpy(p, name, strlen(name));
12011 p += strlen(name);
11d2b114
SS		 12012
12013 /* Counter is 32 bits */
12014 if (port_cntrs[i].flags & CNTR_32BIT) {
12015 memcpy(p, bit_type_32, bit_type_32_sz);
12016 p += bit_type_32_sz;
12017 }
12018
77241056
MM		 12019 *p++ = '\n';
12020 }
12021 } else {
12022 memcpy(p, port_cntrs[i].name,
12023 strlen(port_cntrs[i].name));
12024 p += strlen(port_cntrs[i].name);
11d2b114
SS		 12025
12026 /* Counter is 32 bits */
12027 if (port_cntrs[i].flags & CNTR_32BIT) {
12028 memcpy(p, bit_type_32, bit_type_32_sz);
12029 p += bit_type_32_sz;
12030 }
12031
77241056
MM		 12032 *p++ = '\n';
12033 }
12034 }
12035
12036 /* allocate per port storage for counter values */
12037 ppd = (struct hfi1_pportdata *)(dd + 1);
12038 for (i = 0; i < dd->num_pports; i++, ppd++) {
12039 ppd->cntrs = kcalloc(dd->nportcntrs, sizeof(u64), GFP_KERNEL);
12040 if (!ppd->cntrs)
12041 goto bail;
12042
12043 ppd->scntrs = kcalloc(dd->nportcntrs, sizeof(u64), GFP_KERNEL);
12044 if (!ppd->scntrs)
12045 goto bail;
12046 }
12047
12048 /* CPU counters need to be allocated and zeroed */
12049 if (init_cpu_counters(dd))
12050 goto bail;
12051
12052 mod_timer(&dd->synth_stats_timer, jiffies + HZ * SYNTH_CNT_TIME);
12053 return 0;
12054bail:
12055 free_cntrs(dd);
12056 return -ENOMEM;
12057}
12058
77241056
MM		 12059static u32 chip_to_opa_lstate(struct hfi1_devdata *dd, u32 chip_lstate)
12060{
12061 switch (chip_lstate) {
12062 default:
12063 dd_dev_err(dd,
12064 "Unknown logical state 0x%x, reporting IB_PORT_DOWN\n",
12065 chip_lstate);
12066 /* fall through */
12067 case LSTATE_DOWN:
12068 return IB_PORT_DOWN;
12069 case LSTATE_INIT:
12070 return IB_PORT_INIT;
12071 case LSTATE_ARMED:
12072 return IB_PORT_ARMED;
12073 case LSTATE_ACTIVE:
12074 return IB_PORT_ACTIVE;
12075 }
12076}
12077
12078u32 chip_to_opa_pstate(struct hfi1_devdata *dd, u32 chip_pstate)
12079{
12080 /* look at the HFI meta-states only */
12081 switch (chip_pstate & 0xf0) {
12082 default:
12083 dd_dev_err(dd, "Unexpected chip physical state of 0x%x\n",
12084 chip_pstate);
12085 /* fall through */
12086 case PLS_DISABLED:
12087 return IB_PORTPHYSSTATE_DISABLED;
12088 case PLS_OFFLINE:
12089 return OPA_PORTPHYSSTATE_OFFLINE;
12090 case PLS_POLLING:
12091 return IB_PORTPHYSSTATE_POLLING;
12092 case PLS_CONFIGPHY:
12093 return IB_PORTPHYSSTATE_TRAINING;
12094 case PLS_LINKUP:
12095 return IB_PORTPHYSSTATE_LINKUP;
12096 case PLS_PHYTEST:
12097 return IB_PORTPHYSSTATE_PHY_TEST;
12098 }
12099}
12100
12101/* return the OPA port logical state name */
12102const char *opa_lstate_name(u32 lstate)
12103{
12104 static const char * const port_logical_names[] = {
12105 "PORT_NOP",
12106 "PORT_DOWN",
12107 "PORT_INIT",
12108 "PORT_ARMED",
12109 "PORT_ACTIVE",
12110 "PORT_ACTIVE_DEFER",
12111 };
12112 if (lstate < ARRAY_SIZE(port_logical_names))
12113 return port_logical_names[lstate];
12114 return "unknown";
12115}
12116
12117/* return the OPA port physical state name */
12118const char *opa_pstate_name(u32 pstate)
12119{
12120 static const char * const port_physical_names[] = {
12121 "PHYS_NOP",
12122 "reserved1",
12123 "PHYS_POLL",
12124 "PHYS_DISABLED",
12125 "PHYS_TRAINING",
12126 "PHYS_LINKUP",
12127 "PHYS_LINK_ERR_RECOVER",
12128 "PHYS_PHY_TEST",
12129 "reserved8",
12130 "PHYS_OFFLINE",
12131 "PHYS_GANGED",
12132 "PHYS_TEST",
12133 };
12134 if (pstate < ARRAY_SIZE(port_physical_names))
12135 return port_physical_names[pstate];
12136 return "unknown";
12137}
12138
12139/*
12140 * Read the hardware link state and set the driver's cached value of it.
12141 * Return the (new) current value.
12142 */
12143u32 get_logical_state(struct hfi1_pportdata *ppd)
12144{
12145 u32 new_state;
12146
12147 new_state = chip_to_opa_lstate(ppd->dd, read_logical_state(ppd->dd));
12148 if (new_state != ppd->lstate) {
12149 dd_dev_info(ppd->dd, "logical state changed to %s (0x%x)\n",
12150 opa_lstate_name(new_state), new_state);
12151 ppd->lstate = new_state;
12152 }
12153 /*
12154 * Set port status flags in the page mapped into userspace
12155 * memory. Do it here to ensure a reliable state - this is
12156 * the only function called by all state handling code.
12157 * Always set the flags due to the fact that the cache value
12158 * might have been changed explicitly outside of this
12159 * function.
12160 */
12161 if (ppd->statusp) {
12162 switch (ppd->lstate) {
12163 case IB_PORT_DOWN:
12164 case IB_PORT_INIT:
12165 *ppd->statusp &= ~(HFI1_STATUS_IB_CONF |
12166 HFI1_STATUS_IB_READY);
12167 break;
12168 case IB_PORT_ARMED:
12169 *ppd->statusp |= HFI1_STATUS_IB_CONF;
12170 break;
12171 case IB_PORT_ACTIVE:
12172 *ppd->statusp |= HFI1_STATUS_IB_READY;
12173 break;
12174 }
12175 }
12176 return ppd->lstate;
12177}
12178
12179/**
12180 * wait_logical_linkstate - wait for an IB link state change to occur
12181 * @ppd: port device
12182 * @state: the state to wait for
12183 * @msecs: the number of milliseconds to wait
12184 *
12185 * Wait up to msecs milliseconds for IB link state change to occur.
12186 * For now, take the easy polling route.
12187 * Returns 0 if state reached, otherwise -ETIMEDOUT.
12188 */
12189static int wait_logical_linkstate(struct hfi1_pportdata *ppd, u32 state,
12190 int msecs)
12191{
12192 unsigned long timeout;
12193
12194 timeout = jiffies + msecs_to_jiffies(msecs);
12195 while (1) {
12196 if (get_logical_state(ppd) == state)
12197 return 0;
12198 if (time_after(jiffies, timeout))
12199 break;
12200 msleep(20);
12201 }
12202 dd_dev_err(ppd->dd, "timeout waiting for link state 0x%x\n", state);
12203
12204 return -ETIMEDOUT;
12205}
12206
12207u8 hfi1_ibphys_portstate(struct hfi1_pportdata *ppd)
12208{
77241056
MM		 12209 u32 pstate;
12210 u32 ib_pstate;
12211
12212 pstate = read_physical_state(ppd->dd);
12213 ib_pstate = chip_to_opa_pstate(ppd->dd, pstate);
f45c8dc8 12214 if (ppd->last_pstate != ib_pstate) {
77241056
MM		 12215 dd_dev_info(ppd->dd,
12216 "%s: physical state changed to %s (0x%x), phy 0x%x\n",
12217 __func__, opa_pstate_name(ib_pstate), ib_pstate,
12218 pstate);
f45c8dc8 12219 ppd->last_pstate = ib_pstate;
77241056
MM		 12220 }
12221 return ib_pstate;
12222}
12223
12224/*
12225 * Read/modify/write ASIC_QSFP register bits as selected by mask
12226 * data: 0 or 1 in the positions depending on what needs to be written
12227 * dir: 0 for read, 1 for write
12228 * mask: select by setting
12229 * I2CCLK (bit 0)
12230 * I2CDATA (bit 1)
12231 */
12232u64 hfi1_gpio_mod(struct hfi1_devdata *dd, u32 target, u32 data, u32 dir,
12233 u32 mask)
12234{
12235 u64 qsfp_oe, target_oe;
12236
12237 target_oe = target ? ASIC_QSFP2_OE : ASIC_QSFP1_OE;
12238 if (mask) {
12239 /* We are writing register bits, so lock access */
12240 dir &= mask;
12241 data &= mask;
12242
12243 qsfp_oe = read_csr(dd, target_oe);
12244 qsfp_oe = (qsfp_oe & ~(u64)mask) | (u64)dir;
12245 write_csr(dd, target_oe, qsfp_oe);
12246 }
12247 /* We are exclusively reading bits here, but it is unlikely
12248 * we'll get valid data when we set the direction of the pin
12249 * in the same call, so read should call this function again
12250 * to get valid data
12251 */
12252 return read_csr(dd, target ? ASIC_QSFP2_IN : ASIC_QSFP1_IN);
12253}
12254
12255#define CLEAR_STATIC_RATE_CONTROL_SMASK(r) \
12256(r &= ~SEND_CTXT_CHECK_ENABLE_DISALLOW_PBC_STATIC_RATE_CONTROL_SMASK)
12257
12258#define SET_STATIC_RATE_CONTROL_SMASK(r) \
12259(r |= SEND_CTXT_CHECK_ENABLE_DISALLOW_PBC_STATIC_RATE_CONTROL_SMASK)
12260
12261int hfi1_init_ctxt(struct send_context *sc)
12262{
12263 if (sc != NULL) {
12264 struct hfi1_devdata *dd = sc->dd;
12265 u64 reg;
12266 u8 set = (sc->type == SC_USER ?
12267 HFI1_CAP_IS_USET(STATIC_RATE_CTRL) :
12268 HFI1_CAP_IS_KSET(STATIC_RATE_CTRL));
12269 reg = read_kctxt_csr(dd, sc->hw_context,
12270 SEND_CTXT_CHECK_ENABLE);
12271 if (set)
12272 CLEAR_STATIC_RATE_CONTROL_SMASK(reg);
12273 else
12274 SET_STATIC_RATE_CONTROL_SMASK(reg);
12275 write_kctxt_csr(dd, sc->hw_context,
12276 SEND_CTXT_CHECK_ENABLE, reg);
12277 }
12278 return 0;
12279}
12280
12281int hfi1_tempsense_rd(struct hfi1_devdata *dd, struct hfi1_temp *temp)
12282{
12283 int ret = 0;
12284 u64 reg;
12285
12286 if (dd->icode != ICODE_RTL_SILICON) {
12287 if (HFI1_CAP_IS_KSET(PRINT_UNIMPL))
12288 dd_dev_info(dd, "%s: tempsense not supported by HW\n",
12289 __func__);
12290 return -EINVAL;
12291 }
12292 reg = read_csr(dd, ASIC_STS_THERM);
12293 temp->curr = ((reg >> ASIC_STS_THERM_CURR_TEMP_SHIFT) &
12294 ASIC_STS_THERM_CURR_TEMP_MASK);
12295 temp->lo_lim = ((reg >> ASIC_STS_THERM_LO_TEMP_SHIFT) &
12296 ASIC_STS_THERM_LO_TEMP_MASK);
12297 temp->hi_lim = ((reg >> ASIC_STS_THERM_HI_TEMP_SHIFT) &
12298 ASIC_STS_THERM_HI_TEMP_MASK);
12299 temp->crit_lim = ((reg >> ASIC_STS_THERM_CRIT_TEMP_SHIFT) &
12300 ASIC_STS_THERM_CRIT_TEMP_MASK);
12301 /* triggers is a 3-bit value - 1 bit per trigger. */
12302 temp->triggers = (u8)((reg >> ASIC_STS_THERM_LOW_SHIFT) & 0x7);
12303
12304 return ret;
12305}
12306
12307/* ========================================================================= */
12308
12309/*
12310 * Enable/disable chip from delivering interrupts.
12311 */
12312void set_intr_state(struct hfi1_devdata *dd, u32 enable)
12313{
12314 int i;
12315
12316 /*
12317 * In HFI, the mask needs to be 1 to allow interrupts.
12318 */
12319 if (enable) {
77241056
MM		 12320 /* enable all interrupts */
12321 for (i = 0; i < CCE_NUM_INT_CSRS; i++)
8638b77f 12322 write_csr(dd, CCE_INT_MASK + (8 * i), ~(u64)0);
77241056 12323
8ebd4cf1 12324 init_qsfp_int(dd);
77241056
MM		 12325 } else {
12326 for (i = 0; i < CCE_NUM_INT_CSRS; i++)
8638b77f 12327 write_csr(dd, CCE_INT_MASK + (8 * i), 0ull);
77241056
MM		 12328 }
12329}
12330
12331/*
12332 * Clear all interrupt sources on the chip.
12333 */
12334static void clear_all_interrupts(struct hfi1_devdata *dd)
12335{
12336 int i;
12337
12338 for (i = 0; i < CCE_NUM_INT_CSRS; i++)
8638b77f 12339 write_csr(dd, CCE_INT_CLEAR + (8 * i), ~(u64)0);
77241056
MM		 12340
12341 write_csr(dd, CCE_ERR_CLEAR, ~(u64)0);
12342 write_csr(dd, MISC_ERR_CLEAR, ~(u64)0);
12343 write_csr(dd, RCV_ERR_CLEAR, ~(u64)0);
12344 write_csr(dd, SEND_ERR_CLEAR, ~(u64)0);
12345 write_csr(dd, SEND_PIO_ERR_CLEAR, ~(u64)0);
12346 write_csr(dd, SEND_DMA_ERR_CLEAR, ~(u64)0);
12347 write_csr(dd, SEND_EGRESS_ERR_CLEAR, ~(u64)0);
12348 for (i = 0; i < dd->chip_send_contexts; i++)
12349 write_kctxt_csr(dd, i, SEND_CTXT_ERR_CLEAR, ~(u64)0);
12350 for (i = 0; i < dd->chip_sdma_engines; i++)
12351 write_kctxt_csr(dd, i, SEND_DMA_ENG_ERR_CLEAR, ~(u64)0);
12352
12353 write_csr(dd, DCC_ERR_FLG_CLR, ~(u64)0);
12354 write_csr(dd, DC_LCB_ERR_CLR, ~(u64)0);
12355 write_csr(dd, DC_DC8051_ERR_CLR, ~(u64)0);
12356}
12357
12358/* Move to pcie.c? */
12359static void disable_intx(struct pci_dev *pdev)
12360{
12361 pci_intx(pdev, 0);
12362}
12363
12364static void clean_up_interrupts(struct hfi1_devdata *dd)
12365{
12366 int i;
12367
12368 /* remove irqs - must happen before disabling/turning off */
12369 if (dd->num_msix_entries) {
12370 /* MSI-X */
12371 struct hfi1_msix_entry *me = dd->msix_entries;
12372
12373 for (i = 0; i < dd->num_msix_entries; i++, me++) {
12374 if (me->arg == NULL) /* => no irq, no affinity */
957558c9
MH		 12375 continue;
12376 hfi1_put_irq_affinity(dd, &dd->msix_entries[i]);
77241056
MM		 12377 free_irq(me->msix.vector, me->arg);
12378 }
12379 } else {
12380 /* INTx */
12381 if (dd->requested_intx_irq) {
12382 free_irq(dd->pcidev->irq, dd);
12383 dd->requested_intx_irq = 0;
12384 }
12385 }
12386
12387 /* turn off interrupts */
12388 if (dd->num_msix_entries) {
12389 /* MSI-X */
6e5b6131 12390 pci_disable_msix(dd->pcidev);
77241056
MM		 12391 } else {
12392 /* INTx */
12393 disable_intx(dd->pcidev);
12394 }
12395
12396 /* clean structures */
77241056
MM		 12397 kfree(dd->msix_entries);
12398 dd->msix_entries = NULL;
12399 dd->num_msix_entries = 0;
12400}
12401
12402/*
12403 * Remap the interrupt source from the general handler to the given MSI-X
12404 * interrupt.
12405 */
12406static void remap_intr(struct hfi1_devdata *dd, int isrc, int msix_intr)
12407{
12408 u64 reg;
12409 int m, n;
12410
12411 /* clear from the handled mask of the general interrupt */
12412 m = isrc / 64;
12413 n = isrc % 64;
12414 dd->gi_mask[m] &= ~((u64)1 << n);
12415
12416 /* direct the chip source to the given MSI-X interrupt */
12417 m = isrc / 8;
12418 n = isrc % 8;
8638b77f
JJ		 12419 reg = read_csr(dd, CCE_INT_MAP + (8 * m));
12420 reg &= ~((u64)0xff << (8 * n));
12421 reg |= ((u64)msix_intr & 0xff) << (8 * n);
12422 write_csr(dd, CCE_INT_MAP + (8 * m), reg);
77241056
MM		 12423}
12424
12425static void remap_sdma_interrupts(struct hfi1_devdata *dd,
12426 int engine, int msix_intr)
12427{
12428 /*
12429 * SDMA engine interrupt sources grouped by type, rather than
12430 * engine. Per-engine interrupts are as follows:
12431 * SDMA
12432 * SDMAProgress
12433 * SDMAIdle
12434 */
8638b77f 12435 remap_intr(dd, IS_SDMA_START + 0 * TXE_NUM_SDMA_ENGINES + engine,
77241056 12436 msix_intr);
8638b77f 12437 remap_intr(dd, IS_SDMA_START + 1 * TXE_NUM_SDMA_ENGINES + engine,
77241056 12438 msix_intr);
8638b77f 12439 remap_intr(dd, IS_SDMA_START + 2 * TXE_NUM_SDMA_ENGINES + engine,
77241056
MM		 12440 msix_intr);
12441}
12442
77241056
MM		 12443static int request_intx_irq(struct hfi1_devdata *dd)
12444{
12445 int ret;
12446
9805071e
JJ		 12447 snprintf(dd->intx_name, sizeof(dd->intx_name), DRIVER_NAME "_%d",
12448 dd->unit);
77241056
MM		 12449 ret = request_irq(dd->pcidev->irq, general_interrupt,
12450 IRQF_SHARED, dd->intx_name, dd);
12451 if (ret)
12452 dd_dev_err(dd, "unable to request INTx interrupt, err %d\n",
12453 ret);
12454 else
12455 dd->requested_intx_irq = 1;
12456 return ret;
12457}
12458
12459static int request_msix_irqs(struct hfi1_devdata *dd)
12460{
77241056
MM		 12461 int first_general, last_general;
12462 int first_sdma, last_sdma;
12463 int first_rx, last_rx;
957558c9 12464 int i, ret = 0;
77241056
MM		 12465
12466 /* calculate the ranges we are going to use */
12467 first_general = 0;
12468 first_sdma = last_general = first_general + 1;
12469 first_rx = last_sdma = first_sdma + dd->num_sdma;
12470 last_rx = first_rx + dd->n_krcv_queues;
12471
77241056
MM		 12472 /*
12473 * Sanity check - the code expects all SDMA chip source
12474 * interrupts to be in the same CSR, starting at bit 0. Verify
12475 * that this is true by checking the bit location of the start.
12476 */
12477 BUILD_BUG_ON(IS_SDMA_START % 64);
12478
12479 for (i = 0; i < dd->num_msix_entries; i++) {
12480 struct hfi1_msix_entry *me = &dd->msix_entries[i];
12481 const char *err_info;
12482 irq_handler_t handler;
f4f30031 12483 irq_handler_t thread = NULL;
77241056
MM		 12484 void *arg;
12485 int idx;
12486 struct hfi1_ctxtdata *rcd = NULL;
12487 struct sdma_engine *sde = NULL;
12488
12489 /* obtain the arguments to request_irq */
12490 if (first_general <= i && i < last_general) {
12491 idx = i - first_general;
12492 handler = general_interrupt;
12493 arg = dd;
12494 snprintf(me->name, sizeof(me->name),
9805071e 12495 DRIVER_NAME "_%d", dd->unit);
77241056 12496 err_info = "general";
957558c9 12497 me->type = IRQ_GENERAL;
77241056
MM		 12498 } else if (first_sdma <= i && i < last_sdma) {
12499 idx = i - first_sdma;
12500 sde = &dd->per_sdma[idx];
12501 handler = sdma_interrupt;
12502 arg = sde;
12503 snprintf(me->name, sizeof(me->name),
9805071e 12504 DRIVER_NAME "_%d sdma%d", dd->unit, idx);
77241056
MM		 12505 err_info = "sdma";
12506 remap_sdma_interrupts(dd, idx, i);
957558c9 12507 me->type = IRQ_SDMA;
77241056
MM		 12508 } else if (first_rx <= i && i < last_rx) {
12509 idx = i - first_rx;
12510 rcd = dd->rcd[idx];
12511 /* no interrupt if no rcd */
12512 if (!rcd)
12513 continue;
12514 /*
12515 * Set the interrupt register and mask for this
12516 * context's interrupt.
12517 */
8638b77f 12518 rcd->ireg = (IS_RCVAVAIL_START + idx) / 64;
77241056 12519 rcd->imask = ((u64)1) <<
8638b77f 12520 ((IS_RCVAVAIL_START + idx) % 64);
77241056 12521 handler = receive_context_interrupt;
f4f30031 12522 thread = receive_context_thread;
77241056
MM		 12523 arg = rcd;
12524 snprintf(me->name, sizeof(me->name),
9805071e 12525 DRIVER_NAME "_%d kctxt%d", dd->unit, idx);
77241056 12526 err_info = "receive context";
66c0933b 12527 remap_intr(dd, IS_RCVAVAIL_START + idx, i);
957558c9 12528 me->type = IRQ_RCVCTXT;
77241056
MM		 12529 } else {
12530 /* not in our expected range - complain, then
12531 ignore it */
12532 dd_dev_err(dd,
12533 "Unexpected extra MSI-X interrupt %d\n", i);
12534 continue;
12535 }
12536 /* no argument, no interrupt */
12537 if (arg == NULL)
12538 continue;
12539 /* make sure the name is terminated */
8638b77f 12540 me->name[sizeof(me->name) - 1] = 0;
77241056 12541
f4f30031
DL		 12542 ret = request_threaded_irq(me->msix.vector, handler, thread, 0,
12543 me->name, arg);
77241056
MM		 12544 if (ret) {
12545 dd_dev_err(dd,
12546 "unable to allocate %s interrupt, vector %d, index %d, err %d\n",
12547 err_info, me->msix.vector, idx, ret);
12548 return ret;
12549 }
12550 /*
12551 * assign arg after request_irq call, so it will be
12552 * cleaned up
12553 */
12554 me->arg = arg;
12555
957558c9
MH		 12556 ret = hfi1_get_irq_affinity(dd, me);
12557 if (ret)
12558 dd_dev_err(dd,
12559 "unable to pin IRQ %d\n", ret);
77241056
MM		 12560 }
12561
77241056 12562 return ret;
77241056
MM		 12563}
12564
12565/*
12566 * Set the general handler to accept all interrupts, remap all
12567 * chip interrupts back to MSI-X 0.
12568 */
12569static void reset_interrupts(struct hfi1_devdata *dd)
12570{
12571 int i;
12572
12573 /* all interrupts handled by the general handler */
12574 for (i = 0; i < CCE_NUM_INT_CSRS; i++)
12575 dd->gi_mask[i] = ~(u64)0;
12576
12577 /* all chip interrupts map to MSI-X 0 */
12578 for (i = 0; i < CCE_NUM_INT_MAP_CSRS; i++)
8638b77f 12579 write_csr(dd, CCE_INT_MAP + (8 * i), 0);
77241056
MM		 12580}
12581
12582static int set_up_interrupts(struct hfi1_devdata *dd)
12583{
12584 struct hfi1_msix_entry *entries;
12585 u32 total, request;
12586 int i, ret;
12587 int single_interrupt = 0; /* we expect to have all the interrupts */
12588
12589 /*
12590 * Interrupt count:
12591 * 1 general, "slow path" interrupt (includes the SDMA engines
12592 * slow source, SDMACleanupDone)
12593 * N interrupts - one per used SDMA engine
12594 * M interrupt - one per kernel receive context
12595 */
12596 total = 1 + dd->num_sdma + dd->n_krcv_queues;
12597
12598 entries = kcalloc(total, sizeof(*entries), GFP_KERNEL);
12599 if (!entries) {
77241056
MM		 12600 ret = -ENOMEM;
12601 goto fail;
12602 }
12603 /* 1-1 MSI-X entry assignment */
12604 for (i = 0; i < total; i++)
12605 entries[i].msix.entry = i;
12606
12607 /* ask for MSI-X interrupts */
12608 request = total;
12609 request_msix(dd, &request, entries);
12610
12611 if (request == 0) {
12612 /* using INTx */
12613 /* dd->num_msix_entries already zero */
12614 kfree(entries);
12615 single_interrupt = 1;
12616 dd_dev_err(dd, "MSI-X failed, using INTx interrupts\n");
12617 } else {
12618 /* using MSI-X */
12619 dd->num_msix_entries = request;
12620 dd->msix_entries = entries;
12621
12622 if (request != total) {
12623 /* using MSI-X, with reduced interrupts */
12624 dd_dev_err(
12625 dd,
12626 "cannot handle reduced interrupt case, want %u, got %u\n",
12627 total, request);
12628 ret = -EINVAL;
12629 goto fail;
12630 }
12631 dd_dev_info(dd, "%u MSI-X interrupts allocated\n", total);
12632 }
12633
12634 /* mask all interrupts */
12635 set_intr_state(dd, 0);
12636 /* clear all pending interrupts */
12637 clear_all_interrupts(dd);
12638
12639 /* reset general handler mask, chip MSI-X mappings */
12640 reset_interrupts(dd);
12641
12642 if (single_interrupt)
12643 ret = request_intx_irq(dd);
12644 else
12645 ret = request_msix_irqs(dd);
12646 if (ret)
12647 goto fail;
12648
12649 return 0;
12650
12651fail:
12652 clean_up_interrupts(dd);
12653 return ret;
12654}
12655
12656/*
12657 * Set up context values in dd. Sets:
12658 *
12659 * num_rcv_contexts - number of contexts being used
12660 * n_krcv_queues - number of kernel contexts
12661 * first_user_ctxt - first non-kernel context in array of contexts
12662 * freectxts - number of free user contexts
12663 * num_send_contexts - number of PIO send contexts being used
12664 */
12665static int set_up_context_variables(struct hfi1_devdata *dd)
12666{
12667 int num_kernel_contexts;
77241056
MM		 12668 int total_contexts;
12669 int ret;
12670 unsigned ngroups;
12671
12672 /*
12673 * Kernel contexts: (to be fixed later):
12674 * - min or 2 or 1 context/numa
82c2611d
NV		 12675 * - Context 0 - control context (VL15/multicast/error)
12676 * - Context 1 - default context
77241056
MM		 12677 */
12678 if (n_krcvqs)
82c2611d
NV		 12679 /*
12680 * Don't count context 0 in n_krcvqs since
12681 * is isn't used for normal verbs traffic.
12682 *
12683 * krcvqs will reflect number of kernel
12684 * receive contexts above 0.
12685 */
12686 num_kernel_contexts = n_krcvqs + MIN_KERNEL_KCTXTS - 1;
77241056 12687 else
0edf80ea 12688 num_kernel_contexts = num_online_nodes() + 1;
77241056
MM		 12689 num_kernel_contexts =
12690 max_t(int, MIN_KERNEL_KCTXTS, num_kernel_contexts);
12691 /*
12692 * Every kernel receive context needs an ACK send context.
12693 * one send context is allocated for each VL{0-7} and VL15
12694 */
12695 if (num_kernel_contexts > (dd->chip_send_contexts - num_vls - 1)) {
12696 dd_dev_err(dd,
12697 "Reducing # kernel rcv contexts to: %d, from %d\n",
12698 (int)(dd->chip_send_contexts - num_vls - 1),
12699 (int)num_kernel_contexts);
12700 num_kernel_contexts = dd->chip_send_contexts - num_vls - 1;
12701 }
12702 /*
12703 * User contexts: (to be fixed later)
2ce6bf22
SS		 12704 * - default to 1 user context per CPU if num_user_contexts is
12705 * negative
77241056 12706 */
2ce6bf22 12707 if (num_user_contexts < 0)
77241056
MM		 12708 num_user_contexts = num_online_cpus();
12709
12710 total_contexts = num_kernel_contexts + num_user_contexts;
12711
12712 /*
12713 * Adjust the counts given a global max.
12714 */
12715 if (total_contexts > dd->chip_rcv_contexts) {
12716 dd_dev_err(dd,
12717 "Reducing # user receive contexts to: %d, from %d\n",
12718 (int)(dd->chip_rcv_contexts - num_kernel_contexts),
12719 (int)num_user_contexts);
12720 num_user_contexts = dd->chip_rcv_contexts - num_kernel_contexts;
12721 /* recalculate */
12722 total_contexts = num_kernel_contexts + num_user_contexts;
12723 }
12724
12725 /* the first N are kernel contexts, the rest are user contexts */
12726 dd->num_rcv_contexts = total_contexts;
12727 dd->n_krcv_queues = num_kernel_contexts;
12728 dd->first_user_ctxt = num_kernel_contexts;
affa48de 12729 dd->num_user_contexts = num_user_contexts;
77241056
MM		 12730 dd->freectxts = num_user_contexts;
12731 dd_dev_info(dd,
12732 "rcv contexts: chip %d, used %d (kernel %d, user %d)\n",
12733 (int)dd->chip_rcv_contexts,
12734 (int)dd->num_rcv_contexts,
12735 (int)dd->n_krcv_queues,
12736 (int)dd->num_rcv_contexts - dd->n_krcv_queues);
12737
12738 /*
12739 * Receive array allocation:
12740 * All RcvArray entries are divided into groups of 8. This
12741 * is required by the hardware and will speed up writes to
12742 * consecutive entries by using write-combining of the entire
12743 * cacheline.
12744 *
12745 * The number of groups are evenly divided among all contexts.
12746 * any left over groups will be given to the first N user
12747 * contexts.
12748 */
12749 dd->rcv_entries.group_size = RCV_INCREMENT;
12750 ngroups = dd->chip_rcv_array_count / dd->rcv_entries.group_size;
12751 dd->rcv_entries.ngroups = ngroups / dd->num_rcv_contexts;
12752 dd->rcv_entries.nctxt_extra = ngroups -
12753 (dd->num_rcv_contexts * dd->rcv_entries.ngroups);
12754 dd_dev_info(dd, "RcvArray groups %u, ctxts extra %u\n",
12755 dd->rcv_entries.ngroups,
12756 dd->rcv_entries.nctxt_extra);
12757 if (dd->rcv_entries.ngroups * dd->rcv_entries.group_size >
12758 MAX_EAGER_ENTRIES * 2) {
12759 dd->rcv_entries.ngroups = (MAX_EAGER_ENTRIES * 2) /
12760 dd->rcv_entries.group_size;
12761 dd_dev_info(dd,
12762 "RcvArray group count too high, change to %u\n",
12763 dd->rcv_entries.ngroups);
12764 dd->rcv_entries.nctxt_extra = 0;
12765 }
12766 /*
12767 * PIO send contexts
12768 */
12769 ret = init_sc_pools_and_sizes(dd);
12770 if (ret >= 0) { /* success */
12771 dd->num_send_contexts = ret;
12772 dd_dev_info(
12773 dd,
12774 "send contexts: chip %d, used %d (kernel %d, ack %d, user %d)\n",
12775 dd->chip_send_contexts,
12776 dd->num_send_contexts,
12777 dd->sc_sizes[SC_KERNEL].count,
12778 dd->sc_sizes[SC_ACK].count,
12779 dd->sc_sizes[SC_USER].count);
12780 ret = 0; /* success */
12781 }
12782
12783 return ret;
12784}
12785
12786/*
12787 * Set the device/port partition key table. The MAD code
12788 * will ensure that, at least, the partial management
12789 * partition key is present in the table.
12790 */
12791static void set_partition_keys(struct hfi1_pportdata *ppd)
12792{
12793 struct hfi1_devdata *dd = ppd->dd;
12794 u64 reg = 0;
12795 int i;
12796
12797 dd_dev_info(dd, "Setting partition keys\n");
12798 for (i = 0; i < hfi1_get_npkeys(dd); i++) {
12799 reg |= (ppd->pkeys[i] &
12800 RCV_PARTITION_KEY_PARTITION_KEY_A_MASK) <<
12801 ((i % 4) *
12802 RCV_PARTITION_KEY_PARTITION_KEY_B_SHIFT);
12803 /* Each register holds 4 PKey values. */
12804 if ((i % 4) == 3) {
12805 write_csr(dd, RCV_PARTITION_KEY +
12806 ((i - 3) * 2), reg);
12807 reg = 0;
12808 }
12809 }
12810
12811 /* Always enable HW pkeys check when pkeys table is set */
12812 add_rcvctrl(dd, RCV_CTRL_RCV_PARTITION_KEY_ENABLE_SMASK);
12813}
12814
12815/*
12816 * These CSRs and memories are uninitialized on reset and must be
12817 * written before reading to set the ECC/parity bits.
12818 *
12819 * NOTE: All user context CSRs that are not mmaped write-only
12820 * (e.g. the TID flows) must be initialized even if the driver never
12821 * reads them.
12822 */
12823static void write_uninitialized_csrs_and_memories(struct hfi1_devdata *dd)
12824{
12825 int i, j;
12826
12827 /* CceIntMap */
12828 for (i = 0; i < CCE_NUM_INT_MAP_CSRS; i++)
8638b77f 12829 write_csr(dd, CCE_INT_MAP + (8 * i), 0);
77241056
MM		 12830
12831 /* SendCtxtCreditReturnAddr */
12832 for (i = 0; i < dd->chip_send_contexts; i++)
12833 write_kctxt_csr(dd, i, SEND_CTXT_CREDIT_RETURN_ADDR, 0);
12834
12835 /* PIO Send buffers */
12836 /* SDMA Send buffers */
12837 /* These are not normally read, and (presently) have no method
12838 to be read, so are not pre-initialized */
12839
12840 /* RcvHdrAddr */
12841 /* RcvHdrTailAddr */
12842 /* RcvTidFlowTable */
12843 for (i = 0; i < dd->chip_rcv_contexts; i++) {
12844 write_kctxt_csr(dd, i, RCV_HDR_ADDR, 0);
12845 write_kctxt_csr(dd, i, RCV_HDR_TAIL_ADDR, 0);
12846 for (j = 0; j < RXE_NUM_TID_FLOWS; j++)
8638b77f 12847 write_uctxt_csr(dd, i, RCV_TID_FLOW_TABLE + (8 * j), 0);
77241056
MM		 12848 }
12849
12850 /* RcvArray */
12851 for (i = 0; i < dd->chip_rcv_array_count; i++)
8638b77f 12852 write_csr(dd, RCV_ARRAY + (8 * i),
77241056
MM		 12853 RCV_ARRAY_RT_WRITE_ENABLE_SMASK);
12854
12855 /* RcvQPMapTable */
12856 for (i = 0; i < 32; i++)
12857 write_csr(dd, RCV_QP_MAP_TABLE + (8 * i), 0);
12858}
12859
12860/*
12861 * Use the ctrl_bits in CceCtrl to clear the status_bits in CceStatus.
12862 */
12863static void clear_cce_status(struct hfi1_devdata *dd, u64 status_bits,
12864 u64 ctrl_bits)
12865{
12866 unsigned long timeout;
12867 u64 reg;
12868
12869 /* is the condition present? */
12870 reg = read_csr(dd, CCE_STATUS);
12871 if ((reg & status_bits) == 0)
12872 return;
12873
12874 /* clear the condition */
12875 write_csr(dd, CCE_CTRL, ctrl_bits);
12876
12877 /* wait for the condition to clear */
12878 timeout = jiffies + msecs_to_jiffies(CCE_STATUS_TIMEOUT);
12879 while (1) {
12880 reg = read_csr(dd, CCE_STATUS);
12881 if ((reg & status_bits) == 0)
12882 return;
12883 if (time_after(jiffies, timeout)) {
12884 dd_dev_err(dd,
12885 "Timeout waiting for CceStatus to clear bits 0x%llx, remaining 0x%llx\n",
12886 status_bits, reg & status_bits);
12887 return;
12888 }
12889 udelay(1);
12890 }
12891}
12892
12893/* set CCE CSRs to chip reset defaults */
12894static void reset_cce_csrs(struct hfi1_devdata *dd)
12895{
12896 int i;
12897
12898 /* CCE_REVISION read-only */
12899 /* CCE_REVISION2 read-only */
12900 /* CCE_CTRL - bits clear automatically */
12901 /* CCE_STATUS read-only, use CceCtrl to clear */
12902 clear_cce_status(dd, ALL_FROZE, CCE_CTRL_SPC_UNFREEZE_SMASK);
12903 clear_cce_status(dd, ALL_TXE_PAUSE, CCE_CTRL_TXE_RESUME_SMASK);
12904 clear_cce_status(dd, ALL_RXE_PAUSE, CCE_CTRL_RXE_RESUME_SMASK);
12905 for (i = 0; i < CCE_NUM_SCRATCH; i++)
12906 write_csr(dd, CCE_SCRATCH + (8 * i), 0);
12907 /* CCE_ERR_STATUS read-only */
12908 write_csr(dd, CCE_ERR_MASK, 0);
12909 write_csr(dd, CCE_ERR_CLEAR, ~0ull);
12910 /* CCE_ERR_FORCE leave alone */
12911 for (i = 0; i < CCE_NUM_32_BIT_COUNTERS; i++)
12912 write_csr(dd, CCE_COUNTER_ARRAY32 + (8 * i), 0);
12913 write_csr(dd, CCE_DC_CTRL, CCE_DC_CTRL_RESETCSR);
12914 /* CCE_PCIE_CTRL leave alone */
12915 for (i = 0; i < CCE_NUM_MSIX_VECTORS; i++) {
12916 write_csr(dd, CCE_MSIX_TABLE_LOWER + (8 * i), 0);
12917 write_csr(dd, CCE_MSIX_TABLE_UPPER + (8 * i),
12918 CCE_MSIX_TABLE_UPPER_RESETCSR);
12919 }
12920 for (i = 0; i < CCE_NUM_MSIX_PBAS; i++) {
12921 /* CCE_MSIX_PBA read-only */
12922 write_csr(dd, CCE_MSIX_INT_GRANTED, ~0ull);
12923 write_csr(dd, CCE_MSIX_VEC_CLR_WITHOUT_INT, ~0ull);
12924 }
12925 for (i = 0; i < CCE_NUM_INT_MAP_CSRS; i++)
12926 write_csr(dd, CCE_INT_MAP, 0);
12927 for (i = 0; i < CCE_NUM_INT_CSRS; i++) {
12928 /* CCE_INT_STATUS read-only */
12929 write_csr(dd, CCE_INT_MASK + (8 * i), 0);
12930 write_csr(dd, CCE_INT_CLEAR + (8 * i), ~0ull);
12931 /* CCE_INT_FORCE leave alone */
12932 /* CCE_INT_BLOCKED read-only */
12933 }
12934 for (i = 0; i < CCE_NUM_32_BIT_INT_COUNTERS; i++)
12935 write_csr(dd, CCE_INT_COUNTER_ARRAY32 + (8 * i), 0);
12936}
12937
12938/* set ASIC CSRs to chip reset defaults */
12939static void reset_asic_csrs(struct hfi1_devdata *dd)
12940{
77241056
MM		 12941 int i;
12942
12943 /*
12944 * If the HFIs are shared between separate nodes or VMs,
12945 * then more will need to be done here. One idea is a module
12946 * parameter that returns early, letting the first power-on or
12947 * a known first load do the reset and blocking all others.
12948 */
12949
7c03ed85
EH		 12950 if (!(dd->flags & HFI1_DO_INIT_ASIC))
12951 return;
77241056
MM		 12952
12953 if (dd->icode != ICODE_FPGA_EMULATION) {
12954 /* emulation does not have an SBus - leave these alone */
12955 /*
12956 * All writes to ASIC_CFG_SBUS_REQUEST do something.
12957 * Notes:
12958 * o The reset is not zero if aimed at the core. See the
12959 * SBus documentation for details.
12960 * o If the SBus firmware has been updated (e.g. by the BIOS),
12961 * will the reset revert that?
12962 */
12963 /* ASIC_CFG_SBUS_REQUEST leave alone */
12964 write_csr(dd, ASIC_CFG_SBUS_EXECUTE, 0);
12965 }
12966 /* ASIC_SBUS_RESULT read-only */
12967 write_csr(dd, ASIC_STS_SBUS_COUNTERS, 0);
12968 for (i = 0; i < ASIC_NUM_SCRATCH; i++)
12969 write_csr(dd, ASIC_CFG_SCRATCH + (8 * i), 0);
12970 write_csr(dd, ASIC_CFG_MUTEX, 0); /* this will clear it */
7c03ed85
EH		 12971
12972 /* We might want to retain this state across FLR if we ever use it */
77241056 12973 write_csr(dd, ASIC_CFG_DRV_STR, 0);
7c03ed85 12974
4ef98989 12975 /* ASIC_CFG_THERM_POLL_EN leave alone */
77241056
MM		 12976 /* ASIC_STS_THERM read-only */
12977 /* ASIC_CFG_RESET leave alone */
12978
12979 write_csr(dd, ASIC_PCIE_SD_HOST_CMD, 0);
12980 /* ASIC_PCIE_SD_HOST_STATUS read-only */
12981 write_csr(dd, ASIC_PCIE_SD_INTRPT_DATA_CODE, 0);
12982 write_csr(dd, ASIC_PCIE_SD_INTRPT_ENABLE, 0);
12983 /* ASIC_PCIE_SD_INTRPT_PROGRESS read-only */
12984 write_csr(dd, ASIC_PCIE_SD_INTRPT_STATUS, ~0ull); /* clear */
12985 /* ASIC_HFI0_PCIE_SD_INTRPT_RSPD_DATA read-only */
12986 /* ASIC_HFI1_PCIE_SD_INTRPT_RSPD_DATA read-only */
12987 for (i = 0; i < 16; i++)
12988 write_csr(dd, ASIC_PCIE_SD_INTRPT_LIST + (8 * i), 0);
12989
12990 /* ASIC_GPIO_IN read-only */
12991 write_csr(dd, ASIC_GPIO_OE, 0);
12992 write_csr(dd, ASIC_GPIO_INVERT, 0);
12993 write_csr(dd, ASIC_GPIO_OUT, 0);
12994 write_csr(dd, ASIC_GPIO_MASK, 0);
12995 /* ASIC_GPIO_STATUS read-only */
12996 write_csr(dd, ASIC_GPIO_CLEAR, ~0ull);
12997 /* ASIC_GPIO_FORCE leave alone */
12998
12999 /* ASIC_QSFP1_IN read-only */
13000 write_csr(dd, ASIC_QSFP1_OE, 0);
13001 write_csr(dd, ASIC_QSFP1_INVERT, 0);
13002 write_csr(dd, ASIC_QSFP1_OUT, 0);
13003 write_csr(dd, ASIC_QSFP1_MASK, 0);
13004 /* ASIC_QSFP1_STATUS read-only */
13005 write_csr(dd, ASIC_QSFP1_CLEAR, ~0ull);
13006 /* ASIC_QSFP1_FORCE leave alone */
13007
13008 /* ASIC_QSFP2_IN read-only */
13009 write_csr(dd, ASIC_QSFP2_OE, 0);
13010 write_csr(dd, ASIC_QSFP2_INVERT, 0);
13011 write_csr(dd, ASIC_QSFP2_OUT, 0);
13012 write_csr(dd, ASIC_QSFP2_MASK, 0);
13013 /* ASIC_QSFP2_STATUS read-only */
13014 write_csr(dd, ASIC_QSFP2_CLEAR, ~0ull);
13015 /* ASIC_QSFP2_FORCE leave alone */
13016
13017 write_csr(dd, ASIC_EEP_CTL_STAT, ASIC_EEP_CTL_STAT_RESETCSR);
13018 /* this also writes a NOP command, clearing paging mode */
13019 write_csr(dd, ASIC_EEP_ADDR_CMD, 0);
13020 write_csr(dd, ASIC_EEP_DATA, 0);
77241056
MM		 13021}
13022
13023/* set MISC CSRs to chip reset defaults */
13024static void reset_misc_csrs(struct hfi1_devdata *dd)
13025{
13026 int i;
13027
13028 for (i = 0; i < 32; i++) {
13029 write_csr(dd, MISC_CFG_RSA_R2 + (8 * i), 0);
13030 write_csr(dd, MISC_CFG_RSA_SIGNATURE + (8 * i), 0);
13031 write_csr(dd, MISC_CFG_RSA_MODULUS + (8 * i), 0);
13032 }
13033 /* MISC_CFG_SHA_PRELOAD leave alone - always reads 0 and can
13034 only be written 128-byte chunks */
13035 /* init RSA engine to clear lingering errors */
13036 write_csr(dd, MISC_CFG_RSA_CMD, 1);
13037 write_csr(dd, MISC_CFG_RSA_MU, 0);
13038 write_csr(dd, MISC_CFG_FW_CTRL, 0);
13039 /* MISC_STS_8051_DIGEST read-only */
13040 /* MISC_STS_SBM_DIGEST read-only */
13041 /* MISC_STS_PCIE_DIGEST read-only */
13042 /* MISC_STS_FAB_DIGEST read-only */
13043 /* MISC_ERR_STATUS read-only */
13044 write_csr(dd, MISC_ERR_MASK, 0);
13045 write_csr(dd, MISC_ERR_CLEAR, ~0ull);
13046 /* MISC_ERR_FORCE leave alone */
13047}
13048
13049/* set TXE CSRs to chip reset defaults */
13050static void reset_txe_csrs(struct hfi1_devdata *dd)
13051{
13052 int i;
13053
13054 /*
13055 * TXE Kernel CSRs
13056 */
13057 write_csr(dd, SEND_CTRL, 0);
13058 __cm_reset(dd, 0); /* reset CM internal state */
13059 /* SEND_CONTEXTS read-only */
13060 /* SEND_DMA_ENGINES read-only */
13061 /* SEND_PIO_MEM_SIZE read-only */
13062 /* SEND_DMA_MEM_SIZE read-only */
13063 write_csr(dd, SEND_HIGH_PRIORITY_LIMIT, 0);
13064 pio_reset_all(dd); /* SEND_PIO_INIT_CTXT */
13065 /* SEND_PIO_ERR_STATUS read-only */
13066 write_csr(dd, SEND_PIO_ERR_MASK, 0);
13067 write_csr(dd, SEND_PIO_ERR_CLEAR, ~0ull);
13068 /* SEND_PIO_ERR_FORCE leave alone */
13069 /* SEND_DMA_ERR_STATUS read-only */
13070 write_csr(dd, SEND_DMA_ERR_MASK, 0);
13071 write_csr(dd, SEND_DMA_ERR_CLEAR, ~0ull);
13072 /* SEND_DMA_ERR_FORCE leave alone */
13073 /* SEND_EGRESS_ERR_STATUS read-only */
13074 write_csr(dd, SEND_EGRESS_ERR_MASK, 0);
13075 write_csr(dd, SEND_EGRESS_ERR_CLEAR, ~0ull);
13076 /* SEND_EGRESS_ERR_FORCE leave alone */
13077 write_csr(dd, SEND_BTH_QP, 0);
13078 write_csr(dd, SEND_STATIC_RATE_CONTROL, 0);
13079 write_csr(dd, SEND_SC2VLT0, 0);
13080 write_csr(dd, SEND_SC2VLT1, 0);
13081 write_csr(dd, SEND_SC2VLT2, 0);
13082 write_csr(dd, SEND_SC2VLT3, 0);
13083 write_csr(dd, SEND_LEN_CHECK0, 0);
13084 write_csr(dd, SEND_LEN_CHECK1, 0);
13085 /* SEND_ERR_STATUS read-only */
13086 write_csr(dd, SEND_ERR_MASK, 0);
13087 write_csr(dd, SEND_ERR_CLEAR, ~0ull);
13088 /* SEND_ERR_FORCE read-only */
13089 for (i = 0; i < VL_ARB_LOW_PRIO_TABLE_SIZE; i++)
8638b77f 13090 write_csr(dd, SEND_LOW_PRIORITY_LIST + (8 * i), 0);
77241056 13091 for (i = 0; i < VL_ARB_HIGH_PRIO_TABLE_SIZE; i++)
8638b77f
JJ		 13092 write_csr(dd, SEND_HIGH_PRIORITY_LIST + (8 * i), 0);
13093 for (i = 0; i < dd->chip_send_contexts / NUM_CONTEXTS_PER_SET; i++)
13094 write_csr(dd, SEND_CONTEXT_SET_CTRL + (8 * i), 0);
77241056 13095 for (i = 0; i < TXE_NUM_32_BIT_COUNTER; i++)
8638b77f 13096 write_csr(dd, SEND_COUNTER_ARRAY32 + (8 * i), 0);
77241056 13097 for (i = 0; i < TXE_NUM_64_BIT_COUNTER; i++)
8638b77f 13098 write_csr(dd, SEND_COUNTER_ARRAY64 + (8 * i), 0);
77241056
MM		 13099 write_csr(dd, SEND_CM_CTRL, SEND_CM_CTRL_RESETCSR);
13100 write_csr(dd, SEND_CM_GLOBAL_CREDIT,
13101 SEND_CM_GLOBAL_CREDIT_RESETCSR);
13102 /* SEND_CM_CREDIT_USED_STATUS read-only */
13103 write_csr(dd, SEND_CM_TIMER_CTRL, 0);
13104 write_csr(dd, SEND_CM_LOCAL_AU_TABLE0_TO3, 0);
13105 write_csr(dd, SEND_CM_LOCAL_AU_TABLE4_TO7, 0);
13106 write_csr(dd, SEND_CM_REMOTE_AU_TABLE0_TO3, 0);
13107 write_csr(dd, SEND_CM_REMOTE_AU_TABLE4_TO7, 0);
13108 for (i = 0; i < TXE_NUM_DATA_VL; i++)
8638b77f 13109 write_csr(dd, SEND_CM_CREDIT_VL + (8 * i), 0);
77241056
MM		 13110 write_csr(dd, SEND_CM_CREDIT_VL15, 0);
13111 /* SEND_CM_CREDIT_USED_VL read-only */
13112 /* SEND_CM_CREDIT_USED_VL15 read-only */
13113 /* SEND_EGRESS_CTXT_STATUS read-only */
13114 /* SEND_EGRESS_SEND_DMA_STATUS read-only */
13115 write_csr(dd, SEND_EGRESS_ERR_INFO, ~0ull);
13116 /* SEND_EGRESS_ERR_INFO read-only */
13117 /* SEND_EGRESS_ERR_SOURCE read-only */
13118
13119 /*
13120 * TXE Per-Context CSRs
13121 */
13122 for (i = 0; i < dd->chip_send_contexts; i++) {
13123 write_kctxt_csr(dd, i, SEND_CTXT_CTRL, 0);
13124 write_kctxt_csr(dd, i, SEND_CTXT_CREDIT_CTRL, 0);
13125 write_kctxt_csr(dd, i, SEND_CTXT_CREDIT_RETURN_ADDR, 0);
13126 write_kctxt_csr(dd, i, SEND_CTXT_CREDIT_FORCE, 0);
13127 write_kctxt_csr(dd, i, SEND_CTXT_ERR_MASK, 0);
13128 write_kctxt_csr(dd, i, SEND_CTXT_ERR_CLEAR, ~0ull);
13129 write_kctxt_csr(dd, i, SEND_CTXT_CHECK_ENABLE, 0);
13130 write_kctxt_csr(dd, i, SEND_CTXT_CHECK_VL, 0);
13131 write_kctxt_csr(dd, i, SEND_CTXT_CHECK_JOB_KEY, 0);
13132 write_kctxt_csr(dd, i, SEND_CTXT_CHECK_PARTITION_KEY, 0);
13133 write_kctxt_csr(dd, i, SEND_CTXT_CHECK_SLID, 0);
13134 write_kctxt_csr(dd, i, SEND_CTXT_CHECK_OPCODE, 0);
13135 }
13136
13137 /*
13138 * TXE Per-SDMA CSRs
13139 */
13140 for (i = 0; i < dd->chip_sdma_engines; i++) {
13141 write_kctxt_csr(dd, i, SEND_DMA_CTRL, 0);
13142 /* SEND_DMA_STATUS read-only */
13143 write_kctxt_csr(dd, i, SEND_DMA_BASE_ADDR, 0);
13144 write_kctxt_csr(dd, i, SEND_DMA_LEN_GEN, 0);
13145 write_kctxt_csr(dd, i, SEND_DMA_TAIL, 0);
13146 /* SEND_DMA_HEAD read-only */
13147 write_kctxt_csr(dd, i, SEND_DMA_HEAD_ADDR, 0);
13148 write_kctxt_csr(dd, i, SEND_DMA_PRIORITY_THLD, 0);
13149 /* SEND_DMA_IDLE_CNT read-only */
13150 write_kctxt_csr(dd, i, SEND_DMA_RELOAD_CNT, 0);
13151 write_kctxt_csr(dd, i, SEND_DMA_DESC_CNT, 0);
13152 /* SEND_DMA_DESC_FETCHED_CNT read-only */
13153 /* SEND_DMA_ENG_ERR_STATUS read-only */
13154 write_kctxt_csr(dd, i, SEND_DMA_ENG_ERR_MASK, 0);
13155 write_kctxt_csr(dd, i, SEND_DMA_ENG_ERR_CLEAR, ~0ull);
13156 /* SEND_DMA_ENG_ERR_FORCE leave alone */
13157 write_kctxt_csr(dd, i, SEND_DMA_CHECK_ENABLE, 0);
13158 write_kctxt_csr(dd, i, SEND_DMA_CHECK_VL, 0);
13159 write_kctxt_csr(dd, i, SEND_DMA_CHECK_JOB_KEY, 0);
13160 write_kctxt_csr(dd, i, SEND_DMA_CHECK_PARTITION_KEY, 0);
13161 write_kctxt_csr(dd, i, SEND_DMA_CHECK_SLID, 0);
13162 write_kctxt_csr(dd, i, SEND_DMA_CHECK_OPCODE, 0);
13163 write_kctxt_csr(dd, i, SEND_DMA_MEMORY, 0);
13164 }
13165}
13166
13167/*
13168 * Expect on entry:
13169 * o Packet ingress is disabled, i.e. RcvCtrl.RcvPortEnable == 0
13170 */
13171static void init_rbufs(struct hfi1_devdata *dd)
13172{
13173 u64 reg;
13174 int count;
13175
13176 /*
13177 * Wait for DMA to stop: RxRbufPktPending and RxPktInProgress are
13178 * clear.
13179 */
13180 count = 0;
13181 while (1) {
13182 reg = read_csr(dd, RCV_STATUS);
13183 if ((reg & (RCV_STATUS_RX_RBUF_PKT_PENDING_SMASK
13184 | RCV_STATUS_RX_PKT_IN_PROGRESS_SMASK)) == 0)
13185 break;
13186 /*
13187 * Give up after 1ms - maximum wait time.
13188 *
13189 * RBuf size is 148KiB. Slowest possible is PCIe Gen1 x1 at
13190 * 250MB/s bandwidth. Lower rate to 66% for overhead to get:
13191 * 148 KB / (66% * 250MB/s) = 920us
13192 */
13193 if (count++ > 500) {
13194 dd_dev_err(dd,
13195 "%s: in-progress DMA not clearing: RcvStatus 0x%llx, continuing\n",
13196 __func__, reg);
13197 break;
13198 }
13199 udelay(2); /* do not busy-wait the CSR */
13200 }
13201
13202 /* start the init - expect RcvCtrl to be 0 */
13203 write_csr(dd, RCV_CTRL, RCV_CTRL_RX_RBUF_INIT_SMASK);
13204
13205 /*
13206 * Read to force the write of Rcvtrl.RxRbufInit. There is a brief
13207 * period after the write before RcvStatus.RxRbufInitDone is valid.
13208 * The delay in the first run through the loop below is sufficient and
13209 * required before the first read of RcvStatus.RxRbufInintDone.
13210 */
13211 read_csr(dd, RCV_CTRL);
13212
13213 /* wait for the init to finish */
13214 count = 0;
13215 while (1) {
13216 /* delay is required first time through - see above */
13217 udelay(2); /* do not busy-wait the CSR */
13218 reg = read_csr(dd, RCV_STATUS);
13219 if (reg & (RCV_STATUS_RX_RBUF_INIT_DONE_SMASK))
13220 break;
13221
13222 /* give up after 100us - slowest possible at 33MHz is 73us */
13223 if (count++ > 50) {
13224 dd_dev_err(dd,
13225 "%s: RcvStatus.RxRbufInit not set, continuing\n",
13226 __func__);
13227 break;
13228 }
13229 }
13230}
13231
13232/* set RXE CSRs to chip reset defaults */
13233static void reset_rxe_csrs(struct hfi1_devdata *dd)
13234{
13235 int i, j;
13236
13237 /*
13238 * RXE Kernel CSRs
13239 */
13240 write_csr(dd, RCV_CTRL, 0);
13241 init_rbufs(dd);
13242 /* RCV_STATUS read-only */
13243 /* RCV_CONTEXTS read-only */
13244 /* RCV_ARRAY_CNT read-only */
13245 /* RCV_BUF_SIZE read-only */
13246 write_csr(dd, RCV_BTH_QP, 0);
13247 write_csr(dd, RCV_MULTICAST, 0);
13248 write_csr(dd, RCV_BYPASS, 0);
13249 write_csr(dd, RCV_VL15, 0);
13250 /* this is a clear-down */
13251 write_csr(dd, RCV_ERR_INFO,
13252 RCV_ERR_INFO_RCV_EXCESS_BUFFER_OVERRUN_SMASK);
13253 /* RCV_ERR_STATUS read-only */
13254 write_csr(dd, RCV_ERR_MASK, 0);
13255 write_csr(dd, RCV_ERR_CLEAR, ~0ull);
13256 /* RCV_ERR_FORCE leave alone */
13257 for (i = 0; i < 32; i++)
13258 write_csr(dd, RCV_QP_MAP_TABLE + (8 * i), 0);
13259 for (i = 0; i < 4; i++)
13260 write_csr(dd, RCV_PARTITION_KEY + (8 * i), 0);
13261 for (i = 0; i < RXE_NUM_32_BIT_COUNTERS; i++)
13262 write_csr(dd, RCV_COUNTER_ARRAY32 + (8 * i), 0);
13263 for (i = 0; i < RXE_NUM_64_BIT_COUNTERS; i++)
13264 write_csr(dd, RCV_COUNTER_ARRAY64 + (8 * i), 0);
13265 for (i = 0; i < RXE_NUM_RSM_INSTANCES; i++) {
13266 write_csr(dd, RCV_RSM_CFG + (8 * i), 0);
13267 write_csr(dd, RCV_RSM_SELECT + (8 * i), 0);
13268 write_csr(dd, RCV_RSM_MATCH + (8 * i), 0);
13269 }
13270 for (i = 0; i < 32; i++)
13271 write_csr(dd, RCV_RSM_MAP_TABLE + (8 * i), 0);
13272
13273 /*
13274 * RXE Kernel and User Per-Context CSRs
13275 */
13276 for (i = 0; i < dd->chip_rcv_contexts; i++) {
13277 /* kernel */
13278 write_kctxt_csr(dd, i, RCV_CTXT_CTRL, 0);
13279 /* RCV_CTXT_STATUS read-only */
13280 write_kctxt_csr(dd, i, RCV_EGR_CTRL, 0);
13281 write_kctxt_csr(dd, i, RCV_TID_CTRL, 0);
13282 write_kctxt_csr(dd, i, RCV_KEY_CTRL, 0);
13283 write_kctxt_csr(dd, i, RCV_HDR_ADDR, 0);
13284 write_kctxt_csr(dd, i, RCV_HDR_CNT, 0);
13285 write_kctxt_csr(dd, i, RCV_HDR_ENT_SIZE, 0);
13286 write_kctxt_csr(dd, i, RCV_HDR_SIZE, 0);
13287 write_kctxt_csr(dd, i, RCV_HDR_TAIL_ADDR, 0);
13288 write_kctxt_csr(dd, i, RCV_AVAIL_TIME_OUT, 0);
13289 write_kctxt_csr(dd, i, RCV_HDR_OVFL_CNT, 0);
13290
13291 /* user */
13292 /* RCV_HDR_TAIL read-only */
13293 write_uctxt_csr(dd, i, RCV_HDR_HEAD, 0);
13294 /* RCV_EGR_INDEX_TAIL read-only */
13295 write_uctxt_csr(dd, i, RCV_EGR_INDEX_HEAD, 0);
13296 /* RCV_EGR_OFFSET_TAIL read-only */
13297 for (j = 0; j < RXE_NUM_TID_FLOWS; j++) {
13298 write_uctxt_csr(dd, i, RCV_TID_FLOW_TABLE + (8 * j),
13299 0);
13300 }
13301 }
13302}
13303
13304/*
13305 * Set sc2vl tables.
13306 *
13307 * They power on to zeros, so to avoid send context errors
13308 * they need to be set:
13309 *
13310 * SC 0-7 -> VL 0-7 (respectively)
13311 * SC 15 -> VL 15
13312 * otherwise
13313 * -> VL 0
13314 */
13315static void init_sc2vl_tables(struct hfi1_devdata *dd)
13316{
13317 int i;
13318 /* init per architecture spec, constrained by hardware capability */
13319
13320 /* HFI maps sent packets */
13321 write_csr(dd, SEND_SC2VLT0, SC2VL_VAL(
13322 0,
13323 0, 0, 1, 1,
13324 2, 2, 3, 3,
13325 4, 4, 5, 5,
13326 6, 6, 7, 7));
13327 write_csr(dd, SEND_SC2VLT1, SC2VL_VAL(
13328 1,
13329 8, 0, 9, 0,
13330 10, 0, 11, 0,
13331 12, 0, 13, 0,
13332 14, 0, 15, 15));
13333 write_csr(dd, SEND_SC2VLT2, SC2VL_VAL(
13334 2,
13335 16, 0, 17, 0,
13336 18, 0, 19, 0,
13337 20, 0, 21, 0,
13338 22, 0, 23, 0));
13339 write_csr(dd, SEND_SC2VLT3, SC2VL_VAL(
13340 3,
13341 24, 0, 25, 0,
13342 26, 0, 27, 0,
13343 28, 0, 29, 0,
13344 30, 0, 31, 0));
13345
13346 /* DC maps received packets */
13347 write_csr(dd, DCC_CFG_SC_VL_TABLE_15_0, DC_SC_VL_VAL(
13348 15_0,
13349 0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7,
13350 8, 0, 9, 0, 10, 0, 11, 0, 12, 0, 13, 0, 14, 0, 15, 15));
13351 write_csr(dd, DCC_CFG_SC_VL_TABLE_31_16, DC_SC_VL_VAL(
13352 31_16,
13353 16, 0, 17, 0, 18, 0, 19, 0, 20, 0, 21, 0, 22, 0, 23, 0,
13354 24, 0, 25, 0, 26, 0, 27, 0, 28, 0, 29, 0, 30, 0, 31, 0));
13355
13356 /* initialize the cached sc2vl values consistently with h/w */
13357 for (i = 0; i < 32; i++) {
13358 if (i < 8 || i == 15)
13359 *((u8 *)(dd->sc2vl) + i) = (u8)i;
13360 else
13361 *((u8 *)(dd->sc2vl) + i) = 0;
13362 }
13363}
13364
13365/*
13366 * Read chip sizes and then reset parts to sane, disabled, values. We cannot
13367 * depend on the chip going through a power-on reset - a driver may be loaded
13368 * and unloaded many times.
13369 *
13370 * Do not write any CSR values to the chip in this routine - there may be
13371 * a reset following the (possible) FLR in this routine.
13372 *
13373 */
13374static void init_chip(struct hfi1_devdata *dd)
13375{
13376 int i;
13377
13378 /*
13379 * Put the HFI CSRs in a known state.
13380 * Combine this with a DC reset.
13381 *
13382 * Stop the device from doing anything while we do a
13383 * reset. We know there are no other active users of
13384 * the device since we are now in charge. Turn off
13385 * off all outbound and inbound traffic and make sure
13386 * the device does not generate any interrupts.
13387 */
13388
13389 /* disable send contexts and SDMA engines */
13390 write_csr(dd, SEND_CTRL, 0);
13391 for (i = 0; i < dd->chip_send_contexts; i++)
13392 write_kctxt_csr(dd, i, SEND_CTXT_CTRL, 0);
13393 for (i = 0; i < dd->chip_sdma_engines; i++)
13394 write_kctxt_csr(dd, i, SEND_DMA_CTRL, 0);
13395 /* disable port (turn off RXE inbound traffic) and contexts */
13396 write_csr(dd, RCV_CTRL, 0);
13397 for (i = 0; i < dd->chip_rcv_contexts; i++)
13398 write_csr(dd, RCV_CTXT_CTRL, 0);
13399 /* mask all interrupt sources */
13400 for (i = 0; i < CCE_NUM_INT_CSRS; i++)
8638b77f 13401 write_csr(dd, CCE_INT_MASK + (8 * i), 0ull);
77241056
MM		 13402
13403 /*
13404 * DC Reset: do a full DC reset before the register clear.
13405 * A recommended length of time to hold is one CSR read,
13406 * so reread the CceDcCtrl. Then, hold the DC in reset
13407 * across the clear.
13408 */
13409 write_csr(dd, CCE_DC_CTRL, CCE_DC_CTRL_DC_RESET_SMASK);
50e5dcbe 13410 (void)read_csr(dd, CCE_DC_CTRL);
77241056
MM		 13411
13412 if (use_flr) {
13413 /*
13414 * A FLR will reset the SPC core and part of the PCIe.
13415 * The parts that need to be restored have already been
13416 * saved.
13417 */
13418 dd_dev_info(dd, "Resetting CSRs with FLR\n");
13419
13420 /* do the FLR, the DC reset will remain */
13421 hfi1_pcie_flr(dd);
13422
13423 /* restore command and BARs */
13424 restore_pci_variables(dd);
13425
995deafa 13426 if (is_ax(dd)) {
77241056
MM		 13427 dd_dev_info(dd, "Resetting CSRs with FLR\n");
13428 hfi1_pcie_flr(dd);
13429 restore_pci_variables(dd);
13430 }
13431
7c03ed85 13432 reset_asic_csrs(dd);
77241056
MM		 13433 } else {
13434 dd_dev_info(dd, "Resetting CSRs with writes\n");
13435 reset_cce_csrs(dd);
13436 reset_txe_csrs(dd);
13437 reset_rxe_csrs(dd);
13438 reset_asic_csrs(dd);
13439 reset_misc_csrs(dd);
13440 }
13441 /* clear the DC reset */
13442 write_csr(dd, CCE_DC_CTRL, 0);
7c03ed85 13443
77241056 13444 /* Set the LED off */
773d0451
SS		 13445 setextled(dd, 0);
13446
77241056
MM		 13447 /*
13448 * Clear the QSFP reset.
72a67ba2 13449 * An FLR enforces a 0 on all out pins. The driver does not touch
77241056 13450 * ASIC_QSFPn_OUT otherwise. This leaves RESET_N low and
72a67ba2 13451 * anything plugged constantly in reset, if it pays attention
77241056 13452 * to RESET_N.
72a67ba2 13453 * Prime examples of this are optical cables. Set all pins high.
77241056
MM		 13454 * I2CCLK and I2CDAT will change per direction, and INT_N and
13455 * MODPRS_N are input only and their value is ignored.
13456 */
72a67ba2
EH		 13457 write_csr(dd, ASIC_QSFP1_OUT, 0x1f);
13458 write_csr(dd, ASIC_QSFP2_OUT, 0x1f);
77241056
MM		 13459}
13460
13461static void init_early_variables(struct hfi1_devdata *dd)
13462{
13463 int i;
13464
13465 /* assign link credit variables */
13466 dd->vau = CM_VAU;
13467 dd->link_credits = CM_GLOBAL_CREDITS;
995deafa 13468 if (is_ax(dd))
77241056
MM		 13469 dd->link_credits--;
13470 dd->vcu = cu_to_vcu(hfi1_cu);
13471 /* enough room for 8 MAD packets plus header - 17K */
13472 dd->vl15_init = (8 * (2048 + 128)) / vau_to_au(dd->vau);
13473 if (dd->vl15_init > dd->link_credits)
13474 dd->vl15_init = dd->link_credits;
13475
13476 write_uninitialized_csrs_and_memories(dd);
13477
13478 if (HFI1_CAP_IS_KSET(PKEY_CHECK))
13479 for (i = 0; i < dd->num_pports; i++) {
13480 struct hfi1_pportdata *ppd = &dd->pport[i];
13481
13482 set_partition_keys(ppd);
13483 }
13484 init_sc2vl_tables(dd);
13485}
13486
13487static void init_kdeth_qp(struct hfi1_devdata *dd)
13488{
13489 /* user changed the KDETH_QP */
13490 if (kdeth_qp != 0 && kdeth_qp >= 0xff) {
13491 /* out of range or illegal value */
13492 dd_dev_err(dd, "Invalid KDETH queue pair prefix, ignoring");
13493 kdeth_qp = 0;
13494 }
13495 if (kdeth_qp == 0) /* not set, or failed range check */
13496 kdeth_qp = DEFAULT_KDETH_QP;
13497
13498 write_csr(dd, SEND_BTH_QP,
13499 (kdeth_qp & SEND_BTH_QP_KDETH_QP_MASK)
13500 << SEND_BTH_QP_KDETH_QP_SHIFT);
13501
13502 write_csr(dd, RCV_BTH_QP,
13503 (kdeth_qp & RCV_BTH_QP_KDETH_QP_MASK)
13504 << RCV_BTH_QP_KDETH_QP_SHIFT);
13505}
13506
13507/**
13508 * init_qpmap_table
13509 * @dd - device data
13510 * @first_ctxt - first context
13511 * @last_ctxt - first context
13512 *
13513 * This return sets the qpn mapping table that
13514 * is indexed by qpn[8:1].
13515 *
13516 * The routine will round robin the 256 settings
13517 * from first_ctxt to last_ctxt.
13518 *
13519 * The first/last looks ahead to having specialized
13520 * receive contexts for mgmt and bypass. Normal
13521 * verbs traffic will assumed to be on a range
13522 * of receive contexts.
13523 */
13524static void init_qpmap_table(struct hfi1_devdata *dd,
13525 u32 first_ctxt,
13526 u32 last_ctxt)
13527{
13528 u64 reg = 0;
13529 u64 regno = RCV_QP_MAP_TABLE;
13530 int i;
13531 u64 ctxt = first_ctxt;
13532
13533 for (i = 0; i < 256;) {
77241056
MM		 13534 reg |= ctxt << (8 * (i % 8));
13535 i++;
13536 ctxt++;
13537 if (ctxt > last_ctxt)
13538 ctxt = first_ctxt;
13539 if (i % 8 == 0) {
13540 write_csr(dd, regno, reg);
13541 reg = 0;
13542 regno += 8;
13543 }
13544 }
13545 if (i % 8)
13546 write_csr(dd, regno, reg);
13547
13548 add_rcvctrl(dd, RCV_CTRL_RCV_QP_MAP_ENABLE_SMASK
13549 | RCV_CTRL_RCV_BYPASS_ENABLE_SMASK);
13550}
13551
13552/**
13553 * init_qos - init RX qos
13554 * @dd - device data
13555 * @first_context
13556 *
13557 * This routine initializes Rule 0 and the
13558 * RSM map table to implement qos.
13559 *
13560 * If all of the limit tests succeed,
13561 * qos is applied based on the array
13562 * interpretation of krcvqs where
13563 * entry 0 is VL0.
13564 *
13565 * The number of vl bits (n) and the number of qpn
13566 * bits (m) are computed to feed both the RSM map table
13567 * and the single rule.
13568 *
13569 */
13570static void init_qos(struct hfi1_devdata *dd, u32 first_ctxt)
13571{
13572 u8 max_by_vl = 0;
13573 unsigned qpns_per_vl, ctxt, i, qpn, n = 1, m;
13574 u64 *rsmmap;
13575 u64 reg;
995deafa 13576 u8 rxcontext = is_ax(dd) ? 0 : 0xff; /* 0 is default if a0 ver. */
77241056
MM		 13577
13578 /* validate */
13579 if (dd->n_krcv_queues <= MIN_KERNEL_KCTXTS ||
13580 num_vls == 1 ||
13581 krcvqsset <= 1)
13582 goto bail;
13583 for (i = 0; i < min_t(unsigned, num_vls, krcvqsset); i++)
13584 if (krcvqs[i] > max_by_vl)
13585 max_by_vl = krcvqs[i];
13586 if (max_by_vl > 32)
13587 goto bail;
13588 qpns_per_vl = __roundup_pow_of_two(max_by_vl);
13589 /* determine bits vl */
13590 n = ilog2(num_vls);
13591 /* determine bits for qpn */
13592 m = ilog2(qpns_per_vl);
13593 if ((m + n) > 7)
13594 goto bail;
13595 if (num_vls * qpns_per_vl > dd->chip_rcv_contexts)
13596 goto bail;
13597 rsmmap = kmalloc_array(NUM_MAP_REGS, sizeof(u64), GFP_KERNEL);
859bcad9
EH		 13598 if (!rsmmap)
13599 goto bail;
77241056
MM		 13600 memset(rsmmap, rxcontext, NUM_MAP_REGS * sizeof(u64));
13601 /* init the local copy of the table */
13602 for (i = 0, ctxt = first_ctxt; i < num_vls; i++) {
13603 unsigned tctxt;
13604
13605 for (qpn = 0, tctxt = ctxt;
13606 krcvqs[i] && qpn < qpns_per_vl; qpn++) {
13607 unsigned idx, regoff, regidx;
13608
13609 /* generate index <= 128 */
13610 idx = (qpn << n) ^ i;
13611 regoff = (idx % 8) * 8;
13612 regidx = idx / 8;
13613 reg = rsmmap[regidx];
13614 /* replace 0xff with context number */
13615 reg &= ~(RCV_RSM_MAP_TABLE_RCV_CONTEXT_A_MASK
13616 << regoff);
13617 reg |= (u64)(tctxt++) << regoff;
13618 rsmmap[regidx] = reg;
13619 if (tctxt == ctxt + krcvqs[i])
13620 tctxt = ctxt;
13621 }
13622 ctxt += krcvqs[i];
13623 }
13624 /* flush cached copies to chip */
13625 for (i = 0; i < NUM_MAP_REGS; i++)
13626 write_csr(dd, RCV_RSM_MAP_TABLE + (8 * i), rsmmap[i]);
13627 /* add rule0 */
13628 write_csr(dd, RCV_RSM_CFG /* + (8 * 0) */,
13629 RCV_RSM_CFG_ENABLE_OR_CHAIN_RSM0_MASK
13630 << RCV_RSM_CFG_ENABLE_OR_CHAIN_RSM0_SHIFT |
13631 2ull << RCV_RSM_CFG_PACKET_TYPE_SHIFT);
13632 write_csr(dd, RCV_RSM_SELECT /* + (8 * 0) */,
13633 LRH_BTH_MATCH_OFFSET
13634 << RCV_RSM_SELECT_FIELD1_OFFSET_SHIFT |
13635 LRH_SC_MATCH_OFFSET << RCV_RSM_SELECT_FIELD2_OFFSET_SHIFT |
13636 LRH_SC_SELECT_OFFSET << RCV_RSM_SELECT_INDEX1_OFFSET_SHIFT |
13637 ((u64)n) << RCV_RSM_SELECT_INDEX1_WIDTH_SHIFT |
13638 QPN_SELECT_OFFSET << RCV_RSM_SELECT_INDEX2_OFFSET_SHIFT |
13639 ((u64)m + (u64)n) << RCV_RSM_SELECT_INDEX2_WIDTH_SHIFT);
13640 write_csr(dd, RCV_RSM_MATCH /* + (8 * 0) */,
13641 LRH_BTH_MASK << RCV_RSM_MATCH_MASK1_SHIFT |
13642 LRH_BTH_VALUE << RCV_RSM_MATCH_VALUE1_SHIFT |
13643 LRH_SC_MASK << RCV_RSM_MATCH_MASK2_SHIFT |
13644 LRH_SC_VALUE << RCV_RSM_MATCH_VALUE2_SHIFT);
13645 /* Enable RSM */
13646 add_rcvctrl(dd, RCV_CTRL_RCV_RSM_ENABLE_SMASK);
13647 kfree(rsmmap);
82c2611d
NV		 13648 /* map everything else to first context */
13649 init_qpmap_table(dd, FIRST_KERNEL_KCTXT, MIN_KERNEL_KCTXTS - 1);
77241056
MM		 13650 dd->qos_shift = n + 1;
13651 return;
13652bail:
13653 dd->qos_shift = 1;
82c2611d 13654 init_qpmap_table(dd, FIRST_KERNEL_KCTXT, dd->n_krcv_queues - 1);
77241056
MM		 13655}
13656
13657static void init_rxe(struct hfi1_devdata *dd)
13658{
13659 /* enable all receive errors */
13660 write_csr(dd, RCV_ERR_MASK, ~0ull);
13661 /* setup QPN map table - start where VL15 context leaves off */
13662 init_qos(
13663 dd,
13664 dd->n_krcv_queues > MIN_KERNEL_KCTXTS ? MIN_KERNEL_KCTXTS : 0);
13665 /*
13666 * make sure RcvCtrl.RcvWcb <= PCIe Device Control
13667 * Register Max_Payload_Size (PCI_EXP_DEVCTL in Linux PCIe config
13668 * space, PciCfgCap2.MaxPayloadSize in HFI). There is only one
13669 * invalid configuration: RcvCtrl.RcvWcb set to its max of 256 and
13670 * Max_PayLoad_Size set to its minimum of 128.
13671 *
13672 * Presently, RcvCtrl.RcvWcb is not modified from its default of 0
13673 * (64 bytes). Max_Payload_Size is possibly modified upward in
13674 * tune_pcie_caps() which is called after this routine.
13675 */
13676}
13677
13678static void init_other(struct hfi1_devdata *dd)
13679{
13680 /* enable all CCE errors */
13681 write_csr(dd, CCE_ERR_MASK, ~0ull);
13682 /* enable *some* Misc errors */
13683 write_csr(dd, MISC_ERR_MASK, DRIVER_MISC_MASK);
13684 /* enable all DC errors, except LCB */
13685 write_csr(dd, DCC_ERR_FLG_EN, ~0ull);
13686 write_csr(dd, DC_DC8051_ERR_EN, ~0ull);
13687}
13688
13689/*
13690 * Fill out the given AU table using the given CU. A CU is defined in terms
13691 * AUs. The table is a an encoding: given the index, how many AUs does that
13692 * represent?
13693 *
13694 * NOTE: Assumes that the register layout is the same for the
13695 * local and remote tables.
13696 */
13697static void assign_cm_au_table(struct hfi1_devdata *dd, u32 cu,
13698 u32 csr0to3, u32 csr4to7)
13699{
13700 write_csr(dd, csr0to3,
13701 0ull <<
13702 SEND_CM_LOCAL_AU_TABLE0_TO3_LOCAL_AU_TABLE0_SHIFT
13703 | 1ull <<
13704 SEND_CM_LOCAL_AU_TABLE0_TO3_LOCAL_AU_TABLE1_SHIFT
13705 | 2ull * cu <<
13706 SEND_CM_LOCAL_AU_TABLE0_TO3_LOCAL_AU_TABLE2_SHIFT
13707 | 4ull * cu <<
13708 SEND_CM_LOCAL_AU_TABLE0_TO3_LOCAL_AU_TABLE3_SHIFT);
13709 write_csr(dd, csr4to7,
13710 8ull * cu <<
13711 SEND_CM_LOCAL_AU_TABLE4_TO7_LOCAL_AU_TABLE4_SHIFT
13712 | 16ull * cu <<
13713 SEND_CM_LOCAL_AU_TABLE4_TO7_LOCAL_AU_TABLE5_SHIFT
13714 | 32ull * cu <<
13715 SEND_CM_LOCAL_AU_TABLE4_TO7_LOCAL_AU_TABLE6_SHIFT
13716 | 64ull * cu <<
13717 SEND_CM_LOCAL_AU_TABLE4_TO7_LOCAL_AU_TABLE7_SHIFT);
13718
13719}
13720
13721static void assign_local_cm_au_table(struct hfi1_devdata *dd, u8 vcu)
13722{
13723 assign_cm_au_table(dd, vcu_to_cu(vcu), SEND_CM_LOCAL_AU_TABLE0_TO3,
13724 SEND_CM_LOCAL_AU_TABLE4_TO7);
13725}
13726
13727void assign_remote_cm_au_table(struct hfi1_devdata *dd, u8 vcu)
13728{
13729 assign_cm_au_table(dd, vcu_to_cu(vcu), SEND_CM_REMOTE_AU_TABLE0_TO3,
13730 SEND_CM_REMOTE_AU_TABLE4_TO7);
13731}
13732
13733static void init_txe(struct hfi1_devdata *dd)
13734{
13735 int i;
13736
13737 /* enable all PIO, SDMA, general, and Egress errors */
13738 write_csr(dd, SEND_PIO_ERR_MASK, ~0ull);
13739 write_csr(dd, SEND_DMA_ERR_MASK, ~0ull);
13740 write_csr(dd, SEND_ERR_MASK, ~0ull);
13741 write_csr(dd, SEND_EGRESS_ERR_MASK, ~0ull);
13742
13743 /* enable all per-context and per-SDMA engine errors */
13744 for (i = 0; i < dd->chip_send_contexts; i++)
13745 write_kctxt_csr(dd, i, SEND_CTXT_ERR_MASK, ~0ull);
13746 for (i = 0; i < dd->chip_sdma_engines; i++)
13747 write_kctxt_csr(dd, i, SEND_DMA_ENG_ERR_MASK, ~0ull);
13748
13749 /* set the local CU to AU mapping */
13750 assign_local_cm_au_table(dd, dd->vcu);
13751
13752 /*
13753 * Set reasonable default for Credit Return Timer
13754 * Don't set on Simulator - causes it to choke.
13755 */
13756 if (dd->icode != ICODE_FUNCTIONAL_SIMULATOR)
13757 write_csr(dd, SEND_CM_TIMER_CTRL, HFI1_CREDIT_RETURN_RATE);
13758}
13759
13760int hfi1_set_ctxt_jkey(struct hfi1_devdata *dd, unsigned ctxt, u16 jkey)
13761{
13762 struct hfi1_ctxtdata *rcd = dd->rcd[ctxt];
13763 unsigned sctxt;
13764 int ret = 0;
13765 u64 reg;
13766
13767 if (!rcd || !rcd->sc) {
13768 ret = -EINVAL;
13769 goto done;
13770 }
13771 sctxt = rcd->sc->hw_context;
13772 reg = SEND_CTXT_CHECK_JOB_KEY_MASK_SMASK | /* mask is always 1's */
13773 ((jkey & SEND_CTXT_CHECK_JOB_KEY_VALUE_MASK) <<
13774 SEND_CTXT_CHECK_JOB_KEY_VALUE_SHIFT);
13775 /* JOB_KEY_ALLOW_PERMISSIVE is not allowed by default */
13776 if (HFI1_CAP_KGET_MASK(rcd->flags, ALLOW_PERM_JKEY))
13777 reg |= SEND_CTXT_CHECK_JOB_KEY_ALLOW_PERMISSIVE_SMASK;
13778 write_kctxt_csr(dd, sctxt, SEND_CTXT_CHECK_JOB_KEY, reg);
13779 /*
13780 * Enable send-side J_KEY integrity check, unless this is A0 h/w
77241056 13781 */
995deafa 13782 if (!is_ax(dd)) {
77241056
MM		 13783 reg = read_kctxt_csr(dd, sctxt, SEND_CTXT_CHECK_ENABLE);
13784 reg |= SEND_CTXT_CHECK_ENABLE_CHECK_JOB_KEY_SMASK;
13785 write_kctxt_csr(dd, sctxt, SEND_CTXT_CHECK_ENABLE, reg);
13786 }
13787
13788 /* Enable J_KEY check on receive context. */
13789 reg = RCV_KEY_CTRL_JOB_KEY_ENABLE_SMASK |
13790 ((jkey & RCV_KEY_CTRL_JOB_KEY_VALUE_MASK) <<
13791 RCV_KEY_CTRL_JOB_KEY_VALUE_SHIFT);
13792 write_kctxt_csr(dd, ctxt, RCV_KEY_CTRL, reg);
13793done:
13794 return ret;
13795}
13796
13797int hfi1_clear_ctxt_jkey(struct hfi1_devdata *dd, unsigned ctxt)
13798{
13799 struct hfi1_ctxtdata *rcd = dd->rcd[ctxt];
13800 unsigned sctxt;
13801 int ret = 0;
13802 u64 reg;
13803
13804 if (!rcd || !rcd->sc) {
13805 ret = -EINVAL;
13806 goto done;
13807 }
13808 sctxt = rcd->sc->hw_context;
13809 write_kctxt_csr(dd, sctxt, SEND_CTXT_CHECK_JOB_KEY, 0);
13810 /*
13811 * Disable send-side J_KEY integrity check, unless this is A0 h/w.
13812 * This check would not have been enabled for A0 h/w, see
13813 * set_ctxt_jkey().
13814 */
995deafa 13815 if (!is_ax(dd)) {
77241056
MM		 13816 reg = read_kctxt_csr(dd, sctxt, SEND_CTXT_CHECK_ENABLE);
13817 reg &= ~SEND_CTXT_CHECK_ENABLE_CHECK_JOB_KEY_SMASK;
13818 write_kctxt_csr(dd, sctxt, SEND_CTXT_CHECK_ENABLE, reg);
13819 }
13820 /* Turn off the J_KEY on the receive side */
13821 write_kctxt_csr(dd, ctxt, RCV_KEY_CTRL, 0);
13822done:
13823 return ret;
13824}
13825
13826int hfi1_set_ctxt_pkey(struct hfi1_devdata *dd, unsigned ctxt, u16 pkey)
13827{
13828 struct hfi1_ctxtdata *rcd;
13829 unsigned sctxt;
13830 int ret = 0;
13831 u64 reg;
13832
13833 if (ctxt < dd->num_rcv_contexts)
13834 rcd = dd->rcd[ctxt];
13835 else {
13836 ret = -EINVAL;
13837 goto done;
13838 }
13839 if (!rcd || !rcd->sc) {
13840 ret = -EINVAL;
13841 goto done;
13842 }
13843 sctxt = rcd->sc->hw_context;
13844 reg = ((u64)pkey & SEND_CTXT_CHECK_PARTITION_KEY_VALUE_MASK) <<
13845 SEND_CTXT_CHECK_PARTITION_KEY_VALUE_SHIFT;
13846 write_kctxt_csr(dd, sctxt, SEND_CTXT_CHECK_PARTITION_KEY, reg);
13847 reg = read_kctxt_csr(dd, sctxt, SEND_CTXT_CHECK_ENABLE);
13848 reg |= SEND_CTXT_CHECK_ENABLE_CHECK_PARTITION_KEY_SMASK;
13849 write_kctxt_csr(dd, sctxt, SEND_CTXT_CHECK_ENABLE, reg);
13850done:
13851 return ret;
13852}
13853
13854int hfi1_clear_ctxt_pkey(struct hfi1_devdata *dd, unsigned ctxt)
13855{
13856 struct hfi1_ctxtdata *rcd;
13857 unsigned sctxt;
13858 int ret = 0;
13859 u64 reg;
13860
13861 if (ctxt < dd->num_rcv_contexts)
13862 rcd = dd->rcd[ctxt];
13863 else {
13864 ret = -EINVAL;
13865 goto done;
13866 }
13867 if (!rcd || !rcd->sc) {
13868 ret = -EINVAL;
13869 goto done;
13870 }
13871 sctxt = rcd->sc->hw_context;
13872 reg = read_kctxt_csr(dd, sctxt, SEND_CTXT_CHECK_ENABLE);
13873 reg &= ~SEND_CTXT_CHECK_ENABLE_CHECK_PARTITION_KEY_SMASK;
13874 write_kctxt_csr(dd, sctxt, SEND_CTXT_CHECK_ENABLE, reg);
13875 write_kctxt_csr(dd, sctxt, SEND_CTXT_CHECK_PARTITION_KEY, 0);
13876done:
13877 return ret;
13878}
13879
13880/*
13881 * Start doing the clean up the the chip. Our clean up happens in multiple
13882 * stages and this is just the first.
13883 */
13884void hfi1_start_cleanup(struct hfi1_devdata *dd)
13885{
affa48de 13886 aspm_exit(dd);
77241056
MM		 13887 free_cntrs(dd);
13888 free_rcverr(dd);
13889 clean_up_interrupts(dd);
13890}
13891
13892#define HFI_BASE_GUID(dev) \
13893 ((dev)->base_guid & ~(1ULL << GUID_HFI_INDEX_SHIFT))
13894
13895/*
13896 * Certain chip functions need to be initialized only once per asic
13897 * instead of per-device. This function finds the peer device and
13898 * checks whether that chip initialization needs to be done by this
13899 * device.
13900 */
13901static void asic_should_init(struct hfi1_devdata *dd)
13902{
13903 unsigned long flags;
13904 struct hfi1_devdata *tmp, *peer = NULL;
13905
13906 spin_lock_irqsave(&hfi1_devs_lock, flags);
13907 /* Find our peer device */
13908 list_for_each_entry(tmp, &hfi1_dev_list, list) {
13909 if ((HFI_BASE_GUID(dd) == HFI_BASE_GUID(tmp)) &&
13910 dd->unit != tmp->unit) {
13911 peer = tmp;
13912 break;
13913 }
13914 }
13915
13916 /*
13917 * "Claim" the ASIC for initialization if it hasn't been
13918 " "claimed" yet.
13919 */
13920 if (!peer || !(peer->flags & HFI1_DO_INIT_ASIC))
13921 dd->flags |= HFI1_DO_INIT_ASIC;
13922 spin_unlock_irqrestore(&hfi1_devs_lock, flags);
13923}
13924
5d9157aa
DL		 13925/*
13926 * Set dd->boardname. Use a generic name if a name is not returned from
13927 * EFI variable space.
13928 *
13929 * Return 0 on success, -ENOMEM if space could not be allocated.
13930 */
13931static int obtain_boardname(struct hfi1_devdata *dd)
13932{
13933 /* generic board description */
13934 const char generic[] =
13935 "Intel Omni-Path Host Fabric Interface Adapter 100 Series";
13936 unsigned long size;
13937 int ret;
13938
13939 ret = read_hfi1_efi_var(dd, "description", &size,
13940 (void **)&dd->boardname);
13941 if (ret) {
845f876d 13942 dd_dev_info(dd, "Board description not found\n");
5d9157aa
DL		 13943 /* use generic description */
13944 dd->boardname = kstrdup(generic, GFP_KERNEL);
13945 if (!dd->boardname)
13946 return -ENOMEM;
13947 }
13948 return 0;
13949}
13950
77241056 13951/**
7c03ed85 13952 * Allocate and initialize the device structure for the hfi.
77241056
MM		 13953 * @dev: the pci_dev for hfi1_ib device
13954 * @ent: pci_device_id struct for this dev
13955 *
13956 * Also allocates, initializes, and returns the devdata struct for this
13957 * device instance
13958 *
13959 * This is global, and is called directly at init to set up the
13960 * chip-specific function pointers for later use.
13961 */
13962struct hfi1_devdata *hfi1_init_dd(struct pci_dev *pdev,
13963 const struct pci_device_id *ent)
13964{
13965 struct hfi1_devdata *dd;
13966 struct hfi1_pportdata *ppd;
13967 u64 reg;
13968 int i, ret;
13969 static const char * const inames[] = { /* implementation names */
13970 "RTL silicon",
13971 "RTL VCS simulation",
13972 "RTL FPGA emulation",
13973 "Functional simulator"
13974 };
13975
13976 dd = hfi1_alloc_devdata(pdev,
13977 NUM_IB_PORTS * sizeof(struct hfi1_pportdata));
13978 if (IS_ERR(dd))
13979 goto bail;
13980 ppd = dd->pport;
13981 for (i = 0; i < dd->num_pports; i++, ppd++) {
13982 int vl;
13983 /* init common fields */
13984 hfi1_init_pportdata(pdev, ppd, dd, 0, 1);
13985 /* DC supports 4 link widths */
13986 ppd->link_width_supported =
13987 OPA_LINK_WIDTH_1X | OPA_LINK_WIDTH_2X |
13988 OPA_LINK_WIDTH_3X | OPA_LINK_WIDTH_4X;
13989 ppd->link_width_downgrade_supported =
13990 ppd->link_width_supported;
13991 /* start out enabling only 4X */
13992 ppd->link_width_enabled = OPA_LINK_WIDTH_4X;
13993 ppd->link_width_downgrade_enabled =
13994 ppd->link_width_downgrade_supported;
13995 /* link width active is 0 when link is down */
13996 /* link width downgrade active is 0 when link is down */
13997
13998 if (num_vls < HFI1_MIN_VLS_SUPPORTED
13999 || num_vls > HFI1_MAX_VLS_SUPPORTED) {
14000 hfi1_early_err(&pdev->dev,
14001 "Invalid num_vls %u, using %u VLs\n",
14002 num_vls, HFI1_MAX_VLS_SUPPORTED);
14003 num_vls = HFI1_MAX_VLS_SUPPORTED;
14004 }
14005 ppd->vls_supported = num_vls;
14006 ppd->vls_operational = ppd->vls_supported;
8a4d3444 14007 ppd->actual_vls_operational = ppd->vls_supported;
77241056
MM		 14008 /* Set the default MTU. */
14009 for (vl = 0; vl < num_vls; vl++)
14010 dd->vld[vl].mtu = hfi1_max_mtu;
14011 dd->vld[15].mtu = MAX_MAD_PACKET;
14012 /*
14013 * Set the initial values to reasonable default, will be set
14014 * for real when link is up.
14015 */
14016 ppd->lstate = IB_PORT_DOWN;
14017 ppd->overrun_threshold = 0x4;
14018 ppd->phy_error_threshold = 0xf;
14019 ppd->port_crc_mode_enabled = link_crc_mask;
14020 /* initialize supported LTP CRC mode */
14021 ppd->port_ltp_crc_mode = cap_to_port_ltp(link_crc_mask) << 8;
14022 /* initialize enabled LTP CRC mode */
14023 ppd->port_ltp_crc_mode |= cap_to_port_ltp(link_crc_mask) << 4;
14024 /* start in offline */
14025 ppd->host_link_state = HLS_DN_OFFLINE;
14026 init_vl_arb_caches(ppd);
f45c8dc8 14027 ppd->last_pstate = 0xff; /* invalid value */
77241056
MM		 14028 }
14029
14030 dd->link_default = HLS_DN_POLL;
14031
14032 /*
14033 * Do remaining PCIe setup and save PCIe values in dd.
14034 * Any error printing is already done by the init code.
14035 * On return, we have the chip mapped.
14036 */
14037 ret = hfi1_pcie_ddinit(dd, pdev, ent);
14038 if (ret < 0)
14039 goto bail_free;
14040
14041 /* verify that reads actually work, save revision for reset check */
14042 dd->revision = read_csr(dd, CCE_REVISION);
14043 if (dd->revision == ~(u64)0) {
14044 dd_dev_err(dd, "cannot read chip CSRs\n");
14045 ret = -EINVAL;
14046 goto bail_cleanup;
14047 }
14048 dd->majrev = (dd->revision >> CCE_REVISION_CHIP_REV_MAJOR_SHIFT)
14049 & CCE_REVISION_CHIP_REV_MAJOR_MASK;
14050 dd->minrev = (dd->revision >> CCE_REVISION_CHIP_REV_MINOR_SHIFT)
14051 & CCE_REVISION_CHIP_REV_MINOR_MASK;
14052
14053 /* obtain the hardware ID - NOT related to unit, which is a
14054 software enumeration */
14055 reg = read_csr(dd, CCE_REVISION2);
14056 dd->hfi1_id = (reg >> CCE_REVISION2_HFI_ID_SHIFT)
14057 & CCE_REVISION2_HFI_ID_MASK;
14058 /* the variable size will remove unwanted bits */
14059 dd->icode = reg >> CCE_REVISION2_IMPL_CODE_SHIFT;
14060 dd->irev = reg >> CCE_REVISION2_IMPL_REVISION_SHIFT;
14061 dd_dev_info(dd, "Implementation: %s, revision 0x%x\n",
14062 dd->icode < ARRAY_SIZE(inames) ? inames[dd->icode] : "unknown",
14063 (int)dd->irev);
14064
14065 /* speeds the hardware can support */
14066 dd->pport->link_speed_supported = OPA_LINK_SPEED_25G;
14067 /* speeds allowed to run at */
14068 dd->pport->link_speed_enabled = dd->pport->link_speed_supported;
14069 /* give a reasonable active value, will be set on link up */
14070 dd->pport->link_speed_active = OPA_LINK_SPEED_25G;
14071
14072 dd->chip_rcv_contexts = read_csr(dd, RCV_CONTEXTS);
14073 dd->chip_send_contexts = read_csr(dd, SEND_CONTEXTS);
14074 dd->chip_sdma_engines = read_csr(dd, SEND_DMA_ENGINES);
14075 dd->chip_pio_mem_size = read_csr(dd, SEND_PIO_MEM_SIZE);
14076 dd->chip_sdma_mem_size = read_csr(dd, SEND_DMA_MEM_SIZE);
14077 /* fix up link widths for emulation _p */
14078 ppd = dd->pport;
14079 if (dd->icode == ICODE_FPGA_EMULATION && is_emulator_p(dd)) {
14080 ppd->link_width_supported =
14081 ppd->link_width_enabled =
14082 ppd->link_width_downgrade_supported =
14083 ppd->link_width_downgrade_enabled =
14084 OPA_LINK_WIDTH_1X;
14085 }
14086 /* insure num_vls isn't larger than number of sdma engines */
14087 if (HFI1_CAP_IS_KSET(SDMA) && num_vls > dd->chip_sdma_engines) {
14088 dd_dev_err(dd, "num_vls %u too large, using %u VLs\n",
11a5909b
DL		 14089 num_vls, dd->chip_sdma_engines);
14090 num_vls = dd->chip_sdma_engines;
14091 ppd->vls_supported = dd->chip_sdma_engines;
8a4d3444 14092 ppd->vls_operational = ppd->vls_supported;
77241056
MM		 14093 }
14094
14095 /*
14096 * Convert the ns parameter to the 64 * cclocks used in the CSR.
14097 * Limit the max if larger than the field holds. If timeout is
14098 * non-zero, then the calculated field will be at least 1.
14099 *
14100 * Must be after icode is set up - the cclock rate depends
14101 * on knowing the hardware being used.
14102 */
14103 dd->rcv_intr_timeout_csr = ns_to_cclock(dd, rcv_intr_timeout) / 64;
14104 if (dd->rcv_intr_timeout_csr >
14105 RCV_AVAIL_TIME_OUT_TIME_OUT_RELOAD_MASK)
14106 dd->rcv_intr_timeout_csr =
14107 RCV_AVAIL_TIME_OUT_TIME_OUT_RELOAD_MASK;
14108 else if (dd->rcv_intr_timeout_csr == 0 && rcv_intr_timeout)
14109 dd->rcv_intr_timeout_csr = 1;
14110
7c03ed85
EH		 14111 /* needs to be done before we look for the peer device */
14112 read_guid(dd);
14113
14114 /* should this device init the ASIC block? */
14115 asic_should_init(dd);
14116
77241056
MM		 14117 /* obtain chip sizes, reset chip CSRs */
14118 init_chip(dd);
14119
14120 /* read in the PCIe link speed information */
14121 ret = pcie_speeds(dd);
14122 if (ret)
14123 goto bail_cleanup;
14124
c3838b39
EH		 14125 /* Needs to be called before hfi1_firmware_init */
14126 get_platform_config(dd);
14127
77241056
MM		 14128 /* read in firmware */
14129 ret = hfi1_firmware_init(dd);
14130 if (ret)
14131 goto bail_cleanup;
14132
14133 /*
14134 * In general, the PCIe Gen3 transition must occur after the
14135 * chip has been idled (so it won't initiate any PCIe transactions
14136 * e.g. an interrupt) and before the driver changes any registers
14137 * (the transition will reset the registers).
14138 *
14139 * In particular, place this call after:
14140 * - init_chip() - the chip will not initiate any PCIe transactions
14141 * - pcie_speeds() - reads the current link speed
14142 * - hfi1_firmware_init() - the needed firmware is ready to be
14143 * downloaded
14144 */
14145 ret = do_pcie_gen3_transition(dd);
14146 if (ret)
14147 goto bail_cleanup;
14148
14149 /* start setting dd values and adjusting CSRs */
14150 init_early_variables(dd);
14151
14152 parse_platform_config(dd);
14153
5d9157aa
DL		 14154 ret = obtain_boardname(dd);
14155 if (ret)
77241056 14156 goto bail_cleanup;
77241056
MM		 14157
14158 snprintf(dd->boardversion, BOARD_VERS_MAX,
5d9157aa 14159 "ChipABI %u.%u, ChipRev %u.%u, SW Compat %llu\n",
77241056 14160 HFI1_CHIP_VERS_MAJ, HFI1_CHIP_VERS_MIN,
77241056
MM		 14161 (u32)dd->majrev,
14162 (u32)dd->minrev,
14163 (dd->revision >> CCE_REVISION_SW_SHIFT)
14164 & CCE_REVISION_SW_MASK);
14165
14166 ret = set_up_context_variables(dd);
14167 if (ret)
14168 goto bail_cleanup;
14169
14170 /* set initial RXE CSRs */
14171 init_rxe(dd);
14172 /* set initial TXE CSRs */
14173 init_txe(dd);
14174 /* set initial non-RXE, non-TXE CSRs */
14175 init_other(dd);
14176 /* set up KDETH QP prefix in both RX and TX CSRs */
14177 init_kdeth_qp(dd);
14178
957558c9
MH		 14179 ret = hfi1_dev_affinity_init(dd);
14180 if (ret)
14181 goto bail_cleanup;
14182
77241056
MM		 14183 /* send contexts must be set up before receive contexts */
14184 ret = init_send_contexts(dd);
14185 if (ret)
14186 goto bail_cleanup;
14187
14188 ret = hfi1_create_ctxts(dd);
14189 if (ret)
14190 goto bail_cleanup;
14191
14192 dd->rcvhdrsize = DEFAULT_RCVHDRSIZE;
14193 /*
14194 * rcd[0] is guaranteed to be valid by this point. Also, all
14195 * context are using the same value, as per the module parameter.
14196 */
14197 dd->rhf_offset = dd->rcd[0]->rcvhdrqentsize - sizeof(u64) / sizeof(u32);
14198
14199 ret = init_pervl_scs(dd);
14200 if (ret)
14201 goto bail_cleanup;
14202
14203 /* sdma init */
14204 for (i = 0; i < dd->num_pports; ++i) {
14205 ret = sdma_init(dd, i);
14206 if (ret)
14207 goto bail_cleanup;
14208 }
14209
14210 /* use contexts created by hfi1_create_ctxts */
14211 ret = set_up_interrupts(dd);
14212 if (ret)
14213 goto bail_cleanup;
14214
14215 /* set up LCB access - must be after set_up_interrupts() */
14216 init_lcb_access(dd);
14217
14218 snprintf(dd->serial, SERIAL_MAX, "0x%08llx\n",
14219 dd->base_guid & 0xFFFFFF);
14220
14221 dd->oui1 = dd->base_guid >> 56 & 0xFF;
14222 dd->oui2 = dd->base_guid >> 48 & 0xFF;
14223 dd->oui3 = dd->base_guid >> 40 & 0xFF;
14224
14225 ret = load_firmware(dd); /* asymmetric with dispose_firmware() */
14226 if (ret)
14227 goto bail_clear_intr;
14228 check_fabric_firmware_versions(dd);
14229
14230 thermal_init(dd);
14231
14232 ret = init_cntrs(dd);
14233 if (ret)
14234 goto bail_clear_intr;
14235
14236 ret = init_rcverr(dd);
14237 if (ret)
14238 goto bail_free_cntrs;
14239
14240 ret = eprom_init(dd);
14241 if (ret)
14242 goto bail_free_rcverr;
14243
14244 goto bail;
14245
14246bail_free_rcverr:
14247 free_rcverr(dd);
14248bail_free_cntrs:
14249 free_cntrs(dd);
14250bail_clear_intr:
14251 clean_up_interrupts(dd);
14252bail_cleanup:
14253 hfi1_pcie_ddcleanup(dd);
14254bail_free:
14255 hfi1_free_devdata(dd);
14256 dd = ERR_PTR(ret);
14257bail:
14258 return dd;
14259}
14260
14261static u16 delay_cycles(struct hfi1_pportdata *ppd, u32 desired_egress_rate,
14262 u32 dw_len)
14263{
14264 u32 delta_cycles;
14265 u32 current_egress_rate = ppd->current_egress_rate;
14266 /* rates here are in units of 10^6 bits/sec */
14267
14268 if (desired_egress_rate == -1)
14269 return 0; /* shouldn't happen */
14270
14271 if (desired_egress_rate >= current_egress_rate)
14272 return 0; /* we can't help go faster, only slower */
14273
14274 delta_cycles = egress_cycles(dw_len * 4, desired_egress_rate) -
14275 egress_cycles(dw_len * 4, current_egress_rate);
14276
14277 return (u16)delta_cycles;
14278}
14279
77241056
MM		 14280/**
14281 * create_pbc - build a pbc for transmission
14282 * @flags: special case flags or-ed in built pbc
14283 * @srate: static rate
14284 * @vl: vl
14285 * @dwlen: dword length (header words + data words + pbc words)
14286 *
14287 * Create a PBC with the given flags, rate, VL, and length.
14288 *
14289 * NOTE: The PBC created will not insert any HCRC - all callers but one are
14290 * for verbs, which does not use this PSM feature. The lone other caller
14291 * is for the diagnostic interface which calls this if the user does not
14292 * supply their own PBC.
14293 */
14294u64 create_pbc(struct hfi1_pportdata *ppd, u64 flags, int srate_mbs, u32 vl,
14295 u32 dw_len)
14296{
14297 u64 pbc, delay = 0;
14298
14299 if (unlikely(srate_mbs))
14300 delay = delay_cycles(ppd, srate_mbs, dw_len);
14301
14302 pbc = flags
14303 | (delay << PBC_STATIC_RATE_CONTROL_COUNT_SHIFT)
14304 | ((u64)PBC_IHCRC_NONE << PBC_INSERT_HCRC_SHIFT)
14305 | (vl & PBC_VL_MASK) << PBC_VL_SHIFT
14306 | (dw_len & PBC_LENGTH_DWS_MASK)
14307 << PBC_LENGTH_DWS_SHIFT;
14308
14309 return pbc;
14310}
14311
14312#define SBUS_THERMAL 0x4f
14313#define SBUS_THERM_MONITOR_MODE 0x1
14314
14315#define THERM_FAILURE(dev, ret, reason) \
14316 dd_dev_err((dd), \
14317 "Thermal sensor initialization failed: %s (%d)\n", \
14318 (reason), (ret))
14319
14320/*
14321 * Initialize the Avago Thermal sensor.
14322 *
14323 * After initialization, enable polling of thermal sensor through
14324 * SBus interface. In order for this to work, the SBus Master
14325 * firmware has to be loaded due to the fact that the HW polling
14326 * logic uses SBus interrupts, which are not supported with
14327 * default firmware. Otherwise, no data will be returned through
14328 * the ASIC_STS_THERM CSR.
14329 */
14330static int thermal_init(struct hfi1_devdata *dd)
14331{
14332 int ret = 0;
14333
14334 if (dd->icode != ICODE_RTL_SILICON ||
14335 !(dd->flags & HFI1_DO_INIT_ASIC))
14336 return ret;
14337
14338 acquire_hw_mutex(dd);
14339 dd_dev_info(dd, "Initializing thermal sensor\n");
4ef98989
JAQ		 14340 /* Disable polling of thermal readings */
14341 write_csr(dd, ASIC_CFG_THERM_POLL_EN, 0x0);
14342 msleep(100);
77241056
MM		 14343 /* Thermal Sensor Initialization */
14344 /* Step 1: Reset the Thermal SBus Receiver */
14345 ret = sbus_request_slow(dd, SBUS_THERMAL, 0x0,
14346 RESET_SBUS_RECEIVER, 0);
14347 if (ret) {
14348 THERM_FAILURE(dd, ret, "Bus Reset");
14349 goto done;
14350 }
14351 /* Step 2: Set Reset bit in Thermal block */
14352 ret = sbus_request_slow(dd, SBUS_THERMAL, 0x0,
14353 WRITE_SBUS_RECEIVER, 0x1);
14354 if (ret) {
14355 THERM_FAILURE(dd, ret, "Therm Block Reset");
14356 goto done;
14357 }
14358 /* Step 3: Write clock divider value (100MHz -> 2MHz) */
14359 ret = sbus_request_slow(dd, SBUS_THERMAL, 0x1,
14360 WRITE_SBUS_RECEIVER, 0x32);
14361 if (ret) {
14362 THERM_FAILURE(dd, ret, "Write Clock Div");
14363 goto done;
14364 }
14365 /* Step 4: Select temperature mode */
14366 ret = sbus_request_slow(dd, SBUS_THERMAL, 0x3,
14367 WRITE_SBUS_RECEIVER,
14368 SBUS_THERM_MONITOR_MODE);
14369 if (ret) {
14370 THERM_FAILURE(dd, ret, "Write Mode Sel");
14371 goto done;
14372 }
14373 /* Step 5: De-assert block reset and start conversion */
14374 ret = sbus_request_slow(dd, SBUS_THERMAL, 0x0,
14375 WRITE_SBUS_RECEIVER, 0x2);
14376 if (ret) {
14377 THERM_FAILURE(dd, ret, "Write Reset Deassert");
14378 goto done;
14379 }
14380 /* Step 5.1: Wait for first conversion (21.5ms per spec) */
14381 msleep(22);
14382
14383 /* Enable polling of thermal readings */
14384 write_csr(dd, ASIC_CFG_THERM_POLL_EN, 0x1);
14385done:
14386 release_hw_mutex(dd);
14387 return ret;
14388}
14389
14390static void handle_temp_err(struct hfi1_devdata *dd)
14391{
14392 struct hfi1_pportdata *ppd = &dd->pport[0];
14393 /*
14394 * Thermal Critical Interrupt
14395 * Put the device into forced freeze mode, take link down to
14396 * offline, and put DC into reset.
14397 */
14398 dd_dev_emerg(dd,
14399 "Critical temperature reached! Forcing device into freeze mode!\n");
14400 dd->flags |= HFI1_FORCED_FREEZE;
8638b77f 14401 start_freeze_handling(ppd, FREEZE_SELF | FREEZE_ABORT);
77241056
MM		 14402 /*
14403 * Shut DC down as much and as quickly as possible.
14404 *
14405 * Step 1: Take the link down to OFFLINE. This will cause the
14406 * 8051 to put the Serdes in reset. However, we don't want to
14407 * go through the entire link state machine since we want to
14408 * shutdown ASAP. Furthermore, this is not a graceful shutdown
14409 * but rather an attempt to save the chip.
14410 * Code below is almost the same as quiet_serdes() but avoids
14411 * all the extra work and the sleeps.
14412 */
14413 ppd->driver_link_ready = 0;
14414 ppd->link_enabled = 0;
14415 set_physical_link_state(dd, PLS_OFFLINE |
14416 (OPA_LINKDOWN_REASON_SMA_DISABLED << 8));
14417 /*
14418 * Step 2: Shutdown LCB and 8051
14419 * After shutdown, do not restore DC_CFG_RESET value.
14420 */
14421 dc_shutdown(dd);
14422}
Linux kernel - Deliverables
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